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1.1 root 1: ;; GCC machine description for Intel 80386.
2: ;; Copyright (C) 1988 Free Software Foundation, Inc.
3: ;; Mostly by William Schelter.
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 1, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21:
22: ;;- instruction definitions
23:
24: ;;- @@The original PO technology requires these to be ordered by speed,
25: ;;- @@ so that assigner will pick the fastest.
26:
27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28:
29: ;;- When naming insn's (operand 0 of define_insn) be careful about using
30: ;;- names from other targets machine descriptions.
31:
32: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
33: ;;- updates for most instructions.
34:
35: ;;- Operand classes for the register allocator:
36: ;;- 'a' for eax
37: ;;- 'd' for edx
38: ;;- 'c' for ecx
39: ;;- 'b' for ebx
40: ;;- 'f' for anything in FLOAT_REGS
41: ;;- 'r' any (non-floating-point) register
42: ;;- 'q' regs that allow byte operations (A, B, C and D)
43: ;;- 'A' A and D registers
44:
45: ;; the special asm out single letter directives following a '%' are:
46: ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of operands[1]
47: ;; 's' output a '*'
48: ;; 'w' If the operand is a REG, it uses the mode size to determine the
49: ;; printing of the reg
50:
51:
52: ;; Put tstsi first among test insns so it matches a CONST_INT operand.
53:
54: (define_insn "tstsi"
55: [(set (cc0)
56: (match_operand:SI 0 "general_operand" "rm"))]
57: ""
58: "*
59: {
60: operands[1] = const0_rtx;
61: if (REG_P (operands[0]))
62: return AS2 (test%L0,%0,%0);
63: return AS2 (cmp%L0,%1,%0);
64: }")
65:
66: (define_insn "tsthi"
67: [(set (cc0)
68: (match_operand:HI 0 "general_operand" "rm"))]
69: ""
70: "*
71: {
72: operands[1] = const0_rtx;
73: if (REG_P (operands[0]))
74: return AS2 (test%W0,%0,%0);
75: return AS2 (cmp%W0,%1,%0);
76: }")
77:
78: (define_insn "tstqi"
79: [(set (cc0)
80: (match_operand:QI 0 "general_operand" "qm"))]
81: ""
82: "*
83: {
84: operands[1] = const0_rtx;
85: if (REG_P (operands[0]))
86: return AS2 (test%B0,%0,%0);
87: return AS2 (cmp%B0,%1,%0);
88: }")
89:
90: (define_insn "tstsf"
91: [(set (cc0)
92: (match_operand:SF 0 "general_operand" "rm,f"))
1.1.1.3 ! root 93: (clobber (reg:SI 0))]
1.1 root 94: "TARGET_80387"
95: "*
96: {
97: rtx xops[1];
98: if (!FP_REG_P (operands[0]))
99: fp_push_sf (operands[0]);
100: /* fp_pop_level--; */
101: xops[0] = FP_TOP;
102: cc_status.flags |= CC_IN_80387;
103: if (FP_REG_P (operands[0]) && ! top_dead_p (insn))
104: output_asm_insn (\"ftst\;fnstsw %R0ax\;sahf\", xops);
105: else
106: output_asm_insn (\"ftst\;fstp %0(0)\;fnstsw %R0ax\;sahf\", xops);
107: RETCOM (testsf);
108: }")
109:
110: (define_insn "tstdf"
111: [(set (cc0)
112: (match_operand:DF 0 "general_operand" "rm,f"))
1.1.1.3 ! root 113: (clobber (reg:SI 0))
1.1 root 114: ]
115: "TARGET_80387"
116: "*
117: {
118: rtx xops[1];
119: if (!FP_REG_P (operands[0]))
120: fp_push_df (operands[0]);
121: /* fp_pop_level--; */
122: xops[0] = FP_TOP;
123: cc_status.flags |= CC_IN_80387;
124: if (FP_REG_P (operands[0]) && ! top_dead_p (insn))
125: output_asm_insn (\"ftst\;fnstsw %R0ax\;sahf\", xops);
126: else
127: output_asm_insn (\"ftst\;fstp %0(0)\;fnstsw %R0ax\;sahf\", xops);
128: RETCOM (testdf);
129: }")
130:
131: ;;- compare instructions
132:
133: ;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
134:
135: (define_insn "cmpsi"
136: [(set (cc0)
137: (compare (match_operand:SI 0 "general_operand" "mr,ri")
138: (match_operand:SI 1 "general_operand" "ri,mr")))]
139: ""
140: "*
141: {
142: if (REG_P (operands[1])
143: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
144: {
145: cc_status.flags |= CC_REVERSED;
146: return AS2 (cmp%L0,%0,%1);
147: }
148: return AS2 (cmp%L0,%1,%0);
149: }")
150:
151: (define_insn "cmphi"
152: [(set (cc0)
153: (compare (match_operand:HI 0 "general_operand" "mr,ri")
154: (match_operand:HI 1 "general_operand" "ri,mr")))]
155: ""
156: "*
157: {
158: if (REG_P (operands[1])
159: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
160: {
161: cc_status.flags |= CC_REVERSED;
162: return AS2 (cmp%W0,%0,%1);
163: }
164: return AS2 (cmp%W0,%1,%0);
165: }")
166:
167: (define_insn "cmpqi"
168: [(set (cc0)
169: (compare (match_operand:QI 0 "general_operand" "qn,mq")
170: (match_operand:QI 1 "general_operand" "qm,nq")))]
171: ""
172: "*
173: {
174: if (REG_P (operands[1])
175: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
176: {
177: cc_status.flags |= CC_REVERSED;
178: return AS2 (cmp%B0,%0,%1);
179: }
180: return AS2 (cmp%B0,%1,%0);
181: }")
182:
183: (define_insn "cmpdf"
184: [(set (cc0)
185: (compare (match_operand:DF 0 "general_operand" "m,f*r,m,f,r,!*r")
186: (match_operand:DF 1 "general_operand" "m,m,f*r,r,f,*r")))
187: (clobber (reg:SI 0))]
188: "TARGET_80387"
189: "*
190: {
191: if (FP_REG_P (operands[0]))
192: {
193: rtx tem = operands[1];
194: operands[1] = operands[0];
195: operands[0] = tem;
196: cc_status.flags |= CC_REVERSED;
197: }
198: if (! FP_REG_P (operands[1]))
199: output_movdf (FP_TOP, operands[1]);
200: output_movdf (FP_TOP, operands[0]);
201: /* fp_pop_level--;
202: fp_pop_level--; */
203: cc_status.flags |= CC_IN_80387;
204: return \"fcompp\;fnstsw %R0ax\;sahf\";
205: }")
206:
207: (define_insn "cmpsf"
208: [(set (cc0)
209: (compare (match_operand:SF 0 "general_operand" "m,f*r,m,f,r,!*r")
210: (match_operand:SF 1 "general_operand" "m,m,f*r,r,f,*r")))
211: (clobber (reg:SI 0))]
212: "TARGET_80387"
213: "*
214: {
215: if (FP_REG_P (operands[0]))
216: {
217: rtx tem = operands[1];
218: operands[1] = operands[0];
219: operands[0] = tem;
220: cc_status.flags |= CC_REVERSED;
221: }
222: if (! FP_REG_P (operands[1]))
223: output_movsf (FP_TOP, operands[1]);
224: output_movsf (FP_TOP, operands[0]);
225: /* fp_pop_level--;
226: fp_pop_level--; */
227: cc_status.flags |= CC_IN_80387;
228: return \"fcompp\;fnstsw %R0ax\;sahf\";
229: }")
230:
231: ;; logical compare
232: (define_insn ""
233: [(set (cc0)
234: (and:SI (match_operand:SI 0 "general_operand" "rm,ri")
235: (match_operand:SI 1 "general_operand" "ri,rm")))]
236: ""
237: "*
238: {
1.1.1.3 ! root 239: if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
1.1 root 240: return AS2 (test%L0,%1,%0);
241: return AS2 (test%L0,%0,%1);
242: }")
243:
244: (define_insn ""
245: [(set (cc0)
246: (and:HI (match_operand:HI 0 "general_operand" "rm,ri")
247: (match_operand:HI 1 "general_operand" "ri,rm")))]
248: ""
249: "*
250: {
1.1.1.3 ! root 251: if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
1.1 root 252: return AS2 (test%W0,%1,%0);
253: return AS2 (test%W0,%0,%1);
254: }")
255:
256: (define_insn ""
257: [(set (cc0)
258: (and:QI (match_operand:QI 0 "general_operand" "qm,qi")
259: (match_operand:QI 1 "general_operand" "qi,qm")))]
260: ""
261: "*
262: {
1.1.1.3 ! root 263: if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
1.1 root 264: return AS2 (test%B0,%1,%0);
265: return AS2 (test%B0,%0,%1);
266: }")
267:
268: ;; move instructions.
269: ;; There is one for each machine mode,
270: ;; and each is preceded by a corresponding push-insn pattern
271: ;; (since pushes are not general_operands on the 386).
272:
273: (define_insn ""
274: [(set (match_operand:SI 0 "push_operand" "=<")
275: (match_operand:SI 1 "general_operand" "g"))]
276: ""
277: "push%L0 %1")
278:
279: ;; General case of fullword move.
280: (define_insn "movsi"
281: [(set (match_operand:SI 0 "general_operand" "=g,r")
282: (match_operand:SI 1 "general_operand" "ri,m"))]
283: ""
284: "*
285: {
286: rtx link;
287: if (operands[1] == const0_rtx && REG_P (operands[0]))
288: return \"xor%L0 %0,%0\";
289: if (operands[1] == const1_rtx
290: && (link = find_reg_note (insn, REG_WAS_0, 0))
291: /* Make sure the insn that stored the 0 is still present. */
292: && ! XEXP (link, 0)->volatil
293: && GET_CODE (XEXP (link, 0)) != NOTE
294: /* Make sure cross jumping didn't happen here. */
295: && no_labels_between_p (XEXP (link, 0), insn))
296: /* Fastest way to change a 0 to a 1. */
297: return \"inc%L0 %0\";
298: return \"mov%L0 %1,%0\";
299: }")
300:
301: (define_insn ""
302: [(set (match_operand:HI 0 "push_operand" "=<")
303: (match_operand:HI 1 "general_operand" "g"))]
304: ""
305: "push%W0 %1")
306:
307: (define_insn "movhi"
308: [(set (match_operand:HI 0 "general_operand" "=g,r")
309: (match_operand:HI 1 "general_operand" "ri,m"))]
310: ""
311: "*
312: {
313: rtx link;
314: if (operands[1] == const0_rtx && REG_P (operands[0]))
315: return \"xor%W0 %0,%0\";
316: if (operands[1] == const1_rtx
317: && (link = find_reg_note (insn, REG_WAS_0, 0))
318: /* Make sure the insn that stored the 0 is still present. */
319: && ! XEXP (link, 0)->volatil
320: && GET_CODE (XEXP (link, 0)) != NOTE
321: /* Make sure cross jumping didn't happen here. */
322: && no_labels_between_p (XEXP (link, 0), insn))
323: /* Fastest way to change a 0 to a 1. */
324: return \"inc%W0 %0\";
325: return \"mov%W0 %1,%0\";
326: }")
327:
328: ;; emit_push_insn when it calls move_by_pieces
329: ;; requires an insn to "push a byte".
330: ;; But actually we use pushw, which has the effect of rounding
331: ;; the amount pushed up to a halfword.
332: (define_insn ""
333: [(set (match_operand:QI 0 "push_operand" "=<")
334: (match_operand:QI 1 "general_operand" "q"))]
335: ""
336: "*
337: {
338: operands[1] = gen_rtx (REG, HImode, REGNO (operands[1]));
339: return \"push%W0 %1\";
340: }")
341:
342: (define_insn "movqi"
343: [(set (match_operand:QI 0 "general_operand" "=q,*r,m")
344: (match_operand:QI 1 "general_operand" "*g,q,qi"))]
345: ""
346: "*
347: {
348: rtx link;
349: if (operands[1] == const0_rtx && REG_P (operands[0]))
350: return \"xor%B0 %0,%0\";
351: if (operands[1] == const1_rtx
352: && (link = find_reg_note (insn, REG_WAS_0, 0))
353: /* Make sure the insn that stored the 0 is still present. */
354: && ! XEXP (link, 0)->volatil
355: && GET_CODE (XEXP (link, 0)) != NOTE
356: /* Make sure cross jumping didn't happen here. */
357: && no_labels_between_p (XEXP (link, 0), insn))
358: /* Fastest way to change a 0 to a 1. */
359: return \"inc%B0 %0\";
360: /* If mov%B0 isn't allowed for one of these regs, use mov%W0. */
361: if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1]))
362: return (AS2 (mov%W0,%w1,%w0));
363: return (AS2 (mov%B0,%1,%0));
364: }")
365:
366: ; I suspect nothing can ever match this ???
367: ;(define_insn ""
368: ; [(set (match_operand:SF 0 "general_operand" "rm")
369: ; (match_operand:SF 1 "general_operand" "f"))
370: ; (clobber (reg:SF 8))]
371: ; ""
372: ; "*
373: ;{
374: ; output_asm_insn ("???", operands);
375: ; fpop_sf (operands[0]);
376: ; RETCOM (movsf_clobber);
377: ;}")
378:
379: (define_insn ""
380: [(set (match_operand:SF 0 "push_operand" "=<,<")
381: (match_operand:SF 1 "general_operand" "gF,f"))]
382: ""
383: "*
384: {
385: if (FP_REG_P (operands[1]))
386: {
387: rtx xops[3];
388: xops[0] = AT_SP (SFmode);
389: xops[1] = gen_rtx (CONST_INT, VOIDmode, 4);
390: xops[2] = stack_pointer_rtx;
391: /* fp_pop_level--; */
392: output_asm_insn (AS2 (sub%L0,%1,%2), xops);
1.1.1.2 root 393: if (top_dead_p (insn))
394: output_asm_insn (\"fstp%S0 %0\", xops);
395: else
396: output_asm_insn (\"fst%S0\", xops);
1.1 root 397: RET;
398: }
399: return \"push%L0 %1\";
400: }")
401:
402: (define_insn "movsf"
403: [(set (match_operand:SF 0 "general_operand" "=rf,rmf,!rm")
404: (match_operand:SF 1 "general_operand" "m,rf,F"))]
405: ""
406: "*
407: {
408: if (FP_REG_P (operands[1])
409: && !FP_REG_P (operands[0])
410: && !top_dead_p (insn))
411: fp_store_sf (operands[0]);
412: else
413: output_movsf (operands[0], operands[1]);
414: RETCOM (movsf);
415: }")
416:
417: ;;should change to handle the memory operands[1] without doing df push..
418: (define_insn ""
419: [(set (match_operand:DF 0 "push_operand" "=<,<")
420: (match_operand:DF 1 "general_operand" "gF,f"))]
421: ""
422: "*
423: {
424: if (FP_REG_P (operands[1]))
425: {
426: rtx xops[3];
427: xops[0] = AT_SP (DFmode);
428: xops[1] = gen_rtx (CONST_INT, VOIDmode, 8);
429: xops[2] = stack_pointer_rtx;
430: /* fp_pop_level--; */
431: output_asm_insn (AS2 (sub%L0,%1,%2), xops);
1.1.1.2 root 432: if (top_dead_p(insn))
433: output_asm_insn (\"fstp%Q0 %0\", xops);
434: else
435: output_asm_insn (\"fst%Q0 %0\", xops);
1.1 root 436: RETCOM (pushdf);
437: }
438: else
439: return output_move_double (operands);
440: }")
441:
442: (define_insn "movdf"
443: [(set (match_operand:DF 0 "general_operand" "=&rf,rmf,!rm")
444: (match_operand:DF 1 "general_operand" "m,fr,F"))]
445: ""
446: "*
447: {
448: if (FP_REG_P (operands[1])
449: && ! FP_REG_P (operands[0])
450: && ! top_dead_p (insn))
451: fp_store_df (operands[0]);
452: else
453: output_movdf (operands[0], operands[1]);
454: RETCOM (movdf);
455: }")
456:
457: (define_insn ""
458: [(set (match_operand:DI 0 "push_operand" "=<")
459: (match_operand:DI 1 "general_operand" "roiF"))]
460: ""
461: "*
462: {
463: return output_move_double (operands);
464: }")
465:
466: (define_insn "movdi"
467: [(set (match_operand:DI 0 "general_operand" "=&r,rm")
468: (match_operand:DI 1 "general_operand" "m,riF"))]
469: ""
470: "*
471: {
472: return output_move_double (operands);
473: }")
474:
475: ;; These go after the move instructions
476: ;; because the move instructions are better (require no spilling)
477: ;; when they can apply. But these go before the add and subtract insns
478: ;; because it is often shorter to use these when both apply.
479:
480: ;Lennart Augustsson <[email protected]>
481: ;says this pattern just makes slower code:
482: ; pushl %ebp
483: ; addl $-80,(%esp)
484: ;instead of
485: ; leal -80(%ebp),%eax
486: ; pushl %eax
487: ;
488: ;(define_insn ""
489: ; [(set (match_operand:SI 0 "push_operand" "=<")
490: ; (plus:SI (match_operand:SI 1 "general_operand" "%r")
491: ; (match_operand:SI 2 "general_operand" "ri")))]
492: ; ""
493: ; "*
494: ;{
495: ; rtx xops[4];
496: ; xops[0] = operands[0];
497: ; xops[1] = operands[1];
498: ; xops[2] = operands[2];
499: ; xops[3] = gen_rtx (MEM, SImode, stack_pointer_rtx);
500: ; output_asm_insn (\"push%z1 %1\", xops);
501: ; output_asm_insn (AS2 (add%z3,%2,%3), xops);
502: ; RET;
503: ;}")
504:
505: (define_insn ""
506: [(set (match_operand:SI 0 "general_operand" "=g")
507: (plus:SI (match_operand:SI 1 "general_operand" "0")
508: (const_int 1)))]
509: ""
510: "inc%L0 %0")
511:
512: (define_insn ""
513: [(set (match_operand:SI 0 "general_operand" "=g")
514: (plus:SI (match_operand:SI 1 "general_operand" "0")
515: (const_int -1)))]
516: ""
517: "dec%L0 %0")
518:
519: (define_insn ""
520: [(set (match_operand:SI 0 "general_operand" "=g")
521: (minus:SI (match_operand:SI 1 "general_operand" "0")
522: (const_int 1)))]
523: ""
524: "dec%L0 %0")
525:
526: (define_insn ""
527: [(set (match_operand:SI 0 "register_operand" "=r")
528: (match_operand:QI 1 "address_operand" "p"))]
529: ""
530: "*
531: {
532: CC_STATUS_INIT;
533: /* Adding a constant to a register is faster with an add. */
534: if (GET_CODE (operands[1]) == PLUS
535: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
536: && rtx_equal_p (operands[0], XEXP (operands[1], 0)))
537: {
538: operands[1] = XEXP (operands[1], 1);
539: return AS2 (add%L0,%1,%0);
540: }
541: return \"lea%L0 %a1,%0\";
542: }")
543:
544: ;;- conversion instructions
545: ;;- NONE
546:
547: ;;- truncation instructions
548: (define_insn "truncsiqi2"
1.1.1.3 ! root 549: [(set (match_operand:QI 0 "general_operand" "=q,m")
1.1 root 550: (truncate:QI
1.1.1.3 ! root 551: (match_operand:SI 1 "general_operand" "qim,qn")))]
1.1 root 552: ""
1.1.1.3 ! root 553: "*
! 554: {
! 555: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
! 556: return \"mov%L0 %1,%k0\";
! 557: return \"mov%B0 %b1,%0\";
! 558: }")
1.1 root 559:
560: (define_insn "trunchiqi2"
1.1.1.3 ! root 561: [(set (match_operand:QI 0 "general_operand" "=q,m")
1.1 root 562: (truncate:QI
1.1.1.3 ! root 563: (match_operand:HI 1 "general_operand" "qim,qn")))]
1.1 root 564: ""
1.1.1.3 ! root 565: "*
! 566: {
! 567: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
! 568: return \"mov%W0 %1,%w0\";
! 569: return \"mov%B0 %b1,%0\";
! 570: }")
1.1 root 571:
572: (define_insn "truncsihi2"
1.1.1.3 ! root 573: [(set (match_operand:HI 0 "general_operand" "=r,m")
1.1 root 574: (truncate:HI
1.1.1.3 ! root 575: (match_operand:SI 1 "general_operand" "rim,rn")))]
1.1 root 576: ""
1.1.1.3 ! root 577: "*
! 578: {
! 579: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
! 580: return \"mov%L0 %1,%k0\";
! 581: return \"mov%W0 %w1,%0\";
! 582: }")
1.1 root 583:
584: ;;- zero extension instructions
585: ;; Note that the one starting from HImode comes before those for QImode
586: ;; so that a constant operand will match HImode, not QImode.
587:
588: (define_insn "zero_extendhisi2"
589: [(set (match_operand:SI 0 "general_operand" "=r")
590: (zero_extend:SI
591: (match_operand:HI 1 "general_operand" "rm")))]
592: ""
593: "movz%W0%L0 %1,%0")
594:
595: (define_insn "zero_extendqihi2"
596: [(set (match_operand:HI 0 "general_operand" "=r")
597: (zero_extend:HI
598: (match_operand:QI 1 "general_operand" "qm")))]
599: ""
600: "movz%B0%W0 %1,%0")
601:
602: (define_insn "zero_extendqisi2"
603: [(set (match_operand:SI 0 "general_operand" "=r")
604: (zero_extend:SI
605: (match_operand:QI 1 "general_operand" "qm")))]
606: ""
607: "movz%B0%L0 %1,%0")
608:
609: ;;- sign extension instructions
610: ;; Note that the one starting from HImode comes before those for QImode
611: ;; so that a constant operand will match HImode, not QImode.
612:
613: /*
614: (define_insn "extendsidi2"
615: [(set (match_operand:DI 0 "general_operand" "=a")
616: (sign_extend:DI
617: (match_operand:SI 1 "general_operand" "a")))]
618: ""
619: "clq")
620: */
621:
1.1.1.3 ! root 622: ;; Note that the i386 programmers' manual says that the opcodes
! 623: ;; are named movsx..., but the assembler on Unix does not accept that.
! 624: ;; We use what the Unix assembler expects.
! 625:
1.1 root 626: (define_insn "extendhisi2"
627: [(set (match_operand:SI 0 "general_operand" "=r")
628: (sign_extend:SI
629: (match_operand:HI 1 "general_operand" "rm")))]
630: ""
631: "movs%W0%L0 %1,%0")
632:
633: (define_insn "extendqihi2"
634: [(set (match_operand:HI 0 "general_operand" "=r")
635: (sign_extend:HI
636: (match_operand:QI 1 "general_operand" "qm")))]
637: ""
638: "movs%B0%W0 %1,%0")
639:
640: (define_insn "extendqisi2"
641: [(set (match_operand:SI 0 "general_operand" "=r")
642: (sign_extend:SI
643: (match_operand:QI 1 "general_operand" "qm")))]
644: ""
645: "movs%B0%L0 %1,%0"
646: )
647:
648: ;; Conversions between float and double.
649:
650: (define_insn "extendsfdf2"
651: [(set (match_operand:DF 0 "general_operand" "=fm,f,fm,fm")
652: (float_extend:DF
653: (match_operand:SF 1 "general_operand" "m,0,f,!*r")))]
654: "TARGET_80387"
655: "*
656: {
657: if (FP_REG_P (operands[0]))
658: {
659: output_movsf (operands[0], operands[1]);
660: RET;
661: }
662: if (FP_REG_P (operands[1]))
663: {
664: if (top_dead_p (insn))
665: fp_pop_df (operands[0]);
666: else
667: fp_store_df (operands[0]);
668: RET;
669: }
670: output_movsf (FP_TOP, operands[1]);
671: fp_pop_df (operands[0]);
672: RETCOM (extendsfdf2);
673: }")
674:
675: ;; This cannot output into an f-reg because there is no way to be
676: ;; sure of truncating in that case.
677: (define_insn "truncdfsf2"
678: [(set (match_operand:SF 0 "general_operand" "=m,!*r")
679: (float_truncate:SF
680: (match_operand:DF 1 "general_operand" "f,f")))]
681: "TARGET_80387"
682: "*
683: {
684: if (top_dead_p (insn))
685: fp_pop_sf (operands[0]);
686: else
687: fp_store_sf (operands[0]);
688: RETCOM (truncdfsf2);
689: }")
690:
691: ;; Conversion between fixed point and floating point.
692: ;; Note that among the fix-to-float insns
693: ;; the ones that start with SImode come first.
694: ;; That is so that an operand that is a CONST_INT
695: ;; (and therefore lacks a specific machine mode).
696: ;; will be recognized as SImode (which is always valid)
697: ;; rather than as QImode or HImode. The 80387 would not know
698: ;; what to do with the smaller sizes anyway. (I think).
699:
700: (define_insn "floatsisf2"
701: [(set (match_operand:SF 0 "general_operand" "=fm,fm")
702: (float:SF (match_operand:SI 1 "general_operand" "m,!*r")))]
703: "TARGET_80387"
704: "*
705: {
706: /* fp_pop_level++; */
707:
708: if (GET_CODE (operands[1]) != MEM)
709: {
710: rtx xops[2];
711: output_asm_insn (\"push%L0 %1\", operands);
712: operands[1] = AT_SP (SImode);
713: output_asm_insn (\"fild%L0 %1\", operands);
714: xops[0] = stack_pointer_rtx;
715: xops[1] = gen_rtx (CONST_INT, VOIDmode, 4);
716: output_asm_insn (AS2 (add%L0,%1,%0), xops);
717: }
718: else
719: output_asm_insn (\"fild%L0 %1\", operands);
720:
721: if (! FP_REG_P (operands[0]))
722: {
723: /* fp_pop_level--; */
724: return \"fstp%S0 %0\";
725: }
726: RET;
727: }")
728:
729: (define_insn "floatsidf2"
730: [(set (match_operand:DF 0 "general_operand" "=fm,fm")
731: (float:DF (match_operand:SI 1 "general_operand" "m,!*r")))]
732: "TARGET_80387"
733: "*
734: {
735: /* fp_pop_level++; */
736: if (GET_CODE (operands[1]) != MEM)
737: {
738: rtx xops[2];
739: output_asm_insn (\"push%L0 %1\", operands);
740: operands[1] = AT_SP (SImode);
741: output_asm_insn (\"fild%L0 %1\", operands);
742: xops[0] = stack_pointer_rtx;
743: xops[1] = gen_rtx (CONST_INT, VOIDmode, 4);
744: output_asm_insn (AS2 (add%L0,%1,%0), xops);
745: }
746: else
747: output_asm_insn (\"fild%L0 %1\", operands);
748: if (! FP_REG_P (operands[0]))
749: {
750: /* fp_pop_level--; */
751: return \"fstp%Q0 %0\";
752: }
753: RET;
754: }")
755:
756: ;; Convert a float to a float whose value is an integer.
757: ;; This is the first stage of converting it to an integer type.
758:
759: ;; On the 387 truncating doub to an short integer shor can be performed:
760:
761: ; fstcw -4(%esp) ;save cw
762: ; movw -4(%esp),%ax
763: ; orw $0x0c00,%ax ;set rounding to chop towards zero
764: ; movw %ax,-2(%esp) ;
765: ; fldcw -2(%esp) ;
766: ; fldl doubl
767: ; fistpl -12(%esp) ;store the round value
768: ; fldcw -4(%esp) ;restore cw
769: ; movl -12(%esp),%eax
770: ; movw %ax,shor ; move the result into shor.
771:
772: ;; but it is probably better to have a call, rather than waste this
773: ;; space. The last instruction would have been a movl if were
774: ;; going to an int instead of a short.
775: ;; For the moment we will go with the soft float for these.
776:
777: /* These are incorrect since they don't set the rounding bits of CW flag.
778: The proper way to do that is to make the function prologue save the CW
779: and also construct the alternate CW value needed for these insns.
780: Then these insns can output two fldcw's, referring to fixed places in
781: the stack frame.
782:
783: ;; Convert a float whose value is an integer
784: ;; to an actual integer. Second stage of converting float to integer type.
785:
786: (define_insn "fix_truncsfqi2"
787: [(set (match_operand:QI 0 "general_operand" "=m,?*q")
788: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "f,f"))))]
789: "TARGET_80387"
790: "*
791: {
792: fp_pop_int (operands[0]);
793: RET;
794: }")
795:
796: (define_insn "fix_truncsfhi2"
797: [(set (match_operand:HI 0 "general_operand" "=m,?*r")
798: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "f,f"))))]
799: "TARGET_80387"
800: "*
801: {
802: fp_pop_int (operands[0]);
803: RET;
804: }")
805:
806: (define_insn "fix_truncsfsi2"
807: [(set (match_operand:SI 0 "general_operand" "=m,?*r")
808: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "f,f"))))]
809: "TARGET_80387"
810: "*
811: {
812: fp_pop_int (operands[0]);
813: RET;
814: }")
815:
816: (define_insn "fix_truncdfqi2"
817: [(set (match_operand:QI 0 "general_operand" "=m,?*q")
818: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "f,f"))))]
819:
820: "TARGET_80387"
821: "*
822: {
823: fp_pop_int (operands[0]);
824: RET;
825: }")
826:
827:
828: (define_insn "fix_truncdfhi2"
829: [(set (match_operand:HI 0 "general_operand" "=m,?*r")
830: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "f,f"))))]
831: "TARGET_80387"
832: "*
833: {
834: fp_pop_int (operands[0]);
835: RET;
836: }")
837:
838:
839: (define_insn "fix_truncdfsi2"
840: [(set (match_operand:SI 0 "general_operand" "=m,?*r")
841: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "f,f"))))]
842: "TARGET_80387"
843: "*
844: {
845: fp_pop_int (operands[0]);
846: RET;
847: }")
848: */
849:
850:
851: ;;- add instructions
852: ;;moved incl to above leal
853:
854: (define_insn "addsi3"
855: [(set (match_operand:SI 0 "general_operand" "=rm,r")
856: (plus:SI (match_operand:SI 1 "general_operand" "%0,0")
857: (match_operand:SI 2 "general_operand" "ri,rm")))]
858: ""
859: "add%L0 %2,%0")
860:
861: (define_insn ""
862: [(set (match_operand:HI 0 "general_operand" "=g")
863: (plus:HI (match_operand:HI 1 "general_operand" "0")
864: (const_int 1)))]
865: ""
866: "inc%W0 %0")
867:
868: (define_insn "addhi3"
869: [(set (match_operand:HI 0 "general_operand" "=rm,r")
870: (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
871: (match_operand:HI 2 "general_operand" "ri,rm")))]
872: ""
873: "add%W0 %2,%0")
874:
875: (define_insn ""
876: [(set (match_operand:QI 0 "general_operand" "=qm")
877: (plus:QI (match_operand:QI 1 "general_operand" "0")
878: (const_int 1)))]
879: ""
880: "inc%B0 %0")
881:
882: (define_insn "addqi3"
883: [(set (match_operand:QI 0 "general_operand" "=m,q")
884: (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
885: (match_operand:QI 2 "general_operand" "qn,qmn")))]
886: ""
887: "add%B0 %2,%0")
888:
889: ;;had "fmF,m"
890:
891: (define_insn "adddf3"
892: [(set (match_operand:DF 0 "general_operand" "=f,m,f")
893: (plus:DF (match_operand:DF 1 "general_operand" "%0,0,0")
894: (match_operand:DF 2 "general_operand" "m,!f,!*r")))]
895: "TARGET_80387"
896: "*FP_CALL (\"fadd%z0 %0\", \"fadd%z0 %0\", 2)")
897:
898: (define_insn "addsf3"
899: [(set (match_operand:SF 0 "general_operand" "=f,m,f")
900: (plus:SF (match_operand:SF 1 "general_operand" "%0,0,0")
901: (match_operand:SF 2 "general_operand" "m,!f,!*r")))]
902: "TARGET_80387"
903: "*FP_CALL (\"fadd%z0 %0\", \"fadd%z0 %0\", 2)")
904:
905: ;;- subtract instructions
906:
907: ;;moved decl above leal
908:
909: (define_insn "subsi3"
910: [(set (match_operand:SI 0 "general_operand" "=rm,r")
911: (minus:SI (match_operand:SI 1 "general_operand" "0,0")
912: (match_operand:SI 2 "general_operand" "ri,rm")))]
913: ""
914: "sub%L0 %2,%0")
915:
916: (define_insn ""
917: [(set (match_operand:HI 0 "general_operand" "=g")
918: (minus:HI (match_operand:HI 1 "general_operand" "0")
919: (const_int 1)))]
920: ""
921: "dec%W0 %0")
922:
923: (define_insn "subhi3"
924: [(set (match_operand:HI 0 "general_operand" "=rm,r")
925: (minus:HI (match_operand:HI 1 "general_operand" "0,0")
926: (match_operand:HI 2 "general_operand" "ri,rm")))]
927: ""
928: "sub%W0 %2,%0")
929:
930: (define_insn ""
931: [(set (match_operand:QI 0 "general_operand" "=qm")
932: (minus:QI (match_operand:QI 1 "general_operand" "0")
933: (const_int 1)))]
934: ""
935: "dec%B0 %0")
936:
937: (define_insn "subqi3"
938: [(set (match_operand:QI 0 "general_operand" "=m,q")
939: (minus:QI (match_operand:QI 1 "general_operand" "0,0")
940: (match_operand:QI 2 "general_operand" "qn,qmn")))]
941: ""
942: "sub%B0 %2,%0")
943:
944: (define_insn "subdf3"
945: [(set (match_operand:DF 0 "general_operand" "=f,m,f,f")
946: (minus:DF (match_operand:DF 1 "general_operand" "0,0,0,m")
947: (match_operand:DF 2 "general_operand" "m,!f,!*r,*0")))]
948: "TARGET_80387"
949: "*FP_CALL (\"fsub%z0 %0\", \"fsubr%z0 %0\", 2)")
950:
951:
952: (define_insn "subsf3"
953: [(set (match_operand:SF 0 "general_operand" "=f,m,f,f")
954: (minus:SF (match_operand:SF 1 "general_operand" "0,0,0,m")
955: (match_operand:SF 2 "general_operand" "m,!f,!*r,*0")))]
956: "TARGET_80387"
957: "*FP_CALL (\"fsub%z0 %0\", \"fsubr%z0 %0\", 2)")
958:
959: ;;- multiply instructions
960:
961: ;(define_insn "mulqi3"
962: ; [(set (match_operand:QI 0 "general_operand" "=a")
963: ; (mult:QI (match_operand:QI 1 "general_operand" "%0")
964: ; (match_operand:QI 2 "general_operand" "qm")))]
965: ; ""
966: ; "mul%B0 %2,%0")
967:
968: (define_insn "mulhi3"
969: [(set (match_operand:HI 0 "general_operand" "=r,r")
970: (mult:SI (match_operand:HI 1 "general_operand" "%0,rm")
971: (match_operand:HI 2 "general_operand" "g,i")))]
972: ""
973: "*
974: {
975: if (GET_CODE (operands[1]) == REG
976: && REGNO (operands[1]) == REGNO (operands[0])
977: && (GET_CODE (operands[2]) == MEM
978: || GET_CODE (operands[2]) == REG))
979: /* Assembler has weird restrictions. */
980: return AS2 (imul%W0,%2,%0);
981: return AS3 (imul%W0,%2,%1,%0);
982: }")
983:
984: (define_insn "mulsi3"
985: [(set (match_operand:SI 0 "general_operand" "=r,r")
986: (mult:SI (match_operand:SI 1 "general_operand" "%0,rm")
987: (match_operand:SI 2 "general_operand" "g,i")))]
988: ""
989: "*
990: {
991: if (GET_CODE (operands[1]) == REG
992: && REGNO (operands[1]) == REGNO (operands[0])
993: && (GET_CODE (operands[2]) == MEM
994: || GET_CODE (operands[2]) == REG))
995: /* Assembler has weird restrictions. */
996: return AS2 (imul%L0,%2,%0);
997: return AS3 (imul%L0,%2,%1,%0);
998: }")
999:
1000: ;; Turned off due to possible assembler bug.
1001: ;(define_insn "umulqi3"
1002: ; [(set (match_operand:QI 0 "general_operand" "=a")
1003: ; (umult:QI (match_operand:QI 1 "general_operand" "%0")
1004: ; (match_operand:QI 2 "general_operand" "qm")))]
1005: ; ""
1006: ; "mul%B0 %2,%0")
1007:
1008: ;(define_insn "umulqihi3"
1009: ; [(set (match_operand:HI 0 "general_operand" "=a")
1010: ; (umult:HI (match_operand:QI 1 "general_operand" "%0")
1011: ; (match_operand:QI 2 "general_operand" "qm")))]
1012: ; ""
1013: ; "mul%B0 %2,%0")
1014:
1015: (define_insn "umulhi3"
1016: [(set (match_operand:HI 0 "general_operand" "=a")
1017: (umult:SI (match_operand:HI 1 "general_operand" "%0")
1018: (match_operand:HI 2 "general_operand" "rm")))
1019: (clobber (reg:HI 1))]
1020: ""
1021: "mul%W0 %2,%0")
1022:
1023: (define_insn "umulsi3"
1024: [(set (match_operand:SI 0 "general_operand" "=a")
1025: (umult:SI (match_operand:SI 1 "general_operand" "%0")
1026: (match_operand:SI 2 "general_operand" "rm")))
1027: (clobber (reg:SI 1))]
1028: ""
1029: "mul%L0 %2,%0")
1030:
1031: (define_insn "muldf3"
1032: [(set (match_operand:DF 0 "general_operand" "=f,m,f")
1033: (mult:DF (match_operand:DF 1 "general_operand" "%0,0,0")
1034: (match_operand:DF 2 "general_operand" "m,!f,!*r")))]
1035: "TARGET_80387"
1036: "*FP_CALL (\"fmul%z0 %0\", \"fmul%z0 %0\", 2)
1037: ")
1038:
1039: (define_insn "mulsf3"
1040: [(set (match_operand:SF 0 "general_operand" "=f,m,f")
1041: (mult:SF (match_operand:SF 1 "general_operand" "%0,0,0")
1042: (match_operand:SF 2 "general_operand" "m,!f,!*r")))]
1043: "TARGET_80387"
1044: "*FP_CALL (\"fmul%z0 %0\", \"fmul%z0 %0\", 2)
1045: ")
1046:
1047: ;;- divide instructions
1048: (define_insn "divdf3"
1049: [(set (match_operand:DF 0 "general_operand" "=f,m,f,f")
1050: (div:DF (match_operand:DF 1 "general_operand" "0,0,0,m")
1051: (match_operand:DF 2 "general_operand" "m,!f,!*r,*0")))]
1052: "TARGET_80387"
1053: "*FP_CALL (\"fdiv%z0 %0\", \"fdivr%z0 %0\", 2)
1054: ")
1055:
1056: (define_insn "divsf3"
1057: [(set (match_operand:SF 0 "general_operand" "=f,m,f,f")
1058: (div:SF (match_operand:SF 1 "general_operand" "0,0,0,m")
1059: (match_operand:SF 2 "general_operand" "m,!f,!*r,*0")))]
1060: "TARGET_80387"
1061: "*FP_CALL (\"fdiv%z0 %0\", \"fdivr%z0 %0\", 2)
1062: ")
1063:
1064: ;; Remainder instructions.
1065:
1066: (define_insn "divmodsi4"
1067: [(set (match_operand:SI 0 "general_operand" "=a")
1068: (div:SI (match_operand:SI 1 "general_operand" "0")
1069: (match_operand:SI 2 "general_operand" "rm")))
1070: (set (match_operand:SI 3 "general_operand" "=&d")
1071: (mod:SI (match_dup 1) (match_dup 2)))]
1072: ""
1073: "cltd\;idiv%L0 %2")
1074:
1075: (define_insn "udivmodsi4"
1076: [(set (match_operand:SI 0 "general_operand" "=a")
1077: (udiv:SI (match_operand:SI 1 "general_operand" "0")
1078: (match_operand:SI 2 "general_operand" "rm")))
1079: (set (match_operand:SI 3 "general_operand" "=&d")
1080: (umod:SI (match_dup 1) (match_dup 2)))]
1081: ""
1082: "xor%L0 %3,%3\;div%L0 %2")
1083:
1084: /*
1085: ;;this should be a valid double division which we may want to add
1086:
1087: (define_insn ""
1088: [(set (match_operand:SI 0 "general_operand" "=a")
1089: (udiv:DI (match_operand:DI 1 "general_operand" "a")
1090: (match_operand:SI 2 "general_operand" "rm")))
1091: (set (match_operand:SI 3 "general_operand" "=d")
1092: (umod:SI (match_dup 1) (match_dup 2)))]
1093: ""
1094: "div%L0 %2,%0")
1095: */
1096:
1097: ;;- and instructions
1098:
1099: ;; The `r' in `rm' for operand 3 looks redundant, but it causes
1100: ;; optional reloads to be generated if op 3 is a pseudo in a stack slot.
1101:
1102: (define_insn "andsi3"
1103: [(set (match_operand:SI 0 "general_operand" "=rm,r")
1104: (and:SI (match_operand:SI 1 "general_operand" "%0,0")
1105: (match_operand:SI 2 "general_operand" "ri,rm")))]
1106: ""
1107: "and%L0 %2,%0")
1108:
1109: (define_insn "andhi3"
1110: [(set (match_operand:HI 0 "general_operand" "=rm,r")
1111: (and:HI (match_operand:HI 1 "general_operand" "%0,0")
1112: (match_operand:HI 2 "general_operand" "ri,rm")))]
1113: ""
1114: "and%W0 %2,%0")
1115:
1116: (define_insn "andqi3"
1117: [(set (match_operand:QI 0 "general_operand" "=m,q")
1118: (and:QI (match_operand:QI 1 "general_operand" "%0,0")
1119: (match_operand:QI 2 "general_operand" "qn,qmn")))]
1120: ""
1121: "and%B0 %2,%0")
1122:
1123: /* I am nervous about these two.. add them later..
1124: ;I presume this means that we have something in say op0= eax which is small
1125: ;and we want to and it with memory so we can do this by just an
1126: ;andb m,%al and have success.
1127: (define_insn ""
1128: [(set (match_operand:SI 0 "general_operand" "=r")
1129: (and:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rm"))
1130: (match_operand:SI 2 "general_operand" "0")))]
1131: "GET_CODE (operands[2]) == CONST_INT
1132: && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))"
1133: "and%W0 %1,%0")
1134:
1135: (define_insn ""
1136: [(set (match_operand:SI 0 "general_operand" "=q")
1137: (and:SI (zero_extend:SI (match_operand:QI 1 "general_operand" "qm"))
1138: (match_operand:SI 2 "general_operand" "0")))]
1139: "GET_CODE (operands[2]) == CONST_INT
1140: && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (QImode))"
1141: "and%L0 %1,%0")
1142:
1143: */
1144:
1145:
1146:
1147: ;;- Bit set (inclusive or) instructions
1148:
1149: (define_insn "iorsi3"
1150: [(set (match_operand:SI 0 "general_operand" "=rm,r")
1151: (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1152: (match_operand:SI 2 "general_operand" "ri,rm")))]
1153: ""
1154: "or%L0 %2,%0")
1155:
1156: (define_insn "iorhi3"
1157: [(set (match_operand:HI 0 "general_operand" "=rm,r")
1158: (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
1159: (match_operand:HI 2 "general_operand" "ri,rm")))]
1160: ""
1161: "or%W0 %2,%0")
1162:
1163: (define_insn "iorqi3"
1164: [(set (match_operand:QI 0 "general_operand" "=m,q")
1165: (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
1166: (match_operand:QI 2 "general_operand" "qn,qmn")))]
1167: ""
1168: "or%B0 %2,%0")
1169:
1170: ;;- xor instructions
1171:
1172: (define_insn "xorsi3"
1173: [(set (match_operand:SI 0 "general_operand" "=rm,r")
1174: (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
1175: (match_operand:SI 2 "general_operand" "ri,rm")))]
1176: ""
1177: "xor%L0 %2,%0")
1178:
1179: (define_insn "xorhi3"
1180: [(set (match_operand:HI 0 "general_operand" "=rm,r")
1181: (xor:HI (match_operand:HI 1 "general_operand" "%0,0")
1182: (match_operand:HI 2 "general_operand" "ri,rm")))]
1183: ""
1184: "xor%W0 %2,%0")
1185:
1186: (define_insn "xorqi3"
1187: [(set (match_operand:QI 0 "general_operand" "=qm")
1188: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1189: (match_operand:QI 2 "general_operand" "qn")))]
1190: ""
1191: "xor%B0 %2,%0")
1192:
1193: ;;- negation instructions
1194: (define_insn "negsi2"
1195: [(set (match_operand:SI 0 "general_operand" "=rm")
1196: (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1197: ""
1198: "neg%L0 %0")
1199:
1200: (define_insn "neghi2"
1201: [(set (match_operand:HI 0 "general_operand" "=rm")
1202: (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1203: ""
1204: "neg%W0 %0")
1205:
1206: (define_insn "negqi2"
1207: [(set (match_operand:QI 0 "general_operand" "=qm")
1208: (neg:QI (match_operand:QI 1 "general_operand" "0")))]
1209: ""
1210: "neg%B0 %0")
1211:
1212: (define_insn "negsf2"
1213: [(set (match_operand:SF 0 "general_operand" "=f,!m")
1214: (neg:SF (match_operand:SF 1 "general_operand" "0,0")))]
1215: "TARGET_80387"
1216: "*FP_CALL1 (\"fchs\")")
1217:
1218: (define_insn "negdf2"
1219: [(set (match_operand:DF 0 "general_operand" "=f,!m")
1220: (neg:DF (match_operand:DF 1 "general_operand" "0,0")))]
1221: "TARGET_80387"
1222: "*FP_CALL1 (\"fchs\")")
1223:
1224: ;; Absolute value instructions
1225:
1226: (define_insn "abssf2"
1227: [(set (match_operand:SF 0 "general_operand" "=f,!m")
1228: (abs:SF (match_operand:SF 1 "general_operand" "0,0")))]
1229: "TARGET_80387"
1230: "*FP_CALL1 (\"fabs\")")
1231:
1232: (define_insn "absdf2"
1233: [(set (match_operand:DF 0 "general_operand" "=f,!m")
1234: (abs:DF (match_operand:DF 1 "general_operand" "0,0")))]
1235: "TARGET_80387"
1236: "*FP_CALL1 (\"fabs\")")
1237:
1238: ;;- one complement instructions
1239: (define_insn "one_cmplsi2"
1240: [(set (match_operand:SI 0 "general_operand" "=rm")
1241: (not:SI (match_operand:SI 1 "general_operand" "0")))]
1242: ""
1243: "not%L0 %0")
1244:
1245: (define_insn "one_cmplhi2"
1246: [(set (match_operand:HI 0 "general_operand" "=rm")
1247: (not:HI (match_operand:HI 1 "general_operand" "0")))]
1248: ""
1249: "not%W0 %0")
1250:
1251: (define_insn "one_cmplqi2"
1252: [(set (match_operand:QI 0 "general_operand" "=qm")
1253: (not:QI (match_operand:QI 1 "general_operand" "0")))]
1254: ""
1255: "not%B0 %0")
1256:
1257: ;;- arithmetic shift instructions
1258:
1259: (define_insn "ashlsi3"
1260: [(set (match_operand:SI 0 "general_operand" "=rm")
1261: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1262: (match_operand:SI 2 "general_operand" "cI")))]
1263: ""
1264: "*
1265: {
1266: if (REG_P (operands[2]))
1267: return AS2 (sal%L0,%R0cl,%0);
1268: else if (REG_P (operands[1]) && GET_CODE (operands[2]) == CONST_INT
1269: && INTVAL (operands[2]) == 1)
1270: return AS2 (add%L0,%1,%1);
1271: return AS2 (sal%L0,%2,%1);
1272: }")
1273:
1274: (define_insn "ashlhi3"
1275: [(set (match_operand:HI 0 "general_operand" "=rm")
1276: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1277: (match_operand:HI 2 "general_operand" "cI")))]
1278: ""
1279: "*
1280: {
1281: if (REG_P (operands[2]))
1282: return AS2 (sal%W0,%R0cl,%0);
1283: else
1284: return AS2 (sal%W0,%2,%1);
1285: }")
1286:
1287: (define_insn "ashlqi3"
1288: [(set (match_operand:QI 0 "general_operand" "=qm")
1289: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1290: (match_operand:QI 2 "general_operand" "cI")))]
1291: ""
1292: "*
1293: {
1294: if (REG_P (operands[2]))
1295: return AS2 (sal%B0,%R0cl,%0);
1296: else
1297: return AS2 (sal%B0,%2,%1);
1298: }")
1299:
1300: (define_insn "ashrsi3"
1301: [(set (match_operand:SI 0 "general_operand" "=rm")
1302: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1303: (match_operand:SI 2 "general_operand" "cI")))]
1304: ""
1305: "*
1306: {
1307: if (REG_P (operands[2]))
1308: return AS2 (sar%L0,%R0cl,%0);
1309: else
1310: return AS2 (sar%L0,%2,%0);
1311: }")
1312:
1313: (define_insn "ashrhi3"
1314: [(set (match_operand:HI 0 "general_operand" "=rm")
1315: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1316: (match_operand:HI 2 "general_operand" "cI")))]
1317: ""
1318: "*
1319: {
1320: if (REG_P (operands[2]))
1321: return AS2 (sar%W0,%R0cl,%0);
1322: else
1323: return AS2 (sar%W0,%2,%0);
1324: }")
1325:
1326: (define_insn "ashrqi3"
1327: [(set (match_operand:QI 0 "general_operand" "=qm")
1328: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1329: (match_operand:QI 2 "general_operand" "cI")))]
1330: ""
1331: "*
1332: {
1333: if (REG_P (operands[2]))
1334: return AS2 (sar%B0,%R0cl,%0);
1335: return
1336: AS2 (sar%B0,%2,%1);
1337: }")
1338:
1339: ;;- logical shift instructions
1340:
1341: (define_insn "lshlsi3"
1342: [(set (match_operand:SI 0 "general_operand" "=rm")
1343: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1344: (match_operand:SI 2 "general_operand" "cI")))]
1345: ""
1346: "*
1347: {
1348: if (REG_P (operands[2]))
1349: return AS2 (shl%L0,%R0cl,%0);
1350: else
1351: return AS2 (shl%L0,%2,%1);
1352: }")
1353:
1354: (define_insn "lshlhi3"
1355: [(set (match_operand:HI 0 "general_operand" "=rm")
1356: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1357: (match_operand:HI 2 "general_operand" "cI")))]
1358: ""
1359: "*
1360: {
1361: if (REG_P (operands[2]))
1362: return AS2 (shl%W0,%R0cl,%0);
1363: else
1364: return AS2 (shl%W0,%2,%1);
1365: }")
1366:
1367: (define_insn "lshlqi3"
1368: [(set (match_operand:QI 0 "general_operand" "=qm")
1369: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1370: (match_operand:QI 2 "general_operand" "cI")))]
1371: ""
1372: "*
1373: {
1374: if (REG_P (operands[2]))
1375: return AS2 (shl%B0,%R0cl,%0);
1376: else
1377: return AS2 (shl%B0,%2,%1);
1378: }")
1379:
1380: (define_insn "lshrsi3"
1381: [(set (match_operand:SI 0 "general_operand" "=rm")
1382: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1383: (match_operand:SI 2 "general_operand" "cI")))]
1384: ""
1385: "*
1386: {
1387: if (REG_P (operands[2]))
1388: return AS2 (shr%L0,%R0cl,%0);
1389: else
1390: return AS2 (shr%L0,%2,%1);
1391: }")
1392:
1393: (define_insn "lshrhi3"
1394: [(set (match_operand:HI 0 "general_operand" "=rm")
1395: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1396: (match_operand:HI 2 "general_operand" "cI")))]
1397: ""
1398: "*
1399: {
1400: if (REG_P (operands[2]))
1401: return AS2 (shr%W0,%%cl,%0);
1402: else
1403: return AS2 (shr%W0,%2,%1);
1404: }")
1405:
1406: (define_insn "lshrqi3"
1407: [(set (match_operand:QI 0 "general_operand" "=qm")
1408: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1409: (match_operand:QI 2 "general_operand" "cI")))]
1410: ""
1411: "*
1412: {
1413: if (REG_P (operands[2]))
1414: return AS2 (shr%B0,%%cl,%0);
1415: else
1416: return AS2 (shr%B0,%2,%1);
1417: }")
1418:
1419: ;;- rotate instructions
1420:
1421: (define_insn "rotlsi3"
1422: [(set (match_operand:SI 0 "general_operand" "=rm")
1423: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1424: (match_operand:SI 2 "general_operand" "cI")))]
1425: ""
1426: "*
1427: {
1428: if (REG_P (operands[2]))
1429: return AS2 (rol%L0,%%cl,%0);
1430: else
1431: return AS2 (rol%L0,%2,%1);
1432: }")
1433:
1434: (define_insn "rotlhi3"
1435: [(set (match_operand:HI 0 "general_operand" "=rm")
1436: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1437: (match_operand:HI 2 "general_operand" "cI")))]
1438: ""
1439: "*
1440: {
1441: if (REG_P (operands[2]))
1442: return AS2 (rol%W0,%%cl,%0);
1443: else
1444: return AS2 (rol%W0,%2,%1);
1445: }")
1446:
1447: (define_insn "rotlqi3"
1448: [(set (match_operand:QI 0 "general_operand" "=qm")
1449: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1450: (match_operand:QI 2 "general_operand" "cI")))]
1451: ""
1452: "*
1453: {
1454: if (REG_P (operands[2]))
1455: return AS2 (rol%B0,%%cl,%0);
1456: else
1457: return AS2 (rol%B0,%2,%1);
1458: }")
1459:
1460: (define_insn "rotrsi3"
1461: [(set (match_operand:SI 0 "general_operand" "=rm")
1462: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1463: (match_operand:SI 2 "general_operand" "cI")))]
1464: ""
1465: "*
1466: {
1467: if (REG_P (operands[2]))
1468: return AS2 (ror%L0,%%cl,%0);
1469: else
1470: return AS2 (ror%L0,%2,%1);
1471: }")
1472:
1473: (define_insn "rotrhi3"
1474: [(set (match_operand:HI 0 "general_operand" "=rm")
1475: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1476: (match_operand:HI 2 "general_operand" "cI")))]
1477: ""
1478: "*
1479: {
1480: if (REG_P (operands[2]))
1481: return AS2 (ror%W0,%%cl,%0);
1482: else
1483: return AS2 (ror%W0,%2,%1);
1484: }")
1485:
1486: (define_insn "rotrqi3"
1487: [(set (match_operand:QI 0 "general_operand" "=qm")
1488: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1489: (match_operand:QI 2 "general_operand" "cI")))]
1490: ""
1491: "*
1492: {
1493: if (REG_P (operands[2]))
1494: return AS2 (ror%B0,%%cl,%0);
1495: else
1496: return AS2 (ror%B0,%2,%1);
1497: }")
1498:
1499: ;; Store-flag instructions.
1500:
1501: (define_insn "seq"
1502: [(set (match_operand:QI 0 "general_operand" "=q")
1503: (eq (cc0) (const_int 0)))]
1504: ""
1505: "*
1506: cc_status = cc_prev_status;
1507: return \"sete %0\";
1508: ")
1509:
1510: (define_insn "sne"
1511: [(set (match_operand:QI 0 "general_operand" "=q")
1512: (ne (cc0) (const_int 0)))]
1513: ""
1514: "*
1515: cc_status = cc_prev_status;
1516: return \"setne %0\";
1517: ")
1518:
1519: (define_insn "sgt"
1520: [(set (match_operand:QI 0 "general_operand" "=q")
1521: (gt (cc0) (const_int 0)))]
1522: ""
1523: "*
1524: cc_status = cc_prev_status;
1525: OUTPUT_JUMP (\"setg %0\", \"seta %0\", 0);
1526: ")
1527:
1528: (define_insn "sgtu"
1529: [(set (match_operand:QI 0 "general_operand" "=q")
1530: (gtu (cc0) (const_int 0)))]
1531: ""
1532: "* cc_status = cc_prev_status;
1533: return \"seta %0\"; ")
1534:
1535: (define_insn "slt"
1536: [(set (match_operand:QI 0 "general_operand" "=q")
1537: (lt (cc0) (const_int 0)))]
1538: ""
1539: "* cc_status = cc_prev_status;
1540: OUTPUT_JUMP (\"setl %0\", \"setb %0\", \"sets %0\"); ")
1541:
1542: (define_insn "sltu"
1543: [(set (match_operand:QI 0 "general_operand" "=q")
1544: (ltu (cc0) (const_int 0)))]
1545: ""
1546: "* cc_status = cc_prev_status;
1547: return \"setb %0\"; ")
1548:
1549: (define_insn "sge"
1550: [(set (match_operand:QI 0 "general_operand" "=q")
1551: (ge (cc0) (const_int 0)))]
1552: ""
1553: "* cc_status = cc_prev_status;
1554: OUTPUT_JUMP (\"setge %0\", \"setae %0\", \"setns %0\"); ")
1555:
1556: (define_insn "sgeu"
1557: [(set (match_operand:QI 0 "general_operand" "=q")
1558: (geu (cc0) (const_int 0)))]
1559: ""
1560: "* cc_status = cc_prev_status;
1561: return \"setae %0\"; ")
1562:
1563: (define_insn "sle"
1564: [(set (match_operand:QI 0 "general_operand" "=q")
1565: (le (cc0) (const_int 0)))]
1566: ""
1567: "*
1568: cc_status = cc_prev_status;
1569: OUTPUT_JUMP (\"setle %0\", \"setbe %0\", 0);
1570: ")
1571:
1572: (define_insn "sleu"
1573: [(set (match_operand:QI 0 "general_operand" "=q")
1574: (leu (cc0) (const_int 0)))]
1575: ""
1576: "* cc_status = cc_prev_status;
1577: return \"setbe %0\"; ")
1578:
1579: ;; Basic conditional jump instructions.
1580: ;; We ignore the overflow flag for signed branch instructions.
1581:
1582: (define_insn "beq"
1583: [(set (pc)
1584: (if_then_else (eq (cc0)
1585: (const_int 0))
1586: (label_ref (match_operand 0 "" ""))
1587: (pc)))]
1588: ""
1589: "je %l0")
1590:
1591: (define_insn "bne"
1592: [(set (pc)
1593: (if_then_else (ne (cc0)
1594: (const_int 0))
1595: (label_ref (match_operand 0 "" ""))
1596: (pc)))]
1597: ""
1598: "jne %l0")
1599:
1600: (define_insn "bgt"
1601: [(set (pc)
1602: (if_then_else (gt (cc0)
1603: (const_int 0))
1604: (label_ref (match_operand 0 "" ""))
1605: (pc)))]
1606: ""
1607: "*OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0)")
1608:
1609: (define_insn "bgtu"
1610: [(set (pc)
1611: (if_then_else (gtu (cc0)
1612: (const_int 0))
1613: (label_ref (match_operand 0 "" ""))
1614: (pc)))]
1615: ""
1616: "ja %l0")
1617:
1.1.1.3 ! root 1618: ;; There is no jump insn to check for `<' on IEEE floats.
! 1619: ;; Page 17-80 in the 80387 manual says jb, but that's wrong;
! 1620: ;; jb checks for `not >='. So swap the operands and do `>'.
! 1621: (define_expand "blt"
! 1622: [(set (pc)
! 1623: (if_then_else (lt (cc0)
! 1624: (const_int 0))
! 1625: (label_ref (match_operand 0 "" ""))
! 1626: (pc)))]
! 1627: ""
! 1628: "
! 1629: {
! 1630: extern rtx sequence_stack;
! 1631: rtx prev = XEXP (XEXP (sequence_stack, 1), 0);
! 1632: rtx body = PATTERN (prev);
! 1633: rtx comp;
! 1634: if (GET_CODE (body) == SET)
! 1635: comp = SET_SRC (body);
! 1636: else
! 1637: comp = SET_SRC (XVECEXP (body, 0, 0));
! 1638:
! 1639: if (GET_CODE (comp) == COMPARE
! 1640: ? GET_MODE_CLASS (GET_MODE (XEXP (comp, 0))) == MODE_FLOAT
! 1641: : GET_MODE_CLASS (GET_MODE (comp)) == MODE_FLOAT)
! 1642: {
! 1643: if (GET_CODE (comp) == COMPARE)
! 1644: {
! 1645: rtx op0 = XEXP (comp, 0);
! 1646: rtx op1 = XEXP (comp, 1);
! 1647: XEXP (comp, 0) = op1;
! 1648: XEXP (comp, 1) = op0;
! 1649: }
! 1650: else
! 1651: {
! 1652: rtx new = gen_rtx (COMPARE, VOIDmode,
! 1653: CONST0_RTX (GET_MODE (comp)), comp);
! 1654: if (GET_CODE (body) == SET)
! 1655: SET_SRC (body) = new;
! 1656: else
! 1657: SET_SRC (XVECEXP (body, 0, 0)) = new;
! 1658: }
! 1659: emit_insn (gen_bgt (operands[0]));
! 1660: DONE;
! 1661: }
! 1662: }")
! 1663:
! 1664: (define_insn ""
1.1 root 1665: [(set (pc)
1666: (if_then_else (lt (cc0)
1667: (const_int 0))
1668: (label_ref (match_operand 0 "" ""))
1669: (pc)))]
1670: ""
1671: "*OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\")")
1672:
1673: (define_insn "bltu"
1674: [(set (pc)
1675: (if_then_else (ltu (cc0)
1676: (const_int 0))
1677: (label_ref (match_operand 0 "" ""))
1678: (pc)))]
1679: ""
1680: "jb %l0")
1681:
1682: (define_insn "bge"
1683: [(set (pc)
1684: (if_then_else (ge (cc0)
1685: (const_int 0))
1686: (label_ref (match_operand 0 "" ""))
1687: (pc)))]
1688: ""
1689: "*OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\")")
1690:
1691: (define_insn "bgeu"
1692: [(set (pc)
1693: (if_then_else (geu (cc0)
1694: (const_int 0))
1695: (label_ref (match_operand 0 "" ""))
1696: (pc)))]
1697: ""
1698: "jae %l0")
1699:
1.1.1.3 ! root 1700: ;; See comment on `blt', above.
! 1701: (define_expand "ble"
! 1702: [(set (pc)
! 1703: (if_then_else (le (cc0)
! 1704: (const_int 0))
! 1705: (label_ref (match_operand 0 "" ""))
! 1706: (pc)))]
! 1707: ""
! 1708: "
! 1709: {
! 1710: extern rtx sequence_stack;
! 1711: rtx prev = XEXP (XEXP (sequence_stack, 1), 0);
! 1712: rtx body = PATTERN (prev);
! 1713: rtx comp;
! 1714: if (GET_CODE (body) == SET)
! 1715: comp = SET_SRC (body);
! 1716: else
! 1717: comp = SET_SRC (XVECEXP (body, 0, 0));
! 1718:
! 1719: if (GET_CODE (comp) == COMPARE
! 1720: ? GET_MODE_CLASS (GET_MODE (XEXP (comp, 0))) == MODE_FLOAT
! 1721: : GET_MODE_CLASS (GET_MODE (comp)) == MODE_FLOAT)
! 1722: {
! 1723: if (GET_CODE (comp) == COMPARE)
! 1724: {
! 1725: rtx op0 = XEXP (comp, 0);
! 1726: rtx op1 = XEXP (comp, 1);
! 1727: XEXP (comp, 0) = op1;
! 1728: XEXP (comp, 1) = op0;
! 1729: }
! 1730: else
! 1731: {
! 1732: rtx new = gen_rtx (COMPARE, VOIDmode,
! 1733: CONST0_RTX (GET_MODE (comp)), comp);
! 1734: if (GET_CODE (body) == SET)
! 1735: SET_SRC (body) = new;
! 1736: else
! 1737: SET_SRC (XVECEXP (body, 0, 0)) = new;
! 1738: }
! 1739: emit_insn (gen_bge (operands[0]));
! 1740: DONE;
! 1741: }
! 1742: }")
! 1743:
! 1744: (define_insn ""
1.1 root 1745: [(set (pc)
1746: (if_then_else (le (cc0)
1747: (const_int 0))
1748: (label_ref (match_operand 0 "" ""))
1749: (pc)))]
1750: ""
1751: "*OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0) ")
1752:
1753: (define_insn "bleu"
1754: [(set (pc)
1755: (if_then_else (leu (cc0)
1756: (const_int 0))
1757: (label_ref (match_operand 0 "" ""))
1758: (pc)))]
1759: ""
1760: "jbe %l0")
1761:
1762: ;; Negated conditional jump instructions.
1763:
1764: (define_insn ""
1765: [(set (pc)
1766: (if_then_else (eq (cc0)
1767: (const_int 0))
1768: (pc)
1769: (label_ref (match_operand 0 "" ""))))]
1770: ""
1771: "jne %l0")
1772:
1773: (define_insn ""
1774: [(set (pc)
1775: (if_then_else (ne (cc0)
1776: (const_int 0))
1777: (pc)
1778: (label_ref (match_operand 0 "" ""))))]
1779: ""
1780: "je %l0")
1781:
1782: (define_insn ""
1783: [(set (pc)
1784: (if_then_else (gt (cc0)
1785: (const_int 0))
1786: (pc)
1787: (label_ref (match_operand 0 "" ""))))]
1788: ""
1789: "*OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0) ")
1790:
1791: (define_insn ""
1792: [(set (pc)
1793: (if_then_else (gtu (cc0)
1794: (const_int 0))
1795: (pc)
1796: (label_ref (match_operand 0 "" ""))))]
1797: ""
1798: "jbe %l0")
1799:
1800: (define_insn ""
1801: [(set (pc)
1802: (if_then_else (lt (cc0)
1803: (const_int 0))
1804: (pc)
1805: (label_ref (match_operand 0 "" ""))))]
1806: ""
1807: "*OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\")
1808: ")
1809:
1810: (define_insn ""
1811: [(set (pc)
1812: (if_then_else (ltu (cc0)
1813: (const_int 0))
1814: (pc)
1815: (label_ref (match_operand 0 "" ""))))]
1816: ""
1817: "jae %l0")
1818:
1819: (define_insn ""
1820: [(set (pc)
1821: (if_then_else (ge (cc0)
1822: (const_int 0))
1823: (pc)
1824: (label_ref (match_operand 0 "" ""))))]
1825: ""
1826: "*OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\")")
1827:
1828: (define_insn ""
1829: [(set (pc)
1830: (if_then_else (geu (cc0)
1831: (const_int 0))
1832: (pc)
1833: (label_ref (match_operand 0 "" ""))))]
1834: ""
1835: "jb %l0")
1836:
1837: (define_insn ""
1838: [(set (pc)
1839: (if_then_else (le (cc0)
1840: (const_int 0))
1841: (pc)
1842: (label_ref (match_operand 0 "" ""))))]
1843: ""
1844: "*OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0)")
1845:
1846: (define_insn ""
1847: [(set (pc)
1848: (if_then_else (leu (cc0)
1849: (const_int 0))
1850: (pc)
1851: (label_ref (match_operand 0 "" ""))))]
1852: ""
1853: "ja %l0")
1854:
1855: ;; Unconditional and other jump instructions
1856: (define_insn "jump"
1857: [(set (pc)
1858: (label_ref (match_operand 0 "" "")))]
1859: ""
1860: "jmp %l0")
1861:
1862: (define_insn "tablejump"
1863: [(set (pc) (match_operand:SI 0 "general_operand" "rm"))
1864: (use (label_ref (match_operand 1 "" "")))]
1865: ""
1866: "*
1867: {
1868: CC_STATUS_INIT;
1869:
1870: return \"jmp %*%0\";
1871: }")
1872:
1873: /*
1874: (define_insn ""
1875: [(set (pc)
1876: (if_then_else
1877: (ne (compare (minus:HI (match_operand:HI 0 "general_operand" "c")
1878: (const_int 1))
1879: (const_int -1))
1880: (const_int 0))
1881: (label_ref (match_operand 1 "" "g"))
1882: (pc)))
1883: (set (match_dup 0)
1884: (minus:HI (match_dup 0)
1885: (const_int 1)))]
1886: ""
1887: "loop %l1")
1888:
1889: (define_insn ""
1890: [(set (pc)
1891: (if_then_else
1892: (ne (compare (const_int -1)
1893: (minus:SI (match_operand:SI 0 "general_operand" "c")
1894: (const_int 1)))
1895: (const_int 0))
1896: (label_ref (match_operand 1 "" "g"))
1897: (pc)))
1898: (set (match_dup 0)
1899: (minus:SI (match_dup 0)
1900: (const_int 1)))]
1901: ""
1902: "loop %l1")
1903: */
1904:
1905: ;; Call subroutine returning no value.
1906: (define_insn "call"
1907: [(call (match_operand:QI 0 "indirect_operand" "m")
1908: (match_operand:SI 1 "general_operand" "g"))]
1909: ;; Operand 1 not really used on the m68000.
1910: ""
1911: "*
1912: {
1913: if (GET_CODE (operands[0]) == MEM
1914: && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
1915: {
1916: operands[0] = XEXP (operands[0], 0);
1917: return \"call %*%0\";
1918: }
1919: else
1920: return \"call %0\";
1921: }")
1922:
1923: ;; Call subroutine, returning value in operand 0
1924: ;; (which must be a hard register).
1925: (define_insn "call_value"
1926: [(set (match_operand 0 "" "=rf")
1927: (call (match_operand:QI 1 "indirect_operand" "m")
1928: (match_operand:SI 2 "general_operand" "g")))]
1929: ;; Operand 2 not really used on the m68000.
1930: ""
1931: "*
1932: {
1933: if (GET_CODE (operands[1]) == MEM
1934: && ! CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
1935: {
1936: operands[1] = XEXP (operands[1], 0);
1937: output_asm_insn (\"call %*%1\", operands);
1938: }
1939: else
1940: output_asm_insn (\"call %1\", operands);
1941:
1942: if (GET_MODE (operands[0]) == DFmode
1943: || GET_MODE (operands[0]) == SFmode)
1944: {
1945: /* fp_pop_level++; */
1946: /* pop if reg dead */
1947: if (!FP_REG_P (operands[0]))
1948: abort ();
1949: if (top_dead_p (insn))
1950: {
1951: POP_ONE_FP;
1952: }
1953: }
1954: RET;
1955: }")
1956:
1957: (define_insn "nop"
1958: [(const_int 0)]
1959: ""
1960: "nop")
1961:
1962: ;;- Local variables:
1963: ;;- mode:emacs-lisp
1964: ;;- comment-start: ";;- "
1965: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
1966: ;;- eval: (modify-syntax-entry ?[ "(]")
1967: ;;- eval: (modify-syntax-entry ?] ")[")
1968: ;;- eval: (modify-syntax-entry ?{ "(}")
1969: ;;- eval: (modify-syntax-entry ?} "){")
1970: ;;- End:
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