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1.1 root 1: ;; GCC machine description for Intel 80386.
2: ;; Copyright (C) 1988 Free Software Foundation, Inc.
3: ;; Mostly by William Schelter.
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 1, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21:
22: ;;- instruction definitions
23:
24: ;;- @@The original PO technology requires these to be ordered by speed,
25: ;;- @@ so that assigner will pick the fastest.
26:
27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28:
29: ;;- When naming insn's (operand 0 of define_insn) be careful about using
30: ;;- names from other targets machine descriptions.
31:
32: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
33: ;;- updates for most instructions.
34:
35: ;;- Operand classes for the register allocator:
36: ;;- 'a' for eax
37: ;;- 'd' for edx
38: ;;- 'c' for ecx
39: ;;- 'b' for ebx
40: ;;- 'f' for anything in FLOAT_REGS
41: ;;- 'r' any (non-floating-point) register
42: ;;- 'q' regs that allow byte operations (A, B, C and D)
43: ;;- 'A' A and D registers
44:
45: ;; the special asm out single letter directives following a '%' are:
46: ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of operands[1]
47: ;; 's' output a '*'
48: ;; 'w' If the operand is a REG, it uses the mode size to determine the
49: ;; printing of the reg
50:
51:
52: ;; Put tstsi first among test insns so it matches a CONST_INT operand.
53:
54: (define_insn "tstsi"
55: [(set (cc0)
56: (match_operand:SI 0 "general_operand" "rm"))]
57: ""
58: "*
59: {
60: operands[1] = const0_rtx;
61: if (REG_P (operands[0]))
62: return AS2 (test%L0,%0,%0);
63: return AS2 (cmp%L0,%1,%0);
64: }")
65:
66: (define_insn "tsthi"
67: [(set (cc0)
68: (match_operand:HI 0 "general_operand" "rm"))]
69: ""
70: "*
71: {
72: operands[1] = const0_rtx;
73: if (REG_P (operands[0]))
74: return AS2 (test%W0,%0,%0);
75: return AS2 (cmp%W0,%1,%0);
76: }")
77:
78: (define_insn "tstqi"
79: [(set (cc0)
80: (match_operand:QI 0 "general_operand" "qm"))]
81: ""
82: "*
83: {
84: operands[1] = const0_rtx;
85: if (REG_P (operands[0]))
86: return AS2 (test%B0,%0,%0);
87: return AS2 (cmp%B0,%1,%0);
88: }")
89:
90: (define_insn "tstsf"
91: [(set (cc0)
92: (match_operand:SF 0 "general_operand" "rm,f"))
1.1.1.3 root 93: (clobber (reg:SI 0))]
1.1 root 94: "TARGET_80387"
95: "*
96: {
97: rtx xops[1];
98: if (!FP_REG_P (operands[0]))
99: fp_push_sf (operands[0]);
100: /* fp_pop_level--; */
101: xops[0] = FP_TOP;
102: cc_status.flags |= CC_IN_80387;
103: if (FP_REG_P (operands[0]) && ! top_dead_p (insn))
104: output_asm_insn (\"ftst\;fnstsw %R0ax\;sahf\", xops);
105: else
106: output_asm_insn (\"ftst\;fstp %0(0)\;fnstsw %R0ax\;sahf\", xops);
107: RETCOM (testsf);
108: }")
109:
110: (define_insn "tstdf"
111: [(set (cc0)
112: (match_operand:DF 0 "general_operand" "rm,f"))
1.1.1.3 root 113: (clobber (reg:SI 0))
1.1 root 114: ]
115: "TARGET_80387"
116: "*
117: {
118: rtx xops[1];
119: if (!FP_REG_P (operands[0]))
120: fp_push_df (operands[0]);
121: /* fp_pop_level--; */
122: xops[0] = FP_TOP;
123: cc_status.flags |= CC_IN_80387;
124: if (FP_REG_P (operands[0]) && ! top_dead_p (insn))
125: output_asm_insn (\"ftst\;fnstsw %R0ax\;sahf\", xops);
126: else
127: output_asm_insn (\"ftst\;fstp %0(0)\;fnstsw %R0ax\;sahf\", xops);
128: RETCOM (testdf);
129: }")
130:
131: ;;- compare instructions
132:
133: ;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
134:
135: (define_insn "cmpsi"
136: [(set (cc0)
137: (compare (match_operand:SI 0 "general_operand" "mr,ri")
138: (match_operand:SI 1 "general_operand" "ri,mr")))]
139: ""
140: "*
141: {
142: if (REG_P (operands[1])
143: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
144: {
145: cc_status.flags |= CC_REVERSED;
146: return AS2 (cmp%L0,%0,%1);
147: }
148: return AS2 (cmp%L0,%1,%0);
149: }")
150:
151: (define_insn "cmphi"
152: [(set (cc0)
153: (compare (match_operand:HI 0 "general_operand" "mr,ri")
154: (match_operand:HI 1 "general_operand" "ri,mr")))]
155: ""
156: "*
157: {
158: if (REG_P (operands[1])
159: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
160: {
161: cc_status.flags |= CC_REVERSED;
162: return AS2 (cmp%W0,%0,%1);
163: }
164: return AS2 (cmp%W0,%1,%0);
165: }")
166:
167: (define_insn "cmpqi"
168: [(set (cc0)
169: (compare (match_operand:QI 0 "general_operand" "qn,mq")
170: (match_operand:QI 1 "general_operand" "qm,nq")))]
171: ""
172: "*
173: {
174: if (REG_P (operands[1])
175: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
176: {
177: cc_status.flags |= CC_REVERSED;
178: return AS2 (cmp%B0,%0,%1);
179: }
180: return AS2 (cmp%B0,%1,%0);
181: }")
182:
183: (define_insn "cmpdf"
184: [(set (cc0)
185: (compare (match_operand:DF 0 "general_operand" "m,f*r,m,f,r,!*r")
186: (match_operand:DF 1 "general_operand" "m,m,f*r,r,f,*r")))
187: (clobber (reg:SI 0))]
188: "TARGET_80387"
189: "*
190: {
191: if (FP_REG_P (operands[0]))
192: {
193: rtx tem = operands[1];
194: operands[1] = operands[0];
195: operands[0] = tem;
196: cc_status.flags |= CC_REVERSED;
197: }
198: if (! FP_REG_P (operands[1]))
199: output_movdf (FP_TOP, operands[1]);
200: output_movdf (FP_TOP, operands[0]);
201: /* fp_pop_level--;
202: fp_pop_level--; */
203: cc_status.flags |= CC_IN_80387;
204: return \"fcompp\;fnstsw %R0ax\;sahf\";
205: }")
206:
207: (define_insn "cmpsf"
208: [(set (cc0)
209: (compare (match_operand:SF 0 "general_operand" "m,f*r,m,f,r,!*r")
210: (match_operand:SF 1 "general_operand" "m,m,f*r,r,f,*r")))
211: (clobber (reg:SI 0))]
212: "TARGET_80387"
213: "*
214: {
215: if (FP_REG_P (operands[0]))
216: {
217: rtx tem = operands[1];
218: operands[1] = operands[0];
219: operands[0] = tem;
220: cc_status.flags |= CC_REVERSED;
221: }
222: if (! FP_REG_P (operands[1]))
223: output_movsf (FP_TOP, operands[1]);
224: output_movsf (FP_TOP, operands[0]);
225: /* fp_pop_level--;
226: fp_pop_level--; */
227: cc_status.flags |= CC_IN_80387;
228: return \"fcompp\;fnstsw %R0ax\;sahf\";
229: }")
230:
231: ;; logical compare
232: (define_insn ""
233: [(set (cc0)
234: (and:SI (match_operand:SI 0 "general_operand" "rm,ri")
235: (match_operand:SI 1 "general_operand" "ri,rm")))]
236: ""
237: "*
238: {
1.1.1.3 root 239: if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
1.1 root 240: return AS2 (test%L0,%1,%0);
241: return AS2 (test%L0,%0,%1);
242: }")
243:
244: (define_insn ""
245: [(set (cc0)
246: (and:HI (match_operand:HI 0 "general_operand" "rm,ri")
247: (match_operand:HI 1 "general_operand" "ri,rm")))]
248: ""
249: "*
250: {
1.1.1.3 root 251: if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
1.1 root 252: return AS2 (test%W0,%1,%0);
253: return AS2 (test%W0,%0,%1);
254: }")
255:
256: (define_insn ""
257: [(set (cc0)
258: (and:QI (match_operand:QI 0 "general_operand" "qm,qi")
259: (match_operand:QI 1 "general_operand" "qi,qm")))]
260: ""
261: "*
262: {
1.1.1.3 root 263: if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
1.1 root 264: return AS2 (test%B0,%1,%0);
265: return AS2 (test%B0,%0,%1);
266: }")
267:
268: ;; move instructions.
269: ;; There is one for each machine mode,
270: ;; and each is preceded by a corresponding push-insn pattern
271: ;; (since pushes are not general_operands on the 386).
272:
273: (define_insn ""
274: [(set (match_operand:SI 0 "push_operand" "=<")
275: (match_operand:SI 1 "general_operand" "g"))]
276: ""
277: "push%L0 %1")
278:
279: ;; General case of fullword move.
280: (define_insn "movsi"
281: [(set (match_operand:SI 0 "general_operand" "=g,r")
282: (match_operand:SI 1 "general_operand" "ri,m"))]
283: ""
284: "*
285: {
286: rtx link;
287: if (operands[1] == const0_rtx && REG_P (operands[0]))
288: return \"xor%L0 %0,%0\";
289: if (operands[1] == const1_rtx
290: && (link = find_reg_note (insn, REG_WAS_0, 0))
291: /* Make sure the insn that stored the 0 is still present. */
292: && ! XEXP (link, 0)->volatil
293: && GET_CODE (XEXP (link, 0)) != NOTE
294: /* Make sure cross jumping didn't happen here. */
295: && no_labels_between_p (XEXP (link, 0), insn))
296: /* Fastest way to change a 0 to a 1. */
297: return \"inc%L0 %0\";
298: return \"mov%L0 %1,%0\";
299: }")
300:
301: (define_insn ""
302: [(set (match_operand:HI 0 "push_operand" "=<")
303: (match_operand:HI 1 "general_operand" "g"))]
304: ""
305: "push%W0 %1")
306:
307: (define_insn "movhi"
308: [(set (match_operand:HI 0 "general_operand" "=g,r")
309: (match_operand:HI 1 "general_operand" "ri,m"))]
310: ""
311: "*
312: {
313: rtx link;
314: if (operands[1] == const0_rtx && REG_P (operands[0]))
315: return \"xor%W0 %0,%0\";
316: if (operands[1] == const1_rtx
317: && (link = find_reg_note (insn, REG_WAS_0, 0))
318: /* Make sure the insn that stored the 0 is still present. */
319: && ! XEXP (link, 0)->volatil
320: && GET_CODE (XEXP (link, 0)) != NOTE
321: /* Make sure cross jumping didn't happen here. */
322: && no_labels_between_p (XEXP (link, 0), insn))
323: /* Fastest way to change a 0 to a 1. */
324: return \"inc%W0 %0\";
325: return \"mov%W0 %1,%0\";
326: }")
327:
328: ;; emit_push_insn when it calls move_by_pieces
329: ;; requires an insn to "push a byte".
330: ;; But actually we use pushw, which has the effect of rounding
331: ;; the amount pushed up to a halfword.
332: (define_insn ""
333: [(set (match_operand:QI 0 "push_operand" "=<")
334: (match_operand:QI 1 "general_operand" "q"))]
335: ""
336: "*
337: {
338: operands[1] = gen_rtx (REG, HImode, REGNO (operands[1]));
339: return \"push%W0 %1\";
340: }")
341:
342: (define_insn "movqi"
343: [(set (match_operand:QI 0 "general_operand" "=q,*r,m")
344: (match_operand:QI 1 "general_operand" "*g,q,qi"))]
345: ""
346: "*
347: {
348: rtx link;
349: if (operands[1] == const0_rtx && REG_P (operands[0]))
350: return \"xor%B0 %0,%0\";
351: if (operands[1] == const1_rtx
352: && (link = find_reg_note (insn, REG_WAS_0, 0))
353: /* Make sure the insn that stored the 0 is still present. */
354: && ! XEXP (link, 0)->volatil
355: && GET_CODE (XEXP (link, 0)) != NOTE
356: /* Make sure cross jumping didn't happen here. */
357: && no_labels_between_p (XEXP (link, 0), insn))
358: /* Fastest way to change a 0 to a 1. */
359: return \"inc%B0 %0\";
360: /* If mov%B0 isn't allowed for one of these regs, use mov%W0. */
361: if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1]))
362: return (AS2 (mov%W0,%w1,%w0));
363: return (AS2 (mov%B0,%1,%0));
364: }")
365:
366: ; I suspect nothing can ever match this ???
367: ;(define_insn ""
368: ; [(set (match_operand:SF 0 "general_operand" "rm")
369: ; (match_operand:SF 1 "general_operand" "f"))
370: ; (clobber (reg:SF 8))]
371: ; ""
372: ; "*
373: ;{
374: ; output_asm_insn ("???", operands);
375: ; fpop_sf (operands[0]);
376: ; RETCOM (movsf_clobber);
377: ;}")
378:
379: (define_insn ""
380: [(set (match_operand:SF 0 "push_operand" "=<,<")
381: (match_operand:SF 1 "general_operand" "gF,f"))]
382: ""
383: "*
384: {
385: if (FP_REG_P (operands[1]))
386: {
387: rtx xops[3];
388: xops[0] = AT_SP (SFmode);
389: xops[1] = gen_rtx (CONST_INT, VOIDmode, 4);
390: xops[2] = stack_pointer_rtx;
391: /* fp_pop_level--; */
392: output_asm_insn (AS2 (sub%L0,%1,%2), xops);
1.1.1.2 root 393: if (top_dead_p (insn))
394: output_asm_insn (\"fstp%S0 %0\", xops);
395: else
1.1.1.4 ! root 396: output_asm_insn (\"fst%S0 %0\", xops);
1.1 root 397: RET;
398: }
399: return \"push%L0 %1\";
400: }")
401:
402: (define_insn "movsf"
1.1.1.4 ! root 403: ;; `rf' is duplicated in the second alternative
! 404: ;; to make sure an optional reload is generated
! 405: ;; for the memref in operand 0. Otherwise
! 406: ;; we could use too many hard regs.
! 407: [(set (match_operand:SF 0 "general_operand" "=rf,mrf,!rm")
! 408: (match_operand:SF 1 "general_operand" "mrf,rf,F"))]
1.1 root 409: ""
410: "*
411: {
412: if (FP_REG_P (operands[1])
413: && !FP_REG_P (operands[0])
414: && !top_dead_p (insn))
415: fp_store_sf (operands[0]);
416: else
417: output_movsf (operands[0], operands[1]);
418: RETCOM (movsf);
419: }")
420:
421: ;;should change to handle the memory operands[1] without doing df push..
422: (define_insn ""
423: [(set (match_operand:DF 0 "push_operand" "=<,<")
424: (match_operand:DF 1 "general_operand" "gF,f"))]
425: ""
426: "*
427: {
428: if (FP_REG_P (operands[1]))
429: {
430: rtx xops[3];
431: xops[0] = AT_SP (DFmode);
432: xops[1] = gen_rtx (CONST_INT, VOIDmode, 8);
433: xops[2] = stack_pointer_rtx;
434: /* fp_pop_level--; */
435: output_asm_insn (AS2 (sub%L0,%1,%2), xops);
1.1.1.2 root 436: if (top_dead_p(insn))
437: output_asm_insn (\"fstp%Q0 %0\", xops);
438: else
439: output_asm_insn (\"fst%Q0 %0\", xops);
1.1 root 440: RETCOM (pushdf);
441: }
442: else
443: return output_move_double (operands);
444: }")
445:
446: (define_insn "movdf"
1.1.1.4 ! root 447: [(set (match_operand:DF 0 "general_operand" "=rmf,&fr,!rm")
! 448: ;; `rf' is duplicated in the second alternative
! 449: ;; to make sure that optional reloads are generated
! 450: ;; for the memory reference in operand 1.
! 451: (match_operand:DF 1 "general_operand" "fr,mrf,F"))]
1.1 root 452: ""
453: "*
454: {
455: if (FP_REG_P (operands[1])
456: && ! FP_REG_P (operands[0])
457: && ! top_dead_p (insn))
458: fp_store_df (operands[0]);
459: else
460: output_movdf (operands[0], operands[1]);
461: RETCOM (movdf);
462: }")
463:
464: (define_insn ""
465: [(set (match_operand:DI 0 "push_operand" "=<")
466: (match_operand:DI 1 "general_operand" "roiF"))]
467: ""
468: "*
469: {
470: return output_move_double (operands);
471: }")
472:
473: (define_insn "movdi"
474: [(set (match_operand:DI 0 "general_operand" "=&r,rm")
475: (match_operand:DI 1 "general_operand" "m,riF"))]
476: ""
477: "*
478: {
479: return output_move_double (operands);
480: }")
481:
482: ;; These go after the move instructions
483: ;; because the move instructions are better (require no spilling)
484: ;; when they can apply. But these go before the add and subtract insns
485: ;; because it is often shorter to use these when both apply.
486:
487: ;Lennart Augustsson <[email protected]>
488: ;says this pattern just makes slower code:
489: ; pushl %ebp
490: ; addl $-80,(%esp)
491: ;instead of
492: ; leal -80(%ebp),%eax
493: ; pushl %eax
494: ;
495: ;(define_insn ""
496: ; [(set (match_operand:SI 0 "push_operand" "=<")
497: ; (plus:SI (match_operand:SI 1 "general_operand" "%r")
498: ; (match_operand:SI 2 "general_operand" "ri")))]
499: ; ""
500: ; "*
501: ;{
502: ; rtx xops[4];
503: ; xops[0] = operands[0];
504: ; xops[1] = operands[1];
505: ; xops[2] = operands[2];
506: ; xops[3] = gen_rtx (MEM, SImode, stack_pointer_rtx);
507: ; output_asm_insn (\"push%z1 %1\", xops);
508: ; output_asm_insn (AS2 (add%z3,%2,%3), xops);
509: ; RET;
510: ;}")
511:
512: (define_insn ""
513: [(set (match_operand:SI 0 "general_operand" "=g")
514: (plus:SI (match_operand:SI 1 "general_operand" "0")
515: (const_int 1)))]
516: ""
517: "inc%L0 %0")
518:
519: (define_insn ""
520: [(set (match_operand:SI 0 "general_operand" "=g")
521: (plus:SI (match_operand:SI 1 "general_operand" "0")
522: (const_int -1)))]
523: ""
524: "dec%L0 %0")
525:
526: (define_insn ""
527: [(set (match_operand:SI 0 "general_operand" "=g")
528: (minus:SI (match_operand:SI 1 "general_operand" "0")
529: (const_int 1)))]
530: ""
531: "dec%L0 %0")
532:
533: (define_insn ""
534: [(set (match_operand:SI 0 "register_operand" "=r")
535: (match_operand:QI 1 "address_operand" "p"))]
536: ""
537: "*
538: {
539: CC_STATUS_INIT;
540: /* Adding a constant to a register is faster with an add. */
541: if (GET_CODE (operands[1]) == PLUS
542: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
543: && rtx_equal_p (operands[0], XEXP (operands[1], 0)))
544: {
545: operands[1] = XEXP (operands[1], 1);
546: return AS2 (add%L0,%1,%0);
547: }
548: return \"lea%L0 %a1,%0\";
549: }")
550:
551: ;;- conversion instructions
552: ;;- NONE
553:
554: ;;- truncation instructions
555: (define_insn "truncsiqi2"
1.1.1.3 root 556: [(set (match_operand:QI 0 "general_operand" "=q,m")
1.1 root 557: (truncate:QI
1.1.1.3 root 558: (match_operand:SI 1 "general_operand" "qim,qn")))]
1.1 root 559: ""
1.1.1.3 root 560: "*
561: {
562: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
563: return \"mov%L0 %1,%k0\";
564: return \"mov%B0 %b1,%0\";
565: }")
1.1 root 566:
567: (define_insn "trunchiqi2"
1.1.1.3 root 568: [(set (match_operand:QI 0 "general_operand" "=q,m")
1.1 root 569: (truncate:QI
1.1.1.3 root 570: (match_operand:HI 1 "general_operand" "qim,qn")))]
1.1 root 571: ""
1.1.1.3 root 572: "*
573: {
574: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
575: return \"mov%W0 %1,%w0\";
576: return \"mov%B0 %b1,%0\";
577: }")
1.1 root 578:
579: (define_insn "truncsihi2"
1.1.1.3 root 580: [(set (match_operand:HI 0 "general_operand" "=r,m")
1.1 root 581: (truncate:HI
1.1.1.3 root 582: (match_operand:SI 1 "general_operand" "rim,rn")))]
1.1 root 583: ""
1.1.1.3 root 584: "*
585: {
586: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
587: return \"mov%L0 %1,%k0\";
588: return \"mov%W0 %w1,%0\";
589: }")
1.1 root 590:
591: ;;- zero extension instructions
592: ;; Note that the one starting from HImode comes before those for QImode
593: ;; so that a constant operand will match HImode, not QImode.
594:
595: (define_insn "zero_extendhisi2"
596: [(set (match_operand:SI 0 "general_operand" "=r")
597: (zero_extend:SI
598: (match_operand:HI 1 "general_operand" "rm")))]
599: ""
600: "movz%W0%L0 %1,%0")
601:
602: (define_insn "zero_extendqihi2"
603: [(set (match_operand:HI 0 "general_operand" "=r")
604: (zero_extend:HI
605: (match_operand:QI 1 "general_operand" "qm")))]
606: ""
607: "movz%B0%W0 %1,%0")
608:
609: (define_insn "zero_extendqisi2"
610: [(set (match_operand:SI 0 "general_operand" "=r")
611: (zero_extend:SI
612: (match_operand:QI 1 "general_operand" "qm")))]
613: ""
614: "movz%B0%L0 %1,%0")
615:
616: ;;- sign extension instructions
617: ;; Note that the one starting from HImode comes before those for QImode
618: ;; so that a constant operand will match HImode, not QImode.
619:
620: /*
621: (define_insn "extendsidi2"
622: [(set (match_operand:DI 0 "general_operand" "=a")
623: (sign_extend:DI
624: (match_operand:SI 1 "general_operand" "a")))]
625: ""
626: "clq")
627: */
628:
1.1.1.3 root 629: ;; Note that the i386 programmers' manual says that the opcodes
630: ;; are named movsx..., but the assembler on Unix does not accept that.
631: ;; We use what the Unix assembler expects.
632:
1.1 root 633: (define_insn "extendhisi2"
634: [(set (match_operand:SI 0 "general_operand" "=r")
635: (sign_extend:SI
636: (match_operand:HI 1 "general_operand" "rm")))]
637: ""
638: "movs%W0%L0 %1,%0")
639:
640: (define_insn "extendqihi2"
641: [(set (match_operand:HI 0 "general_operand" "=r")
642: (sign_extend:HI
643: (match_operand:QI 1 "general_operand" "qm")))]
644: ""
645: "movs%B0%W0 %1,%0")
646:
647: (define_insn "extendqisi2"
648: [(set (match_operand:SI 0 "general_operand" "=r")
649: (sign_extend:SI
650: (match_operand:QI 1 "general_operand" "qm")))]
651: ""
652: "movs%B0%L0 %1,%0"
653: )
654:
655: ;; Conversions between float and double.
656:
657: (define_insn "extendsfdf2"
658: [(set (match_operand:DF 0 "general_operand" "=fm,f,fm,fm")
659: (float_extend:DF
660: (match_operand:SF 1 "general_operand" "m,0,f,!*r")))]
661: "TARGET_80387"
662: "*
663: {
664: if (FP_REG_P (operands[0]))
665: {
666: output_movsf (operands[0], operands[1]);
667: RET;
668: }
669: if (FP_REG_P (operands[1]))
670: {
671: if (top_dead_p (insn))
672: fp_pop_df (operands[0]);
673: else
674: fp_store_df (operands[0]);
675: RET;
676: }
677: output_movsf (FP_TOP, operands[1]);
678: fp_pop_df (operands[0]);
679: RETCOM (extendsfdf2);
680: }")
681:
682: ;; This cannot output into an f-reg because there is no way to be
683: ;; sure of truncating in that case.
684: (define_insn "truncdfsf2"
685: [(set (match_operand:SF 0 "general_operand" "=m,!*r")
686: (float_truncate:SF
687: (match_operand:DF 1 "general_operand" "f,f")))]
688: "TARGET_80387"
689: "*
690: {
691: if (top_dead_p (insn))
692: fp_pop_sf (operands[0]);
693: else
694: fp_store_sf (operands[0]);
695: RETCOM (truncdfsf2);
696: }")
697:
698: ;; Conversion between fixed point and floating point.
699: ;; Note that among the fix-to-float insns
700: ;; the ones that start with SImode come first.
701: ;; That is so that an operand that is a CONST_INT
702: ;; (and therefore lacks a specific machine mode).
703: ;; will be recognized as SImode (which is always valid)
704: ;; rather than as QImode or HImode. The 80387 would not know
705: ;; what to do with the smaller sizes anyway. (I think).
706:
707: (define_insn "floatsisf2"
708: [(set (match_operand:SF 0 "general_operand" "=fm,fm")
709: (float:SF (match_operand:SI 1 "general_operand" "m,!*r")))]
710: "TARGET_80387"
711: "*
712: {
713: /* fp_pop_level++; */
714:
715: if (GET_CODE (operands[1]) != MEM)
716: {
717: rtx xops[2];
718: output_asm_insn (\"push%L0 %1\", operands);
719: operands[1] = AT_SP (SImode);
720: output_asm_insn (\"fild%L0 %1\", operands);
721: xops[0] = stack_pointer_rtx;
722: xops[1] = gen_rtx (CONST_INT, VOIDmode, 4);
723: output_asm_insn (AS2 (add%L0,%1,%0), xops);
724: }
725: else
726: output_asm_insn (\"fild%L0 %1\", operands);
727:
728: if (! FP_REG_P (operands[0]))
729: {
730: /* fp_pop_level--; */
731: return \"fstp%S0 %0\";
732: }
733: RET;
734: }")
735:
736: (define_insn "floatsidf2"
737: [(set (match_operand:DF 0 "general_operand" "=fm,fm")
738: (float:DF (match_operand:SI 1 "general_operand" "m,!*r")))]
739: "TARGET_80387"
740: "*
741: {
742: /* fp_pop_level++; */
743: if (GET_CODE (operands[1]) != MEM)
744: {
745: rtx xops[2];
746: output_asm_insn (\"push%L0 %1\", operands);
747: operands[1] = AT_SP (SImode);
748: output_asm_insn (\"fild%L0 %1\", operands);
749: xops[0] = stack_pointer_rtx;
750: xops[1] = gen_rtx (CONST_INT, VOIDmode, 4);
751: output_asm_insn (AS2 (add%L0,%1,%0), xops);
752: }
753: else
754: output_asm_insn (\"fild%L0 %1\", operands);
755: if (! FP_REG_P (operands[0]))
756: {
757: /* fp_pop_level--; */
758: return \"fstp%Q0 %0\";
759: }
760: RET;
761: }")
762:
763: ;; Convert a float to a float whose value is an integer.
764: ;; This is the first stage of converting it to an integer type.
765:
766: ;; On the 387 truncating doub to an short integer shor can be performed:
767:
768: ; fstcw -4(%esp) ;save cw
769: ; movw -4(%esp),%ax
770: ; orw $0x0c00,%ax ;set rounding to chop towards zero
771: ; movw %ax,-2(%esp) ;
772: ; fldcw -2(%esp) ;
773: ; fldl doubl
774: ; fistpl -12(%esp) ;store the round value
775: ; fldcw -4(%esp) ;restore cw
776: ; movl -12(%esp),%eax
777: ; movw %ax,shor ; move the result into shor.
778:
779: ;; but it is probably better to have a call, rather than waste this
780: ;; space. The last instruction would have been a movl if were
781: ;; going to an int instead of a short.
782: ;; For the moment we will go with the soft float for these.
783:
784: /* These are incorrect since they don't set the rounding bits of CW flag.
785: The proper way to do that is to make the function prologue save the CW
786: and also construct the alternate CW value needed for these insns.
787: Then these insns can output two fldcw's, referring to fixed places in
788: the stack frame.
789:
790: ;; Convert a float whose value is an integer
791: ;; to an actual integer. Second stage of converting float to integer type.
792:
793: (define_insn "fix_truncsfqi2"
794: [(set (match_operand:QI 0 "general_operand" "=m,?*q")
795: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "f,f"))))]
796: "TARGET_80387"
797: "*
798: {
799: fp_pop_int (operands[0]);
800: RET;
801: }")
802:
803: (define_insn "fix_truncsfhi2"
804: [(set (match_operand:HI 0 "general_operand" "=m,?*r")
805: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "f,f"))))]
806: "TARGET_80387"
807: "*
808: {
809: fp_pop_int (operands[0]);
810: RET;
811: }")
812:
813: (define_insn "fix_truncsfsi2"
814: [(set (match_operand:SI 0 "general_operand" "=m,?*r")
815: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "f,f"))))]
816: "TARGET_80387"
817: "*
818: {
819: fp_pop_int (operands[0]);
820: RET;
821: }")
822:
823: (define_insn "fix_truncdfqi2"
824: [(set (match_operand:QI 0 "general_operand" "=m,?*q")
825: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "f,f"))))]
826:
827: "TARGET_80387"
828: "*
829: {
830: fp_pop_int (operands[0]);
831: RET;
832: }")
833:
834:
835: (define_insn "fix_truncdfhi2"
836: [(set (match_operand:HI 0 "general_operand" "=m,?*r")
837: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "f,f"))))]
838: "TARGET_80387"
839: "*
840: {
841: fp_pop_int (operands[0]);
842: RET;
843: }")
844:
845:
846: (define_insn "fix_truncdfsi2"
847: [(set (match_operand:SI 0 "general_operand" "=m,?*r")
848: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "f,f"))))]
849: "TARGET_80387"
850: "*
851: {
852: fp_pop_int (operands[0]);
853: RET;
854: }")
855: */
856:
857:
858: ;;- add instructions
859: ;;moved incl to above leal
860:
861: (define_insn "addsi3"
862: [(set (match_operand:SI 0 "general_operand" "=rm,r")
863: (plus:SI (match_operand:SI 1 "general_operand" "%0,0")
864: (match_operand:SI 2 "general_operand" "ri,rm")))]
865: ""
866: "add%L0 %2,%0")
867:
868: (define_insn ""
869: [(set (match_operand:HI 0 "general_operand" "=g")
870: (plus:HI (match_operand:HI 1 "general_operand" "0")
871: (const_int 1)))]
872: ""
873: "inc%W0 %0")
874:
875: (define_insn "addhi3"
876: [(set (match_operand:HI 0 "general_operand" "=rm,r")
877: (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
878: (match_operand:HI 2 "general_operand" "ri,rm")))]
879: ""
880: "add%W0 %2,%0")
881:
882: (define_insn ""
883: [(set (match_operand:QI 0 "general_operand" "=qm")
884: (plus:QI (match_operand:QI 1 "general_operand" "0")
885: (const_int 1)))]
886: ""
887: "inc%B0 %0")
888:
889: (define_insn "addqi3"
890: [(set (match_operand:QI 0 "general_operand" "=m,q")
891: (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
892: (match_operand:QI 2 "general_operand" "qn,qmn")))]
893: ""
894: "add%B0 %2,%0")
895:
896: ;;had "fmF,m"
897:
898: (define_insn "adddf3"
899: [(set (match_operand:DF 0 "general_operand" "=f,m,f")
900: (plus:DF (match_operand:DF 1 "general_operand" "%0,0,0")
901: (match_operand:DF 2 "general_operand" "m,!f,!*r")))]
902: "TARGET_80387"
903: "*FP_CALL (\"fadd%z0 %0\", \"fadd%z0 %0\", 2)")
904:
905: (define_insn "addsf3"
906: [(set (match_operand:SF 0 "general_operand" "=f,m,f")
907: (plus:SF (match_operand:SF 1 "general_operand" "%0,0,0")
908: (match_operand:SF 2 "general_operand" "m,!f,!*r")))]
909: "TARGET_80387"
910: "*FP_CALL (\"fadd%z0 %0\", \"fadd%z0 %0\", 2)")
911:
912: ;;- subtract instructions
913:
914: ;;moved decl above leal
915:
916: (define_insn "subsi3"
917: [(set (match_operand:SI 0 "general_operand" "=rm,r")
918: (minus:SI (match_operand:SI 1 "general_operand" "0,0")
919: (match_operand:SI 2 "general_operand" "ri,rm")))]
920: ""
921: "sub%L0 %2,%0")
922:
923: (define_insn ""
924: [(set (match_operand:HI 0 "general_operand" "=g")
925: (minus:HI (match_operand:HI 1 "general_operand" "0")
926: (const_int 1)))]
927: ""
928: "dec%W0 %0")
929:
930: (define_insn "subhi3"
931: [(set (match_operand:HI 0 "general_operand" "=rm,r")
932: (minus:HI (match_operand:HI 1 "general_operand" "0,0")
933: (match_operand:HI 2 "general_operand" "ri,rm")))]
934: ""
935: "sub%W0 %2,%0")
936:
937: (define_insn ""
938: [(set (match_operand:QI 0 "general_operand" "=qm")
939: (minus:QI (match_operand:QI 1 "general_operand" "0")
940: (const_int 1)))]
941: ""
942: "dec%B0 %0")
943:
944: (define_insn "subqi3"
945: [(set (match_operand:QI 0 "general_operand" "=m,q")
946: (minus:QI (match_operand:QI 1 "general_operand" "0,0")
947: (match_operand:QI 2 "general_operand" "qn,qmn")))]
948: ""
949: "sub%B0 %2,%0")
950:
951: (define_insn "subdf3"
952: [(set (match_operand:DF 0 "general_operand" "=f,m,f,f")
953: (minus:DF (match_operand:DF 1 "general_operand" "0,0,0,m")
954: (match_operand:DF 2 "general_operand" "m,!f,!*r,*0")))]
955: "TARGET_80387"
956: "*FP_CALL (\"fsub%z0 %0\", \"fsubr%z0 %0\", 2)")
957:
958:
959: (define_insn "subsf3"
960: [(set (match_operand:SF 0 "general_operand" "=f,m,f,f")
961: (minus:SF (match_operand:SF 1 "general_operand" "0,0,0,m")
962: (match_operand:SF 2 "general_operand" "m,!f,!*r,*0")))]
963: "TARGET_80387"
964: "*FP_CALL (\"fsub%z0 %0\", \"fsubr%z0 %0\", 2)")
965:
966: ;;- multiply instructions
967:
968: ;(define_insn "mulqi3"
969: ; [(set (match_operand:QI 0 "general_operand" "=a")
970: ; (mult:QI (match_operand:QI 1 "general_operand" "%0")
971: ; (match_operand:QI 2 "general_operand" "qm")))]
972: ; ""
973: ; "mul%B0 %2,%0")
974:
975: (define_insn "mulhi3"
976: [(set (match_operand:HI 0 "general_operand" "=r,r")
977: (mult:SI (match_operand:HI 1 "general_operand" "%0,rm")
978: (match_operand:HI 2 "general_operand" "g,i")))]
979: ""
980: "*
981: {
982: if (GET_CODE (operands[1]) == REG
983: && REGNO (operands[1]) == REGNO (operands[0])
984: && (GET_CODE (operands[2]) == MEM
985: || GET_CODE (operands[2]) == REG))
986: /* Assembler has weird restrictions. */
987: return AS2 (imul%W0,%2,%0);
988: return AS3 (imul%W0,%2,%1,%0);
989: }")
990:
991: (define_insn "mulsi3"
992: [(set (match_operand:SI 0 "general_operand" "=r,r")
993: (mult:SI (match_operand:SI 1 "general_operand" "%0,rm")
994: (match_operand:SI 2 "general_operand" "g,i")))]
995: ""
996: "*
997: {
998: if (GET_CODE (operands[1]) == REG
999: && REGNO (operands[1]) == REGNO (operands[0])
1000: && (GET_CODE (operands[2]) == MEM
1001: || GET_CODE (operands[2]) == REG))
1002: /* Assembler has weird restrictions. */
1003: return AS2 (imul%L0,%2,%0);
1004: return AS3 (imul%L0,%2,%1,%0);
1005: }")
1006:
1007: ;; Turned off due to possible assembler bug.
1008: ;(define_insn "umulqi3"
1009: ; [(set (match_operand:QI 0 "general_operand" "=a")
1010: ; (umult:QI (match_operand:QI 1 "general_operand" "%0")
1011: ; (match_operand:QI 2 "general_operand" "qm")))]
1012: ; ""
1013: ; "mul%B0 %2,%0")
1014:
1015: ;(define_insn "umulqihi3"
1016: ; [(set (match_operand:HI 0 "general_operand" "=a")
1017: ; (umult:HI (match_operand:QI 1 "general_operand" "%0")
1018: ; (match_operand:QI 2 "general_operand" "qm")))]
1019: ; ""
1020: ; "mul%B0 %2,%0")
1021:
1022: (define_insn "umulhi3"
1023: [(set (match_operand:HI 0 "general_operand" "=a")
1024: (umult:SI (match_operand:HI 1 "general_operand" "%0")
1025: (match_operand:HI 2 "general_operand" "rm")))
1026: (clobber (reg:HI 1))]
1027: ""
1028: "mul%W0 %2,%0")
1029:
1030: (define_insn "umulsi3"
1031: [(set (match_operand:SI 0 "general_operand" "=a")
1032: (umult:SI (match_operand:SI 1 "general_operand" "%0")
1033: (match_operand:SI 2 "general_operand" "rm")))
1034: (clobber (reg:SI 1))]
1035: ""
1036: "mul%L0 %2,%0")
1037:
1038: (define_insn "muldf3"
1039: [(set (match_operand:DF 0 "general_operand" "=f,m,f")
1040: (mult:DF (match_operand:DF 1 "general_operand" "%0,0,0")
1041: (match_operand:DF 2 "general_operand" "m,!f,!*r")))]
1042: "TARGET_80387"
1043: "*FP_CALL (\"fmul%z0 %0\", \"fmul%z0 %0\", 2)
1044: ")
1045:
1046: (define_insn "mulsf3"
1047: [(set (match_operand:SF 0 "general_operand" "=f,m,f")
1048: (mult:SF (match_operand:SF 1 "general_operand" "%0,0,0")
1049: (match_operand:SF 2 "general_operand" "m,!f,!*r")))]
1050: "TARGET_80387"
1051: "*FP_CALL (\"fmul%z0 %0\", \"fmul%z0 %0\", 2)
1052: ")
1053:
1054: ;;- divide instructions
1055: (define_insn "divdf3"
1056: [(set (match_operand:DF 0 "general_operand" "=f,m,f,f")
1057: (div:DF (match_operand:DF 1 "general_operand" "0,0,0,m")
1058: (match_operand:DF 2 "general_operand" "m,!f,!*r,*0")))]
1059: "TARGET_80387"
1060: "*FP_CALL (\"fdiv%z0 %0\", \"fdivr%z0 %0\", 2)
1061: ")
1062:
1063: (define_insn "divsf3"
1064: [(set (match_operand:SF 0 "general_operand" "=f,m,f,f")
1065: (div:SF (match_operand:SF 1 "general_operand" "0,0,0,m")
1066: (match_operand:SF 2 "general_operand" "m,!f,!*r,*0")))]
1067: "TARGET_80387"
1068: "*FP_CALL (\"fdiv%z0 %0\", \"fdivr%z0 %0\", 2)
1069: ")
1070:
1071: ;; Remainder instructions.
1072:
1073: (define_insn "divmodsi4"
1074: [(set (match_operand:SI 0 "general_operand" "=a")
1075: (div:SI (match_operand:SI 1 "general_operand" "0")
1076: (match_operand:SI 2 "general_operand" "rm")))
1077: (set (match_operand:SI 3 "general_operand" "=&d")
1078: (mod:SI (match_dup 1) (match_dup 2)))]
1079: ""
1080: "cltd\;idiv%L0 %2")
1081:
1082: (define_insn "udivmodsi4"
1083: [(set (match_operand:SI 0 "general_operand" "=a")
1084: (udiv:SI (match_operand:SI 1 "general_operand" "0")
1085: (match_operand:SI 2 "general_operand" "rm")))
1086: (set (match_operand:SI 3 "general_operand" "=&d")
1087: (umod:SI (match_dup 1) (match_dup 2)))]
1088: ""
1089: "xor%L0 %3,%3\;div%L0 %2")
1090:
1091: /*
1092: ;;this should be a valid double division which we may want to add
1093:
1094: (define_insn ""
1095: [(set (match_operand:SI 0 "general_operand" "=a")
1096: (udiv:DI (match_operand:DI 1 "general_operand" "a")
1097: (match_operand:SI 2 "general_operand" "rm")))
1098: (set (match_operand:SI 3 "general_operand" "=d")
1099: (umod:SI (match_dup 1) (match_dup 2)))]
1100: ""
1101: "div%L0 %2,%0")
1102: */
1103:
1104: ;;- and instructions
1105:
1106: ;; The `r' in `rm' for operand 3 looks redundant, but it causes
1107: ;; optional reloads to be generated if op 3 is a pseudo in a stack slot.
1108:
1109: (define_insn "andsi3"
1110: [(set (match_operand:SI 0 "general_operand" "=rm,r")
1111: (and:SI (match_operand:SI 1 "general_operand" "%0,0")
1112: (match_operand:SI 2 "general_operand" "ri,rm")))]
1113: ""
1114: "and%L0 %2,%0")
1115:
1116: (define_insn "andhi3"
1117: [(set (match_operand:HI 0 "general_operand" "=rm,r")
1118: (and:HI (match_operand:HI 1 "general_operand" "%0,0")
1119: (match_operand:HI 2 "general_operand" "ri,rm")))]
1120: ""
1121: "and%W0 %2,%0")
1122:
1123: (define_insn "andqi3"
1124: [(set (match_operand:QI 0 "general_operand" "=m,q")
1125: (and:QI (match_operand:QI 1 "general_operand" "%0,0")
1126: (match_operand:QI 2 "general_operand" "qn,qmn")))]
1127: ""
1128: "and%B0 %2,%0")
1129:
1130: /* I am nervous about these two.. add them later..
1131: ;I presume this means that we have something in say op0= eax which is small
1132: ;and we want to and it with memory so we can do this by just an
1133: ;andb m,%al and have success.
1134: (define_insn ""
1135: [(set (match_operand:SI 0 "general_operand" "=r")
1136: (and:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rm"))
1137: (match_operand:SI 2 "general_operand" "0")))]
1138: "GET_CODE (operands[2]) == CONST_INT
1139: && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))"
1140: "and%W0 %1,%0")
1141:
1142: (define_insn ""
1143: [(set (match_operand:SI 0 "general_operand" "=q")
1144: (and:SI (zero_extend:SI (match_operand:QI 1 "general_operand" "qm"))
1145: (match_operand:SI 2 "general_operand" "0")))]
1146: "GET_CODE (operands[2]) == CONST_INT
1147: && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (QImode))"
1148: "and%L0 %1,%0")
1149:
1150: */
1151:
1152:
1153:
1154: ;;- Bit set (inclusive or) instructions
1155:
1156: (define_insn "iorsi3"
1157: [(set (match_operand:SI 0 "general_operand" "=rm,r")
1158: (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1159: (match_operand:SI 2 "general_operand" "ri,rm")))]
1160: ""
1161: "or%L0 %2,%0")
1162:
1163: (define_insn "iorhi3"
1164: [(set (match_operand:HI 0 "general_operand" "=rm,r")
1165: (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
1166: (match_operand:HI 2 "general_operand" "ri,rm")))]
1167: ""
1168: "or%W0 %2,%0")
1169:
1170: (define_insn "iorqi3"
1171: [(set (match_operand:QI 0 "general_operand" "=m,q")
1172: (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
1173: (match_operand:QI 2 "general_operand" "qn,qmn")))]
1174: ""
1175: "or%B0 %2,%0")
1176:
1177: ;;- xor instructions
1178:
1179: (define_insn "xorsi3"
1180: [(set (match_operand:SI 0 "general_operand" "=rm,r")
1181: (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
1182: (match_operand:SI 2 "general_operand" "ri,rm")))]
1183: ""
1184: "xor%L0 %2,%0")
1185:
1186: (define_insn "xorhi3"
1187: [(set (match_operand:HI 0 "general_operand" "=rm,r")
1188: (xor:HI (match_operand:HI 1 "general_operand" "%0,0")
1189: (match_operand:HI 2 "general_operand" "ri,rm")))]
1190: ""
1191: "xor%W0 %2,%0")
1192:
1193: (define_insn "xorqi3"
1194: [(set (match_operand:QI 0 "general_operand" "=qm")
1195: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1196: (match_operand:QI 2 "general_operand" "qn")))]
1197: ""
1198: "xor%B0 %2,%0")
1199:
1200: ;;- negation instructions
1201: (define_insn "negsi2"
1202: [(set (match_operand:SI 0 "general_operand" "=rm")
1203: (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1204: ""
1205: "neg%L0 %0")
1206:
1207: (define_insn "neghi2"
1208: [(set (match_operand:HI 0 "general_operand" "=rm")
1209: (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1210: ""
1211: "neg%W0 %0")
1212:
1213: (define_insn "negqi2"
1214: [(set (match_operand:QI 0 "general_operand" "=qm")
1215: (neg:QI (match_operand:QI 1 "general_operand" "0")))]
1216: ""
1217: "neg%B0 %0")
1218:
1219: (define_insn "negsf2"
1220: [(set (match_operand:SF 0 "general_operand" "=f,!m")
1221: (neg:SF (match_operand:SF 1 "general_operand" "0,0")))]
1222: "TARGET_80387"
1223: "*FP_CALL1 (\"fchs\")")
1224:
1225: (define_insn "negdf2"
1226: [(set (match_operand:DF 0 "general_operand" "=f,!m")
1227: (neg:DF (match_operand:DF 1 "general_operand" "0,0")))]
1228: "TARGET_80387"
1229: "*FP_CALL1 (\"fchs\")")
1230:
1231: ;; Absolute value instructions
1232:
1233: (define_insn "abssf2"
1234: [(set (match_operand:SF 0 "general_operand" "=f,!m")
1235: (abs:SF (match_operand:SF 1 "general_operand" "0,0")))]
1236: "TARGET_80387"
1237: "*FP_CALL1 (\"fabs\")")
1238:
1239: (define_insn "absdf2"
1240: [(set (match_operand:DF 0 "general_operand" "=f,!m")
1241: (abs:DF (match_operand:DF 1 "general_operand" "0,0")))]
1242: "TARGET_80387"
1243: "*FP_CALL1 (\"fabs\")")
1244:
1245: ;;- one complement instructions
1246: (define_insn "one_cmplsi2"
1247: [(set (match_operand:SI 0 "general_operand" "=rm")
1248: (not:SI (match_operand:SI 1 "general_operand" "0")))]
1249: ""
1250: "not%L0 %0")
1251:
1252: (define_insn "one_cmplhi2"
1253: [(set (match_operand:HI 0 "general_operand" "=rm")
1254: (not:HI (match_operand:HI 1 "general_operand" "0")))]
1255: ""
1256: "not%W0 %0")
1257:
1258: (define_insn "one_cmplqi2"
1259: [(set (match_operand:QI 0 "general_operand" "=qm")
1260: (not:QI (match_operand:QI 1 "general_operand" "0")))]
1261: ""
1262: "not%B0 %0")
1263:
1264: ;;- arithmetic shift instructions
1265:
1266: (define_insn "ashlsi3"
1267: [(set (match_operand:SI 0 "general_operand" "=rm")
1268: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1269: (match_operand:SI 2 "general_operand" "cI")))]
1270: ""
1271: "*
1272: {
1273: if (REG_P (operands[2]))
1274: return AS2 (sal%L0,%R0cl,%0);
1275: else if (REG_P (operands[1]) && GET_CODE (operands[2]) == CONST_INT
1276: && INTVAL (operands[2]) == 1)
1277: return AS2 (add%L0,%1,%1);
1278: return AS2 (sal%L0,%2,%1);
1279: }")
1280:
1281: (define_insn "ashlhi3"
1282: [(set (match_operand:HI 0 "general_operand" "=rm")
1283: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1284: (match_operand:HI 2 "general_operand" "cI")))]
1285: ""
1286: "*
1287: {
1288: if (REG_P (operands[2]))
1289: return AS2 (sal%W0,%R0cl,%0);
1290: else
1291: return AS2 (sal%W0,%2,%1);
1292: }")
1293:
1294: (define_insn "ashlqi3"
1295: [(set (match_operand:QI 0 "general_operand" "=qm")
1296: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1297: (match_operand:QI 2 "general_operand" "cI")))]
1298: ""
1299: "*
1300: {
1301: if (REG_P (operands[2]))
1302: return AS2 (sal%B0,%R0cl,%0);
1303: else
1304: return AS2 (sal%B0,%2,%1);
1305: }")
1306:
1307: (define_insn "ashrsi3"
1308: [(set (match_operand:SI 0 "general_operand" "=rm")
1309: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1310: (match_operand:SI 2 "general_operand" "cI")))]
1311: ""
1312: "*
1313: {
1314: if (REG_P (operands[2]))
1315: return AS2 (sar%L0,%R0cl,%0);
1316: else
1317: return AS2 (sar%L0,%2,%0);
1318: }")
1319:
1320: (define_insn "ashrhi3"
1321: [(set (match_operand:HI 0 "general_operand" "=rm")
1322: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1323: (match_operand:HI 2 "general_operand" "cI")))]
1324: ""
1325: "*
1326: {
1327: if (REG_P (operands[2]))
1328: return AS2 (sar%W0,%R0cl,%0);
1329: else
1330: return AS2 (sar%W0,%2,%0);
1331: }")
1332:
1333: (define_insn "ashrqi3"
1334: [(set (match_operand:QI 0 "general_operand" "=qm")
1335: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1336: (match_operand:QI 2 "general_operand" "cI")))]
1337: ""
1338: "*
1339: {
1340: if (REG_P (operands[2]))
1341: return AS2 (sar%B0,%R0cl,%0);
1342: return
1343: AS2 (sar%B0,%2,%1);
1344: }")
1345:
1346: ;;- logical shift instructions
1347:
1348: (define_insn "lshlsi3"
1349: [(set (match_operand:SI 0 "general_operand" "=rm")
1350: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1351: (match_operand:SI 2 "general_operand" "cI")))]
1352: ""
1353: "*
1354: {
1355: if (REG_P (operands[2]))
1356: return AS2 (shl%L0,%R0cl,%0);
1357: else
1358: return AS2 (shl%L0,%2,%1);
1359: }")
1360:
1361: (define_insn "lshlhi3"
1362: [(set (match_operand:HI 0 "general_operand" "=rm")
1363: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1364: (match_operand:HI 2 "general_operand" "cI")))]
1365: ""
1366: "*
1367: {
1368: if (REG_P (operands[2]))
1369: return AS2 (shl%W0,%R0cl,%0);
1370: else
1371: return AS2 (shl%W0,%2,%1);
1372: }")
1373:
1374: (define_insn "lshlqi3"
1375: [(set (match_operand:QI 0 "general_operand" "=qm")
1376: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1377: (match_operand:QI 2 "general_operand" "cI")))]
1378: ""
1379: "*
1380: {
1381: if (REG_P (operands[2]))
1382: return AS2 (shl%B0,%R0cl,%0);
1383: else
1384: return AS2 (shl%B0,%2,%1);
1385: }")
1386:
1387: (define_insn "lshrsi3"
1388: [(set (match_operand:SI 0 "general_operand" "=rm")
1389: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1390: (match_operand:SI 2 "general_operand" "cI")))]
1391: ""
1392: "*
1393: {
1394: if (REG_P (operands[2]))
1395: return AS2 (shr%L0,%R0cl,%0);
1396: else
1397: return AS2 (shr%L0,%2,%1);
1398: }")
1399:
1400: (define_insn "lshrhi3"
1401: [(set (match_operand:HI 0 "general_operand" "=rm")
1402: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1403: (match_operand:HI 2 "general_operand" "cI")))]
1404: ""
1405: "*
1406: {
1407: if (REG_P (operands[2]))
1408: return AS2 (shr%W0,%%cl,%0);
1409: else
1410: return AS2 (shr%W0,%2,%1);
1411: }")
1412:
1413: (define_insn "lshrqi3"
1414: [(set (match_operand:QI 0 "general_operand" "=qm")
1415: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1416: (match_operand:QI 2 "general_operand" "cI")))]
1417: ""
1418: "*
1419: {
1420: if (REG_P (operands[2]))
1421: return AS2 (shr%B0,%%cl,%0);
1422: else
1423: return AS2 (shr%B0,%2,%1);
1424: }")
1425:
1426: ;;- rotate instructions
1427:
1428: (define_insn "rotlsi3"
1429: [(set (match_operand:SI 0 "general_operand" "=rm")
1430: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1431: (match_operand:SI 2 "general_operand" "cI")))]
1432: ""
1433: "*
1434: {
1435: if (REG_P (operands[2]))
1436: return AS2 (rol%L0,%%cl,%0);
1437: else
1438: return AS2 (rol%L0,%2,%1);
1439: }")
1440:
1441: (define_insn "rotlhi3"
1442: [(set (match_operand:HI 0 "general_operand" "=rm")
1443: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1444: (match_operand:HI 2 "general_operand" "cI")))]
1445: ""
1446: "*
1447: {
1448: if (REG_P (operands[2]))
1449: return AS2 (rol%W0,%%cl,%0);
1450: else
1451: return AS2 (rol%W0,%2,%1);
1452: }")
1453:
1454: (define_insn "rotlqi3"
1455: [(set (match_operand:QI 0 "general_operand" "=qm")
1456: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1457: (match_operand:QI 2 "general_operand" "cI")))]
1458: ""
1459: "*
1460: {
1461: if (REG_P (operands[2]))
1462: return AS2 (rol%B0,%%cl,%0);
1463: else
1464: return AS2 (rol%B0,%2,%1);
1465: }")
1466:
1467: (define_insn "rotrsi3"
1468: [(set (match_operand:SI 0 "general_operand" "=rm")
1469: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1470: (match_operand:SI 2 "general_operand" "cI")))]
1471: ""
1472: "*
1473: {
1474: if (REG_P (operands[2]))
1475: return AS2 (ror%L0,%%cl,%0);
1476: else
1477: return AS2 (ror%L0,%2,%1);
1478: }")
1479:
1480: (define_insn "rotrhi3"
1481: [(set (match_operand:HI 0 "general_operand" "=rm")
1482: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1483: (match_operand:HI 2 "general_operand" "cI")))]
1484: ""
1485: "*
1486: {
1487: if (REG_P (operands[2]))
1488: return AS2 (ror%W0,%%cl,%0);
1489: else
1490: return AS2 (ror%W0,%2,%1);
1491: }")
1492:
1493: (define_insn "rotrqi3"
1494: [(set (match_operand:QI 0 "general_operand" "=qm")
1495: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1496: (match_operand:QI 2 "general_operand" "cI")))]
1497: ""
1498: "*
1499: {
1500: if (REG_P (operands[2]))
1501: return AS2 (ror%B0,%%cl,%0);
1502: else
1503: return AS2 (ror%B0,%2,%1);
1504: }")
1505:
1506: ;; Store-flag instructions.
1507:
1508: (define_insn "seq"
1509: [(set (match_operand:QI 0 "general_operand" "=q")
1510: (eq (cc0) (const_int 0)))]
1511: ""
1512: "*
1513: cc_status = cc_prev_status;
1514: return \"sete %0\";
1515: ")
1516:
1517: (define_insn "sne"
1518: [(set (match_operand:QI 0 "general_operand" "=q")
1519: (ne (cc0) (const_int 0)))]
1520: ""
1521: "*
1522: cc_status = cc_prev_status;
1523: return \"setne %0\";
1524: ")
1525:
1526: (define_insn "sgt"
1527: [(set (match_operand:QI 0 "general_operand" "=q")
1528: (gt (cc0) (const_int 0)))]
1529: ""
1530: "*
1531: cc_status = cc_prev_status;
1532: OUTPUT_JUMP (\"setg %0\", \"seta %0\", 0);
1533: ")
1534:
1535: (define_insn "sgtu"
1536: [(set (match_operand:QI 0 "general_operand" "=q")
1537: (gtu (cc0) (const_int 0)))]
1538: ""
1539: "* cc_status = cc_prev_status;
1540: return \"seta %0\"; ")
1541:
1542: (define_insn "slt"
1543: [(set (match_operand:QI 0 "general_operand" "=q")
1544: (lt (cc0) (const_int 0)))]
1545: ""
1546: "* cc_status = cc_prev_status;
1547: OUTPUT_JUMP (\"setl %0\", \"setb %0\", \"sets %0\"); ")
1548:
1549: (define_insn "sltu"
1550: [(set (match_operand:QI 0 "general_operand" "=q")
1551: (ltu (cc0) (const_int 0)))]
1552: ""
1553: "* cc_status = cc_prev_status;
1554: return \"setb %0\"; ")
1555:
1556: (define_insn "sge"
1557: [(set (match_operand:QI 0 "general_operand" "=q")
1558: (ge (cc0) (const_int 0)))]
1559: ""
1560: "* cc_status = cc_prev_status;
1561: OUTPUT_JUMP (\"setge %0\", \"setae %0\", \"setns %0\"); ")
1562:
1563: (define_insn "sgeu"
1564: [(set (match_operand:QI 0 "general_operand" "=q")
1565: (geu (cc0) (const_int 0)))]
1566: ""
1567: "* cc_status = cc_prev_status;
1568: return \"setae %0\"; ")
1569:
1570: (define_insn "sle"
1571: [(set (match_operand:QI 0 "general_operand" "=q")
1572: (le (cc0) (const_int 0)))]
1573: ""
1574: "*
1575: cc_status = cc_prev_status;
1576: OUTPUT_JUMP (\"setle %0\", \"setbe %0\", 0);
1577: ")
1578:
1579: (define_insn "sleu"
1580: [(set (match_operand:QI 0 "general_operand" "=q")
1581: (leu (cc0) (const_int 0)))]
1582: ""
1583: "* cc_status = cc_prev_status;
1584: return \"setbe %0\"; ")
1585:
1586: ;; Basic conditional jump instructions.
1587: ;; We ignore the overflow flag for signed branch instructions.
1588:
1589: (define_insn "beq"
1590: [(set (pc)
1591: (if_then_else (eq (cc0)
1592: (const_int 0))
1593: (label_ref (match_operand 0 "" ""))
1594: (pc)))]
1595: ""
1596: "je %l0")
1597:
1598: (define_insn "bne"
1599: [(set (pc)
1600: (if_then_else (ne (cc0)
1601: (const_int 0))
1602: (label_ref (match_operand 0 "" ""))
1603: (pc)))]
1604: ""
1605: "jne %l0")
1606:
1607: (define_insn "bgt"
1608: [(set (pc)
1609: (if_then_else (gt (cc0)
1610: (const_int 0))
1611: (label_ref (match_operand 0 "" ""))
1612: (pc)))]
1613: ""
1614: "*OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0)")
1615:
1616: (define_insn "bgtu"
1617: [(set (pc)
1618: (if_then_else (gtu (cc0)
1619: (const_int 0))
1620: (label_ref (match_operand 0 "" ""))
1621: (pc)))]
1622: ""
1623: "ja %l0")
1624:
1.1.1.3 root 1625: ;; There is no jump insn to check for `<' on IEEE floats.
1626: ;; Page 17-80 in the 80387 manual says jb, but that's wrong;
1627: ;; jb checks for `not >='. So swap the operands and do `>'.
1628: (define_expand "blt"
1629: [(set (pc)
1630: (if_then_else (lt (cc0)
1631: (const_int 0))
1632: (label_ref (match_operand 0 "" ""))
1633: (pc)))]
1634: ""
1635: "
1636: {
1637: extern rtx sequence_stack;
1638: rtx prev = XEXP (XEXP (sequence_stack, 1), 0);
1639: rtx body = PATTERN (prev);
1640: rtx comp;
1641: if (GET_CODE (body) == SET)
1642: comp = SET_SRC (body);
1643: else
1644: comp = SET_SRC (XVECEXP (body, 0, 0));
1645:
1646: if (GET_CODE (comp) == COMPARE
1647: ? GET_MODE_CLASS (GET_MODE (XEXP (comp, 0))) == MODE_FLOAT
1648: : GET_MODE_CLASS (GET_MODE (comp)) == MODE_FLOAT)
1649: {
1650: if (GET_CODE (comp) == COMPARE)
1651: {
1652: rtx op0 = XEXP (comp, 0);
1653: rtx op1 = XEXP (comp, 1);
1654: XEXP (comp, 0) = op1;
1655: XEXP (comp, 1) = op0;
1656: }
1657: else
1658: {
1659: rtx new = gen_rtx (COMPARE, VOIDmode,
1660: CONST0_RTX (GET_MODE (comp)), comp);
1661: if (GET_CODE (body) == SET)
1662: SET_SRC (body) = new;
1663: else
1664: SET_SRC (XVECEXP (body, 0, 0)) = new;
1665: }
1666: emit_insn (gen_bgt (operands[0]));
1667: DONE;
1668: }
1669: }")
1670:
1671: (define_insn ""
1.1 root 1672: [(set (pc)
1673: (if_then_else (lt (cc0)
1674: (const_int 0))
1675: (label_ref (match_operand 0 "" ""))
1676: (pc)))]
1677: ""
1678: "*OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\")")
1679:
1680: (define_insn "bltu"
1681: [(set (pc)
1682: (if_then_else (ltu (cc0)
1683: (const_int 0))
1684: (label_ref (match_operand 0 "" ""))
1685: (pc)))]
1686: ""
1687: "jb %l0")
1688:
1689: (define_insn "bge"
1690: [(set (pc)
1691: (if_then_else (ge (cc0)
1692: (const_int 0))
1693: (label_ref (match_operand 0 "" ""))
1694: (pc)))]
1695: ""
1696: "*OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\")")
1697:
1698: (define_insn "bgeu"
1699: [(set (pc)
1700: (if_then_else (geu (cc0)
1701: (const_int 0))
1702: (label_ref (match_operand 0 "" ""))
1703: (pc)))]
1704: ""
1705: "jae %l0")
1706:
1.1.1.3 root 1707: ;; See comment on `blt', above.
1708: (define_expand "ble"
1709: [(set (pc)
1710: (if_then_else (le (cc0)
1711: (const_int 0))
1712: (label_ref (match_operand 0 "" ""))
1713: (pc)))]
1714: ""
1715: "
1716: {
1717: extern rtx sequence_stack;
1718: rtx prev = XEXP (XEXP (sequence_stack, 1), 0);
1719: rtx body = PATTERN (prev);
1720: rtx comp;
1721: if (GET_CODE (body) == SET)
1722: comp = SET_SRC (body);
1723: else
1724: comp = SET_SRC (XVECEXP (body, 0, 0));
1725:
1726: if (GET_CODE (comp) == COMPARE
1727: ? GET_MODE_CLASS (GET_MODE (XEXP (comp, 0))) == MODE_FLOAT
1728: : GET_MODE_CLASS (GET_MODE (comp)) == MODE_FLOAT)
1729: {
1730: if (GET_CODE (comp) == COMPARE)
1731: {
1732: rtx op0 = XEXP (comp, 0);
1733: rtx op1 = XEXP (comp, 1);
1734: XEXP (comp, 0) = op1;
1735: XEXP (comp, 1) = op0;
1736: }
1737: else
1738: {
1739: rtx new = gen_rtx (COMPARE, VOIDmode,
1740: CONST0_RTX (GET_MODE (comp)), comp);
1741: if (GET_CODE (body) == SET)
1742: SET_SRC (body) = new;
1743: else
1744: SET_SRC (XVECEXP (body, 0, 0)) = new;
1745: }
1746: emit_insn (gen_bge (operands[0]));
1747: DONE;
1748: }
1749: }")
1750:
1751: (define_insn ""
1.1 root 1752: [(set (pc)
1753: (if_then_else (le (cc0)
1754: (const_int 0))
1755: (label_ref (match_operand 0 "" ""))
1756: (pc)))]
1757: ""
1758: "*OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0) ")
1759:
1760: (define_insn "bleu"
1761: [(set (pc)
1762: (if_then_else (leu (cc0)
1763: (const_int 0))
1764: (label_ref (match_operand 0 "" ""))
1765: (pc)))]
1766: ""
1767: "jbe %l0")
1768:
1769: ;; Negated conditional jump instructions.
1770:
1771: (define_insn ""
1772: [(set (pc)
1773: (if_then_else (eq (cc0)
1774: (const_int 0))
1775: (pc)
1776: (label_ref (match_operand 0 "" ""))))]
1777: ""
1778: "jne %l0")
1779:
1780: (define_insn ""
1781: [(set (pc)
1782: (if_then_else (ne (cc0)
1783: (const_int 0))
1784: (pc)
1785: (label_ref (match_operand 0 "" ""))))]
1786: ""
1787: "je %l0")
1788:
1789: (define_insn ""
1790: [(set (pc)
1791: (if_then_else (gt (cc0)
1792: (const_int 0))
1793: (pc)
1794: (label_ref (match_operand 0 "" ""))))]
1795: ""
1796: "*OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0) ")
1797:
1798: (define_insn ""
1799: [(set (pc)
1800: (if_then_else (gtu (cc0)
1801: (const_int 0))
1802: (pc)
1803: (label_ref (match_operand 0 "" ""))))]
1804: ""
1805: "jbe %l0")
1806:
1807: (define_insn ""
1808: [(set (pc)
1809: (if_then_else (lt (cc0)
1810: (const_int 0))
1811: (pc)
1812: (label_ref (match_operand 0 "" ""))))]
1813: ""
1814: "*OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\")
1815: ")
1816:
1817: (define_insn ""
1818: [(set (pc)
1819: (if_then_else (ltu (cc0)
1820: (const_int 0))
1821: (pc)
1822: (label_ref (match_operand 0 "" ""))))]
1823: ""
1824: "jae %l0")
1825:
1826: (define_insn ""
1827: [(set (pc)
1828: (if_then_else (ge (cc0)
1829: (const_int 0))
1830: (pc)
1831: (label_ref (match_operand 0 "" ""))))]
1832: ""
1833: "*OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\")")
1834:
1835: (define_insn ""
1836: [(set (pc)
1837: (if_then_else (geu (cc0)
1838: (const_int 0))
1839: (pc)
1840: (label_ref (match_operand 0 "" ""))))]
1841: ""
1842: "jb %l0")
1843:
1844: (define_insn ""
1845: [(set (pc)
1846: (if_then_else (le (cc0)
1847: (const_int 0))
1848: (pc)
1849: (label_ref (match_operand 0 "" ""))))]
1850: ""
1851: "*OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0)")
1852:
1853: (define_insn ""
1854: [(set (pc)
1855: (if_then_else (leu (cc0)
1856: (const_int 0))
1857: (pc)
1858: (label_ref (match_operand 0 "" ""))))]
1859: ""
1860: "ja %l0")
1861:
1862: ;; Unconditional and other jump instructions
1863: (define_insn "jump"
1864: [(set (pc)
1865: (label_ref (match_operand 0 "" "")))]
1866: ""
1867: "jmp %l0")
1868:
1869: (define_insn "tablejump"
1870: [(set (pc) (match_operand:SI 0 "general_operand" "rm"))
1871: (use (label_ref (match_operand 1 "" "")))]
1872: ""
1873: "*
1874: {
1875: CC_STATUS_INIT;
1876:
1877: return \"jmp %*%0\";
1878: }")
1879:
1880: /*
1881: (define_insn ""
1882: [(set (pc)
1883: (if_then_else
1884: (ne (compare (minus:HI (match_operand:HI 0 "general_operand" "c")
1885: (const_int 1))
1886: (const_int -1))
1887: (const_int 0))
1888: (label_ref (match_operand 1 "" "g"))
1889: (pc)))
1890: (set (match_dup 0)
1891: (minus:HI (match_dup 0)
1892: (const_int 1)))]
1893: ""
1894: "loop %l1")
1895:
1896: (define_insn ""
1897: [(set (pc)
1898: (if_then_else
1899: (ne (compare (const_int -1)
1900: (minus:SI (match_operand:SI 0 "general_operand" "c")
1901: (const_int 1)))
1902: (const_int 0))
1903: (label_ref (match_operand 1 "" "g"))
1904: (pc)))
1905: (set (match_dup 0)
1906: (minus:SI (match_dup 0)
1907: (const_int 1)))]
1908: ""
1909: "loop %l1")
1910: */
1911:
1912: ;; Call subroutine returning no value.
1913: (define_insn "call"
1914: [(call (match_operand:QI 0 "indirect_operand" "m")
1915: (match_operand:SI 1 "general_operand" "g"))]
1916: ;; Operand 1 not really used on the m68000.
1917: ""
1918: "*
1919: {
1920: if (GET_CODE (operands[0]) == MEM
1921: && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
1922: {
1923: operands[0] = XEXP (operands[0], 0);
1924: return \"call %*%0\";
1925: }
1926: else
1927: return \"call %0\";
1928: }")
1929:
1930: ;; Call subroutine, returning value in operand 0
1931: ;; (which must be a hard register).
1932: (define_insn "call_value"
1933: [(set (match_operand 0 "" "=rf")
1934: (call (match_operand:QI 1 "indirect_operand" "m")
1935: (match_operand:SI 2 "general_operand" "g")))]
1936: ;; Operand 2 not really used on the m68000.
1937: ""
1938: "*
1939: {
1940: if (GET_CODE (operands[1]) == MEM
1941: && ! CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
1942: {
1943: operands[1] = XEXP (operands[1], 0);
1944: output_asm_insn (\"call %*%1\", operands);
1945: }
1946: else
1947: output_asm_insn (\"call %1\", operands);
1948:
1949: if (GET_MODE (operands[0]) == DFmode
1950: || GET_MODE (operands[0]) == SFmode)
1951: {
1952: /* fp_pop_level++; */
1953: /* pop if reg dead */
1954: if (!FP_REG_P (operands[0]))
1955: abort ();
1956: if (top_dead_p (insn))
1957: {
1958: POP_ONE_FP;
1959: }
1960: }
1961: RET;
1962: }")
1963:
1964: (define_insn "nop"
1965: [(const_int 0)]
1966: ""
1967: "nop")
1968:
1969: ;;- Local variables:
1970: ;;- mode:emacs-lisp
1971: ;;- comment-start: ";;- "
1972: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
1973: ;;- eval: (modify-syntax-entry ?[ "(]")
1974: ;;- eval: (modify-syntax-entry ?] ")[")
1975: ;;- eval: (modify-syntax-entry ?{ "(}")
1976: ;;- eval: (modify-syntax-entry ?} "){")
1977: ;;- End:
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