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1.1 root 1: ;; GCC machine description for Intel 80386.
2: ;; Copyright (C) 1988 Free Software Foundation, Inc.
3: ;; Mostly by William Schelter.
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 1, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21:
22: ;;- instruction definitions
23:
24: ;;- @@The original PO technology requires these to be ordered by speed,
25: ;;- @@ so that assigner will pick the fastest.
26:
27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28:
29: ;;- When naming insn's (operand 0 of define_insn) be careful about using
30: ;;- names from other targets machine descriptions.
31:
32: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
33: ;;- updates for most instructions.
34:
35: ;;- Operand classes for the register allocator:
36: ;;- 'a' for eax
37: ;;- 'd' for edx
38: ;;- 'c' for ecx
39: ;;- 'b' for ebx
40: ;;- 'f' for anything in FLOAT_REGS
41: ;;- 'r' any (non-floating-point) register
42: ;;- 'q' regs that allow byte operations (A, B, C and D)
43: ;;- 'A' A and D registers
44:
45: ;; the special asm out single letter directives following a '%' are:
46: ;; 'z' mov%z1 would be movl, movw, or movb depending on the mode of operands[1]
47: ;; 's' output a '*'
48: ;; 'w' If the operand is a REG, it uses the mode size to determine the
49: ;; printing of the reg
50:
51:
52: ;; Put tstsi first among test insns so it matches a CONST_INT operand.
53:
54: (define_insn "tstsi"
55: [(set (cc0)
56: (match_operand:SI 0 "general_operand" "rm"))]
57: ""
58: "*
59: {
60: operands[1] = const0_rtx;
61: if (REG_P (operands[0]))
62: return AS2 (test%L0,%0,%0);
63: return AS2 (cmp%L0,%1,%0);
64: }")
65:
66: (define_insn "tsthi"
67: [(set (cc0)
68: (match_operand:HI 0 "general_operand" "rm"))]
69: ""
70: "*
71: {
72: operands[1] = const0_rtx;
73: if (REG_P (operands[0]))
74: return AS2 (test%W0,%0,%0);
75: return AS2 (cmp%W0,%1,%0);
76: }")
77:
78: (define_insn "tstqi"
79: [(set (cc0)
80: (match_operand:QI 0 "general_operand" "qm"))]
81: ""
82: "*
83: {
84: operands[1] = const0_rtx;
85: if (REG_P (operands[0]))
86: return AS2 (test%B0,%0,%0);
87: return AS2 (cmp%B0,%1,%0);
88: }")
89:
90: (define_insn "tstsf"
91: [(set (cc0)
92: (match_operand:SF 0 "general_operand" "rm,f"))
1.1.1.3 root 93: (clobber (reg:SI 0))]
1.1 root 94: "TARGET_80387"
95: "*
96: {
97: rtx xops[1];
98: if (!FP_REG_P (operands[0]))
99: fp_push_sf (operands[0]);
100: /* fp_pop_level--; */
101: xops[0] = FP_TOP;
102: cc_status.flags |= CC_IN_80387;
103: if (FP_REG_P (operands[0]) && ! top_dead_p (insn))
104: output_asm_insn (\"ftst\;fnstsw %R0ax\;sahf\", xops);
105: else
106: output_asm_insn (\"ftst\;fstp %0(0)\;fnstsw %R0ax\;sahf\", xops);
107: RETCOM (testsf);
108: }")
109:
110: (define_insn "tstdf"
111: [(set (cc0)
112: (match_operand:DF 0 "general_operand" "rm,f"))
1.1.1.3 root 113: (clobber (reg:SI 0))
1.1 root 114: ]
115: "TARGET_80387"
116: "*
117: {
118: rtx xops[1];
119: if (!FP_REG_P (operands[0]))
120: fp_push_df (operands[0]);
121: /* fp_pop_level--; */
122: xops[0] = FP_TOP;
123: cc_status.flags |= CC_IN_80387;
124: if (FP_REG_P (operands[0]) && ! top_dead_p (insn))
125: output_asm_insn (\"ftst\;fnstsw %R0ax\;sahf\", xops);
126: else
127: output_asm_insn (\"ftst\;fstp %0(0)\;fnstsw %R0ax\;sahf\", xops);
128: RETCOM (testdf);
129: }")
130:
131: ;;- compare instructions
132:
133: ;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
134:
135: (define_insn "cmpsi"
136: [(set (cc0)
137: (compare (match_operand:SI 0 "general_operand" "mr,ri")
138: (match_operand:SI 1 "general_operand" "ri,mr")))]
139: ""
140: "*
141: {
142: if (REG_P (operands[1])
143: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
144: {
145: cc_status.flags |= CC_REVERSED;
146: return AS2 (cmp%L0,%0,%1);
147: }
148: return AS2 (cmp%L0,%1,%0);
149: }")
150:
151: (define_insn "cmphi"
152: [(set (cc0)
153: (compare (match_operand:HI 0 "general_operand" "mr,ri")
154: (match_operand:HI 1 "general_operand" "ri,mr")))]
155: ""
156: "*
157: {
158: if (REG_P (operands[1])
159: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
160: {
161: cc_status.flags |= CC_REVERSED;
162: return AS2 (cmp%W0,%0,%1);
163: }
164: return AS2 (cmp%W0,%1,%0);
165: }")
166:
167: (define_insn "cmpqi"
168: [(set (cc0)
169: (compare (match_operand:QI 0 "general_operand" "qn,mq")
170: (match_operand:QI 1 "general_operand" "qm,nq")))]
171: ""
172: "*
173: {
174: if (REG_P (operands[1])
175: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
176: {
177: cc_status.flags |= CC_REVERSED;
178: return AS2 (cmp%B0,%0,%1);
179: }
180: return AS2 (cmp%B0,%1,%0);
181: }")
182:
183: (define_insn "cmpdf"
184: [(set (cc0)
185: (compare (match_operand:DF 0 "general_operand" "m,f*r,m,f,r,!*r")
186: (match_operand:DF 1 "general_operand" "m,m,f*r,r,f,*r")))
187: (clobber (reg:SI 0))]
188: "TARGET_80387"
189: "*
190: {
191: if (FP_REG_P (operands[0]))
192: {
193: rtx tem = operands[1];
194: operands[1] = operands[0];
195: operands[0] = tem;
196: cc_status.flags |= CC_REVERSED;
197: }
198: if (! FP_REG_P (operands[1]))
199: output_movdf (FP_TOP, operands[1]);
200: output_movdf (FP_TOP, operands[0]);
201: /* fp_pop_level--;
202: fp_pop_level--; */
203: cc_status.flags |= CC_IN_80387;
204: return \"fcompp\;fnstsw %R0ax\;sahf\";
205: }")
206:
207: (define_insn "cmpsf"
208: [(set (cc0)
209: (compare (match_operand:SF 0 "general_operand" "m,f*r,m,f,r,!*r")
210: (match_operand:SF 1 "general_operand" "m,m,f*r,r,f,*r")))
211: (clobber (reg:SI 0))]
212: "TARGET_80387"
213: "*
214: {
215: if (FP_REG_P (operands[0]))
216: {
217: rtx tem = operands[1];
218: operands[1] = operands[0];
219: operands[0] = tem;
220: cc_status.flags |= CC_REVERSED;
221: }
222: if (! FP_REG_P (operands[1]))
223: output_movsf (FP_TOP, operands[1]);
224: output_movsf (FP_TOP, operands[0]);
225: /* fp_pop_level--;
226: fp_pop_level--; */
227: cc_status.flags |= CC_IN_80387;
228: return \"fcompp\;fnstsw %R0ax\;sahf\";
229: }")
230:
231: ;; logical compare
232: (define_insn ""
233: [(set (cc0)
234: (and:SI (match_operand:SI 0 "general_operand" "rm,ri")
235: (match_operand:SI 1 "general_operand" "ri,rm")))]
236: ""
237: "*
238: {
1.1.1.3 root 239: if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
1.1 root 240: return AS2 (test%L0,%1,%0);
241: return AS2 (test%L0,%0,%1);
242: }")
243:
244: (define_insn ""
245: [(set (cc0)
246: (and:HI (match_operand:HI 0 "general_operand" "rm,ri")
247: (match_operand:HI 1 "general_operand" "ri,rm")))]
248: ""
249: "*
250: {
1.1.1.3 root 251: if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
1.1 root 252: return AS2 (test%W0,%1,%0);
253: return AS2 (test%W0,%0,%1);
254: }")
255:
256: (define_insn ""
257: [(set (cc0)
258: (and:QI (match_operand:QI 0 "general_operand" "qm,qi")
259: (match_operand:QI 1 "general_operand" "qi,qm")))]
260: ""
261: "*
262: {
1.1.1.3 root 263: if (CONSTANT_P (operands[1]) || GET_CODE (operands[0]) == MEM)
1.1 root 264: return AS2 (test%B0,%1,%0);
265: return AS2 (test%B0,%0,%1);
266: }")
267:
268: ;; move instructions.
269: ;; There is one for each machine mode,
270: ;; and each is preceded by a corresponding push-insn pattern
271: ;; (since pushes are not general_operands on the 386).
272:
273: (define_insn ""
274: [(set (match_operand:SI 0 "push_operand" "=<")
275: (match_operand:SI 1 "general_operand" "g"))]
276: ""
277: "push%L0 %1")
278:
279: ;; General case of fullword move.
280: (define_insn "movsi"
281: [(set (match_operand:SI 0 "general_operand" "=g,r")
282: (match_operand:SI 1 "general_operand" "ri,m"))]
283: ""
284: "*
285: {
286: rtx link;
287: if (operands[1] == const0_rtx && REG_P (operands[0]))
288: return \"xor%L0 %0,%0\";
289: if (operands[1] == const1_rtx
290: && (link = find_reg_note (insn, REG_WAS_0, 0))
291: /* Make sure the insn that stored the 0 is still present. */
292: && ! XEXP (link, 0)->volatil
293: && GET_CODE (XEXP (link, 0)) != NOTE
294: /* Make sure cross jumping didn't happen here. */
295: && no_labels_between_p (XEXP (link, 0), insn))
296: /* Fastest way to change a 0 to a 1. */
297: return \"inc%L0 %0\";
298: return \"mov%L0 %1,%0\";
299: }")
300:
301: (define_insn ""
302: [(set (match_operand:HI 0 "push_operand" "=<")
303: (match_operand:HI 1 "general_operand" "g"))]
304: ""
305: "push%W0 %1")
306:
307: (define_insn "movhi"
308: [(set (match_operand:HI 0 "general_operand" "=g,r")
309: (match_operand:HI 1 "general_operand" "ri,m"))]
310: ""
311: "*
312: {
313: rtx link;
314: if (operands[1] == const0_rtx && REG_P (operands[0]))
315: return \"xor%W0 %0,%0\";
316: if (operands[1] == const1_rtx
317: && (link = find_reg_note (insn, REG_WAS_0, 0))
318: /* Make sure the insn that stored the 0 is still present. */
319: && ! XEXP (link, 0)->volatil
320: && GET_CODE (XEXP (link, 0)) != NOTE
321: /* Make sure cross jumping didn't happen here. */
322: && no_labels_between_p (XEXP (link, 0), insn))
323: /* Fastest way to change a 0 to a 1. */
324: return \"inc%W0 %0\";
325: return \"mov%W0 %1,%0\";
326: }")
327:
328: ;; emit_push_insn when it calls move_by_pieces
329: ;; requires an insn to "push a byte".
330: ;; But actually we use pushw, which has the effect of rounding
331: ;; the amount pushed up to a halfword.
332: (define_insn ""
333: [(set (match_operand:QI 0 "push_operand" "=<")
334: (match_operand:QI 1 "general_operand" "q"))]
335: ""
336: "*
337: {
338: operands[1] = gen_rtx (REG, HImode, REGNO (operands[1]));
339: return \"push%W0 %1\";
340: }")
341:
342: (define_insn "movqi"
343: [(set (match_operand:QI 0 "general_operand" "=q,*r,m")
344: (match_operand:QI 1 "general_operand" "*g,q,qi"))]
345: ""
346: "*
347: {
348: rtx link;
349: if (operands[1] == const0_rtx && REG_P (operands[0]))
350: return \"xor%B0 %0,%0\";
351: if (operands[1] == const1_rtx
352: && (link = find_reg_note (insn, REG_WAS_0, 0))
353: /* Make sure the insn that stored the 0 is still present. */
354: && ! XEXP (link, 0)->volatil
355: && GET_CODE (XEXP (link, 0)) != NOTE
356: /* Make sure cross jumping didn't happen here. */
357: && no_labels_between_p (XEXP (link, 0), insn))
358: /* Fastest way to change a 0 to a 1. */
359: return \"inc%B0 %0\";
360: /* If mov%B0 isn't allowed for one of these regs, use mov%W0. */
361: if (NON_QI_REG_P (operands[0]) || NON_QI_REG_P (operands[1]))
362: return (AS2 (mov%W0,%w1,%w0));
363: return (AS2 (mov%B0,%1,%0));
364: }")
365:
366: ; I suspect nothing can ever match this ???
367: ;(define_insn ""
368: ; [(set (match_operand:SF 0 "general_operand" "rm")
369: ; (match_operand:SF 1 "general_operand" "f"))
370: ; (clobber (reg:SF 8))]
371: ; ""
372: ; "*
373: ;{
374: ; output_asm_insn ("???", operands);
375: ; fpop_sf (operands[0]);
376: ; RETCOM (movsf_clobber);
377: ;}")
378:
379: (define_insn ""
380: [(set (match_operand:SF 0 "push_operand" "=<,<")
381: (match_operand:SF 1 "general_operand" "gF,f"))]
382: ""
383: "*
384: {
385: if (FP_REG_P (operands[1]))
386: {
387: rtx xops[3];
388: xops[0] = AT_SP (SFmode);
389: xops[1] = gen_rtx (CONST_INT, VOIDmode, 4);
390: xops[2] = stack_pointer_rtx;
391: /* fp_pop_level--; */
392: output_asm_insn (AS2 (sub%L0,%1,%2), xops);
1.1.1.2 root 393: if (top_dead_p (insn))
394: output_asm_insn (\"fstp%S0 %0\", xops);
395: else
1.1.1.4 root 396: output_asm_insn (\"fst%S0 %0\", xops);
1.1 root 397: RET;
398: }
399: return \"push%L0 %1\";
400: }")
401:
402: (define_insn "movsf"
1.1.1.4 root 403: ;; `rf' is duplicated in the second alternative
404: ;; to make sure an optional reload is generated
405: ;; for the memref in operand 0. Otherwise
406: ;; we could use too many hard regs.
407: [(set (match_operand:SF 0 "general_operand" "=rf,mrf,!rm")
408: (match_operand:SF 1 "general_operand" "mrf,rf,F"))]
1.1 root 409: ""
410: "*
411: {
412: if (FP_REG_P (operands[1])
413: && !FP_REG_P (operands[0])
414: && !top_dead_p (insn))
415: fp_store_sf (operands[0]);
416: else
417: output_movsf (operands[0], operands[1]);
418: RETCOM (movsf);
419: }")
420:
421: ;;should change to handle the memory operands[1] without doing df push..
422: (define_insn ""
423: [(set (match_operand:DF 0 "push_operand" "=<,<")
424: (match_operand:DF 1 "general_operand" "gF,f"))]
425: ""
426: "*
427: {
428: if (FP_REG_P (operands[1]))
429: {
430: rtx xops[3];
431: xops[0] = AT_SP (DFmode);
432: xops[1] = gen_rtx (CONST_INT, VOIDmode, 8);
433: xops[2] = stack_pointer_rtx;
434: /* fp_pop_level--; */
435: output_asm_insn (AS2 (sub%L0,%1,%2), xops);
1.1.1.2 root 436: if (top_dead_p(insn))
437: output_asm_insn (\"fstp%Q0 %0\", xops);
438: else
439: output_asm_insn (\"fst%Q0 %0\", xops);
1.1 root 440: RETCOM (pushdf);
441: }
442: else
443: return output_move_double (operands);
444: }")
445:
446: (define_insn "movdf"
1.1.1.4 root 447: [(set (match_operand:DF 0 "general_operand" "=rmf,&fr,!rm")
448: ;; `rf' is duplicated in the second alternative
449: ;; to make sure that optional reloads are generated
450: ;; for the memory reference in operand 1.
451: (match_operand:DF 1 "general_operand" "fr,mrf,F"))]
1.1 root 452: ""
453: "*
454: {
455: if (FP_REG_P (operands[1])
456: && ! FP_REG_P (operands[0])
457: && ! top_dead_p (insn))
458: fp_store_df (operands[0]);
459: else
460: output_movdf (operands[0], operands[1]);
461: RETCOM (movdf);
462: }")
463:
464: (define_insn ""
465: [(set (match_operand:DI 0 "push_operand" "=<")
466: (match_operand:DI 1 "general_operand" "roiF"))]
467: ""
468: "*
469: {
470: return output_move_double (operands);
471: }")
472:
473: (define_insn "movdi"
474: [(set (match_operand:DI 0 "general_operand" "=&r,rm")
475: (match_operand:DI 1 "general_operand" "m,riF"))]
476: ""
477: "*
478: {
479: return output_move_double (operands);
480: }")
481:
482: ;; These go after the move instructions
483: ;; because the move instructions are better (require no spilling)
484: ;; when they can apply. But these go before the add and subtract insns
485: ;; because it is often shorter to use these when both apply.
486:
487: ;Lennart Augustsson <[email protected]>
488: ;says this pattern just makes slower code:
489: ; pushl %ebp
490: ; addl $-80,(%esp)
491: ;instead of
492: ; leal -80(%ebp),%eax
493: ; pushl %eax
494: ;
495: ;(define_insn ""
496: ; [(set (match_operand:SI 0 "push_operand" "=<")
497: ; (plus:SI (match_operand:SI 1 "general_operand" "%r")
498: ; (match_operand:SI 2 "general_operand" "ri")))]
499: ; ""
500: ; "*
501: ;{
502: ; rtx xops[4];
503: ; xops[0] = operands[0];
504: ; xops[1] = operands[1];
505: ; xops[2] = operands[2];
506: ; xops[3] = gen_rtx (MEM, SImode, stack_pointer_rtx);
507: ; output_asm_insn (\"push%z1 %1\", xops);
508: ; output_asm_insn (AS2 (add%z3,%2,%3), xops);
509: ; RET;
510: ;}")
511:
512: (define_insn ""
513: [(set (match_operand:SI 0 "general_operand" "=g")
514: (plus:SI (match_operand:SI 1 "general_operand" "0")
515: (const_int 1)))]
516: ""
517: "inc%L0 %0")
518:
519: (define_insn ""
520: [(set (match_operand:SI 0 "general_operand" "=g")
521: (plus:SI (match_operand:SI 1 "general_operand" "0")
522: (const_int -1)))]
523: ""
524: "dec%L0 %0")
525:
526: (define_insn ""
527: [(set (match_operand:SI 0 "general_operand" "=g")
528: (minus:SI (match_operand:SI 1 "general_operand" "0")
529: (const_int 1)))]
530: ""
531: "dec%L0 %0")
532:
533: (define_insn ""
534: [(set (match_operand:SI 0 "register_operand" "=r")
535: (match_operand:QI 1 "address_operand" "p"))]
536: ""
537: "*
538: {
539: CC_STATUS_INIT;
540: /* Adding a constant to a register is faster with an add. */
541: if (GET_CODE (operands[1]) == PLUS
542: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
543: && rtx_equal_p (operands[0], XEXP (operands[1], 0)))
544: {
545: operands[1] = XEXP (operands[1], 1);
546: return AS2 (add%L0,%1,%0);
547: }
548: return \"lea%L0 %a1,%0\";
549: }")
550:
551: ;;- conversion instructions
552: ;;- NONE
553:
554: ;;- truncation instructions
555: (define_insn "truncsiqi2"
1.1.1.3 root 556: [(set (match_operand:QI 0 "general_operand" "=q,m")
1.1 root 557: (truncate:QI
1.1.1.3 root 558: (match_operand:SI 1 "general_operand" "qim,qn")))]
1.1 root 559: ""
1.1.1.3 root 560: "*
561: {
562: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
563: return \"mov%L0 %1,%k0\";
564: return \"mov%B0 %b1,%0\";
565: }")
1.1 root 566:
567: (define_insn "trunchiqi2"
1.1.1.3 root 568: [(set (match_operand:QI 0 "general_operand" "=q,m")
1.1 root 569: (truncate:QI
1.1.1.3 root 570: (match_operand:HI 1 "general_operand" "qim,qn")))]
1.1 root 571: ""
1.1.1.3 root 572: "*
573: {
574: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
575: return \"mov%W0 %1,%w0\";
576: return \"mov%B0 %b1,%0\";
577: }")
1.1 root 578:
579: (define_insn "truncsihi2"
1.1.1.3 root 580: [(set (match_operand:HI 0 "general_operand" "=r,m")
1.1 root 581: (truncate:HI
1.1.1.3 root 582: (match_operand:SI 1 "general_operand" "rim,rn")))]
1.1 root 583: ""
1.1.1.3 root 584: "*
585: {
586: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
587: return \"mov%L0 %1,%k0\";
588: return \"mov%W0 %w1,%0\";
589: }")
1.1 root 590:
591: ;;- zero extension instructions
592: ;; Note that the one starting from HImode comes before those for QImode
593: ;; so that a constant operand will match HImode, not QImode.
594:
595: (define_insn "zero_extendhisi2"
596: [(set (match_operand:SI 0 "general_operand" "=r")
597: (zero_extend:SI
598: (match_operand:HI 1 "general_operand" "rm")))]
599: ""
600: "movz%W0%L0 %1,%0")
601:
602: (define_insn "zero_extendqihi2"
603: [(set (match_operand:HI 0 "general_operand" "=r")
604: (zero_extend:HI
605: (match_operand:QI 1 "general_operand" "qm")))]
606: ""
607: "movz%B0%W0 %1,%0")
608:
609: (define_insn "zero_extendqisi2"
610: [(set (match_operand:SI 0 "general_operand" "=r")
611: (zero_extend:SI
612: (match_operand:QI 1 "general_operand" "qm")))]
613: ""
614: "movz%B0%L0 %1,%0")
615:
616: ;;- sign extension instructions
617: ;; Note that the one starting from HImode comes before those for QImode
618: ;; so that a constant operand will match HImode, not QImode.
619:
620: /*
621: (define_insn "extendsidi2"
622: [(set (match_operand:DI 0 "general_operand" "=a")
623: (sign_extend:DI
624: (match_operand:SI 1 "general_operand" "a")))]
625: ""
626: "clq")
627: */
628:
1.1.1.3 root 629: ;; Note that the i386 programmers' manual says that the opcodes
630: ;; are named movsx..., but the assembler on Unix does not accept that.
631: ;; We use what the Unix assembler expects.
632:
1.1 root 633: (define_insn "extendhisi2"
634: [(set (match_operand:SI 0 "general_operand" "=r")
635: (sign_extend:SI
636: (match_operand:HI 1 "general_operand" "rm")))]
637: ""
638: "movs%W0%L0 %1,%0")
639:
640: (define_insn "extendqihi2"
641: [(set (match_operand:HI 0 "general_operand" "=r")
642: (sign_extend:HI
643: (match_operand:QI 1 "general_operand" "qm")))]
644: ""
645: "movs%B0%W0 %1,%0")
646:
647: (define_insn "extendqisi2"
648: [(set (match_operand:SI 0 "general_operand" "=r")
649: (sign_extend:SI
650: (match_operand:QI 1 "general_operand" "qm")))]
651: ""
652: "movs%B0%L0 %1,%0"
653: )
654:
655: ;; Conversions between float and double.
656:
657: (define_insn "extendsfdf2"
658: [(set (match_operand:DF 0 "general_operand" "=fm,f,fm,fm")
659: (float_extend:DF
660: (match_operand:SF 1 "general_operand" "m,0,f,!*r")))]
661: "TARGET_80387"
662: "*
663: {
664: if (FP_REG_P (operands[0]))
665: {
666: output_movsf (operands[0], operands[1]);
667: RET;
668: }
669: if (FP_REG_P (operands[1]))
670: {
671: if (top_dead_p (insn))
672: fp_pop_df (operands[0]);
673: else
674: fp_store_df (operands[0]);
675: RET;
676: }
677: output_movsf (FP_TOP, operands[1]);
678: fp_pop_df (operands[0]);
679: RETCOM (extendsfdf2);
680: }")
681:
682: ;; This cannot output into an f-reg because there is no way to be
683: ;; sure of truncating in that case.
684: (define_insn "truncdfsf2"
685: [(set (match_operand:SF 0 "general_operand" "=m,!*r")
686: (float_truncate:SF
687: (match_operand:DF 1 "general_operand" "f,f")))]
688: "TARGET_80387"
689: "*
690: {
691: if (top_dead_p (insn))
692: fp_pop_sf (operands[0]);
693: else
694: fp_store_sf (operands[0]);
695: RETCOM (truncdfsf2);
696: }")
697:
698: ;; Conversion between fixed point and floating point.
699: ;; Note that among the fix-to-float insns
700: ;; the ones that start with SImode come first.
701: ;; That is so that an operand that is a CONST_INT
702: ;; (and therefore lacks a specific machine mode).
703: ;; will be recognized as SImode (which is always valid)
704: ;; rather than as QImode or HImode. The 80387 would not know
705: ;; what to do with the smaller sizes anyway. (I think).
706:
707: (define_insn "floatsisf2"
708: [(set (match_operand:SF 0 "general_operand" "=fm,fm")
709: (float:SF (match_operand:SI 1 "general_operand" "m,!*r")))]
710: "TARGET_80387"
711: "*
712: {
713: /* fp_pop_level++; */
714:
715: if (GET_CODE (operands[1]) != MEM)
716: {
717: rtx xops[2];
718: output_asm_insn (\"push%L0 %1\", operands);
719: operands[1] = AT_SP (SImode);
720: output_asm_insn (\"fild%L0 %1\", operands);
721: xops[0] = stack_pointer_rtx;
722: xops[1] = gen_rtx (CONST_INT, VOIDmode, 4);
723: output_asm_insn (AS2 (add%L0,%1,%0), xops);
724: }
725: else
726: output_asm_insn (\"fild%L0 %1\", operands);
727:
728: if (! FP_REG_P (operands[0]))
729: {
730: /* fp_pop_level--; */
731: return \"fstp%S0 %0\";
732: }
733: RET;
734: }")
735:
736: (define_insn "floatsidf2"
737: [(set (match_operand:DF 0 "general_operand" "=fm,fm")
738: (float:DF (match_operand:SI 1 "general_operand" "m,!*r")))]
739: "TARGET_80387"
740: "*
741: {
742: /* fp_pop_level++; */
743: if (GET_CODE (operands[1]) != MEM)
744: {
745: rtx xops[2];
746: output_asm_insn (\"push%L0 %1\", operands);
747: operands[1] = AT_SP (SImode);
748: output_asm_insn (\"fild%L0 %1\", operands);
749: xops[0] = stack_pointer_rtx;
750: xops[1] = gen_rtx (CONST_INT, VOIDmode, 4);
751: output_asm_insn (AS2 (add%L0,%1,%0), xops);
752: }
753: else
754: output_asm_insn (\"fild%L0 %1\", operands);
755: if (! FP_REG_P (operands[0]))
756: {
757: /* fp_pop_level--; */
758: return \"fstp%Q0 %0\";
759: }
760: RET;
761: }")
762:
763: ;; Convert a float to a float whose value is an integer.
764: ;; This is the first stage of converting it to an integer type.
765:
766: ;; On the 387 truncating doub to an short integer shor can be performed:
767:
768: ; fstcw -4(%esp) ;save cw
769: ; movw -4(%esp),%ax
770: ; orw $0x0c00,%ax ;set rounding to chop towards zero
771: ; movw %ax,-2(%esp) ;
772: ; fldcw -2(%esp) ;
773: ; fldl doubl
774: ; fistpl -12(%esp) ;store the round value
775: ; fldcw -4(%esp) ;restore cw
776: ; movl -12(%esp),%eax
777: ; movw %ax,shor ; move the result into shor.
778:
779: ;; but it is probably better to have a call, rather than waste this
780: ;; space. The last instruction would have been a movl if were
781: ;; going to an int instead of a short.
782: ;; For the moment we will go with the soft float for these.
783:
784: /* These are incorrect since they don't set the rounding bits of CW flag.
785: The proper way to do that is to make the function prologue save the CW
786: and also construct the alternate CW value needed for these insns.
787: Then these insns can output two fldcw's, referring to fixed places in
788: the stack frame.
789:
790: ;; Convert a float whose value is an integer
791: ;; to an actual integer. Second stage of converting float to integer type.
792:
793: (define_insn "fix_truncsfqi2"
794: [(set (match_operand:QI 0 "general_operand" "=m,?*q")
795: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "f,f"))))]
796: "TARGET_80387"
797: "*
798: {
799: fp_pop_int (operands[0]);
800: RET;
801: }")
802:
803: (define_insn "fix_truncsfhi2"
804: [(set (match_operand:HI 0 "general_operand" "=m,?*r")
805: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "f,f"))))]
806: "TARGET_80387"
807: "*
808: {
809: fp_pop_int (operands[0]);
810: RET;
811: }")
812:
813: (define_insn "fix_truncsfsi2"
814: [(set (match_operand:SI 0 "general_operand" "=m,?*r")
815: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "f,f"))))]
816: "TARGET_80387"
817: "*
818: {
819: fp_pop_int (operands[0]);
820: RET;
821: }")
822:
823: (define_insn "fix_truncdfqi2"
824: [(set (match_operand:QI 0 "general_operand" "=m,?*q")
825: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "f,f"))))]
826:
827: "TARGET_80387"
828: "*
829: {
830: fp_pop_int (operands[0]);
831: RET;
832: }")
833:
834:
835: (define_insn "fix_truncdfhi2"
836: [(set (match_operand:HI 0 "general_operand" "=m,?*r")
837: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "f,f"))))]
838: "TARGET_80387"
839: "*
840: {
841: fp_pop_int (operands[0]);
842: RET;
843: }")
844:
845:
846: (define_insn "fix_truncdfsi2"
847: [(set (match_operand:SI 0 "general_operand" "=m,?*r")
848: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "f,f"))))]
849: "TARGET_80387"
850: "*
851: {
852: fp_pop_int (operands[0]);
853: RET;
854: }")
855: */
856:
857:
858: ;;- add instructions
859: ;;moved incl to above leal
860:
861: (define_insn "addsi3"
862: [(set (match_operand:SI 0 "general_operand" "=rm,r")
863: (plus:SI (match_operand:SI 1 "general_operand" "%0,0")
864: (match_operand:SI 2 "general_operand" "ri,rm")))]
865: ""
866: "add%L0 %2,%0")
867:
868: (define_insn ""
869: [(set (match_operand:HI 0 "general_operand" "=g")
870: (plus:HI (match_operand:HI 1 "general_operand" "0")
871: (const_int 1)))]
872: ""
873: "inc%W0 %0")
874:
875: (define_insn "addhi3"
876: [(set (match_operand:HI 0 "general_operand" "=rm,r")
877: (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
878: (match_operand:HI 2 "general_operand" "ri,rm")))]
879: ""
880: "add%W0 %2,%0")
881:
882: (define_insn ""
883: [(set (match_operand:QI 0 "general_operand" "=qm")
884: (plus:QI (match_operand:QI 1 "general_operand" "0")
885: (const_int 1)))]
886: ""
887: "inc%B0 %0")
888:
889: (define_insn "addqi3"
890: [(set (match_operand:QI 0 "general_operand" "=m,q")
891: (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
892: (match_operand:QI 2 "general_operand" "qn,qmn")))]
893: ""
894: "add%B0 %2,%0")
895:
896: ;;had "fmF,m"
897:
898: (define_insn "adddf3"
899: [(set (match_operand:DF 0 "general_operand" "=f,m,f")
900: (plus:DF (match_operand:DF 1 "general_operand" "%0,0,0")
901: (match_operand:DF 2 "general_operand" "m,!f,!*r")))]
902: "TARGET_80387"
903: "*FP_CALL (\"fadd%z0 %0\", \"fadd%z0 %0\", 2)")
904:
905: (define_insn "addsf3"
906: [(set (match_operand:SF 0 "general_operand" "=f,m,f")
907: (plus:SF (match_operand:SF 1 "general_operand" "%0,0,0")
908: (match_operand:SF 2 "general_operand" "m,!f,!*r")))]
909: "TARGET_80387"
910: "*FP_CALL (\"fadd%z0 %0\", \"fadd%z0 %0\", 2)")
911:
912: ;;- subtract instructions
913:
914: ;;moved decl above leal
915:
916: (define_insn "subsi3"
917: [(set (match_operand:SI 0 "general_operand" "=rm,r")
918: (minus:SI (match_operand:SI 1 "general_operand" "0,0")
919: (match_operand:SI 2 "general_operand" "ri,rm")))]
920: ""
921: "sub%L0 %2,%0")
922:
923: (define_insn ""
924: [(set (match_operand:HI 0 "general_operand" "=g")
925: (minus:HI (match_operand:HI 1 "general_operand" "0")
926: (const_int 1)))]
927: ""
928: "dec%W0 %0")
929:
930: (define_insn "subhi3"
931: [(set (match_operand:HI 0 "general_operand" "=rm,r")
932: (minus:HI (match_operand:HI 1 "general_operand" "0,0")
933: (match_operand:HI 2 "general_operand" "ri,rm")))]
934: ""
935: "sub%W0 %2,%0")
936:
937: (define_insn ""
938: [(set (match_operand:QI 0 "general_operand" "=qm")
939: (minus:QI (match_operand:QI 1 "general_operand" "0")
940: (const_int 1)))]
941: ""
942: "dec%B0 %0")
943:
944: (define_insn "subqi3"
945: [(set (match_operand:QI 0 "general_operand" "=m,q")
946: (minus:QI (match_operand:QI 1 "general_operand" "0,0")
947: (match_operand:QI 2 "general_operand" "qn,qmn")))]
948: ""
949: "sub%B0 %2,%0")
950:
951: (define_insn "subdf3"
952: [(set (match_operand:DF 0 "general_operand" "=f,m,f,f")
953: (minus:DF (match_operand:DF 1 "general_operand" "0,0,0,m")
954: (match_operand:DF 2 "general_operand" "m,!f,!*r,*0")))]
955: "TARGET_80387"
956: "*FP_CALL (\"fsub%z0 %0\", \"fsubr%z0 %0\", 2)")
957:
958:
959: (define_insn "subsf3"
960: [(set (match_operand:SF 0 "general_operand" "=f,m,f,f")
961: (minus:SF (match_operand:SF 1 "general_operand" "0,0,0,m")
962: (match_operand:SF 2 "general_operand" "m,!f,!*r,*0")))]
963: "TARGET_80387"
964: "*FP_CALL (\"fsub%z0 %0\", \"fsubr%z0 %0\", 2)")
965:
966: ;;- multiply instructions
967:
968: ;(define_insn "mulqi3"
969: ; [(set (match_operand:QI 0 "general_operand" "=a")
970: ; (mult:QI (match_operand:QI 1 "general_operand" "%0")
971: ; (match_operand:QI 2 "general_operand" "qm")))]
972: ; ""
973: ; "mul%B0 %2,%0")
974:
975: (define_insn "mulhi3"
976: [(set (match_operand:HI 0 "general_operand" "=r,r")
977: (mult:SI (match_operand:HI 1 "general_operand" "%0,rm")
978: (match_operand:HI 2 "general_operand" "g,i")))]
979: ""
980: "*
981: {
982: if (GET_CODE (operands[1]) == REG
983: && REGNO (operands[1]) == REGNO (operands[0])
984: && (GET_CODE (operands[2]) == MEM
985: || GET_CODE (operands[2]) == REG))
986: /* Assembler has weird restrictions. */
987: return AS2 (imul%W0,%2,%0);
988: return AS3 (imul%W0,%2,%1,%0);
989: }")
990:
991: (define_insn "mulsi3"
992: [(set (match_operand:SI 0 "general_operand" "=r,r")
993: (mult:SI (match_operand:SI 1 "general_operand" "%0,rm")
994: (match_operand:SI 2 "general_operand" "g,i")))]
995: ""
996: "*
997: {
998: if (GET_CODE (operands[1]) == REG
999: && REGNO (operands[1]) == REGNO (operands[0])
1000: && (GET_CODE (operands[2]) == MEM
1001: || GET_CODE (operands[2]) == REG))
1002: /* Assembler has weird restrictions. */
1003: return AS2 (imul%L0,%2,%0);
1004: return AS3 (imul%L0,%2,%1,%0);
1005: }")
1006:
1007: ;; Turned off due to possible assembler bug.
1008: ;(define_insn "umulqi3"
1009: ; [(set (match_operand:QI 0 "general_operand" "=a")
1010: ; (umult:QI (match_operand:QI 1 "general_operand" "%0")
1011: ; (match_operand:QI 2 "general_operand" "qm")))]
1012: ; ""
1013: ; "mul%B0 %2,%0")
1014:
1015: ;(define_insn "umulqihi3"
1016: ; [(set (match_operand:HI 0 "general_operand" "=a")
1017: ; (umult:HI (match_operand:QI 1 "general_operand" "%0")
1018: ; (match_operand:QI 2 "general_operand" "qm")))]
1019: ; ""
1020: ; "mul%B0 %2,%0")
1021:
1022: (define_insn "umulhi3"
1023: [(set (match_operand:HI 0 "general_operand" "=a")
1024: (umult:SI (match_operand:HI 1 "general_operand" "%0")
1025: (match_operand:HI 2 "general_operand" "rm")))
1026: (clobber (reg:HI 1))]
1027: ""
1028: "mul%W0 %2,%0")
1029:
1030: (define_insn "umulsi3"
1031: [(set (match_operand:SI 0 "general_operand" "=a")
1032: (umult:SI (match_operand:SI 1 "general_operand" "%0")
1033: (match_operand:SI 2 "general_operand" "rm")))
1034: (clobber (reg:SI 1))]
1035: ""
1036: "mul%L0 %2,%0")
1037:
1038: (define_insn "muldf3"
1039: [(set (match_operand:DF 0 "general_operand" "=f,m,f")
1040: (mult:DF (match_operand:DF 1 "general_operand" "%0,0,0")
1041: (match_operand:DF 2 "general_operand" "m,!f,!*r")))]
1042: "TARGET_80387"
1043: "*FP_CALL (\"fmul%z0 %0\", \"fmul%z0 %0\", 2)
1044: ")
1045:
1046: (define_insn "mulsf3"
1047: [(set (match_operand:SF 0 "general_operand" "=f,m,f")
1048: (mult:SF (match_operand:SF 1 "general_operand" "%0,0,0")
1049: (match_operand:SF 2 "general_operand" "m,!f,!*r")))]
1050: "TARGET_80387"
1051: "*FP_CALL (\"fmul%z0 %0\", \"fmul%z0 %0\", 2)
1052: ")
1053:
1054: ;;- divide instructions
1055: (define_insn "divdf3"
1056: [(set (match_operand:DF 0 "general_operand" "=f,m,f,f")
1057: (div:DF (match_operand:DF 1 "general_operand" "0,0,0,m")
1058: (match_operand:DF 2 "general_operand" "m,!f,!*r,*0")))]
1059: "TARGET_80387"
1060: "*FP_CALL (\"fdiv%z0 %0\", \"fdivr%z0 %0\", 2)
1061: ")
1062:
1063: (define_insn "divsf3"
1064: [(set (match_operand:SF 0 "general_operand" "=f,m,f,f")
1065: (div:SF (match_operand:SF 1 "general_operand" "0,0,0,m")
1066: (match_operand:SF 2 "general_operand" "m,!f,!*r,*0")))]
1067: "TARGET_80387"
1068: "*FP_CALL (\"fdiv%z0 %0\", \"fdivr%z0 %0\", 2)
1069: ")
1070:
1.1.1.5 ! root 1071: ;; Divide and Remainder instructions.
1.1 root 1072:
1.1.1.5 ! root 1073: ;; Copy operands 1 and 2 to new registers, so that there's no
! 1074: ;; danger that put_var_into_stack will mess up the sharing match_dup needs.
! 1075: ;; CSE will get rid of the extra pseudo regs.
! 1076: ;; No problem if not optimizing, since then only `register' vars
! 1077: ;; will get pseudo regs, and they aren't allowed to have address taken.
! 1078:
! 1079: (define_expand "divmodsi4"
! 1080: [(parallel [(set (match_operand:SI 0 "general_operand" "=a")
! 1081: (div:SI (match_operand:SI 1 "general_operand" "0")
! 1082: (match_operand:SI 2 "general_operand" "rm")))
! 1083: (set (match_operand:SI 3 "general_operand" "=&d")
! 1084: (mod:SI (match_dup 1) (match_dup 2)))])]
! 1085: ""
! 1086: "
! 1087: {
! 1088: extern int optimize;
! 1089: if (optimize)
! 1090: {
! 1091: if (GET_CODE (operands[1]) == REG && REG_USERVAR_P (operands[1]))
! 1092: operands[1] = copy_to_mode_reg (SImode, operands[1]);
! 1093: if (GET_CODE (operands[2]) == REG && REG_USERVAR_P (operands[2]))
! 1094: operands[2] = copy_to_mode_reg (SImode, operands[2]);
! 1095: }
! 1096: }")
! 1097:
! 1098: (define_expand "udivmodsi4"
! 1099: [(parallel [(set (match_operand:SI 0 "general_operand" "=a")
! 1100: (udiv:SI (match_operand:SI 1 "general_operand" "0")
! 1101: (match_operand:SI 2 "general_operand" "rm")))
! 1102: (set (match_operand:SI 3 "general_operand" "=&d")
! 1103: (umod:SI (match_dup 1) (match_dup 2)))])]
! 1104: ""
! 1105: "
! 1106: {
! 1107: extern int optimize;
! 1108: if (optimize)
! 1109: {
! 1110: if (GET_CODE (operands[1]) == REG && REG_USERVAR_P (operands[1]))
! 1111: operands[1] = copy_to_mode_reg (SImode, operands[1]);
! 1112: if (GET_CODE (operands[2]) == REG && REG_USERVAR_P (operands[2]))
! 1113: operands[2] = copy_to_mode_reg (SImode, operands[2]);
! 1114: }
! 1115: }")
! 1116:
! 1117: (define_insn ""
1.1 root 1118: [(set (match_operand:SI 0 "general_operand" "=a")
1119: (div:SI (match_operand:SI 1 "general_operand" "0")
1120: (match_operand:SI 2 "general_operand" "rm")))
1121: (set (match_operand:SI 3 "general_operand" "=&d")
1122: (mod:SI (match_dup 1) (match_dup 2)))]
1123: ""
1124: "cltd\;idiv%L0 %2")
1125:
1.1.1.5 ! root 1126: (define_insn ""
1.1 root 1127: [(set (match_operand:SI 0 "general_operand" "=a")
1128: (udiv:SI (match_operand:SI 1 "general_operand" "0")
1129: (match_operand:SI 2 "general_operand" "rm")))
1130: (set (match_operand:SI 3 "general_operand" "=&d")
1131: (umod:SI (match_dup 1) (match_dup 2)))]
1132: ""
1133: "xor%L0 %3,%3\;div%L0 %2")
1134:
1135: /*
1136: ;;this should be a valid double division which we may want to add
1137:
1138: (define_insn ""
1139: [(set (match_operand:SI 0 "general_operand" "=a")
1140: (udiv:DI (match_operand:DI 1 "general_operand" "a")
1141: (match_operand:SI 2 "general_operand" "rm")))
1142: (set (match_operand:SI 3 "general_operand" "=d")
1143: (umod:SI (match_dup 1) (match_dup 2)))]
1144: ""
1145: "div%L0 %2,%0")
1146: */
1147:
1148: ;;- and instructions
1149:
1150: ;; The `r' in `rm' for operand 3 looks redundant, but it causes
1151: ;; optional reloads to be generated if op 3 is a pseudo in a stack slot.
1152:
1153: (define_insn "andsi3"
1154: [(set (match_operand:SI 0 "general_operand" "=rm,r")
1155: (and:SI (match_operand:SI 1 "general_operand" "%0,0")
1156: (match_operand:SI 2 "general_operand" "ri,rm")))]
1157: ""
1158: "and%L0 %2,%0")
1159:
1160: (define_insn "andhi3"
1161: [(set (match_operand:HI 0 "general_operand" "=rm,r")
1162: (and:HI (match_operand:HI 1 "general_operand" "%0,0")
1163: (match_operand:HI 2 "general_operand" "ri,rm")))]
1164: ""
1165: "and%W0 %2,%0")
1166:
1167: (define_insn "andqi3"
1168: [(set (match_operand:QI 0 "general_operand" "=m,q")
1169: (and:QI (match_operand:QI 1 "general_operand" "%0,0")
1170: (match_operand:QI 2 "general_operand" "qn,qmn")))]
1171: ""
1172: "and%B0 %2,%0")
1173:
1174: /* I am nervous about these two.. add them later..
1175: ;I presume this means that we have something in say op0= eax which is small
1176: ;and we want to and it with memory so we can do this by just an
1177: ;andb m,%al and have success.
1178: (define_insn ""
1179: [(set (match_operand:SI 0 "general_operand" "=r")
1180: (and:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rm"))
1181: (match_operand:SI 2 "general_operand" "0")))]
1182: "GET_CODE (operands[2]) == CONST_INT
1183: && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))"
1184: "and%W0 %1,%0")
1185:
1186: (define_insn ""
1187: [(set (match_operand:SI 0 "general_operand" "=q")
1188: (and:SI (zero_extend:SI (match_operand:QI 1 "general_operand" "qm"))
1189: (match_operand:SI 2 "general_operand" "0")))]
1190: "GET_CODE (operands[2]) == CONST_INT
1191: && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (QImode))"
1192: "and%L0 %1,%0")
1193:
1194: */
1195:
1196:
1197:
1198: ;;- Bit set (inclusive or) instructions
1199:
1200: (define_insn "iorsi3"
1201: [(set (match_operand:SI 0 "general_operand" "=rm,r")
1202: (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
1203: (match_operand:SI 2 "general_operand" "ri,rm")))]
1204: ""
1205: "or%L0 %2,%0")
1206:
1207: (define_insn "iorhi3"
1208: [(set (match_operand:HI 0 "general_operand" "=rm,r")
1209: (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
1210: (match_operand:HI 2 "general_operand" "ri,rm")))]
1211: ""
1212: "or%W0 %2,%0")
1213:
1214: (define_insn "iorqi3"
1215: [(set (match_operand:QI 0 "general_operand" "=m,q")
1216: (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
1217: (match_operand:QI 2 "general_operand" "qn,qmn")))]
1218: ""
1219: "or%B0 %2,%0")
1220:
1221: ;;- xor instructions
1222:
1223: (define_insn "xorsi3"
1224: [(set (match_operand:SI 0 "general_operand" "=rm,r")
1225: (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
1226: (match_operand:SI 2 "general_operand" "ri,rm")))]
1227: ""
1228: "xor%L0 %2,%0")
1229:
1230: (define_insn "xorhi3"
1231: [(set (match_operand:HI 0 "general_operand" "=rm,r")
1232: (xor:HI (match_operand:HI 1 "general_operand" "%0,0")
1233: (match_operand:HI 2 "general_operand" "ri,rm")))]
1234: ""
1235: "xor%W0 %2,%0")
1236:
1237: (define_insn "xorqi3"
1238: [(set (match_operand:QI 0 "general_operand" "=qm")
1239: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1240: (match_operand:QI 2 "general_operand" "qn")))]
1241: ""
1242: "xor%B0 %2,%0")
1243:
1244: ;;- negation instructions
1245: (define_insn "negsi2"
1246: [(set (match_operand:SI 0 "general_operand" "=rm")
1247: (neg:SI (match_operand:SI 1 "general_operand" "0")))]
1248: ""
1249: "neg%L0 %0")
1250:
1251: (define_insn "neghi2"
1252: [(set (match_operand:HI 0 "general_operand" "=rm")
1253: (neg:HI (match_operand:HI 1 "general_operand" "0")))]
1254: ""
1255: "neg%W0 %0")
1256:
1257: (define_insn "negqi2"
1258: [(set (match_operand:QI 0 "general_operand" "=qm")
1259: (neg:QI (match_operand:QI 1 "general_operand" "0")))]
1260: ""
1261: "neg%B0 %0")
1262:
1263: (define_insn "negsf2"
1264: [(set (match_operand:SF 0 "general_operand" "=f,!m")
1265: (neg:SF (match_operand:SF 1 "general_operand" "0,0")))]
1266: "TARGET_80387"
1267: "*FP_CALL1 (\"fchs\")")
1268:
1269: (define_insn "negdf2"
1270: [(set (match_operand:DF 0 "general_operand" "=f,!m")
1271: (neg:DF (match_operand:DF 1 "general_operand" "0,0")))]
1272: "TARGET_80387"
1273: "*FP_CALL1 (\"fchs\")")
1274:
1275: ;; Absolute value instructions
1276:
1277: (define_insn "abssf2"
1278: [(set (match_operand:SF 0 "general_operand" "=f,!m")
1279: (abs:SF (match_operand:SF 1 "general_operand" "0,0")))]
1280: "TARGET_80387"
1281: "*FP_CALL1 (\"fabs\")")
1282:
1283: (define_insn "absdf2"
1284: [(set (match_operand:DF 0 "general_operand" "=f,!m")
1285: (abs:DF (match_operand:DF 1 "general_operand" "0,0")))]
1286: "TARGET_80387"
1287: "*FP_CALL1 (\"fabs\")")
1288:
1289: ;;- one complement instructions
1290: (define_insn "one_cmplsi2"
1291: [(set (match_operand:SI 0 "general_operand" "=rm")
1292: (not:SI (match_operand:SI 1 "general_operand" "0")))]
1293: ""
1294: "not%L0 %0")
1295:
1296: (define_insn "one_cmplhi2"
1297: [(set (match_operand:HI 0 "general_operand" "=rm")
1298: (not:HI (match_operand:HI 1 "general_operand" "0")))]
1299: ""
1300: "not%W0 %0")
1301:
1302: (define_insn "one_cmplqi2"
1303: [(set (match_operand:QI 0 "general_operand" "=qm")
1304: (not:QI (match_operand:QI 1 "general_operand" "0")))]
1305: ""
1306: "not%B0 %0")
1307:
1308: ;;- arithmetic shift instructions
1309:
1310: (define_insn "ashlsi3"
1311: [(set (match_operand:SI 0 "general_operand" "=rm")
1312: (ashift:SI (match_operand:SI 1 "general_operand" "0")
1313: (match_operand:SI 2 "general_operand" "cI")))]
1314: ""
1315: "*
1316: {
1317: if (REG_P (operands[2]))
1318: return AS2 (sal%L0,%R0cl,%0);
1319: else if (REG_P (operands[1]) && GET_CODE (operands[2]) == CONST_INT
1320: && INTVAL (operands[2]) == 1)
1321: return AS2 (add%L0,%1,%1);
1322: return AS2 (sal%L0,%2,%1);
1323: }")
1324:
1325: (define_insn "ashlhi3"
1326: [(set (match_operand:HI 0 "general_operand" "=rm")
1327: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1328: (match_operand:HI 2 "general_operand" "cI")))]
1329: ""
1330: "*
1331: {
1332: if (REG_P (operands[2]))
1333: return AS2 (sal%W0,%R0cl,%0);
1334: else
1335: return AS2 (sal%W0,%2,%1);
1336: }")
1337:
1338: (define_insn "ashlqi3"
1339: [(set (match_operand:QI 0 "general_operand" "=qm")
1340: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1341: (match_operand:QI 2 "general_operand" "cI")))]
1342: ""
1343: "*
1344: {
1345: if (REG_P (operands[2]))
1346: return AS2 (sal%B0,%R0cl,%0);
1347: else
1348: return AS2 (sal%B0,%2,%1);
1349: }")
1350:
1351: (define_insn "ashrsi3"
1352: [(set (match_operand:SI 0 "general_operand" "=rm")
1353: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1354: (match_operand:SI 2 "general_operand" "cI")))]
1355: ""
1356: "*
1357: {
1358: if (REG_P (operands[2]))
1359: return AS2 (sar%L0,%R0cl,%0);
1360: else
1361: return AS2 (sar%L0,%2,%0);
1362: }")
1363:
1364: (define_insn "ashrhi3"
1365: [(set (match_operand:HI 0 "general_operand" "=rm")
1366: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1367: (match_operand:HI 2 "general_operand" "cI")))]
1368: ""
1369: "*
1370: {
1371: if (REG_P (operands[2]))
1372: return AS2 (sar%W0,%R0cl,%0);
1373: else
1374: return AS2 (sar%W0,%2,%0);
1375: }")
1376:
1377: (define_insn "ashrqi3"
1378: [(set (match_operand:QI 0 "general_operand" "=qm")
1379: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1380: (match_operand:QI 2 "general_operand" "cI")))]
1381: ""
1382: "*
1383: {
1384: if (REG_P (operands[2]))
1385: return AS2 (sar%B0,%R0cl,%0);
1386: return
1387: AS2 (sar%B0,%2,%1);
1388: }")
1389:
1390: ;;- logical shift instructions
1391:
1392: (define_insn "lshlsi3"
1393: [(set (match_operand:SI 0 "general_operand" "=rm")
1394: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1395: (match_operand:SI 2 "general_operand" "cI")))]
1396: ""
1397: "*
1398: {
1399: if (REG_P (operands[2]))
1400: return AS2 (shl%L0,%R0cl,%0);
1401: else
1402: return AS2 (shl%L0,%2,%1);
1403: }")
1404:
1405: (define_insn "lshlhi3"
1406: [(set (match_operand:HI 0 "general_operand" "=rm")
1407: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1408: (match_operand:HI 2 "general_operand" "cI")))]
1409: ""
1410: "*
1411: {
1412: if (REG_P (operands[2]))
1413: return AS2 (shl%W0,%R0cl,%0);
1414: else
1415: return AS2 (shl%W0,%2,%1);
1416: }")
1417:
1418: (define_insn "lshlqi3"
1419: [(set (match_operand:QI 0 "general_operand" "=qm")
1420: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1421: (match_operand:QI 2 "general_operand" "cI")))]
1422: ""
1423: "*
1424: {
1425: if (REG_P (operands[2]))
1426: return AS2 (shl%B0,%R0cl,%0);
1427: else
1428: return AS2 (shl%B0,%2,%1);
1429: }")
1430:
1431: (define_insn "lshrsi3"
1432: [(set (match_operand:SI 0 "general_operand" "=rm")
1433: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1434: (match_operand:SI 2 "general_operand" "cI")))]
1435: ""
1436: "*
1437: {
1438: if (REG_P (operands[2]))
1439: return AS2 (shr%L0,%R0cl,%0);
1440: else
1441: return AS2 (shr%L0,%2,%1);
1442: }")
1443:
1444: (define_insn "lshrhi3"
1445: [(set (match_operand:HI 0 "general_operand" "=rm")
1446: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1447: (match_operand:HI 2 "general_operand" "cI")))]
1448: ""
1449: "*
1450: {
1451: if (REG_P (operands[2]))
1452: return AS2 (shr%W0,%%cl,%0);
1453: else
1454: return AS2 (shr%W0,%2,%1);
1455: }")
1456:
1457: (define_insn "lshrqi3"
1458: [(set (match_operand:QI 0 "general_operand" "=qm")
1459: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1460: (match_operand:QI 2 "general_operand" "cI")))]
1461: ""
1462: "*
1463: {
1464: if (REG_P (operands[2]))
1465: return AS2 (shr%B0,%%cl,%0);
1466: else
1467: return AS2 (shr%B0,%2,%1);
1468: }")
1469:
1470: ;;- rotate instructions
1471:
1472: (define_insn "rotlsi3"
1473: [(set (match_operand:SI 0 "general_operand" "=rm")
1474: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1475: (match_operand:SI 2 "general_operand" "cI")))]
1476: ""
1477: "*
1478: {
1479: if (REG_P (operands[2]))
1480: return AS2 (rol%L0,%%cl,%0);
1481: else
1482: return AS2 (rol%L0,%2,%1);
1483: }")
1484:
1485: (define_insn "rotlhi3"
1486: [(set (match_operand:HI 0 "general_operand" "=rm")
1487: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1488: (match_operand:HI 2 "general_operand" "cI")))]
1489: ""
1490: "*
1491: {
1492: if (REG_P (operands[2]))
1493: return AS2 (rol%W0,%%cl,%0);
1494: else
1495: return AS2 (rol%W0,%2,%1);
1496: }")
1497:
1498: (define_insn "rotlqi3"
1499: [(set (match_operand:QI 0 "general_operand" "=qm")
1500: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1501: (match_operand:QI 2 "general_operand" "cI")))]
1502: ""
1503: "*
1504: {
1505: if (REG_P (operands[2]))
1506: return AS2 (rol%B0,%%cl,%0);
1507: else
1508: return AS2 (rol%B0,%2,%1);
1509: }")
1510:
1511: (define_insn "rotrsi3"
1512: [(set (match_operand:SI 0 "general_operand" "=rm")
1513: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1514: (match_operand:SI 2 "general_operand" "cI")))]
1515: ""
1516: "*
1517: {
1518: if (REG_P (operands[2]))
1519: return AS2 (ror%L0,%%cl,%0);
1520: else
1521: return AS2 (ror%L0,%2,%1);
1522: }")
1523:
1524: (define_insn "rotrhi3"
1525: [(set (match_operand:HI 0 "general_operand" "=rm")
1526: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1527: (match_operand:HI 2 "general_operand" "cI")))]
1528: ""
1529: "*
1530: {
1531: if (REG_P (operands[2]))
1532: return AS2 (ror%W0,%%cl,%0);
1533: else
1534: return AS2 (ror%W0,%2,%1);
1535: }")
1536:
1537: (define_insn "rotrqi3"
1538: [(set (match_operand:QI 0 "general_operand" "=qm")
1539: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1540: (match_operand:QI 2 "general_operand" "cI")))]
1541: ""
1542: "*
1543: {
1544: if (REG_P (operands[2]))
1545: return AS2 (ror%B0,%%cl,%0);
1546: else
1547: return AS2 (ror%B0,%2,%1);
1548: }")
1549:
1550: ;; Store-flag instructions.
1551:
1552: (define_insn "seq"
1553: [(set (match_operand:QI 0 "general_operand" "=q")
1554: (eq (cc0) (const_int 0)))]
1555: ""
1556: "*
1557: cc_status = cc_prev_status;
1558: return \"sete %0\";
1559: ")
1560:
1561: (define_insn "sne"
1562: [(set (match_operand:QI 0 "general_operand" "=q")
1563: (ne (cc0) (const_int 0)))]
1564: ""
1565: "*
1566: cc_status = cc_prev_status;
1567: return \"setne %0\";
1568: ")
1569:
1570: (define_insn "sgt"
1571: [(set (match_operand:QI 0 "general_operand" "=q")
1572: (gt (cc0) (const_int 0)))]
1573: ""
1574: "*
1575: cc_status = cc_prev_status;
1576: OUTPUT_JUMP (\"setg %0\", \"seta %0\", 0);
1577: ")
1578:
1579: (define_insn "sgtu"
1580: [(set (match_operand:QI 0 "general_operand" "=q")
1581: (gtu (cc0) (const_int 0)))]
1582: ""
1583: "* cc_status = cc_prev_status;
1584: return \"seta %0\"; ")
1585:
1586: (define_insn "slt"
1587: [(set (match_operand:QI 0 "general_operand" "=q")
1588: (lt (cc0) (const_int 0)))]
1589: ""
1590: "* cc_status = cc_prev_status;
1591: OUTPUT_JUMP (\"setl %0\", \"setb %0\", \"sets %0\"); ")
1592:
1593: (define_insn "sltu"
1594: [(set (match_operand:QI 0 "general_operand" "=q")
1595: (ltu (cc0) (const_int 0)))]
1596: ""
1597: "* cc_status = cc_prev_status;
1598: return \"setb %0\"; ")
1599:
1600: (define_insn "sge"
1601: [(set (match_operand:QI 0 "general_operand" "=q")
1602: (ge (cc0) (const_int 0)))]
1603: ""
1604: "* cc_status = cc_prev_status;
1605: OUTPUT_JUMP (\"setge %0\", \"setae %0\", \"setns %0\"); ")
1606:
1607: (define_insn "sgeu"
1608: [(set (match_operand:QI 0 "general_operand" "=q")
1609: (geu (cc0) (const_int 0)))]
1610: ""
1611: "* cc_status = cc_prev_status;
1612: return \"setae %0\"; ")
1613:
1614: (define_insn "sle"
1615: [(set (match_operand:QI 0 "general_operand" "=q")
1616: (le (cc0) (const_int 0)))]
1617: ""
1618: "*
1619: cc_status = cc_prev_status;
1620: OUTPUT_JUMP (\"setle %0\", \"setbe %0\", 0);
1621: ")
1622:
1623: (define_insn "sleu"
1624: [(set (match_operand:QI 0 "general_operand" "=q")
1625: (leu (cc0) (const_int 0)))]
1626: ""
1627: "* cc_status = cc_prev_status;
1628: return \"setbe %0\"; ")
1629:
1630: ;; Basic conditional jump instructions.
1631: ;; We ignore the overflow flag for signed branch instructions.
1632:
1633: (define_insn "beq"
1634: [(set (pc)
1635: (if_then_else (eq (cc0)
1636: (const_int 0))
1637: (label_ref (match_operand 0 "" ""))
1638: (pc)))]
1639: ""
1640: "je %l0")
1641:
1642: (define_insn "bne"
1643: [(set (pc)
1644: (if_then_else (ne (cc0)
1645: (const_int 0))
1646: (label_ref (match_operand 0 "" ""))
1647: (pc)))]
1648: ""
1649: "jne %l0")
1650:
1651: (define_insn "bgt"
1652: [(set (pc)
1653: (if_then_else (gt (cc0)
1654: (const_int 0))
1655: (label_ref (match_operand 0 "" ""))
1656: (pc)))]
1657: ""
1658: "*OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0)")
1659:
1660: (define_insn "bgtu"
1661: [(set (pc)
1662: (if_then_else (gtu (cc0)
1663: (const_int 0))
1664: (label_ref (match_operand 0 "" ""))
1665: (pc)))]
1666: ""
1667: "ja %l0")
1668:
1.1.1.3 root 1669: ;; There is no jump insn to check for `<' on IEEE floats.
1670: ;; Page 17-80 in the 80387 manual says jb, but that's wrong;
1671: ;; jb checks for `not >='. So swap the operands and do `>'.
1672: (define_expand "blt"
1673: [(set (pc)
1674: (if_then_else (lt (cc0)
1675: (const_int 0))
1676: (label_ref (match_operand 0 "" ""))
1677: (pc)))]
1678: ""
1679: "
1680: {
1681: extern rtx sequence_stack;
1682: rtx prev = XEXP (XEXP (sequence_stack, 1), 0);
1683: rtx body = PATTERN (prev);
1684: rtx comp;
1685: if (GET_CODE (body) == SET)
1686: comp = SET_SRC (body);
1687: else
1688: comp = SET_SRC (XVECEXP (body, 0, 0));
1689:
1690: if (GET_CODE (comp) == COMPARE
1691: ? GET_MODE_CLASS (GET_MODE (XEXP (comp, 0))) == MODE_FLOAT
1692: : GET_MODE_CLASS (GET_MODE (comp)) == MODE_FLOAT)
1693: {
1694: if (GET_CODE (comp) == COMPARE)
1695: {
1696: rtx op0 = XEXP (comp, 0);
1697: rtx op1 = XEXP (comp, 1);
1698: XEXP (comp, 0) = op1;
1699: XEXP (comp, 1) = op0;
1700: }
1701: else
1702: {
1703: rtx new = gen_rtx (COMPARE, VOIDmode,
1704: CONST0_RTX (GET_MODE (comp)), comp);
1705: if (GET_CODE (body) == SET)
1706: SET_SRC (body) = new;
1707: else
1708: SET_SRC (XVECEXP (body, 0, 0)) = new;
1709: }
1710: emit_insn (gen_bgt (operands[0]));
1711: DONE;
1712: }
1713: }")
1714:
1715: (define_insn ""
1.1 root 1716: [(set (pc)
1717: (if_then_else (lt (cc0)
1718: (const_int 0))
1719: (label_ref (match_operand 0 "" ""))
1720: (pc)))]
1721: ""
1722: "*OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\")")
1723:
1724: (define_insn "bltu"
1725: [(set (pc)
1726: (if_then_else (ltu (cc0)
1727: (const_int 0))
1728: (label_ref (match_operand 0 "" ""))
1729: (pc)))]
1730: ""
1731: "jb %l0")
1732:
1733: (define_insn "bge"
1734: [(set (pc)
1735: (if_then_else (ge (cc0)
1736: (const_int 0))
1737: (label_ref (match_operand 0 "" ""))
1738: (pc)))]
1739: ""
1740: "*OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\")")
1741:
1742: (define_insn "bgeu"
1743: [(set (pc)
1744: (if_then_else (geu (cc0)
1745: (const_int 0))
1746: (label_ref (match_operand 0 "" ""))
1747: (pc)))]
1748: ""
1749: "jae %l0")
1750:
1.1.1.3 root 1751: ;; See comment on `blt', above.
1752: (define_expand "ble"
1753: [(set (pc)
1754: (if_then_else (le (cc0)
1755: (const_int 0))
1756: (label_ref (match_operand 0 "" ""))
1757: (pc)))]
1758: ""
1759: "
1760: {
1761: extern rtx sequence_stack;
1762: rtx prev = XEXP (XEXP (sequence_stack, 1), 0);
1763: rtx body = PATTERN (prev);
1764: rtx comp;
1765: if (GET_CODE (body) == SET)
1766: comp = SET_SRC (body);
1767: else
1768: comp = SET_SRC (XVECEXP (body, 0, 0));
1769:
1770: if (GET_CODE (comp) == COMPARE
1771: ? GET_MODE_CLASS (GET_MODE (XEXP (comp, 0))) == MODE_FLOAT
1772: : GET_MODE_CLASS (GET_MODE (comp)) == MODE_FLOAT)
1773: {
1774: if (GET_CODE (comp) == COMPARE)
1775: {
1776: rtx op0 = XEXP (comp, 0);
1777: rtx op1 = XEXP (comp, 1);
1778: XEXP (comp, 0) = op1;
1779: XEXP (comp, 1) = op0;
1780: }
1781: else
1782: {
1783: rtx new = gen_rtx (COMPARE, VOIDmode,
1784: CONST0_RTX (GET_MODE (comp)), comp);
1785: if (GET_CODE (body) == SET)
1786: SET_SRC (body) = new;
1787: else
1788: SET_SRC (XVECEXP (body, 0, 0)) = new;
1789: }
1790: emit_insn (gen_bge (operands[0]));
1791: DONE;
1792: }
1793: }")
1794:
1795: (define_insn ""
1.1 root 1796: [(set (pc)
1797: (if_then_else (le (cc0)
1798: (const_int 0))
1799: (label_ref (match_operand 0 "" ""))
1800: (pc)))]
1801: ""
1802: "*OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0) ")
1803:
1804: (define_insn "bleu"
1805: [(set (pc)
1806: (if_then_else (leu (cc0)
1807: (const_int 0))
1808: (label_ref (match_operand 0 "" ""))
1809: (pc)))]
1810: ""
1811: "jbe %l0")
1812:
1813: ;; Negated conditional jump instructions.
1814:
1815: (define_insn ""
1816: [(set (pc)
1817: (if_then_else (eq (cc0)
1818: (const_int 0))
1819: (pc)
1820: (label_ref (match_operand 0 "" ""))))]
1821: ""
1822: "jne %l0")
1823:
1824: (define_insn ""
1825: [(set (pc)
1826: (if_then_else (ne (cc0)
1827: (const_int 0))
1828: (pc)
1829: (label_ref (match_operand 0 "" ""))))]
1830: ""
1831: "je %l0")
1832:
1833: (define_insn ""
1834: [(set (pc)
1835: (if_then_else (gt (cc0)
1836: (const_int 0))
1837: (pc)
1838: (label_ref (match_operand 0 "" ""))))]
1839: ""
1840: "*OUTPUT_JUMP (\"jle %l0\", \"jbe %l0\", 0) ")
1841:
1842: (define_insn ""
1843: [(set (pc)
1844: (if_then_else (gtu (cc0)
1845: (const_int 0))
1846: (pc)
1847: (label_ref (match_operand 0 "" ""))))]
1848: ""
1849: "jbe %l0")
1850:
1851: (define_insn ""
1852: [(set (pc)
1853: (if_then_else (lt (cc0)
1854: (const_int 0))
1855: (pc)
1856: (label_ref (match_operand 0 "" ""))))]
1857: ""
1858: "*OUTPUT_JUMP (\"jge %l0\", \"jae %l0\", \"jns %l0\")
1859: ")
1860:
1861: (define_insn ""
1862: [(set (pc)
1863: (if_then_else (ltu (cc0)
1864: (const_int 0))
1865: (pc)
1866: (label_ref (match_operand 0 "" ""))))]
1867: ""
1868: "jae %l0")
1869:
1870: (define_insn ""
1871: [(set (pc)
1872: (if_then_else (ge (cc0)
1873: (const_int 0))
1874: (pc)
1875: (label_ref (match_operand 0 "" ""))))]
1876: ""
1877: "*OUTPUT_JUMP (\"jl %l0\", \"jb %l0\", \"js %l0\")")
1878:
1879: (define_insn ""
1880: [(set (pc)
1881: (if_then_else (geu (cc0)
1882: (const_int 0))
1883: (pc)
1884: (label_ref (match_operand 0 "" ""))))]
1885: ""
1886: "jb %l0")
1887:
1888: (define_insn ""
1889: [(set (pc)
1890: (if_then_else (le (cc0)
1891: (const_int 0))
1892: (pc)
1893: (label_ref (match_operand 0 "" ""))))]
1894: ""
1895: "*OUTPUT_JUMP (\"jg %l0\", \"ja %l0\", 0)")
1896:
1897: (define_insn ""
1898: [(set (pc)
1899: (if_then_else (leu (cc0)
1900: (const_int 0))
1901: (pc)
1902: (label_ref (match_operand 0 "" ""))))]
1903: ""
1904: "ja %l0")
1905:
1906: ;; Unconditional and other jump instructions
1907: (define_insn "jump"
1908: [(set (pc)
1909: (label_ref (match_operand 0 "" "")))]
1910: ""
1911: "jmp %l0")
1912:
1913: (define_insn "tablejump"
1914: [(set (pc) (match_operand:SI 0 "general_operand" "rm"))
1915: (use (label_ref (match_operand 1 "" "")))]
1916: ""
1917: "*
1918: {
1919: CC_STATUS_INIT;
1920:
1921: return \"jmp %*%0\";
1922: }")
1923:
1924: /*
1925: (define_insn ""
1926: [(set (pc)
1927: (if_then_else
1928: (ne (compare (minus:HI (match_operand:HI 0 "general_operand" "c")
1929: (const_int 1))
1930: (const_int -1))
1931: (const_int 0))
1932: (label_ref (match_operand 1 "" "g"))
1933: (pc)))
1934: (set (match_dup 0)
1935: (minus:HI (match_dup 0)
1936: (const_int 1)))]
1937: ""
1938: "loop %l1")
1939:
1940: (define_insn ""
1941: [(set (pc)
1942: (if_then_else
1943: (ne (compare (const_int -1)
1944: (minus:SI (match_operand:SI 0 "general_operand" "c")
1945: (const_int 1)))
1946: (const_int 0))
1947: (label_ref (match_operand 1 "" "g"))
1948: (pc)))
1949: (set (match_dup 0)
1950: (minus:SI (match_dup 0)
1951: (const_int 1)))]
1952: ""
1953: "loop %l1")
1954: */
1955:
1956: ;; Call subroutine returning no value.
1957: (define_insn "call"
1958: [(call (match_operand:QI 0 "indirect_operand" "m")
1959: (match_operand:SI 1 "general_operand" "g"))]
1960: ;; Operand 1 not really used on the m68000.
1961: ""
1962: "*
1963: {
1964: if (GET_CODE (operands[0]) == MEM
1965: && ! CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
1966: {
1967: operands[0] = XEXP (operands[0], 0);
1968: return \"call %*%0\";
1969: }
1970: else
1971: return \"call %0\";
1972: }")
1973:
1974: ;; Call subroutine, returning value in operand 0
1975: ;; (which must be a hard register).
1976: (define_insn "call_value"
1977: [(set (match_operand 0 "" "=rf")
1978: (call (match_operand:QI 1 "indirect_operand" "m")
1979: (match_operand:SI 2 "general_operand" "g")))]
1980: ;; Operand 2 not really used on the m68000.
1981: ""
1982: "*
1983: {
1984: if (GET_CODE (operands[1]) == MEM
1985: && ! CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
1986: {
1987: operands[1] = XEXP (operands[1], 0);
1988: output_asm_insn (\"call %*%1\", operands);
1989: }
1990: else
1991: output_asm_insn (\"call %1\", operands);
1992:
1993: if (GET_MODE (operands[0]) == DFmode
1994: || GET_MODE (operands[0]) == SFmode)
1995: {
1996: /* fp_pop_level++; */
1997: /* pop if reg dead */
1998: if (!FP_REG_P (operands[0]))
1999: abort ();
2000: if (top_dead_p (insn))
2001: {
2002: POP_ONE_FP;
2003: }
2004: }
2005: RET;
2006: }")
2007:
2008: (define_insn "nop"
2009: [(const_int 0)]
2010: ""
2011: "nop")
2012:
2013: ;;- Local variables:
2014: ;;- mode:emacs-lisp
2015: ;;- comment-start: ";;- "
2016: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2017: ;;- eval: (modify-syntax-entry ?[ "(]")
2018: ;;- eval: (modify-syntax-entry ?] ")[")
2019: ;;- eval: (modify-syntax-entry ?{ "(}")
2020: ;;- eval: (modify-syntax-entry ?} "){")
2021: ;;- End:
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