--- gcc/config/i860.md 2018/04/24 16:53:27 1.1 +++ gcc/config/i860.md 2018/04/24 16:54:41 1.1.1.2 @@ -176,7 +176,7 @@ { cc_status.flags &= ~ CC_CONDITION_MASK; cc_status.flags |= CC_ONLY_EQ; - return \"pfeq.s %r1,%r0\"; + return \"pfeq.s %r1,%r0,f0\"; }") (define_insn "cmpltsf" @@ -187,7 +187,7 @@ { cc_status.flags &= ~ CC_CONDITION_MASK; cc_status.flags |= CC_ONLY_LT; - return \"pfgt.s %r1,%r0\"; + return \"pfgt.s %r1,%r0,f0\"; }") (define_insn "cmpgtsf" @@ -198,7 +198,7 @@ { cc_status.flags &= ~ CC_CONDITION_MASK; cc_status.flags |= CC_ONLY_LT; - return \"pfgt.s %r0,%r1\"; + return \"pfgt.s %r0,%r1,f0\"; }") (define_insn "cmplesf" @@ -209,7 +209,7 @@ { cc_status.flags &= ~ CC_CONDITION_MASK; cc_status.flags |= CC_ONLY_LE; - return \"pfle.s %r1,%r0\"; + return \"pfle.s %r1,%r0,f0\"; }") (define_insn "cmpgesf" @@ -220,7 +220,7 @@ { cc_status.flags &= ~ CC_CONDITION_MASK; cc_status.flags |= CC_ONLY_LE; - return \"pfle.s %r0,%r1\"; + return \"pfle.s %r0,%r1,f0\"; }") (define_insn "cmpeqdf" @@ -231,7 +231,7 @@ { cc_status.flags &= ~ CC_CONDITION_MASK; cc_status.flags |= CC_ONLY_EQ; - return \"pfeq.d %r1,%r0\"; + return \"pfeq.d %r1,%r0,f0\"; }") (define_insn "cmpltdf" @@ -242,7 +242,7 @@ { cc_status.flags &= ~ CC_CONDITION_MASK; cc_status.flags |= CC_ONLY_LT; - return \"pfgt.d %r1,%r0\"; + return \"pfgt.d %r1,%r0,f0\"; }") (define_insn "cmpgtdf" @@ -253,7 +253,7 @@ { cc_status.flags &= ~ CC_CONDITION_MASK; cc_status.flags |= CC_ONLY_LT; - return \"pfgt.d %r0,%r1\"; + return \"pfgt.d %r0,%r1,f0\"; }") (define_insn "cmpledf" @@ -264,7 +264,7 @@ { cc_status.flags &= ~ CC_CONDITION_MASK; cc_status.flags |= CC_ONLY_LE; - return \"pfle.d %r1,%r0\"; + return \"pfle.d %r1,%r0,f0\"; }") (define_insn "cmpgedf" @@ -275,7 +275,7 @@ { cc_status.flags &= ~ CC_CONDITION_MASK; cc_status.flags |= CC_ONLY_LE; - return \"pfle.d %r0,%r1\"; + return \"pfle.d %r0,%r1,f0\"; }") (define_insn "" @@ -824,10 +824,10 @@ return \"ixfr %1,%0\"; return \"mov %1,%0\"; }") - + (define_insn "movhi" - [(set (match_operand:HI 0 "general_operand" "=r,m") - (match_operand:HI 1 "general_operand" "rmi,rJ"))] + [(set (match_operand:HI 0 "general_operand" "=r,m,!*f,!r") + (match_operand:HI 1 "general_operand" "rmi,rJ,rJ*f,*f"))] "" "* { @@ -843,12 +843,20 @@ return output_load (operands); return \"ld.s %1,%0\"; } + if (FP_REG_P (operands[1]) && FP_REG_P (operands[0])) + return \"fmov.ss %1,%0\"; + if (FP_REG_P (operands[1])) + return \"fxfr %1,%0\"; + if (FP_REG_P (operands[0]) && operands[1] == const0_rtx) + return \"fmov.ss f0,%0\"; + if (FP_REG_P (operands[0])) + return \"ixfr %1,%0\"; return \"mov %1,%0\"; }") (define_insn "movqi" - [(set (match_operand:QI 0 "general_operand" "=r,m") - (match_operand:QI 1 "general_operand" "rmi,rJ"))] + [(set (match_operand:QI 0 "general_operand" "=r,m,!*f,!r") + (match_operand:QI 1 "general_operand" "rmi,rJ,rJ*f,*f"))] "" "* { @@ -864,6 +872,14 @@ return output_load (operands); return \"ld.b %1,%0\"; } + if (FP_REG_P (operands[1]) && FP_REG_P (operands[0])) + return \"fmov.ss %1,%0\"; + if (FP_REG_P (operands[1])) + return \"fxfr %1,%0\"; + if (FP_REG_P (operands[0]) && operands[1] == const0_rtx) + return \"fmov.ss f0,%0\"; + if (FP_REG_P (operands[0])) + return \"ixfr %1,%0\"; return \"mov %1,%0\"; }") @@ -934,7 +950,7 @@ cc_status.mdep = XEXP (operands[0], 0); output_asm_insn (\"orh ha%%%m0,r0,r31\", operands); } - return \"st.l r0,l%%%%m0(r31)\;st.l r0,l%%%%m0+4(r31)\"; + return \"st.l r0,l%%%m0(r31)\;st.l r0,l%%%m0+4(r31)\"; } operands[1] = adj_offsettable_operand (operands[0], 4); return \"st.l r0,%0\;st.l r0,%1\"; @@ -962,7 +978,7 @@ (define_insn "movdi" [(set (match_operand:DI 0 "general_operand" "=rm,&r,?f,?rm") - (match_operand:DI 1 "general_operand" "r,mi,rfm,f"))] + (match_operand:DI 1 "general_operand" "r,miF,rfmG,f"))] "" "* { @@ -973,14 +989,20 @@ && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) return output_load (operands); + if (FP_REG_P (operands[0]) && operands[1] == dconst0_rtx) + return \"fmov.dd f0,%0\"; + if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) return output_fp_move_double (operands); return output_move_double (operands); }") +;; The alternative m/r is separate from m/f +;; so that an f-reg won't be used as a reload reg between m and F. +;; The first alternative is separate from the second for the same reason. (define_insn "movsf" - [(set (match_operand:SF 0 "general_operand" "=*rf,m") - (match_operand:SF 1 "general_operand" "*rfmG,*rf"))] + [(set (match_operand:SF 0 "general_operand" "=*rf,*rf,*r,m,m") + (match_operand:SF 1 "general_operand" "*r,fmG,F,*r,f"))] "" "* { @@ -1406,15 +1428,12 @@ ;; will be recognized as SImode (which is always valid) ;; rather than as QImode or HImode. -;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...))) -;; to be reloaded by putting the constant into memory. -;; It must come before the more general floatsisf2 pattern. (define_expand "floatsidf2" [(set (match_dup 2) (match_dup 3)) (set (match_dup 4) (xor:SI (match_operand:SI 1 "register_operand" "") (const_int -2147483648))) - (set (subreg:SI (match_dup 5) 1) (match_dup 4)) - (set (subreg:SI (match_dup 5) 0) (subreg:SI (match_dup 2) 0)) + (set (subreg:SI (match_dup 5) 0) (match_dup 4)) + (set (subreg:SI (match_dup 5) 1) (subreg:SI (match_dup 2) 1)) (set (match_operand:DF 0 "register_operand" "") (minus:DF (match_dup 5) (match_dup 2)))] "" @@ -1504,7 +1523,7 @@ (plus:DI (match_operand:DI 1 "register_operand" "%f") (match_operand:DI 2 "register_operand" "f")))] "" - "fiadd.ss %1,%2,%0") + "fiadd.dd %1,%2,%0") (define_insn "subsi3" [(set (match_operand:SI 0 "register_operand" "=r,r,*f") @@ -1531,7 +1550,7 @@ (minus:DI (match_operand:DI 1 "register_operand" "%f") (match_operand:DI 2 "register_operand" "f")))] "" - "fisub.ss %1,%2,%0") + "fisub.dd %1,%2,%0") (define_expand "mulsi3" [(set (subreg:SI (match_dup 4) 0) (match_operand:SI 1 "general_operand" "")) @@ -1575,7 +1594,7 @@ } xop[0] = operands[0]; xop[1] = operands[1]; - xop[2] = gen_rtx (CONST_INT, VOIDmode, ~(INTVAL (operands[2]) & 0xffff)); + xop[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]) & 0xffff); output_asm_insn (\"andnot %2,%1,%0\", xop); operands[2] = gen_rtx (CONST_INT, VOIDmode, ~(unsigned) INTVAL (operands[2]) >> 16);