--- gcc/config/i860.md	2018/04/24 16:54:41	1.1.1.2
+++ gcc/config/i860.md	2018/04/24 17:01:59	1.1.1.4
@@ -176,7 +176,7 @@
 {
   cc_status.flags &= ~ CC_CONDITION_MASK;
   cc_status.flags |= CC_ONLY_EQ;
-  return \"pfeq.s %r1,%r0,f0\";
+  return \"pfeq.ss %r1,%r0,f0\";
 }")
 
 (define_insn "cmpltsf"
@@ -187,7 +187,7 @@
 {
   cc_status.flags &= ~ CC_CONDITION_MASK;
   cc_status.flags |= CC_ONLY_LT;
-  return \"pfgt.s %r1,%r0,f0\";
+  return \"pfgt.ss %r1,%r0,f0\";
 }")
 
 (define_insn "cmpgtsf"
@@ -198,7 +198,7 @@
 {
   cc_status.flags &= ~ CC_CONDITION_MASK;
   cc_status.flags |= CC_ONLY_LT;
-  return \"pfgt.s %r0,%r1,f0\";
+  return \"pfgt.ss %r0,%r1,f0\";
 }")
 
 (define_insn "cmplesf"
@@ -209,7 +209,8 @@
 {
   cc_status.flags &= ~ CC_CONDITION_MASK;
   cc_status.flags |= CC_ONLY_LE;
-  return \"pfle.s %r1,%r0,f0\";
+  cc_status.flags |= CC_NEGATED;	/* added by markb */
+  return \"pfle.ss %r0,%r1,f0\";
 }")
 
 (define_insn "cmpgesf"
@@ -220,7 +221,8 @@
 {
   cc_status.flags &= ~ CC_CONDITION_MASK;
   cc_status.flags |= CC_ONLY_LE;
-  return \"pfle.s %r0,%r1,f0\";
+  cc_status.flags |= CC_NEGATED;	/* added by markb */
+  return \"pfle.ss %r1,%r0,f0\";
 }")
 
 (define_insn "cmpeqdf"
@@ -231,7 +233,7 @@
 {
   cc_status.flags &= ~ CC_CONDITION_MASK;
   cc_status.flags |= CC_ONLY_EQ;
-  return \"pfeq.d %r1,%r0,f0\";
+  return \"pfeq.dd %r1,%r0,f0\";
 }")
 
 (define_insn "cmpltdf"
@@ -242,7 +244,7 @@
 {
   cc_status.flags &= ~ CC_CONDITION_MASK;
   cc_status.flags |= CC_ONLY_LT;
-  return \"pfgt.d %r1,%r0,f0\";
+  return \"pfgt.dd %r1,%r0,f0\";
 }")
 
 (define_insn "cmpgtdf"
@@ -253,7 +255,7 @@
 {
   cc_status.flags &= ~ CC_CONDITION_MASK;
   cc_status.flags |= CC_ONLY_LT;
-  return \"pfgt.d %r0,%r1,f0\";
+  return \"pfgt.dd %r0,%r1,f0\";
 }")
 
 (define_insn "cmpledf"
@@ -264,7 +266,8 @@
 {
   cc_status.flags &= ~ CC_CONDITION_MASK;
   cc_status.flags |= CC_ONLY_LE;
-  return \"pfle.d %r1,%r0,f0\";
+  cc_status.flags |= CC_NEGATED;	/* added by markb */
+  return \"pfle.dd %r0,%r1,f0\";
 }")
 
 (define_insn "cmpgedf"
@@ -275,7 +278,8 @@
 {
   cc_status.flags &= ~ CC_CONDITION_MASK;
   cc_status.flags |= CC_ONLY_LE;
-  return \"pfle.d %r0,%r1,f0\";
+  cc_status.flags |= CC_NEGATED;	/* added by markb */
+  return \"pfle.dd %r1,%r0,f0\";
 }")
 
 (define_insn ""
@@ -824,7 +828,7 @@
     return \"ixfr %1,%0\";
   return \"mov %1,%0\";
 }")
- 
+
 (define_insn "movhi"
   [(set (match_operand:HI 0 "general_operand" "=r,m,!*f,!r")
 	(match_operand:HI 1 "general_operand" "rmi,rJ,rJ*f,*f"))]
@@ -971,14 +975,16 @@
       && CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
     return output_load (operands);
 
-  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
+  /* Note that the only CONST_DOUBLE that should be possible is 0.  */
+  if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])
+      || GET_CODE (operands[1]) == CONST_DOUBLE)
     return output_fp_move_double (operands);
   return output_move_double (operands);
 }")
 
 (define_insn "movdi"
   [(set (match_operand:DI 0 "general_operand" "=rm,&r,?f,?rm")
-	(match_operand:DI 1 "general_operand" "r,miF,rfmG,f"))]
+	(match_operand:DI 1 "general_operand" "r,miF,rfmG,fG"))]
   ""
   "*
 {
@@ -1002,7 +1008,7 @@
 ;; The first alternative is separate from the second for the same reason.
 (define_insn "movsf"
   [(set (match_operand:SF 0 "general_operand" "=*rf,*rf,*r,m,m")
-	(match_operand:SF 1 "general_operand" "*r,fmG,F,*r,f"))]
+	(match_operand:SF 1 "general_operand" "*r,fmG,F,*r,fG"))]
   ""
   "*
 {
@@ -1022,16 +1028,24 @@
         return \"fmov.ss f0,%0\";
       if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
 	{
+	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
+		 && (cc_prev_status.flags & CC_HI_R31_ADJ)
+		 && cc_prev_status.mdep == XEXP(operands[1],0)))
+	    output_asm_insn(\"orh ha%%%m1,r0,r31\",operands);
 	  cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
 	  cc_status.mdep = XEXP (operands[1], 0);
-	  return \"orh ha%%%m1,r0,r31\;fld.l l%%%m1(r31),%0\";
+	  return \"fld.l l%%%m1(r31),%0\";
 	}
       return \"fld.l %1,%0\";
     }
-  if (FP_REG_P (operands[1]))
+  if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
     {
-      if (GET_CODE (operands[0]) == REG)
+      if (GET_CODE (operands[0]) == REG && FP_REG_P (operands[1]))
 	return \"fxfr %1,%0\";
+      if (GET_CODE (operands[0]) == REG)
+        return \"mov %1,%0\";
+      /* Now operand 0 must be memory.
+         If operand 1 is CONST_DOUBLE, its value must be 0.  */
       if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
 	{
 	  if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
@@ -1059,7 +1073,7 @@
 ;; Such addresses are not "legitimate" because st rejects them.
 
 (define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "rf")
+  [(set (match_operand:DF 0 "register_operand" "=rf")
 	(match_operand:DF 1 "indexed_operand" "m"))]
   ""
   "*
@@ -1070,7 +1084,7 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "rf")
+  [(set (match_operand:SF 0 "register_operand" "=rf")
 	(match_operand:SF 1 "indexed_operand" "m"))]
   ""
   "*
@@ -1081,7 +1095,7 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "rf")
+  [(set (match_operand:SI 0 "register_operand" "=rf")
 	(match_operand:SI 1 "indexed_operand" "m"))]
   ""
   "*
@@ -1092,13 +1106,13 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:HI 0 "register_operand" "r")
+  [(set (match_operand:HI 0 "register_operand" "=r")
 	(match_operand:HI 1 "indexed_operand" "m"))]
   ""
   "ld.s %1,%0")
 
 (define_insn ""
-  [(set (match_operand:QI 0 "register_operand" "r")
+  [(set (match_operand:QI 0 "register_operand" "=r")
 	(match_operand:QI 1 "indexed_operand" "m"))]
   ""
   "ld.b %1,%0")
@@ -1106,13 +1120,13 @@
 ;; Likewise for floating-point store insns.
 
 (define_insn ""
-  [(set (match_operand:DF 0 "indexed_operand" "m")
+  [(set (match_operand:DF 0 "indexed_operand" "=m")
 	(match_operand:DF 1 "register_operand" "f"))]
   ""
   "fst.d %1,%0")
 
 (define_insn ""
-  [(set (match_operand:SF 0 "indexed_operand" "m")
+  [(set (match_operand:SF 0 "indexed_operand" "=m")
 	(match_operand:SF 1 "register_operand" "f"))]
   ""
   "fst.l %1,%0")
@@ -1318,7 +1332,7 @@
 	 (sign_extend:SI
 	  (match_operand:QI 1 "register_operand" "r"))
 	 (match_operand:SI 2 "logic_int" "n")))]
-  ""
+  "INTVAL (operands[2]) < 8"
   "*
 {
   return \"shl 24,%1,%0\;shra 24+%2,%0,%0\";
@@ -1331,7 +1345,7 @@
 	  (subreg:QI (ashift:SI (match_operand:SI 1 "register_operand" "r")
 				(match_operand:SI 2 "logic_int" "n")) 0))
 	 (match_operand:SI 3 "logic_int" "n")))]
-  ""
+  "INTVAL (operands[3]) < 8"
   "*
 {
   return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\";
@@ -1344,7 +1358,7 @@
 	  (ashift:QI (match_operand:QI 1 "register_operand" "r")
 		     (match_operand:QI 2 "logic_int" "n")))
 	 (match_operand:SI 3 "logic_int" "n")))]
-  ""
+  "INTVAL (operands[3]) < 8"
   "*
 {
   return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\";
@@ -1373,7 +1387,7 @@
 
 ;; next two patterns are good for bitfields coming from memory
 ;; (via pseudo-register) or from a register, though this optimization
-;; is only good for values contained wholly within the bottom 13 bits
+;; is only good for values contained wholly within the bottom 16 bits
 (define_insn ""
   [(set (cc0)
 	(eq 
@@ -1574,7 +1588,7 @@
   ""
   "fmlow.dd %2,%1,%0")
 
-;;- and instructions (with compliment also)			   
+;;- and instructions (with complement also)			   
 (define_insn "andsi3"
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(and:SI (match_operand:SI 1 "nonmemory_operand" "%r")
@@ -1940,7 +1954,7 @@
 }")
 
 (define_expand "call_value"
-  [(set (match_operand 0 "register_operand" "rf")
+  [(set (match_operand 0 "register_operand" "=rf")
 	(call (match_operand:SI 1 "memory_operand" "m")
 	      (match_operand 2 "" "i")))]
   ;; operand 3 is next_arg_register
@@ -2010,7 +2024,7 @@
   "nop")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "r")
+  [(set (match_operand:SI 0 "register_operand" "=r")
 	(mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
 			 (label_ref (match_operand 2 "" "")))))]
   ""