--- gcc/config/i860.md	2018/04/24 17:51:32	1.1
+++ gcc/config/i860.md	2018/04/24 18:04:08	1.1.1.3
@@ -497,78 +497,8 @@
 }")
 
 ;; Simple BTE/BTNE compare-and-branch insns made by combining.
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (eq (match_operand:QI 0 "register_operand" "r")
-			  (match_operand:QI 1 "bte_operand" "rK"))
-		      (label_ref (match_operand 2 "" ""))
-		      (pc)))]
-  ""
-  "bte %1,%0,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (ne (match_operand:QI 0 "register_operand" "r")
-			  (match_operand:QI 1 "bte_operand" "rK"))
-		      (label_ref (match_operand 2 "" ""))
-		      (pc)))]
-  ""
-  "btne %1,%0,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (eq (match_operand:QI 0 "register_operand" "r")
-			  (match_operand:QI 1 "bte_operand" "rK"))
-		      (pc)
-		      (label_ref (match_operand 2 "" ""))))]
-  ""
-  "btne %1,%0,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (ne (match_operand:QI 0 "register_operand" "r")
-			  (match_operand:QI 1 "bte_operand" "rK"))
-		      (pc)
-		      (label_ref (match_operand 2 "" ""))))]
-  ""
-  "bte %1,%0,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (eq (match_operand:HI 0 "register_operand" "r")
-			  (match_operand:HI 1 "bte_operand" "rK"))
-		      (label_ref (match_operand 2 "" ""))
-		      (pc)))]
-  ""
-  "bte %1,%0,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (ne (match_operand:HI 0 "register_operand" "r")
-			  (match_operand:HI 1 "bte_operand" "rK"))
-		      (label_ref (match_operand 2 "" ""))
-		      (pc)))]
-  ""
-  "btne %1,%0,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (eq (match_operand:HI 0 "register_operand" "r")
-			  (match_operand:HI 1 "bte_operand" "rK"))
-		      (pc)
-		      (label_ref (match_operand 2 "" ""))))]
-  ""
-  "btne %1,%0,%2")
-
-(define_insn ""
-  [(set (pc)
-        (if_then_else (ne (match_operand:HI 0 "register_operand" "r")
-			  (match_operand:HI 1 "bte_operand" "rK"))
-		      (pc)
-		      (label_ref (match_operand 2 "" ""))))]
-  ""
-  "bte %1,%0,%2")
+;; Note that it is wrong to add similar patterns for QI or HImode
+;; because bte/btne always compare the whole register.
 
 (define_insn ""
   [(set (pc)
@@ -1646,8 +1576,8 @@
   [(set (match_dup 2) (match_dup 3))
    (set (match_dup 4) (xor:SI (match_operand:SI 1 "register_operand" "")
 			      (const_int -2147483648)))
+   (set (match_dup 5) (match_dup 3))
    (set (subreg:SI (match_dup 5) 0) (match_dup 4))
-   (set (subreg:SI (match_dup 5) 1) (subreg:SI (match_dup 2) 1))
    (set (match_operand:DF 0 "register_operand" "")
 	(minus:DF (match_dup 5) (match_dup 2)))]
   ""
@@ -1769,6 +1699,38 @@
   ""
   "
 {
+  if (WORDS_BIG_ENDIAN)
+    emit_insn (gen_mulsi3_big (operands[0], operands[1], operands[2]));
+  else
+    emit_insn (gen_mulsi3_little (operands[0], operands[1], operands[2]));
+  DONE;
+}")
+
+(define_expand "mulsi3_little"
+  [(set (subreg:SI (match_dup 4) 0) (match_operand:SI 1 "general_operand" ""))
+   (set (subreg:SI (match_dup 5) 0) (match_operand:SI 2 "general_operand" ""))
+   (clobber (match_dup 3))
+   (set (subreg:SI (match_dup 3) 0)
+	(mult:SI (subreg:SI (match_dup 4) 0) (subreg:SI (match_dup 5) 0)))
+   (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 0))]
+  "! WORDS_BIG_ENDIAN"
+  "
+{
+  operands[3] = gen_reg_rtx (DImode);
+  operands[4] = gen_reg_rtx (DImode);
+  operands[5] = gen_reg_rtx (DImode);
+}")
+
+(define_expand "mulsi3_big"
+  [(set (subreg:SI (match_dup 4) 1) (match_operand:SI 1 "general_operand" ""))
+   (set (subreg:SI (match_dup 5) 1) (match_operand:SI 2 "general_operand" ""))
+   (clobber (match_dup 3))
+   (set (subreg:SI (match_dup 3) 1)
+	(mult:SI (subreg:SI (match_dup 4) 1) (subreg:SI (match_dup 5) 1)))
+   (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 1))]
+  "WORDS_BIG_ENDIAN"
+  "
+{
   operands[3] = gen_reg_rtx (DImode);
   operands[4] = gen_reg_rtx (DImode);
   operands[5] = gen_reg_rtx (DImode);
@@ -1778,7 +1740,14 @@
   [(set (subreg:SI (match_operand:DI 0 "register_operand" "=f") 0)
 	(mult:SI (subreg:SI (match_operand:DI 1 "register_operand" "f") 0)
 		 (subreg:SI (match_operand:DI 2 "register_operand" "f") 0)))]
-  ""
+  "! WORDS_BIG_ENDIAN"
+  "fmlow.dd %2,%1,%0")
+
+(define_insn ""
+  [(set (subreg:SI (match_operand:DI 0 "register_operand" "=f") 1)
+	(mult:SI (subreg:SI (match_operand:DI 1 "register_operand" "f") 1)
+		 (subreg:SI (match_operand:DI 2 "register_operand" "f") 1)))]
+  "WORDS_BIG_ENDIAN"
   "fmlow.dd %2,%1,%0")
 
 ;;- and instructions (with compliment also)