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1.1 ! root 1: ;;- Machine description for Intel 860 chip for GNU C compiler ! 2: ;; Copyright (C) 1989 Free Software Foundation, Inc. ! 3: ! 4: ;; This file is part of GNU CC. ! 5: ! 6: ;; GNU CC is free software; you can redistribute it and/or modify ! 7: ;; it under the terms of the GNU General Public License as published by ! 8: ;; the Free Software Foundation; either version 1, or (at your option) ! 9: ;; any later version. ! 10: ! 11: ;; GNU CC is distributed in the hope that it will be useful, ! 12: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 13: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 14: ;; GNU General Public License for more details. ! 15: ! 16: ;; You should have received a copy of the GNU General Public License ! 17: ;; along with GNU CC; see the file COPYING. If not, write to ! 18: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 19: ! 20: ! 21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 22: ! 23: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ! 24: ;;- updates for most instructions. ! 25: ! 26: ;;- Operand classes for the register allocator: ! 27: ! 28: /* Bit-test instructions. */ ! 29: ! 30: (define_insn "" ! 31: [(set (cc0) (eq (and:SI (match_operand:SI 0 "register_operand" "r") ! 32: (match_operand:SI 1 "logic_operand" "rL")) ! 33: (const_int 0)))] ! 34: "" ! 35: "* ! 36: { ! 37: cc_status.flags |= CC_ONLY_EQ; ! 38: return \"and %1,%0,r0\"; ! 39: }") ! 40: ! 41: (define_insn "" ! 42: [(set (cc0) (ne (and:SI (match_operand:SI 0 "register_operand" "r") ! 43: (match_operand:SI 1 "logic_operand" "rL")) ! 44: (const_int 0)))] ! 45: "" ! 46: "* ! 47: { ! 48: cc_status.flags |= CC_NEGATED; ! 49: cc_status.flags |= CC_ONLY_EQ; ! 50: return \"and %1,%0,r0\"; ! 51: }") ! 52: ! 53: (define_insn "" ! 54: [(set (cc0) (eq (and:SI (match_operand:SI 0 "register_operand" "r") ! 55: (match_operand:SI 1 "immediate_operand" "i")) ! 56: (const_int 0)))] ! 57: "GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) & 0xffff) == 0" ! 58: "* ! 59: { ! 60: cc_status.flags |= CC_ONLY_EQ; ! 61: return \"andh h%%%1,%0,r0\"; ! 62: }") ! 63: ! 64: (define_insn "" ! 65: [(set (cc0) (ne (and:SI (match_operand:SI 0 "register_operand" "r") ! 66: (match_operand:SI 1 "immediate_operand" "i")) ! 67: (const_int 0)))] ! 68: "GET_CODE (operands[1]) == CONST_INT && (INTVAL (operands[1]) & 0xffff) == 0" ! 69: "* ! 70: { ! 71: cc_status.flags |= CC_NEGATED; ! 72: cc_status.flags |= CC_ONLY_EQ; ! 73: return \"andh h%%%1,%0,r0\"; ! 74: }") ! 75: ! 76: (define_insn "" ! 77: [(set (cc0) (eq (ashiftrt:SI ! 78: (sign_extend:SI ! 79: (ashift:QI (match_operand:QI 0 "register_operand" "r") ! 80: (match_operand:QI 1 "logic_int" "n"))) ! 81: (match_operand:SI 2 "logic_int" "n")) ! 82: (const_int 0)))] ! 83: "" ! 84: "* ! 85: { ! 86: int width = 8 - INTVAL (operands[2]); ! 87: int pos = 8 - width - INTVAL (operands[1]); ! 88: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 89: ~((-1) << width) << pos); ! 90: return \"and %2,%0,r0\"; ! 91: }") ! 92: ! 93: ;; Compare instructions. ! 94: ;; This controls RTL generation and register allocation. ! 95: ! 96: ;; Put cmpsi first among compare insns so it matches two CONST_INT operands. ! 97: ! 98: (define_insn "cmpeqsi" ! 99: [(set (cc0) (eq (match_operand:SI 0 "logic_operand" "r,rL") ! 100: (match_operand:SI 1 "logic_operand" "L,r")))] ! 101: "" ! 102: "* ! 103: { ! 104: cc_status.flags &= ~ CC_CONDITION_MASK; ! 105: cc_status.flags |= CC_ONLY_EQ; ! 106: if (REG_P (operands[0])) ! 107: return \"xor %1,%0,r0\"; ! 108: return \"xor %0,%1,r0\"; ! 109: }") ! 110: ! 111: (define_insn "cmpltsi" ! 112: [(set (cc0) (lt (match_operand:SI 0 "arith_operand" "r,rI") ! 113: (match_operand:SI 1 "arith_operand" "I,r")))] ! 114: "" ! 115: "* ! 116: { ! 117: cc_status.flags &= ~ CC_CONDITION_MASK; ! 118: cc_status.flags |= CC_ONLY_LT; ! 119: if (REG_P (operands[1])) ! 120: return \"subs %0,%1,r0\"; ! 121: cc_status.flags |= CC_REVERSED; ! 122: operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); ! 123: return \"adds %1,%0,r0\"; ! 124: }") ! 125: ! 126: (define_insn "cmpgtsi" ! 127: [(set (cc0) (gt (match_operand:SI 0 "arith_operand" "r,rI") ! 128: (match_operand:SI 1 "arith_operand" "I,r")))] ! 129: "" ! 130: "* ! 131: { ! 132: cc_status.flags &= ~ CC_CONDITION_MASK; ! 133: cc_status.flags |= CC_ONLY_LT; ! 134: if (REG_P (operands[0])) ! 135: return \"subs %1,%0,r0\"; ! 136: cc_status.flags |= CC_REVERSED; ! 137: operands[0] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[0])); ! 138: return \"adds %0,%1,r0\"; ! 139: }") ! 140: ! 141: (define_insn "cmpgeusi" ! 142: [(set (cc0) (geu (match_operand:SI 0 "arith_operand" "r,rI") ! 143: (match_operand:SI 1 "arith_operand" "I,r")))] ! 144: "" ! 145: "* ! 146: { ! 147: cc_status.flags &= ~ CC_CONDITION_MASK; ! 148: cc_status.flags |= CC_ONLY_LEU; ! 149: if (REG_P (operands[1])) ! 150: return \"subu %0,%1,r0\"; ! 151: cc_status.flags |= CC_REVERSED; ! 152: operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); ! 153: return \"addu %1,%0,r0\"; ! 154: }") ! 155: ! 156: (define_insn "cmpleusi" ! 157: [(set (cc0) (leu (match_operand:SI 0 "arith_operand" "r,rI") ! 158: (match_operand:SI 1 "arith_operand" "I,r")))] ! 159: "" ! 160: "* ! 161: { ! 162: cc_status.flags &= ~ CC_CONDITION_MASK; ! 163: cc_status.flags |= CC_ONLY_LEU; ! 164: if (REG_P (operands[0])) ! 165: return \"subu %1,%0,r0\"; ! 166: cc_status.flags |= CC_REVERSED; ! 167: operands[0] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[0])); ! 168: return \"addu %0,%1,r0\"; ! 169: }") ! 170: ! 171: (define_insn "cmpeqsf" ! 172: [(set (cc0) (eq (match_operand:SF 0 "reg_or_0_operand" "fG") ! 173: (match_operand:SF 1 "reg_or_0_operand" "fG")))] ! 174: "" ! 175: "* ! 176: { ! 177: cc_status.flags &= ~ CC_CONDITION_MASK; ! 178: cc_status.flags |= CC_ONLY_EQ; ! 179: return \"pfeq.s %r1,%r0\"; ! 180: }") ! 181: ! 182: (define_insn "cmpltsf" ! 183: [(set (cc0) (lt (match_operand:SF 0 "reg_or_0_operand" "fG") ! 184: (match_operand:SF 1 "reg_or_0_operand" "fG")))] ! 185: "" ! 186: "* ! 187: { ! 188: cc_status.flags &= ~ CC_CONDITION_MASK; ! 189: cc_status.flags |= CC_ONLY_LT; ! 190: return \"pfgt.s %r1,%r0\"; ! 191: }") ! 192: ! 193: (define_insn "cmpgtsf" ! 194: [(set (cc0) (gt (match_operand:SF 0 "reg_or_0_operand" "fG") ! 195: (match_operand:SF 1 "reg_or_0_operand" "fG")))] ! 196: "" ! 197: "* ! 198: { ! 199: cc_status.flags &= ~ CC_CONDITION_MASK; ! 200: cc_status.flags |= CC_ONLY_LT; ! 201: return \"pfgt.s %r0,%r1\"; ! 202: }") ! 203: ! 204: (define_insn "cmplesf" ! 205: [(set (cc0) (le (match_operand:SF 0 "reg_or_0_operand" "fG") ! 206: (match_operand:SF 1 "reg_or_0_operand" "fG")))] ! 207: "" ! 208: "* ! 209: { ! 210: cc_status.flags &= ~ CC_CONDITION_MASK; ! 211: cc_status.flags |= CC_ONLY_LE; ! 212: return \"pfle.s %r1,%r0\"; ! 213: }") ! 214: ! 215: (define_insn "cmpgesf" ! 216: [(set (cc0) (ge (match_operand:SF 0 "reg_or_0_operand" "fG") ! 217: (match_operand:SF 1 "reg_or_0_operand" "fG")))] ! 218: "" ! 219: "* ! 220: { ! 221: cc_status.flags &= ~ CC_CONDITION_MASK; ! 222: cc_status.flags |= CC_ONLY_LE; ! 223: return \"pfle.s %r0,%r1\"; ! 224: }") ! 225: ! 226: (define_insn "cmpeqdf" ! 227: [(set (cc0) (eq (match_operand:DF 0 "reg_or_0_operand" "fG") ! 228: (match_operand:DF 1 "reg_or_0_operand" "fG")))] ! 229: "" ! 230: "* ! 231: { ! 232: cc_status.flags &= ~ CC_CONDITION_MASK; ! 233: cc_status.flags |= CC_ONLY_EQ; ! 234: return \"pfeq.d %r1,%r0\"; ! 235: }") ! 236: ! 237: (define_insn "cmpltdf" ! 238: [(set (cc0) (lt (match_operand:DF 0 "reg_or_0_operand" "fG") ! 239: (match_operand:DF 1 "reg_or_0_operand" "fG")))] ! 240: "" ! 241: "* ! 242: { ! 243: cc_status.flags &= ~ CC_CONDITION_MASK; ! 244: cc_status.flags |= CC_ONLY_LT; ! 245: return \"pfgt.d %r1,%r0\"; ! 246: }") ! 247: ! 248: (define_insn "cmpgtdf" ! 249: [(set (cc0) (gt (match_operand:DF 0 "reg_or_0_operand" "fG") ! 250: (match_operand:DF 1 "reg_or_0_operand" "fG")))] ! 251: "" ! 252: "* ! 253: { ! 254: cc_status.flags &= ~ CC_CONDITION_MASK; ! 255: cc_status.flags |= CC_ONLY_LT; ! 256: return \"pfgt.d %r0,%r1\"; ! 257: }") ! 258: ! 259: (define_insn "cmpledf" ! 260: [(set (cc0) (le (match_operand:DF 0 "reg_or_0_operand" "fG") ! 261: (match_operand:DF 1 "reg_or_0_operand" "fG")))] ! 262: "" ! 263: "* ! 264: { ! 265: cc_status.flags &= ~ CC_CONDITION_MASK; ! 266: cc_status.flags |= CC_ONLY_LE; ! 267: return \"pfle.d %r1,%r0\"; ! 268: }") ! 269: ! 270: (define_insn "cmpgedf" ! 271: [(set (cc0) (ge (match_operand:DF 0 "reg_or_0_operand" "fG") ! 272: (match_operand:DF 1 "reg_or_0_operand" "fG")))] ! 273: "" ! 274: "* ! 275: { ! 276: cc_status.flags &= ~ CC_CONDITION_MASK; ! 277: cc_status.flags |= CC_ONLY_LE; ! 278: return \"pfle.d %r0,%r1\"; ! 279: }") ! 280: ! 281: (define_insn "" ! 282: [(set (cc0) (eq (zero_extend:SI (match_operand:HI 0 "load_operand" "m")) ! 283: (match_operand:SI 1 "small_int" "I")))] ! 284: "INTVAL (operands[1]) >= 0" ! 285: "ld.s %0,r31\;xor %1,r31,r0") ! 286: ! 287: (define_insn "" ! 288: [(set (cc0) (eq (match_operand:SI 0 "small_int" "I") ! 289: (zero_extend:SI (match_operand:HI 1 "load_operand" "m"))))] ! 290: "INTVAL (operands[0]) >= 0" ! 291: "ld.s %1,r31\;xor %0,r31,r0") ! 292: ! 293: ;; Define the real conditional branch instructions. ! 294: ! 295: (define_insn "cbranch" ! 296: [(set (pc) (if_then_else (cc0) (label_ref (match_operand 0 "" "")) (pc)))] ! 297: "" ! 298: "* ! 299: { ! 300: if (cc_prev_status.flags & CC_NEGATED) ! 301: return \"bnc %l0\"; ! 302: else ! 303: return \"bc %l0\"; ! 304: }") ! 305: ! 306: (define_insn "inverse_cbranch" ! 307: [(set (pc) (if_then_else (cc0) (pc) (label_ref (match_operand 0 "" ""))))] ! 308: "" ! 309: "* ! 310: { ! 311: if (cc_prev_status.flags & CC_NEGATED) ! 312: return \"bc %l0\"; ! 313: else ! 314: return \"bnc %l0\"; ! 315: }") ! 316: ! 317: ;; Other conditional branches, made by combining. ! 318: ! 319: (define_insn "" ! 320: [(set (pc) (if_then_else (eq (match_operand:SI 0 "bte_operand" "%rK") ! 321: (match_operand:SI 1 "bte_operand" "rJ")) ! 322: (label_ref (match_operand 2 "" "")) ! 323: (pc)))] ! 324: "GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG" ! 325: "bte %0,%r1,%2") ! 326: ! 327: (define_insn "" ! 328: [(set (pc) (if_then_else (eq (match_operand:SI 0 "bte_operand" "%rK") ! 329: (match_operand:SI 1 "bte_operand" "rJ")) ! 330: (pc) ! 331: (label_ref (match_operand 2 "" ""))))] ! 332: "GET_CODE (operands[0]) == REG || GET_CODE (operands[1]) == REG" ! 333: "btne %0,%r1,%2") ! 334: ! 335: ;; Optimize fetching an unsigned half word and comparing against constant. ! 336: ;; No need to zero-extend. ! 337: ! 338: (define_insn "" ! 339: [(set (pc) (if_then_else (eq (zero_extend:SI (match_operand:HI 0 "load_operand" "m")) ! 340: (match_operand:SI 1 "immediate_operand" "K")) ! 341: (label_ref (match_operand 2 "" "")) ! 342: (pc)))] ! 343: "GET_CODE (operands[1]) == CONST_INT ! 344: && INTVAL (operands[1]) < 0x10 && INTVAL (operands[1]) >= 0" ! 345: "ld.s %0,r31\;bte %1,r31,%2") ! 346: ! 347: (define_insn "" ! 348: [(set (pc) (if_then_else (eq (match_operand:SI 0 "immediate_operand" "K") ! 349: (zero_extend:SI (match_operand:HI 1 "load_operand" "m"))) ! 350: (label_ref (match_operand 2 "" "")) ! 351: (pc)))] ! 352: "GET_CODE (operands[0]) == CONST_INT ! 353: && INTVAL (operands[0]) < 0x10 && INTVAL (operands[0]) >= 0" ! 354: "ld.s %1,r31\;bte %0,r31,%2") ! 355: ! 356: (define_insn "" ! 357: [(set (pc) (if_then_else (eq (zero_extend:SI (match_operand:HI 0 "load_operand" "m")) ! 358: (match_operand:SI 1 "immediate_operand" "K")) ! 359: (pc) ! 360: (label_ref (match_operand 2 "" ""))))] ! 361: "GET_CODE (operands[1]) == CONST_INT ! 362: && INTVAL (operands[1]) < 0x10 && INTVAL (operands[1]) >= 0" ! 363: "ld.s %0,r31\;btne %1,r31,%2") ! 364: ! 365: (define_insn "" ! 366: [(set (pc) (if_then_else (eq (match_operand:SI 0 "immediate_operand" "K") ! 367: (zero_extend:SI (match_operand:HI 1 "load_operand" "m"))) ! 368: (pc) ! 369: (label_ref (match_operand 2 "" ""))))] ! 370: "GET_CODE (operands[0]) == CONST_INT ! 371: && INTVAL (operands[0]) < 0x10 && INTVAL (operands[0]) >= 0" ! 372: "ld.s %1,r31\;btne %0,r31,%2") ! 373: ! 374: (define_insn "" ! 375: [(set (pc) (if_then_else (eq (zero_extend:SI (match_operand:QI 0 "load_operand" "m")) ! 376: (match_operand:SI 1 "immediate_operand" "K")) ! 377: (label_ref (match_operand 2 "" "")) ! 378: (pc)))] ! 379: "GET_CODE (operands[1]) == CONST_INT ! 380: && INTVAL (operands[1]) < 0x10 && INTVAL (operands[1]) >= 0" ! 381: "ld.b %0,r31\;bte %1,r31,%2") ! 382: ! 383: (define_insn "" ! 384: [(set (pc) (if_then_else (eq (match_operand:SI 0 "immediate_operand" "K") ! 385: (zero_extend:SI (match_operand:QI 1 "load_operand" "m"))) ! 386: (label_ref (match_operand 2 "" "")) ! 387: (pc)))] ! 388: "GET_CODE (operands[0]) == CONST_INT ! 389: && INTVAL (operands[0]) < 0x10 && INTVAL (operands[0]) >= 0" ! 390: "ld.b %1,r31\;bte %0,r31,%2") ! 391: ! 392: (define_insn "" ! 393: [(set (pc) (if_then_else (eq (zero_extend:SI (match_operand:QI 0 "load_operand" "m")) ! 394: (match_operand:SI 1 "immediate_operand" "K")) ! 395: (pc) ! 396: (label_ref (match_operand 2 "" ""))))] ! 397: "GET_CODE (operands[1]) == CONST_INT ! 398: && INTVAL (operands[1]) < 0x10 && INTVAL (operands[1]) >= 0" ! 399: "ld.b %0,r31\;btne %1,r31,%2") ! 400: ! 401: (define_insn "" ! 402: [(set (pc) (if_then_else (eq (match_operand:SI 0 "immediate_operand" "K") ! 403: (zero_extend:SI (match_operand:QI 1 "load_operand" "m"))) ! 404: (pc) ! 405: (label_ref (match_operand 2 "" ""))))] ! 406: "GET_CODE (operands[0]) == CONST_INT ! 407: && INTVAL (operands[0]) < 0x10 && INTVAL (operands[0]) >= 0" ! 408: "ld.b %1,r31\;btne %0,r31,%2") ! 409: ! 410: ;; Generation of conditionals. ! 411: ! 412: ;; The first step is the emission of a standard-looking compare insn. ! 413: ;; Then a standard-named conditional branch pattern is run. ! 414: ;; That branch pattern looks back at the compare insn and deletes it. ! 415: ;; It then emits a machine-specific compare insn and a branch-if-true ! 416: ;; or a branch-if-false. ! 417: ! 418: ;; These patterns have `abort' because they are supposed to be deleted ! 419: ;; in that fashion. ! 420: ! 421: (define_insn "cmpsi" ! 422: [(set (cc0) (compare (match_operand:SI 0 "compare_operand" "") ! 423: (match_operand:SI 1 "compare_operand" "")))] ! 424: "" ! 425: "* abort ();") ! 426: ! 427: (define_insn "cmpsf" ! 428: [(set (cc0) (compare (match_operand:SF 0 "register_operand" "") ! 429: (match_operand:SF 1 "register_operand" "")))] ! 430: "" ! 431: "* abort ();") ! 432: ! 433: (define_insn "cmpdf" ! 434: [(set (cc0) (compare (match_operand:DF 0 "register_operand" "") ! 435: (match_operand:DF 1 "register_operand" "")))] ! 436: "" ! 437: "* abort ();") ! 438: ! 439: ;; These are the standard-named conditional branch patterns. ! 440: ;; Detailed comments are found in the first one only. ! 441: ! 442: (define_expand "beq" ! 443: [(set (pc) ! 444: (if_then_else (eq (cc0) ! 445: (const_int 0)) ! 446: (label_ref (match_operand 0 "" "")) ! 447: (pc)))] ! 448: "" ! 449: " ! 450: { ! 451: rtx label = operands[0]; ! 452: enum insn_code code; ! 453: rtx prev; ! 454: ! 455: /* Get out of the sequence just started for us. */ ! 456: ! 457: end_sequence (); ! 458: prev = get_last_insn (); ! 459: ! 460: /* Examine the preceding compare insn, and get rid of it. */ ! 461: ! 462: code = recog_memoized (prev); ! 463: insn_extract (prev); ! 464: NEXT_INSN (PREV_INSN (prev)) = 0; ! 465: set_last_insn (PREV_INSN (prev)); ! 466: ! 467: /* Now once again start a sequence for our new instructions. */ ! 468: ! 469: start_sequence (); ! 470: ! 471: /* Emit a single-condition compare insn according to ! 472: the type of operands and the condition to be tested. */ ! 473: ! 474: if (code == CODE_FOR_cmpsi) ! 475: emit_insn (gen_cmpeqsi (recog_operand[0], recog_operand[1])); ! 476: else if (code == CODE_FOR_cmpsf) ! 477: emit_insn (gen_cmpeqsf (recog_operand[0], recog_operand[1])); ! 478: else if (code == CODE_FOR_cmpdf) ! 479: emit_insn (gen_cmpeqdf (recog_operand[0], recog_operand[1])); ! 480: else ! 481: abort (); ! 482: ! 483: /* Emit branch-if-true. */ ! 484: ! 485: emit_jump_insn (gen_cbranch (label)); ! 486: ! 487: DONE; ! 488: }") ! 489: ! 490: (define_expand "bne" ! 491: [(set (pc) ! 492: (if_then_else (ne (cc0) ! 493: (const_int 0)) ! 494: (label_ref (match_operand 0 "" "")) ! 495: (pc)))] ! 496: "" ! 497: " ! 498: { ! 499: rtx label = operands[0]; ! 500: enum insn_code code; ! 501: rtx prev; ! 502: ! 503: end_sequence (); ! 504: prev = get_last_insn (); ! 505: ! 506: code = recog_memoized (prev); ! 507: insn_extract (prev); ! 508: NEXT_INSN (PREV_INSN (prev)) = 0; ! 509: set_last_insn (PREV_INSN (prev)); ! 510: start_sequence (); ! 511: ! 512: if (code == CODE_FOR_cmpsi) ! 513: emit_insn (gen_cmpeqsi (recog_operand[0], recog_operand[1])); ! 514: else if (code == CODE_FOR_cmpsf) ! 515: emit_insn (gen_cmpeqsf (recog_operand[0], recog_operand[1])); ! 516: else if (code == CODE_FOR_cmpdf) ! 517: emit_insn (gen_cmpeqdf (recog_operand[0], recog_operand[1])); ! 518: else ! 519: abort (); ! 520: emit_jump_insn (gen_inverse_cbranch (label)); ! 521: ! 522: DONE; ! 523: }") ! 524: ! 525: (define_expand "bgt" ! 526: [(set (pc) ! 527: (if_then_else (gt (cc0) ! 528: (const_int 0)) ! 529: (label_ref (match_operand 0 "" "")) ! 530: (pc)))] ! 531: "" ! 532: " ! 533: { ! 534: rtx label = operands[0]; ! 535: enum insn_code code; ! 536: rtx prev; ! 537: ! 538: end_sequence (); ! 539: prev = get_last_insn (); ! 540: ! 541: code = recog_memoized (prev); ! 542: insn_extract (prev); ! 543: NEXT_INSN (PREV_INSN (prev)) = 0; ! 544: set_last_insn (PREV_INSN (prev)); ! 545: start_sequence (); ! 546: ! 547: if (code == CODE_FOR_cmpsi) ! 548: emit_insn (gen_cmpgtsi (recog_operand[0], recog_operand[1])); ! 549: else if (code == CODE_FOR_cmpsf) ! 550: emit_insn (gen_cmpgtsf (recog_operand[0], recog_operand[1])); ! 551: else if (code == CODE_FOR_cmpdf) ! 552: emit_insn (gen_cmpgtdf (recog_operand[0], recog_operand[1])); ! 553: else ! 554: abort (); ! 555: emit_jump_insn (gen_cbranch (label)); ! 556: DONE; ! 557: }") ! 558: ! 559: (define_expand "blt" ! 560: [(set (pc) ! 561: (if_then_else (lt (cc0) ! 562: (const_int 0)) ! 563: (label_ref (match_operand 0 "" "")) ! 564: (pc)))] ! 565: "" ! 566: " ! 567: { ! 568: rtx label = operands[0]; ! 569: enum insn_code code; ! 570: rtx prev; ! 571: ! 572: end_sequence (); ! 573: prev = get_last_insn (); ! 574: ! 575: code = recog_memoized (prev); ! 576: insn_extract (prev); ! 577: NEXT_INSN (PREV_INSN (prev)) = 0; ! 578: set_last_insn (PREV_INSN (prev)); ! 579: start_sequence (); ! 580: ! 581: if (code == CODE_FOR_cmpsi) ! 582: emit_insn (gen_cmpltsi (recog_operand[0], recog_operand[1])); ! 583: else if (code == CODE_FOR_cmpsf) ! 584: emit_insn (gen_cmpltsf (recog_operand[0], recog_operand[1])); ! 585: else if (code == CODE_FOR_cmpdf) ! 586: emit_insn (gen_cmpltdf (recog_operand[0], recog_operand[1])); ! 587: else ! 588: abort (); ! 589: emit_jump_insn (gen_cbranch (label)); ! 590: DONE; ! 591: }") ! 592: ! 593: (define_expand "ble" ! 594: [(set (pc) ! 595: (if_then_else (le (cc0) ! 596: (const_int 0)) ! 597: (label_ref (match_operand 0 "" "")) ! 598: (pc)))] ! 599: "" ! 600: " ! 601: { ! 602: rtx label = operands[0]; ! 603: enum insn_code code; ! 604: rtx prev; ! 605: ! 606: end_sequence (); ! 607: prev = get_last_insn (); ! 608: ! 609: code = recog_memoized (prev); ! 610: insn_extract (prev); ! 611: NEXT_INSN (PREV_INSN (prev)) = 0; ! 612: set_last_insn (PREV_INSN (prev)); ! 613: start_sequence (); ! 614: ! 615: if (code == CODE_FOR_cmpsi) ! 616: { ! 617: emit_insn (gen_cmpgtsi (recog_operand[0], recog_operand[1])); ! 618: emit_jump_insn (gen_inverse_cbranch (label)); ! 619: } ! 620: else ! 621: { ! 622: if (code == CODE_FOR_cmpsf) ! 623: emit_insn (gen_cmplesf (recog_operand[0], recog_operand[1])); ! 624: else if (code == CODE_FOR_cmpdf) ! 625: emit_insn (gen_cmpledf (recog_operand[0], recog_operand[1])); ! 626: else ! 627: abort (); ! 628: emit_jump_insn (gen_cbranch (label)); ! 629: } ! 630: DONE; ! 631: }") ! 632: ! 633: (define_expand "bge" ! 634: [(set (pc) ! 635: (if_then_else (ge (cc0) ! 636: (const_int 0)) ! 637: (label_ref (match_operand 0 "" "")) ! 638: (pc)))] ! 639: "" ! 640: " ! 641: { ! 642: rtx label = operands[0]; ! 643: enum insn_code code; ! 644: rtx prev; ! 645: ! 646: end_sequence (); ! 647: prev = get_last_insn (); ! 648: ! 649: code = recog_memoized (prev); ! 650: insn_extract (prev); ! 651: NEXT_INSN (PREV_INSN (prev)) = 0; ! 652: set_last_insn (PREV_INSN (prev)); ! 653: start_sequence (); ! 654: ! 655: if (code == CODE_FOR_cmpsi) ! 656: { ! 657: emit_insn (gen_cmpltsi (recog_operand[0], recog_operand[1])); ! 658: emit_jump_insn (gen_inverse_cbranch (label)); ! 659: } ! 660: else ! 661: { ! 662: if (code == CODE_FOR_cmpsf) ! 663: emit_insn (gen_cmpgesf (recog_operand[0], recog_operand[1])); ! 664: else if (code == CODE_FOR_cmpdf) ! 665: emit_insn (gen_cmpgedf (recog_operand[0], recog_operand[1])); ! 666: else ! 667: abort (); ! 668: emit_jump_insn (gen_cbranch (label)); ! 669: } ! 670: DONE; ! 671: }") ! 672: ! 673: (define_expand "bgtu" ! 674: [(set (pc) ! 675: (if_then_else (gtu (cc0) ! 676: (const_int 0)) ! 677: (label_ref (match_operand 0 "" "")) ! 678: (pc)))] ! 679: "" ! 680: " ! 681: { ! 682: rtx label = operands[0]; ! 683: enum insn_code code; ! 684: rtx prev; ! 685: ! 686: end_sequence (); ! 687: prev = get_last_insn (); ! 688: ! 689: code = recog_memoized (prev); ! 690: insn_extract (prev); ! 691: NEXT_INSN (PREV_INSN (prev)) = 0; ! 692: set_last_insn (PREV_INSN (prev)); ! 693: start_sequence (); ! 694: ! 695: if (code == CODE_FOR_cmpsi) ! 696: emit_insn (gen_cmpleusi (recog_operand[0], recog_operand[1])); ! 697: else ! 698: abort (); ! 699: emit_jump_insn (gen_inverse_cbranch (label)); ! 700: DONE; ! 701: }") ! 702: ! 703: (define_expand "bltu" ! 704: [(set (pc) ! 705: (if_then_else (ltu (cc0) ! 706: (const_int 0)) ! 707: (label_ref (match_operand 0 "" "")) ! 708: (pc)))] ! 709: "" ! 710: " ! 711: { ! 712: rtx label = operands[0]; ! 713: enum insn_code code; ! 714: rtx prev; ! 715: ! 716: end_sequence (); ! 717: prev = get_last_insn (); ! 718: ! 719: code = recog_memoized (prev); ! 720: insn_extract (prev); ! 721: NEXT_INSN (PREV_INSN (prev)) = 0; ! 722: set_last_insn (PREV_INSN (prev)); ! 723: start_sequence (); ! 724: ! 725: if (code == CODE_FOR_cmpsi) ! 726: emit_insn (gen_cmpgeusi (recog_operand[0], recog_operand[1])); ! 727: else ! 728: abort (); ! 729: emit_jump_insn (gen_inverse_cbranch (label)); ! 730: DONE; ! 731: }") ! 732: ! 733: (define_expand "bgeu" ! 734: [(set (pc) ! 735: (if_then_else (geu (cc0) ! 736: (const_int 0)) ! 737: (label_ref (match_operand 0 "" "")) ! 738: (pc)))] ! 739: "" ! 740: " ! 741: { ! 742: rtx label = operands[0]; ! 743: enum insn_code code; ! 744: rtx prev; ! 745: ! 746: end_sequence (); ! 747: prev = get_last_insn (); ! 748: ! 749: code = recog_memoized (prev); ! 750: insn_extract (prev); ! 751: NEXT_INSN (PREV_INSN (prev)) = 0; ! 752: set_last_insn (PREV_INSN (prev)); ! 753: start_sequence (); ! 754: ! 755: if (code == CODE_FOR_cmpsi) ! 756: emit_insn (gen_cmpgeusi (recog_operand[0], recog_operand[1])); ! 757: else ! 758: abort (); ! 759: emit_jump_insn (gen_cbranch (label)); ! 760: DONE; ! 761: }") ! 762: ! 763: (define_expand "bleu" ! 764: [(set (pc) ! 765: (if_then_else (leu (cc0) ! 766: (const_int 0)) ! 767: (label_ref (match_operand 0 "" "")) ! 768: (pc)))] ! 769: "" ! 770: " ! 771: { ! 772: rtx label = operands[0]; ! 773: enum insn_code code; ! 774: rtx prev; ! 775: ! 776: end_sequence (); ! 777: prev = get_last_insn (); ! 778: ! 779: code = recog_memoized (prev); ! 780: insn_extract (prev); ! 781: NEXT_INSN (PREV_INSN (prev)) = 0; ! 782: set_last_insn (PREV_INSN (prev)); ! 783: start_sequence (); ! 784: ! 785: if (code == CODE_FOR_cmpsi) ! 786: emit_insn (gen_cmpleusi (recog_operand[0], recog_operand[1])); ! 787: else ! 788: abort (); ! 789: emit_jump_insn (gen_cbranch (label)); ! 790: DONE; ! 791: }") ! 792: ! 793: ;; Move instructions ! 794: ! 795: (define_insn "movsi" ! 796: [(set (match_operand:SI 0 "general_operand" "=r,m,f") ! 797: (match_operand:SI 1 "general_operand" "rmif,rfJ,rmfJ"))] ! 798: "" ! 799: "* ! 800: { ! 801: if (GET_CODE (operands[0]) == MEM) ! 802: { ! 803: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) ! 804: return output_store (operands); ! 805: if (FP_REG_P (operands[1])) ! 806: return \"fst.l %1,%0\"; ! 807: return \"st.l %r1,%0\"; ! 808: } ! 809: if (GET_CODE (operands[1]) == MEM) ! 810: { ! 811: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ! 812: return output_load (operands); ! 813: if (FP_REG_P (operands[0])) ! 814: return \"fld.l %1,%0\"; ! 815: return \"ld.l %1,%0\"; ! 816: } ! 817: if (FP_REG_P (operands[1]) && FP_REG_P (operands[0])) ! 818: return \"fmov.ss %1,%0\"; ! 819: if (FP_REG_P (operands[1])) ! 820: return \"fxfr %1,%0\"; ! 821: if (FP_REG_P (operands[0]) && operands[1] == const0_rtx) ! 822: return \"fmov.ss f0,%0\"; ! 823: if (FP_REG_P (operands[0])) ! 824: return \"ixfr %1,%0\"; ! 825: return \"mov %1,%0\"; ! 826: }") ! 827: ! 828: (define_insn "movhi" ! 829: [(set (match_operand:HI 0 "general_operand" "=r,m") ! 830: (match_operand:HI 1 "general_operand" "rmi,rJ"))] ! 831: "" ! 832: "* ! 833: { ! 834: if (GET_CODE (operands[0]) == MEM) ! 835: { ! 836: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) ! 837: return output_store (operands); ! 838: return \"st.s %r1,%0\"; ! 839: } ! 840: if (GET_CODE (operands[1]) == MEM) ! 841: { ! 842: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ! 843: return output_load (operands); ! 844: return \"ld.s %1,%0\"; ! 845: } ! 846: return \"mov %1,%0\"; ! 847: }") ! 848: ! 849: (define_insn "movqi" ! 850: [(set (match_operand:QI 0 "general_operand" "=r,m") ! 851: (match_operand:QI 1 "general_operand" "rmi,rJ"))] ! 852: "" ! 853: "* ! 854: { ! 855: if (GET_CODE (operands[0]) == MEM) ! 856: { ! 857: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) ! 858: return output_store (operands); ! 859: return \"st.b %r1,%0\"; ! 860: } ! 861: if (GET_CODE (operands[1]) == MEM) ! 862: { ! 863: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ! 864: return output_load (operands); ! 865: return \"ld.b %1,%0\"; ! 866: } ! 867: return \"mov %1,%0\"; ! 868: }") ! 869: ! 870: ;; The definition of this insn does not really explain what it does, ! 871: ;; but it should suffice ! 872: ;; that anything generated as this insn will be recognized as one ! 873: ;; and that it won't successfully combine with anything. ! 874: (define_expand "movstrsi" ! 875: [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" "")) ! 876: (mem:BLK (match_operand:BLK 1 "general_operand" ""))) ! 877: (use (match_operand:SI 2 "nonmemory_operand" "")) ! 878: (use (match_operand:SI 3 "immediate_operand" "")) ! 879: (clobber (match_dup 4)) ! 880: (clobber (match_dup 5)) ! 881: (clobber (match_dup 6)) ! 882: (clobber (match_dup 0)) ! 883: (clobber (match_dup 1))])] ! 884: "" ! 885: " ! 886: { ! 887: operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0)); ! 888: operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0)); ! 889: operands[4] = gen_reg_rtx (SImode); ! 890: operands[5] = gen_reg_rtx (SImode); ! 891: operands[6] = gen_reg_rtx (SImode); ! 892: }") ! 893: ! 894: (define_insn "" ! 895: [(set (mem:BLK (match_operand:SI 0 "register_operand" "r")) ! 896: (mem:BLK (match_operand:SI 1 "register_operand" "r"))) ! 897: (use (match_operand:SI 2 "nonmemory_operand" "rn")) ! 898: (use (match_operand:SI 3 "immediate_operand" "i")) ! 899: (clobber (match_operand:SI 4 "register_operand" "=r")) ! 900: (clobber (match_operand:SI 5 "register_operand" "=r")) ! 901: (clobber (match_operand:SI 6 "register_operand" "=r")) ! 902: (clobber (match_dup 0)) ! 903: (clobber (match_dup 1))] ! 904: "" ! 905: "* return output_block_move (operands);") ! 906: ! 907: ;; Floating point move insns ! 908: ! 909: ;; This pattern forces (set (reg:DF ...) (const_double ...)) ! 910: ;; to be reloaded by putting the constant into memory. ! 911: ;; It must come before the more general movdf pattern. ! 912: (define_insn "" ! 913: [(set (match_operand:DF 0 "general_operand" "=r,f,o") ! 914: (match_operand:DF 1 "" "mG,m,G"))] ! 915: "GET_CODE (operands[1]) == CONST_DOUBLE" ! 916: "* ! 917: { ! 918: if (FP_REG_P (operands[0])) ! 919: return output_fp_move_double (operands); ! 920: if (operands[1] == dconst0_rtx && GET_CODE (operands[0]) == REG) ! 921: { ! 922: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); ! 923: return \"mov r0,%0\;mov r0,%1\"; ! 924: } ! 925: if (operands[1] == dconst0_rtx && GET_CODE (operands[0]) == MEM) ! 926: { ! 927: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) ! 928: { ! 929: if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) ! 930: && (cc_prev_status.flags & CC_HI_R31_ADJ) ! 931: && XEXP (operands[0], 0) == cc_prev_status.mdep)) ! 932: { ! 933: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; ! 934: cc_status.mdep = XEXP (operands[0], 0); ! 935: output_asm_insn (\"orh ha%%%m0,r0,r31\", operands); ! 936: } ! 937: return \"st.l r0,l%%%%m0(r31)\;st.l r0,l%%%%m0+4(r31)\"; ! 938: } ! 939: operands[1] = adj_offsettable_operand (operands[0], 4); ! 940: return \"st.l r0,%0\;st.l r0,%1\"; ! 941: } ! 942: return output_move_double (operands); ! 943: }") ! 944: ! 945: (define_insn "movdf" ! 946: [(set (match_operand:DF 0 "general_operand" "=*rm,&*r,?f,?*rm") ! 947: (match_operand:DF 1 "general_operand" "*r,m,*rfmG,f"))] ! 948: "" ! 949: "* ! 950: { ! 951: if (GET_CODE (operands[0]) == MEM ! 952: && CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) ! 953: return output_store (operands); ! 954: if (GET_CODE (operands[1]) == MEM ! 955: && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ! 956: return output_load (operands); ! 957: ! 958: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) ! 959: return output_fp_move_double (operands); ! 960: return output_move_double (operands); ! 961: }") ! 962: ! 963: (define_insn "movdi" ! 964: [(set (match_operand:DI 0 "general_operand" "=rm,&r,?f,?rm") ! 965: (match_operand:DI 1 "general_operand" "r,mi,rfm,f"))] ! 966: "" ! 967: "* ! 968: { ! 969: if (GET_CODE (operands[0]) == MEM ! 970: && CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) ! 971: return output_store (operands); ! 972: if (GET_CODE (operands[1]) == MEM ! 973: && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ! 974: return output_load (operands); ! 975: ! 976: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) ! 977: return output_fp_move_double (operands); ! 978: return output_move_double (operands); ! 979: }") ! 980: ! 981: (define_insn "movsf" ! 982: [(set (match_operand:SF 0 "general_operand" "=*rf,m") ! 983: (match_operand:SF 1 "general_operand" "*rfmG,*rf"))] ! 984: "" ! 985: "* ! 986: { ! 987: if (GET_CODE (operands[0]) == MEM ! 988: && CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) ! 989: return output_store (operands); ! 990: if (GET_CODE (operands[1]) == MEM ! 991: && CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ! 992: return output_load (operands); ! 993: if (FP_REG_P (operands[0])) ! 994: { ! 995: if (FP_REG_P (operands[1])) ! 996: return \"fmov.ss %1,%0\"; ! 997: if (GET_CODE (operands[1]) == REG) ! 998: return \"ixfr %1,%0\"; ! 999: if (operands[1] == fconst0_rtx) ! 1000: return \"fmov.ss f0,%0\"; ! 1001: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ! 1002: { ! 1003: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; ! 1004: cc_status.mdep = XEXP (operands[1], 0); ! 1005: return \"orh ha%%%m1,r0,r31\;fld.l l%%%m1(r31),%0\"; ! 1006: } ! 1007: return \"fld.l %1,%0\"; ! 1008: } ! 1009: if (FP_REG_P (operands[1])) ! 1010: { ! 1011: if (GET_CODE (operands[0]) == REG) ! 1012: return \"fxfr %1,%0\"; ! 1013: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) ! 1014: { ! 1015: if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) ! 1016: && (cc_prev_status.flags & CC_HI_R31_ADJ) ! 1017: && XEXP (operands[0], 0) == cc_prev_status.mdep)) ! 1018: { ! 1019: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; ! 1020: cc_status.mdep = XEXP (operands[0], 0); ! 1021: output_asm_insn (\"orh ha%%%m0,r0,r31\", operands); ! 1022: } ! 1023: return \"fst.l %r1,l%%%m0(r31)\"; ! 1024: } ! 1025: return \"fst.l %r1,%0\"; ! 1026: } ! 1027: if (GET_CODE (operands[0]) == MEM) ! 1028: return \"st.l %r1,%0\"; ! 1029: if (GET_CODE (operands[1]) == MEM) ! 1030: return \"ld.l %1,%0\"; ! 1031: if (operands[1] == fconst0_rtx) ! 1032: return \"mov r0,%0\"; ! 1033: return \"mov %1,%0\"; ! 1034: }") ! 1035: ! 1036: ;; Special load insns for REG+REG addresses. ! 1037: ;; Such addresses are not "legitimate" because st rejects them. ! 1038: ! 1039: (define_insn "" ! 1040: [(set (match_operand:DF 0 "register_operand" "rf") ! 1041: (match_operand:DF 1 "indexed_operand" "m"))] ! 1042: "" ! 1043: "* ! 1044: { ! 1045: if (FP_REG_P (operands[0])) ! 1046: return output_fp_move_double (operands); ! 1047: return output_move_double (operands); ! 1048: }") ! 1049: ! 1050: (define_insn "" ! 1051: [(set (match_operand:SF 0 "register_operand" "rf") ! 1052: (match_operand:SF 1 "indexed_operand" "m"))] ! 1053: "" ! 1054: "* ! 1055: { ! 1056: if (FP_REG_P (operands[0])) ! 1057: return \"fld.l %1,%0\"; ! 1058: return \"ld.l %1,%0\"; ! 1059: }") ! 1060: ! 1061: (define_insn "" ! 1062: [(set (match_operand:SI 0 "register_operand" "rf") ! 1063: (match_operand:SI 1 "indexed_operand" "m"))] ! 1064: "" ! 1065: "* ! 1066: { ! 1067: if (FP_REG_P (operands[0])) ! 1068: return \"fld.l %1,%0\"; ! 1069: return \"ld.l %1,%0\"; ! 1070: }") ! 1071: ! 1072: (define_insn "" ! 1073: [(set (match_operand:HI 0 "register_operand" "r") ! 1074: (match_operand:HI 1 "indexed_operand" "m"))] ! 1075: "" ! 1076: "ld.s %1,%0") ! 1077: ! 1078: (define_insn "" ! 1079: [(set (match_operand:QI 0 "register_operand" "r") ! 1080: (match_operand:QI 1 "indexed_operand" "m"))] ! 1081: "" ! 1082: "ld.b %1,%0") ! 1083: ! 1084: ;; Likewise for floating-point store insns. ! 1085: ! 1086: (define_insn "" ! 1087: [(set (match_operand:DF 0 "indexed_operand" "m") ! 1088: (match_operand:DF 1 "register_operand" "f"))] ! 1089: "" ! 1090: "fst.d %1,%0") ! 1091: ! 1092: (define_insn "" ! 1093: [(set (match_operand:SF 0 "indexed_operand" "m") ! 1094: (match_operand:SF 1 "register_operand" "f"))] ! 1095: "" ! 1096: "fst.l %1,%0") ! 1097: ! 1098: ;;- truncation instructions ! 1099: (define_insn "truncsiqi2" ! 1100: [(set (match_operand:QI 0 "general_operand" "=g") ! 1101: (truncate:QI ! 1102: (match_operand:SI 1 "register_operand" "r")))] ! 1103: "" ! 1104: "* ! 1105: { ! 1106: if (GET_CODE (operands[0]) == MEM) ! 1107: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) ! 1108: { ! 1109: if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) ! 1110: && (cc_prev_status.flags & CC_HI_R31_ADJ) ! 1111: && XEXP (operands[0], 0) == cc_prev_status.mdep)) ! 1112: { ! 1113: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; ! 1114: cc_status.mdep = XEXP (operands[0], 0); ! 1115: output_asm_insn (\"orh ha%%%m0,r0,r31\", operands); ! 1116: } ! 1117: return \"st.b %1,l%%%m0(r31)\"; ! 1118: } ! 1119: else ! 1120: return \"st.b %1,%0\"; ! 1121: return \"mov %1,%0\"; ! 1122: }") ! 1123: ! 1124: (define_insn "trunchiqi2" ! 1125: [(set (match_operand:QI 0 "general_operand" "=g") ! 1126: (truncate:QI ! 1127: (match_operand:HI 1 "register_operand" "r")))] ! 1128: "" ! 1129: "* ! 1130: { ! 1131: if (GET_CODE (operands[0]) == MEM) ! 1132: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) ! 1133: { ! 1134: if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) ! 1135: && (cc_prev_status.flags & CC_HI_R31_ADJ) ! 1136: && XEXP (operands[0], 0) == cc_prev_status.mdep)) ! 1137: { ! 1138: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; ! 1139: cc_status.mdep = XEXP (operands[0], 0); ! 1140: output_asm_insn (\"orh ha%%%m0,r0,r31\", operands); ! 1141: } ! 1142: return \"st.b %1,l%%%m0(r31)\"; ! 1143: } ! 1144: else ! 1145: return \"st.b %1,%0\"; ! 1146: return \"mov %1,%0\"; ! 1147: }") ! 1148: ! 1149: (define_insn "truncsihi2" ! 1150: [(set (match_operand:HI 0 "general_operand" "=g") ! 1151: (truncate:HI ! 1152: (match_operand:SI 1 "register_operand" "r")))] ! 1153: "" ! 1154: "* ! 1155: { ! 1156: if (GET_CODE (operands[0]) == MEM) ! 1157: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) ! 1158: { ! 1159: if (! ((cc_prev_status.flags & CC_KNOW_HI_R31) ! 1160: && (cc_prev_status.flags & CC_HI_R31_ADJ) ! 1161: && XEXP (operands[0], 0) == cc_prev_status.mdep)) ! 1162: { ! 1163: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; ! 1164: cc_status.mdep = XEXP (operands[0], 0); ! 1165: output_asm_insn (\"orh ha%%%m0,r0,r31\", operands); ! 1166: } ! 1167: return \"st.s %1,l%%%m0(r31)\"; ! 1168: } ! 1169: else ! 1170: return \"st.s %1,%0\"; ! 1171: return \"mov %1,%0\"; ! 1172: }") ! 1173: ! 1174: ;;- zero extension instructions ! 1175: ! 1176: ;; Note that the one starting from HImode comes before those for QImode ! 1177: ;; so that a constant operand will match HImode, not QImode. ! 1178: ! 1179: (define_insn "zero_extendhisi2" ! 1180: [(set (match_operand:SI 0 "register_operand" "=r") ! 1181: (zero_extend:SI ! 1182: (match_operand:HI 1 "register_operand" "r")))] ! 1183: "" ! 1184: "and 0xffff,%1,%0") ! 1185: ! 1186: (define_insn "zero_extendqihi2" ! 1187: [(set (match_operand:HI 0 "register_operand" "=r") ! 1188: (zero_extend:HI ! 1189: (match_operand:QI 1 "register_operand" "r")))] ! 1190: "" ! 1191: "and 0xff,%1,%0") ! 1192: ! 1193: (define_insn "zero_extendqisi2" ! 1194: [(set (match_operand:SI 0 "register_operand" "=r") ! 1195: (zero_extend:SI ! 1196: (match_operand:QI 1 "register_operand" "r")))] ! 1197: "" ! 1198: "and 0xff,%1,%0") ! 1199: ! 1200: ;;- sign extension instructions ! 1201: ;; Note that the one starting from HImode comes before those for QImode ! 1202: ;; so that a constant operand will match HImode, not QImode. ! 1203: ! 1204: (define_insn "extendhisi2" ! 1205: [(set (match_operand:SI 0 "register_operand" "=r") ! 1206: (sign_extend:SI ! 1207: (match_operand:HI 1 "general_operand" "mr")))] ! 1208: "" ! 1209: "* ! 1210: { ! 1211: if (REG_P (operands[1])) ! 1212: return \"shl 16,%1,%0\;shra 16,%0,%0\"; ! 1213: if (GET_CODE (operands[1]) == CONST_INT) ! 1214: abort (); ! 1215: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ! 1216: { ! 1217: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; ! 1218: cc_status.mdep = XEXP (operands[1], 0); ! 1219: return \"orh ha%%%m1,r0,r31\;ld.s l%%%m1(r31),%0\"; ! 1220: } ! 1221: else ! 1222: return \"ld.s %1,%0\"; ! 1223: }") ! 1224: ! 1225: (define_insn "extendqihi2" ! 1226: [(set (match_operand:HI 0 "register_operand" "=r") ! 1227: (sign_extend:HI ! 1228: (match_operand:QI 1 "general_operand" "mr")))] ! 1229: "" ! 1230: "* ! 1231: { ! 1232: if (REG_P (operands[1])) ! 1233: return \"shl 24,%1,%0\;shra 24,%0,%0\"; ! 1234: if (GET_CODE (operands[1]) == CONST_INT) ! 1235: abort (); ! 1236: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ! 1237: { ! 1238: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; ! 1239: cc_status.mdep = XEXP (operands[1], 0); ! 1240: return \"orh ha%%%m1,r0,r31\;ld.b l%%%m1(r31),%0\"; ! 1241: } ! 1242: else ! 1243: return \"ld.b %1,%0\"; ! 1244: }") ! 1245: ! 1246: (define_insn "extendqisi2" ! 1247: [(set (match_operand:SI 0 "register_operand" "=r") ! 1248: (sign_extend:SI ! 1249: (match_operand:QI 1 "general_operand" "mr")))] ! 1250: "" ! 1251: "* ! 1252: { ! 1253: if (REG_P (operands[1])) ! 1254: return \"shl 24,%1,%0\;shra 24,%0,%0\"; ! 1255: if (GET_CODE (operands[1]) == CONST_INT) ! 1256: abort (); ! 1257: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ! 1258: { ! 1259: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; ! 1260: cc_status.mdep = XEXP (operands[1], 0); ! 1261: return \"orh ha%%%m1,r0,r31\;ld.b l%%%m1(r31),%0\"; ! 1262: } ! 1263: else ! 1264: return \"ld.b %1,%0\"; ! 1265: }") ! 1266: ! 1267: (define_insn "" ! 1268: [(set (match_operand:SI 0 "register_operand" "=r") ! 1269: (sign_extend:SI ! 1270: (match_operand:HI 1 "indexed_operand" "m")))] ! 1271: "" ! 1272: "ld.s %1,%0") ! 1273: ! 1274: (define_insn "" ! 1275: [(set (match_operand:HI 0 "register_operand" "=r") ! 1276: (sign_extend:HI ! 1277: (match_operand:QI 1 "indexed_operand" "m")))] ! 1278: "" ! 1279: "ld.b %1,%0") ! 1280: ! 1281: (define_insn "" ! 1282: [(set (match_operand:SI 0 "register_operand" "=r") ! 1283: (sign_extend:SI ! 1284: (match_operand:QI 1 "indexed_operand" "m")))] ! 1285: "" ! 1286: "ld.b %1,%0") ! 1287: ! 1288: ;; Signed bitfield extractions come out looking like ! 1289: ;; (shiftrt (sign_extend (shift <Y> <C1>)) <C2>) ! 1290: ;; which we expand poorly as four shift insns. ! 1291: ;; These patters yeild two shifts: ! 1292: ;; (shiftrt (shift <Y> <C3>) <C4>) ! 1293: (define_insn "" ! 1294: [(set (match_operand:SI 0 "register_operand" "=r") ! 1295: (ashiftrt:SI ! 1296: (sign_extend:SI ! 1297: (match_operand:QI 1 "register_operand" "r")) ! 1298: (match_operand:SI 2 "logic_int" "n")))] ! 1299: "" ! 1300: "* ! 1301: { ! 1302: return \"shl 24,%1,%0\;shra 24+%2,%0,%0\"; ! 1303: }") ! 1304: ! 1305: (define_insn "" ! 1306: [(set (match_operand:SI 0 "register_operand" "=r") ! 1307: (ashiftrt:SI ! 1308: (sign_extend:SI ! 1309: (subreg:QI (ashift:SI (match_operand:SI 1 "register_operand" "r") ! 1310: (match_operand:SI 2 "logic_int" "n")) 0)) ! 1311: (match_operand:SI 3 "logic_int" "n")))] ! 1312: "" ! 1313: "* ! 1314: { ! 1315: return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\"; ! 1316: }") ! 1317: ! 1318: (define_insn "" ! 1319: [(set (match_operand:SI 0 "register_operand" "=r") ! 1320: (ashiftrt:SI ! 1321: (sign_extend:SI ! 1322: (ashift:QI (match_operand:QI 1 "register_operand" "r") ! 1323: (match_operand:QI 2 "logic_int" "n"))) ! 1324: (match_operand:SI 3 "logic_int" "n")))] ! 1325: "" ! 1326: "* ! 1327: { ! 1328: return \"shl 0x18+%2,%1,%0\;shra 0x18+%3,%0,%0\"; ! 1329: }") ! 1330: ! 1331: ;; Special patterns for optimizing bit-field instructions. ! 1332: ! 1333: ;; First two patterns are for bitfields that came from memory ! 1334: ;; testing only the high bit. They work with old combiner. ! 1335: ! 1336: (define_insn "" ! 1337: [(set (cc0) ! 1338: (eq (zero_extend:SI (subreg:QI (lshiftrt:SI (match_operand:SI 0 "register_operand" "r") ! 1339: (const_int 7)) 0)) ! 1340: (const_int 0)))] ! 1341: "" ! 1342: "and 128,%0,r0") ! 1343: ! 1344: (define_insn "" ! 1345: [(set (cc0) ! 1346: (eq (sign_extend:SI (subreg:QI (ashiftrt:SI (match_operand:SI 0 "register_operand" "r") ! 1347: (const_int 7)) 0)) ! 1348: (const_int 0)))] ! 1349: "" ! 1350: "and 128,%0,r0") ! 1351: ! 1352: ;; next two patterns are good for bitfields coming from memory ! 1353: ;; (via pseudo-register) or from a register, though this optimization ! 1354: ;; is only good for values contained wholly within the bottom 13 bits ! 1355: (define_insn "" ! 1356: [(set (cc0) ! 1357: (eq ! 1358: (and:SI (lshiftrt:SI (match_operand:SI 0 "register_operand" "r") ! 1359: (match_operand:SI 1 "logic_int" "n")) ! 1360: (match_operand:SI 2 "logic_int" "n")) ! 1361: (const_int 0)))] ! 1362: "LOGIC_INTVAL (INTVAL (operands[2]) << INTVAL (operands[1]))" ! 1363: "* ! 1364: { ! 1365: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1366: (INTVAL (operands[2]) << INTVAL (operands[1]))); ! 1367: return \"and %2,%0,r0\"; ! 1368: }") ! 1369: ! 1370: (define_insn "" ! 1371: [(set (cc0) ! 1372: (eq ! 1373: (and:SI (ashiftrt:SI (match_operand:SI 0 "register_operand" "r") ! 1374: (match_operand:SI 1 "logic_int" "n")) ! 1375: (match_operand:SI 2 "logic_int" "n")) ! 1376: (const_int 0)))] ! 1377: "LOGIC_INTVAL (INTVAL (operands[2]) << INTVAL (operands[1]))" ! 1378: "* ! 1379: { ! 1380: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1381: (INTVAL (operands[2]) << INTVAL (operands[1]))); ! 1382: return \"and %2,%0,r0\"; ! 1383: }") ! 1384: ! 1385: ;; Conversions between float and double. ! 1386: ! 1387: (define_insn "extendsfdf2" ! 1388: [(set (match_operand:DF 0 "register_operand" "=f") ! 1389: (float_extend:DF ! 1390: (match_operand:SF 1 "register_operand" "f")))] ! 1391: "" ! 1392: "fmov.sd %1,%0") ! 1393: ! 1394: (define_insn "truncdfsf2" ! 1395: [(set (match_operand:SF 0 "register_operand" "=f") ! 1396: (float_truncate:SF ! 1397: (match_operand:DF 1 "register_operand" "f")))] ! 1398: "" ! 1399: "fmov.ds %1,%0") ! 1400: ! 1401: ;; Conversion between fixed point and floating point. ! 1402: ;; Note that among the fix-to-float insns ! 1403: ;; the ones that start with SImode come first. ! 1404: ;; That is so that an operand that is a CONST_INT ! 1405: ;; (and therefore lacks a specific machine mode). ! 1406: ;; will be recognized as SImode (which is always valid) ! 1407: ;; rather than as QImode or HImode. ! 1408: ! 1409: ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...))) ! 1410: ;; to be reloaded by putting the constant into memory. ! 1411: ;; It must come before the more general floatsisf2 pattern. ! 1412: (define_expand "floatsidf2" ! 1413: [(set (match_dup 2) (match_dup 3)) ! 1414: (set (match_dup 4) (xor:SI (match_operand:SI 1 "register_operand" "") ! 1415: (const_int -2147483648))) ! 1416: (set (subreg:SI (match_dup 5) 1) (match_dup 4)) ! 1417: (set (subreg:SI (match_dup 5) 0) (subreg:SI (match_dup 2) 0)) ! 1418: (set (match_operand:DF 0 "register_operand" "") ! 1419: (minus:DF (match_dup 5) (match_dup 2)))] ! 1420: "" ! 1421: " ! 1422: { ! 1423: /* Generate desired value, in float format of host machine. */ ! 1424: double d = (double) (1 << 30) * ((double) (1 << 22) + (double) (1 << 1)); ! 1425: operands[2] = gen_reg_rtx (DFmode); ! 1426: operands[3] = immed_double_const (d, DFmode); ! 1427: operands[4] = gen_reg_rtx (SImode); ! 1428: operands[5] = gen_reg_rtx (DFmode); ! 1429: }") ! 1430: ! 1431: ;; Floating to fixed conversion. ! 1432: ! 1433: (define_expand "fix_truncdfsi2" ! 1434: ;; This first insn produces a double-word value ! 1435: ;; in which only the low word is valid. ! 1436: [(set (match_dup 2) ! 1437: (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f")))) ! 1438: (set (match_operand:SI 0 "register_operand" "=f") ! 1439: (subreg:SI (match_dup 2) 0))] ! 1440: "" ! 1441: " ! 1442: { ! 1443: operands[2] = gen_reg_rtx (DImode); ! 1444: }") ! 1445: ! 1446: ;; Recognize the first insn generated above. ! 1447: ;; This RTL looks like a fix_truncdfdi2 insn, ! 1448: ;; but we dont call it that, because only 32 bits ! 1449: ;; of the result are valid. ! 1450: ;; This pattern will work for the intended purposes ! 1451: ;; as long as we do not have any fixdfdi2 or fix_truncdfdi2. ! 1452: (define_insn "" ! 1453: [(set (match_operand:DI 0 "register_operand" "=f") ! 1454: (fix:DI (fix:DF (match_operand:DF 1 "register_operand" "f"))))] ! 1455: "" ! 1456: "ftrunc.dd %1,%0") ! 1457: ! 1458: (define_expand "fix_truncsfsi2" ! 1459: ;; This first insn produces a double-word value ! 1460: ;; in which only the low word is valid. ! 1461: [(set (match_dup 2) ! 1462: (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f")))) ! 1463: (set (match_operand:SI 0 "register_operand" "=f") ! 1464: (subreg:SI (match_dup 2) 0))] ! 1465: "" ! 1466: " ! 1467: { ! 1468: operands[2] = gen_reg_rtx (DImode); ! 1469: }") ! 1470: ! 1471: ;; Recognize the first insn generated above. ! 1472: ;; This RTL looks like a fix_truncsfdi2 insn, ! 1473: ;; but we dont call it that, because only 32 bits ! 1474: ;; of the result are valid. ! 1475: ;; This pattern will work for the intended purposes ! 1476: ;; as long as we do not have any fixsfdi2 or fix_truncsfdi2. ! 1477: (define_insn "" ! 1478: [(set (match_operand:DI 0 "register_operand" "=f") ! 1479: (fix:DI (fix:SF (match_operand:SF 1 "register_operand" "f"))))] ! 1480: "" ! 1481: "ftrunc.sd %1,%0") ! 1482: ! 1483: ;;- arithmetic instructions ! 1484: ! 1485: (define_insn "addsi3" ! 1486: [(set (match_operand:SI 0 "register_operand" "=r,*f") ! 1487: (plus:SI (match_operand:SI 1 "nonmemory_operand" "%r,*f") ! 1488: (match_operand:SI 2 "nonmemory_operand" "rn,*f")))] ! 1489: "" ! 1490: "* ! 1491: { ! 1492: if (which_alternative == 1) ! 1493: return \"fiadd.ss %2,%1,%0\"; ! 1494: if (REG_P (operands[2])) ! 1495: return \"addu %2,%1,%0\"; ! 1496: if (SMALL_INT (operands[2])) ! 1497: return \"addu %2,%1,%0\"; ! 1498: cc_status.flags &= ~CC_KNOW_HI_R31; ! 1499: return \"orh h%%%2,r0,r31\;or l%%%2,r31,r31\;addu %1,r31,%0\"; ! 1500: }") ! 1501: ! 1502: (define_insn "adddi3" ! 1503: [(set (match_operand:DI 0 "register_operand" "=f") ! 1504: (plus:DI (match_operand:DI 1 "register_operand" "%f") ! 1505: (match_operand:DI 2 "register_operand" "f")))] ! 1506: "" ! 1507: "fiadd.ss %1,%2,%0") ! 1508: ! 1509: (define_insn "subsi3" ! 1510: [(set (match_operand:SI 0 "register_operand" "=r,r,*f") ! 1511: (minus:SI (match_operand:SI 1 "register_operand" "r,I,*f") ! 1512: (match_operand:SI 2 "nonmemory_operand" "rn,r,*f")))] ! 1513: "" ! 1514: "* ! 1515: { ! 1516: if (which_alternative == 2) ! 1517: return \"fisub.ss %1,%2,%0\"; ! 1518: if (REG_P (operands[2])) ! 1519: return \"subu %1,%2,%0\"; ! 1520: if (SMALL_INT (operands[2]) && INTVAL (operands[2]) != -0x10000) ! 1521: { ! 1522: operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2])); ! 1523: return \"addu %2,%1,%0\"; ! 1524: } ! 1525: cc_status.flags &= ~CC_KNOW_HI_R31; ! 1526: return \"orh h%%%2,r0,r31\;or l%%%2,r31,r31\;sub %1,r31,%0\"; ! 1527: }") ! 1528: ! 1529: (define_insn "subdi3" ! 1530: [(set (match_operand:DI 0 "register_operand" "=f") ! 1531: (minus:DI (match_operand:DI 1 "register_operand" "%f") ! 1532: (match_operand:DI 2 "register_operand" "f")))] ! 1533: "" ! 1534: "fisub.ss %1,%2,%0") ! 1535: ! 1536: (define_expand "mulsi3" ! 1537: [(set (subreg:SI (match_dup 4) 0) (match_operand:SI 1 "general_operand" "")) ! 1538: (set (subreg:SI (match_dup 5) 0) (match_operand:SI 2 "general_operand" "")) ! 1539: (clobber (match_dup 3)) ! 1540: (set (subreg:SI (match_dup 3) 0) ! 1541: (mult:SI (subreg:SI (match_dup 4) 0) (subreg:SI (match_dup 5) 0))) ! 1542: (set (match_operand:SI 0 "register_operand" "") (subreg:SI (match_dup 3) 0))] ! 1543: "" ! 1544: " ! 1545: { ! 1546: operands[3] = gen_reg_rtx (DImode); ! 1547: operands[4] = gen_reg_rtx (DImode); ! 1548: operands[5] = gen_reg_rtx (DImode); ! 1549: }") ! 1550: ! 1551: (define_insn "" ! 1552: [(set (subreg:SI (match_operand:DI 0 "register_operand" "=f") 0) ! 1553: (mult:SI (subreg:SI (match_operand:DI 1 "register_operand" "f") 0) ! 1554: (subreg:SI (match_operand:DI 2 "register_operand" "f") 0)))] ! 1555: "" ! 1556: "fmlow.dd %2,%1,%0") ! 1557: ! 1558: ;;- and instructions (with compliment also) ! 1559: (define_insn "andsi3" ! 1560: [(set (match_operand:SI 0 "register_operand" "=r") ! 1561: (and:SI (match_operand:SI 1 "nonmemory_operand" "%r") ! 1562: (match_operand:SI 2 "nonmemory_operand" "rn")))] ! 1563: "" ! 1564: "* ! 1565: { ! 1566: rtx xop[3]; ! 1567: ! 1568: if (REG_P (operands[2]) || LOGIC_INT (operands[2])) ! 1569: return \"and %2,%1,%0\"; ! 1570: if ((INTVAL (operands[2]) & 0xffff) == 0) ! 1571: { ! 1572: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1573: (unsigned) INTVAL (operands[2]) >> 16); ! 1574: return \"andh %2,%1,%0\"; ! 1575: } ! 1576: xop[0] = operands[0]; ! 1577: xop[1] = operands[1]; ! 1578: xop[2] = gen_rtx (CONST_INT, VOIDmode, ~(INTVAL (operands[2]) & 0xffff)); ! 1579: output_asm_insn (\"andnot %2,%1,%0\", xop); ! 1580: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1581: ~(unsigned) INTVAL (operands[2]) >> 16); ! 1582: return \"andnoth %2,%0,%0\"; ! 1583: }") ! 1584: ! 1585: (define_insn "andcbsi3" ! 1586: [(set (match_operand:SI 0 "register_operand" "=r") ! 1587: (and:SI (match_operand:SI 1 "register_operand" "r") ! 1588: (not:SI (match_operand:SI 2 "register_operand" "rn"))))] ! 1589: "" ! 1590: "* ! 1591: { ! 1592: rtx xop[3]; ! 1593: ! 1594: if (REG_P (operands[2]) || LOGIC_INT (operands[2])) ! 1595: return \"andnot %2,%1,%0\"; ! 1596: if ((INTVAL (operands[2]) & 0xffff) == 0) ! 1597: { ! 1598: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1599: (unsigned) INTVAL (operands[2]) >> 16); ! 1600: return \"andnoth %2,%1,%0\"; ! 1601: } ! 1602: xop[0] = operands[0]; ! 1603: xop[1] = operands[1]; ! 1604: xop[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) & 0xffff)); ! 1605: output_asm_insn (\"andnot %2,%1,%0\", xop); ! 1606: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1607: (unsigned) INTVAL (operands[2]) >> 16); ! 1608: return \"andnoth %2,%0,%0\"; ! 1609: }") ! 1610: ! 1611: (define_insn "iorsi3" ! 1612: [(set (match_operand:SI 0 "register_operand" "=r") ! 1613: (ior:SI (match_operand:SI 1 "nonmemory_operand" "%r") ! 1614: (match_operand:SI 2 "nonmemory_operand" "rn")))] ! 1615: "" ! 1616: "* ! 1617: { ! 1618: rtx xop[3]; ! 1619: ! 1620: if (REG_P (operands[2]) || LOGIC_INT (operands[2])) ! 1621: return \"or %2,%1,%0\"; ! 1622: if ((INTVAL (operands[2]) & 0xffff) == 0) ! 1623: { ! 1624: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1625: (unsigned) INTVAL (operands[2]) >> 16); ! 1626: return \"orh %2,%1,%0\"; ! 1627: } ! 1628: xop[0] = operands[0]; ! 1629: xop[1] = operands[1]; ! 1630: xop[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) & 0xffff)); ! 1631: output_asm_insn (\"or %2,%1,%0\", xop); ! 1632: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1633: (unsigned) INTVAL (operands[2]) >> 16); ! 1634: return \"orh %2,%0,%0\"; ! 1635: }") ! 1636: ! 1637: (define_insn "xorsi3" ! 1638: [(set (match_operand:SI 0 "register_operand" "=r") ! 1639: (xor:SI (match_operand:SI 1 "nonmemory_operand" "%r") ! 1640: (match_operand:SI 2 "nonmemory_operand" "rn")))] ! 1641: "" ! 1642: "* ! 1643: { ! 1644: rtx xop[3]; ! 1645: ! 1646: if (REG_P (operands[2]) || LOGIC_INT (operands[2])) ! 1647: return \"xor %2,%1,%0\"; ! 1648: if ((INTVAL (operands[2]) & 0xffff) == 0) ! 1649: { ! 1650: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1651: (unsigned) INTVAL (operands[2]) >> 16); ! 1652: return \"xorh %2,%1,%0\"; ! 1653: } ! 1654: xop[0] = operands[0]; ! 1655: xop[1] = operands[1]; ! 1656: xop[2] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[2]) & 0xffff)); ! 1657: output_asm_insn (\"xor %2,%1,%0\", xop); ! 1658: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1659: (unsigned) INTVAL (operands[2]) >> 16); ! 1660: return \"xorh %2,%0,%0\"; ! 1661: }") ! 1662: ! 1663: (define_insn "negsi2" ! 1664: [(set (match_operand:SI 0 "general_operand" "=r") ! 1665: (neg:SI (match_operand:SI 1 "arith_operand" "rI")))] ! 1666: "" ! 1667: "subu r0,%1,%0") ! 1668: ! 1669: (define_insn "one_cmplsi2" ! 1670: [(set (match_operand:SI 0 "general_operand" "=r") ! 1671: (not:SI (match_operand:SI 1 "arith_operand" "r")))] ! 1672: "" ! 1673: "subu -1,%1,%0") ! 1674: ! 1675: ;; Floating point arithmetic instructions. ! 1676: ! 1677: (define_insn "adddf3" ! 1678: [(set (match_operand:DF 0 "register_operand" "=f") ! 1679: (plus:DF (match_operand:DF 1 "register_operand" "f") ! 1680: (match_operand:DF 2 "register_operand" "f")))] ! 1681: "" ! 1682: "fadd.dd %1,%2,%0") ! 1683: ! 1684: (define_insn "addsf3" ! 1685: [(set (match_operand:SF 0 "register_operand" "=f") ! 1686: (plus:SF (match_operand:SF 1 "register_operand" "f") ! 1687: (match_operand:SF 2 "register_operand" "f")))] ! 1688: "" ! 1689: "fadd.ss %1,%2,%0") ! 1690: ! 1691: (define_insn "subdf3" ! 1692: [(set (match_operand:DF 0 "register_operand" "=f") ! 1693: (minus:DF (match_operand:DF 1 "register_operand" "f") ! 1694: (match_operand:DF 2 "register_operand" "f")))] ! 1695: "" ! 1696: "fsub.dd %1,%2,%0") ! 1697: ! 1698: (define_insn "subsf3" ! 1699: [(set (match_operand:SF 0 "register_operand" "=f") ! 1700: (minus:SF (match_operand:SF 1 "register_operand" "f") ! 1701: (match_operand:SF 2 "register_operand" "f")))] ! 1702: "" ! 1703: "fsub.ss %1,%2,%0") ! 1704: ! 1705: (define_insn "muldf3" ! 1706: [(set (match_operand:DF 0 "register_operand" "=f") ! 1707: (mult:DF (match_operand:DF 1 "register_operand" "f") ! 1708: (match_operand:DF 2 "register_operand" "f")))] ! 1709: "" ! 1710: "fmul.dd %1,%2,%0") ! 1711: ! 1712: (define_insn "mulsf3" ! 1713: [(set (match_operand:SF 0 "register_operand" "=f") ! 1714: (mult:SF (match_operand:SF 1 "register_operand" "f") ! 1715: (match_operand:SF 2 "register_operand" "f")))] ! 1716: "" ! 1717: "fmul.ss %1,%2,%0") ! 1718: ! 1719: (define_insn "negdf2" ! 1720: [(set (match_operand:DF 0 "register_operand" "=f") ! 1721: (neg:DF (match_operand:DF 1 "register_operand" "f")))] ! 1722: "" ! 1723: "fsub.dd f0,%1,%0") ! 1724: ! 1725: (define_insn "negsf2" ! 1726: [(set (match_operand:SF 0 "register_operand" "=f") ! 1727: (neg:SF (match_operand:SF 1 "register_operand" "f")))] ! 1728: "" ! 1729: "fsub.ss f0,%1,%0") ! 1730: ! 1731: ;; Shift instructions ! 1732: ! 1733: ;; Optimized special case of shifting. ! 1734: ;; Must precede the general case. ! 1735: ! 1736: (define_insn "" ! 1737: [(set (match_operand:SI 0 "register_operand" "=r") ! 1738: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m") ! 1739: (const_int 24)))] ! 1740: "" ! 1741: "* ! 1742: { ! 1743: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ! 1744: { ! 1745: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ; ! 1746: cc_status.mdep = XEXP (operands[1], 0); ! 1747: return \"orh ha%%%m1,r0,r31\;ld.b l%%%m1(r31),%0\"; ! 1748: } ! 1749: return \"ld.b %1,%0\"; ! 1750: }") ! 1751: ! 1752: ! 1753: ;;- arithmetic shift instructions ! 1754: (define_insn "ashlsi3" ! 1755: [(set (match_operand:SI 0 "register_operand" "=r") ! 1756: (ashift:SI (match_operand:SI 1 "register_operand" "r") ! 1757: (match_operand:SI 2 "nonmemory_operand" "rn")))] ! 1758: "" ! 1759: "* ! 1760: { ! 1761: if (GET_CODE (operands[2]) == CONST_INT ! 1762: && INTVAL (operands[2]) >= 32) ! 1763: return \"mov r0,%0\"; ! 1764: return \"shl %2,%1,%0\"; ! 1765: }") ! 1766: ! 1767: (define_insn "ashlhi3" ! 1768: [(set (match_operand:HI 0 "register_operand" "=r") ! 1769: (ashift:HI (match_operand:HI 1 "register_operand" "r") ! 1770: (match_operand:HI 2 "nonmemory_operand" "rn")))] ! 1771: "" ! 1772: "* ! 1773: { ! 1774: if (GET_CODE (operands[2]) == CONST_INT ! 1775: && INTVAL (operands[2]) >= 16) ! 1776: return \"mov r0,%0\"; ! 1777: return \"shl %2,%1,%0\"; ! 1778: }") ! 1779: ! 1780: (define_insn "ashlqi3" ! 1781: [(set (match_operand:QI 0 "register_operand" "=r") ! 1782: (ashift:QI (match_operand:QI 1 "register_operand" "r") ! 1783: (match_operand:QI 2 "nonmemory_operand" "rn")))] ! 1784: "" ! 1785: "* ! 1786: { ! 1787: if (GET_CODE (operands[2]) == CONST_INT ! 1788: && INTVAL (operands[2]) >= 8) ! 1789: return \"mov r0,%0\"; ! 1790: return \"shl %2,%1,%0\"; ! 1791: }") ! 1792: ! 1793: (define_insn "ashrsi3" ! 1794: [(set (match_operand:SI 0 "register_operand" "=r") ! 1795: (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") ! 1796: (match_operand:SI 2 "nonmemory_operand" "rn")))] ! 1797: "" ! 1798: "* ! 1799: { ! 1800: if (GET_CODE (operands[2]) == CONST_INT ! 1801: && INTVAL (operands[2]) >= 32) ! 1802: return \"shra 31,%1,%0\"; ! 1803: return \"shra %2,%1,%0\"; ! 1804: }") ! 1805: ! 1806: (define_insn "lshrsi3" ! 1807: [(set (match_operand:SI 0 "register_operand" "=r") ! 1808: (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") ! 1809: (match_operand:SI 2 "nonmemory_operand" "rn")))] ! 1810: "" ! 1811: "* ! 1812: { ! 1813: if (GET_CODE (operands[2]) == CONST_INT ! 1814: && INTVAL (operands[2]) >= 32) ! 1815: return \"mov r0,%0\"; ! 1816: return \"shr %2,%1,%0\"; ! 1817: }") ! 1818: ! 1819: ;; Unconditional and other jump instructions ! 1820: ! 1821: (define_insn "jump" ! 1822: [(set (pc) (label_ref (match_operand 0 "" "")))] ! 1823: "" ! 1824: "* ! 1825: { ! 1826: return \"br %l0\;nop\"; ! 1827: }") ! 1828: ! 1829: ;; Here are two simple peepholes which fill the delay slot of ! 1830: ;; an unconditional branch. ! 1831: ! 1832: (define_peephole ! 1833: [(set (match_operand:SI 0 "register_operand" "=rf") ! 1834: (match_operand:SI 1 "single_insn_src_p" "p")) ! 1835: (set (pc) (label_ref (match_operand 2 "" "")))] ! 1836: "" ! 1837: "* return output_delayed_branch (\"br %l2\", operands, insn);") ! 1838: ! 1839: (define_peephole ! 1840: [(set (match_operand:SI 0 "memory_operand" "=m") ! 1841: (match_operand:SI 1 "reg_or_0_operand" "rfJ")) ! 1842: (set (pc) (label_ref (match_operand 2 "" "")))] ! 1843: "" ! 1844: "* return output_delayed_branch (\"br %l2\", operands, insn);") ! 1845: ! 1846: (define_insn "tablejump" ! 1847: [(set (pc) (match_operand:SI 0 "register_operand" "r")) ! 1848: (use (label_ref (match_operand 1 "" "")))] ! 1849: "" ! 1850: "bri %0\;nop") ! 1851: ! 1852: (define_peephole ! 1853: [(set (match_operand:SI 0 "memory_operand" "=m") ! 1854: (match_operand:SI 1 "reg_or_0_operand" "rfJ")) ! 1855: (set (pc) (match_operand:SI 2 "register_operand" "r")) ! 1856: (use (label_ref (match_operand 3 "" "")))] ! 1857: "" ! 1858: "* return output_delayed_branch (\"bri %2\", operands, insn);") ! 1859: ! 1860: ;;- jump to subroutine ! 1861: (define_expand "call" ! 1862: [(call (match_operand:SI 0 "memory_operand" "m") ! 1863: (match_operand 1 "" "i"))] ! 1864: ;; operand[2] is next_arg_register ! 1865: "" ! 1866: " ! 1867: { ! 1868: if (INTVAL (operands[1]) > 0) ! 1869: { ! 1870: emit_move_insn (arg_pointer_rtx, stack_pointer_rtx); ! 1871: emit_insn (gen_rtx (USE, VOIDmode, arg_pointer_rtx)); ! 1872: } ! 1873: }") ! 1874: ! 1875: ;;- jump to subroutine ! 1876: (define_insn "" ! 1877: [(call (match_operand:SI 0 "memory_operand" "m") ! 1878: (match_operand 1 "" "i"))] ! 1879: ;; operand[2] is next_arg_register ! 1880: "" ! 1881: "* ! 1882: { ! 1883: /* strip the MEM. */ ! 1884: operands[0] = XEXP (operands[0], 0); ! 1885: CC_STATUS_INIT; ! 1886: if (GET_CODE (operands[0]) == REG) ! 1887: return \"calli %0\;nop\"; ! 1888: return \"call %0\;nop\"; ! 1889: }") ! 1890: ! 1891: (define_peephole ! 1892: [(set (match_operand:SI 0 "register_operand" "=rf") ! 1893: (match_operand:SI 1 "single_insn_src_p" "p")) ! 1894: (call (match_operand:SI 2 "memory_operand" "m") ! 1895: (match_operand 3 "" "i"))] ! 1896: ;;- Don't use operand 1 for most machines. ! 1897: "! reg_mentioned_p (operands[0], operands[2])" ! 1898: "* ! 1899: { ! 1900: /* strip the MEM. */ ! 1901: operands[2] = XEXP (operands[2], 0); ! 1902: if (GET_CODE (operands[2]) == REG) ! 1903: return output_delayed_branch (\"calli %2\", operands, insn); ! 1904: return output_delayed_branch (\"call %2\", operands, insn); ! 1905: }") ! 1906: ! 1907: (define_peephole ! 1908: [(set (match_operand:SI 0 "memory_operand" "=m") ! 1909: (match_operand:SI 1 "reg_or_0_operand" "rfJ")) ! 1910: (call (match_operand:SI 2 "memory_operand" "m") ! 1911: (match_operand 3 "" "i"))] ! 1912: ;;- Don't use operand 1 for most machines. ! 1913: "" ! 1914: "* ! 1915: { ! 1916: /* strip the MEM. */ ! 1917: operands[2] = XEXP (operands[2], 0); ! 1918: if (GET_CODE (operands[2]) == REG) ! 1919: return output_delayed_branch (\"calli %2\", operands, insn); ! 1920: return output_delayed_branch (\"call %2\", operands, insn); ! 1921: }") ! 1922: ! 1923: (define_expand "call_value" ! 1924: [(set (match_operand 0 "register_operand" "rf") ! 1925: (call (match_operand:SI 1 "memory_operand" "m") ! 1926: (match_operand 2 "" "i")))] ! 1927: ;; operand 3 is next_arg_register ! 1928: "" ! 1929: " ! 1930: { ! 1931: if (INTVAL (operands[2]) > 0) ! 1932: { ! 1933: emit_move_insn (arg_pointer_rtx, stack_pointer_rtx); ! 1934: emit_insn (gen_rtx (USE, VOIDmode, arg_pointer_rtx)); ! 1935: } ! 1936: }") ! 1937: ! 1938: (define_insn "" ! 1939: [(set (match_operand 0 "register_operand" "=rf") ! 1940: (call (match_operand:SI 1 "memory_operand" "m") ! 1941: (match_operand 2 "" "i")))] ! 1942: ;; operand 3 is next_arg_register ! 1943: "" ! 1944: "* ! 1945: { ! 1946: /* strip the MEM. */ ! 1947: operands[1] = XEXP (operands[1], 0); ! 1948: CC_STATUS_INIT; ! 1949: if (GET_CODE (operands[1]) == REG) ! 1950: return \"calli %1\;nop\"; ! 1951: return \"call %1\;nop\"; ! 1952: }") ! 1953: ! 1954: (define_peephole ! 1955: [(set (match_operand:SI 0 "register_operand" "=rf") ! 1956: (match_operand:SI 1 "single_insn_src_p" "p")) ! 1957: (set (match_operand 2 "" "=rf") ! 1958: (call (match_operand:SI 3 "memory_operand" "m") ! 1959: (match_operand 4 "" "i")))] ! 1960: ;;- Don't use operand 4 for most machines. ! 1961: "! reg_mentioned_p (operands[0], operands[3])" ! 1962: "* ! 1963: { ! 1964: /* strip the MEM. */ ! 1965: operands[3] = XEXP (operands[3], 0); ! 1966: if (GET_CODE (operands[3]) == REG) ! 1967: return output_delayed_branch (\"calli %3\", operands, insn); ! 1968: return output_delayed_branch (\"call %3\", operands, insn); ! 1969: }") ! 1970: ! 1971: (define_peephole ! 1972: [(set (match_operand:SI 0 "memory_operand" "=m") ! 1973: (match_operand:SI 1 "reg_or_0_operand" "rJf")) ! 1974: (set (match_operand 2 "" "=rf") ! 1975: (call (match_operand:SI 3 "memory_operand" "m") ! 1976: (match_operand 4 "" "i")))] ! 1977: ;;- Don't use operand 4 for most machines. ! 1978: "" ! 1979: "* ! 1980: { ! 1981: /* strip the MEM. */ ! 1982: operands[3] = XEXP (operands[3], 0); ! 1983: if (GET_CODE (operands[3]) == REG) ! 1984: return output_delayed_branch (\"calli %3\", operands, insn); ! 1985: return output_delayed_branch (\"call %3\", operands, insn); ! 1986: }") ! 1987: ! 1988: (define_insn "nop" ! 1989: [(const_int 0)] ! 1990: "" ! 1991: "nop") ! 1992: ! 1993: (define_insn "" ! 1994: [(set (match_operand:SI 0 "register_operand" "r") ! 1995: (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") ! 1996: (label_ref (match_operand 2 "" "")))))] ! 1997: "" ! 1998: "* ! 1999: { ! 2000: cc_status.flags = 0; ! 2001: return \"mov %l2,r31\;ld.l r31(%1),%0\"; ! 2002: }") ! 2003: ! 2004: (define_peephole ! 2005: [(set (match_operand:SI 0 "register_operand" "=rf") ! 2006: (match_operand:SI 1 "single_insn_src_p" "p")) ! 2007: (set (pc) (match_operand:SI 2 "register_operand" "r")) ! 2008: (use (label_ref (match_operand 3 "" "")))] ! 2009: "REGNO (operands[0]) != REGNO (operands[2])" ! 2010: "* return output_delayed_branch (\"bri %2\", operands, insn);") ! 2011: ! 2012: ;;- Local variables: ! 2013: ;;- mode:emacs-lisp ! 2014: ;;- comment-start: ";;- " ! 2015: ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) ! 2016: ;;- eval: (modify-syntax-entry ?[ "(]") ! 2017: ;;- eval: (modify-syntax-entry ?] ")[") ! 2018: ;;- eval: (modify-syntax-entry ?{ "(}") ! 2019: ;;- eval: (modify-syntax-entry ?} "){") ! 2020: ;;- End: ! 2021:
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