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1.1 root 1: /* Subroutines for insn-output.c for Intel 860
2: Copyright (C) 1989, 1991 Free Software Foundation, Inc.
3: Derived from sparc.c.
4:
5: Written by Richard Stallman ([email protected]).
6:
7: Hacked substantially by Ron Guilmette ([email protected]) to cater
8: to the whims of the System V Release 4 assembler.
9:
10: This file is part of GNU CC.
11:
12: GNU CC is free software; you can redistribute it and/or modify
13: it under the terms of the GNU General Public License as published by
14: the Free Software Foundation; either version 2, or (at your option)
15: any later version.
16:
17: GNU CC is distributed in the hope that it will be useful,
18: but WITHOUT ANY WARRANTY; without even the implied warranty of
19: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20: GNU General Public License for more details.
21:
22: You should have received a copy of the GNU General Public License
23: along with GNU CC; see the file COPYING. If not, write to
24: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
25:
26:
27: #include "config.h"
28: #include "flags.h"
29: #include "rtl.h"
30: #include "regs.h"
31: #include "hard-reg-set.h"
32: #include "real.h"
33: #include "insn-config.h"
34: #include "conditions.h"
35: #include "insn-flags.h"
36: #include "output.h"
37: #include "recog.h"
38: #include "insn-attr.h"
39:
40: #include <stdio.h>
41:
42: static rtx find_addr_reg ();
43:
44: #ifndef I860_REG_PREFIX
45: #define I860_REG_PREFIX ""
46: #endif
47:
48: char *i860_reg_prefix = I860_REG_PREFIX;
49:
50: /* Save information from a "cmpxx" operation until the branch is emitted. */
51:
52: rtx i860_compare_op0, i860_compare_op1;
53:
54: /* Return non-zero if this pattern, can be evaluated safely, even if it
55: was not asked for. */
56: int
57: safe_insn_src_p (op, mode)
58: rtx op;
59: enum machine_mode mode;
60: {
61: /* Just experimenting. */
62:
63: /* No floating point src is safe if it contains an arithmetic
64: operation, since that operation may trap. */
65: switch (GET_CODE (op))
66: {
67: case CONST_INT:
68: case LABEL_REF:
69: case SYMBOL_REF:
70: case CONST:
71: return 1;
72:
73: case REG:
74: return 1;
75:
76: case MEM:
77: return CONSTANT_ADDRESS_P (XEXP (op, 0));
78:
79: /* We never need to negate or complement constants. */
80: case NEG:
81: return (mode != SFmode && mode != DFmode);
82: case NOT:
83: case ZERO_EXTEND:
84: return 1;
85:
86: case EQ:
87: case NE:
88: case LT:
89: case GT:
90: case LE:
91: case GE:
92: case LTU:
93: case GTU:
94: case LEU:
95: case GEU:
96: case MINUS:
97: case PLUS:
98: return (mode != SFmode && mode != DFmode);
99: case AND:
100: case IOR:
101: case XOR:
102: case LSHIFT:
103: case ASHIFT:
104: case ASHIFTRT:
105: case LSHIFTRT:
106: if ((GET_CODE (XEXP (op, 0)) == CONST_INT && ! SMALL_INT (XEXP (op, 0)))
107: || (GET_CODE (XEXP (op, 1)) == CONST_INT && ! SMALL_INT (XEXP (op, 1))))
108: return 0;
109: return 1;
110:
111: default:
112: return 0;
113: }
114: }
115:
116: /* Return 1 if REG is clobbered in IN.
117: Return 2 if REG is used in IN.
118: Return 3 if REG is both used and clobbered in IN.
119: Return 0 if neither. */
120:
121: static int
122: reg_clobbered_p (reg, in)
123: rtx reg;
124: rtx in;
125: {
126: register enum rtx_code code;
127:
128: if (in == 0)
129: return 0;
130:
131: code = GET_CODE (in);
132:
133: if (code == SET || code == CLOBBER)
134: {
135: rtx dest = SET_DEST (in);
136: int set = 0;
137: int used = 0;
138:
139: while (GET_CODE (dest) == STRICT_LOW_PART
140: || GET_CODE (dest) == SUBREG
141: || GET_CODE (dest) == SIGN_EXTRACT
142: || GET_CODE (dest) == ZERO_EXTRACT)
143: dest = XEXP (dest, 0);
144:
145: if (dest == reg)
146: set = 1;
147: else if (GET_CODE (dest) == REG
148: && refers_to_regno_p (REGNO (reg),
149: REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
150: SET_DEST (in), 0))
151: {
152: set = 1;
153: /* Anything that sets just part of the register
154: is considered using as well as setting it.
155: But note that a straight SUBREG of a single-word value
156: clobbers the entire value. */
157: if (dest != SET_DEST (in)
158: && ! (GET_CODE (SET_DEST (in)) == SUBREG
159: || UNITS_PER_WORD >= GET_MODE_SIZE (GET_MODE (dest))))
160: used = 1;
161: }
162:
163: if (code == SET)
164: {
165: if (set)
166: used = refers_to_regno_p (REGNO (reg),
167: REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
168: SET_SRC (in), 0);
169: else
170: used = refers_to_regno_p (REGNO (reg),
171: REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
172: in, 0);
173: }
174:
175: return set + used * 2;
176: }
177:
178: if (refers_to_regno_p (REGNO (reg),
179: REGNO (reg) + HARD_REGNO_NREGS (reg, GET_MODE (reg)),
180: in, 0))
181: return 2;
182: return 0;
183: }
184:
185: /* Return non-zero if OP can be written to without screwing up
186: GCC's model of what's going on. It is assumed that this operand
187: appears in the dest position of a SET insn in a conditional
188: branch's delay slot. AFTER is the label to start looking from. */
189: int
190: operand_clobbered_before_used_after (op, after)
191: rtx op;
192: rtx after;
193: {
194: /* Just experimenting. */
195: if (GET_CODE (op) == CC0)
196: return 1;
197: if (GET_CODE (op) == REG)
198: {
199: rtx insn;
200:
201: if (op == stack_pointer_rtx)
202: return 0;
203:
204: /* Scan forward from the label, to see if the value of OP
205: is clobbered before the first use. */
206:
207: for (insn = NEXT_INSN (after); insn; insn = NEXT_INSN (insn))
208: {
209: if (GET_CODE (insn) == NOTE)
210: continue;
211: if (GET_CODE (insn) == INSN
212: || GET_CODE (insn) == JUMP_INSN
213: || GET_CODE (insn) == CALL_INSN)
214: {
215: switch (reg_clobbered_p (op, PATTERN (insn)))
216: {
217: default:
218: return 0;
219: case 1:
220: return 1;
221: case 0:
222: break;
223: }
224: }
225: /* If we reach another label without clobbering OP,
226: then we cannot safely write it here. */
227: else if (GET_CODE (insn) == CODE_LABEL)
228: return 0;
229: if (GET_CODE (insn) == JUMP_INSN)
230: {
231: if (condjump_p (insn))
232: return 0;
233: /* This is a jump insn which has already
234: been mangled. We can't tell what it does. */
235: if (GET_CODE (PATTERN (insn)) == PARALLEL)
236: return 0;
237: if (! JUMP_LABEL (insn))
238: return 0;
239: /* Keep following jumps. */
240: insn = JUMP_LABEL (insn);
241: }
242: }
243: return 1;
244: }
245:
246: /* In both of these cases, the first insn executed
247: for this op will be a orh whatever%h,%?r0,%?r31,
248: which is tolerable. */
249: if (GET_CODE (op) == MEM)
250: return (CONSTANT_ADDRESS_P (XEXP (op, 0)));
251:
252: return 0;
253: }
254:
255: /* Return non-zero if this pattern, as a source to a "SET",
256: is known to yield an instruction of unit size. */
257: int
258: single_insn_src_p (op, mode)
259: rtx op;
260: enum machine_mode mode;
261: {
262: switch (GET_CODE (op))
263: {
264: case CONST_INT:
265: /* This is not always a single insn src, technically,
266: but output_delayed_branch knows how to deal with it. */
267: return 1;
268:
269: case SYMBOL_REF:
270: case CONST:
271: /* This is not a single insn src, technically,
272: but output_delayed_branch knows how to deal with it. */
273: return 1;
274:
275: case REG:
276: return 1;
277:
278: case MEM:
279: return 1;
280:
281: /* We never need to negate or complement constants. */
282: case NEG:
283: return (mode != DFmode);
284: case NOT:
285: case ZERO_EXTEND:
286: return 1;
287:
288: case PLUS:
289: case MINUS:
290: /* Detect cases that require multiple instructions. */
291: if (CONSTANT_P (XEXP (op, 1))
292: && !(GET_CODE (XEXP (op, 1)) == CONST_INT
293: && SMALL_INT (XEXP (op, 1))))
294: return 0;
295: case EQ:
296: case NE:
297: case LT:
298: case GT:
299: case LE:
300: case GE:
301: case LTU:
302: case GTU:
303: case LEU:
304: case GEU:
305: /* Not doing floating point, since they probably
306: take longer than the branch slot they might fill. */
307: return (mode != SFmode && mode != DFmode);
308:
309: case AND:
310: if (GET_CODE (XEXP (op, 1)) == NOT)
311: {
312: rtx arg = XEXP (XEXP (op, 1), 0);
313: if (CONSTANT_P (arg)
314: && !(GET_CODE (arg) == CONST_INT
315: && (SMALL_INT (arg)
316: || INTVAL (arg) & 0xffff == 0)))
317: return 0;
318: }
319: case IOR:
320: case XOR:
321: /* Both small and round numbers take one instruction;
322: others take two. */
323: if (CONSTANT_P (XEXP (op, 1))
324: && !(GET_CODE (XEXP (op, 1)) == CONST_INT
325: && (SMALL_INT (XEXP (op, 1))
326: || INTVAL (XEXP (op, 1)) & 0xffff == 0)))
327: return 0;
328:
329: case LSHIFT:
330: case ASHIFT:
331: case ASHIFTRT:
332: case LSHIFTRT:
333: return 1;
334:
335: case SUBREG:
336: if (SUBREG_WORD (op) != 0)
337: return 0;
338: return single_insn_src_p (SUBREG_REG (op), mode);
339:
340: /* Not doing floating point, since they probably
341: take longer than the branch slot they might fill. */
342: case FLOAT_EXTEND:
343: case FLOAT_TRUNCATE:
344: case FLOAT:
345: case FIX:
346: case UNSIGNED_FLOAT:
347: case UNSIGNED_FIX:
348: return 0;
349:
350: default:
351: return 0;
352: }
353: }
354:
355: /* Return non-zero only if OP is a register of mode MODE,
356: or const0_rtx. */
357: int
358: reg_or_0_operand (op, mode)
359: rtx op;
360: enum machine_mode mode;
361: {
362: return (op == const0_rtx || register_operand (op, mode)
363: || op == CONST0_RTX (mode));
364: }
365:
366: /* Return truth value of whether OP can be used as an operands in a three
367: address add/subtract insn (such as add %o1,7,%l2) of mode MODE. */
368:
369: int
370: arith_operand (op, mode)
371: rtx op;
372: enum machine_mode mode;
373: {
374: return (register_operand (op, mode)
375: || (GET_CODE (op) == CONST_INT && SMALL_INT (op)));
376: }
377:
378: /* Return 1 if OP is a valid first operand for a logical insn of mode MODE. */
379:
380: int
381: logic_operand (op, mode)
382: rtx op;
383: enum machine_mode mode;
384: {
385: return (register_operand (op, mode)
386: || (GET_CODE (op) == CONST_INT && LOGIC_INT (op)));
387: }
388:
389: /* Return 1 if OP is a valid first operand for a shift insn of mode MODE. */
390:
391: int
392: shift_operand (op, mode)
393: rtx op;
394: enum machine_mode mode;
395: {
396: return (register_operand (op, mode)
397: || (GET_CODE (op) == CONST_INT));
398: }
399:
400: /* Return 1 if OP is a valid first operand for either a logical insn
401: or an add insn of mode MODE. */
402:
403: int
404: compare_operand (op, mode)
405: rtx op;
406: enum machine_mode mode;
407: {
408: return (register_operand (op, mode)
409: || (GET_CODE (op) == CONST_INT && SMALL_INT (op) && LOGIC_INT (op)));
410: }
411:
412: /* Return truth value of whether OP can be used as the 5-bit immediate
413: operand of a bte or btne insn. */
414:
415: int
416: bte_operand (op, mode)
417: rtx op;
418: enum machine_mode mode;
419: {
420: return (register_operand (op, mode)
421: || (GET_CODE (op) == CONST_INT
422: && (unsigned) INTVAL (op) < 0x20));
423: }
424:
425: /* Return 1 if OP is an indexed memory reference of mode MODE. */
426:
427: int
428: indexed_operand (op, mode)
429: rtx op;
430: enum machine_mode mode;
431: {
432: return (GET_CODE (op) == MEM && GET_MODE (op) == mode
433: && GET_CODE (XEXP (op, 0)) == PLUS
434: && GET_MODE (XEXP (op, 0)) == SImode
435: && register_operand (XEXP (XEXP (op, 0), 0), SImode)
436: && register_operand (XEXP (XEXP (op, 0), 1), SImode));
437: }
438:
439: /* Return 1 if OP is a suitable source operand for a load insn
440: with mode MODE. */
441:
442: int
443: load_operand (op, mode)
444: rtx op;
445: enum machine_mode mode;
446: {
447: return (memory_operand (op, mode) || indexed_operand (op, mode));
448: }
449:
450: /* Return truth value of whether OP is a integer which fits the
451: range constraining immediate operands in add/subtract insns. */
452:
453: int
454: small_int (op, mode)
455: rtx op;
456: enum machine_mode mode;
457: {
458: return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
459: }
460:
461: /* Return truth value of whether OP is a integer which fits the
462: range constraining immediate operands in logic insns. */
463:
464: int
465: logic_int (op, mode)
466: rtx op;
467: enum machine_mode mode;
468: {
469: return (GET_CODE (op) == CONST_INT && LOGIC_INT (op));
470: }
471:
472: /* Test for a valid operand for a call instruction.
473: Don't allow the arg pointer register or virtual regs
474: since they may change into reg + const, which the patterns
475: can't handle yet. */
476:
477: int
478: call_insn_operand (op, mode)
479: rtx op;
480: enum machine_mode mode;
481: {
482: if (GET_CODE (op) == MEM
483: && (CONSTANT_ADDRESS_P (XEXP (op, 0))
484: || (GET_CODE (XEXP (op, 0)) == REG
485: && XEXP (op, 0) != arg_pointer_rtx
486: && !(REGNO (XEXP (op, 0)) >= FIRST_PSEUDO_REGISTER
487: && REGNO (XEXP (op, 0)) <= LAST_VIRTUAL_REGISTER))))
488: return 1;
489: return 0;
490: }
491:
492: /* Return the best assembler insn template
493: for moving operands[1] into operands[0] as a fullword. */
494:
495: static char *
496: singlemove_string (operands)
497: rtx *operands;
498: {
499: if (GET_CODE (operands[0]) == MEM)
500: {
501: if (GET_CODE (operands[1]) != MEM)
502: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
503: {
504: if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
505: && (cc_prev_status.flags & CC_HI_R31_ADJ)
506: && cc_prev_status.mdep == XEXP (operands[0], 0)))
507: {
508: CC_STATUS_INIT;
509: output_asm_insn ("orh %h0,%?r0,%?r31", operands);
510: }
511: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
512: cc_status.mdep = XEXP (operands[0], 0);
513: return "st.l %r1,%L0(%?r31)";
514: }
515: else
516: return "st.l %r1,%0";
517: else
518: abort ();
519: #if 0
520: {
521: rtx xoperands[2];
522:
523: cc_status.flags &= ~CC_F0_IS_0;
524: xoperands[0] = gen_rtx (REG, SFmode, 32);
525: xoperands[1] = operands[1];
526: output_asm_insn (singlemove_string (xoperands), xoperands);
527: xoperands[1] = xoperands[0];
528: xoperands[0] = operands[0];
529: output_asm_insn (singlemove_string (xoperands), xoperands);
530: return "";
531: }
532: #endif
533: }
534: if (GET_CODE (operands[1]) == MEM)
535: {
536: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
537: {
538: if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
539: && (cc_prev_status.flags & CC_HI_R31_ADJ)
540: && cc_prev_status.mdep == XEXP (operands[1], 0)))
541: {
542: CC_STATUS_INIT;
543: output_asm_insn ("orh %h1,%?r0,%?r31", operands);
544: }
545: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
546: cc_status.mdep = XEXP (operands[1], 0);
547: return "ld.l %L1(%?r31),%0";
548: }
549: return "ld.l %m1,%0";
550: }
551: if (GET_CODE (operands[1]) == CONST_INT)
552: {
553: if (operands[1] == const0_rtx)
554: return "mov %?r0,%0";
555: if((INTVAL (operands[1]) & 0xffff0000) == 0)
556: return "or %L1,%?r0,%0";
557: if((INTVAL (operands[1]) & 0xffff8000) == 0xffff8000)
558: return "adds %1,%?r0,%0";
559: if((INTVAL (operands[1]) & 0x0000ffff) == 0)
560: return "orh %H1,%?r0,%0";
561: }
562: return "mov %1,%0";
563: }
564:
565: /* Output assembler code to perform a doubleword move insn
566: with operands OPERANDS. */
567:
568: char *
569: output_move_double (operands)
570: rtx *operands;
571: {
572: enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
573: rtx latehalf[2];
574: rtx addreg0 = 0, addreg1 = 0;
575:
576: /* First classify both operands. */
577:
578: if (REG_P (operands[0]))
579: optype0 = REGOP;
580: else if (offsettable_memref_p (operands[0]))
581: optype0 = OFFSOP;
582: else if (GET_CODE (operands[0]) == MEM)
583: optype0 = MEMOP;
584: else
585: optype0 = RNDOP;
586:
587: if (REG_P (operands[1]))
588: optype1 = REGOP;
589: else if (CONSTANT_P (operands[1]))
590: optype1 = CNSTOP;
591: else if (offsettable_memref_p (operands[1]))
592: optype1 = OFFSOP;
593: else if (GET_CODE (operands[1]) == MEM)
594: optype1 = MEMOP;
595: else
596: optype1 = RNDOP;
597:
598: /* Check for the cases that the operand constraints are not
599: supposed to allow to happen. Abort if we get one,
600: because generating code for these cases is painful. */
601:
602: if (optype0 == RNDOP || optype1 == RNDOP)
603: abort ();
604:
605: /* If an operand is an unoffsettable memory ref, find a register
606: we can increment temporarily to make it refer to the second word. */
607:
608: if (optype0 == MEMOP)
609: addreg0 = find_addr_reg (XEXP (operands[0], 0));
610:
611: if (optype1 == MEMOP)
612: addreg1 = find_addr_reg (XEXP (operands[1], 0));
613:
614: /* ??? Perhaps in some cases move double words
615: if there is a spare pair of floating regs. */
616:
617: /* Ok, we can do one word at a time.
618: Normally we do the low-numbered word first,
619: but if either operand is autodecrementing then we
620: do the high-numbered word first.
621:
622: In either case, set up in LATEHALF the operands to use
623: for the high-numbered word and in some cases alter the
624: operands in OPERANDS to be suitable for the low-numbered word. */
625:
626: if (optype0 == REGOP)
627: latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
628: else if (optype0 == OFFSOP)
629: latehalf[0] = adj_offsettable_operand (operands[0], 4);
630: else
631: latehalf[0] = operands[0];
632:
633: if (optype1 == REGOP)
634: latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
635: else if (optype1 == OFFSOP)
636: latehalf[1] = adj_offsettable_operand (operands[1], 4);
637: else if (optype1 == CNSTOP)
638: {
639: if (GET_CODE (operands[1]) == CONST_DOUBLE)
640: split_double (operands[1], &operands[1], &latehalf[1]);
641: else if (CONSTANT_P (operands[1]))
642: latehalf[1] = const0_rtx;
643: }
644: else
645: latehalf[1] = operands[1];
646:
647: /* If the first move would clobber the source of the second one,
648: do them in the other order.
649:
650: RMS says "This happens only for registers;
651: such overlap can't happen in memory unless the user explicitly
652: sets it up, and that is an undefined circumstance."
653:
654: but it happens on the sparc when loading parameter registers,
655: so I am going to define that circumstance, and make it work
656: as expected. */
657:
658: if (optype0 == REGOP && optype1 == REGOP
659: && REGNO (operands[0]) == REGNO (latehalf[1]))
660: {
661: CC_STATUS_PARTIAL_INIT;
662: /* Make any unoffsettable addresses point at high-numbered word. */
663: if (addreg0)
664: output_asm_insn ("adds 0x4,%0,%0", &addreg0);
665: if (addreg1)
666: output_asm_insn ("adds 0x4,%0,%0", &addreg1);
667:
668: /* Do that word. */
669: output_asm_insn (singlemove_string (latehalf), latehalf);
670:
671: /* Undo the adds we just did. */
672: if (addreg0)
673: output_asm_insn ("adds -0x4,%0,%0", &addreg0);
674: if (addreg1)
675: output_asm_insn ("adds -0x4,%0,%0", &addreg1);
676:
677: /* Do low-numbered word. */
678: return singlemove_string (operands);
679: }
680: else if (optype0 == REGOP && optype1 != REGOP
681: && reg_overlap_mentioned_p (operands[0], operands[1]))
682: {
683: /* Do the late half first. */
684: output_asm_insn (singlemove_string (latehalf), latehalf);
685: /* Then clobber. */
686: return singlemove_string (operands);
687: }
688:
689: /* Normal case: do the two words, low-numbered first. */
690:
691: output_asm_insn (singlemove_string (operands), operands);
692:
693: CC_STATUS_PARTIAL_INIT;
694: /* Make any unoffsettable addresses point at high-numbered word. */
695: if (addreg0)
696: output_asm_insn ("adds 0x4,%0,%0", &addreg0);
697: if (addreg1)
698: output_asm_insn ("adds 0x4,%0,%0", &addreg1);
699:
700: /* Do that word. */
701: output_asm_insn (singlemove_string (latehalf), latehalf);
702:
703: /* Undo the adds we just did. */
704: if (addreg0)
705: output_asm_insn ("adds -0x4,%0,%0", &addreg0);
706: if (addreg1)
707: output_asm_insn ("adds -0x4,%0,%0", &addreg1);
708:
709: return "";
710: }
711:
712: char *
713: output_fp_move_double (operands)
714: rtx *operands;
715: {
716: /* If the source operand is any sort of zero, use f0 instead. */
717:
718: if (operands[1] == CONST0_RTX (GET_MODE (operands[1])))
719: operands[1] = gen_rtx (REG, DFmode, F0_REGNUM);
720:
721: if (FP_REG_P (operands[0]))
722: {
723: if (FP_REG_P (operands[1]))
724: return "fmov.dd %1,%0";
725: if (GET_CODE (operands[1]) == REG)
726: {
727: output_asm_insn ("ixfr %1,%0", operands);
728: operands[0] = gen_rtx (REG, VOIDmode, REGNO (operands[0]) + 1);
729: operands[1] = gen_rtx (REG, VOIDmode, REGNO (operands[1]) + 1);
730: return "ixfr %1,%0";
731: }
732: if (operands[1] == CONST0_RTX (DFmode))
733: return "fmov.dd f0,%0";
734: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
735: {
736: if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
737: && (cc_prev_status.flags & CC_HI_R31_ADJ)
738: && cc_prev_status.mdep == XEXP (operands[1], 0)))
739: {
740: CC_STATUS_INIT;
741: output_asm_insn ("orh %h1,%?r0,%?r31", operands);
742: }
743: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
744: cc_status.mdep = XEXP (operands[1], 0);
745: return "fld.d %L1(%?r31),%0";
746: }
747: return "fld.d %1,%0";
748: }
749: else if (FP_REG_P (operands[1]))
750: {
751: if (GET_CODE (operands[0]) == REG)
752: {
753: output_asm_insn ("fxfr %1,%0", operands);
754: operands[0] = gen_rtx (REG, VOIDmode, REGNO (operands[0]) + 1);
755: operands[1] = gen_rtx (REG, VOIDmode, REGNO (operands[1]) + 1);
756: return "fxfr %1,%0";
757: }
758: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
759: {
760: if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
761: && (cc_prev_status.flags & CC_HI_R31_ADJ)
762: && cc_prev_status.mdep == XEXP (operands[0], 0)))
763: {
764: CC_STATUS_INIT;
765: output_asm_insn ("orh %h0,%?r0,%?r31", operands);
766: }
767: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
768: cc_status.mdep = XEXP (operands[0], 0);
769: return "fst.d %1,%L0(%?r31)";
770: }
771: return "fst.d %1,%0";
772: }
773: else
774: abort ();
775: /* NOTREACHED */
776: return NULL;
777: }
778:
779: /* Return a REG that occurs in ADDR with coefficient 1.
780: ADDR can be effectively incremented by incrementing REG. */
781:
782: static rtx
783: find_addr_reg (addr)
784: rtx addr;
785: {
786: while (GET_CODE (addr) == PLUS)
787: {
788: if (GET_CODE (XEXP (addr, 0)) == REG)
789: addr = XEXP (addr, 0);
790: else if (GET_CODE (XEXP (addr, 1)) == REG)
791: addr = XEXP (addr, 1);
792: else if (CONSTANT_P (XEXP (addr, 0)))
793: addr = XEXP (addr, 1);
794: else if (CONSTANT_P (XEXP (addr, 1)))
795: addr = XEXP (addr, 0);
796: else
797: abort ();
798: }
799: if (GET_CODE (addr) == REG)
800: return addr;
801: abort ();
802: /* NOTREACHED */
803: return NULL;
804: }
805:
806: /* Return a template for a load instruction with mode MODE and
807: arguments from the string ARGS.
808:
809: This string is in static storage. */
810:
811: static char *
812: load_opcode (mode, args, reg)
813: enum machine_mode mode;
814: char *args;
815: rtx reg;
816: {
817: static char buf[30];
818: char *opcode;
819:
820: switch (mode)
821: {
822: case QImode:
823: opcode = "ld.b";
824: break;
825:
826: case HImode:
827: opcode = "ld.s";
828: break;
829:
830: case SImode:
831: case SFmode:
832: if (FP_REG_P (reg))
833: opcode = "fld.l";
834: else
835: opcode = "ld.l";
836: break;
837:
838: case DImode:
839: if (!FP_REG_P (reg))
840: abort ();
841: case DFmode:
842: opcode = "fld.d";
843: break;
844:
845: default:
846: abort ();
847: }
848:
849: sprintf (buf, "%s %s", opcode, args);
850: return buf;
851: }
852:
853: /* Return a template for a store instruction with mode MODE and
854: arguments from the string ARGS.
855:
856: This string is in static storage. */
857:
858: static char *
859: store_opcode (mode, args, reg)
860: enum machine_mode mode;
861: char *args;
862: rtx reg;
863: {
864: static char buf[30];
865: char *opcode;
866:
867: switch (mode)
868: {
869: case QImode:
870: opcode = "st.b";
871: break;
872:
873: case HImode:
874: opcode = "st.s";
875: break;
876:
877: case SImode:
878: case SFmode:
879: if (FP_REG_P (reg))
880: opcode = "fst.l";
881: else
882: opcode = "st.l";
883: break;
884:
885: case DImode:
886: if (!FP_REG_P (reg))
887: abort ();
888: case DFmode:
889: opcode = "fst.d";
890: break;
891:
892: default:
893: abort ();
894: }
895:
896: sprintf (buf, "%s %s", opcode, args);
897: return buf;
898: }
899:
900: /* Output a store-in-memory whose operands are OPERANDS[0,1].
901: OPERANDS[0] is a MEM, and OPERANDS[1] is a reg or zero.
902:
903: This function returns a template for an insn.
904: This is in static storage.
905:
906: It may also output some insns directly.
907: It may alter the values of operands[0] and operands[1]. */
908:
909: char *
910: output_store (operands)
911: rtx *operands;
912: {
913: enum machine_mode mode = GET_MODE (operands[0]);
914: rtx address = XEXP (operands[0], 0);
915: char *string;
916:
917: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
918: cc_status.mdep = address;
919:
920: if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
921: && (cc_prev_status.flags & CC_HI_R31_ADJ)
922: && address == cc_prev_status.mdep))
923: {
924: CC_STATUS_INIT;
925: output_asm_insn ("orh %h0,%?r0,%?r31", operands);
926: cc_prev_status.mdep = address;
927: }
928:
929: /* Store zero in two parts when appropriate. */
930: if (mode == DFmode && operands[1] == CONST0_RTX (DFmode))
931: return store_opcode (DFmode, "%r1,%L0(%?r31)", operands[1]);
932:
933: /* Code below isn't smart enough to move a doubleword in two parts,
934: so use output_move_double to do that in the cases that require it. */
935: if ((mode == DImode || mode == DFmode)
936: && ! FP_REG_P (operands[1]))
937: return output_move_double (operands);
938:
939: return store_opcode (mode, "%r1,%L0(%?r31)", operands[1]);
940: }
941:
942: /* Output a load-from-memory whose operands are OPERANDS[0,1].
943: OPERANDS[0] is a reg, and OPERANDS[1] is a mem.
944:
945: This function returns a template for an insn.
946: This is in static storage.
947:
948: It may also output some insns directly.
949: It may alter the values of operands[0] and operands[1]. */
950:
951: char *
952: output_load (operands)
953: rtx *operands;
954: {
955: enum machine_mode mode = GET_MODE (operands[0]);
956: rtx address = XEXP (operands[1], 0);
957:
958: /* We don't bother trying to see if we know %hi(address).
959: This is because we are doing a load, and if we know the
960: %hi value, we probably also know that value in memory. */
961: cc_status.flags |= CC_KNOW_HI_R31 | CC_HI_R31_ADJ;
962: cc_status.mdep = address;
963:
964: if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
965: && (cc_prev_status.flags & CC_HI_R31_ADJ)
966: && address == cc_prev_status.mdep
967: && cc_prev_status.mdep == cc_status.mdep))
968: {
969: CC_STATUS_INIT;
970: output_asm_insn ("orh %h1,%?r0,%?r31", operands);
971: cc_prev_status.mdep = address;
972: }
973:
974: /* Code below isn't smart enough to move a doubleword in two parts,
975: so use output_move_double to do that in the cases that require it. */
976: if ((mode == DImode || mode == DFmode)
977: && ! FP_REG_P (operands[0]))
978: return output_move_double (operands);
979:
980: return load_opcode (mode, "%L1(%?r31),%0", operands[0]);
981: }
982:
983: #if 0
984: /* Load the address specified by OPERANDS[3] into the register
985: specified by OPERANDS[0].
986:
987: OPERANDS[3] may be the result of a sum, hence it could either be:
988:
989: (1) CONST
990: (2) REG
991: (2) REG + CONST_INT
992: (3) REG + REG + CONST_INT
993: (4) REG + REG (special case of 3).
994:
995: Note that (3) is not a legitimate address.
996: All cases are handled here. */
997:
998: void
999: output_load_address (operands)
1000: rtx *operands;
1001: {
1002: rtx base, offset;
1003:
1004: if (CONSTANT_P (operands[3]))
1005: {
1006: output_asm_insn ("mov %3,%0", operands);
1007: return;
1008: }
1009:
1010: if (REG_P (operands[3]))
1011: {
1012: if (REGNO (operands[0]) != REGNO (operands[3]))
1013: output_asm_insn ("shl %?r0,%3,%0", operands);
1014: return;
1015: }
1016:
1017: if (GET_CODE (operands[3]) != PLUS)
1018: abort ();
1019:
1020: base = XEXP (operands[3], 0);
1021: offset = XEXP (operands[3], 1);
1022:
1023: if (GET_CODE (base) == CONST_INT)
1024: {
1025: rtx tmp = base;
1026: base = offset;
1027: offset = tmp;
1028: }
1029:
1030: if (GET_CODE (offset) != CONST_INT)
1031: {
1032: /* Operand is (PLUS (REG) (REG)). */
1033: base = operands[3];
1034: offset = const0_rtx;
1035: }
1036:
1037: if (REG_P (base))
1038: {
1039: operands[6] = base;
1040: operands[7] = offset;
1041: CC_STATUS_PARTIAL_INIT;
1042: if (SMALL_INT (offset))
1043: output_asm_insn ("adds %7,%6,%0", operands);
1044: else
1045: output_asm_insn ("mov %7,%0\n\tadds %0,%6,%0", operands);
1046: }
1047: else if (GET_CODE (base) == PLUS)
1048: {
1049: operands[6] = XEXP (base, 0);
1050: operands[7] = XEXP (base, 1);
1051: operands[8] = offset;
1052:
1053: CC_STATUS_PARTIAL_INIT;
1054: if (SMALL_INT (offset))
1055: output_asm_insn ("adds %6,%7,%0\n\tadds %8,%0,%0", operands);
1056: else
1057: output_asm_insn ("mov %8,%0\n\tadds %0,%6,%0\n\tadds %0,%7,%0", operands);
1058: }
1059: else
1060: abort ();
1061: }
1062: #endif
1063:
1064: /* Output code to place a size count SIZE in register REG.
1065: Because block moves are pipelined, we don't include the
1066: first element in the transfer of SIZE to REG.
1067: For this, we subtract ALIGN. (Actually, I think it is not
1068: right to subtract on this machine, so right now we don't.) */
1069:
1070: static void
1071: output_size_for_block_move (size, reg, align)
1072: rtx size, reg, align;
1073: {
1074: rtx xoperands[3];
1075:
1076: xoperands[0] = reg;
1077: xoperands[1] = size;
1078: xoperands[2] = align;
1079:
1080: #if 1
1081: cc_status.flags &= ~ CC_KNOW_HI_R31;
1082: output_asm_insn (singlemove_string (xoperands), xoperands);
1083: #else
1084: if (GET_CODE (size) == REG)
1085: output_asm_insn ("sub %2,%1,%0", xoperands);
1086: else
1087: {
1088: xoperands[1]
1089: = gen_rtx (CONST_INT, VOIDmode, INTVAL (size) - INTVAL (align));
1090: cc_status.flags &= ~ CC_KNOW_HI_R31;
1091: output_asm_insn ("mov %1,%0", xoperands);
1092: }
1093: #endif
1094: }
1095:
1096: /* Emit code to perform a block move.
1097:
1098: OPERANDS[0] is the destination.
1099: OPERANDS[1] is the source.
1100: OPERANDS[2] is the size.
1101: OPERANDS[3] is the known safe alignment.
1102: OPERANDS[4..6] are pseudos we can safely clobber as temps. */
1103:
1104: char *
1105: output_block_move (operands)
1106: rtx *operands;
1107: {
1108: /* A vector for our computed operands. Note that load_output_address
1109: makes use of (and can clobber) up to the 8th element of this vector. */
1110: rtx xoperands[10];
1111: rtx zoperands[10];
1112: static int movstrsi_label = 0;
1113: int i, j;
1114: rtx temp1 = operands[4];
1115: rtx alignrtx = operands[3];
1116: int align = INTVAL (alignrtx);
1117: int chunk_size;
1118:
1119: xoperands[0] = operands[0];
1120: xoperands[1] = operands[1];
1121: xoperands[2] = temp1;
1122:
1123: /* We can't move more than four bytes at a time
1124: because we have only one register to move them through. */
1125: if (align > 4)
1126: {
1127: align = 4;
1128: alignrtx = gen_rtx (CONST_INT, VOIDmode, 4);
1129: }
1130:
1131: /* Recognize special cases of block moves. These occur
1132: when GNU C++ is forced to treat something as BLKmode
1133: to keep it in memory, when its mode could be represented
1134: with something smaller.
1135:
1136: We cannot do this for global variables, since we don't know
1137: what pages they don't cross. Sigh. */
1138: if (GET_CODE (operands[2]) == CONST_INT
1139: && ! CONSTANT_ADDRESS_P (operands[0])
1140: && ! CONSTANT_ADDRESS_P (operands[1]))
1141: {
1142: int size = INTVAL (operands[2]);
1143: rtx op0 = xoperands[0];
1144: rtx op1 = xoperands[1];
1145:
1146: if ((align & 3) == 0 && (size & 3) == 0 && (size >> 2) <= 16)
1147: {
1148: if (memory_address_p (SImode, plus_constant (op0, size))
1149: && memory_address_p (SImode, plus_constant (op1, size)))
1150: {
1151: cc_status.flags &= ~CC_KNOW_HI_R31;
1152: for (i = (size>>2)-1; i >= 0; i--)
1153: {
1154: xoperands[0] = plus_constant (op0, i * 4);
1155: xoperands[1] = plus_constant (op1, i * 4);
1156: output_asm_insn ("ld.l %a1,%?r31\n\tst.l %?r31,%a0",
1157: xoperands);
1158: }
1159: return "";
1160: }
1161: }
1162: else if ((align & 1) == 0 && (size & 1) == 0 && (size >> 1) <= 16)
1163: {
1164: if (memory_address_p (HImode, plus_constant (op0, size))
1165: && memory_address_p (HImode, plus_constant (op1, size)))
1166: {
1167: cc_status.flags &= ~CC_KNOW_HI_R31;
1168: for (i = (size>>1)-1; i >= 0; i--)
1169: {
1170: xoperands[0] = plus_constant (op0, i * 2);
1171: xoperands[1] = plus_constant (op1, i * 2);
1172: output_asm_insn ("ld.s %a1,%?r31\n\tst.s %?r31,%a0",
1173: xoperands);
1174: }
1175: return "";
1176: }
1177: }
1178: else if (size <= 16)
1179: {
1180: if (memory_address_p (QImode, plus_constant (op0, size))
1181: && memory_address_p (QImode, plus_constant (op1, size)))
1182: {
1183: cc_status.flags &= ~CC_KNOW_HI_R31;
1184: for (i = size-1; i >= 0; i--)
1185: {
1186: xoperands[0] = plus_constant (op0, i);
1187: xoperands[1] = plus_constant (op1, i);
1188: output_asm_insn ("ld.b %a1,%?r31\n\tst.b %?r31,%a0",
1189: xoperands);
1190: }
1191: return "";
1192: }
1193: }
1194: }
1195:
1196: /* Since we clobber untold things, nix the condition codes. */
1197: CC_STATUS_INIT;
1198:
1199: /* This is the size of the transfer.
1200: Either use the register which already contains the size,
1201: or use a free register (used by no operands). */
1202: output_size_for_block_move (operands[2], operands[4], alignrtx);
1203:
1204: #if 0
1205: /* Also emit code to decrement the size value by ALIGN. */
1206: zoperands[0] = operands[0];
1207: zoperands[3] = plus_constant (operands[0], align);
1208: output_load_address (zoperands);
1209: #endif
1210:
1211: /* Generate number for unique label. */
1212:
1213: xoperands[3] = gen_rtx (CONST_INT, VOIDmode, movstrsi_label++);
1214:
1215: /* Calculate the size of the chunks we will be trying to move first. */
1216:
1217: #if 0
1218: if ((align & 3) == 0)
1219: chunk_size = 4;
1220: else if ((align & 1) == 0)
1221: chunk_size = 2;
1222: else
1223: #endif
1224: chunk_size = 1;
1225:
1226: /* Copy the increment (negative) to a register for bla insn. */
1227:
1228: xoperands[4] = gen_rtx (CONST_INT, VOIDmode, - chunk_size);
1229: xoperands[5] = operands[5];
1230: output_asm_insn ("adds %4,%?r0,%5", xoperands);
1231:
1232: /* Predecrement the loop counter. This happens again also in the `bla'
1233: instruction which precedes the loop, but we need to have it done
1234: two times before we enter the loop because of the bizarre semantics
1235: of the bla instruction. */
1236:
1237: output_asm_insn ("adds %5,%2,%2", xoperands);
1238:
1239: /* Check for the case where the original count was less than or equal to
1240: zero. Avoid going through the loop at all if the original count was
1241: indeed less than or equal to zero. Note that we treat the count as
1242: if it were a signed 32-bit quantity here, rather than an unsigned one,
1243: even though we really shouldn't. We have to do this because of the
1244: semantics of the `ble' instruction, which assume that the count is
1245: a signed 32-bit value. Anyway, in practice it won't matter because
1246: nobody is going to try to do a memcpy() of more than half of the
1247: entire address space (i.e. 2 gigabytes) anyway. */
1248:
1249: output_asm_insn ("bc .Le%3", xoperands);
1250:
1251: /* Make available a register which is a temporary. */
1252:
1253: xoperands[6] = operands[6];
1254:
1255: /* Now the actual loop.
1256: In xoperands, elements 1 and 0 are the input and output vectors.
1257: Element 2 is the loop index. Element 5 is the increment. */
1258:
1259: output_asm_insn ("subs %1,%5,%1", xoperands);
1260: output_asm_insn ("bla %5,%2,.Lm%3", xoperands);
1261: output_asm_insn ("adds %0,%2,%6", xoperands);
1262: output_asm_insn ("\n.Lm%3:", xoperands); /* Label for bla above. */
1263: output_asm_insn ("\n.Ls%3:", xoperands); /* Loop start label. */
1264: output_asm_insn ("adds %5,%6,%6", xoperands);
1265:
1266: /* NOTE: The code here which is supposed to handle the cases where the
1267: sources and destinations are known to start on a 4 or 2 byte boundary
1268: are currently broken. They fail to do anything about the overflow
1269: bytes which might still need to be copied even after we have copied
1270: some number of words or halfwords. Thus, for now we use the lowest
1271: common denominator, i.e. the code which just copies some number of
1272: totally unaligned individual bytes. (See the calculation of
1273: chunk_size above. */
1274:
1275: if (chunk_size == 4)
1276: {
1277: output_asm_insn ("ld.l %2(%1),%?r31", xoperands);
1278: output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
1279: output_asm_insn ("st.l %?r31,8(%6)", xoperands);
1280: }
1281: else if (chunk_size == 2)
1282: {
1283: output_asm_insn ("ld.s %2(%1),%?r31", xoperands);
1284: output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
1285: output_asm_insn ("st.s %?r31,4(%6)", xoperands);
1286: }
1287: else /* chunk_size == 1 */
1288: {
1289: output_asm_insn ("ld.b %2(%1),%?r31", xoperands);
1290: output_asm_insn ("bla %5,%2,.Ls%3", xoperands);
1291: output_asm_insn ("st.b %?r31,2(%6)", xoperands);
1292: }
1293: output_asm_insn ("\n.Le%3:", xoperands); /* Here if count <= 0. */
1294:
1295: return "";
1296: }
1297:
1298: /* Output a delayed branch insn with the delay insn in its
1299: branch slot. The delayed branch insn template is in TEMPLATE,
1300: with operands OPERANDS. The insn in its delay slot is INSN.
1301:
1302: As a special case, since we know that all memory transfers are via
1303: ld/st insns, if we see a (MEM (SYMBOL_REF ...)) we divide the memory
1304: reference around the branch as
1305:
1306: orh ha%x,%?r0,%?r31
1307: b ...
1308: ld/st l%x(%?r31),...
1309:
1310: As another special case, we handle loading (SYMBOL_REF ...) and
1311: other large constants around branches as well:
1312:
1313: orh h%x,%?r0,%0
1314: b ...
1315: or l%x,%0,%1
1316:
1317: */
1318:
1319: char *
1320: output_delayed_branch (template, operands, insn)
1321: char *template;
1322: rtx *operands;
1323: rtx insn;
1324: {
1325: rtx src = XVECEXP (PATTERN (insn), 0, 1);
1326: rtx dest = XVECEXP (PATTERN (insn), 0, 0);
1327:
1328: /* See if we are doing some branch together with setting some register
1329: to some 32-bit value which does (or may) have some of the high-order
1330: 16 bits set. If so, we need to set the register in two stages. One
1331: stage must be done before the branch, and the other one can be done
1332: in the delay slot. */
1333:
1334: if ( (GET_CODE (src) == CONST_INT
1335: && ((unsigned) INTVAL (src) & (unsigned) 0xffff0000) != (unsigned) 0)
1336: || (GET_CODE (src) == SYMBOL_REF)
1337: || (GET_CODE (src) == LABEL_REF)
1338: || (GET_CODE (src) == CONST))
1339: {
1340: rtx xoperands[2];
1341: xoperands[0] = dest;
1342: xoperands[1] = src;
1343:
1344: CC_STATUS_PARTIAL_INIT;
1345: /* Output the `orh' insn. */
1346: output_asm_insn ("orh %H1,%?r0,%0", xoperands);
1347:
1348: /* Output the branch instruction next. */
1349: output_asm_insn (template, operands);
1350:
1351: /* Now output the `or' insn. */
1352: output_asm_insn ("or %L1,%0,%0", xoperands);
1353: }
1354: else if ((GET_CODE (src) == MEM
1355: && CONSTANT_ADDRESS_P (XEXP (src, 0)))
1356: || (GET_CODE (dest) == MEM
1357: && CONSTANT_ADDRESS_P (XEXP (dest, 0))))
1358: {
1359: rtx xoperands[2];
1360: char *split_template;
1361: xoperands[0] = dest;
1362: xoperands[1] = src;
1363:
1364: /* Output the `orh' insn. */
1365: if (GET_CODE (src) == MEM)
1366: {
1367: if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
1368: && (cc_prev_status.flags & CC_HI_R31_ADJ)
1369: && cc_prev_status.mdep == XEXP (operands[1], 0)))
1370: {
1371: CC_STATUS_INIT;
1372: output_asm_insn ("orh %h1,%?r0,%?r31", xoperands);
1373: }
1374: split_template = load_opcode (GET_MODE (dest),
1375: "%L1(%?r31),%0", dest);
1376: }
1377: else
1378: {
1379: if (! ((cc_prev_status.flags & CC_KNOW_HI_R31)
1380: && (cc_prev_status.flags & CC_HI_R31_ADJ)
1381: && cc_prev_status.mdep == XEXP (operands[0], 0)))
1382: {
1383: CC_STATUS_INIT;
1384: output_asm_insn ("orh %h0,%?r0,%?r31", xoperands);
1385: }
1386: split_template = store_opcode (GET_MODE (dest),
1387: "%r1,%L0(%?r31)", src);
1388: }
1389:
1390: /* Output the branch instruction next. */
1391: output_asm_insn (template, operands);
1392:
1393: /* Now output the load or store.
1394: No need to do a CC_STATUS_INIT, because we are branching anyway. */
1395: output_asm_insn (split_template, xoperands);
1396: }
1397: else
1398: {
1399: int insn_code_number;
1400: rtx pat = gen_rtx (SET, VOIDmode, dest, src);
1401: rtx delay_insn = gen_rtx (INSN, VOIDmode, 0, 0, 0, pat, -1, 0, 0);
1402: int i;
1403:
1404: /* Output the branch instruction first. */
1405: output_asm_insn (template, operands);
1406:
1407: /* Now recognize the insn which we put in its delay slot.
1408: We must do this after outputting the branch insn,
1409: since operands may just be a pointer to `recog_operand'. */
1410: INSN_CODE (delay_insn) = insn_code_number = recog (pat, delay_insn);
1411: if (insn_code_number == -1)
1412: abort ();
1413:
1414: for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1415: {
1416: if (GET_CODE (recog_operand[i]) == SUBREG)
1417: recog_operand[i] = alter_subreg (recog_operand[i]);
1418: }
1419:
1420: insn_extract (delay_insn);
1421: if (! constrain_operands (insn_code_number, 1))
1422: fatal_insn_not_found (delay_insn);
1423:
1424: template = insn_template[insn_code_number];
1425: if (template == 0)
1426: template = (*insn_outfun[insn_code_number]) (recog_operand, delay_insn);
1427: output_asm_insn (template, recog_operand);
1428: }
1429: CC_STATUS_INIT;
1430: return "";
1431: }
1432:
1433: /* Output a newly constructed insn DELAY_INSN. */
1434: char *
1435: output_delay_insn (delay_insn)
1436: rtx delay_insn;
1437: {
1438: char *template;
1439: int insn_code_number;
1440: int i;
1441:
1442: /* Now recognize the insn which we put in its delay slot.
1443: We must do this after outputting the branch insn,
1444: since operands may just be a pointer to `recog_operand'. */
1445: insn_code_number = recog_memoized (delay_insn);
1446: if (insn_code_number == -1)
1447: abort ();
1448:
1449: /* Extract the operands of this delay insn. */
1450: INSN_CODE (delay_insn) = insn_code_number;
1451: insn_extract (delay_insn);
1452:
1453: /* It is possible that this insn has not been properly scanned by final
1454: yet. If this insn's operands don't appear in the peephole's
1455: actual operands, then they won't be fixed up by final, so we
1456: make sure they get fixed up here. -- This is a kludge. */
1457: for (i = 0; i < insn_n_operands[insn_code_number]; i++)
1458: {
1459: if (GET_CODE (recog_operand[i]) == SUBREG)
1460: recog_operand[i] = alter_subreg (recog_operand[i]);
1461: }
1462:
1463: #ifdef REGISTER_CONSTRAINTS
1464: if (! constrain_operands (insn_code_number))
1465: abort ();
1466: #endif
1467:
1468: cc_prev_status = cc_status;
1469:
1470: /* Update `cc_status' for this instruction.
1471: The instruction's output routine may change it further.
1472: If the output routine for a jump insn needs to depend
1473: on the cc status, it should look at cc_prev_status. */
1474:
1475: NOTICE_UPDATE_CC (PATTERN (delay_insn), delay_insn);
1476:
1477: /* Now get the template for what this insn would
1478: have been, without the branch. */
1479:
1480: template = insn_template[insn_code_number];
1481: if (template == 0)
1482: template = (*insn_outfun[insn_code_number]) (recog_operand, delay_insn);
1483: output_asm_insn (template, recog_operand);
1484: return "";
1485: }
1486:
1487: /* Special routine to convert an SFmode value represented as a
1488: CONST_DOUBLE into its equivalent unsigned long bit pattern.
1489: We convert the value from a double precision floating-point
1490: value to single precision first, and thence to a bit-wise
1491: equivalent unsigned long value. This routine is used when
1492: generating an immediate move of an SFmode value directly
1493: into a general register because the svr4 assembler doesn't
1494: grok floating literals in instruction operand contexts. */
1495:
1496: unsigned long
1497: sfmode_constant_to_ulong (x)
1498: rtx x;
1499: {
1500: REAL_VALUE_TYPE d;
1501: union { float f; unsigned long i; } u2;
1502:
1503: if (GET_CODE (x) != CONST_DOUBLE || GET_MODE (x) != SFmode)
1504: abort ();
1505:
1506: #if TARGET_FLOAT_FORMAT != HOST_FLOAT_FORMAT
1507: error IEEE emulation needed
1508: #endif
1509: REAL_VALUE_FROM_CONST_DOUBLE (d, x);
1510: u2.f = d;
1511: return u2.i;
1512: }
1513:
1514: /* This function generates the assembly code for function entry.
1515: The macro FUNCTION_PROLOGUE in i860.h is defined to call this function.
1516:
1517: ASM_FILE is a stdio stream to output the code to.
1518: SIZE is an int: how many units of temporary storage to allocate.
1519:
1520: Refer to the array `regs_ever_live' to determine which registers
1521: to save; `regs_ever_live[I]' is nonzero if register number I
1522: is ever used in the function. This macro is responsible for
1523: knowing which registers should not be saved even if used.
1524:
1525: NOTE: `frame_lower_bytes' is the count of bytes which will lie
1526: between the new `fp' value and the new `sp' value after the
1527: prologue is done. `frame_upper_bytes' is the count of bytes
1528: that will lie between the new `fp' and the *old* `sp' value
1529: after the new `fp' is setup (in the prologue). The upper
1530: part of each frame always includes at least 2 words (8 bytes)
1531: to hold the saved frame pointer and the saved return address.
1532:
1533: The svr4 ABI for the i860 now requires that the values of the
1534: stack pointer and frame pointer registers be kept aligned to
1535: 16-byte boundaries at all times. We obey that restriction here.
1536:
1537: The svr4 ABI for the i860 is entirely vague when it comes to specifying
1538: exactly where the "preserved" registers should be saved. The native
1539: svr4 C compiler I now have doesn't help to clarify the requirements
1540: very much because it is plainly out-of-date and non-ABI-compliant
1541: (in at least one important way, i.e. how it generates function
1542: epilogues).
1543:
1544: The native svr4 C compiler saves the "preserved" registers (i.e.
1545: r4-r15 and f2-f7) in the lower part of a frame (i.e. at negative
1546: offsets from the frame pointer).
1547:
1548: Previous versions of GCC also saved the "preserved" registers in the
1549: "negative" part of the frame, but they saved them using positive
1550: offsets from the (adjusted) stack pointer (after it had been adjusted
1551: to allocate space for the new frame). That's just plain wrong
1552: because if the current function calls alloca(), the stack pointer
1553: will get moved, and it will be impossible to restore the registers
1554: properly again after that.
1555:
1556: Both compilers handled parameter registers (i.e. r16-r27 and f8-f15)
1557: by copying their values either into various "preserved" registers or
1558: into stack slots in the lower part of the current frame (as seemed
1559: appropriate, depending upon subsequent usage of these values).
1560:
1561: Here we want to save the preserved registers at some offset from the
1562: frame pointer register so as to avoid any possible problems arising
1563: from calls to alloca(). We can either save them at small positive
1564: offsets from the frame pointer, or at small negative offsets from
1565: the frame pointer. If we save them at small negative offsets from
1566: the frame pointer (i.e. in the lower part of the frame) then we
1567: must tell the rest of GCC (via STARTING_FRAME_OFFSET) exactly how
1568: many bytes of space we plan to use in the lower part of the frame
1569: for this purpose. Since other parts of the compiler reference the
1570: value of STARTING_FRAME_OFFSET long before final() calls this function,
1571: we would have to go ahead and assume the worst-case storage requirements
1572: for saving all of the "preserved" registers (and use that number, i.e.
1573: `80', to define STARTING_FRAME_OFFSET) if we wanted to save them in
1574: the lower part of the frame. That could potentially be very wasteful,
1575: and that wastefulness could really hamper people compiling for embedded
1576: i860 targets with very tight limits on stack space. Thus, we choose
1577: here to save the preserved registers in the upper part of the
1578: frame, so that we can decide at the very last minute how much (or how
1579: little) space we must allocate for this purpose.
1580:
1581: To satisfy the needs of the svr4 ABI "tdesc" scheme, preserved
1582: registers must always be saved so that the saved values of registers
1583: with higher numbers are at higher addresses. We obey that restriction
1584: here.
1585:
1586: There are two somewhat different ways that you can generate prologues
1587: here... i.e. pedantically ABI-compliant, and the "other" way. The
1588: "other" way is more consistent with what is currently generated by the
1589: "native" svr4 C compiler for the i860. That's important if you want
1590: to use the current (as of 8/91) incarnation of svr4 SDB for the i860.
1591: The SVR4 SDB for the i860 insists on having function prologues be
1592: non-ABI-compliant!
1593:
1594: To get fully ABI-compliant prologues, define I860_STRICT_ABI_PROLOGUES
1595: in the i860svr4.h file. (By default this is *not* defined).
1596:
1597: The differences between the ABI-compliant and non-ABI-compliant prologues
1598: are that (a) the ABI version seems to require the use of *signed*
1599: (rather than unsigned) adds and subtracts, and (b) the ordering of
1600: the various steps (e.g. saving preserved registers, saving the
1601: return address, setting up the new frame pointer value) is different.
1602:
1603: For strict ABI compliance, it seems to be the case that the very last
1604: thing that is supposed to happen in the prologue is getting the frame
1605: pointer set to its new value (but only after everything else has
1606: already been properly setup). We do that here, but only if the symbol
1607: I860_STRICT_ABI_PROLOGUES is defined.
1608: */
1609:
1610: #ifndef STACK_ALIGNMENT
1611: #define STACK_ALIGNMENT 16
1612: #endif
1613:
1614: extern char call_used_regs[];
1615: extern int leaf_function_p ();
1616:
1617: char *current_function_original_name;
1618:
1619: static int must_preserve_r1;
1620: static unsigned must_preserve_bytes;
1621:
1622: void
1623: function_prologue (asm_file, local_bytes)
1624: register FILE *asm_file;
1625: register unsigned local_bytes;
1626: {
1627: register unsigned frame_lower_bytes;
1628: register unsigned frame_upper_bytes;
1629: register unsigned total_fsize;
1630: register unsigned preserved_reg_bytes = 0;
1631: register unsigned i;
1632: register unsigned preserved_so_far = 0;
1633:
1634: must_preserve_r1 = (optimize < 2 || ! leaf_function_p ());
1635: must_preserve_bytes = 4 + (must_preserve_r1 ? 4 : 0);
1636:
1637: /* Count registers that need preserving. Ignore r0. It never needs
1638: preserving. */
1639:
1640: for (i = 1; i < FIRST_PSEUDO_REGISTER; i++)
1641: {
1642: if (regs_ever_live[i] && ! call_used_regs[i])
1643: preserved_reg_bytes += 4;
1644: }
1645:
1646: /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1647:
1648: frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1649:
1650: /* The upper part of each frame will contain the saved fp,
1651: the saved r1, and stack slots for all of the other "preserved"
1652: registers that we find we will need to save & restore. */
1653:
1654: frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes;
1655:
1656: /* Round-up the frame_upper_bytes so that it's a multiple of 16. */
1657:
1658: frame_upper_bytes
1659: = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1660:
1661: total_fsize = frame_upper_bytes + frame_lower_bytes;
1662:
1663: #ifndef I860_STRICT_ABI_PROLOGUES
1664:
1665: /* There are two kinds of function prologues.
1666: You use the "small" version if the total frame size is
1667: small enough so that it can fit into an immediate 16-bit
1668: value in one instruction. Otherwise, you use the "large"
1669: version of the function prologue. */
1670:
1671: if (total_fsize > 0x7fff)
1672: {
1673: /* Adjust the stack pointer. The ABI sez to do this using `adds',
1674: but the native C compiler on svr4 uses `addu'. */
1675:
1676: fprintf (asm_file, "\taddu -%d,%ssp,%ssp\n",
1677: frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
1678:
1679: /* Save the old frame pointer. */
1680:
1681: fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n",
1682: i860_reg_prefix, i860_reg_prefix);
1683:
1684: /* Setup the new frame pointer. The ABI sez to do this after
1685: preserving registers (using adds), but that's not what the
1686: native C compiler on svr4 does. */
1687:
1688: fprintf (asm_file, "\taddu 0,%ssp,%sfp\n",
1689: i860_reg_prefix, i860_reg_prefix);
1690:
1691: /* Get the value of frame_lower_bytes into r31. */
1692:
1693: fprintf (asm_file, "\torh %d,%sr0,%sr31\n",
1694: frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix);
1695: fprintf (asm_file, "\tor %d,%sr31,%sr31\n",
1696: frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix);
1697:
1698: /* Now re-adjust the stack pointer using the value in r31.
1699: The ABI sez to do this with `subs' but SDB may prefer `subu'. */
1700:
1701: fprintf (asm_file, "\tsubu %ssp,%sr31,%ssp\n",
1702: i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
1703:
1704: /* Preserve registers. The ABI sez to do this before setting
1705: up the new frame pointer, but that's not what the native
1706: C compiler on svr4 does. */
1707:
1708: for (i = 1; i < 32; i++)
1709: if (regs_ever_live[i] && ! call_used_regs[i])
1710: fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n",
1711: i860_reg_prefix, reg_names[i],
1712: must_preserve_bytes + (4 * preserved_so_far++),
1713: i860_reg_prefix);
1714:
1715: for (i = 32; i < 64; i++)
1716: if (regs_ever_live[i] && ! call_used_regs[i])
1717: fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n",
1718: i860_reg_prefix, reg_names[i],
1719: must_preserve_bytes + (4 * preserved_so_far++),
1720: i860_reg_prefix);
1721:
1722: /* Save the return address. */
1723:
1724: if (must_preserve_r1)
1725: fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n",
1726: i860_reg_prefix, i860_reg_prefix);
1727: }
1728: else
1729: {
1730: /* Adjust the stack pointer. The ABI sez to do this using `adds',
1731: but the native C compiler on svr4 uses `addu'. */
1732:
1733: fprintf (asm_file, "\taddu -%d,%ssp,%ssp\n",
1734: total_fsize, i860_reg_prefix, i860_reg_prefix);
1735:
1736: /* Save the old frame pointer. */
1737:
1738: fprintf (asm_file, "\tst.l %sfp,%d(%ssp)\n",
1739: i860_reg_prefix, frame_lower_bytes, i860_reg_prefix);
1740:
1741: /* Setup the new frame pointer. The ABI sez to do this after
1742: preserving registers and after saving the return address,
1743: (and its saz to do this using adds), but that's not what the
1744: native C compiler on svr4 does. */
1745:
1746: fprintf (asm_file, "\taddu %d,%ssp,%sfp\n",
1747: frame_lower_bytes, i860_reg_prefix, i860_reg_prefix);
1748:
1749: /* Preserve registers. The ABI sez to do this before setting
1750: up the new frame pointer, but that's not what the native
1751: compiler on svr4 does. */
1752:
1753: for (i = 1; i < 32; i++)
1754: if (regs_ever_live[i] && ! call_used_regs[i])
1755: fprintf (asm_file, "\tst.l %s%s,%d(%sfp)\n",
1756: i860_reg_prefix, reg_names[i],
1757: must_preserve_bytes + (4 * preserved_so_far++),
1758: i860_reg_prefix);
1759:
1760: for (i = 32; i < 64; i++)
1761: if (regs_ever_live[i] && ! call_used_regs[i])
1762: fprintf (asm_file, "\tfst.l %s%s,%d(%sfp)\n",
1763: i860_reg_prefix, reg_names[i],
1764: must_preserve_bytes + (4 * preserved_so_far++),
1765: i860_reg_prefix);
1766:
1767: /* Save the return address. The ABI sez to do this earlier,
1768: and also via an offset from %sp, but the native C compiler
1769: on svr4 does it later (i.e. now) and uses an offset from
1770: %fp. */
1771:
1772: if (must_preserve_r1)
1773: fprintf (asm_file, "\tst.l %sr1,4(%sfp)\n",
1774: i860_reg_prefix, i860_reg_prefix);
1775: }
1776:
1777: #else /* defined(I860_STRICT_ABI_PROLOGUES) */
1778:
1779: /* There are two kinds of function prologues.
1780: You use the "small" version if the total frame size is
1781: small enough so that it can fit into an immediate 16-bit
1782: value in one instruction. Otherwise, you use the "large"
1783: version of the function prologue. */
1784:
1785: if (total_fsize > 0x7fff)
1786: {
1787: /* Adjust the stack pointer (thereby allocating a new frame). */
1788:
1789: fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n",
1790: frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
1791:
1792: /* Save the caller's frame pointer. */
1793:
1794: fprintf (asm_file, "\tst.l %sfp,0(%ssp)\n",
1795: i860_reg_prefix, i860_reg_prefix);
1796:
1797: /* Save return address. */
1798:
1799: if (must_preserve_r1)
1800: fprintf (asm_file, "\tst.l %sr1,4(%ssp)\n",
1801: i860_reg_prefix, i860_reg_prefix);
1802:
1803: /* Get the value of frame_lower_bytes into r31 for later use. */
1804:
1805: fprintf (asm_file, "\torh %d,%sr0,%sr31\n",
1806: frame_lower_bytes >> 16, i860_reg_prefix, i860_reg_prefix);
1807: fprintf (asm_file, "\tor %d,%sr31,%sr31\n",
1808: frame_lower_bytes & 0xffff, i860_reg_prefix, i860_reg_prefix);
1809:
1810: /* Now re-adjust the stack pointer using the value in r31. */
1811:
1812: fprintf (asm_file, "\tsubs %ssp,%sr31,%ssp\n",
1813: i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
1814:
1815: /* Pre-compute value to be used as the new frame pointer. */
1816:
1817: fprintf (asm_file, "\tadds %ssp,%sr31,%sr31\n",
1818: i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
1819:
1820: /* Preserve registers. */
1821:
1822: for (i = 1; i < 32; i++)
1823: if (regs_ever_live[i] && ! call_used_regs[i])
1824: fprintf (asm_file, "\tst.l %s%s,%d(%sr31)\n",
1825: i860_reg_prefix, reg_names[i],
1826: must_preserve_bytes + (4 * preserved_so_far++),
1827: i860_reg_prefix);
1828:
1829: for (i = 32; i < 64; i++)
1830: if (regs_ever_live[i] && ! call_used_regs[i])
1831: fprintf (asm_file, "\tfst.l %s%s,%d(%sr31)\n",
1832: i860_reg_prefix, reg_names[i],
1833: must_preserve_bytes + (4 * preserved_so_far++),
1834: i860_reg_prefix);
1835:
1836: /* Actually set the new value of the frame pointer. */
1837:
1838: fprintf (asm_file, "\tmov %sr31,%sfp\n",
1839: i860_reg_prefix, i860_reg_prefix);
1840: }
1841: else
1842: {
1843: /* Adjust the stack pointer. */
1844:
1845: fprintf (asm_file, "\tadds -%d,%ssp,%ssp\n",
1846: total_fsize, i860_reg_prefix, i860_reg_prefix);
1847:
1848: /* Save the caller's frame pointer. */
1849:
1850: fprintf (asm_file, "\tst.l %sfp,%d(%ssp)\n",
1851: i860_reg_prefix, frame_lower_bytes, i860_reg_prefix);
1852:
1853: /* Save the return address. */
1854:
1855: if (must_preserve_r1)
1856: fprintf (asm_file, "\tst.l %sr1,%d(%ssp)\n",
1857: i860_reg_prefix, frame_lower_bytes + 4, i860_reg_prefix);
1858:
1859: /* Preserve registers. */
1860:
1861: for (i = 1; i < 32; i++)
1862: if (regs_ever_live[i] && ! call_used_regs[i])
1863: fprintf (asm_file, "\tst.l %s%s,%d(%ssp)\n",
1864: i860_reg_prefix, reg_names[i],
1865: frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++),
1866: i860_reg_prefix);
1867:
1868: for (i = 32; i < 64; i++)
1869: if (regs_ever_live[i] && ! call_used_regs[i])
1870: fprintf (asm_file, "\tfst.l %s%s,%d(%ssp)\n",
1871: i860_reg_prefix, reg_names[i],
1872: frame_lower_bytes + must_preserve_bytes + (4 * preserved_so_far++),
1873: i860_reg_prefix);
1874:
1875: /* Setup the new frame pointer. */
1876:
1877: fprintf (asm_file, "\tadds %d,%ssp,%sfp\n",
1878: frame_lower_bytes, i860_reg_prefix, i860_reg_prefix);
1879: }
1880: #endif /* defined(I860_STRICT_ABI_PROLOGUES) */
1881:
1882: #ifdef ASM_OUTPUT_PROLOGUE_SUFFIX
1883: ASM_OUTPUT_PROLOGUE_SUFFIX (asm_file);
1884: #endif /* defined(ASM_OUTPUT_PROLOGUE_SUFFIX) */
1885: }
1886:
1887: /* This function generates the assembly code for function exit.
1888: The macro FUNCTION_EPILOGUE in i860.h is defined to call this function.
1889:
1890: ASM_FILE is a stdio stream to output the code to.
1891: SIZE is an int: how many units of temporary storage to allocate.
1892:
1893: The function epilogue should not depend on the current stack pointer!
1894: It should use the frame pointer only. This is mandatory because
1895: of alloca; we also take advantage of it to omit stack adjustments
1896: before returning.
1897:
1898: Note that when we go to restore the preserved register values we must
1899: not try to address their slots by using offsets from the stack pointer.
1900: That's because the stack pointer may have been moved during the function
1901: execution due to a call to alloca(). Rather, we must restore all
1902: preserved registers via offsets from the frame pointer value.
1903:
1904: Note also that when the current frame is being "popped" (by adjusting
1905: the value of the stack pointer) on function exit, we must (for the
1906: sake of alloca) set the new value of the stack pointer based upon
1907: the current value of the frame pointer. We can't just add what we
1908: believe to be the (static) frame size to the stack pointer because
1909: if we did that, and alloca() had been called during this function,
1910: we would end up returning *without* having fully deallocated all of
1911: the space grabbed by alloca. If that happened, and a function
1912: containing one or more alloca() calls was called over and over again,
1913: then the stack would grow without limit!
1914:
1915: Finally note that the epilogues generated here are completely ABI
1916: compliant. They go out of their way to insure that the value in
1917: the frame pointer register is never less than the value in the stack
1918: pointer register. It's not clear why this relationship needs to be
1919: maintained at all times, but maintaining it only costs one extra
1920: instruction, so what the hell.
1921: */
1922:
1923: /* This corresponds to a version 4 TDESC structure. Lower numbered
1924: versions successively omit the last word of the structure. We
1925: don't try to handle version 5 here. */
1926:
1927: typedef struct TDESC_flags {
1928: int version:4;
1929: int reg_packing:1;
1930: int callable_block:1;
1931: int reserved:4;
1932: int fregs:6; /* fp regs 2-7 */
1933: int iregs:16; /* regs 0-15 */
1934: } TDESC_flags;
1935:
1936: typedef struct TDESC {
1937: TDESC_flags flags;
1938: int integer_reg_offset; /* same as must_preserve_bytes */
1939: int floating_point_reg_offset;
1940: unsigned int positive_frame_size; /* same as frame_upper_bytes */
1941: unsigned int negative_frame_size; /* same as frame_lower_bytes */
1942: } TDESC;
1943:
1944: void
1945: function_epilogue (asm_file, local_bytes)
1946: register FILE *asm_file;
1947: register unsigned local_bytes;
1948: {
1949: register unsigned frame_upper_bytes;
1950: register unsigned frame_lower_bytes;
1951: register unsigned preserved_reg_bytes = 0;
1952: register unsigned i;
1953: register unsigned restored_so_far = 0;
1954: register unsigned int_restored;
1955: register unsigned mask;
1956: unsigned intflags=0;
1957: register TDESC_flags *flags = (TDESC_flags *) &intflags;
1958:
1959: flags->version = 4;
1960: flags->reg_packing = 1;
1961: flags->iregs = 8; /* old fp always gets saved */
1962:
1963: /* Round-up the frame_lower_bytes so that it's a multiple of 16. */
1964:
1965: frame_lower_bytes = (local_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1966:
1967: /* Count the number of registers that were preserved in the prologue.
1968: Ignore r0. It is never preserved. */
1969:
1970: for (i = 1; i < FIRST_PSEUDO_REGISTER; i++)
1971: {
1972: if (regs_ever_live[i] && ! call_used_regs[i])
1973: preserved_reg_bytes += 4;
1974: }
1975:
1976: /* The upper part of each frame will contain only saved fp,
1977: the saved r1, and stack slots for all of the other "preserved"
1978: registers that we find we will need to save & restore. */
1979:
1980: frame_upper_bytes = must_preserve_bytes + preserved_reg_bytes;
1981:
1982: /* Round-up frame_upper_bytes so that t is a multiple of 16. */
1983:
1984: frame_upper_bytes
1985: = (frame_upper_bytes + STACK_ALIGNMENT - 1) & -STACK_ALIGNMENT;
1986:
1987: /* Restore all of the "preserved" registers that need restoring. */
1988:
1989: mask = 2;
1990:
1991: for (i = 1; i < 32; i++, mask<<=1)
1992: if (regs_ever_live[i] && ! call_used_regs[i]) {
1993: fprintf (asm_file, "\tld.l %d(%sfp),%s%s\n",
1994: must_preserve_bytes + (4 * restored_so_far++),
1995: i860_reg_prefix, i860_reg_prefix, reg_names[i]);
1996: if (i > 3 && i < 16)
1997: flags->iregs |= mask;
1998: }
1999:
2000: int_restored = restored_so_far;
2001: mask = 1;
2002:
2003: for (i = 32; i < 64; i++) {
2004: if (regs_ever_live[i] && ! call_used_regs[i]) {
2005: fprintf (asm_file, "\tfld.l %d(%sfp),%s%s\n",
2006: must_preserve_bytes + (4 * restored_so_far++),
2007: i860_reg_prefix, i860_reg_prefix, reg_names[i]);
2008: if (i > 33 & i < 40)
2009: flags->fregs |= mask;
2010: }
2011: if (i > 33 && i < 40)
2012: mask<<=1;
2013: }
2014:
2015: /* Get the value we plan to use to restore the stack pointer into r31. */
2016:
2017: fprintf (asm_file, "\tadds %d,%sfp,%sr31\n",
2018: frame_upper_bytes, i860_reg_prefix, i860_reg_prefix);
2019:
2020: /* Restore the return address and the old frame pointer. */
2021:
2022: if (must_preserve_r1) {
2023: fprintf (asm_file, "\tld.l 4(%sfp),%sr1\n",
2024: i860_reg_prefix, i860_reg_prefix);
2025: flags->iregs |= 2;
2026: }
2027:
2028: fprintf (asm_file, "\tld.l 0(%sfp),%sfp\n",
2029: i860_reg_prefix, i860_reg_prefix);
2030:
2031: /* Return and restore the old stack pointer value. */
2032:
2033: fprintf (asm_file, "\tbri %sr1\n\tmov %sr31,%ssp\n",
2034: i860_reg_prefix, i860_reg_prefix, i860_reg_prefix);
2035:
2036: #ifdef OUTPUT_TDESC /* Output an ABI-compliant TDESC entry */
2037: if (! frame_lower_bytes) {
2038: flags->version--;
2039: if (! frame_upper_bytes) {
2040: flags->version--;
2041: if (restored_so_far == int_restored) /* No FP saves */
2042: flags->version--;
2043: }
2044: }
2045: assemble_name(asm_file,current_function_original_name);
2046: fputs(".TDESC:\n", asm_file);
2047: fprintf(asm_file, "%s 0x%0x\n", ASM_LONG, intflags);
2048: fprintf(asm_file, "%s %d\n", ASM_LONG,
2049: int_restored ? must_preserve_bytes : 0);
2050: if (flags->version > 1) {
2051: fprintf(asm_file, "%s %d\n", ASM_LONG,
2052: (restored_so_far == int_restored) ? 0 : must_preserve_bytes +
2053: (4 * int_restored));
2054: if (flags->version > 2) {
2055: fprintf(asm_file, "%s %d\n", ASM_LONG, frame_upper_bytes);
2056: if (flags->version > 3)
2057: fprintf(asm_file, "%s %d\n", ASM_LONG, frame_lower_bytes);
2058: }
2059: }
2060: tdesc_section();
2061: fprintf(asm_file, "%s ", ASM_LONG);
2062: assemble_name(asm_file, current_function_original_name);
2063: fprintf(asm_file, "\n%s ", ASM_LONG);
2064: assemble_name(asm_file, current_function_original_name);
2065: fputs(".TDESC\n", asm_file);
2066: text_section();
2067: #endif
2068: }
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