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1.1 ! root 1: /* Definitions of target machine for GNU compiler, for Intel 80960 ! 2: Copyright (C) 1992 Free Software Foundation, Inc. ! 3: Contributed by Steven McGeady, Intel Corp. ! 4: Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson ! 5: Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support. ! 6: ! 7: This file is part of GNU CC. ! 8: ! 9: GNU CC is free software; you can redistribute it and/or modify ! 10: it under the terms of the GNU General Public License as published by ! 11: the Free Software Foundation; either version 2, or (at your option) ! 12: any later version. ! 13: ! 14: GNU CC is distributed in the hope that it will be useful, ! 15: but WITHOUT ANY WARRANTY; without even the implied warranty of ! 16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 17: GNU General Public License for more details. ! 18: ! 19: You should have received a copy of the GNU General Public License ! 20: along with GNU CC; see the file COPYING. If not, write to ! 21: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ ! 22: ! 23: /* Note that some other tm.h files may include this one and then override ! 24: many of the definitions that relate to assembler syntax. */ ! 25: ! 26: /* Names to predefine in the preprocessor for this target machine. */ ! 27: #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960" ! 28: ! 29: /* Name to predefine in the preprocessor for processor variations. */ ! 30: #define CPP_SPEC "%{mic*:-D__i960\ ! 31: %{mka:-D__i960KA}%{mkb:-D__i960KB}%{mkc:-D__i960KC}\ ! 32: %{msa:-D__i960SA}%{msb:-D__i960SB}%{msc:-D__i960SC}\ ! 33: %{mmc:-D__i960MC}\ ! 34: %{mca:-D__i960CA}%{mcb:-D__i960CB}%{mcc:-D__i960CC}\ ! 35: %{mcf:-D__i960CF}}\ ! 36: %{mka:-D__i960KA__ -D__i960_KA__}\ ! 37: %{mkb:-D__i960KB__ -D__i960_KB__}\ ! 38: %{mkc:-D__i960KC__ -D__i960_KC__}\ ! 39: %{msa:-D__i960SA__ -D__i960_SA__}\ ! 40: %{msb:-D__i960SB__ -D__i960_SB__}\ ! 41: %{msc:-D__i960SC__ -D__i960_SC__}\ ! 42: %{mmc:-D__i960MC__ -D__i960_MC__}\ ! 43: %{mca:-D__i960CA__ -D__i960_CA__}\ ! 44: %{mcb:-D__i960CB__ -D__i960_CB__}\ ! 45: %{mcc:-D__i960CC__ -D__i960_CC__}\ ! 46: %{mcf:-D__i960CF__ -D__i960_CF__}\ ! 47: %{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\ ! 48: %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}}}}" ! 49: ! 50: /* -mic* options make characters signed by default. */ ! 51: #define SIGNED_CHAR_SPEC \ ! 52: (DEFAULT_SIGNED_CHAR ? "%{funsigned-char:-D__CHAR_UNSIGNED__}" \ ! 53: : "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}") ! 54: ! 55: /* Specs for the compiler, to handle processor variations. */ ! 56: #define CC1_SPEC \ ! 57: "%{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\ ! 58: %{!mcc:%{!mcf:-mkb}}}}}}}}}}}\ ! 59: %{mbout:%{g*:-gstabs}}\ ! 60: %{mcoff:%{g*:-gcoff}}\ ! 61: %{!mbout:%{!mcoff:%{g*:-gstabs}}}" ! 62: ! 63: /* Specs for the assembler, to handle processor variations. ! 64: For compatibility with Intel's gnu960 tool chain, pass -A options to ! 65: the assembler. */ ! 66: #define ASM_SPEC \ ! 67: "%{mka:-AKA}%{mkb:-AKB}%{mkc:-AKC}%{msa:-ASA}%{msb:-ASB}\ ! 68: %{msc:-ASC}%{mmc:-AMC}%{mca:-ACA}%{mcb:-ACB}%{mcc:-ACC}%{mcf:-ACF}\ ! 69: %{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\ ! 70: %{!mcc:%{!mcf:-AKB}}}}}}}}}}}" ! 71: ! 72: /* Specs for the linker, to handle processor variations. ! 73: For compatibility with Intel's gnu960 tool chain, pass -F and -A options ! 74: to the linker. */ ! 75: #define LINK_SPEC \ ! 76: "%{mka:-AKA}%{mkb:-AKB}%{mkc:-AKC}%{msa:-ASA}%{msb:-ASB}\ ! 77: %{msc:-ASC}%{mmc:-AMC}%{mca:-ACA}%{mcb:-ACB}%{mcc:-ACC}%{mcf:-ACF}\ ! 78: %{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\ ! 79: %{!mcc:%{!mcf:-AKB}}}}}}}}}}}\ ! 80: %{mbout:-Fbout}%{mcoff:-Fcoff}" ! 81: ! 82: /* Specs for the libraries to link with, to handle processor variations. ! 83: Compatible with Intel's gnu960 tool chain. */ ! 84: #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\ ! 85: %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}" ! 86: ! 87: /* These compiler options take an argument. */ ! 88: #define WORD_SWITCH_TAKES_ARG(STR) \ ! 89: (!strcmp (STR, "Tdata") || !strcmp (STR, "include") \ ! 90: || !strcmp (STR, "imacros") || !strcmp (STR, "Ttext")) ! 91: ! 92: /* Omit frame pointer at -O2. Inline functions at -O3. */ ! 93: #define OPTIMIZATION_OPTIONS(LEVEL) \ ! 94: { \ ! 95: if ((LEVEL) >= 2) \ ! 96: { \ ! 97: flag_omit_frame_pointer = 1; \ ! 98: target_flags |= TARGET_FLAG_LEAFPROC; \ ! 99: target_flags |= TARGET_FLAG_TAILCALL; \ ! 100: } \ ! 101: if ((LEVEL) >= 3) \ ! 102: flag_inline_functions = 1; \ ! 103: } ! 104: ! 105: /* Print subsidiary information on the compiler version in use. */ ! 106: #define TARGET_VERSION fprintf (stderr," (intel 80960)"); ! 107: ! 108: /* Generate DBX debugging information. */ ! 109: #define DBX_DEBUGGING_INFO ! 110: ! 111: /* Generate SDB style debugging information. */ ! 112: #define SDB_DEBUGGING_INFO ! 113: ! 114: /* Generate DBX_DEBUGGING_INFO by default. */ ! 115: #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG ! 116: ! 117: /* Redefine this to print in hex like iC960. */ ! 118: #define PUT_SDB_TYPE(A) fprintf (asm_out_file, "\t.type\t0x%x;", A) ! 119: ! 120: /* Run-time compilation parameters selecting different hardware subsets. */ ! 121: ! 122: /* 960 architecture with floating-point. */ ! 123: #define TARGET_FLAG_NUMERICS 0x01 ! 124: #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS) ! 125: ! 126: /* 960 architecture with memory management. */ ! 127: /* ??? Not used currently. */ ! 128: #define TARGET_FLAG_PROTECTED 0x02 ! 129: #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED) ! 130: ! 131: /* The following three are mainly used to provide a little sanity checking ! 132: against the -mARCH flags given. */ ! 133: ! 134: /* Nonzero if we should generate code for the KA and similar processors. ! 135: No FPU, no microcode instructions. */ ! 136: #define TARGET_FLAG_K_SERIES 0x04 ! 137: #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES) ! 138: ! 139: /* Nonzero if we should generate code for the MC processor. ! 140: Not really different from KB for our purposes. */ ! 141: #define TARGET_FLAG_MC 0x08 ! 142: #define TARGET_MC (target_flags & TARGET_FLAG_MC) ! 143: ! 144: /* Nonzero if we should generate code for the CA processor. ! 145: Enables different optimization strategies. */ ! 146: #define TARGET_FLAG_C_SERIES 0x10 ! 147: #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES) ! 148: ! 149: /* Nonzero if we should generate leaf-procedures when we find them. ! 150: You may not want to do this because leaf-proc entries are ! 151: slower when not entered via BAL - this would be true when ! 152: a linker not supporting the optimization is used. */ ! 153: #define TARGET_FLAG_LEAFPROC 0x20 ! 154: #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC) ! 155: ! 156: /* Nonzero if we should perform tail-call optimizations when we find them. ! 157: You may not want to do this because the detection of cases where ! 158: this is not valid is not totally complete. */ ! 159: #define TARGET_FLAG_TAILCALL 0x40 ! 160: #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL) ! 161: ! 162: /* Nonzero if use of a complex addressing mode is a win on this implementation. ! 163: Complex addressing modes are probably not worthwhile on the K-series, ! 164: but they definitely are on the C-series. */ ! 165: #define TARGET_FLAG_COMPLEX_ADDR 0x80 ! 166: #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR) ! 167: ! 168: /* Align code to 8 byte boundaries for faster fetching. */ ! 169: #define TARGET_FLAG_CODE_ALIGN 0x100 ! 170: #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN) ! 171: ! 172: /* Append branch prediction suffixes to branch opcodes. */ ! 173: /* ??? Not used currently. */ ! 174: #define TARGET_FLAG_BRANCH_PREDICT 0x200 ! 175: #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT) ! 176: ! 177: /* Forces prototype and return promotions. */ ! 178: /* ??? This does not work. */ ! 179: #define TARGET_FLAG_CLEAN_LINKAGE 0x400 ! 180: #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE) ! 181: ! 182: /* For compatibility with iC960 v3.0. */ ! 183: #define TARGET_FLAG_IC_COMPAT3_0 0x800 ! 184: #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0) ! 185: ! 186: /* For compatibility with iC960 v2.0. */ ! 187: #define TARGET_FLAG_IC_COMPAT2_0 0x1000 ! 188: #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0) ! 189: ! 190: /* If no unaligned accesses are to be permitted. */ ! 191: #define TARGET_FLAG_STRICT_ALIGN 0x2000 ! 192: #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN) ! 193: ! 194: /* For compatibility with iC960 assembler. */ ! 195: #define TARGET_FLAG_ASM_COMPAT 0x4000 ! 196: #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT) ! 197: ! 198: /* For compatibility with the gcc960 v1.2 compiler. Use the old structure ! 199: alignement rules. Also, turns on STRICT_ALIGNMENT. */ ! 200: #define TARGET_FLAG_OLD_ALIGN 0x8000 ! 201: #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN) ! 202: ! 203: extern int target_flags; ! 204: ! 205: /* Macro to define tables used to set the flags. ! 206: This is a list in braces of pairs in braces, ! 207: each pair being { "NAME", VALUE } ! 208: where VALUE is the bits to set or minus the bits to clear. ! 209: An empty string NAME is used to identify the default VALUE. */ ! 210: ! 211: /* ??? Not all ten of these architecture variations actually exist, but I ! 212: am not sure which are real and which aren't. */ ! 213: ! 214: #define TARGET_SWITCHES \ ! 215: { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\ ! 216: {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \ ! 217: TARGET_FLAG_COMPLEX_ADDR)},\ ! 218: {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ ! 219: TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\ ! 220: {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\ ! 221: {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \ ! 222: TARGET_FLAG_COMPLEX_ADDR)},\ ! 223: {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ ! 224: TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\ ! 225: {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ ! 226: TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\ ! 227: {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\ ! 228: TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\ ! 229: {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\ ! 230: TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\ ! 231: {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\ ! 232: TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\ ! 233: TARGET_FLAG_CODE_ALIGN)}, \ ! 234: {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\ ! 235: TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\ ! 236: {"numerics", (TARGET_FLAG_NUMERICS)}, \ ! 237: {"soft-float", -(TARGET_FLAG_NUMERICS)}, \ ! 238: {"leaf-procedures", TARGET_FLAG_LEAFPROC}, \ ! 239: {"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)}, \ ! 240: {"tail-call",TARGET_FLAG_TAILCALL}, \ ! 241: {"no-tail-call",-(TARGET_FLAG_TAILCALL)}, \ ! 242: {"complex-addr",TARGET_FLAG_COMPLEX_ADDR}, \ ! 243: {"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)}, \ ! 244: {"code-align",TARGET_FLAG_CODE_ALIGN}, \ ! 245: {"no-code-align",-(TARGET_FLAG_CODE_ALIGN)}, \ ! 246: {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)}, \ ! 247: {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)}, \ ! 248: {"ic-compat", TARGET_FLAG_IC_COMPAT2_0}, \ ! 249: {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0}, \ ! 250: {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0}, \ ! 251: {"asm-compat",TARGET_FLAG_ASM_COMPAT}, \ ! 252: {"intel-asm",TARGET_FLAG_ASM_COMPAT}, \ ! 253: {"strict-align", TARGET_FLAG_STRICT_ALIGN}, \ ! 254: {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)}, \ ! 255: {"old-align", TARGET_FLAG_OLD_ALIGN}, \ ! 256: {"no-old-align", -(TARGET_FLAG_OLD_ALIGN)}, \ ! 257: { "", TARGET_DEFAULT}} ! 258: ! 259: /* Override conflicting target switch options. ! 260: Doesn't actually detect if more than one -mARCH option is given, but ! 261: does handle the case of two blatantly conflicting -mARCH options. */ ! 262: #define OVERRIDE_OPTIONS \ ! 263: { \ ! 264: if (TARGET_K_SERIES && TARGET_C_SERIES) \ ! 265: { \ ! 266: warning ("conflicting architectures defined - using C series", 0); \ ! 267: target_flags &= ~TARGET_FLAG_K_SERIES; \ ! 268: } \ ! 269: if (TARGET_K_SERIES && TARGET_MC) \ ! 270: { \ ! 271: warning ("conflicting architectures defined - using K series", 0); \ ! 272: target_flags &= ~TARGET_FLAG_MC; \ ! 273: } \ ! 274: if (TARGET_C_SERIES && TARGET_MC) \ ! 275: { \ ! 276: warning ("conflicting architectures defined - using C series", 0);\ ! 277: target_flags &= ~TARGET_FLAG_MC; \ ! 278: } \ ! 279: if (TARGET_IC_COMPAT3_0) \ ! 280: { \ ! 281: flag_short_enums = 1; \ ! 282: flag_signed_char = 1; \ ! 283: target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \ ! 284: if (TARGET_IC_COMPAT2_0) \ ! 285: { \ ! 286: warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \ ! 287: target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \ ! 288: } \ ! 289: } \ ! 290: if (TARGET_IC_COMPAT2_0) \ ! 291: { \ ! 292: flag_signed_char = 1; \ ! 293: target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \ ! 294: } \ ! 295: /* ??? Function inlining is not supported, because the i960 \ ! 296: calling convention requires the caller to manage the arg \ ! 297: pointer in a wierd fashion. This is ordinarily done by \ ! 298: expand_call, but this is never called when inlining \ ! 299: functions, and no replacement for it exists. */ \ ! 300: flag_no_inline = 1; \ ! 301: i960_initialize (); \ ! 302: } ! 303: ! 304: /* Don't enable anything by default. The user is expected to supply a -mARCH ! 305: option. If none is given, then -mkb is added by CC1_SPEC. */ ! 306: #define TARGET_DEFAULT 0 ! 307: ! 308: /* Target machine storage layout. */ ! 309: ! 310: /* Define this if most significant bit is lowest numbered ! 311: in instructions that operate on numbered bit-fields. */ ! 312: #define BITS_BIG_ENDIAN 0 ! 313: ! 314: /* Define this if most significant byte of a word is the lowest numbered. ! 315: The i960 case be either big endian or little endian. We only support ! 316: little endian, which is the most common. */ ! 317: #define BYTES_BIG_ENDIAN 0 ! 318: ! 319: /* Define this if most significant word of a multiword number is lowest ! 320: numbered. */ ! 321: #define WORDS_BIG_ENDIAN 0 ! 322: ! 323: /* Number of bits in an addressible storage unit. */ ! 324: #define BITS_PER_UNIT 8 ! 325: ! 326: /* Bitfields cannot cross word boundaries. */ ! 327: #define BITFIELD_NBYTES_LIMITED 1 ! 328: ! 329: /* Width in bits of a "word", which is the contents of a machine register. ! 330: Note that this is not necessarily the width of data type `int'; ! 331: if using 16-bit ints on a 68000, this would still be 32. ! 332: But on a machine with 16-bit registers, this would be 16. */ ! 333: #define BITS_PER_WORD 32 ! 334: ! 335: /* Width of a word, in units (bytes). */ ! 336: #define UNITS_PER_WORD 4 ! 337: ! 338: /* Width in bits of a pointer. See also the macro `Pmode' defined below. */ ! 339: #define POINTER_SIZE 32 ! 340: ! 341: /* Width in bits of a long double. Identical to double for now. */ ! 342: #define LONG_DOUBLE_TYPE_SIZE 64 ! 343: ! 344: /* Allocation boundary (in *bits*) for storing pointers in memory. */ ! 345: #define POINTER_BOUNDARY 32 ! 346: ! 347: /* Allocation boundary (in *bits*) for storing arguments in argument list. */ ! 348: #define PARM_BOUNDARY 32 ! 349: ! 350: /* Boundary (in *bits*) on which stack pointer should be aligned. */ ! 351: #define STACK_BOUNDARY 128 ! 352: ! 353: /* Allocation boundary (in *bits*) for the code of a function. */ ! 354: #define FUNCTION_BOUNDARY 128 ! 355: ! 356: /* Alignment of field after `int : 0' in a structure. */ ! 357: #define EMPTY_FIELD_BOUNDARY 32 ! 358: ! 359: /* This makes zero-length anonymous fields lay the next field ! 360: at a word boundary. It also makes the whole struct have ! 361: at least word alignment if there are any bitfields at all. */ ! 362: #define PCC_BITFIELD_TYPE_MATTERS 1 ! 363: ! 364: /* Every structure's size must be a multiple of this. */ ! 365: #define STRUCTURE_SIZE_BOUNDARY 8 ! 366: ! 367: /* No data type wants to be aligned rounder than this. ! 368: Extended precision floats gets 4-word alignment. */ ! 369: #define BIGGEST_ALIGNMENT 128 ! 370: ! 371: /* Define this if move instructions will actually fail to work ! 372: when given unaligned data. ! 373: 80960 will work even with unaligned data, but it is slow. */ ! 374: #define STRICT_ALIGNMENT TARGET_OLD_ALIGN ! 375: ! 376: /* Specify alignment for string literals (which might be higher than the ! 377: base type's minimnal alignment requirement. This allows strings to be ! 378: aligned on word boundaries, and optimizes calls to the str* and mem* ! 379: library functions. */ ! 380: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ ! 381: (i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \ ! 382: ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \ ! 383: : (ALIGN)) ! 384: ! 385: /* Macros to determine size of aggregates (structures and unions ! 386: in C). Normally, these may be defined to simply return the maximum ! 387: alignment and simple rounded-up size, but on some machines (like ! 388: the i960), the total size of a structure is based on a non-trivial ! 389: rounding method. */ ! 390: ! 391: #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \ ! 392: ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \ ! 393: ? i960_round_align ((SPECIFIED), TYPE_SIZE (TYPE)) \ ! 394: : MAX ((COMPUTED), (SPECIFIED))) ! 395: ! 396: #define ROUND_TYPE_SIZE(TYPE, SIZE, ALIGN) \ ! 397: ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \ ! 398: ? (tree) i960_round_size (SIZE) \ ! 399: : round_up ((SIZE), (ALIGN))) ! 400: ! 401: /* Standard register usage. */ ! 402: ! 403: /* Number of actual hardware registers. ! 404: The hardware registers are assigned numbers for the compiler ! 405: from 0 to just below FIRST_PSEUDO_REGISTER. ! 406: All registers that the compiler knows about must be given numbers, ! 407: even those that are not normally considered general registers. ! 408: ! 409: Registers 0-15 are the global registers (g0-g15). ! 410: Registers 16-31 are the local registers (r0-r15). ! 411: Register 32-35 are the fp registers (fp0-fp3). ! 412: Register 36 is the condition code register. ! 413: Register 37 is unused. */ ! 414: ! 415: #define FIRST_PSEUDO_REGISTER 38 ! 416: ! 417: /* 1 for registers that have pervasive standard uses and are not available ! 418: for the register allocator. On 80960, this includes the frame pointer ! 419: (g15), the previous FP (r0), the stack pointer (r1), the return ! 420: instruction pointer (r2), and the argument pointer (g14). */ ! 421: #define FIXED_REGISTERS \ ! 422: {0, 0, 0, 0, 0, 0, 0, 0, \ ! 423: 0, 0, 0, 0, 0, 0, 1, 1, \ ! 424: 1, 1, 1, 0, 0, 0, 0, 0, \ ! 425: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 426: 0, 0, 0, 0, 1, 1} ! 427: ! 428: /* 1 for registers not available across function calls. ! 429: These must include the FIXED_REGISTERS and also any ! 430: registers that can be used without being saved. ! 431: The latter must include the registers where values are returned ! 432: and the register where structure-value addresses are passed. ! 433: Aside from that, you can include as many other registers as you like. */ ! 434: ! 435: /* On the 80960, note that: ! 436: g0..g3 are used for return values, ! 437: g0..g7 may always be used for parameters, ! 438: g8..g11 may be used for parameters, but are preserved if they aren't, ! 439: g12 is always preserved, but otherwise unused, ! 440: g13 is the struct return ptr if used, or temp, but may be trashed, ! 441: g14 is the leaf return ptr or the arg block ptr otherwise zero, ! 442: must be reset to zero before returning if it was used, ! 443: g15 is the frame pointer, ! 444: r0 is the previous FP, ! 445: r1 is the stack pointer, ! 446: r2 is the return instruction pointer, ! 447: r3-r15 are always available, ! 448: fp0..fp3 are never available. */ ! 449: #define CALL_USED_REGISTERS \ ! 450: {1, 1, 1, 1, 1, 1, 1, 1, \ ! 451: 0, 0, 0, 0, 0, 1, 1, 1, \ ! 452: 1, 1, 1, 0, 0, 0, 0, 0, \ ! 453: 0, 0, 0, 0, 0, 0, 0, 0, \ ! 454: 1, 1, 1, 1, 1, 1} ! 455: ! 456: /* If no fp unit, make all of the fp registers fixed so that they can't ! 457: be used. */ ! 458: #define CONDITIONAL_REGISTER_USAGE \ ! 459: if (! TARGET_NUMERICS) { \ ! 460: fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\ ! 461: } \ ! 462: ! 463: /* Return number of consecutive hard regs needed starting at reg REGNO ! 464: to hold something of mode MODE. ! 465: This is ordinarily the length in words of a value of mode MODE ! 466: but can be less for certain modes in special long registers. ! 467: ! 468: On 80960, ordinary registers hold 32 bits worth, but can be ganged ! 469: together to hold double or extended precision floating point numbers, ! 470: and the floating point registers hold any size floating point number */ ! 471: #define HARD_REGNO_NREGS(REGNO, MODE) \ ! 472: ((REGNO) < 32 \ ! 473: ? (((MODE) == VOIDmode) \ ! 474: ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \ ! 475: : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0) ! 476: ! 477: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. ! 478: On 80960, the cpu registers can hold any mode but the float registers ! 479: can only hold SFmode, DFmode, or TFmode. */ ! 480: extern unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER]; ! 481: #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ! 482: ((hard_regno_mode_ok[REGNO] & (1 << (int) (MODE))) != 0) ! 483: ! 484: /* Value is 1 if it is a good idea to tie two pseudo registers ! 485: when one has mode MODE1 and one has mode MODE2. ! 486: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, ! 487: for any hard reg, then this must be 0 for correct output. */ ! 488: ! 489: #define MODES_TIEABLE_P(MODE1, MODE2) \ ! 490: ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) ! 491: ! 492: /* Specify the registers used for certain standard purposes. ! 493: The values of these macros are register numbers. */ ! 494: ! 495: /* 80960 pc isn't overloaded on a register that the compiler knows about. */ ! 496: /* #define PC_REGNUM */ ! 497: ! 498: /* Register to use for pushing function arguments. */ ! 499: #define STACK_POINTER_REGNUM 17 ! 500: ! 501: /* Actual top-of-stack address is same as ! 502: the contents of the stack pointer register. */ ! 503: #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size) ! 504: ! 505: /* Base register for access to local variables of the function. */ ! 506: #define FRAME_POINTER_REGNUM 15 ! 507: ! 508: /* Value should be nonzero if functions must have frame pointers. ! 509: Zero means the frame pointer need not be set up (and parms ! 510: may be accessed via the stack pointer) in functions that seem suitable. ! 511: This is computed in `reload', in reload1.c. */ ! 512: #define FRAME_POINTER_REQUIRED (! leaf_function_p ()) ! 513: ! 514: /* C statement to store the difference between the frame pointer ! 515: and the stack pointer values immediately after the function prologue. */ ! 516: ! 517: #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ ! 518: do { (VAR) = compute_frame_size (get_frame_size ()); } while (0) ! 519: ! 520: /* Base register for access to arguments of the function. */ ! 521: #define ARG_POINTER_REGNUM 14 ! 522: ! 523: /* Register in which static-chain is passed to a function. ! 524: On i960, we use r3. */ ! 525: #define STATIC_CHAIN_REGNUM 19 ! 526: ! 527: /* Functions which return large structures get the address ! 528: to place the wanted value at in g13. */ ! 529: ! 530: #define STRUCT_VALUE_REGNUM 13 ! 531: ! 532: /* The order in which to allocate registers. */ ! 533: ! 534: #define REG_ALLOC_ORDER \ ! 535: { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \ ! 536: 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \ ! 537: 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \ ! 538: 11, 12, /* g11, g12 */ \ ! 539: 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \ ! 540: /* We can't actually allocate these. */ \ ! 541: 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */ ! 542: ! 543: /* Define the classes of registers for register constraints in the ! 544: machine description. Also define ranges of constants. ! 545: ! 546: One of the classes must always be named ALL_REGS and include all hard regs. ! 547: If there is more than one class, another class must be named NO_REGS ! 548: and contain no registers. ! 549: ! 550: The name GENERAL_REGS must be the name of a class (or an alias for ! 551: another name such as ALL_REGS). This is the class of registers ! 552: that is allowed by "g" or "r" in a register constraint. ! 553: Also, registers outside this class are allocated only when ! 554: instructions express preferences for them. ! 555: ! 556: The classes must be numbered in nondecreasing order; that is, ! 557: a larger-numbered class must never be contained completely ! 558: in a smaller-numbered class. ! 559: ! 560: For any two classes, it is very desirable that there be another ! 561: class that represents their union. */ ! 562: ! 563: /* The 80960 has four kinds of registers, global, local, floating point, ! 564: and condition code. The cc register is never allocated, so no class ! 565: needs to be defined for it. */ ! 566: ! 567: enum reg_class { NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS, ! 568: FP_REGS, ALL_REGS, LIM_REG_CLASSES }; ! 569: ! 570: /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never ! 571: does. */ ! 572: #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS) ! 573: ! 574: #define N_REG_CLASSES (int) LIM_REG_CLASSES ! 575: ! 576: /* Give names of register classes as strings for dump file. */ ! 577: ! 578: #define REG_CLASS_NAMES \ ! 579: { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \ ! 580: "FP_REGS", "ALL_REGS" } ! 581: ! 582: /* Define which registers fit in which classes. ! 583: This is an initializer for a vector of HARD_REG_SET ! 584: of length N_REG_CLASSES. */ ! 585: ! 586: #define REG_CLASS_CONTENTS \ ! 587: { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}} ! 588: ! 589: /* The same information, inverted: ! 590: Return the class number of the smallest class containing ! 591: reg number REGNO. This could be a conditional expression ! 592: or could index an array. */ ! 593: ! 594: #define REGNO_REG_CLASS(REGNO) \ ! 595: ((REGNO) < 16 ? GLOBAL_REGS \ ! 596: : (REGNO) < 32 ? LOCAL_REGS \ ! 597: : (REGNO) < 36 ? FP_REGS \ ! 598: : NO_REGS) ! 599: ! 600: /* The class value for index registers, and the one for base regs. ! 601: There is currently no difference between base and index registers on the ! 602: i960, but this distinction may one day be useful. */ ! 603: #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS ! 604: #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS ! 605: ! 606: /* Get reg_class from a letter such as appears in the machine description. ! 607: 'f' is a floating point register (fp0..fp3) ! 608: 'l' is a local register (r0-r15) ! 609: 'b' is a global register (g0-g15) ! 610: 'd' is any local or global register ! 611: 'r' or 'g' are pre-defined to the class GENERAL_REGS. */ ! 612: /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not* ! 613: the same thing, since 'r' may include the fp registers. */ ! 614: #define REG_CLASS_FROM_LETTER(C) \ ! 615: (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \ ! 616: (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS))) ! 617: ! 618: /* The letters I, J, K, L and M in a register constraint string ! 619: can be used to stand for particular ranges of immediate operands. ! 620: This macro defines what the ranges are. ! 621: C is the letter, and VALUE is a constant value. ! 622: Return 1 if VALUE is in the range specified by C. ! 623: ! 624: For 80960: ! 625: 'I' is used for literal values 0..31 ! 626: 'J' means literal 0 ! 627: 'K' means 0..-31. */ ! 628: ! 629: #define CONST_OK_FOR_LETTER_P(VALUE, C) \ ! 630: ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \ ! 631: : (C) == 'J' ? ((VALUE) == 0) \ ! 632: : (C) == 'K' ? ((VALUE) > -32 && (VALUE) <= 0) \ ! 633: : 0) ! 634: ! 635: /* Similar, but for floating constants, and defining letters G and H. ! 636: Here VALUE is the CONST_DOUBLE rtx itself. ! 637: For the 80960, G is 0.0 and H is 1.0. */ ! 638: ! 639: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ ! 640: ((TARGET_NUMERICS) && \ ! 641: (((C) == 'G' && ((VALUE) == CONST0_RTX (DFmode) \ ! 642: || (VALUE) == CONST0_RTX (SFmode))) \ ! 643: || ((C) == 'H' && ((VALUE) == CONST1_RTX (DFmode) \ ! 644: || (VALUE) == CONST1_RTX (SFmode))))) ! 645: ! 646: /* Given an rtx X being reloaded into a reg required to be ! 647: in class CLASS, return the class of reg to actually use. ! 648: In general this is just CLASS; but on some machines ! 649: in some cases it is preferable to use a more restrictive class. */ ! 650: ! 651: /* On 960, can't load constant into floating-point reg except ! 652: 0.0 or 1.0. ! 653: ! 654: Any hard reg is ok as a src operand of a reload insn. */ ! 655: ! 656: #define PREFERRED_RELOAD_CLASS(X,CLASS) \ ! 657: (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \ ! 658: ? (CLASS) \ ! 659: : ((CLASS) == FP_REGS && CONSTANT_P (X) \ ! 660: && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\ ! 661: && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\ ! 662: ? NO_REGS \ ! 663: : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS))) ! 664: ! 665: #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ ! 666: secondary_reload_class (CLASS, MODE, IN) ! 667: ! 668: /* Return the maximum number of consecutive registers ! 669: needed to represent mode MODE in a register of class CLASS. */ ! 670: /* On 80960, this is the size of MODE in words, ! 671: except in the FP regs, where a single reg is always enough. */ ! 672: #define CLASS_MAX_NREGS(CLASS, MODE) \ ! 673: ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE))) ! 674: ! 675: /* Stack layout; function entry, exit and calling. */ ! 676: ! 677: /* Define this if pushing a word on the stack ! 678: makes the stack pointer a smaller address. */ ! 679: /* #define STACK_GROWS_DOWNWARD */ ! 680: ! 681: /* Define this if the nominal address of the stack frame ! 682: is at the high-address end of the local variables; ! 683: that is, each additional local variable allocated ! 684: goes at a more negative offset in the frame. */ ! 685: /* #define FRAME_GROWS_DOWNWARD */ ! 686: ! 687: /* Offset within stack frame to start allocating local variables at. ! 688: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the ! 689: first local allocated. Otherwise, it is the offset to the BEGINNING ! 690: of the first local allocated. ! 691: ! 692: The i960 has a 64 byte register save area, plus possibly some extra ! 693: bytes allocated for varargs functions. */ ! 694: #define STARTING_FRAME_OFFSET 64 ! 695: ! 696: /* If we generate an insn to push BYTES bytes, ! 697: this says how many the stack pointer really advances by. ! 698: On 80960, don't define this because there are no push insns. */ ! 699: /* #define PUSH_ROUNDING(BYTES) BYTES */ ! 700: ! 701: /* Offset of first parameter from the argument pointer register value. */ ! 702: #define FIRST_PARM_OFFSET(FNDECL) 0 ! 703: ! 704: /* When a parameter is passed in a register, no stack space is ! 705: allocated for it. However, when args are passed in the ! 706: stack, space is allocated for every register parameter. */ ! 707: #define MAYBE_REG_PARM_STACK_SPACE 48 ! 708: #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \ ! 709: i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE); ! 710: #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL) ! 711: #define OUTGOING_REG_PARM_STACK_SPACE ! 712: ! 713: /* Keep the stack pointer constant throughout the function. */ ! 714: #define ACCUMULATE_OUTGOING_ARGS ! 715: ! 716: /* Value is 1 if returning from a function call automatically ! 717: pops the arguments described by the number-of-args field in the call. ! 718: FUNTYPE is the data type of the function (as a tree), ! 719: or for a library call it is an identifier node for the subroutine name. */ ! 720: ! 721: #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0 ! 722: ! 723: /* Define how to find the value returned by a library function ! 724: assuming the value has mode MODE. */ ! 725: ! 726: #define LIBCALL_VALUE(MODE) gen_rtx ((REG), (MODE), 0) ! 727: ! 728: /* 1 if N is a possible register number for a function value ! 729: as seen by the caller. ! 730: On 80960, returns are in g0..g3 */ ! 731: ! 732: #define FUNCTION_VALUE_REGNO_P(N) ((N) < 4) ! 733: ! 734: /* 1 if N is a possible register number for function argument passing. ! 735: On 80960, parameters are passed in g0..g11 */ ! 736: ! 737: #define FUNCTION_ARG_REGNO_P(N) ((N) < 12) ! 738: ! 739: /* Perform any needed actions needed for a function that is receiving a ! 740: variable number of arguments. ! 741: ! 742: CUM is as above. ! 743: ! 744: MODE and TYPE are the mode and type of the current parameter. ! 745: ! 746: PRETEND_SIZE is a variable that should be set to the amount of stack ! 747: that must be pushed by the prolog to pretend that our caller pushed ! 748: it. ! 749: ! 750: Normally, this macro will push all remaining incoming registers on the ! 751: stack and set PRETEND_SIZE to the length of the registers pushed. */ ! 752: ! 753: #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \ ! 754: i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL) ! 755: ! 756: /* Define a data type for recording info about an argument list ! 757: during the scan of that argument list. This data type should ! 758: hold all necessary information about the function itself ! 759: and about the args processed so far, enough to enable macros ! 760: such as FUNCTION_ARG to determine where the next arg should go. ! 761: ! 762: On 80960, this is two integers, which count the number of register ! 763: parameters and the number of stack parameters seen so far. */ ! 764: ! 765: struct cum_args { int ca_nregparms; int ca_nstackparms; }; ! 766: ! 767: #define CUMULATIVE_ARGS struct cum_args ! 768: ! 769: /* Define the number of registers that can hold parameters. ! 770: This macro is used only in macro definitions below and/or i960.c. */ ! 771: #define NPARM_REGS 12 ! 772: ! 773: /* Define how to round to the next parameter boundary. ! 774: This macro is used only in macro definitions below and/or i960.c. */ ! 775: #define ROUND(X, MULTIPLE_OF) \ ! 776: ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF) ! 777: ! 778: /* Initialize a variable CUM of type CUMULATIVE_ARGS ! 779: for a call to a function whose data type is FNTYPE. ! 780: For a library call, FNTYPE is 0. ! 781: ! 782: On 80960, the offset always starts at 0; the first parm reg is g0. */ ! 783: ! 784: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ ! 785: ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0) ! 786: ! 787: /* Update the data in CUM to advance over an argument ! 788: of mode MODE and data type TYPE. ! 789: CUM should be advanced to align with the data type accessed and ! 790: also the size of that data type in # of regs. ! 791: (TYPE is null for libcalls where that information may not be available.) */ ! 792: ! 793: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ ! 794: i960_function_arg_advance(&CUM, MODE, TYPE, NAMED) ! 795: ! 796: /* Indicate the alignment boundary for an argument of the specified mode and ! 797: type. */ ! 798: #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ ! 799: (((TYPE) != 0) \ ! 800: ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \ ! 801: ? PARM_BOUNDARY \ ! 802: : TYPE_ALIGN (TYPE)) \ ! 803: : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \ ! 804: ? PARM_BOUNDARY \ ! 805: : GET_MODE_ALIGNMENT (MODE))) ! 806: ! 807: /* Determine where to put an argument to a function. ! 808: Value is zero to push the argument on the stack, ! 809: or a hard register in which to store the argument. ! 810: ! 811: MODE is the argument's machine mode. ! 812: TYPE is the data type of the argument (as a tree). ! 813: This is null for libcalls where that information may ! 814: not be available. ! 815: CUM is a variable of type CUMULATIVE_ARGS which gives info about ! 816: the preceding args and about the function being called. ! 817: NAMED is nonzero if this argument is a named parameter ! 818: (otherwise it is an extra parameter matching an ellipsis). */ ! 819: ! 820: extern struct rtx_def *i960_function_arg (); ! 821: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ ! 822: i960_function_arg(&CUM, MODE, TYPE, NAMED) ! 823: ! 824: /* Define how to find the value returned by a function. ! 825: VALTYPE is the data type of the value (as a tree). ! 826: If the precise function being called is known, FUNC is its FUNCTION_DECL; ! 827: otherwise, FUNC is 0. */ ! 828: ! 829: extern struct rtx_def *i960_function_value (); ! 830: #define FUNCTION_VALUE(TYPE, FUNC) i960_function_value (TYPE) ! 831: ! 832: /* Force objects larger than 16 bytes to be returned in memory, since we ! 833: only have 4 registers available for return values. */ ! 834: ! 835: #define RETURN_IN_MEMORY(TYPE) (int_size_in_bytes (TYPE) > 16) ! 836: ! 837: /* For an arg passed partly in registers and partly in memory, ! 838: this is the number of registers used. ! 839: This never happens on 80960. */ ! 840: ! 841: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0 ! 842: ! 843: /* Output the label for a function definition. ! 844: This handles leaf functions and a few other things for the i960. */ ! 845: ! 846: #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \ ! 847: i960_function_name_declare (FILE, NAME, DECL) ! 848: ! 849: /* This macro generates the assembly code for function entry. ! 850: FILE is a stdio stream to output the code to. ! 851: SIZE is an int: how many units of temporary storage to allocate. ! 852: Refer to the array `regs_ever_live' to determine which registers ! 853: to save; `regs_ever_live[I]' is nonzero if register number I ! 854: is ever used in the function. This macro is responsible for ! 855: knowing which registers should not be saved even if used. */ ! 856: ! 857: #define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE)) ! 858: ! 859: /* Output assembler code to FILE to increment profiler label # LABELNO ! 860: for profiling a function entry. */ ! 861: ! 862: #define FUNCTION_PROFILER(FILE, LABELNO) \ ! 863: fprintf (FILE, "\tlda LP%d,g0\n\tbal mcount\n", (LABELNO)) ! 864: ! 865: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, ! 866: the stack pointer does not matter. The value is tested only in ! 867: functions that have frame pointers. ! 868: No definition is equivalent to always zero. */ ! 869: ! 870: #define EXIT_IGNORE_STACK 1 ! 871: ! 872: /* This macro generates the assembly code for function exit, ! 873: on machines that need it. If FUNCTION_EPILOGUE is not defined ! 874: then individual return instructions are generated for each ! 875: return statement. Args are same as for FUNCTION_PROLOGUE. ! 876: ! 877: The function epilogue should not depend on the current stack pointer! ! 878: It should use the frame pointer only. This is mandatory because ! 879: of alloca; we also take advantage of it to omit stack adjustments ! 880: before returning. */ ! 881: ! 882: #define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE) ! 883: ! 884: /* Addressing modes, and classification of registers for them. */ ! 885: ! 886: /* #define HAVE_POST_INCREMENT */ ! 887: /* #define HAVE_POST_DECREMENT */ ! 888: ! 889: /* #define HAVE_PRE_DECREMENT */ ! 890: /* #define HAVE_PRE_INCREMENT */ ! 891: ! 892: /* Macros to check register numbers against specific register classes. */ ! 893: ! 894: /* These assume that REGNO is a hard or pseudo reg number. ! 895: They give nonzero only if REGNO is a hard reg of the suitable class ! 896: or a pseudo reg currently allocated to a suitable hard reg. ! 897: Since they use reg_renumber, they are safe only once reg_renumber ! 898: has been allocated, which happens in local-alloc.c. */ ! 899: ! 900: #define REGNO_OK_FOR_INDEX_P(REGNO) \ ! 901: ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) ! 902: #define REGNO_OK_FOR_BASE_P(REGNO) \ ! 903: ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32) ! 904: #define REGNO_OK_FOR_FP_P(REGNO) \ ! 905: ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36) ! 906: ! 907: /* Now macros that check whether X is a register and also, ! 908: strictly, whether it is in a specified class. ! 909: ! 910: These macros are specific to the 960, and may be used only ! 911: in code for printing assembler insns and in conditions for ! 912: define_optimization. */ ! 913: ! 914: /* 1 if X is an fp register. */ ! 915: ! 916: #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36) ! 917: ! 918: /* Maximum number of registers that can appear in a valid memory address. */ ! 919: #define MAX_REGS_PER_ADDRESS 2 ! 920: ! 921: #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X) ! 922: ! 923: /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X ! 924: is a legitimate general operand. ! 925: It is given that X satisfies CONSTANT_P. ! 926: ! 927: Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0. */ ! 928: ! 929: #define LEGITIMATE_CONSTANT_P(X) \ ! 930: ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), VOIDmode)) ! 931: ! 932: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx ! 933: and check its validity for a certain class. ! 934: We have two alternate definitions for each of them. ! 935: The usual definition accepts all pseudo regs; the other rejects ! 936: them unless they have been allocated suitable hard regs. ! 937: The symbol REG_OK_STRICT causes the latter definition to be used. ! 938: ! 939: Most source files want to accept pseudo regs in the hope that ! 940: they will get allocated to the class that the insn wants them to be in. ! 941: Source files for reload pass need to be strict. ! 942: After reload, it makes no difference, since pseudo regs have ! 943: been eliminated by then. */ ! 944: ! 945: #ifndef REG_OK_STRICT ! 946: ! 947: /* Nonzero if X is a hard reg that can be used as an index ! 948: or if it is a pseudo reg. */ ! 949: #define REG_OK_FOR_INDEX_P(X) \ ! 950: (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER) ! 951: /* Nonzero if X is a hard reg that can be used as a base reg ! 952: or if it is a pseudo reg. */ ! 953: #define REG_OK_FOR_BASE_P(X) \ ! 954: (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER) ! 955: ! 956: #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) ! 957: #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X)) ! 958: ! 959: #else ! 960: ! 961: /* Nonzero if X is a hard reg that can be used as an index. */ ! 962: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) ! 963: /* Nonzero if X is a hard reg that can be used as a base reg. */ ! 964: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) ! 965: ! 966: #endif ! 967: ! 968: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression ! 969: that is a valid memory address for an instruction. ! 970: The MODE argument is the machine mode for the MEM expression ! 971: that wants to use this address. ! 972: ! 973: On 80960, legitimate addresses are: ! 974: base ld (g0),r0 ! 975: disp (12 or 32 bit) ld foo,r0 ! 976: base + index ld (g0)[g1*1],r0 ! 977: base + displ ld 0xf00(g0),r0 ! 978: base + index*scale + displ ld 0xf00(g0)[g1*4],r0 ! 979: index*scale + base ld (g0)[g1*4],r0 ! 980: index*scale + displ ld 0xf00[g1*4],r0 ! 981: index*scale ld [g1*4],r0 ! 982: index + base + displ ld 0xf00(g0)[g1*1],r0 ! 983: ! 984: In each case, scale can be 1, 2, 4, 8, or 16. */ ! 985: ! 986: /* Returns 1 if the scale factor of an index term is valid. */ ! 987: #define SCALE_TERM_P(X) \ ! 988: (GET_CODE (X) == CONST_INT \ ! 989: && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \ ! 990: || INTVAL(X) == 8 || INTVAL (X) == 16)) ! 991: ! 992: ! 993: #ifdef REG_OK_STRICT ! 994: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ ! 995: { if (legitimate_address_p (MODE, X, 1)) goto ADDR; } ! 996: #else ! 997: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ ! 998: { if (legitimate_address_p (MODE, X, 0)) goto ADDR; } ! 999: #endif ! 1000: ! 1001: /* Try machine-dependent ways of modifying an illegitimate address ! 1002: to be legitimate. If we find one, return the new, valid address. ! 1003: This macro is used in only one place: `memory_address' in explow.c. ! 1004: ! 1005: OLDX is the address as it was before break_out_memory_refs was called. ! 1006: In some cases it is useful to look at this to decide what needs to be done. ! 1007: ! 1008: MODE and WIN are passed so that this macro can use ! 1009: GO_IF_LEGITIMATE_ADDRESS. ! 1010: ! 1011: It is always safe for this macro to do nothing. It exists to recognize ! 1012: opportunities to optimize the output. */ ! 1013: ! 1014: /* On 80960, convert non-cannonical addresses to canonical form. */ ! 1015: ! 1016: extern struct rtx_def *legitimize_address (); ! 1017: #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \ ! 1018: { rtx orig_x = (X); \ ! 1019: (X) = legitimize_address (X, OLDX, MODE); \ ! 1020: if ((X) != orig_x && memory_address_p (MODE, X)) \ ! 1021: goto WIN; } ! 1022: ! 1023: /* Go to LABEL if ADDR (a legitimate address expression) ! 1024: has an effect that depends on the machine mode it is used for. ! 1025: On the 960 this is never true. */ ! 1026: ! 1027: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) ! 1028: ! 1029: /* Specify the machine mode that this machine uses ! 1030: for the index in the tablejump instruction. */ ! 1031: #define CASE_VECTOR_MODE SImode ! 1032: ! 1033: /* Define this if the tablejump instruction expects the table ! 1034: to contain offsets from the address of the table. ! 1035: Do not define this if the table should contain absolute addresses. */ ! 1036: /* #define CASE_VECTOR_PC_RELATIVE */ ! 1037: ! 1038: /* Specify the tree operation to be used to convert reals to integers. */ ! 1039: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR ! 1040: ! 1041: /* This is the kind of divide that is easiest to do in the general case. */ ! 1042: #define EASY_DIV_EXPR TRUNC_DIV_EXPR ! 1043: ! 1044: /* Define this as 1 if `char' should by default be signed; else as 0. */ ! 1045: #define DEFAULT_SIGNED_CHAR 0 ! 1046: ! 1047: /* Allow and ignore #sccs directives. */ ! 1048: #define SCCS_DIRECTIVE ! 1049: ! 1050: /* Max number of bytes we can move from memory to memory ! 1051: in one reasonably fast instruction. */ ! 1052: #define MOVE_MAX 16 ! 1053: ! 1054: /* Define if normal loads of shorter-than-word items from memory clears ! 1055: the rest of the bigs in the register. */ ! 1056: #define BYTE_LOADS_ZERO_EXTEND ! 1057: ! 1058: /* Nonzero if access to memory by bytes is no faster than for words. ! 1059: Defining this results in worse code on the i960. */ ! 1060: ! 1061: #define SLOW_BYTE_ACCESS 0 ! 1062: ! 1063: /* We assume that the store-condition-codes instructions store 0 for false ! 1064: and some other value for true. This is the value stored for true. */ ! 1065: ! 1066: #define STORE_FLAG_VALUE 1 ! 1067: ! 1068: /* Define if shifts truncate the shift count ! 1069: which implies one can omit a sign-extension or zero-extension ! 1070: of a shift count. */ ! 1071: #define SHIFT_COUNT_TRUNCATED ! 1072: ! 1073: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits ! 1074: is done just by pretending it is already truncated. */ ! 1075: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 ! 1076: ! 1077: /* Specify the machine mode that pointers have. ! 1078: After generation of rtl, the compiler makes no further distinction ! 1079: between pointers and any other objects of this machine mode. */ ! 1080: #define Pmode SImode ! 1081: ! 1082: /* Specify the widest mode that BLKmode objects can be promoted to */ ! 1083: #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) ! 1084: ! 1085: /* These global variables are used to pass information between ! 1086: cc setter and cc user at insn emit time. */ ! 1087: ! 1088: extern struct rtx_def *i960_compare_op0, *i960_compare_op1; ! 1089: ! 1090: /* Define the function that build the compare insn for scc and bcc. */ ! 1091: ! 1092: extern struct rtx_def *gen_compare_reg (); ! 1093: ! 1094: /* Add any extra modes needed to represent the condition code. ! 1095: ! 1096: Also, signed and unsigned comparisons are distinguished, as ! 1097: are operations which are compatible with chkbit insns. */ ! 1098: #define EXTRA_CC_MODES CC_UNSmode, CC_CHKmode ! 1099: ! 1100: /* Define the names for the modes specified above. */ ! 1101: #define EXTRA_CC_NAMES "CC_UNS", "CC_CHK" ! 1102: ! 1103: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, ! 1104: return the mode to be used for the comparison. For floating-point, CCFPmode ! 1105: should be used. CC_NOOVmode should be used when the first operand is a ! 1106: PLUS, MINUS, or NEG. CCmode should be used when no special processing is ! 1107: needed. */ ! 1108: #define SELECT_CC_MODE(OP,X) select_cc_mode (OP, X) ! 1109: ! 1110: /* A function address in a call instruction is a byte address ! 1111: (for indexing purposes) so give the MEM rtx a byte's mode. */ ! 1112: #define FUNCTION_MODE SImode ! 1113: ! 1114: /* Define this if addresses of constant functions ! 1115: shouldn't be put through pseudo regs where they can be cse'd. ! 1116: Desirable on machines where ordinary constants are expensive ! 1117: but a CALL with constant address is cheap. */ ! 1118: #define NO_FUNCTION_CSE ! 1119: ! 1120: /* Use memcpy, etc. instead of bcopy. */ ! 1121: ! 1122: #ifndef WIND_RIVER ! 1123: #define TARGET_MEM_FUNCTIONS 1 ! 1124: #endif ! 1125: ! 1126: /* Compute the cost of computing a constant rtl expression RTX ! 1127: whose rtx-code is CODE. The body of this macro is a portion ! 1128: of a switch statement. If the code is computed here, ! 1129: return it with a return statement. Otherwise, break from the switch. */ ! 1130: ! 1131: /* Constants that can be (non-ldconst) insn operands are cost 0. Constants ! 1132: that can be non-ldconst operands in rare cases are cost 1. Other constants ! 1133: have higher costs. */ ! 1134: ! 1135: #define CONST_COSTS(RTX, CODE, OUTER_CODE) \ ! 1136: case CONST_INT: \ ! 1137: if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \ ! 1138: || power2_operand (RTX, VOIDmode)) \ ! 1139: return 0; \ ! 1140: else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \ ! 1141: return 1; \ ! 1142: case CONST: \ ! 1143: case LABEL_REF: \ ! 1144: case SYMBOL_REF: \ ! 1145: return (TARGET_FLAG_C_SERIES ? 6 : 8); \ ! 1146: case CONST_DOUBLE: \ ! 1147: if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \ ! 1148: || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\ ! 1149: return 1; \ ! 1150: return 12; ! 1151: ! 1152: /* The i960 offers addressing modes which are "as cheap as a register". ! 1153: See i960.c (or gcc.texinfo) for details. */ ! 1154: ! 1155: #define ADDRESS_COST(RTX) \ ! 1156: (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX)) ! 1157: ! 1158: /* Control the assembler format that we output. */ ! 1159: ! 1160: /* Output at beginning of assembler file. */ ! 1161: ! 1162: #define ASM_FILE_START(file) ! 1163: ! 1164: /* Output to assembler file text saying following lines ! 1165: may contain character constants, extra white space, comments, etc. */ ! 1166: ! 1167: #define ASM_APP_ON "" ! 1168: ! 1169: /* Output to assembler file text saying following lines ! 1170: no longer contain unusual constructs. */ ! 1171: ! 1172: #define ASM_APP_OFF "" ! 1173: ! 1174: /* Output before read-only data. */ ! 1175: ! 1176: #define TEXT_SECTION_ASM_OP ".text" ! 1177: ! 1178: /* Output before writable data. */ ! 1179: ! 1180: #define DATA_SECTION_ASM_OP ".data" ! 1181: ! 1182: /* How to refer to registers in assembler output. ! 1183: This sequence is indexed by compiler's hard-register-number (see above). */ ! 1184: ! 1185: #define REGISTER_NAMES { \ ! 1186: "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \ ! 1187: "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \ ! 1188: "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \ ! 1189: "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \ ! 1190: "fp0","fp1","fp2", "fp3", "cc", "fake" } ! 1191: ! 1192: /* How to renumber registers for dbx and gdb. ! 1193: In the 960 encoding, g0..g15 are registers 16..31. */ ! 1194: ! 1195: #define DBX_REGISTER_NUMBER(REGNO) \ ! 1196: (((REGNO) < 16) ? (REGNO) + 16 \ ! 1197: : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16)) ! 1198: ! 1199: /* Don't emit dbx records longer than this. This is an arbitrary value. */ ! 1200: #define DBX_CONTIN_LENGTH 1500 ! 1201: ! 1202: /* This is how to output a note to DBX telling it the line number ! 1203: to which the following sequence of instructions corresponds. */ ! 1204: ! 1205: #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \ ! 1206: { if (write_symbols == SDB_DEBUG) { \ ! 1207: fprintf ((FILE), "\t.ln %d\n", \ ! 1208: (sdb_begin_function_line \ ! 1209: ? (LINE) - sdb_begin_function_line : 1)); \ ! 1210: } else if (write_symbols == DBX_DEBUG) { \ ! 1211: fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \ ! 1212: } } ! 1213: ! 1214: /* This is how to output the definition of a user-level label named NAME, ! 1215: such as the label on a static function or variable NAME. */ ! 1216: ! 1217: #define ASM_OUTPUT_LABEL(FILE,NAME) \ ! 1218: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) ! 1219: ! 1220: /* This is how to output a command to make the user-level label named NAME ! 1221: defined for reference from other files. */ ! 1222: ! 1223: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ ! 1224: { fputs ("\t.globl ", FILE); \ ! 1225: assemble_name (FILE, NAME); \ ! 1226: fputs ("\n", FILE); } ! 1227: ! 1228: /* This is how to output a reference to a user-level label named NAME. ! 1229: `assemble_name' uses this. */ ! 1230: ! 1231: #define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME) ! 1232: ! 1233: /* This is how to output an internal numbered label where ! 1234: PREFIX is the class of label and NUM is the number within the class. */ ! 1235: ! 1236: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ ! 1237: fprintf (FILE, "%s%d:\n", PREFIX, NUM) ! 1238: ! 1239: /* This is how to store into the string LABEL ! 1240: the symbol_ref name of an internal numbered label where ! 1241: PREFIX is the class of label and NUM is the number within the class. ! 1242: This is suitable for output with `assemble_name'. */ ! 1243: ! 1244: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ ! 1245: sprintf (LABEL, "*%s%d", PREFIX, NUM) ! 1246: ! 1247: /* This is how to output an assembler line defining a `double' constant. */ ! 1248: ! 1249: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) i960_output_double(FILE, VALUE) ! 1250: ! 1251: /* This is how to output an assembler line defining a `float' constant. */ ! 1252: ! 1253: #define ASM_OUTPUT_FLOAT(FILE,VALUE) i960_output_float(FILE, VALUE) ! 1254: ! 1255: /* This is how to output an assembler line defining an `int' constant. */ ! 1256: ! 1257: #define ASM_OUTPUT_INT(FILE,VALUE) \ ! 1258: ( fprintf (FILE, "\t.word "), \ ! 1259: output_addr_const (FILE, (VALUE)), \ ! 1260: fprintf (FILE, "\n")) ! 1261: ! 1262: /* Likewise for `char' and `short' constants. */ ! 1263: ! 1264: #define ASM_OUTPUT_SHORT(FILE,VALUE) \ ! 1265: ( fprintf (FILE, "\t.short "), \ ! 1266: output_addr_const (FILE, (VALUE)), \ ! 1267: fprintf (FILE, "\n")) ! 1268: ! 1269: #define ASM_OUTPUT_CHAR(FILE,VALUE) \ ! 1270: ( fprintf (FILE, "\t.byte "), \ ! 1271: output_addr_const (FILE, (VALUE)), \ ! 1272: fprintf (FILE, "\n")) ! 1273: ! 1274: /* This is how to output an assembler line for a numeric constant byte. */ ! 1275: ! 1276: #define ASM_OUTPUT_BYTE(FILE,VALUE) \ ! 1277: fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) ! 1278: ! 1279: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ ! 1280: fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO]) ! 1281: ! 1282: /* This is how to output an insn to pop a register from the stack. ! 1283: It need not be very fast code. */ ! 1284: ! 1285: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ ! 1286: fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO]) ! 1287: ! 1288: /* This is how to output an element of a case-vector that is absolute. */ ! 1289: ! 1290: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ ! 1291: fprintf (FILE, "\t.word L%d\n", VALUE) ! 1292: ! 1293: /* This is how to output an element of a case-vector that is relative. */ ! 1294: ! 1295: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ ! 1296: fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL) ! 1297: ! 1298: /* This is how to output an assembler line that says to advance the ! 1299: location counter to a multiple of 2**LOG bytes. */ ! 1300: ! 1301: #define ASM_OUTPUT_ALIGN(FILE,LOG) \ ! 1302: fprintf (FILE, "\t.align %d\n", (LOG)) ! 1303: ! 1304: #define ASM_OUTPUT_SKIP(FILE,SIZE) \ ! 1305: fprintf (FILE, "\t.space %d\n", (SIZE)) ! 1306: ! 1307: /* This says how to output an assembler line ! 1308: to define a global common symbol. */ ! 1309: ! 1310: /* For common objects, output unpadded size... gld960 & lnk960 both ! 1311: have code to align each common object at link time. Also, if size ! 1312: is 0, treat this as a declaration, not a definition - i.e., ! 1313: do nothing at all. */ ! 1314: ! 1315: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ ! 1316: { if ((SIZE) != 0) \ ! 1317: { \ ! 1318: fputs (".globl ", (FILE)), \ ! 1319: assemble_name ((FILE), (NAME)), \ ! 1320: fputs ("\n.comm ", (FILE)), \ ! 1321: assemble_name ((FILE), (NAME)), \ ! 1322: fprintf ((FILE), ",%d\n", (ROUNDED)); \ ! 1323: } \ ! 1324: } ! 1325: ! 1326: /* This says how to output an assembler line to define a local common symbol. ! 1327: Output unpadded size, with request to linker to align as requested. ! 1328: 0 size should not be possible here. */ ! 1329: ! 1330: #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \ ! 1331: ( fputs (".bss\t", (FILE)), \ ! 1332: assemble_name ((FILE), (NAME)), \ ! 1333: fprintf ((FILE), ",%d,%d\n", (SIZE), \ ! 1334: ((ALIGN) <= 8 ? 0 \ ! 1335: : ((ALIGN) <= 16 ? 1 \ ! 1336: : ((ALIGN) <= 32 ? 2 \ ! 1337: : ((ALIGN <= 64 ? 3 : 4))))))) ! 1338: ! 1339: /* Output text for an #ident directive. */ ! 1340: #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR); ! 1341: ! 1342: /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */ ! 1343: ! 1344: #define ASM_OUTPUT_ALIGN_CODE(FILE) \ ! 1345: { if (TARGET_CODE_ALIGN) fputs("\t.align 3\n",FILE); } ! 1346: ! 1347: /* Store in OUTPUT a string (made with alloca) containing ! 1348: an assembler-name for a local static variable named NAME. ! 1349: LABELNO is an integer which is different for each call. */ ! 1350: ! 1351: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ ! 1352: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ ! 1353: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) ! 1354: ! 1355: /* Define the parentheses used to group arithmetic operations ! 1356: in assembler code. */ ! 1357: ! 1358: #define ASM_OPEN_PAREN "(" ! 1359: #define ASM_CLOSE_PAREN ")" ! 1360: ! 1361: /* Define results of standard character escape sequences. */ ! 1362: #define TARGET_BELL 007 ! 1363: #define TARGET_BS 010 ! 1364: #define TARGET_TAB 011 ! 1365: #define TARGET_NEWLINE 012 ! 1366: #define TARGET_VT 013 ! 1367: #define TARGET_FF 014 ! 1368: #define TARGET_CR 015 ! 1369: ! 1370: /* Output assembler code to FILE to initialize this source file's ! 1371: basic block profiling info, if that has not already been done. */ ! 1372: ! 1373: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ ! 1374: { fprintf (FILE, "\tld LPBX0,g12\n"); \ ! 1375: fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\ ! 1376: fprintf (FILE, "\tlda LPBX0,g12\n"); \ ! 1377: fprintf (FILE, "\tcall ___bb_init_func\n"); \ ! 1378: fprintf (FILE, "LPY%d:\n",LABELNO); } ! 1379: ! 1380: /* Output assembler code to FILE to increment the entry-count for ! 1381: the BLOCKNO'th basic block in this source file. */ ! 1382: ! 1383: #define BLOCK_PROFILER(FILE, BLOCKNO) \ ! 1384: { int blockn = (BLOCKNO); \ ! 1385: fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \ ! 1386: fprintf (FILE, "\taddo g12,1,g12\n"); \ ! 1387: fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); } ! 1388: ! 1389: /* Print operand X (an rtx) in assembler syntax to file FILE. ! 1390: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. ! 1391: For `%' followed by punctuation, CODE is the punctuation and X is null. */ ! 1392: ! 1393: #define PRINT_OPERAND(FILE, X, CODE) \ ! 1394: i960_print_operand (FILE, X, CODE); ! 1395: ! 1396: /* Print a memory address as an operand to reference that memory location. */ ! 1397: ! 1398: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ ! 1399: i960_print_operand_addr (FILE, ADDR) ! 1400: ! 1401: /* Output assembler code for a block containing the constant parts ! 1402: of a trampoline, leaving space for the variable parts. */ ! 1403: ! 1404: /* On the i960, the trampoline contains three instructions: ! 1405: ldconst _function, r4 ! 1406: ldconst static addr, r3 ! 1407: jump (r4) */ ! 1408: ! 1409: #define TRAMPOLINE_TEMPLATE(FILE) \ ! 1410: { \ ! 1411: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C203000)); \ ! 1412: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ ! 1413: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C183000)); \ ! 1414: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \ ! 1415: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x84212000)); \ ! 1416: } ! 1417: ! 1418: /* Length in units of the trampoline for entering a nested function. */ ! 1419: ! 1420: #define TRAMPOLINE_SIZE 20 ! 1421: ! 1422: /* Emit RTL insns to initialize the variable parts of a trampoline. ! 1423: FNADDR is an RTX for the address of the function's pure code. ! 1424: CXT is an RTX for the static chain value for the function. */ ! 1425: ! 1426: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ ! 1427: { \ ! 1428: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), \ ! 1429: FNADDR); \ ! 1430: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), \ ! 1431: CXT); \ ! 1432: } ! 1433: ! 1434: #if 0 ! 1435: /* Promote char and short arguments to ints, when want compitibility with ! 1436: the iC960 compilers. */ ! 1437: ! 1438: /* ??? In order for this to work, all users would need to be changed ! 1439: to test the value of the macro at run time. */ ! 1440: #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE ! 1441: /* ??? This does not exist. */ ! 1442: #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE ! 1443: #endif ! 1444: ! 1445: /* Instruction type definitions. Used to alternate instructions types for ! 1446: better performance on the C series chips. */ ! 1447: ! 1448: enum insn_types { I_TYPE_REG, I_TYPE_MEM, I_TYPE_CTRL }; ! 1449: ! 1450: /* Holds the insn type of the last insn output to the assembly file. */ ! 1451: ! 1452: extern enum insn_types i960_last_insn_type; ! 1453: ! 1454: /* Parse opcodes, and set the insn last insn type based on them. */ ! 1455: ! 1456: #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN) ! 1457: ! 1458: /* Table listing what rtl codes each predicate in i960.c will accept. */ ! 1459: ! 1460: #define PREDICATE_CODES \ ! 1461: {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \ ! 1462: LABEL_REF, SUBREG, REG, MEM}}, \ ! 1463: {"arith_operand", {SUBREG, REG, CONST_INT}}, \ ! 1464: {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \ ! 1465: {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \ ! 1466: {"literal", {CONST_INT}}, \ ! 1467: {"fp_literal_one", {CONST_DOUBLE}}, \ ! 1468: {"fp_literal_double", {CONST_DOUBLE}}, \ ! 1469: {"fp_literal", {CONST_DOUBLE}}, \ ! 1470: {"signed_literal", {CONST_INT}}, \ ! 1471: {"symbolic_memory_operand", {SUBREG, MEM}}, \ ! 1472: {"eq_or_neq", {EQ, NE}}, \ ! 1473: {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \ ! 1474: CONST_DOUBLE, CONST}}, \ ! 1475: {"power2_operand", {CONST_INT}}, ! 1476: ! 1477: /* Define functions in i960.c and used in insn-output.c. */ ! 1478: ! 1479: extern char *i960_output_ldconst (); ! 1480: extern char *i960_output_call_insn (); ! 1481: extern char *i960_output_ret_insn ();
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