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1.1 root 1: /* Definitions of target machine for GNU compiler, for Intel 80960
2: Copyright (C) 1992 Free Software Foundation, Inc.
3: Contributed by Steven McGeady, Intel Corp.
4: Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5: Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
6:
7: This file is part of GNU CC.
8:
9: GNU CC is free software; you can redistribute it and/or modify
10: it under the terms of the GNU General Public License as published by
11: the Free Software Foundation; either version 2, or (at your option)
12: any later version.
13:
14: GNU CC is distributed in the hope that it will be useful,
15: but WITHOUT ANY WARRANTY; without even the implied warranty of
16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17: GNU General Public License for more details.
18:
19: You should have received a copy of the GNU General Public License
20: along with GNU CC; see the file COPYING. If not, write to
21: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22:
23: /* Note that some other tm.h files may include this one and then override
24: many of the definitions that relate to assembler syntax. */
25:
26: /* Names to predefine in the preprocessor for this target machine. */
27: #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960"
28:
29: /* Name to predefine in the preprocessor for processor variations. */
30: #define CPP_SPEC "%{mic*:-D__i960\
31: %{mka:-D__i960KA}%{mkb:-D__i960KB}%{mkc:-D__i960KC}\
32: %{msa:-D__i960SA}%{msb:-D__i960SB}%{msc:-D__i960SC}\
33: %{mmc:-D__i960MC}\
34: %{mca:-D__i960CA}%{mcb:-D__i960CB}%{mcc:-D__i960CC}\
35: %{mcf:-D__i960CF}}\
36: %{mka:-D__i960KA__ -D__i960_KA__}\
37: %{mkb:-D__i960KB__ -D__i960_KB__}\
38: %{mkc:-D__i960KC__ -D__i960_KC__}\
39: %{msa:-D__i960SA__ -D__i960_SA__}\
40: %{msb:-D__i960SB__ -D__i960_SB__}\
41: %{msc:-D__i960SC__ -D__i960_SC__}\
42: %{mmc:-D__i960MC__ -D__i960_MC__}\
43: %{mca:-D__i960CA__ -D__i960_CA__}\
44: %{mcb:-D__i960CB__ -D__i960_CB__}\
45: %{mcc:-D__i960CC__ -D__i960_CC__}\
46: %{mcf:-D__i960CF__ -D__i960_CF__}\
47: %{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\
48: %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}}}}"
49:
50: /* -mic* options make characters signed by default. */
51: #define SIGNED_CHAR_SPEC \
52: (DEFAULT_SIGNED_CHAR ? "%{funsigned-char:-D__CHAR_UNSIGNED__}" \
53: : "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}")
54:
55: /* Specs for the compiler, to handle processor variations. */
56: #define CC1_SPEC \
57: "%{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\
58: %{!mcc:%{!mcf:-mkb}}}}}}}}}}}\
59: %{mbout:%{g*:-gstabs}}\
60: %{mcoff:%{g*:-gcoff}}\
61: %{!mbout:%{!mcoff:%{g*:-gstabs}}}"
62:
63: /* Specs for the assembler, to handle processor variations.
64: For compatibility with Intel's gnu960 tool chain, pass -A options to
65: the assembler. */
66: #define ASM_SPEC \
67: "%{mka:-AKA}%{mkb:-AKB}%{mkc:-AKC}%{msa:-ASA}%{msb:-ASB}\
68: %{msc:-ASC}%{mmc:-AMC}%{mca:-ACA}%{mcb:-ACB}%{mcc:-ACC}%{mcf:-ACF}\
69: %{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\
70: %{!mcc:%{!mcf:-AKB}}}}}}}}}}}"
71:
72: /* Specs for the linker, to handle processor variations.
73: For compatibility with Intel's gnu960 tool chain, pass -F and -A options
74: to the linker. */
75: #define LINK_SPEC \
76: "%{mka:-AKA}%{mkb:-AKB}%{mkc:-AKC}%{msa:-ASA}%{msb:-ASB}\
77: %{msc:-ASC}%{mmc:-AMC}%{mca:-ACA}%{mcb:-ACB}%{mcc:-ACC}%{mcf:-ACF}\
78: %{!mka:%{!mkb:%{!mkc:%{!msa:%{!msb:%{!msc:%{!mmc:%{!mca:%{!mcb:\
79: %{!mcc:%{!mcf:-AKB}}}}}}}}}}}\
80: %{mbout:-Fbout}%{mcoff:-Fcoff}"
81:
82: /* Specs for the libraries to link with, to handle processor variations.
83: Compatible with Intel's gnu960 tool chain. */
84: #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
85: %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"
86:
87: /* Omit frame pointer at -O2. Inline functions at -O3. */
88: #define OPTIMIZATION_OPTIONS(LEVEL) \
89: { \
90: if ((LEVEL) >= 2) \
91: { \
92: flag_omit_frame_pointer = 1; \
93: target_flags |= TARGET_FLAG_LEAFPROC; \
94: target_flags |= TARGET_FLAG_TAILCALL; \
95: } \
96: if ((LEVEL) >= 3) \
97: flag_inline_functions = 1; \
98: }
99:
100: /* Print subsidiary information on the compiler version in use. */
101: #define TARGET_VERSION fprintf (stderr," (intel 80960)");
102:
103: /* Generate DBX debugging information. */
104: #define DBX_DEBUGGING_INFO
105:
106: /* Generate SDB style debugging information. */
107: #define SDB_DEBUGGING_INFO
108:
109: /* Generate DBX_DEBUGGING_INFO by default. */
110: #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
111:
112: /* Redefine this to print in hex like iC960. */
113: #define PUT_SDB_TYPE(A) fprintf (asm_out_file, "\t.type\t0x%x;", A)
114:
115: /* Run-time compilation parameters selecting different hardware subsets. */
116:
117: /* 960 architecture with floating-point. */
118: #define TARGET_FLAG_NUMERICS 0x01
119: #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS)
120:
121: /* 960 architecture with memory management. */
122: /* ??? Not used currently. */
123: #define TARGET_FLAG_PROTECTED 0x02
124: #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED)
125:
126: /* The following three are mainly used to provide a little sanity checking
127: against the -mARCH flags given. */
128:
129: /* Nonzero if we should generate code for the KA and similar processors.
130: No FPU, no microcode instructions. */
131: #define TARGET_FLAG_K_SERIES 0x04
132: #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES)
133:
134: /* Nonzero if we should generate code for the MC processor.
135: Not really different from KB for our purposes. */
136: #define TARGET_FLAG_MC 0x08
137: #define TARGET_MC (target_flags & TARGET_FLAG_MC)
138:
139: /* Nonzero if we should generate code for the CA processor.
140: Enables different optimization strategies. */
141: #define TARGET_FLAG_C_SERIES 0x10
142: #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES)
143:
144: /* Nonzero if we should generate leaf-procedures when we find them.
145: You may not want to do this because leaf-proc entries are
146: slower when not entered via BAL - this would be true when
147: a linker not supporting the optimization is used. */
148: #define TARGET_FLAG_LEAFPROC 0x20
149: #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC)
150:
151: /* Nonzero if we should perform tail-call optimizations when we find them.
152: You may not want to do this because the detection of cases where
153: this is not valid is not totally complete. */
154: #define TARGET_FLAG_TAILCALL 0x40
155: #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL)
156:
157: /* Nonzero if use of a complex addressing mode is a win on this implementation.
158: Complex addressing modes are probably not worthwhile on the K-series,
159: but they definitely are on the C-series. */
160: #define TARGET_FLAG_COMPLEX_ADDR 0x80
161: #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR)
162:
163: /* Align code to 8 byte boundaries for faster fetching. */
164: #define TARGET_FLAG_CODE_ALIGN 0x100
165: #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN)
166:
167: /* Append branch prediction suffixes to branch opcodes. */
168: /* ??? Not used currently. */
169: #define TARGET_FLAG_BRANCH_PREDICT 0x200
170: #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT)
171:
172: /* Forces prototype and return promotions. */
173: /* ??? This does not work. */
174: #define TARGET_FLAG_CLEAN_LINKAGE 0x400
175: #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE)
176:
177: /* For compatibility with iC960 v3.0. */
178: #define TARGET_FLAG_IC_COMPAT3_0 0x800
179: #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0)
180:
181: /* For compatibility with iC960 v2.0. */
182: #define TARGET_FLAG_IC_COMPAT2_0 0x1000
183: #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0)
184:
185: /* If no unaligned accesses are to be permitted. */
186: #define TARGET_FLAG_STRICT_ALIGN 0x2000
187: #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN)
188:
189: /* For compatibility with iC960 assembler. */
190: #define TARGET_FLAG_ASM_COMPAT 0x4000
191: #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT)
192:
193: /* For compatibility with the gcc960 v1.2 compiler. Use the old structure
194: alignement rules. Also, turns on STRICT_ALIGNMENT. */
195: #define TARGET_FLAG_OLD_ALIGN 0x8000
196: #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN)
197:
198: extern int target_flags;
199:
200: /* Macro to define tables used to set the flags.
201: This is a list in braces of pairs in braces,
202: each pair being { "NAME", VALUE }
203: where VALUE is the bits to set or minus the bits to clear.
204: An empty string NAME is used to identify the default VALUE. */
205:
206: /* ??? Not all ten of these architecture variations actually exist, but I
207: am not sure which are real and which aren't. */
208:
209: #define TARGET_SWITCHES \
210: { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
211: {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
212: TARGET_FLAG_COMPLEX_ADDR)},\
213: {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
214: TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\
215: {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
216: {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
217: TARGET_FLAG_COMPLEX_ADDR)},\
218: {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
219: TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\
220: {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
221: TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\
222: {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
223: TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
224: {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\
225: TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\
226: {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
227: TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
228: TARGET_FLAG_CODE_ALIGN)}, \
229: {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
230: TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
231: {"numerics", (TARGET_FLAG_NUMERICS)}, \
232: {"soft-float", -(TARGET_FLAG_NUMERICS)}, \
233: {"leaf-procedures", TARGET_FLAG_LEAFPROC}, \
234: {"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)}, \
235: {"tail-call",TARGET_FLAG_TAILCALL}, \
236: {"no-tail-call",-(TARGET_FLAG_TAILCALL)}, \
237: {"complex-addr",TARGET_FLAG_COMPLEX_ADDR}, \
238: {"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)}, \
239: {"code-align",TARGET_FLAG_CODE_ALIGN}, \
240: {"no-code-align",-(TARGET_FLAG_CODE_ALIGN)}, \
241: {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)}, \
242: {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)}, \
243: {"ic-compat", TARGET_FLAG_IC_COMPAT2_0}, \
244: {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0}, \
245: {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0}, \
246: {"asm-compat",TARGET_FLAG_ASM_COMPAT}, \
247: {"intel-asm",TARGET_FLAG_ASM_COMPAT}, \
248: {"strict-align", TARGET_FLAG_STRICT_ALIGN}, \
249: {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)}, \
250: {"old-align", TARGET_FLAG_OLD_ALIGN}, \
251: {"no-old-align", -(TARGET_FLAG_OLD_ALIGN)}, \
252: { "", TARGET_DEFAULT}}
253:
254: /* Override conflicting target switch options.
255: Doesn't actually detect if more than one -mARCH option is given, but
256: does handle the case of two blatantly conflicting -mARCH options. */
257: #define OVERRIDE_OPTIONS \
258: { \
259: if (TARGET_K_SERIES && TARGET_C_SERIES) \
260: { \
261: warning ("conflicting architectures defined - using C series", 0); \
262: target_flags &= ~TARGET_FLAG_K_SERIES; \
263: } \
264: if (TARGET_K_SERIES && TARGET_MC) \
265: { \
266: warning ("conflicting architectures defined - using K series", 0); \
267: target_flags &= ~TARGET_FLAG_MC; \
268: } \
269: if (TARGET_C_SERIES && TARGET_MC) \
270: { \
271: warning ("conflicting architectures defined - using C series", 0);\
272: target_flags &= ~TARGET_FLAG_MC; \
273: } \
274: if (TARGET_IC_COMPAT3_0) \
275: { \
276: flag_short_enums = 1; \
277: flag_signed_char = 1; \
278: target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
279: if (TARGET_IC_COMPAT2_0) \
280: { \
281: warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \
282: target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \
283: } \
284: } \
285: if (TARGET_IC_COMPAT2_0) \
286: { \
287: flag_signed_char = 1; \
288: target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
289: } \
290: i960_initialize (); \
291: }
292:
293: /* Don't enable anything by default. The user is expected to supply a -mARCH
294: option. If none is given, then -mkb is added by CC1_SPEC. */
295: #define TARGET_DEFAULT 0
296:
297: /* Target machine storage layout. */
298:
299: /* Define this if most significant bit is lowest numbered
300: in instructions that operate on numbered bit-fields. */
301: #define BITS_BIG_ENDIAN 0
302:
303: /* Define this if most significant byte of a word is the lowest numbered.
304: The i960 case be either big endian or little endian. We only support
305: little endian, which is the most common. */
306: #define BYTES_BIG_ENDIAN 0
307:
308: /* Define this if most significant word of a multiword number is lowest
309: numbered. */
310: #define WORDS_BIG_ENDIAN 0
311:
312: /* Number of bits in an addressible storage unit. */
313: #define BITS_PER_UNIT 8
314:
315: /* Bitfields cannot cross word boundaries. */
316: #define BITFIELD_NBYTES_LIMITED 1
317:
318: /* Width in bits of a "word", which is the contents of a machine register.
319: Note that this is not necessarily the width of data type `int';
320: if using 16-bit ints on a 68000, this would still be 32.
321: But on a machine with 16-bit registers, this would be 16. */
322: #define BITS_PER_WORD 32
323:
324: /* Width of a word, in units (bytes). */
325: #define UNITS_PER_WORD 4
326:
327: /* Width in bits of a pointer. See also the macro `Pmode' defined below. */
328: #define POINTER_SIZE 32
329:
330: /* Width in bits of a long double. Identical to double for now. */
331: #define LONG_DOUBLE_TYPE_SIZE 64
332:
333: /* Allocation boundary (in *bits*) for storing pointers in memory. */
334: #define POINTER_BOUNDARY 32
335:
336: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
337: #define PARM_BOUNDARY 32
338:
339: /* Boundary (in *bits*) on which stack pointer should be aligned. */
340: #define STACK_BOUNDARY 128
341:
342: /* Allocation boundary (in *bits*) for the code of a function. */
343: #define FUNCTION_BOUNDARY 128
344:
345: /* Alignment of field after `int : 0' in a structure. */
346: #define EMPTY_FIELD_BOUNDARY 32
347:
348: /* This makes zero-length anonymous fields lay the next field
349: at a word boundary. It also makes the whole struct have
350: at least word alignment if there are any bitfields at all. */
351: #define PCC_BITFIELD_TYPE_MATTERS 1
352:
353: /* Every structure's size must be a multiple of this. */
354: #define STRUCTURE_SIZE_BOUNDARY 8
355:
356: /* No data type wants to be aligned rounder than this.
357: Extended precision floats gets 4-word alignment. */
358: #define BIGGEST_ALIGNMENT 128
359:
360: /* Define this if move instructions will actually fail to work
361: when given unaligned data.
362: 80960 will work even with unaligned data, but it is slow. */
363: #define STRICT_ALIGNMENT TARGET_OLD_ALIGN
364:
365: /* Specify alignment for string literals (which might be higher than the
366: base type's minimnal alignment requirement. This allows strings to be
367: aligned on word boundaries, and optimizes calls to the str* and mem*
368: library functions. */
369: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
370: (i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \
371: ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \
372: : (ALIGN))
373:
374: /* Macros to determine size of aggregates (structures and unions
375: in C). Normally, these may be defined to simply return the maximum
376: alignment and simple rounded-up size, but on some machines (like
377: the i960), the total size of a structure is based on a non-trivial
378: rounding method. */
379:
380: #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \
381: ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \
382: ? i960_round_align ((SPECIFIED), TYPE_SIZE (TYPE)) \
383: : MAX ((COMPUTED), (SPECIFIED)))
384:
385: #define ROUND_TYPE_SIZE(TYPE, SIZE, ALIGN) \
386: ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \
387: ? (tree) i960_round_size (SIZE) \
388: : round_up ((SIZE), (ALIGN)))
389:
390: /* Standard register usage. */
391:
392: /* Number of actual hardware registers.
393: The hardware registers are assigned numbers for the compiler
394: from 0 to just below FIRST_PSEUDO_REGISTER.
395: All registers that the compiler knows about must be given numbers,
396: even those that are not normally considered general registers.
397:
398: Registers 0-15 are the global registers (g0-g15).
399: Registers 16-31 are the local registers (r0-r15).
400: Register 32-35 are the fp registers (fp0-fp3).
401: Register 36 is the condition code register.
402: Register 37 is unused. */
403:
404: #define FIRST_PSEUDO_REGISTER 38
405:
406: /* 1 for registers that have pervasive standard uses and are not available
407: for the register allocator. On 80960, this includes the frame pointer
408: (g15), the previous FP (r0), the stack pointer (r1), the return
409: instruction pointer (r2), and the argument pointer (g14). */
410: #define FIXED_REGISTERS \
411: {0, 0, 0, 0, 0, 0, 0, 0, \
412: 0, 0, 0, 0, 0, 0, 1, 1, \
413: 1, 1, 1, 0, 0, 0, 0, 0, \
414: 0, 0, 0, 0, 0, 0, 0, 0, \
415: 0, 0, 0, 0, 1, 1}
416:
417: /* 1 for registers not available across function calls.
418: These must include the FIXED_REGISTERS and also any
419: registers that can be used without being saved.
420: The latter must include the registers where values are returned
421: and the register where structure-value addresses are passed.
422: Aside from that, you can include as many other registers as you like. */
423:
424: /* On the 80960, note that:
425: g0..g3 are used for return values,
426: g0..g7 may always be used for parameters,
427: g8..g11 may be used for parameters, but are preserved if they aren't,
428: g12 is always preserved, but otherwise unused,
429: g13 is the struct return ptr if used, or temp, but may be trashed,
430: g14 is the leaf return ptr or the arg block ptr otherwise zero,
431: must be reset to zero before returning if it was used,
432: g15 is the frame pointer,
433: r0 is the previous FP,
434: r1 is the stack pointer,
435: r2 is the return instruction pointer,
436: r3-r15 are always available,
437: fp0..fp3 are never available. */
438: #define CALL_USED_REGISTERS \
439: {1, 1, 1, 1, 1, 1, 1, 1, \
440: 0, 0, 0, 0, 0, 1, 1, 1, \
441: 1, 1, 1, 0, 0, 0, 0, 0, \
442: 0, 0, 0, 0, 0, 0, 0, 0, \
443: 1, 1, 1, 1, 1, 1}
444:
445: /* If no fp unit, make all of the fp registers fixed so that they can't
446: be used. */
447: #define CONDITIONAL_REGISTER_USAGE \
448: if (! TARGET_NUMERICS) { \
449: fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\
450: } \
451:
452: /* Return number of consecutive hard regs needed starting at reg REGNO
453: to hold something of mode MODE.
454: This is ordinarily the length in words of a value of mode MODE
455: but can be less for certain modes in special long registers.
456:
457: On 80960, ordinary registers hold 32 bits worth, but can be ganged
458: together to hold double or extended precision floating point numbers,
459: and the floating point registers hold any size floating point number */
460: #define HARD_REGNO_NREGS(REGNO, MODE) \
461: ((REGNO) < 32 \
462: ? (((MODE) == VOIDmode) \
463: ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
464: : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0)
465:
466: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
467: On 80960, the cpu registers can hold any mode but the float registers
468: can only hold SFmode, DFmode, or TFmode. */
469: extern unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
470: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
471: ((hard_regno_mode_ok[REGNO] & (1 << (int) (MODE))) != 0)
472:
473: /* Value is 1 if it is a good idea to tie two pseudo registers
474: when one has mode MODE1 and one has mode MODE2.
475: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
476: for any hard reg, then this must be 0 for correct output. */
477:
478: #define MODES_TIEABLE_P(MODE1, MODE2) \
479: ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
480:
481: /* Specify the registers used for certain standard purposes.
482: The values of these macros are register numbers. */
483:
484: /* 80960 pc isn't overloaded on a register that the compiler knows about. */
485: /* #define PC_REGNUM */
486:
487: /* Register to use for pushing function arguments. */
488: #define STACK_POINTER_REGNUM 17
489:
490: /* Actual top-of-stack address is same as
491: the contents of the stack pointer register. */
492: #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size)
493:
494: /* Base register for access to local variables of the function. */
495: #define FRAME_POINTER_REGNUM 15
496:
497: /* Value should be nonzero if functions must have frame pointers.
498: Zero means the frame pointer need not be set up (and parms
499: may be accessed via the stack pointer) in functions that seem suitable.
500: This is computed in `reload', in reload1.c. */
501: #define FRAME_POINTER_REQUIRED (! leaf_function_p ())
502:
503: /* C statement to store the difference between the frame pointer
504: and the stack pointer values immediately after the function prologue. */
505:
506: #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
507: do { (VAR) = compute_frame_size (get_frame_size ()); } while (0)
508:
509: /* Base register for access to arguments of the function. */
510: #define ARG_POINTER_REGNUM 14
511:
512: /* Register in which static-chain is passed to a function.
513: On i960, we use r3. */
514: #define STATIC_CHAIN_REGNUM 19
515:
516: /* Functions which return large structures get the address
517: to place the wanted value at in g13. */
518:
519: #define STRUCT_VALUE_REGNUM 13
520:
521: /* The order in which to allocate registers. */
522:
523: #define REG_ALLOC_ORDER \
524: { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \
525: 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \
526: 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \
527: 11, 12, /* g11, g12 */ \
528: 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \
529: /* We can't actually allocate these. */ \
530: 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */
531:
532: /* Define the classes of registers for register constraints in the
533: machine description. Also define ranges of constants.
534:
535: One of the classes must always be named ALL_REGS and include all hard regs.
536: If there is more than one class, another class must be named NO_REGS
537: and contain no registers.
538:
539: The name GENERAL_REGS must be the name of a class (or an alias for
540: another name such as ALL_REGS). This is the class of registers
541: that is allowed by "g" or "r" in a register constraint.
542: Also, registers outside this class are allocated only when
543: instructions express preferences for them.
544:
545: The classes must be numbered in nondecreasing order; that is,
546: a larger-numbered class must never be contained completely
547: in a smaller-numbered class.
548:
549: For any two classes, it is very desirable that there be another
550: class that represents their union. */
551:
552: /* The 80960 has four kinds of registers, global, local, floating point,
553: and condition code. The cc register is never allocated, so no class
554: needs to be defined for it. */
555:
556: enum reg_class { NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS,
557: FP_REGS, ALL_REGS, LIM_REG_CLASSES };
558:
559: /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never
560: does. */
561: #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS)
562:
563: #define N_REG_CLASSES (int) LIM_REG_CLASSES
564:
565: /* Give names of register classes as strings for dump file. */
566:
567: #define REG_CLASS_NAMES \
568: { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \
569: "FP_REGS", "ALL_REGS" }
570:
571: /* Define which registers fit in which classes.
572: This is an initializer for a vector of HARD_REG_SET
573: of length N_REG_CLASSES. */
574:
575: #define REG_CLASS_CONTENTS \
576: { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}}
577:
578: /* The same information, inverted:
579: Return the class number of the smallest class containing
580: reg number REGNO. This could be a conditional expression
581: or could index an array. */
582:
583: #define REGNO_REG_CLASS(REGNO) \
584: ((REGNO) < 16 ? GLOBAL_REGS \
585: : (REGNO) < 32 ? LOCAL_REGS \
586: : (REGNO) < 36 ? FP_REGS \
587: : NO_REGS)
588:
589: /* The class value for index registers, and the one for base regs.
590: There is currently no difference between base and index registers on the
591: i960, but this distinction may one day be useful. */
592: #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS
593: #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS
594:
595: /* Get reg_class from a letter such as appears in the machine description.
596: 'f' is a floating point register (fp0..fp3)
597: 'l' is a local register (r0-r15)
598: 'b' is a global register (g0-g15)
599: 'd' is any local or global register
600: 'r' or 'g' are pre-defined to the class GENERAL_REGS. */
601: /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not*
602: the same thing, since 'r' may include the fp registers. */
603: #define REG_CLASS_FROM_LETTER(C) \
604: (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \
605: (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS)))
606:
607: /* The letters I, J, K, L and M in a register constraint string
608: can be used to stand for particular ranges of immediate operands.
609: This macro defines what the ranges are.
610: C is the letter, and VALUE is a constant value.
611: Return 1 if VALUE is in the range specified by C.
612:
613: For 80960:
614: 'I' is used for literal values 0..31
615: 'J' means literal 0
616: 'K' means 0..-31. */
617:
618: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
619: ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \
620: : (C) == 'J' ? ((VALUE) == 0) \
621: : (C) == 'K' ? ((VALUE) > -32 && (VALUE) <= 0) \
622: : 0)
623:
624: /* Similar, but for floating constants, and defining letters G and H.
625: Here VALUE is the CONST_DOUBLE rtx itself.
626: For the 80960, G is 0.0 and H is 1.0. */
627:
628: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
629: ((TARGET_NUMERICS) && \
630: (((C) == 'G' && ((VALUE) == CONST0_RTX (DFmode) \
631: || (VALUE) == CONST0_RTX (SFmode))) \
632: || ((C) == 'H' && ((VALUE) == CONST1_RTX (DFmode) \
633: || (VALUE) == CONST1_RTX (SFmode)))))
634:
635: /* Given an rtx X being reloaded into a reg required to be
636: in class CLASS, return the class of reg to actually use.
637: In general this is just CLASS; but on some machines
638: in some cases it is preferable to use a more restrictive class. */
639:
640: /* On 960, can't load constant into floating-point reg except
641: 0.0 or 1.0.
642:
643: Any hard reg is ok as a src operand of a reload insn. */
644:
645: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
646: (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \
647: ? (CLASS) \
648: : ((CLASS) == FP_REGS && CONSTANT_P (X) \
649: && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\
650: && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\
651: ? NO_REGS \
652: : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS)))
653:
654: #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
655: secondary_reload_class (CLASS, MODE, IN)
656:
657: /* Return the maximum number of consecutive registers
658: needed to represent mode MODE in a register of class CLASS. */
659: /* On 80960, this is the size of MODE in words,
660: except in the FP regs, where a single reg is always enough. */
661: #define CLASS_MAX_NREGS(CLASS, MODE) \
662: ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE)))
663:
664: /* Stack layout; function entry, exit and calling. */
665:
666: /* Define this if pushing a word on the stack
667: makes the stack pointer a smaller address. */
668: /* #define STACK_GROWS_DOWNWARD */
669:
670: /* Define this if the nominal address of the stack frame
671: is at the high-address end of the local variables;
672: that is, each additional local variable allocated
673: goes at a more negative offset in the frame. */
674: /* #define FRAME_GROWS_DOWNWARD */
675:
676: /* Offset within stack frame to start allocating local variables at.
677: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
678: first local allocated. Otherwise, it is the offset to the BEGINNING
679: of the first local allocated.
680:
681: The i960 has a 64 byte register save area, plus possibly some extra
682: bytes allocated for varargs functions. */
683: #define STARTING_FRAME_OFFSET 64
684:
685: /* If we generate an insn to push BYTES bytes,
686: this says how many the stack pointer really advances by.
687: On 80960, don't define this because there are no push insns. */
688: /* #define PUSH_ROUNDING(BYTES) BYTES */
689:
690: /* Offset of first parameter from the argument pointer register value. */
691: #define FIRST_PARM_OFFSET(FNDECL) 0
692:
693: /* When a parameter is passed in a register, no stack space is
694: allocated for it. However, when args are passed in the
695: stack, space is allocated for every register parameter. */
696: #define MAYBE_REG_PARM_STACK_SPACE 48
697: #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \
698: i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE);
699: #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL)
700: #define OUTGOING_REG_PARM_STACK_SPACE
701:
702: /* Keep the stack pointer constant throughout the function. */
703: #define ACCUMULATE_OUTGOING_ARGS
704:
705: /* Value is 1 if returning from a function call automatically
706: pops the arguments described by the number-of-args field in the call.
707: FUNTYPE is the data type of the function (as a tree),
708: or for a library call it is an identifier node for the subroutine name. */
709:
710: #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
711:
712: /* Define how to find the value returned by a library function
713: assuming the value has mode MODE. */
714:
715: #define LIBCALL_VALUE(MODE) gen_rtx ((REG), (MODE), 0)
716:
717: /* 1 if N is a possible register number for a function value
718: as seen by the caller.
719: On 80960, returns are in g0..g3 */
720:
721: #define FUNCTION_VALUE_REGNO_P(N) ((N) < 4)
722:
723: /* 1 if N is a possible register number for function argument passing.
724: On 80960, parameters are passed in g0..g11 */
725:
726: #define FUNCTION_ARG_REGNO_P(N) ((N) < 12)
727:
728: /* Perform any needed actions needed for a function that is receiving a
729: variable number of arguments.
730:
731: CUM is as above.
732:
733: MODE and TYPE are the mode and type of the current parameter.
734:
735: PRETEND_SIZE is a variable that should be set to the amount of stack
736: that must be pushed by the prolog to pretend that our caller pushed
737: it.
738:
739: Normally, this macro will push all remaining incoming registers on the
740: stack and set PRETEND_SIZE to the length of the registers pushed. */
741:
742: #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
743: i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL)
744:
745: /* Define a data type for recording info about an argument list
746: during the scan of that argument list. This data type should
747: hold all necessary information about the function itself
748: and about the args processed so far, enough to enable macros
749: such as FUNCTION_ARG to determine where the next arg should go.
750:
751: On 80960, this is two integers, which count the number of register
752: parameters and the number of stack parameters seen so far. */
753:
754: struct cum_args { int ca_nregparms; int ca_nstackparms; };
755:
756: #define CUMULATIVE_ARGS struct cum_args
757:
758: /* Define the number of registers that can hold parameters.
759: This macro is used only in macro definitions below and/or i960.c. */
760: #define NPARM_REGS 12
761:
762: /* Define how to round to the next parameter boundary.
763: This macro is used only in macro definitions below and/or i960.c. */
764: #define ROUND(X, MULTIPLE_OF) \
765: ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF)
766:
767: /* Initialize a variable CUM of type CUMULATIVE_ARGS
768: for a call to a function whose data type is FNTYPE.
769: For a library call, FNTYPE is 0.
770:
771: On 80960, the offset always starts at 0; the first parm reg is g0. */
772:
773: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
774: ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0)
775:
776: /* Update the data in CUM to advance over an argument
777: of mode MODE and data type TYPE.
778: CUM should be advanced to align with the data type accessed and
779: also the size of that data type in # of regs.
780: (TYPE is null for libcalls where that information may not be available.) */
781:
782: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
783: i960_function_arg_advance(&CUM, MODE, TYPE, NAMED)
784:
785: /* Indicate the alignment boundary for an argument of the specified mode and
786: type. */
787: #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
788: (((TYPE) != 0) \
789: ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \
790: ? PARM_BOUNDARY \
791: : TYPE_ALIGN (TYPE)) \
792: : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \
793: ? PARM_BOUNDARY \
794: : GET_MODE_ALIGNMENT (MODE)))
795:
796: /* Determine where to put an argument to a function.
797: Value is zero to push the argument on the stack,
798: or a hard register in which to store the argument.
799:
800: MODE is the argument's machine mode.
801: TYPE is the data type of the argument (as a tree).
802: This is null for libcalls where that information may
803: not be available.
804: CUM is a variable of type CUMULATIVE_ARGS which gives info about
805: the preceding args and about the function being called.
806: NAMED is nonzero if this argument is a named parameter
807: (otherwise it is an extra parameter matching an ellipsis). */
808:
809: extern struct rtx_def *i960_function_arg ();
810: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
811: i960_function_arg(&CUM, MODE, TYPE, NAMED)
812:
813: /* Define how to find the value returned by a function.
814: VALTYPE is the data type of the value (as a tree).
815: If the precise function being called is known, FUNC is its FUNCTION_DECL;
816: otherwise, FUNC is 0. */
817:
1.1.1.2 ! root 818: #define FUNCTION_VALUE(TYPE, FUNC) \
! 819: gen_rtx (REG, TYPE_MODE (TYPE), 0)
1.1 root 820:
821: /* Force objects larger than 16 bytes to be returned in memory, since we
822: only have 4 registers available for return values. */
823:
824: #define RETURN_IN_MEMORY(TYPE) (int_size_in_bytes (TYPE) > 16)
825:
826: /* For an arg passed partly in registers and partly in memory,
827: this is the number of registers used.
828: This never happens on 80960. */
829:
830: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
831:
832: /* Output the label for a function definition.
833: This handles leaf functions and a few other things for the i960. */
834:
835: #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
836: i960_function_name_declare (FILE, NAME, DECL)
837:
838: /* This macro generates the assembly code for function entry.
839: FILE is a stdio stream to output the code to.
840: SIZE is an int: how many units of temporary storage to allocate.
841: Refer to the array `regs_ever_live' to determine which registers
842: to save; `regs_ever_live[I]' is nonzero if register number I
843: is ever used in the function. This macro is responsible for
844: knowing which registers should not be saved even if used. */
845:
846: #define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE))
847:
848: /* Output assembler code to FILE to increment profiler label # LABELNO
849: for profiling a function entry. */
850:
851: #define FUNCTION_PROFILER(FILE, LABELNO) \
852: fprintf (FILE, "\tlda LP%d,g0\n\tbal mcount\n", (LABELNO))
853:
854: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
855: the stack pointer does not matter. The value is tested only in
856: functions that have frame pointers.
857: No definition is equivalent to always zero. */
858:
859: #define EXIT_IGNORE_STACK 1
860:
861: /* This macro generates the assembly code for function exit,
862: on machines that need it. If FUNCTION_EPILOGUE is not defined
863: then individual return instructions are generated for each
864: return statement. Args are same as for FUNCTION_PROLOGUE.
865:
866: The function epilogue should not depend on the current stack pointer!
867: It should use the frame pointer only. This is mandatory because
868: of alloca; we also take advantage of it to omit stack adjustments
869: before returning. */
870:
871: #define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE)
872:
873: /* Addressing modes, and classification of registers for them. */
874:
875: /* #define HAVE_POST_INCREMENT */
876: /* #define HAVE_POST_DECREMENT */
877:
878: /* #define HAVE_PRE_DECREMENT */
879: /* #define HAVE_PRE_INCREMENT */
880:
881: /* Macros to check register numbers against specific register classes. */
882:
883: /* These assume that REGNO is a hard or pseudo reg number.
884: They give nonzero only if REGNO is a hard reg of the suitable class
885: or a pseudo reg currently allocated to a suitable hard reg.
886: Since they use reg_renumber, they are safe only once reg_renumber
887: has been allocated, which happens in local-alloc.c. */
888:
889: #define REGNO_OK_FOR_INDEX_P(REGNO) \
890: ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
891: #define REGNO_OK_FOR_BASE_P(REGNO) \
892: ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
893: #define REGNO_OK_FOR_FP_P(REGNO) \
894: ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36)
895:
896: /* Now macros that check whether X is a register and also,
897: strictly, whether it is in a specified class.
898:
899: These macros are specific to the 960, and may be used only
900: in code for printing assembler insns and in conditions for
901: define_optimization. */
902:
903: /* 1 if X is an fp register. */
904:
905: #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36)
906:
907: /* Maximum number of registers that can appear in a valid memory address. */
908: #define MAX_REGS_PER_ADDRESS 2
909:
910: #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
911:
912: /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X
913: is a legitimate general operand.
914: It is given that X satisfies CONSTANT_P.
915:
916: Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0. */
917:
918: #define LEGITIMATE_CONSTANT_P(X) \
919: ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), VOIDmode))
920:
921: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
922: and check its validity for a certain class.
923: We have two alternate definitions for each of them.
924: The usual definition accepts all pseudo regs; the other rejects
925: them unless they have been allocated suitable hard regs.
926: The symbol REG_OK_STRICT causes the latter definition to be used.
927:
928: Most source files want to accept pseudo regs in the hope that
929: they will get allocated to the class that the insn wants them to be in.
930: Source files for reload pass need to be strict.
931: After reload, it makes no difference, since pseudo regs have
932: been eliminated by then. */
933:
934: #ifndef REG_OK_STRICT
935:
936: /* Nonzero if X is a hard reg that can be used as an index
937: or if it is a pseudo reg. */
938: #define REG_OK_FOR_INDEX_P(X) \
939: (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
940: /* Nonzero if X is a hard reg that can be used as a base reg
941: or if it is a pseudo reg. */
942: #define REG_OK_FOR_BASE_P(X) \
943: (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
944:
945: #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
946: #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
947:
948: #else
949:
950: /* Nonzero if X is a hard reg that can be used as an index. */
951: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
952: /* Nonzero if X is a hard reg that can be used as a base reg. */
953: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
954:
955: #endif
956:
957: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
958: that is a valid memory address for an instruction.
959: The MODE argument is the machine mode for the MEM expression
960: that wants to use this address.
961:
962: On 80960, legitimate addresses are:
963: base ld (g0),r0
964: disp (12 or 32 bit) ld foo,r0
965: base + index ld (g0)[g1*1],r0
966: base + displ ld 0xf00(g0),r0
967: base + index*scale + displ ld 0xf00(g0)[g1*4],r0
968: index*scale + base ld (g0)[g1*4],r0
969: index*scale + displ ld 0xf00[g1*4],r0
970: index*scale ld [g1*4],r0
971: index + base + displ ld 0xf00(g0)[g1*1],r0
972:
973: In each case, scale can be 1, 2, 4, 8, or 16. */
974:
975: /* Returns 1 if the scale factor of an index term is valid. */
976: #define SCALE_TERM_P(X) \
977: (GET_CODE (X) == CONST_INT \
978: && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \
979: || INTVAL(X) == 8 || INTVAL (X) == 16))
980:
981:
982: #ifdef REG_OK_STRICT
983: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
984: { if (legitimate_address_p (MODE, X, 1)) goto ADDR; }
985: #else
986: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
987: { if (legitimate_address_p (MODE, X, 0)) goto ADDR; }
988: #endif
989:
990: /* Try machine-dependent ways of modifying an illegitimate address
991: to be legitimate. If we find one, return the new, valid address.
992: This macro is used in only one place: `memory_address' in explow.c.
993:
994: OLDX is the address as it was before break_out_memory_refs was called.
995: In some cases it is useful to look at this to decide what needs to be done.
996:
997: MODE and WIN are passed so that this macro can use
998: GO_IF_LEGITIMATE_ADDRESS.
999:
1000: It is always safe for this macro to do nothing. It exists to recognize
1001: opportunities to optimize the output. */
1002:
1003: /* On 80960, convert non-cannonical addresses to canonical form. */
1004:
1005: extern struct rtx_def *legitimize_address ();
1006: #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1007: { rtx orig_x = (X); \
1008: (X) = legitimize_address (X, OLDX, MODE); \
1009: if ((X) != orig_x && memory_address_p (MODE, X)) \
1010: goto WIN; }
1011:
1012: /* Go to LABEL if ADDR (a legitimate address expression)
1013: has an effect that depends on the machine mode it is used for.
1014: On the 960 this is never true. */
1015:
1016: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1017:
1018: /* Specify the machine mode that this machine uses
1019: for the index in the tablejump instruction. */
1020: #define CASE_VECTOR_MODE SImode
1021:
1022: /* Define this if the tablejump instruction expects the table
1023: to contain offsets from the address of the table.
1024: Do not define this if the table should contain absolute addresses. */
1025: /* #define CASE_VECTOR_PC_RELATIVE */
1026:
1027: /* Specify the tree operation to be used to convert reals to integers. */
1028: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1029:
1030: /* This is the kind of divide that is easiest to do in the general case. */
1031: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1032:
1033: /* Define this as 1 if `char' should by default be signed; else as 0. */
1034: #define DEFAULT_SIGNED_CHAR 0
1035:
1036: /* Allow and ignore #sccs directives. */
1037: #define SCCS_DIRECTIVE
1038:
1039: /* Max number of bytes we can move from memory to memory
1040: in one reasonably fast instruction. */
1041: #define MOVE_MAX 16
1042:
1043: /* Define if normal loads of shorter-than-word items from memory clears
1044: the rest of the bigs in the register. */
1045: #define BYTE_LOADS_ZERO_EXTEND
1046:
1047: /* Nonzero if access to memory by bytes is no faster than for words.
1048: Defining this results in worse code on the i960. */
1049:
1050: #define SLOW_BYTE_ACCESS 0
1051:
1052: /* We assume that the store-condition-codes instructions store 0 for false
1053: and some other value for true. This is the value stored for true. */
1054:
1055: #define STORE_FLAG_VALUE 1
1056:
1057: /* Define if shifts truncate the shift count
1058: which implies one can omit a sign-extension or zero-extension
1059: of a shift count. */
1060: #define SHIFT_COUNT_TRUNCATED
1061:
1062: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1063: is done just by pretending it is already truncated. */
1064: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1065:
1066: /* Specify the machine mode that pointers have.
1067: After generation of rtl, the compiler makes no further distinction
1068: between pointers and any other objects of this machine mode. */
1069: #define Pmode SImode
1070:
1071: /* Specify the widest mode that BLKmode objects can be promoted to */
1072: #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1073:
1074: /* These global variables are used to pass information between
1075: cc setter and cc user at insn emit time. */
1076:
1077: extern struct rtx_def *i960_compare_op0, *i960_compare_op1;
1078:
1079: /* Define the function that build the compare insn for scc and bcc. */
1080:
1081: extern struct rtx_def *gen_compare_reg ();
1082:
1083: /* Add any extra modes needed to represent the condition code.
1084:
1085: Also, signed and unsigned comparisons are distinguished, as
1086: are operations which are compatible with chkbit insns. */
1087: #define EXTRA_CC_MODES CC_UNSmode, CC_CHKmode
1088:
1089: /* Define the names for the modes specified above. */
1090: #define EXTRA_CC_NAMES "CC_UNS", "CC_CHK"
1091:
1092: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1093: return the mode to be used for the comparison. For floating-point, CCFPmode
1094: should be used. CC_NOOVmode should be used when the first operand is a
1095: PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1096: needed. */
1.1.1.2 ! root 1097: #define SELECT_CC_MODE(OP,X,Y) select_cc_mode (OP, X,Y)
1.1 root 1098:
1099: /* A function address in a call instruction is a byte address
1100: (for indexing purposes) so give the MEM rtx a byte's mode. */
1101: #define FUNCTION_MODE SImode
1102:
1103: /* Define this if addresses of constant functions
1104: shouldn't be put through pseudo regs where they can be cse'd.
1105: Desirable on machines where ordinary constants are expensive
1106: but a CALL with constant address is cheap. */
1107: #define NO_FUNCTION_CSE
1108:
1109: /* Use memcpy, etc. instead of bcopy. */
1110:
1111: #ifndef WIND_RIVER
1112: #define TARGET_MEM_FUNCTIONS 1
1113: #endif
1114:
1115: /* Compute the cost of computing a constant rtl expression RTX
1116: whose rtx-code is CODE. The body of this macro is a portion
1117: of a switch statement. If the code is computed here,
1118: return it with a return statement. Otherwise, break from the switch. */
1119:
1120: /* Constants that can be (non-ldconst) insn operands are cost 0. Constants
1121: that can be non-ldconst operands in rare cases are cost 1. Other constants
1122: have higher costs. */
1123:
1124: #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1125: case CONST_INT: \
1126: if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \
1127: || power2_operand (RTX, VOIDmode)) \
1128: return 0; \
1129: else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \
1130: return 1; \
1131: case CONST: \
1132: case LABEL_REF: \
1133: case SYMBOL_REF: \
1134: return (TARGET_FLAG_C_SERIES ? 6 : 8); \
1135: case CONST_DOUBLE: \
1136: if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \
1137: || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\
1138: return 1; \
1139: return 12;
1140:
1141: /* The i960 offers addressing modes which are "as cheap as a register".
1142: See i960.c (or gcc.texinfo) for details. */
1143:
1144: #define ADDRESS_COST(RTX) \
1145: (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX))
1146:
1147: /* Control the assembler format that we output. */
1148:
1149: /* Output at beginning of assembler file. */
1150:
1151: #define ASM_FILE_START(file)
1152:
1153: /* Output to assembler file text saying following lines
1154: may contain character constants, extra white space, comments, etc. */
1155:
1156: #define ASM_APP_ON ""
1157:
1158: /* Output to assembler file text saying following lines
1159: no longer contain unusual constructs. */
1160:
1161: #define ASM_APP_OFF ""
1162:
1163: /* Output before read-only data. */
1164:
1165: #define TEXT_SECTION_ASM_OP ".text"
1166:
1167: /* Output before writable data. */
1168:
1169: #define DATA_SECTION_ASM_OP ".data"
1170:
1171: /* How to refer to registers in assembler output.
1172: This sequence is indexed by compiler's hard-register-number (see above). */
1173:
1174: #define REGISTER_NAMES { \
1175: "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
1176: "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \
1177: "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \
1178: "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1179: "fp0","fp1","fp2", "fp3", "cc", "fake" }
1180:
1181: /* How to renumber registers for dbx and gdb.
1182: In the 960 encoding, g0..g15 are registers 16..31. */
1183:
1184: #define DBX_REGISTER_NUMBER(REGNO) \
1185: (((REGNO) < 16) ? (REGNO) + 16 \
1186: : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16))
1187:
1188: /* Don't emit dbx records longer than this. This is an arbitrary value. */
1189: #define DBX_CONTIN_LENGTH 1500
1190:
1191: /* This is how to output a note to DBX telling it the line number
1192: to which the following sequence of instructions corresponds. */
1193:
1194: #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \
1195: { if (write_symbols == SDB_DEBUG) { \
1196: fprintf ((FILE), "\t.ln %d\n", \
1197: (sdb_begin_function_line \
1198: ? (LINE) - sdb_begin_function_line : 1)); \
1199: } else if (write_symbols == DBX_DEBUG) { \
1200: fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \
1201: } }
1202:
1203: /* This is how to output the definition of a user-level label named NAME,
1204: such as the label on a static function or variable NAME. */
1205:
1206: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1207: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1208:
1209: /* This is how to output a command to make the user-level label named NAME
1210: defined for reference from other files. */
1211:
1212: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1213: { fputs ("\t.globl ", FILE); \
1214: assemble_name (FILE, NAME); \
1215: fputs ("\n", FILE); }
1216:
1217: /* This is how to output a reference to a user-level label named NAME.
1218: `assemble_name' uses this. */
1219:
1220: #define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME)
1221:
1222: /* This is how to output an internal numbered label where
1223: PREFIX is the class of label and NUM is the number within the class. */
1224:
1225: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1226: fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1227:
1228: /* This is how to store into the string LABEL
1229: the symbol_ref name of an internal numbered label where
1230: PREFIX is the class of label and NUM is the number within the class.
1231: This is suitable for output with `assemble_name'. */
1232:
1233: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1234: sprintf (LABEL, "*%s%d", PREFIX, NUM)
1235:
1236: /* This is how to output an assembler line defining a `double' constant. */
1237:
1238: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) i960_output_double(FILE, VALUE)
1239:
1240: /* This is how to output an assembler line defining a `float' constant. */
1241:
1242: #define ASM_OUTPUT_FLOAT(FILE,VALUE) i960_output_float(FILE, VALUE)
1243:
1244: /* This is how to output an assembler line defining an `int' constant. */
1245:
1246: #define ASM_OUTPUT_INT(FILE,VALUE) \
1247: ( fprintf (FILE, "\t.word "), \
1248: output_addr_const (FILE, (VALUE)), \
1249: fprintf (FILE, "\n"))
1250:
1251: /* Likewise for `char' and `short' constants. */
1252:
1253: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1254: ( fprintf (FILE, "\t.short "), \
1255: output_addr_const (FILE, (VALUE)), \
1256: fprintf (FILE, "\n"))
1257:
1258: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1259: ( fprintf (FILE, "\t.byte "), \
1260: output_addr_const (FILE, (VALUE)), \
1261: fprintf (FILE, "\n"))
1262:
1263: /* This is how to output an assembler line for a numeric constant byte. */
1264:
1265: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1266: fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1267:
1268: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1269: fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO])
1270:
1271: /* This is how to output an insn to pop a register from the stack.
1272: It need not be very fast code. */
1273:
1274: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1275: fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO])
1276:
1277: /* This is how to output an element of a case-vector that is absolute. */
1278:
1279: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1280: fprintf (FILE, "\t.word L%d\n", VALUE)
1281:
1282: /* This is how to output an element of a case-vector that is relative. */
1283:
1284: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1285: fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
1286:
1287: /* This is how to output an assembler line that says to advance the
1288: location counter to a multiple of 2**LOG bytes. */
1289:
1290: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1291: fprintf (FILE, "\t.align %d\n", (LOG))
1292:
1293: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1294: fprintf (FILE, "\t.space %d\n", (SIZE))
1295:
1296: /* This says how to output an assembler line
1297: to define a global common symbol. */
1298:
1299: /* For common objects, output unpadded size... gld960 & lnk960 both
1300: have code to align each common object at link time. Also, if size
1301: is 0, treat this as a declaration, not a definition - i.e.,
1302: do nothing at all. */
1303:
1304: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1305: { if ((SIZE) != 0) \
1306: { \
1307: fputs (".globl ", (FILE)), \
1308: assemble_name ((FILE), (NAME)), \
1309: fputs ("\n.comm ", (FILE)), \
1310: assemble_name ((FILE), (NAME)), \
1311: fprintf ((FILE), ",%d\n", (ROUNDED)); \
1312: } \
1313: }
1314:
1315: /* This says how to output an assembler line to define a local common symbol.
1316: Output unpadded size, with request to linker to align as requested.
1317: 0 size should not be possible here. */
1318:
1319: #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1320: ( fputs (".bss\t", (FILE)), \
1321: assemble_name ((FILE), (NAME)), \
1322: fprintf ((FILE), ",%d,%d\n", (SIZE), \
1323: ((ALIGN) <= 8 ? 0 \
1324: : ((ALIGN) <= 16 ? 1 \
1325: : ((ALIGN) <= 32 ? 2 \
1326: : ((ALIGN <= 64 ? 3 : 4)))))))
1327:
1328: /* Output text for an #ident directive. */
1329: #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR);
1330:
1331: /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */
1332:
1333: #define ASM_OUTPUT_ALIGN_CODE(FILE) \
1334: { if (TARGET_CODE_ALIGN) fputs("\t.align 3\n",FILE); }
1335:
1336: /* Store in OUTPUT a string (made with alloca) containing
1337: an assembler-name for a local static variable named NAME.
1338: LABELNO is an integer which is different for each call. */
1339:
1340: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1341: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1342: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1343:
1344: /* Define the parentheses used to group arithmetic operations
1345: in assembler code. */
1346:
1347: #define ASM_OPEN_PAREN "("
1348: #define ASM_CLOSE_PAREN ")"
1349:
1350: /* Define results of standard character escape sequences. */
1351: #define TARGET_BELL 007
1352: #define TARGET_BS 010
1353: #define TARGET_TAB 011
1354: #define TARGET_NEWLINE 012
1355: #define TARGET_VT 013
1356: #define TARGET_FF 014
1357: #define TARGET_CR 015
1358:
1359: /* Output assembler code to FILE to initialize this source file's
1360: basic block profiling info, if that has not already been done. */
1361:
1362: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1363: { fprintf (FILE, "\tld LPBX0,g12\n"); \
1364: fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\
1365: fprintf (FILE, "\tlda LPBX0,g12\n"); \
1366: fprintf (FILE, "\tcall ___bb_init_func\n"); \
1367: fprintf (FILE, "LPY%d:\n",LABELNO); }
1368:
1369: /* Output assembler code to FILE to increment the entry-count for
1370: the BLOCKNO'th basic block in this source file. */
1371:
1372: #define BLOCK_PROFILER(FILE, BLOCKNO) \
1373: { int blockn = (BLOCKNO); \
1374: fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \
1375: fprintf (FILE, "\taddo g12,1,g12\n"); \
1376: fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); }
1377:
1378: /* Print operand X (an rtx) in assembler syntax to file FILE.
1379: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1380: For `%' followed by punctuation, CODE is the punctuation and X is null. */
1381:
1382: #define PRINT_OPERAND(FILE, X, CODE) \
1383: i960_print_operand (FILE, X, CODE);
1384:
1385: /* Print a memory address as an operand to reference that memory location. */
1386:
1387: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1388: i960_print_operand_addr (FILE, ADDR)
1389:
1390: /* Output assembler code for a block containing the constant parts
1391: of a trampoline, leaving space for the variable parts. */
1392:
1393: /* On the i960, the trampoline contains three instructions:
1394: ldconst _function, r4
1395: ldconst static addr, r3
1396: jump (r4) */
1397:
1398: #define TRAMPOLINE_TEMPLATE(FILE) \
1399: { \
1400: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C203000)); \
1401: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1402: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C183000)); \
1403: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1404: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x84212000)); \
1405: }
1406:
1407: /* Length in units of the trampoline for entering a nested function. */
1408:
1409: #define TRAMPOLINE_SIZE 20
1410:
1411: /* Emit RTL insns to initialize the variable parts of a trampoline.
1412: FNADDR is an RTX for the address of the function's pure code.
1413: CXT is an RTX for the static chain value for the function. */
1414:
1415: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1416: { \
1417: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), \
1418: FNADDR); \
1419: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), \
1420: CXT); \
1421: }
1422:
1423: #if 0
1424: /* Promote char and short arguments to ints, when want compitibility with
1425: the iC960 compilers. */
1426:
1427: /* ??? In order for this to work, all users would need to be changed
1428: to test the value of the macro at run time. */
1429: #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE
1430: /* ??? This does not exist. */
1431: #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE
1432: #endif
1433:
1434: /* Instruction type definitions. Used to alternate instructions types for
1435: better performance on the C series chips. */
1436:
1437: enum insn_types { I_TYPE_REG, I_TYPE_MEM, I_TYPE_CTRL };
1438:
1439: /* Holds the insn type of the last insn output to the assembly file. */
1440:
1441: extern enum insn_types i960_last_insn_type;
1442:
1443: /* Parse opcodes, and set the insn last insn type based on them. */
1444:
1445: #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN)
1446:
1447: /* Table listing what rtl codes each predicate in i960.c will accept. */
1448:
1449: #define PREDICATE_CODES \
1450: {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1451: LABEL_REF, SUBREG, REG, MEM}}, \
1452: {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1453: {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1454: {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \
1455: {"literal", {CONST_INT}}, \
1456: {"fp_literal_one", {CONST_DOUBLE}}, \
1457: {"fp_literal_double", {CONST_DOUBLE}}, \
1458: {"fp_literal", {CONST_DOUBLE}}, \
1459: {"signed_literal", {CONST_INT}}, \
1460: {"symbolic_memory_operand", {SUBREG, MEM}}, \
1461: {"eq_or_neq", {EQ, NE}}, \
1462: {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \
1463: CONST_DOUBLE, CONST}}, \
1464: {"power2_operand", {CONST_INT}},
1465:
1466: /* Define functions in i960.c and used in insn-output.c. */
1467:
1468: extern char *i960_output_ldconst ();
1469: extern char *i960_output_call_insn ();
1470: extern char *i960_output_ret_insn ();
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