--- gcc/config/i960.md	2018/04/24 17:59:54	1.1.1.1
+++ gcc/config/i960.md	2018/04/24 18:05:43	1.1.1.2
@@ -22,6 +22,13 @@
 
 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
 
+;; There are very few (4) 'f' registers, they can't be loaded/stored from/to
+;; memory, and some instructions explicitly require them, so we get better
+;; code by discouraging psuedo-registers from being allocated to them.
+;; However, we do want to allow all patterns which can store to them to
+;; include them in their constraints, so we always use '*f' in a destination
+;; constraint except when 'f' is the only alternative.
+
 ;; Insn attributes which describe the i960.
 
 ;; Modscan is not used, since the compiler never emits any of these insns.
@@ -48,7 +55,7 @@
    (set_attr "type" "multi")])
 
 ;; (define_function_unit {name} {num-units} {n-users} {test}
-;;                       {ready-delay} {busy-delay} [{conflict-list}])
+;;                       {ready-delay} {issue-delay} [{conflict-list}])
 
 ;; The integer ALU
 (define_function_unit "alu" 2 0 (eq_attr "type" "arith,compare,move,address") 1 0)
@@ -526,7 +533,7 @@
   [(set_attr "type" "branch")])
 
 ;; Normal move instructions.
-;; This code is based on the sparc machine desciption.
+;; This code is based on the sparc machine description.
 
 (define_expand "movsi"
   [(set (match_operand:SI 0 "general_operand" "")
@@ -773,8 +780,8 @@
 
 ;; The store case can not be separate.  See comment above.
 (define_insn ""
-  [(set (match_operand:DI 0 "general_operand" "=d,d,d,m")
-	(match_operand:DI 1 "general_operand" "dI,i,m,dJ"))]
+  [(set (match_operand:DI 0 "general_operand" "=d,d,d,m,o")
+	(match_operand:DI 1 "general_operand" "dI,i,m,d,J"))]
   "current_function_args_size == 0
    && (register_operand (operands[0], DImode)
        || register_operand (operands[1], DImode)
@@ -790,12 +797,13 @@
     case 2:
       return \"ldl	%1,%0\";
     case 3:
-      if (operands[1] == const0_rtx)
-	return \"st	g14,%0\;st	g14,4(%0)\";
       return \"stl	%1,%0\";
+    case 4:
+      operands[1] = adj_offsettable_operand (operands[0], 4);
+      return \"st	g14,%0\;st	g14,%1\";
     }
 }"
-  [(set_attr "type" "move,load,load,store")])
+  [(set_attr "type" "move,load,load,store,store")])
 
 ;; The store case can not be separate.  See comment above.
 (define_insn ""
@@ -832,8 +840,8 @@
 
 ;; The store case can not be separate.  See comment above.
 (define_insn ""
-  [(set (match_operand:TI 0 "general_operand" "=d,d,d,m")
-	(match_operand:TI 1 "general_operand" "dI,i,m,dJ"))]
+  [(set (match_operand:TI 0 "general_operand" "=d,d,d,m,o")
+	(match_operand:TI 1 "general_operand" "dI,i,m,d,J"))]
   "current_function_args_size == 0
    && (register_operand (operands[0], TImode)
        || register_operand (operands[1], TImode)
@@ -849,12 +857,15 @@
     case 2:
       return \"ldq	%1,%0\";
     case 3:
-      if (operands[1] == const0_rtx)
-	return \"st	g14,%0\;st	g14,4(%0)\;st	g14,8(%0)\;st	g14,12(%0)\";
       return \"stq	%1,%0\";
+    case 4:
+      operands[1] = adj_offsettable_operand (operands[0], 4);
+      operands[2] = adj_offsettable_operand (operands[0], 8);
+      operands[3] = adj_offsettable_operand (operands[0], 12);
+      return \"st	g14,%0\;st	g14,%1\;st	g14,%2\;st	g14,%3\";
     }
 }"
-  [(set_attr "type" "move,load,load,store")])
+  [(set_attr "type" "move,load,load,store,store")])
 
 ;; The store case can not be separate.  See comment above.
 (define_insn ""
@@ -945,8 +956,8 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=r,f,d,d,m")
-	(match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,dG"))]
+  [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m,o")
+	(match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d,G"))]
   "current_function_args_size == 0
    && (register_operand (operands[0], DFmode)
        || register_operand (operands[1], DFmode)
@@ -967,15 +978,16 @@
     case 3:
       return \"ldl	%1,%0\";
     case 4:
-      if (operands[1] == CONST0_RTX (DFmode))
-	return \"st	g14,%0\;st	g14,4(%0)\";
       return \"stl	%1,%0\";
+    case 5:
+      operands[1] = adj_offsettable_operand (operands[0], 4);
+      return \"st	g14,%0\;st	g14,%1\";
     }
 }"
-  [(set_attr "type" "move,move,load,fpload,fpstore")])
+  [(set_attr "type" "move,move,load,fpload,fpstore,fpstore")])
 
 (define_insn ""
-  [(set (match_operand:DF 0 "general_operand" "=r,f,d,d,m")
+  [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m")
 	(match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
   "current_function_args_size != 0
    && (register_operand (operands[0], DFmode)
@@ -1012,7 +1024,7 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=r,f,d,d,m")
+  [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m")
 	(match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,dG"))]
   "current_function_args_size == 0
    && (register_operand (operands[0], SFmode)
@@ -1042,7 +1054,7 @@
   [(set_attr "type" "move,move,load,fpload,fpstore")])
 
 (define_insn ""
-  [(set (match_operand:SF 0 "general_operand" "=r,f,d,d,m")
+  [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m")
 	(match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
   "current_function_args_size != 0
    && (register_operand (operands[0], SFmode)
@@ -1307,7 +1319,7 @@
 ;; Conversions between float and double.
 
 (define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "register_operand" "=f,d")
+  [(set (match_operand:DF 0 "register_operand" "=*f,d")
 	(float_extend:DF (match_operand:SF 1 "fp_arith_operand" "dGH,fGH")))]
   "TARGET_NUMERICS"
   "@
@@ -1333,7 +1345,7 @@
   [(set_attr "type" "fpcvt")])
 
 (define_insn "floatsisf2"
-  [(set (match_operand:SF 0 "register_operand" "=df")
+  [(set (match_operand:SF 0 "register_operand" "=d*f")
 	(float:SF (match_operand:SI 1 "register_operand" "d")))]
   "TARGET_NUMERICS"
   "cvtir	%1,%0"
@@ -1692,7 +1704,7 @@
 ;; Floating point arithmetic instructions.
 
 (define_insn "adddf3"
-  [(set (match_operand:DF 0 "register_operand" "=d")
+  [(set (match_operand:DF 0 "register_operand" "=d*f")
 	(plus:DF (match_operand:DF 1 "fp_arith_operand" "%rGH")
 		 (match_operand:DF 2 "fp_arith_operand" "rGH")))]
   "TARGET_NUMERICS"
@@ -1700,7 +1712,7 @@
   [(set_attr "type" "fpadd")])
 
 (define_insn "addsf3"
-  [(set (match_operand:SF 0 "register_operand" "=d")
+  [(set (match_operand:SF 0 "register_operand" "=d*f")
 	(plus:SF (match_operand:SF 1 "fp_arith_operand" "%rGH")
 		 (match_operand:SF 2 "fp_arith_operand" "rGH")))]
   "TARGET_NUMERICS"
@@ -1709,7 +1721,7 @@
 
 
 (define_insn "subdf3"
-  [(set (match_operand:DF 0 "register_operand" "=d")
+  [(set (match_operand:DF 0 "register_operand" "=d*f")
 	(minus:DF (match_operand:DF 1 "fp_arith_operand" "rGH")
 		  (match_operand:DF 2 "fp_arith_operand" "rGH")))]
   "TARGET_NUMERICS"
@@ -1717,7 +1729,7 @@
   [(set_attr "type" "fpadd")])
 
 (define_insn "subsf3"
-  [(set (match_operand:SF 0 "register_operand" "=d")
+  [(set (match_operand:SF 0 "register_operand" "=d*f")
 	(minus:SF (match_operand:SF 1 "fp_arith_operand" "rGH")
 		  (match_operand:SF 2 "fp_arith_operand" "rGH")))]
   "TARGET_NUMERICS"
@@ -1726,7 +1738,7 @@
 
 
 (define_insn "muldf3"
-  [(set (match_operand:DF 0 "register_operand" "=d")
+  [(set (match_operand:DF 0 "register_operand" "=d*f")
 	(mult:DF (match_operand:DF 1 "fp_arith_operand" "rGH")
 		 (match_operand:DF 2 "fp_arith_operand" "rGH")))]
   "TARGET_NUMERICS"
@@ -1734,7 +1746,7 @@
   [(set_attr "type" "fpmul")])
 
 (define_insn "mulsf3"
-  [(set (match_operand:SF 0 "register_operand" "=d")
+  [(set (match_operand:SF 0 "register_operand" "=d*f")
 	(mult:SF (match_operand:SF 1 "fp_arith_operand" "rGH")
 		 (match_operand:SF 2 "fp_arith_operand" "rGH")))]
   "TARGET_NUMERICS"
@@ -1743,7 +1755,7 @@
 
 
 (define_insn "divdf3"
-  [(set (match_operand:DF 0 "register_operand" "=d")
+  [(set (match_operand:DF 0 "register_operand" "=d*f")
 	(div:DF (match_operand:DF 1 "fp_arith_operand" "rGH")
 		(match_operand:DF 2 "fp_arith_operand" "rGH")))]
   "TARGET_NUMERICS"
@@ -1751,7 +1763,7 @@
   [(set_attr "type" "fpdiv")])
 
 (define_insn "divsf3"
-  [(set (match_operand:SF 0 "register_operand" "=d")
+  [(set (match_operand:SF 0 "register_operand" "=d*f")
 	(div:SF (match_operand:SF 1 "fp_arith_operand" "rGH")
 		(match_operand:SF 2 "fp_arith_operand" "rGH")))]
   "TARGET_NUMERICS"
@@ -1759,7 +1771,7 @@
   [(set_attr "type" "fpdiv")])
 
 (define_insn "negdf2"
-  [(set (match_operand:DF 0 "register_operand" "=d,f")
+  [(set (match_operand:DF 0 "register_operand" "=d,d*f")
 	(neg:DF (match_operand:DF 1 "register_operand" "d,r")))]
   ""
   "*
@@ -1775,7 +1787,7 @@
   [(set_attr "type" "fpadd")])
 
 (define_insn "negsf2"
-  [(set (match_operand:SF 0 "register_operand" "=d,f")
+  [(set (match_operand:SF 0 "register_operand" "=d,d*f")
 	(neg:SF (match_operand:SF 1 "register_operand" "d,r")))]
   ""
   "@
@@ -1788,7 +1800,7 @@
 ;;; less than 32.
 
 (define_insn "absdf2"
-  [(set (match_operand:DF 0 "register_operand" "=df")
+  [(set (match_operand:DF 0 "register_operand" "=d*f")
 	(abs:DF (match_operand:DF 1 "register_operand" "df")))]
   ""
   "*
@@ -1814,7 +1826,7 @@
   [(set_attr "type" "multi")])
 
 (define_insn "abssf2"
-  [(set (match_operand:SF 0 "register_operand" "=df")
+  [(set (match_operand:SF 0 "register_operand" "=d*f")
 	(abs:SF (match_operand:SF 1 "register_operand" "df")))]
   ""
   "*
@@ -1856,8 +1868,8 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:TF 0 "general_operand" "=r,f,d,d,m")
-	(match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,dG"))]
+  [(set (match_operand:TF 0 "general_operand" "=r,*f,d,d,m,o")
+	(match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d,G"))]
   "current_function_args_size == 0
    && (register_operand (operands[0], TFmode)
        || register_operand (operands[1], TFmode)
@@ -1878,15 +1890,18 @@
     case 3:
       return \"ldq	%1,%0\";
     case 4:
-      if (operands[1] == CONST0_RTX (TFmode))
-	return \"st	g14,%0\;st	g14,4(%0)\;st	g14,8(%0)\;st	g14,12(%0)\";
       return \"stq	%1,%0\";
+    case 5:
+      operands[1] = adj_offsettable_operand (operands[0], 4);
+      operands[2] = adj_offsettable_operand (operands[0], 8);
+      operands[3] = adj_offsettable_operand (operands[0], 12);
+      return \"st	g14,%0\;st	g14,%1\;st	g14,%2\;st	g14,%3\";
     }
 }"
-  [(set_attr "type" "move,move,load,fpload,fpstore")])
+  [(set_attr "type" "move,move,load,fpload,fpstore,fpstore")])
 
 (define_insn ""
-  [(set (match_operand:TF 0 "general_operand" "=r,f,d,d,m")
+  [(set (match_operand:TF 0 "general_operand" "=r,*f,d,d,m")
 	(match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
   "current_function_args_size != 0
    && (register_operand (operands[0], TFmode)
@@ -1913,7 +1928,7 @@
   [(set_attr "type" "move,move,load,fpload,fpstore")])
 
 (define_insn "extendsftf2"
-  [(set (match_operand:TF 0 "register_operand" "=f,d")
+  [(set (match_operand:TF 0 "register_operand" "=*f,d")
 	(float_extend:TF
 	 (match_operand:SF 1 "register_operand" "d,f")))]
   "TARGET_NUMERICS"
@@ -1923,7 +1938,7 @@
   [(set_attr "type" "fpmove")])
 
 (define_insn "extenddftf2"
-  [(set (match_operand:TF 0 "register_operand" "=f,d")
+  [(set (match_operand:TF 0 "register_operand" "=*f,d")
 	(float_extend:TF
 	 (match_operand:DF 1 "register_operand" "d,f")))]
   "TARGET_NUMERICS"
@@ -2051,9 +2066,9 @@
   [(set_attr "type" "branch")])
 
 (define_insn "indirect_jump"
-  [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
+  [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
   ""
-  "b*	%0"
+  "bx	%a0"
   [(set_attr "type" "branch")])
 
 (define_insn "tablejump"
@@ -2066,20 +2081,24 @@
 ;;- jump to subroutine
 
 (define_expand "call"
-  [(call (match_operand:SI 0 "general_operand" "")
-	 (match_operand:SI 1 "immediate_operand" ""))]
+  [(call (match_operand:SI 0 "general_operand" "g")
+	 (match_operand:SI 1 "immediate_operand" "i"))]
   ""
   "
 {
-  i960_expand_call (operand0, operand1, 0);
+  emit_insn (gen_call_internal (operands[0], operands[1],
+				virtual_outgoing_args_rtx));
   DONE;
 }")
 
-(define_insn ""
+(define_insn "call_internal"
   [(call (match_operand:SI 0 "general_operand" "g")
-	 (match_operand:SI 1 "immediate_operand" "i"))]
+	 (match_operand:SI 1 "immediate_operand" "i"))
+   (use (match_operand:SI 2 "address_operand" "p"))
+   (clobber (match_scratch:SI 3 "=&d"))]
   ""
-  "* return i960_output_call_insn (operands[0], operands[1], insn);"
+  "* return i960_output_call_insn (operands[0], operands[1], operands[2],
+				   operands[3], insn);"
   [(set_attr "type" "call")])
 
 (define_expand "call_value"
@@ -2089,16 +2108,20 @@
   ""
   "
 {
-  i960_expand_call (operand1, operand2, operand0);
+  emit_insn (gen_call_value_internal (operands[0], operands[1], operands[2],
+				      virtual_outgoing_args_rtx));
   DONE;
 }")
 
-(define_insn ""
+(define_insn "call_value_internal"
   [(set (match_operand 0 "register_operand" "=d")
 	(call (match_operand:SI 1 "general_operand" "g")
-	      (match_operand:SI 2 "immediate_operand" "i")))]
+	      (match_operand:SI 2 "immediate_operand" "i")))
+   (use (match_operand:SI 3 "address_operand" "p"))
+   (clobber (match_scratch:SI 4 "=&d"))]
   ""
-  "* return i960_output_call_insn (operands[1], operands[2], insn);"
+  "* return i960_output_call_insn (operands[1], operands[2], operands[3],
+				   operands[4], insn);"
   [(set_attr "type" "call")])
 
 (define_insn "return"