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1.1 ! root 1: ;;- Machine description for Intel 80960 chip for GNU C compiler ! 2: ;; Copyright (C) 1992 Free Software Foundation, Inc. ! 3: ;; Contributed by Steven McGeady, Intel Corp. ! 4: ;; Additional work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson ! 5: ;; Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support. ! 6: ! 7: ;; This file is part of GNU CC. ! 8: ! 9: ;; GNU CC is free software; you can redistribute it and/or modify ! 10: ;; it under the terms of the GNU General Public License as published by ! 11: ;; the Free Software Foundation; either version 2, or (at your option) ! 12: ;; any later version. ! 13: ! 14: ;; GNU CC is distributed in the hope that it will be useful, ! 15: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 16: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 17: ;; GNU General Public License for more details. ! 18: ! 19: ;; You should have received a copy of the GNU General Public License ! 20: ;; along with GNU CC; see the file COPYING. If not, write to ! 21: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 22: ! 23: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 24: ! 25: ;; Insn attributes which describe the i960. ! 26: ! 27: ;; Modscan is not used, since the compiler never emits any of these insns. ! 28: (define_attr "type" ! 29: "move,arith,alu2,mult,div,modscan,load,store,branch,call,address,compare,fpload,fpstore,fpmove,fpcvt,fpcc,fpadd,fpmul,fpdiv,multi,misc" ! 30: (const_string "arith")) ! 31: ! 32: ;; Length (in # of insns). ! 33: (define_attr "length" "" ! 34: (cond [(eq_attr "type" "load,fpload") ! 35: (if_then_else (match_operand 1 "symbolic_memory_operand" "") ! 36: (const_int 2) ! 37: (const_int 1)) ! 38: (eq_attr "type" "store,fpstore") ! 39: (if_then_else (match_operand 0 "symbolic_memory_operand" "") ! 40: (const_int 2) ! 41: (const_int 1)) ! 42: (eq_attr "type" "address") ! 43: (const_int 2)] ! 44: (const_int 1))) ! 45: ! 46: (define_asm_attributes ! 47: [(set_attr "length" "1") ! 48: (set_attr "type" "multi")]) ! 49: ! 50: ;; (define_function_unit {name} {num-units} {n-users} {test} ! 51: ;; {ready-delay} {busy-delay} [{conflict-list}]) ! 52: ! 53: ;; The integer ALU ! 54: (define_function_unit "alu" 2 0 (eq_attr "type" "arith,compare,move,address") 1 0) ! 55: (define_function_unit "alu" 2 0 (eq_attr "type" "alu2") 2 0) ! 56: (define_function_unit "alu" 2 0 (eq_attr "type" "mult") 5 0) ! 57: (define_function_unit "alu" 2 0 (eq_attr "type" "div") 35 0) ! 58: (define_function_unit "alu" 2 0 (eq_attr "type" "modscan") 3 0) ! 59: ! 60: ;; Memory with load-delay of 1 (i.e., 2 cycle load). ! 61: (define_function_unit "memory" 1 0 (eq_attr "type" "load,fpload") 2 0) ! 62: ! 63: ;; Floating point operations. ! 64: (define_function_unit "fp" 1 2 (eq_attr "type" "fpmove") 5 0) ! 65: (define_function_unit "fp" 1 2 (eq_attr "type" "fpcvt") 35 0) ! 66: (define_function_unit "fp" 1 2 (eq_attr "type" "fpcc") 10 0) ! 67: (define_function_unit "fp" 1 2 (eq_attr "type" "fpadd") 10 0) ! 68: (define_function_unit "fp" 1 2 (eq_attr "type" "fpmul") 20 0) ! 69: (define_function_unit "fp" 1 2 (eq_attr "type" "fpdiv") 35 0) ! 70: ! 71: ;; Compare instructions. ! 72: ;; This controls RTL generation and register allocation. ! 73: ! 74: ;; We generate RTL for comparisons and branches by having the cmpxx ! 75: ;; patterns store away the operands. Then, the scc and bcc patterns ! 76: ;; emit RTL for both the compare and the branch. ! 77: ;; ! 78: ;; We start with the DEFINE_EXPANDs, then then DEFINE_INSNs to match ! 79: ;; the patterns. Finally, we have the DEFINE_SPLITs for some of the scc ! 80: ;; insns that actually require more than one machine instruction. ! 81: ! 82: ;; Put cmpsi first because it is expected to be the most common. ! 83: ! 84: (define_expand "cmpsi" ! 85: [(set (reg:CC 36) ! 86: (compare:CC (match_operand:SI 0 "nonimmediate_operand" "") ! 87: (match_operand:SI 1 "general_operand" "")))] ! 88: "" ! 89: " ! 90: { ! 91: i960_compare_op0 = operands[0]; ! 92: i960_compare_op1 = operands[1]; ! 93: DONE; ! 94: }") ! 95: ! 96: (define_expand "cmpdf" ! 97: [(set (reg:CC 36) ! 98: (compare:CC (match_operand:DF 0 "register_operand" "r") ! 99: (match_operand:DF 1 "nonmemory_operand" "rGH")))] ! 100: "TARGET_NUMERICS" ! 101: " ! 102: { ! 103: i960_compare_op0 = operands[0]; ! 104: i960_compare_op1 = operands[1]; ! 105: DONE; ! 106: }") ! 107: ! 108: (define_expand "cmpsf" ! 109: [(set (reg:CC 36) ! 110: (compare:CC (match_operand:SF 0 "register_operand" "r") ! 111: (match_operand:SF 1 "nonmemory_operand" "rGH")))] ! 112: "TARGET_NUMERICS" ! 113: " ! 114: { ! 115: i960_compare_op0 = operands[0]; ! 116: i960_compare_op1 = operands[1]; ! 117: DONE; ! 118: }") ! 119: ! 120: ;; Now the DEFINE_INSNs for the compare and scc cases. First the compares. ! 121: ! 122: (define_insn "" ! 123: [(set (reg:CC 36) ! 124: (compare:CC (match_operand:SI 0 "register_operand" "d") ! 125: (match_operand:SI 1 "arith_operand" "dI")))] ! 126: "" ! 127: "cmpi %0,%1" ! 128: [(set_attr "type" "compare")]) ! 129: ! 130: (define_insn "" ! 131: [(set (reg:CC_UNS 36) ! 132: (compare:CC_UNS (match_operand:SI 0 "register_operand" "d") ! 133: (match_operand:SI 1 "arith_operand" "dI")))] ! 134: "" ! 135: "cmpo %0,%1" ! 136: [(set_attr "type" "compare")]) ! 137: ! 138: (define_insn "" ! 139: [(set (reg:CC 36) ! 140: (compare:CC (match_operand:DF 0 "register_operand" "r") ! 141: (match_operand:DF 1 "nonmemory_operand" "rGH")))] ! 142: "TARGET_NUMERICS" ! 143: "cmprl %0,%1" ! 144: [(set_attr "type" "fpcc")]) ! 145: ! 146: (define_insn "" ! 147: [(set (reg:CC 36) ! 148: (compare:CC (match_operand:SF 0 "register_operand" "r") ! 149: (match_operand:SF 1 "nonmemory_operand" "rGH")))] ! 150: "TARGET_NUMERICS" ! 151: "cmpr %0,%1" ! 152: [(set_attr "type" "fpcc")]) ! 153: ! 154: ;; Instruction definitions for branch-on-bit-set and clear insns. ! 155: ! 156: (define_insn "" ! 157: [(set (pc) ! 158: (if_then_else ! 159: (ne (sign_extract:SI (match_operand:SI 1 "register_operand" "d") ! 160: (const_int 1) ! 161: (match_operand:SI 2 "arith_operand" "dI")) ! 162: (const_int 0)) ! 163: (label_ref (match_operand 3 "" "")) ! 164: (pc)))] ! 165: "" ! 166: "bbs %2,%1,%l3" ! 167: [(set_attr "type" "branch")]) ! 168: ! 169: (define_insn "" ! 170: [(set (pc) ! 171: (if_then_else ! 172: (eq (sign_extract:SI (match_operand:SI 1 "register_operand" "d") ! 173: (const_int 1) ! 174: (match_operand:SI 2 "arith_operand" "dI")) ! 175: (const_int 0)) ! 176: (label_ref (match_operand 3 "" "")) ! 177: (pc)))] ! 178: "" ! 179: "bbc %2,%1,%l3" ! 180: [(set_attr "type" "branch")]) ! 181: ! 182: (define_insn "" ! 183: [(set (pc) ! 184: (if_then_else ! 185: (ne (zero_extract:SI (match_operand:SI 1 "register_operand" "d") ! 186: (const_int 1) ! 187: (match_operand:SI 2 "arith_operand" "dI")) ! 188: (const_int 0)) ! 189: (label_ref (match_operand 3 "" "")) ! 190: (pc)))] ! 191: "" ! 192: "bbs %2,%1,%l3" ! 193: [(set_attr "type" "branch")]) ! 194: ! 195: (define_insn "" ! 196: [(set (pc) ! 197: (if_then_else ! 198: (eq (zero_extract:SI (match_operand:SI 1 "register_operand" "d") ! 199: (const_int 1) ! 200: (match_operand:SI 2 "arith_operand" "dI")) ! 201: (const_int 0)) ! 202: (label_ref (match_operand 3 "" "")) ! 203: (pc)))] ! 204: "" ! 205: "bbc %2,%1,%l3" ! 206: [(set_attr "type" "branch")]) ! 207: ! 208: ;; ??? These will never match. The LOG_LINKs necessary to make these match ! 209: ;; are not created by flow. These remain as a reminder to make this work ! 210: ;; some day. ! 211: ! 212: (define_insn "" ! 213: [(set (reg:CC 36) ! 214: (compare (match_operand:SI 0 "arith_operand" "d") ! 215: (match_operand:SI 1 "arith_operand" "d"))) ! 216: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))] ! 217: "0" ! 218: "cmpinci %0,%1" ! 219: [(set_attr "type" "compare")]) ! 220: ! 221: (define_insn "" ! 222: [(set (reg:CC_UNS 36) ! 223: (compare (match_operand:SI 0 "arith_operand" "d") ! 224: (match_operand:SI 1 "arith_operand" "d"))) ! 225: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))] ! 226: "0" ! 227: "cmpinco %0,%1" ! 228: [(set_attr "type" "compare")]) ! 229: ! 230: (define_insn "" ! 231: [(set (reg:CC 36) ! 232: (compare (match_operand:SI 0 "arith_operand" "d") ! 233: (match_operand:SI 1 "arith_operand" "d"))) ! 234: (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))] ! 235: "0" ! 236: "cmpdeci %0,%1" ! 237: [(set_attr "type" "compare")]) ! 238: ! 239: (define_insn "" ! 240: [(set (reg:CC_UNS 36) ! 241: (compare (match_operand:SI 0 "arith_operand" "d") ! 242: (match_operand:SI 1 "arith_operand" "d"))) ! 243: (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))] ! 244: "0" ! 245: "cmpdeco %0,%1" ! 246: [(set_attr "type" "compare")]) ! 247: ! 248: ;; Templates to store result of condition. ! 249: ;; '1' is stored if condition is true. ! 250: ;; '0' is stored if condition is false. ! 251: ;; These should use predicate "general_operand", since ! 252: ;; gcc seems to be creating mem references which use these ! 253: ;; templates. ! 254: ! 255: (define_expand "seq" ! 256: [(set (match_operand:SI 0 "general_operand" "=d") ! 257: (eq (match_dup 1) (const_int 0)))] ! 258: "" ! 259: " ! 260: { ! 261: operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1); ! 262: }") ! 263: ! 264: (define_expand "sne" ! 265: [(set (match_operand:SI 0 "general_operand" "=d") ! 266: (ne (match_dup 1) (const_int 0)))] ! 267: "" ! 268: " ! 269: { ! 270: operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1); ! 271: }") ! 272: ! 273: (define_expand "sgt" ! 274: [(set (match_operand:SI 0 "general_operand" "=d") ! 275: (gt (match_dup 1) (const_int 0)))] ! 276: "" ! 277: " ! 278: { ! 279: operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1); ! 280: }") ! 281: ! 282: (define_expand "sgtu" ! 283: [(set (match_operand:SI 0 "general_operand" "=d") ! 284: (gtu (match_dup 1) (const_int 0)))] ! 285: "" ! 286: " ! 287: { ! 288: operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1); ! 289: }") ! 290: ! 291: (define_expand "slt" ! 292: [(set (match_operand:SI 0 "general_operand" "=d") ! 293: (lt (match_dup 1) (const_int 0)))] ! 294: "" ! 295: " ! 296: { ! 297: operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1); ! 298: }") ! 299: ! 300: (define_expand "sltu" ! 301: [(set (match_operand:SI 0 "general_operand" "=d") ! 302: (ltu (match_dup 1) (const_int 0)))] ! 303: "" ! 304: " ! 305: { ! 306: operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1); ! 307: }") ! 308: ! 309: (define_expand "sge" ! 310: [(set (match_operand:SI 0 "general_operand" "=d") ! 311: (ge (match_dup 1) (const_int 0)))] ! 312: "" ! 313: " ! 314: { ! 315: operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1); ! 316: }") ! 317: ! 318: (define_expand "sgeu" ! 319: [(set (match_operand:SI 0 "general_operand" "=d") ! 320: (geu (match_dup 1) (const_int 0)))] ! 321: "" ! 322: " ! 323: { ! 324: operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1); ! 325: }") ! 326: ! 327: (define_expand "sle" ! 328: [(set (match_operand:SI 0 "general_operand" "=d") ! 329: (le (match_dup 1) (const_int 0)))] ! 330: "" ! 331: " ! 332: { ! 333: operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1); ! 334: }") ! 335: ! 336: (define_expand "sleu" ! 337: [(set (match_operand:SI 0 "general_operand" "=d") ! 338: (leu (match_dup 1) (const_int 0)))] ! 339: "" ! 340: " ! 341: { ! 342: operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1); ! 343: }") ! 344: ! 345: (define_insn "" ! 346: [(set (match_operand:SI 0 "general_operand" "=d") ! 347: (match_operator 1 "comparison_operator" [(reg:CC 36) (const_int 0)]))] ! 348: "" ! 349: "test%C1 %0" ! 350: [(set_attr "type" "compare")]) ! 351: ! 352: (define_insn "" ! 353: [(set (match_operand:SI 0 "general_operand" "=d") ! 354: (match_operator 1 "comparison_operator" [(reg:CC_UNS 36) (const_int 0)]))] ! 355: "" ! 356: "test%C1 %0" ! 357: [(set_attr "type" "compare")]) ! 358: ! 359: ;; These control RTL generation for conditional jump insns ! 360: ;; and match them for register allocation. ! 361: ! 362: (define_expand "beq" ! 363: [(set (pc) ! 364: (if_then_else (eq (match_dup 1) ! 365: (const_int 0)) ! 366: (label_ref (match_operand 0 "" "")) ! 367: (pc)))] ! 368: "" ! 369: " ! 370: { operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1); }") ! 371: ! 372: (define_expand "bne" ! 373: [(set (pc) ! 374: (if_then_else (ne (match_dup 1) ! 375: (const_int 0)) ! 376: (label_ref (match_operand 0 "" "")) ! 377: (pc)))] ! 378: "" ! 379: " ! 380: { operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1); }") ! 381: ! 382: (define_expand "bgt" ! 383: [(set (pc) ! 384: (if_then_else (gt (match_dup 1) ! 385: (const_int 0)) ! 386: (label_ref (match_operand 0 "" "")) ! 387: (pc)))] ! 388: "" ! 389: " ! 390: { operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1); }") ! 391: ! 392: (define_expand "bgtu" ! 393: [(set (pc) ! 394: (if_then_else (gtu (match_dup 1) ! 395: (const_int 0)) ! 396: (label_ref (match_operand 0 "" "")) ! 397: (pc)))] ! 398: "" ! 399: " ! 400: { operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1); }") ! 401: ! 402: (define_expand "blt" ! 403: [(set (pc) ! 404: (if_then_else (lt (match_dup 1) ! 405: (const_int 0)) ! 406: (label_ref (match_operand 0 "" "")) ! 407: (pc)))] ! 408: "" ! 409: " ! 410: { operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1); }") ! 411: ! 412: (define_expand "bltu" ! 413: [(set (pc) ! 414: (if_then_else (ltu (match_dup 1) ! 415: (const_int 0)) ! 416: (label_ref (match_operand 0 "" "")) ! 417: (pc)))] ! 418: "" ! 419: " ! 420: { operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1); }") ! 421: ! 422: (define_expand "bge" ! 423: [(set (pc) ! 424: (if_then_else (ge (match_dup 1) ! 425: (const_int 0)) ! 426: (label_ref (match_operand 0 "" "")) ! 427: (pc)))] ! 428: "" ! 429: " ! 430: { operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1); }") ! 431: ! 432: (define_expand "bgeu" ! 433: [(set (pc) ! 434: (if_then_else (geu (match_dup 1) ! 435: (const_int 0)) ! 436: (label_ref (match_operand 0 "" "")) ! 437: (pc)))] ! 438: "" ! 439: " ! 440: { operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1); }") ! 441: ! 442: (define_expand "ble" ! 443: [(set (pc) ! 444: (if_then_else (le (match_dup 1) ! 445: (const_int 0)) ! 446: (label_ref (match_operand 0 "" "")) ! 447: (pc)))] ! 448: "" ! 449: " ! 450: { operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1); }") ! 451: ! 452: (define_expand "bleu" ! 453: [(set (pc) ! 454: (if_then_else (leu (match_dup 1) ! 455: (const_int 0)) ! 456: (label_ref (match_operand 0 "" "")) ! 457: (pc)))] ! 458: "" ! 459: " ! 460: { operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1); }") ! 461: ! 462: ;; Now the normal branch insns (forward and reverse). ! 463: ! 464: (define_insn "" ! 465: [(set (pc) ! 466: (if_then_else (match_operator 0 "comparison_operator" ! 467: [(reg:CC 36) (const_int 0)]) ! 468: (label_ref (match_operand 1 "" "")) ! 469: (pc)))] ! 470: "" ! 471: "b%C0 %l1" ! 472: [(set_attr "type" "branch")]) ! 473: ! 474: (define_insn "" ! 475: [(set (pc) ! 476: (if_then_else (match_operator 0 "comparison_operator" ! 477: [(reg:CC 36) (const_int 0)]) ! 478: (pc) ! 479: (label_ref (match_operand 1 "" ""))))] ! 480: "" ! 481: "b%I0 %l1" ! 482: [(set_attr "type" "branch")]) ! 483: ! 484: (define_insn "" ! 485: [(set (pc) ! 486: (if_then_else (match_operator 0 "comparison_operator" ! 487: [(reg:CC_UNS 36) (const_int 0)]) ! 488: (label_ref (match_operand 1 "" "")) ! 489: (pc)))] ! 490: "" ! 491: "b%C0 %l1" ! 492: [(set_attr "type" "branch")]) ! 493: ! 494: (define_insn "" ! 495: [(set (pc) ! 496: (if_then_else (match_operator 0 "comparison_operator" ! 497: [(reg:CC_UNS 36) (const_int 0)]) ! 498: (pc) ! 499: (label_ref (match_operand 1 "" ""))))] ! 500: "" ! 501: "b%I0 %l1" ! 502: [(set_attr "type" "branch")]) ! 503: ! 504: (define_insn "" ! 505: [(set (pc) ! 506: (if_then_else ! 507: (match_operator 0 "comparison_operator" ! 508: [(match_operand:SI 1 "arith_operand" "d") ! 509: (match_operand:SI 2 "arith_operand" "dI")]) ! 510: (label_ref (match_operand 3 "" "")) ! 511: (pc)))] ! 512: "" ! 513: "cmp%S0%B0%R0 %2,%1,%l3" ! 514: [(set_attr "type" "branch")]) ! 515: ! 516: (define_insn "" ! 517: [(set (pc) ! 518: (if_then_else ! 519: (match_operator 0 "comparison_operator" ! 520: [(match_operand:SI 1 "arith_operand" "d") ! 521: (match_operand:SI 2 "arith_operand" "dI")]) ! 522: (pc) ! 523: (label_ref (match_operand 3 "" ""))))] ! 524: "" ! 525: "cmp%S0%B0%X0 %2,%1,%l3" ! 526: [(set_attr "type" "branch")]) ! 527: ! 528: ;; Normal move instructions. ! 529: ;; This code is based on the sparc machine desciption. ! 530: ! 531: (define_expand "movsi" ! 532: [(set (match_operand:SI 0 "general_operand" "") ! 533: (match_operand:SI 1 "general_operand" ""))] ! 534: "" ! 535: " ! 536: { ! 537: if (emit_move_sequence (operands, SImode)) ! 538: DONE; ! 539: }") ! 540: ! 541: ;; The store case can not be separate, because reload may convert a register ! 542: ;; to register move insn to a store (or load) insn without rerecognizing ! 543: ;; the insn. ! 544: ! 545: ;; Special pattern for zero stores to memory for functions which don't use ! 546: ;; the arg pointer. ! 547: ! 548: (define_insn "" ! 549: [(set (match_operand:SI 0 "general_operand" "=d,d,d,m") ! 550: (match_operand:SI 1 "general_operand" "dI,i,m,dJ"))] ! 551: "current_function_args_size == 0 ! 552: && (register_operand (operands[0], SImode) ! 553: || register_operand (operands[1], SImode) ! 554: || operands[1] == const0_rtx)" ! 555: "* ! 556: { ! 557: switch (which_alternative) ! 558: { ! 559: case 0: ! 560: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) ! 561: { ! 562: if (GET_CODE (operands[1]) == REG) ! 563: return \"lda (%1),%0\"; ! 564: else ! 565: return \"lda %1,%0\"; ! 566: } ! 567: return \"mov %1,%0\"; ! 568: case 1: ! 569: return i960_output_ldconst (operands[0], operands[1]); ! 570: case 2: ! 571: return \"ld %1,%0\"; ! 572: case 3: ! 573: if (operands[1] == const0_rtx) ! 574: return \"st g14,%0\"; ! 575: return \"st %1,%0\"; ! 576: } ! 577: }" ! 578: [(set_attr "type" "move,address,load,store") ! 579: (set_attr "length" "*,3,*,*")]) ! 580: ! 581: (define_insn "" ! 582: [(set (match_operand:SI 0 "general_operand" "=d,d,d,m") ! 583: (match_operand:SI 1 "general_operand" "dI,i,m,d"))] ! 584: "current_function_args_size != 0 ! 585: && (register_operand (operands[0], SImode) ! 586: || register_operand (operands[1], SImode))" ! 587: "* ! 588: { ! 589: switch (which_alternative) ! 590: { ! 591: case 0: ! 592: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) ! 593: { ! 594: if (GET_CODE (operands[1]) == REG) ! 595: return \"lda (%1),%0\"; ! 596: else ! 597: return \"lda %1,%0\"; ! 598: } ! 599: return \"mov %1,%0\"; ! 600: case 1: ! 601: return i960_output_ldconst (operands[0], operands[1]); ! 602: case 2: ! 603: return \"ld %1,%0\"; ! 604: case 3: ! 605: return \"st %1,%0\"; ! 606: } ! 607: }" ! 608: [(set_attr "type" "move,address,load,store") ! 609: (set_attr "length" "*,3,*,*")]) ! 610: ! 611: (define_expand "movhi" ! 612: [(set (match_operand:HI 0 "general_operand" "") ! 613: (match_operand:HI 1 "general_operand" ""))] ! 614: "" ! 615: " ! 616: { ! 617: if (emit_move_sequence (operands, HImode)) ! 618: DONE; ! 619: }") ! 620: ! 621: ;; Special pattern for zero stores to memory for functions which don't use ! 622: ;; the arg pointer. ! 623: ! 624: ;; The store case can not be separate. See above. ! 625: (define_insn "" ! 626: [(set (match_operand:HI 0 "general_operand" "=d,d,d,m") ! 627: (match_operand:HI 1 "general_operand" "dI,i,m,dJ"))] ! 628: "current_function_args_size == 0 ! 629: && (register_operand (operands[0], HImode) ! 630: || register_operand (operands[1], HImode) ! 631: || operands[1] == const0_rtx)" ! 632: "* ! 633: { ! 634: switch (which_alternative) ! 635: { ! 636: case 0: ! 637: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) ! 638: { ! 639: if (GET_CODE (operands[1]) == REG) ! 640: return \"lda (%1),%0\"; ! 641: else ! 642: return \"lda %1,%0\"; ! 643: } ! 644: return \"mov %1,%0\"; ! 645: case 1: ! 646: return i960_output_ldconst (operands[0], operands[1]); ! 647: case 2: ! 648: return \"ldos %1,%0\"; ! 649: case 3: ! 650: if (operands[1] == const0_rtx) ! 651: return \"stos g14,%0\"; ! 652: return \"stos %1,%0\"; ! 653: } ! 654: }" ! 655: [(set_attr "type" "move,misc,load,store") ! 656: (set_attr "length" "*,3,*,*")]) ! 657: ! 658: ;; The store case can not be separate. See above. ! 659: (define_insn "" ! 660: [(set (match_operand:HI 0 "general_operand" "=d,d,d,m") ! 661: (match_operand:HI 1 "general_operand" "dI,i,m,d"))] ! 662: "current_function_args_size != 0 ! 663: && (register_operand (operands[0], HImode) ! 664: || register_operand (operands[1], HImode))" ! 665: "* ! 666: { ! 667: switch (which_alternative) ! 668: { ! 669: case 0: ! 670: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) ! 671: { ! 672: if (GET_CODE (operands[1]) == REG) ! 673: return \"lda (%1),%0\"; ! 674: else ! 675: return \"lda %1,%0\"; ! 676: } ! 677: return \"mov %1,%0\"; ! 678: case 1: ! 679: return i960_output_ldconst (operands[0], operands[1]); ! 680: case 2: ! 681: return \"ldos %1,%0\"; ! 682: case 3: ! 683: return \"stos %1,%0\"; ! 684: } ! 685: }" ! 686: [(set_attr "type" "move,misc,load,store") ! 687: (set_attr "length" "*,3,*,*")]) ! 688: ! 689: (define_expand "movqi" ! 690: [(set (match_operand:QI 0 "general_operand" "") ! 691: (match_operand:QI 1 "general_operand" ""))] ! 692: "" ! 693: " ! 694: { ! 695: if (emit_move_sequence (operands, QImode)) ! 696: DONE; ! 697: }") ! 698: ! 699: ;; The store case can not be separate. See comment above. ! 700: (define_insn "" ! 701: [(set (match_operand:QI 0 "general_operand" "=d,d,d,m") ! 702: (match_operand:QI 1 "general_operand" "dI,i,m,dJ"))] ! 703: "current_function_args_size == 0 ! 704: && (register_operand (operands[0], QImode) ! 705: || register_operand (operands[1], QImode) ! 706: || operands[1] == const0_rtx)" ! 707: "* ! 708: { ! 709: switch (which_alternative) ! 710: { ! 711: case 0: ! 712: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) ! 713: { ! 714: if (GET_CODE (operands[1]) == REG) ! 715: return \"lda (%1),%0\"; ! 716: else ! 717: return \"lda %1,%0\"; ! 718: } ! 719: return \"mov %1,%0\"; ! 720: case 1: ! 721: return i960_output_ldconst (operands[0], operands[1]); ! 722: case 2: ! 723: return \"ldob %1,%0\"; ! 724: case 3: ! 725: if (operands[1] == const0_rtx) ! 726: return \"stob g14,%0\"; ! 727: return \"stob %1,%0\"; ! 728: } ! 729: }" ! 730: [(set_attr "type" "move,misc,load,store") ! 731: (set_attr "length" "*,3,*,*")]) ! 732: ! 733: ;; The store case can not be separate. See comment above. ! 734: (define_insn "" ! 735: [(set (match_operand:QI 0 "general_operand" "=d,d,d,m") ! 736: (match_operand:QI 1 "general_operand" "dI,i,m,d"))] ! 737: "current_function_args_size != 0 ! 738: && (register_operand (operands[0], QImode) ! 739: || register_operand (operands[1], QImode))" ! 740: "* ! 741: { ! 742: switch (which_alternative) ! 743: { ! 744: case 0: ! 745: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) ! 746: { ! 747: if (GET_CODE (operands[1]) == REG) ! 748: return \"lda (%1),%0\"; ! 749: else ! 750: return \"lda %1,%0\"; ! 751: } ! 752: return \"mov %1,%0\"; ! 753: case 1: ! 754: return i960_output_ldconst (operands[0], operands[1]); ! 755: case 2: ! 756: return \"ldob %1,%0\"; ! 757: case 3: ! 758: return \"stob %1,%0\"; ! 759: } ! 760: }" ! 761: [(set_attr "type" "move,misc,load,store") ! 762: (set_attr "length" "*,3,*,*")]) ! 763: ! 764: (define_expand "movdi" ! 765: [(set (match_operand:DI 0 "general_operand" "") ! 766: (match_operand:DI 1 "general_operand" ""))] ! 767: "" ! 768: " ! 769: { ! 770: if (emit_move_sequence (operands, DImode)) ! 771: DONE; ! 772: }") ! 773: ! 774: ;; The store case can not be separate. See comment above. ! 775: (define_insn "" ! 776: [(set (match_operand:DI 0 "general_operand" "=d,d,d,m") ! 777: (match_operand:DI 1 "general_operand" "dI,i,m,dJ"))] ! 778: "current_function_args_size == 0 ! 779: && (register_operand (operands[0], DImode) ! 780: || register_operand (operands[1], DImode) ! 781: || operands[1] == const0_rtx)" ! 782: "* ! 783: { ! 784: switch (which_alternative) ! 785: { ! 786: case 0: ! 787: return \"movl %1,%0\"; ! 788: case 1: ! 789: return i960_output_ldconst (operands[0], operands[1]); ! 790: case 2: ! 791: return \"ldl %1,%0\"; ! 792: case 3: ! 793: if (operands[1] == const0_rtx) ! 794: return \"st g14,%0\;st g14,4(%0)\"; ! 795: return \"stl %1,%0\"; ! 796: } ! 797: }" ! 798: [(set_attr "type" "move,load,load,store")]) ! 799: ! 800: ;; The store case can not be separate. See comment above. ! 801: (define_insn "" ! 802: [(set (match_operand:DI 0 "general_operand" "=d,d,d,m") ! 803: (match_operand:DI 1 "general_operand" "dI,i,m,d"))] ! 804: "current_function_args_size != 0 ! 805: && (register_operand (operands[0], DImode) ! 806: || register_operand (operands[1], DImode))" ! 807: "* ! 808: { ! 809: switch (which_alternative) ! 810: { ! 811: case 0: ! 812: return \"movl %1,%0\"; ! 813: case 1: ! 814: return i960_output_ldconst (operands[0], operands[1]); ! 815: case 2: ! 816: return \"ldl %1,%0\"; ! 817: case 3: ! 818: return \"stl %1,%0\"; ! 819: } ! 820: }" ! 821: [(set_attr "type" "move,load,load,store")]) ! 822: ! 823: (define_expand "movti" ! 824: [(set (match_operand:TI 0 "general_operand" "") ! 825: (match_operand:TI 1 "general_operand" ""))] ! 826: "" ! 827: " ! 828: { ! 829: if (emit_move_sequence (operands, TImode)) ! 830: DONE; ! 831: }") ! 832: ! 833: ;; The store case can not be separate. See comment above. ! 834: (define_insn "" ! 835: [(set (match_operand:TI 0 "general_operand" "=d,d,d,m") ! 836: (match_operand:TI 1 "general_operand" "dI,i,m,dJ"))] ! 837: "current_function_args_size == 0 ! 838: && (register_operand (operands[0], TImode) ! 839: || register_operand (operands[1], TImode) ! 840: || operands[1] == const0_rtx)" ! 841: "* ! 842: { ! 843: switch (which_alternative) ! 844: { ! 845: case 0: ! 846: return \"movq %1,%0\"; ! 847: case 1: ! 848: return i960_output_ldconst (operands[0], operands[1]); ! 849: case 2: ! 850: return \"ldq %1,%0\"; ! 851: case 3: ! 852: if (operands[1] == const0_rtx) ! 853: return \"st g14,%0\;st g14,4(%0)\;st g14,8(%0)\;st g14,12(%0)\"; ! 854: return \"stq %1,%0\"; ! 855: } ! 856: }" ! 857: [(set_attr "type" "move,load,load,store")]) ! 858: ! 859: ;; The store case can not be separate. See comment above. ! 860: (define_insn "" ! 861: [(set (match_operand:TI 0 "general_operand" "=d,d,d,m") ! 862: (match_operand:TI 1 "general_operand" "dI,i,m,d"))] ! 863: "current_function_args_size != 0 ! 864: && (register_operand (operands[0], TImode) ! 865: || register_operand (operands[1], TImode))" ! 866: "* ! 867: { ! 868: switch (which_alternative) ! 869: { ! 870: case 0: ! 871: return \"movq %1,%0\"; ! 872: case 1: ! 873: return i960_output_ldconst (operands[0], operands[1]); ! 874: case 2: ! 875: return \"ldq %1,%0\"; ! 876: case 3: ! 877: return \"stq %1,%0\"; ! 878: } ! 879: }" ! 880: [(set_attr "type" "move,load,load,store")]) ! 881: ! 882: (define_expand "store_multiple" ! 883: [(set (match_operand:SI 0 "" "") ;;- dest ! 884: (match_operand:SI 1 "" "")) ;;- src ! 885: (use (match_operand:SI 2 "" ""))] ;;- nregs ! 886: "" ! 887: " ! 888: { ! 889: int regno; ! 890: int count; ! 891: rtx from; ! 892: int i; ! 893: ! 894: if (GET_CODE (operands[0]) != MEM ! 895: || GET_CODE (operands[1]) != REG ! 896: || GET_CODE (operands[2]) != CONST_INT) ! 897: FAIL; ! 898: ! 899: count = INTVAL (operands[2]); ! 900: if (count > 12) ! 901: FAIL; ! 902: ! 903: regno = REGNO (operands[1]); ! 904: from = memory_address (SImode, XEXP (operands[0], 0)); ! 905: while (count >= 4 && ((regno & 3) == 0)) ! 906: { ! 907: emit_insn (gen_rtx (SET, VOIDmode, ! 908: gen_rtx (MEM, TImode, from), ! 909: gen_rtx (REG, TImode, regno))); ! 910: count -= 4; ! 911: regno += 4; ! 912: from = memory_address (TImode, plus_constant (from, 16)); ! 913: } ! 914: while (count >= 2 && ((regno & 1) == 0)) ! 915: { ! 916: emit_insn (gen_rtx (SET, VOIDmode, ! 917: gen_rtx (MEM, DImode, from), ! 918: gen_rtx (REG, DImode, regno))); ! 919: count -= 2; ! 920: regno += 2; ! 921: from = memory_address (DImode, plus_constant (from, 8)); ! 922: } ! 923: while (count > 0) ! 924: { ! 925: emit_insn (gen_rtx (SET, VOIDmode, ! 926: gen_rtx (MEM, SImode, from), ! 927: gen_rtx (REG, SImode, regno))); ! 928: count -= 1; ! 929: regno += 1; ! 930: from = memory_address (SImode, plus_constant (from, 4)); ! 931: } ! 932: DONE; ! 933: }") ! 934: ! 935: ;; Floating point move insns ! 936: ! 937: (define_expand "movdf" ! 938: [(set (match_operand:DF 0 "general_operand" "") ! 939: (match_operand:DF 1 "fpmove_src_operand" ""))] ! 940: "" ! 941: " ! 942: { ! 943: if (emit_move_sequence (operands, DFmode)) ! 944: DONE; ! 945: }") ! 946: ! 947: (define_insn "" ! 948: [(set (match_operand:DF 0 "general_operand" "=r,f,d,d,m") ! 949: (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,dG"))] ! 950: "current_function_args_size == 0 ! 951: && (register_operand (operands[0], DFmode) ! 952: || register_operand (operands[1], DFmode) ! 953: || operands[1] == CONST0_RTX (DFmode))" ! 954: "* ! 955: { ! 956: switch (which_alternative) ! 957: { ! 958: case 0: ! 959: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) ! 960: return \"movrl %1,%0\"; ! 961: else ! 962: return \"movl %1,%0\"; ! 963: case 1: ! 964: return \"movrl %1,%0\"; ! 965: case 2: ! 966: return i960_output_ldconst (operands[0], operands[1]); ! 967: case 3: ! 968: return \"ldl %1,%0\"; ! 969: case 4: ! 970: if (operands[1] == CONST0_RTX (DFmode)) ! 971: return \"st g14,%0\;st g14,4(%0)\"; ! 972: return \"stl %1,%0\"; ! 973: } ! 974: }" ! 975: [(set_attr "type" "move,move,load,fpload,fpstore")]) ! 976: ! 977: (define_insn "" ! 978: [(set (match_operand:DF 0 "general_operand" "=r,f,d,d,m") ! 979: (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d"))] ! 980: "current_function_args_size != 0 ! 981: && (register_operand (operands[0], DFmode) ! 982: || register_operand (operands[1], DFmode))" ! 983: "* ! 984: { ! 985: switch (which_alternative) ! 986: { ! 987: case 0: ! 988: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) ! 989: return \"movrl %1,%0\"; ! 990: else ! 991: return \"movl %1,%0\"; ! 992: case 1: ! 993: return \"movrl %1,%0\"; ! 994: case 2: ! 995: return i960_output_ldconst (operands[0], operands[1]); ! 996: case 3: ! 997: return \"ldl %1,%0\"; ! 998: case 4: ! 999: return \"stl %1,%0\"; ! 1000: } ! 1001: }" ! 1002: [(set_attr "type" "move,move,load,fpload,fpstore")]) ! 1003: ! 1004: (define_expand "movsf" ! 1005: [(set (match_operand:SF 0 "general_operand" "") ! 1006: (match_operand:SF 1 "fpmove_src_operand" ""))] ! 1007: "" ! 1008: " ! 1009: { ! 1010: if (emit_move_sequence (operands, SFmode)) ! 1011: DONE; ! 1012: }") ! 1013: ! 1014: (define_insn "" ! 1015: [(set (match_operand:SF 0 "general_operand" "=r,f,d,d,m") ! 1016: (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,dG"))] ! 1017: "current_function_args_size == 0 ! 1018: && (register_operand (operands[0], SFmode) ! 1019: || register_operand (operands[1], SFmode) ! 1020: || operands[1] == CONST0_RTX (SFmode))" ! 1021: "* ! 1022: { ! 1023: switch (which_alternative) ! 1024: { ! 1025: case 0: ! 1026: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) ! 1027: return \"movr %1,%0\"; ! 1028: else ! 1029: return \"mov %1,%0\"; ! 1030: case 1: ! 1031: return \"movr %1,%0\"; ! 1032: case 2: ! 1033: return i960_output_ldconst (operands[0], operands[1]); ! 1034: case 3: ! 1035: return \"ld %1,%0\"; ! 1036: case 4: ! 1037: if (operands[1] == CONST0_RTX (SFmode)) ! 1038: return \"st g14,%0\"; ! 1039: return \"st %1,%0\"; ! 1040: } ! 1041: }" ! 1042: [(set_attr "type" "move,move,load,fpload,fpstore")]) ! 1043: ! 1044: (define_insn "" ! 1045: [(set (match_operand:SF 0 "general_operand" "=r,f,d,d,m") ! 1046: (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,d"))] ! 1047: "current_function_args_size != 0 ! 1048: && (register_operand (operands[0], SFmode) ! 1049: || register_operand (operands[1], SFmode))" ! 1050: "* ! 1051: { ! 1052: switch (which_alternative) ! 1053: { ! 1054: case 0: ! 1055: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) ! 1056: return \"movr %1,%0\"; ! 1057: else ! 1058: return \"mov %1,%0\"; ! 1059: case 1: ! 1060: return \"movr %1,%0\"; ! 1061: case 2: ! 1062: return i960_output_ldconst (operands[0], operands[1]); ! 1063: case 3: ! 1064: return \"ld %1,%0\"; ! 1065: case 4: ! 1066: return \"st %1,%0\"; ! 1067: } ! 1068: }" ! 1069: [(set_attr "type" "move,move,load,fpload,fpstore")]) ! 1070: ! 1071: ;; Mixed-mode moves with sign and zero-extension. ! 1072: ! 1073: ;; Note that the one starting from HImode comes before those for QImode ! 1074: ;; so that a constant operand will match HImode, not QImode. ! 1075: ! 1076: (define_expand "extendhisi2" ! 1077: [(set (match_operand:SI 0 "register_operand" "") ! 1078: (sign_extend:SI ! 1079: (match_operand:HI 1 "nonimmediate_operand" "")))] ! 1080: "" ! 1081: " ! 1082: { ! 1083: if (GET_CODE (operand1) == REG ! 1084: || (GET_CODE (operand1) == SUBREG ! 1085: && GET_CODE (XEXP (operand1, 0)) == REG)) ! 1086: { ! 1087: rtx temp = gen_reg_rtx (SImode); ! 1088: rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16); ! 1089: int op1_subreg_word = 0; ! 1090: ! 1091: if (GET_CODE (operand1) == SUBREG) ! 1092: { ! 1093: op1_subreg_word = SUBREG_WORD (operand1); ! 1094: operand1 = SUBREG_REG (operand1); ! 1095: } ! 1096: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); ! 1097: ! 1098: emit_insn (gen_ashlsi3 (temp, operand1, shift_16)); ! 1099: emit_insn (gen_ashrsi3 (operand0, temp, shift_16)); ! 1100: DONE; ! 1101: } ! 1102: }") ! 1103: ! 1104: (define_insn "" ! 1105: [(set (match_operand:SI 0 "register_operand" "=d") ! 1106: (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] ! 1107: "" ! 1108: "ldis %1,%0" ! 1109: [(set_attr "type" "load")]) ! 1110: ! 1111: (define_expand "extendqisi2" ! 1112: [(set (match_operand:SI 0 "register_operand" "") ! 1113: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] ! 1114: "" ! 1115: " ! 1116: { ! 1117: if (GET_CODE (operand1) == REG ! 1118: || (GET_CODE (operand1) == SUBREG ! 1119: && GET_CODE (XEXP (operand1, 0)) == REG)) ! 1120: { ! 1121: rtx temp = gen_reg_rtx (SImode); ! 1122: rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); ! 1123: int op1_subreg_word = 0; ! 1124: ! 1125: if (GET_CODE (operand1) == SUBREG) ! 1126: { ! 1127: op1_subreg_word = SUBREG_WORD (operand1); ! 1128: operand1 = SUBREG_REG (operand1); ! 1129: } ! 1130: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word), ! 1131: ! 1132: emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); ! 1133: emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); ! 1134: DONE; ! 1135: } ! 1136: }") ! 1137: ! 1138: (define_insn "" ! 1139: [(set (match_operand:SI 0 "register_operand" "=d") ! 1140: (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] ! 1141: "" ! 1142: "ldib %1,%0" ! 1143: [(set_attr "type" "load")]) ! 1144: ! 1145: (define_expand "extendqihi2" ! 1146: [(set (match_operand:HI 0 "register_operand" "") ! 1147: (sign_extend:HI ! 1148: (match_operand:QI 1 "nonimmediate_operand" "")))] ! 1149: "" ! 1150: " ! 1151: { ! 1152: if (GET_CODE (operand1) == REG ! 1153: || (GET_CODE (operand1) == SUBREG ! 1154: && GET_CODE (XEXP (operand1, 0)) == REG)) ! 1155: { ! 1156: rtx temp = gen_reg_rtx (SImode); ! 1157: rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); ! 1158: int op0_subreg_word = 0; ! 1159: int op1_subreg_word = 0; ! 1160: ! 1161: if (GET_CODE (operand1) == SUBREG) ! 1162: { ! 1163: op1_subreg_word = SUBREG_WORD (operand1); ! 1164: operand1 = SUBREG_REG (operand1); ! 1165: } ! 1166: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); ! 1167: ! 1168: if (GET_CODE (operand0) == SUBREG) ! 1169: { ! 1170: op0_subreg_word = SUBREG_WORD (operand0); ! 1171: operand0 = SUBREG_REG (operand0); ! 1172: } ! 1173: if (GET_MODE (operand0) != SImode) ! 1174: operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word); ! 1175: ! 1176: emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); ! 1177: emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); ! 1178: DONE; ! 1179: } ! 1180: }") ! 1181: ! 1182: (define_insn "" ! 1183: [(set (match_operand:HI 0 "register_operand" "=d") ! 1184: (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))] ! 1185: "" ! 1186: "ldib %1,%0" ! 1187: [(set_attr "type" "load")]) ! 1188: ! 1189: (define_expand "zero_extendhisi2" ! 1190: [(set (match_operand:SI 0 "register_operand" "") ! 1191: (zero_extend:SI ! 1192: (match_operand:HI 1 "nonimmediate_operand" "")))] ! 1193: "" ! 1194: " ! 1195: { ! 1196: if (GET_CODE (operand1) == REG ! 1197: || (GET_CODE (operand1) == SUBREG ! 1198: && GET_CODE (XEXP (operand1, 0)) == REG)) ! 1199: { ! 1200: rtx temp = gen_reg_rtx (SImode); ! 1201: rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16); ! 1202: int op1_subreg_word = 0; ! 1203: ! 1204: if (GET_CODE (operand1) == SUBREG) ! 1205: { ! 1206: op1_subreg_word = SUBREG_WORD (operand1); ! 1207: operand1 = SUBREG_REG (operand1); ! 1208: } ! 1209: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); ! 1210: ! 1211: emit_insn (gen_ashlsi3 (temp, operand1, shift_16)); ! 1212: emit_insn (gen_lshrsi3 (operand0, temp, shift_16)); ! 1213: DONE; ! 1214: } ! 1215: }") ! 1216: ! 1217: (define_insn "" ! 1218: [(set (match_operand:SI 0 "register_operand" "=d") ! 1219: (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] ! 1220: "" ! 1221: "ldos %1,%0" ! 1222: [(set_attr "type" "load")]) ! 1223: ! 1224: ;; Using shifts here generates much better code than doing an `and 255'. ! 1225: ;; This is mainly because the `and' requires loading the constant separately, ! 1226: ;; the constant is likely to get optimized, and then the compiler can't ! 1227: ;; optimize the `and' because it doesn't know that one operand is a constant. ! 1228: ! 1229: (define_expand "zero_extendqisi2" ! 1230: [(set (match_operand:SI 0 "register_operand" "") ! 1231: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] ! 1232: "" ! 1233: " ! 1234: { ! 1235: if (GET_CODE (operand1) == REG ! 1236: || (GET_CODE (operand1) == SUBREG ! 1237: && GET_CODE (XEXP (operand1, 0)) == REG)) ! 1238: { ! 1239: rtx temp = gen_reg_rtx (SImode); ! 1240: rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); ! 1241: int op1_subreg_word = 0; ! 1242: ! 1243: if (GET_CODE (operand1) == SUBREG) ! 1244: { ! 1245: op1_subreg_word = SUBREG_WORD (operand1); ! 1246: operand1 = SUBREG_REG (operand1); ! 1247: } ! 1248: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); ! 1249: ! 1250: emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); ! 1251: emit_insn (gen_lshrsi3 (operand0, temp, shift_24)); ! 1252: DONE; ! 1253: } ! 1254: }") ! 1255: ! 1256: (define_insn "" ! 1257: [(set (match_operand:SI 0 "register_operand" "=d") ! 1258: (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] ! 1259: "" ! 1260: "ldob %1,%0" ! 1261: [(set_attr "type" "load")]) ! 1262: ! 1263: (define_expand "zero_extendqihi2" ! 1264: [(set (match_operand:HI 0 "register_operand" "") ! 1265: (zero_extend:HI ! 1266: (match_operand:QI 1 "nonimmediate_operand" "")))] ! 1267: "" ! 1268: " ! 1269: { ! 1270: if (GET_CODE (operand1) == REG ! 1271: || (GET_CODE (operand1) == SUBREG ! 1272: && GET_CODE (XEXP (operand1, 0)) == REG)) ! 1273: { ! 1274: rtx temp = gen_reg_rtx (SImode); ! 1275: rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); ! 1276: int op0_subreg_word = 0; ! 1277: int op1_subreg_word = 0; ! 1278: ! 1279: if (GET_CODE (operand1) == SUBREG) ! 1280: { ! 1281: op1_subreg_word = SUBREG_WORD (operand1); ! 1282: operand1 = SUBREG_REG (operand1); ! 1283: } ! 1284: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); ! 1285: ! 1286: if (GET_CODE (operand0) == SUBREG) ! 1287: { ! 1288: op0_subreg_word = SUBREG_WORD (operand0); ! 1289: operand0 = SUBREG_REG (operand0); ! 1290: } ! 1291: if (GET_MODE (operand0) != SImode) ! 1292: operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word); ! 1293: ! 1294: emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); ! 1295: emit_insn (gen_lshrsi3 (operand0, temp, shift_24)); ! 1296: DONE; ! 1297: } ! 1298: }") ! 1299: ! 1300: (define_insn "" ! 1301: [(set (match_operand:HI 0 "register_operand" "=d") ! 1302: (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] ! 1303: "" ! 1304: "ldob %1,%0" ! 1305: [(set_attr "type" "load")]) ! 1306: ! 1307: ;; Conversions between float and double. ! 1308: ! 1309: (define_insn "extendsfdf2" ! 1310: [(set (match_operand:DF 0 "register_operand" "=f,d") ! 1311: (float_extend:DF (match_operand:SF 1 "fp_arith_operand" "dGH,fGH")))] ! 1312: "TARGET_NUMERICS" ! 1313: "@ ! 1314: movr %1,%0 ! 1315: movrl %1,%0" ! 1316: [(set_attr "type" "fpmove")]) ! 1317: ! 1318: (define_insn "truncdfsf2" ! 1319: [(set (match_operand:SF 0 "register_operand" "=d") ! 1320: (float_truncate:SF ! 1321: (match_operand:DF 1 "fp_arith_operand" "fGH")))] ! 1322: "TARGET_NUMERICS" ! 1323: "movr %1,%0" ! 1324: [(set_attr "type" "fpmove")]) ! 1325: ! 1326: ;; Conversion between fixed point and floating point. ! 1327: ! 1328: (define_insn "floatsidf2" ! 1329: [(set (match_operand:DF 0 "register_operand" "=f") ! 1330: (float:DF (match_operand:SI 1 "register_operand" "d")))] ! 1331: "TARGET_NUMERICS" ! 1332: "cvtir %1,%0" ! 1333: [(set_attr "type" "fpcvt")]) ! 1334: ! 1335: (define_insn "floatsisf2" ! 1336: [(set (match_operand:SF 0 "register_operand" "=df") ! 1337: (float:SF (match_operand:SI 1 "register_operand" "d")))] ! 1338: "TARGET_NUMERICS" ! 1339: "cvtir %1,%0" ! 1340: [(set_attr "type" "fpcvt")]) ! 1341: ! 1342: ;; Convert a float to an actual integer. ! 1343: ;; Truncation is performed as part of the conversion. ! 1344: ;; The i960 requires conversion from DFmode to DImode to make ! 1345: ;; unsigned conversions work properly. ! 1346: ! 1347: (define_insn "fixuns_truncdfdi2" ! 1348: [(set (match_operand:DI 0 "register_operand" "=d") ! 1349: (unsigned_fix:DI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))] ! 1350: "TARGET_NUMERICS" ! 1351: "cvtzril %1,%0" ! 1352: [(set_attr "type" "fpcvt")]) ! 1353: ! 1354: (define_insn "fixuns_truncsfdi2" ! 1355: [(set (match_operand:DI 0 "register_operand" "=d") ! 1356: (unsigned_fix:DI (fix:SF (match_operand:SF 1 "fp_arith_operand" "fGH"))))] ! 1357: "TARGET_NUMERICS" ! 1358: "cvtzril %1,%0" ! 1359: [(set_attr "type" "fpcvt")]) ! 1360: ! 1361: (define_insn "fix_truncdfsi2" ! 1362: [(set (match_operand:SI 0 "register_operand" "=d") ! 1363: (fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))] ! 1364: "TARGET_NUMERICS" ! 1365: "cvtzri %1,%0" ! 1366: [(set_attr "type" "fpcvt")]) ! 1367: ! 1368: (define_expand "fixuns_truncdfsi2" ! 1369: [(set (match_operand:SI 0 "register_operand" "") ! 1370: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" ""))))] ! 1371: "TARGET_NUMERICS" ! 1372: " ! 1373: { ! 1374: rtx temp = gen_reg_rtx (DImode); ! 1375: emit_insn (gen_rtx (SET, VOIDmode, temp, ! 1376: gen_rtx (UNSIGNED_FIX, DImode, ! 1377: gen_rtx (FIX, DFmode, operands[1])))); ! 1378: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 1379: gen_rtx (SUBREG, SImode, temp, 0))); ! 1380: DONE; ! 1381: }") ! 1382: ! 1383: (define_insn "fix_truncsfsi2" ! 1384: [(set (match_operand:SI 0 "register_operand" "=d") ! 1385: (fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" "dfGH"))))] ! 1386: "TARGET_NUMERICS" ! 1387: "cvtzri %1,%0" ! 1388: [(set_attr "type" "fpcvt")]) ! 1389: ! 1390: (define_expand "fixuns_truncsfsi2" ! 1391: [(set (match_operand:SI 0 "register_operand" "") ! 1392: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" ""))))] ! 1393: "TARGET_NUMERICS" ! 1394: " ! 1395: { ! 1396: rtx temp = gen_reg_rtx (DImode); ! 1397: emit_insn (gen_rtx (SET, VOIDmode, temp, ! 1398: gen_rtx (UNSIGNED_FIX, DImode, ! 1399: gen_rtx (FIX, SFmode, operands[1])))); ! 1400: emit_insn (gen_rtx (SET, VOIDmode, operands[0], ! 1401: gen_rtx (SUBREG, SImode, temp, 0))); ! 1402: DONE; ! 1403: }") ! 1404: ! 1405: ;; Arithmetic instructions. ! 1406: ! 1407: (define_insn "subsi3" ! 1408: [(set (match_operand:SI 0 "register_operand" "=d") ! 1409: (minus:SI (match_operand:SI 1 "arith_operand" "dI") ! 1410: (match_operand:SI 2 "arith_operand" "dI")))] ! 1411: "" ! 1412: "subo %2,%1,%0") ! 1413: ! 1414: ;; Try to generate an lda instruction when it would be faster than an ! 1415: ;; add instruction. ! 1416: ;; Some assemblers apparently won't accept two addresses added together. ! 1417: ! 1418: (define_insn "" ! 1419: [(set (match_operand:SI 0 "register_operand" "=d,d,d") ! 1420: (plus:SI (match_operand:SI 1 "arith32_operand" "%dn,i,dn") ! 1421: (match_operand:SI 2 "arith32_operand" "dn,dn,i")))] ! 1422: "(TARGET_C_SERIES) && (CONSTANT_P (operands[1]) || CONSTANT_P (operands[2]))" ! 1423: "* ! 1424: { ! 1425: if (GET_CODE (operands[1]) == CONST_INT) ! 1426: { ! 1427: rtx tmp = operands[1]; ! 1428: operands[1] = operands[2]; ! 1429: operands[2] = tmp; ! 1430: } ! 1431: if (GET_CODE (operands[2]) == CONST_INT ! 1432: && GET_CODE (operands[1]) == REG ! 1433: && i960_last_insn_type != I_TYPE_REG) ! 1434: { ! 1435: if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) > -32) ! 1436: return \"subo %n2,%1,%0\"; ! 1437: else if (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32) ! 1438: return \"addo %1,%2,%0\"; ! 1439: } ! 1440: if (CONSTANT_P (operands[1])) ! 1441: return \"lda %1+%2,%0\"; ! 1442: return \"lda %2(%1),%0\"; ! 1443: }") ! 1444: ! 1445: (define_insn "addsi3" ! 1446: [(set (match_operand:SI 0 "register_operand" "=d") ! 1447: (plus:SI (match_operand:SI 1 "signed_arith_operand" "%dI") ! 1448: (match_operand:SI 2 "signed_arith_operand" "dIK")))] ! 1449: "" ! 1450: "* ! 1451: { ! 1452: if (GET_CODE (operands[2]) == CONST_INT ! 1453: && INTVAL (operands[2]) < 0 && INTVAL (operands[2]) > -32) ! 1454: return \"subo %n2,%1,%0\"; ! 1455: if (i960_bypass (insn, operands[1], operands[2], 0)) ! 1456: return \"addo %2,%1,%0\"; ! 1457: return \"addo %1,%2,%0\"; ! 1458: }") ! 1459: ! 1460: (define_insn "mulsi3" ! 1461: [(set (match_operand:SI 0 "register_operand" "=d") ! 1462: (mult:SI (match_operand:SI 1 "arith_operand" "%dI") ! 1463: (match_operand:SI 2 "arith_operand" "dI")))] ! 1464: "" ! 1465: "* ! 1466: { ! 1467: if (i960_bypass (insn, operands[1], operands[2], 0)) ! 1468: return \"mulo %2,%1,%0\"; ! 1469: return \"mulo %1,%2,%0\"; ! 1470: }" ! 1471: [(set_attr "type" "mult")]) ! 1472: ! 1473: ;; This goes after the move/add/sub/mul instructions ! 1474: ;; because those instructions are better when they apply. ! 1475: ! 1476: (define_insn "" ! 1477: [(set (match_operand:SI 0 "register_operand" "=d") ! 1478: (match_operand:SI 1 "address_operand" "p"))] ! 1479: "" ! 1480: "lda %a1,%0" ! 1481: [(set_attr "type" "load")]) ! 1482: ! 1483: ;; This will never be selected because of an "optimization" that GCC does. ! 1484: ;; It always converts divides by a power of 2 into a sequence of instructions ! 1485: ;; that does a right shift, and then corrects the result if it was negative. ! 1486: ! 1487: ;; (define_insn "" ! 1488: ;; [(set (match_operand:SI 0 "register_operand" "=d") ! 1489: ;; (div:SI (match_operand:SI 1 "arith_operand" "dI") ! 1490: ;; (match_operand:SI 2 "power2_operand" "nI")))] ! 1491: ;; "" ! 1492: ;; "*{ ! 1493: ;; operands[2] = gen_rtx(CONST_INT, VOIDmode,bitpos (INTVAL (operands[2]))); ! 1494: ;; return \"shrdi %2,%1,%0\"; ! 1495: ;; }" ! 1496: ! 1497: (define_insn "divsi3" ! 1498: [(set (match_operand:SI 0 "register_operand" "=d") ! 1499: (div:SI (match_operand:SI 1 "arith_operand" "dI") ! 1500: (match_operand:SI 2 "arith_operand" "dI")))] ! 1501: "" ! 1502: "divi %2,%1,%0" ! 1503: [(set_attr "type" "div")]) ! 1504: ! 1505: (define_insn "udivsi3" ! 1506: [(set (match_operand:SI 0 "register_operand" "=d") ! 1507: (udiv:SI (match_operand:SI 1 "arith_operand" "dI") ! 1508: (match_operand:SI 2 "arith_operand" "dI")))] ! 1509: "" ! 1510: "divo %2,%1,%0" ! 1511: [(set_attr "type" "div")]) ! 1512: ! 1513: ;; We must use `remi' not `modi' here, to ensure that `%' has the effects ! 1514: ;; specified by the ANSI C standard. ! 1515: ! 1516: (define_insn "modsi3" ! 1517: [(set (match_operand:SI 0 "register_operand" "=d") ! 1518: (mod:SI (match_operand:SI 1 "arith_operand" "dI") ! 1519: (match_operand:SI 2 "arith_operand" "dI")))] ! 1520: "" ! 1521: "remi %2,%1,%0" ! 1522: [(set_attr "type" "div")]) ! 1523: ! 1524: (define_insn "umodsi3" ! 1525: [(set (match_operand:SI 0 "register_operand" "=d") ! 1526: (umod:SI (match_operand:SI 1 "arith_operand" "dI") ! 1527: (match_operand:SI 2 "arith_operand" "dI")))] ! 1528: "" ! 1529: "remo %2,%1,%0" ! 1530: [(set_attr "type" "div")]) ! 1531: ! 1532: ;; And instructions (with complement also). ! 1533: ! 1534: (define_insn "andsi3" ! 1535: [(set (match_operand:SI 0 "register_operand" "=d") ! 1536: (and:SI (match_operand:SI 1 "arith_operand" "%dI") ! 1537: (match_operand:SI 2 "arith_operand" "dI")))] ! 1538: "" ! 1539: "* ! 1540: { ! 1541: if (i960_bypass (insn, operands[1], operands[2], 0)) ! 1542: return \"and %2,%1,%0\"; ! 1543: return \"and %1,%2,%0\"; ! 1544: }") ! 1545: ! 1546: (define_insn "" ! 1547: [(set (match_operand:SI 0 "register_operand" "=d") ! 1548: (and:SI (not:SI (match_operand:SI 1 "arith_operand" "dI")) ! 1549: (match_operand:SI 2 "arith_operand" "dI")))] ! 1550: "" ! 1551: "* ! 1552: { ! 1553: if (i960_bypass (insn, operands[1], operands[2], 0)) ! 1554: return \"notand %2,%1,%0\"; ! 1555: return \"andnot %1,%2,%0\"; ! 1556: }") ! 1557: ! 1558: (define_insn "" ! 1559: [(set (match_operand:SI 0 "register_operand" "=d") ! 1560: (ior:SI (not:SI (match_operand:SI 1 "arith_operand" "%dI")) ! 1561: (not:SI (match_operand:SI 2 "arith_operand" "dI"))))] ! 1562: "" ! 1563: "* ! 1564: { ! 1565: if (i960_bypass (insn, operands[1], operands[2], 0)) ! 1566: return \"nand %2,%1,%0\"; ! 1567: return \"nand %1,%2,%0\"; ! 1568: }") ! 1569: ! 1570: (define_insn "" ! 1571: [(set (match_operand:SI 0 "register_operand" "=d") ! 1572: (not:SI (and:SI (match_operand:SI 1 "arith_operand" "%dI") ! 1573: (match_operand:SI 2 "arith_operand" "dI"))))] ! 1574: "" ! 1575: "* ! 1576: { ! 1577: if (i960_bypass (insn, operands[1], operands[2], 0)) ! 1578: return \"nand %2,%1,%0\"; ! 1579: return \"nand %1,%2,%0\"; ! 1580: }") ! 1581: ! 1582: (define_insn "" ! 1583: [(set (match_operand:SI 0 "register_operand" "=d") ! 1584: (ior:SI (match_operand:SI 1 "arith_operand" "dI") ! 1585: (match_operand:SI 2 "power2_operand" "n")))] ! 1586: "" ! 1587: "* ! 1588: { ! 1589: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1590: bitpos (INTVAL (operands[2]))); ! 1591: return \"setbit %2,%1,%0\"; ! 1592: }") ! 1593: ! 1594: (define_insn "" ! 1595: [(set (match_operand:SI 0 "register_operand" "=d") ! 1596: (ior:SI (match_operand:SI 1 "power2_operand" "n") ! 1597: (match_operand:SI 2 "arith_operand" "dI")))] ! 1598: "" ! 1599: "* ! 1600: { ! 1601: operands[1] = gen_rtx (CONST_INT, VOIDmode, ! 1602: bitpos (INTVAL (operands[1]))); ! 1603: return \"setbit %1,%2,%0\"; ! 1604: }") ! 1605: ! 1606: (define_insn "iorsi3" ! 1607: [(set (match_operand:SI 0 "register_operand" "=d") ! 1608: (ior:SI (match_operand:SI 1 "arith_operand" "%dI") ! 1609: (match_operand:SI 2 "arith_operand" "dI")))] ! 1610: "" ! 1611: "* ! 1612: { ! 1613: if (i960_bypass (insn, operands[1], operands[2], 0)) ! 1614: return \"or %2,%1,%0\"; ! 1615: return \"or %1,%2,%0\"; ! 1616: }") ! 1617: ! 1618: (define_insn "" ! 1619: [(set (match_operand:SI 0 "register_operand" "=d") ! 1620: (ior:SI (not:SI (match_operand:SI 1 "arith_operand" "dI")) ! 1621: (match_operand:SI 2 "arith_operand" "dI")))] ! 1622: "" ! 1623: "* ! 1624: { ! 1625: if (i960_bypass (insn, operands[1], operands[2], 0)) ! 1626: return \"notor %2,%1,%0\"; ! 1627: return \"ornot %1,%2,%0\"; ! 1628: }") ! 1629: ! 1630: (define_insn "" ! 1631: [(set (match_operand:SI 0 "register_operand" "=d") ! 1632: (and:SI (not:SI (match_operand:SI 1 "arith_operand" "%dI")) ! 1633: (not:SI (match_operand:SI 2 "arith_operand" "dI"))))] ! 1634: "" ! 1635: "* ! 1636: { ! 1637: if (i960_bypass (insn, operands[1], operands[2], 0)) ! 1638: return \"nor %2,%1,%0\"; ! 1639: return \"nor %1,%2,%0\"; ! 1640: }") ! 1641: ! 1642: (define_insn "" ! 1643: [(set (match_operand:SI 0 "register_operand" "=d") ! 1644: (not:SI (ior:SI (match_operand:SI 1 "arith_operand" "%dI") ! 1645: (match_operand:SI 2 "arith_operand" "dI"))))] ! 1646: "" ! 1647: "* ! 1648: { ! 1649: if (i960_bypass (insn, operands[1], operands[2], 0)) ! 1650: return \"nor %2,%1,%0\"; ! 1651: return \"nor %1,%2,%0\"; ! 1652: }") ! 1653: ! 1654: (define_insn "xorsi3" ! 1655: [(set (match_operand:SI 0 "register_operand" "=d") ! 1656: (xor:SI (match_operand:SI 1 "arith_operand" "%dI") ! 1657: (match_operand:SI 2 "arith_operand" "dI")))] ! 1658: "" ! 1659: "* ! 1660: { ! 1661: if (i960_bypass (insn, operands[1], operands[2], 0)) ! 1662: return \"xor %2,%1,%0\"; ! 1663: return \"xor %1,%2,%0\"; ! 1664: }") ! 1665: ! 1666: (define_insn "" ! 1667: [(set (match_operand:SI 0 "register_operand" "=d") ! 1668: (not:SI (xor:SI (match_operand:SI 1 "arith_operand" "%dI") ! 1669: (match_operand:SI 2 "arith_operand" "dI"))))] ! 1670: "" ! 1671: "* ! 1672: { ! 1673: if (i960_bypass (insn, operands[1], operands[2], 0)) ! 1674: return \"xnor %2,%1,%0\"; ! 1675: return \"xnor %2,%1,%0\"; ! 1676: }") ! 1677: ! 1678: (define_insn "negsi2" ! 1679: [(set (match_operand:SI 0 "register_operand" "=d") ! 1680: (neg:SI (match_operand:SI 1 "arith_operand" "dI")))] ! 1681: "" ! 1682: "subo %1,0,%0" ! 1683: [(set_attr "length" "1")]) ! 1684: ! 1685: (define_insn "one_cmplsi2" ! 1686: [(set (match_operand:SI 0 "register_operand" "=d") ! 1687: (not:SI (match_operand:SI 1 "arith_operand" "dI")))] ! 1688: "" ! 1689: "not %1,%0" ! 1690: [(set_attr "length" "1")]) ! 1691: ! 1692: ;; Floating point arithmetic instructions. ! 1693: ! 1694: (define_insn "adddf3" ! 1695: [(set (match_operand:DF 0 "register_operand" "=d") ! 1696: (plus:DF (match_operand:DF 1 "fp_arith_operand" "%rGH") ! 1697: (match_operand:DF 2 "fp_arith_operand" "rGH")))] ! 1698: "TARGET_NUMERICS" ! 1699: "addrl %1,%2,%0" ! 1700: [(set_attr "type" "fpadd")]) ! 1701: ! 1702: (define_insn "addsf3" ! 1703: [(set (match_operand:SF 0 "register_operand" "=d") ! 1704: (plus:SF (match_operand:SF 1 "fp_arith_operand" "%rGH") ! 1705: (match_operand:SF 2 "fp_arith_operand" "rGH")))] ! 1706: "TARGET_NUMERICS" ! 1707: "addr %1,%2,%0" ! 1708: [(set_attr "type" "fpadd")]) ! 1709: ! 1710: ! 1711: (define_insn "subdf3" ! 1712: [(set (match_operand:DF 0 "register_operand" "=d") ! 1713: (minus:DF (match_operand:DF 1 "fp_arith_operand" "rGH") ! 1714: (match_operand:DF 2 "fp_arith_operand" "rGH")))] ! 1715: "TARGET_NUMERICS" ! 1716: "subrl %2,%1,%0" ! 1717: [(set_attr "type" "fpadd")]) ! 1718: ! 1719: (define_insn "subsf3" ! 1720: [(set (match_operand:SF 0 "register_operand" "=d") ! 1721: (minus:SF (match_operand:SF 1 "fp_arith_operand" "rGH") ! 1722: (match_operand:SF 2 "fp_arith_operand" "rGH")))] ! 1723: "TARGET_NUMERICS" ! 1724: "subr %2,%1,%0" ! 1725: [(set_attr "type" "fpadd")]) ! 1726: ! 1727: ! 1728: (define_insn "muldf3" ! 1729: [(set (match_operand:DF 0 "register_operand" "=d") ! 1730: (mult:DF (match_operand:DF 1 "fp_arith_operand" "rGH") ! 1731: (match_operand:DF 2 "fp_arith_operand" "rGH")))] ! 1732: "TARGET_NUMERICS" ! 1733: "mulrl %1,%2,%0" ! 1734: [(set_attr "type" "fpmul")]) ! 1735: ! 1736: (define_insn "mulsf3" ! 1737: [(set (match_operand:SF 0 "register_operand" "=d") ! 1738: (mult:SF (match_operand:SF 1 "fp_arith_operand" "rGH") ! 1739: (match_operand:SF 2 "fp_arith_operand" "rGH")))] ! 1740: "TARGET_NUMERICS" ! 1741: "mulr %1,%2,%0" ! 1742: [(set_attr "type" "fpmul")]) ! 1743: ! 1744: ! 1745: (define_insn "divdf3" ! 1746: [(set (match_operand:DF 0 "register_operand" "=d") ! 1747: (div:DF (match_operand:DF 1 "fp_arith_operand" "rGH") ! 1748: (match_operand:DF 2 "fp_arith_operand" "rGH")))] ! 1749: "TARGET_NUMERICS" ! 1750: "divrl %2,%1,%0" ! 1751: [(set_attr "type" "fpdiv")]) ! 1752: ! 1753: (define_insn "divsf3" ! 1754: [(set (match_operand:SF 0 "register_operand" "=d") ! 1755: (div:SF (match_operand:SF 1 "fp_arith_operand" "rGH") ! 1756: (match_operand:SF 2 "fp_arith_operand" "rGH")))] ! 1757: "TARGET_NUMERICS" ! 1758: "divr %2,%1,%0" ! 1759: [(set_attr "type" "fpdiv")]) ! 1760: ! 1761: (define_insn "negdf2" ! 1762: [(set (match_operand:DF 0 "register_operand" "=d,f") ! 1763: (neg:DF (match_operand:DF 1 "register_operand" "d,r")))] ! 1764: "" ! 1765: "* ! 1766: { ! 1767: if (which_alternative == 0) ! 1768: { ! 1769: if (REGNO (operands[0]) == REGNO (operands[1])) ! 1770: return \"notbit 31,%D1,%D0\"; ! 1771: return \"mov %1,%0\;notbit 31,%D1,%D0\"; ! 1772: } ! 1773: return \"subrl %1,0f0.0,%0\"; ! 1774: }" ! 1775: [(set_attr "type" "fpadd")]) ! 1776: ! 1777: (define_insn "negsf2" ! 1778: [(set (match_operand:SF 0 "register_operand" "=d,f") ! 1779: (neg:SF (match_operand:SF 1 "register_operand" "d,r")))] ! 1780: "" ! 1781: "@ ! 1782: notbit 31,%1,%0 ! 1783: subr %1,0f0.0,%0" ! 1784: [(set_attr "type" "fpadd")]) ! 1785: ! 1786: ;;; The abs patterns also work even if the target machine doesn't have ! 1787: ;;; floating point, because in that case dstreg and srcreg will always be ! 1788: ;;; less than 32. ! 1789: ! 1790: (define_insn "absdf2" ! 1791: [(set (match_operand:DF 0 "register_operand" "=df") ! 1792: (abs:DF (match_operand:DF 1 "register_operand" "df")))] ! 1793: "" ! 1794: "* ! 1795: { ! 1796: int dstreg = REGNO (operands[0]); ! 1797: int srcreg = REGNO (operands[1]); ! 1798: ! 1799: if (dstreg < 32) ! 1800: { ! 1801: if (srcreg < 32) ! 1802: { ! 1803: if (dstreg != srcreg) ! 1804: output_asm_insn (\"mov %1,%0\", operands); ! 1805: return \"clrbit 31,%D1,%D0\"; ! 1806: } ! 1807: /* Src is an fp reg. */ ! 1808: return \"movrl %1,%0\;clrbit 31,%D1,%D0\"; ! 1809: } ! 1810: if (srcreg >= 32) ! 1811: return \"cpysre %1,0f0.0,%0\"; ! 1812: return \"movrl %1,%0\;cpysre %0,0f0.0,%0\"; ! 1813: }" ! 1814: [(set_attr "type" "multi")]) ! 1815: ! 1816: (define_insn "abssf2" ! 1817: [(set (match_operand:SF 0 "register_operand" "=df") ! 1818: (abs:SF (match_operand:SF 1 "register_operand" "df")))] ! 1819: "" ! 1820: "* ! 1821: { ! 1822: int dstreg = REGNO (operands[0]); ! 1823: int srcreg = REGNO (operands[1]); ! 1824: ! 1825: if (dstreg < 32 && srcreg < 32) ! 1826: return \"clrbit 31,%1,%0\"; ! 1827: ! 1828: if (dstreg >= 32 && srcreg >= 32) ! 1829: return \"cpysre %1,0f0.0,%0\"; ! 1830: ! 1831: if (dstreg < 32) ! 1832: return \"movr %1,%0\;clrbit 31,%0,%0\"; ! 1833: ! 1834: return \"movr %1,%0\;cpysre %0,0f0.0,%0\"; ! 1835: }" ! 1836: [(set_attr "type" "multi")]) ! 1837: ! 1838: ;; Tetra (16 byte) float support. ! 1839: ! 1840: (define_insn "cmptf" ! 1841: [(set (reg:CC 36) ! 1842: (compare:CC (match_operand:TF 0 "register_operand" "f") ! 1843: (match_operand:TF 1 "nonmemory_operand" "fG")))] ! 1844: "TARGET_NUMERICS" ! 1845: "cmpr %0,%1" ! 1846: [(set_attr "type" "fpcc")]) ! 1847: ! 1848: (define_expand "movtf" ! 1849: [(set (match_operand:TF 0 "general_operand" "") ! 1850: (match_operand:TF 1 "fpmove_src_operand" ""))] ! 1851: "" ! 1852: " ! 1853: { ! 1854: if (emit_move_sequence (operands, TFmode)) ! 1855: DONE; ! 1856: }") ! 1857: ! 1858: (define_insn "" ! 1859: [(set (match_operand:TF 0 "general_operand" "=r,f,d,d,m") ! 1860: (match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,dG"))] ! 1861: "current_function_args_size == 0 ! 1862: && (register_operand (operands[0], TFmode) ! 1863: || register_operand (operands[1], TFmode) ! 1864: || operands[1] == CONST0_RTX (TFmode))" ! 1865: "* ! 1866: { ! 1867: switch (which_alternative) ! 1868: { ! 1869: case 0: ! 1870: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) ! 1871: return \"movre %1,%0\"; ! 1872: else ! 1873: return \"movq %1,%0\"; ! 1874: case 1: ! 1875: return \"movre %1,%0\"; ! 1876: case 2: ! 1877: return i960_output_ldconst (operands[0], operands[1]); ! 1878: case 3: ! 1879: return \"ldq %1,%0\"; ! 1880: case 4: ! 1881: if (operands[1] == CONST0_RTX (TFmode)) ! 1882: return \"st g14,%0\;st g14,4(%0)\;st g14,8(%0)\;st g14,12(%0)\"; ! 1883: return \"stq %1,%0\"; ! 1884: } ! 1885: }" ! 1886: [(set_attr "type" "move,move,load,fpload,fpstore")]) ! 1887: ! 1888: (define_insn "" ! 1889: [(set (match_operand:TF 0 "general_operand" "=r,f,d,d,m") ! 1890: (match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d"))] ! 1891: "current_function_args_size != 0 ! 1892: && (register_operand (operands[0], TFmode) ! 1893: || register_operand (operands[1], TFmode))" ! 1894: "* ! 1895: { ! 1896: switch (which_alternative) ! 1897: { ! 1898: case 0: ! 1899: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) ! 1900: return \"movre %1,%0\"; ! 1901: else ! 1902: return \"movq %1,%0\"; ! 1903: case 1: ! 1904: return \"movre %1,%0\"; ! 1905: case 2: ! 1906: return i960_output_ldconst (operands[0], operands[1]); ! 1907: case 3: ! 1908: return \"ldq %1,%0\"; ! 1909: case 4: ! 1910: return \"stq %1,%0\"; ! 1911: } ! 1912: }" ! 1913: [(set_attr "type" "move,move,load,fpload,fpstore")]) ! 1914: ! 1915: (define_insn "extendsftf2" ! 1916: [(set (match_operand:TF 0 "register_operand" "=f,d") ! 1917: (float_extend:TF ! 1918: (match_operand:SF 1 "register_operand" "d,f")))] ! 1919: "TARGET_NUMERICS" ! 1920: "@ ! 1921: movr %1,%0 ! 1922: movre %1,%0" ! 1923: [(set_attr "type" "fpmove")]) ! 1924: ! 1925: (define_insn "extenddftf2" ! 1926: [(set (match_operand:TF 0 "register_operand" "=f,d") ! 1927: (float_extend:TF ! 1928: (match_operand:DF 1 "register_operand" "d,f")))] ! 1929: "TARGET_NUMERICS" ! 1930: "@ ! 1931: movrl %1,%0 ! 1932: movre %1,%0" ! 1933: [(set_attr "type" "fpmove")]) ! 1934: ! 1935: (define_insn "trunctfdf2" ! 1936: [(set (match_operand:DF 0 "register_operand" "=d") ! 1937: (float_truncate:DF ! 1938: (match_operand:TF 1 "register_operand" "f")))] ! 1939: "TARGET_NUMERICS" ! 1940: "movrl %1,%0" ! 1941: [(set_attr "type" "fpmove")]) ! 1942: ! 1943: (define_insn "trunctfsf2" ! 1944: [(set (match_operand:SF 0 "register_operand" "=d") ! 1945: (float_truncate:SF ! 1946: (match_operand:TF 1 "register_operand" "f")))] ! 1947: "TARGET_NUMERICS" ! 1948: "movr %1,%0" ! 1949: [(set_attr "type" "fpmove")]) ! 1950: ! 1951: (define_insn "floatsitf2" ! 1952: [(set (match_operand:TF 0 "register_operand" "=f") ! 1953: (float:TF (match_operand:SI 1 "register_operand" "d")))] ! 1954: "TARGET_NUMERICS" ! 1955: "cvtir %1,%0" ! 1956: [(set_attr "type" "fpcvt")]) ! 1957: ! 1958: (define_insn "fix_trunctfsi2" ! 1959: [(set (match_operand:SI 0 "register_operand" "=d") ! 1960: (fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))] ! 1961: "TARGET_NUMERICS" ! 1962: "cvtzri %1,%0" ! 1963: [(set_attr "type" "fpcvt")]) ! 1964: ! 1965: (define_insn "fixuns_trunctfsi2" ! 1966: [(set (match_operand:SI 0 "register_operand" "=d") ! 1967: (unsigned_fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))] ! 1968: "TARGET_NUMERICS" ! 1969: "cvtzri %1,%0" ! 1970: [(set_attr "type" "fpcvt")]) ! 1971: ! 1972: (define_insn "addtf3" ! 1973: [(set (match_operand:TF 0 "register_operand" "=f") ! 1974: (plus:TF (match_operand:TF 1 "nonmemory_operand" "%fG") ! 1975: (match_operand:TF 2 "nonmemory_operand" "fG")))] ! 1976: "TARGET_NUMERICS" ! 1977: "addr %1,%2,%0" ! 1978: [(set_attr "type" "fpadd")]) ! 1979: ! 1980: (define_insn "subtf3" ! 1981: [(set (match_operand:TF 0 "register_operand" "=f") ! 1982: (minus:TF (match_operand:TF 1 "nonmemory_operand" "fG") ! 1983: (match_operand:TF 2 "nonmemory_operand" "fG")))] ! 1984: "TARGET_NUMERICS" ! 1985: "subr %2,%1,%0" ! 1986: [(set_attr "type" "fpadd")]) ! 1987: ! 1988: (define_insn "multf3" ! 1989: [(set (match_operand:TF 0 "register_operand" "=f") ! 1990: (mult:TF (match_operand:TF 1 "nonmemory_operand" "fG") ! 1991: (match_operand:TF 2 "nonmemory_operand" "fG")))] ! 1992: "TARGET_NUMERICS" ! 1993: "mulr %1,%2,%0" ! 1994: [(set_attr "type" "fpmul")]) ! 1995: ! 1996: (define_insn "divtf3" ! 1997: [(set (match_operand:TF 0 "register_operand" "=f") ! 1998: (div:TF (match_operand:TF 1 "nonmemory_operand" "fG") ! 1999: (match_operand:TF 2 "nonmemory_operand" "fG")))] ! 2000: "TARGET_NUMERICS" ! 2001: "divr %2,%1,%0" ! 2002: [(set_attr "type" "fpdiv")]) ! 2003: ! 2004: (define_insn "negtf2" ! 2005: [(set (match_operand:TF 0 "register_operand" "=f") ! 2006: (neg:TF (match_operand:TF 1 "register_operand" "f")))] ! 2007: "TARGET_NUMERICS" ! 2008: "subr %1,0f0.0,%0" ! 2009: [(set_attr "type" "fpadd")]) ! 2010: ! 2011: (define_insn "abstf2" ! 2012: [(set (match_operand:TF 0 "register_operand" "=f") ! 2013: (abs:TF (match_operand:TF 1 "register_operand" "f")))] ! 2014: "(TARGET_NUMERICS)" ! 2015: "cpysre %1,0f0.0,%0" ! 2016: [(set_attr "type" "fpmove")]) ! 2017: ! 2018: ;; Arithmetic shift instructions. ! 2019: ! 2020: (define_insn "ashlsi3" ! 2021: [(set (match_operand:SI 0 "register_operand" "=d") ! 2022: (ashift:SI (match_operand:SI 1 "arith_operand" "dI") ! 2023: (match_operand:SI 2 "arith_operand" "dI")))] ! 2024: "" ! 2025: "shli %2,%1,%0" ! 2026: [(set_attr "type" "alu2")]) ! 2027: ! 2028: (define_insn "ashrsi3" ! 2029: [(set (match_operand:SI 0 "register_operand" "=d") ! 2030: (ashiftrt:SI (match_operand:SI 1 "arith_operand" "dI") ! 2031: (match_operand:SI 2 "arith_operand" "dI")))] ! 2032: "" ! 2033: "shri %2,%1,%0" ! 2034: [(set_attr "type" "alu2")]) ! 2035: ! 2036: (define_insn "lshrsi3" ! 2037: [(set (match_operand:SI 0 "register_operand" "=d") ! 2038: (lshiftrt:SI (match_operand:SI 1 "arith_operand" "dI") ! 2039: (match_operand:SI 2 "arith_operand" "dI")))] ! 2040: "" ! 2041: "shro %2,%1,%0" ! 2042: [(set_attr "type" "alu2")]) ! 2043: ! 2044: ;; Unconditional and other jump instructions. ! 2045: ! 2046: (define_insn "jump" ! 2047: [(set (pc) ! 2048: (label_ref (match_operand 0 "" "")))] ! 2049: "" ! 2050: "b %l0" ! 2051: [(set_attr "type" "branch")]) ! 2052: ! 2053: (define_insn "indirect_jump" ! 2054: [(set (pc) (match_operand:SI 0 "register_operand" "r"))] ! 2055: "" ! 2056: "b* %0" ! 2057: [(set_attr "type" "branch")]) ! 2058: ! 2059: (define_insn "tablejump" ! 2060: [(set (pc) (match_operand:SI 0 "register_operand" "d")) ! 2061: (use (label_ref (match_operand 1 "" "")))] ! 2062: "" ! 2063: "bx (%0)" ! 2064: [(set_attr "type" "branch")]) ! 2065: ! 2066: ;;- jump to subroutine ! 2067: ! 2068: (define_expand "call" ! 2069: [(call (match_operand:SI 0 "general_operand" "") ! 2070: (match_operand:SI 1 "immediate_operand" ""))] ! 2071: "" ! 2072: " ! 2073: { ! 2074: i960_expand_call (operand0, operand1, 0); ! 2075: DONE; ! 2076: }") ! 2077: ! 2078: (define_insn "" ! 2079: [(call (match_operand:SI 0 "general_operand" "g") ! 2080: (match_operand:SI 1 "immediate_operand" "i"))] ! 2081: "" ! 2082: "* return i960_output_call_insn (operands[0], operands[1], insn);" ! 2083: [(set_attr "type" "call")]) ! 2084: ! 2085: (define_expand "call_value" ! 2086: [(set (match_operand 0 "register_operand" "=d") ! 2087: (call (match_operand:SI 1 "general_operand" "g") ! 2088: (match_operand:SI 2 "immediate_operand" "i")))] ! 2089: "" ! 2090: " ! 2091: { ! 2092: i960_expand_call (operand1, operand2, operand0); ! 2093: DONE; ! 2094: }") ! 2095: ! 2096: (define_insn "" ! 2097: [(set (match_operand 0 "register_operand" "=d") ! 2098: (call (match_operand:SI 1 "general_operand" "g") ! 2099: (match_operand:SI 2 "immediate_operand" "i")))] ! 2100: "" ! 2101: "* return i960_output_call_insn (operands[1], operands[2], insn);" ! 2102: [(set_attr "type" "call")]) ! 2103: ! 2104: (define_insn "return" ! 2105: [(return)] ! 2106: "" ! 2107: "* return i960_output_ret_insn (insn);" ! 2108: [(set_attr "type" "branch")]) ! 2109: ! 2110: (define_insn "nop" ! 2111: [(const_int 0)] ! 2112: "" ! 2113: "") ! 2114: ! 2115: ;; Various peephole optimizations for multiple-word moves, loads, and stores. ! 2116: ;; Multiple register moves. ! 2117: ! 2118: ;; Matched 5/28/91 ! 2119: (define_peephole ! 2120: [(set (match_operand:SI 0 "register_operand" "=r") ! 2121: (match_operand:SI 1 "register_operand" "r")) ! 2122: (set (match_operand:SI 2 "register_operand" "=r") ! 2123: (match_operand:SI 3 "register_operand" "r")) ! 2124: (set (match_operand:SI 4 "register_operand" "=r") ! 2125: (match_operand:SI 5 "register_operand" "r")) ! 2126: (set (match_operand:SI 6 "register_operand" "=r") ! 2127: (match_operand:SI 7 "register_operand" "r"))] ! 2128: "((REGNO (operands[0]) & 3) == 0) ! 2129: && ((REGNO (operands[1]) & 3) == 0) ! 2130: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) ! 2131: && (REGNO (operands[1]) + 1 == REGNO (operands[3])) ! 2132: && (REGNO (operands[0]) + 2 == REGNO (operands[4])) ! 2133: && (REGNO (operands[1]) + 2 == REGNO (operands[5])) ! 2134: && (REGNO (operands[0]) + 3 == REGNO (operands[6])) ! 2135: && (REGNO (operands[1]) + 3 == REGNO (operands[7]))" ! 2136: "movq %1,%0") ! 2137: ! 2138: ;; Matched 4/17/92 ! 2139: (define_peephole ! 2140: [(set (match_operand:DI 0 "register_operand" "=r") ! 2141: (match_operand:DI 1 "register_operand" "r")) ! 2142: (set (match_operand:DI 2 "register_operand" "=r") ! 2143: (match_operand:DI 3 "register_operand" "r"))] ! 2144: "((REGNO (operands[0]) & 3) == 0) ! 2145: && ((REGNO (operands[1]) & 3) == 0) ! 2146: && (REGNO (operands[0]) + 2 == REGNO (operands[2])) ! 2147: && (REGNO (operands[1]) + 2 == REGNO (operands[3]))" ! 2148: "movq %1,%0") ! 2149: ! 2150: ;; Matched 4/17/92 ! 2151: (define_peephole ! 2152: [(set (match_operand:DI 0 "register_operand" "=r") ! 2153: (match_operand:DI 1 "register_operand" "r")) ! 2154: (set (match_operand:SI 2 "register_operand" "=r") ! 2155: (match_operand:SI 3 "register_operand" "r")) ! 2156: (set (match_operand:SI 4 "register_operand" "=r") ! 2157: (match_operand:SI 5 "register_operand" "r"))] ! 2158: "((REGNO (operands[0]) & 3) == 0) ! 2159: && ((REGNO (operands[1]) & 3) == 0) ! 2160: && (REGNO (operands[0]) + 2 == REGNO (operands[2])) ! 2161: && (REGNO (operands[1]) + 2 == REGNO (operands[3])) ! 2162: && (REGNO (operands[0]) + 3 == REGNO (operands[4])) ! 2163: && (REGNO (operands[1]) + 3 == REGNO (operands[5]))" ! 2164: "movq %1,%0") ! 2165: ! 2166: ;; Matched 4/17/92 ! 2167: (define_peephole ! 2168: [(set (match_operand:SI 0 "register_operand" "=r") ! 2169: (match_operand:SI 1 "register_operand" "r")) ! 2170: (set (match_operand:SI 2 "register_operand" "=r") ! 2171: (match_operand:SI 3 "register_operand" "r")) ! 2172: (set (match_operand:DI 4 "register_operand" "=r") ! 2173: (match_operand:DI 5 "register_operand" "r"))] ! 2174: "((REGNO (operands[0]) & 3) == 0) ! 2175: && ((REGNO (operands[1]) & 3) == 0) ! 2176: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) ! 2177: && (REGNO (operands[1]) + 1 == REGNO (operands[3])) ! 2178: && (REGNO (operands[0]) + 2 == REGNO (operands[4])) ! 2179: && (REGNO (operands[1]) + 2 == REGNO (operands[5]))" ! 2180: "movq %1,%0") ! 2181: ! 2182: ;; Matched 4/17/92 ! 2183: (define_peephole ! 2184: [(set (match_operand:DI 0 "register_operand" "=r") ! 2185: (match_operand:DI 1 "register_operand" "r")) ! 2186: (set (match_operand:SI 2 "register_operand" "=r") ! 2187: (match_operand:SI 3 "register_operand" "r"))] ! 2188: "((REGNO (operands[0]) & 3) == 0) ! 2189: && ((REGNO (operands[1]) & 3) == 0) ! 2190: && (REGNO (operands[0]) + 2 == REGNO (operands[2])) ! 2191: && (REGNO (operands[1]) + 2 == REGNO (operands[3]))" ! 2192: "movt %1,%0") ! 2193: ! 2194: ;; Matched 5/28/91 ! 2195: (define_peephole ! 2196: [(set (match_operand:SI 0 "register_operand" "=r") ! 2197: (match_operand:SI 1 "register_operand" "r")) ! 2198: (set (match_operand:SI 2 "register_operand" "=r") ! 2199: (match_operand:SI 3 "register_operand" "r")) ! 2200: (set (match_operand:SI 4 "register_operand" "=r") ! 2201: (match_operand:SI 5 "register_operand" "r"))] ! 2202: "((REGNO (operands[0]) & 3) == 0) ! 2203: && ((REGNO (operands[1]) & 3) == 0) ! 2204: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) ! 2205: && (REGNO (operands[1]) + 1 == REGNO (operands[3])) ! 2206: && (REGNO (operands[0]) + 2 == REGNO (operands[4])) ! 2207: && (REGNO (operands[1]) + 2 == REGNO (operands[5]))" ! 2208: "movt %1,%0") ! 2209: ! 2210: ;; Matched 5/28/91 ! 2211: (define_peephole ! 2212: [(set (match_operand:SI 0 "register_operand" "=r") ! 2213: (match_operand:SI 1 "register_operand" "r")) ! 2214: (set (match_operand:SI 2 "register_operand" "=r") ! 2215: (match_operand:SI 3 "register_operand" "r"))] ! 2216: "((REGNO (operands[0]) & 1) == 0) ! 2217: && ((REGNO (operands[1]) & 1) == 0) ! 2218: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) ! 2219: && (REGNO (operands[1]) + 1 == REGNO (operands[3]))" ! 2220: "movl %1,%0") ! 2221: ! 2222: ; Multiple register loads. ! 2223: ! 2224: ;; Matched 6/15/91 ! 2225: (define_peephole ! 2226: [(set (match_operand:SI 0 "register_operand" "=r") ! 2227: (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") ! 2228: (match_operand:SI 2 "immediate_operand" "n")))) ! 2229: (set (match_operand:SI 3 "register_operand" "=r") ! 2230: (mem:SI (plus:SI (match_dup 1) ! 2231: (match_operand:SI 4 "immediate_operand" "n")))) ! 2232: (set (match_operand:SI 5 "register_operand" "=r") ! 2233: (mem:SI (plus:SI (match_dup 1) ! 2234: (match_operand:SI 6 "immediate_operand" "n")))) ! 2235: (set (match_operand:SI 7 "register_operand" "=r") ! 2236: (mem:SI (plus:SI (match_dup 1) ! 2237: (match_operand:SI 8 "immediate_operand" "n"))))] ! 2238: "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) ! 2239: && (REGNO (operands[1]) != REGNO (operands[0])) ! 2240: && (REGNO (operands[0]) + 1 == REGNO (operands[3])) ! 2241: && (REGNO (operands[1]) != REGNO (operands[3])) ! 2242: && (REGNO (operands[0]) + 2 == REGNO (operands[5])) ! 2243: && (REGNO (operands[1]) != REGNO (operands[5])) ! 2244: && (REGNO (operands[0]) + 3 == REGNO (operands[7])) ! 2245: && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])) ! 2246: && (INTVAL (operands[2]) + 8 == INTVAL (operands[6])) ! 2247: && (INTVAL (operands[2]) + 12 == INTVAL (operands[8])))" ! 2248: "ldq %2(%1),%0") ! 2249: ! 2250: ;; Matched 5/28/91 ! 2251: (define_peephole ! 2252: [(set (match_operand:DF 0 "register_operand" "=d") ! 2253: (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d") ! 2254: (match_operand:SI 2 "immediate_operand" "n")))) ! 2255: (set (match_operand:DF 3 "register_operand" "=d") ! 2256: (mem:DF (plus:SI (match_dup 1) ! 2257: (match_operand:SI 4 "immediate_operand" "n"))))] ! 2258: "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) ! 2259: && (REGNO (operands[1]) != REGNO (operands[0])) ! 2260: && (REGNO (operands[0]) + 2 == REGNO (operands[3])) ! 2261: && (REGNO (operands[1]) != REGNO (operands[3])) ! 2262: && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))" ! 2263: "ldq %2(%1),%0") ! 2264: ! 2265: ;; Matched 1/24/92 ! 2266: (define_peephole ! 2267: [(set (match_operand:DI 0 "register_operand" "=d") ! 2268: (mem:DI (plus:SI (match_operand:SI 1 "register_operand" "d") ! 2269: (match_operand:SI 2 "immediate_operand" "n")))) ! 2270: (set (match_operand:DI 3 "register_operand" "=d") ! 2271: (mem:DI (plus:SI (match_dup 1) ! 2272: (match_operand:SI 4 "immediate_operand" "n"))))] ! 2273: "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) ! 2274: && (REGNO (operands[1]) != REGNO (operands[0])) ! 2275: && (REGNO (operands[0]) + 2 == REGNO (operands[3])) ! 2276: && (REGNO (operands[1]) != REGNO (operands[3])) ! 2277: && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))" ! 2278: "ldq %2(%1),%0") ! 2279: ! 2280: ;; Matched 4/17/92 ! 2281: (define_peephole ! 2282: [(set (match_operand:SI 0 "register_operand" "=d") ! 2283: (mem:SI (match_operand:SI 1 "register_operand" "d"))) ! 2284: (set (match_operand:SI 2 "register_operand" "=d") ! 2285: (mem:SI (plus:SI (match_dup 1) ! 2286: (match_operand:SI 3 "immediate_operand" "n")))) ! 2287: (set (match_operand:SI 4 "register_operand" "=d") ! 2288: (mem:SI (plus:SI (match_dup 1) ! 2289: (match_operand:SI 5 "immediate_operand" "n")))) ! 2290: (set (match_operand:SI 6 "register_operand" "=d") ! 2291: (mem:SI (plus:SI (match_dup 1) ! 2292: (match_operand:SI 7 "immediate_operand" "n"))))] ! 2293: "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0) ! 2294: && (REGNO (operands[1]) != REGNO (operands[0])) ! 2295: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) ! 2296: && (REGNO (operands[1]) != REGNO (operands[2])) ! 2297: && (REGNO (operands[0]) + 2 == REGNO (operands[4])) ! 2298: && (REGNO (operands[1]) != REGNO (operands[4])) ! 2299: && (REGNO (operands[0]) + 3 == REGNO (operands[6])) ! 2300: && (INTVAL (operands[3]) == 4) ! 2301: && (INTVAL (operands[5]) == 8) ! 2302: && (INTVAL (operands[7]) == 12))" ! 2303: "ldq (%1),%0") ! 2304: ! 2305: ;; Matched 5/28/91 ! 2306: (define_peephole ! 2307: [(set (match_operand:SI 0 "register_operand" "=d") ! 2308: (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d") ! 2309: (match_operand:SI 2 "immediate_operand" "n")))) ! 2310: (set (match_operand:SI 3 "register_operand" "=d") ! 2311: (mem:SI (plus:SI (match_dup 1) ! 2312: (match_operand:SI 4 "immediate_operand" "n")))) ! 2313: (set (match_operand:SI 5 "register_operand" "=d") ! 2314: (mem:SI (plus:SI (match_dup 1) ! 2315: (match_operand:SI 6 "immediate_operand" "n"))))] ! 2316: "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) ! 2317: && (REGNO (operands[1]) != REGNO (operands[0])) ! 2318: && (REGNO (operands[0]) + 1 == REGNO (operands[3])) ! 2319: && (REGNO (operands[1]) != REGNO (operands[3])) ! 2320: && (REGNO (operands[0]) + 2 == REGNO (operands[5])) ! 2321: && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])) ! 2322: && (INTVAL (operands[2]) + 8 == INTVAL (operands[6])))" ! 2323: "ldt %2(%1),%0") ! 2324: ! 2325: ;; Matched 6/15/91 ! 2326: (define_peephole ! 2327: [(set (match_operand:SI 0 "register_operand" "=d") ! 2328: (mem:SI (match_operand:SI 1 "register_operand" "d"))) ! 2329: (set (match_operand:SI 2 "register_operand" "=d") ! 2330: (mem:SI (plus:SI (match_dup 1) ! 2331: (match_operand:SI 3 "immediate_operand" "n")))) ! 2332: (set (match_operand:SI 4 "register_operand" "=d") ! 2333: (mem:SI (plus:SI (match_dup 1) ! 2334: (match_operand:SI 5 "immediate_operand" "n"))))] ! 2335: "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0) ! 2336: && (REGNO (operands[1]) != REGNO (operands[0])) ! 2337: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) ! 2338: && (REGNO (operands[1]) != REGNO (operands[2])) ! 2339: && (REGNO (operands[0]) + 2 == REGNO (operands[4])) ! 2340: && (INTVAL (operands[3]) == 4) ! 2341: && (INTVAL (operands[5]) == 8))" ! 2342: "ldt (%1),%0") ! 2343: ! 2344: ;; Matched 5/28/91 ! 2345: (define_peephole ! 2346: [(set (match_operand:SI 0 "register_operand" "=d") ! 2347: (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d") ! 2348: (match_operand:SI 2 "immediate_operand" "n")))) ! 2349: (set (match_operand:SI 3 "register_operand" "=d") ! 2350: (mem:SI (plus:SI (match_dup 1) ! 2351: (match_operand:SI 4 "immediate_operand" "n"))))] ! 2352: "(i960_si_di (operands[1], operands[2]) && ((REGNO (operands[0]) & 1) == 0) ! 2353: && (REGNO (operands[1]) != REGNO (operands[0])) ! 2354: && (REGNO (operands[0]) + 1 == REGNO (operands[3])) ! 2355: && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])))" ! 2356: "ldl %2(%1),%0") ! 2357: ! 2358: ;; Matched 5/28/91 ! 2359: (define_peephole ! 2360: [(set (match_operand:SI 0 "register_operand" "=d") ! 2361: (mem:SI (match_operand:SI 1 "register_operand" "d"))) ! 2362: (set (match_operand:SI 2 "register_operand" "=d") ! 2363: (mem:SI (plus:SI (match_dup 1) ! 2364: (match_operand:SI 3 "immediate_operand" "n"))))] ! 2365: "(i960_si_di (operands[1], 0) && ((REGNO (operands[0]) & 1) == 0) ! 2366: && (REGNO (operands[1]) != REGNO (operands[0])) ! 2367: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) ! 2368: && (INTVAL (operands[3]) == 4))" ! 2369: "ldl (%1),%0") ! 2370: ! 2371: ; Multiple register stores. ! 2372: ! 2373: ;; Matched 5/28/91 ! 2374: (define_peephole ! 2375: [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d") ! 2376: (match_operand:SI 1 "immediate_operand" "n"))) ! 2377: (match_operand:SI 2 "register_operand" "d")) ! 2378: (set (mem:SI (plus:SI (match_dup 0) ! 2379: (match_operand:SI 3 "immediate_operand" "n"))) ! 2380: (match_operand:SI 4 "register_operand" "d")) ! 2381: (set (mem:SI (plus:SI (match_dup 0) ! 2382: (match_operand:SI 5 "immediate_operand" "n"))) ! 2383: (match_operand:SI 6 "register_operand" "d")) ! 2384: (set (mem:SI (plus:SI (match_dup 0) ! 2385: (match_operand:SI 7 "immediate_operand" "n"))) ! 2386: (match_operand:SI 8 "register_operand" "d"))] ! 2387: "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) ! 2388: && (REGNO (operands[2]) + 1 == REGNO (operands[4])) ! 2389: && (REGNO (operands[2]) + 2 == REGNO (operands[6])) ! 2390: && (REGNO (operands[2]) + 3 == REGNO (operands[8])) ! 2391: && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])) ! 2392: && (INTVAL (operands[1]) + 8 == INTVAL (operands[5])) ! 2393: && (INTVAL (operands[1]) + 12 == INTVAL (operands[7])))" ! 2394: "stq %2,%1(%0)") ! 2395: ! 2396: ;; Matched 6/16/91 ! 2397: (define_peephole ! 2398: [(set (mem:DF (plus:SI (match_operand:SI 0 "register_operand" "d") ! 2399: (match_operand:SI 1 "immediate_operand" "n"))) ! 2400: (match_operand:DF 2 "register_operand" "d")) ! 2401: (set (mem:DF (plus:SI (match_dup 0) ! 2402: (match_operand:SI 3 "immediate_operand" "n"))) ! 2403: (match_operand:DF 4 "register_operand" "d"))] ! 2404: "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) ! 2405: && (REGNO (operands[2]) + 2 == REGNO (operands[4])) ! 2406: && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))" ! 2407: "stq %2,%1(%0)") ! 2408: ! 2409: ;; Matched 4/17/92 ! 2410: (define_peephole ! 2411: [(set (mem:DI (plus:SI (match_operand:SI 0 "register_operand" "d") ! 2412: (match_operand:SI 1 "immediate_operand" "n"))) ! 2413: (match_operand:DI 2 "register_operand" "d")) ! 2414: (set (mem:DI (plus:SI (match_dup 0) ! 2415: (match_operand:SI 3 "immediate_operand" "n"))) ! 2416: (match_operand:DI 4 "register_operand" "d"))] ! 2417: "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) ! 2418: && (REGNO (operands[2]) + 2 == REGNO (operands[4])) ! 2419: && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))" ! 2420: "stq %2,%1(%0)") ! 2421: ! 2422: ;; Matched 1/23/92 ! 2423: (define_peephole ! 2424: [(set (mem:SI (match_operand:SI 0 "register_operand" "d")) ! 2425: (match_operand:SI 1 "register_operand" "d")) ! 2426: (set (mem:SI (plus:SI (match_dup 0) ! 2427: (match_operand:SI 2 "immediate_operand" "n"))) ! 2428: (match_operand:SI 3 "register_operand" "d")) ! 2429: (set (mem:SI (plus:SI (match_dup 0) ! 2430: (match_operand:SI 4 "immediate_operand" "n"))) ! 2431: (match_operand:SI 5 "register_operand" "d")) ! 2432: (set (mem:SI (plus:SI (match_dup 0) ! 2433: (match_operand:SI 6 "immediate_operand" "n"))) ! 2434: (match_operand:SI 7 "register_operand" "d"))] ! 2435: "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0) ! 2436: && (REGNO (operands[1]) + 1 == REGNO (operands[3])) ! 2437: && (REGNO (operands[1]) + 2 == REGNO (operands[5])) ! 2438: && (REGNO (operands[1]) + 3 == REGNO (operands[7])) ! 2439: && (INTVAL (operands[2]) == 4) ! 2440: && (INTVAL (operands[4]) == 8) ! 2441: && (INTVAL (operands[6]) == 12))" ! 2442: "stq %1,(%0)") ! 2443: ! 2444: ;; Matched 5/29/91 ! 2445: (define_peephole ! 2446: [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d") ! 2447: (match_operand:SI 1 "immediate_operand" "n"))) ! 2448: (match_operand:SI 2 "register_operand" "d")) ! 2449: (set (mem:SI (plus:SI (match_dup 0) ! 2450: (match_operand:SI 3 "immediate_operand" "n"))) ! 2451: (match_operand:SI 4 "register_operand" "d")) ! 2452: (set (mem:SI (plus:SI (match_dup 0) ! 2453: (match_operand:SI 5 "immediate_operand" "n"))) ! 2454: (match_operand:SI 6 "register_operand" "d"))] ! 2455: "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) ! 2456: && (REGNO (operands[2]) + 1 == REGNO (operands[4])) ! 2457: && (REGNO (operands[2]) + 2 == REGNO (operands[6])) ! 2458: && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])) ! 2459: && (INTVAL (operands[1]) + 8 == INTVAL (operands[5])))" ! 2460: "stt %2,%1(%0)") ! 2461: ! 2462: ;; Matched 5/29/91 ! 2463: (define_peephole ! 2464: [(set (mem:SI (match_operand:SI 0 "register_operand" "d")) ! 2465: (match_operand:SI 1 "register_operand" "d")) ! 2466: (set (mem:SI (plus:SI (match_dup 0) ! 2467: (match_operand:SI 2 "immediate_operand" "n"))) ! 2468: (match_operand:SI 3 "register_operand" "d")) ! 2469: (set (mem:SI (plus:SI (match_dup 0) ! 2470: (match_operand:SI 4 "immediate_operand" "n"))) ! 2471: (match_operand:SI 5 "register_operand" "d"))] ! 2472: "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0) ! 2473: && (REGNO (operands[1]) + 1 == REGNO (operands[3])) ! 2474: && (REGNO (operands[1]) + 2 == REGNO (operands[5])) ! 2475: && (INTVAL (operands[2]) == 4) ! 2476: && (INTVAL (operands[4]) == 8))" ! 2477: "stt %1,(%0)") ! 2478: ! 2479: ;; Matched 5/28/91 ! 2480: (define_peephole ! 2481: [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d") ! 2482: (match_operand:SI 1 "immediate_operand" "n"))) ! 2483: (match_operand:SI 2 "register_operand" "d")) ! 2484: (set (mem:SI (plus:SI (match_dup 0) ! 2485: (match_operand:SI 3 "immediate_operand" "n"))) ! 2486: (match_operand:SI 4 "register_operand" "d"))] ! 2487: "(i960_si_di (operands[0], operands[1]) && ((REGNO (operands[2]) & 1) == 0) ! 2488: && (REGNO (operands[2]) + 1 == REGNO (operands[4])) ! 2489: && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])))" ! 2490: "stl %2,%1(%0)") ! 2491: ! 2492: ;; Matched 5/28/91 ! 2493: (define_peephole ! 2494: [(set (mem:SI (match_operand:SI 0 "register_operand" "d")) ! 2495: (match_operand:SI 1 "register_operand" "d")) ! 2496: (set (mem:SI (plus:SI (match_dup 0) ! 2497: (match_operand:SI 2 "immediate_operand" "n"))) ! 2498: (match_operand:SI 3 "register_operand" "d"))] ! 2499: "(i960_si_di (operands[0], 0) && ((REGNO (operands[1]) & 1) == 0) ! 2500: && (REGNO (operands[1]) + 1 == REGNO (operands[3])) ! 2501: && (INTVAL (operands[2]) == 4))" ! 2502: "stl %1,(%0)") ! 2503: ! 2504: ;;- Local variables: ! 2505: ;;- mode:emacs-lisp ! 2506: ;;- comment-start: ";;- " ! 2507: ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) ! 2508: ;;- eval: (modify-syntax-entry ?[ "(]") ! 2509: ;;- eval: (modify-syntax-entry ?] ")[") ! 2510: ;;- eval: (modify-syntax-entry ?{ "(}") ! 2511: ;;- eval: (modify-syntax-entry ?} "){") ! 2512: ;;- End:
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