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1.1 root 1: ;;- Machine description for Intel 80960 chip for GNU C compiler
2: ;; Copyright (C) 1992 Free Software Foundation, Inc.
3: ;; Contributed by Steven McGeady, Intel Corp.
4: ;; Additional work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5: ;; Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
6:
7: ;; This file is part of GNU CC.
8:
9: ;; GNU CC is free software; you can redistribute it and/or modify
10: ;; it under the terms of the GNU General Public License as published by
11: ;; the Free Software Foundation; either version 2, or (at your option)
12: ;; any later version.
13:
14: ;; GNU CC is distributed in the hope that it will be useful,
15: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
16: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17: ;; GNU General Public License for more details.
18:
19: ;; You should have received a copy of the GNU General Public License
20: ;; along with GNU CC; see the file COPYING. If not, write to
21: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
22:
23: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
24:
1.1.1.2 ! root 25: ;; There are very few (4) 'f' registers, they can't be loaded/stored from/to
! 26: ;; memory, and some instructions explicitly require them, so we get better
! 27: ;; code by discouraging psuedo-registers from being allocated to them.
! 28: ;; However, we do want to allow all patterns which can store to them to
! 29: ;; include them in their constraints, so we always use '*f' in a destination
! 30: ;; constraint except when 'f' is the only alternative.
! 31:
1.1 root 32: ;; Insn attributes which describe the i960.
33:
34: ;; Modscan is not used, since the compiler never emits any of these insns.
35: (define_attr "type"
36: "move,arith,alu2,mult,div,modscan,load,store,branch,call,address,compare,fpload,fpstore,fpmove,fpcvt,fpcc,fpadd,fpmul,fpdiv,multi,misc"
37: (const_string "arith"))
38:
39: ;; Length (in # of insns).
40: (define_attr "length" ""
41: (cond [(eq_attr "type" "load,fpload")
42: (if_then_else (match_operand 1 "symbolic_memory_operand" "")
43: (const_int 2)
44: (const_int 1))
45: (eq_attr "type" "store,fpstore")
46: (if_then_else (match_operand 0 "symbolic_memory_operand" "")
47: (const_int 2)
48: (const_int 1))
49: (eq_attr "type" "address")
50: (const_int 2)]
51: (const_int 1)))
52:
53: (define_asm_attributes
54: [(set_attr "length" "1")
55: (set_attr "type" "multi")])
56:
57: ;; (define_function_unit {name} {num-units} {n-users} {test}
1.1.1.2 ! root 58: ;; {ready-delay} {issue-delay} [{conflict-list}])
1.1 root 59:
60: ;; The integer ALU
61: (define_function_unit "alu" 2 0 (eq_attr "type" "arith,compare,move,address") 1 0)
62: (define_function_unit "alu" 2 0 (eq_attr "type" "alu2") 2 0)
63: (define_function_unit "alu" 2 0 (eq_attr "type" "mult") 5 0)
64: (define_function_unit "alu" 2 0 (eq_attr "type" "div") 35 0)
65: (define_function_unit "alu" 2 0 (eq_attr "type" "modscan") 3 0)
66:
67: ;; Memory with load-delay of 1 (i.e., 2 cycle load).
68: (define_function_unit "memory" 1 0 (eq_attr "type" "load,fpload") 2 0)
69:
70: ;; Floating point operations.
71: (define_function_unit "fp" 1 2 (eq_attr "type" "fpmove") 5 0)
72: (define_function_unit "fp" 1 2 (eq_attr "type" "fpcvt") 35 0)
73: (define_function_unit "fp" 1 2 (eq_attr "type" "fpcc") 10 0)
74: (define_function_unit "fp" 1 2 (eq_attr "type" "fpadd") 10 0)
75: (define_function_unit "fp" 1 2 (eq_attr "type" "fpmul") 20 0)
76: (define_function_unit "fp" 1 2 (eq_attr "type" "fpdiv") 35 0)
77:
78: ;; Compare instructions.
79: ;; This controls RTL generation and register allocation.
80:
81: ;; We generate RTL for comparisons and branches by having the cmpxx
82: ;; patterns store away the operands. Then, the scc and bcc patterns
83: ;; emit RTL for both the compare and the branch.
84: ;;
85: ;; We start with the DEFINE_EXPANDs, then then DEFINE_INSNs to match
86: ;; the patterns. Finally, we have the DEFINE_SPLITs for some of the scc
87: ;; insns that actually require more than one machine instruction.
88:
89: ;; Put cmpsi first because it is expected to be the most common.
90:
91: (define_expand "cmpsi"
92: [(set (reg:CC 36)
93: (compare:CC (match_operand:SI 0 "nonimmediate_operand" "")
94: (match_operand:SI 1 "general_operand" "")))]
95: ""
96: "
97: {
98: i960_compare_op0 = operands[0];
99: i960_compare_op1 = operands[1];
100: DONE;
101: }")
102:
103: (define_expand "cmpdf"
104: [(set (reg:CC 36)
105: (compare:CC (match_operand:DF 0 "register_operand" "r")
106: (match_operand:DF 1 "nonmemory_operand" "rGH")))]
107: "TARGET_NUMERICS"
108: "
109: {
110: i960_compare_op0 = operands[0];
111: i960_compare_op1 = operands[1];
112: DONE;
113: }")
114:
115: (define_expand "cmpsf"
116: [(set (reg:CC 36)
117: (compare:CC (match_operand:SF 0 "register_operand" "r")
118: (match_operand:SF 1 "nonmemory_operand" "rGH")))]
119: "TARGET_NUMERICS"
120: "
121: {
122: i960_compare_op0 = operands[0];
123: i960_compare_op1 = operands[1];
124: DONE;
125: }")
126:
127: ;; Now the DEFINE_INSNs for the compare and scc cases. First the compares.
128:
129: (define_insn ""
130: [(set (reg:CC 36)
131: (compare:CC (match_operand:SI 0 "register_operand" "d")
132: (match_operand:SI 1 "arith_operand" "dI")))]
133: ""
134: "cmpi %0,%1"
135: [(set_attr "type" "compare")])
136:
137: (define_insn ""
138: [(set (reg:CC_UNS 36)
139: (compare:CC_UNS (match_operand:SI 0 "register_operand" "d")
140: (match_operand:SI 1 "arith_operand" "dI")))]
141: ""
142: "cmpo %0,%1"
143: [(set_attr "type" "compare")])
144:
145: (define_insn ""
146: [(set (reg:CC 36)
147: (compare:CC (match_operand:DF 0 "register_operand" "r")
148: (match_operand:DF 1 "nonmemory_operand" "rGH")))]
149: "TARGET_NUMERICS"
150: "cmprl %0,%1"
151: [(set_attr "type" "fpcc")])
152:
153: (define_insn ""
154: [(set (reg:CC 36)
155: (compare:CC (match_operand:SF 0 "register_operand" "r")
156: (match_operand:SF 1 "nonmemory_operand" "rGH")))]
157: "TARGET_NUMERICS"
158: "cmpr %0,%1"
159: [(set_attr "type" "fpcc")])
160:
161: ;; Instruction definitions for branch-on-bit-set and clear insns.
162:
163: (define_insn ""
164: [(set (pc)
165: (if_then_else
166: (ne (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
167: (const_int 1)
168: (match_operand:SI 2 "arith_operand" "dI"))
169: (const_int 0))
170: (label_ref (match_operand 3 "" ""))
171: (pc)))]
172: ""
173: "bbs %2,%1,%l3"
174: [(set_attr "type" "branch")])
175:
176: (define_insn ""
177: [(set (pc)
178: (if_then_else
179: (eq (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
180: (const_int 1)
181: (match_operand:SI 2 "arith_operand" "dI"))
182: (const_int 0))
183: (label_ref (match_operand 3 "" ""))
184: (pc)))]
185: ""
186: "bbc %2,%1,%l3"
187: [(set_attr "type" "branch")])
188:
189: (define_insn ""
190: [(set (pc)
191: (if_then_else
192: (ne (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
193: (const_int 1)
194: (match_operand:SI 2 "arith_operand" "dI"))
195: (const_int 0))
196: (label_ref (match_operand 3 "" ""))
197: (pc)))]
198: ""
199: "bbs %2,%1,%l3"
200: [(set_attr "type" "branch")])
201:
202: (define_insn ""
203: [(set (pc)
204: (if_then_else
205: (eq (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
206: (const_int 1)
207: (match_operand:SI 2 "arith_operand" "dI"))
208: (const_int 0))
209: (label_ref (match_operand 3 "" ""))
210: (pc)))]
211: ""
212: "bbc %2,%1,%l3"
213: [(set_attr "type" "branch")])
214:
215: ;; ??? These will never match. The LOG_LINKs necessary to make these match
216: ;; are not created by flow. These remain as a reminder to make this work
217: ;; some day.
218:
219: (define_insn ""
220: [(set (reg:CC 36)
221: (compare (match_operand:SI 0 "arith_operand" "d")
222: (match_operand:SI 1 "arith_operand" "d")))
223: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))]
224: "0"
225: "cmpinci %0,%1"
226: [(set_attr "type" "compare")])
227:
228: (define_insn ""
229: [(set (reg:CC_UNS 36)
230: (compare (match_operand:SI 0 "arith_operand" "d")
231: (match_operand:SI 1 "arith_operand" "d")))
232: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))]
233: "0"
234: "cmpinco %0,%1"
235: [(set_attr "type" "compare")])
236:
237: (define_insn ""
238: [(set (reg:CC 36)
239: (compare (match_operand:SI 0 "arith_operand" "d")
240: (match_operand:SI 1 "arith_operand" "d")))
241: (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))]
242: "0"
243: "cmpdeci %0,%1"
244: [(set_attr "type" "compare")])
245:
246: (define_insn ""
247: [(set (reg:CC_UNS 36)
248: (compare (match_operand:SI 0 "arith_operand" "d")
249: (match_operand:SI 1 "arith_operand" "d")))
250: (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))]
251: "0"
252: "cmpdeco %0,%1"
253: [(set_attr "type" "compare")])
254:
255: ;; Templates to store result of condition.
256: ;; '1' is stored if condition is true.
257: ;; '0' is stored if condition is false.
258: ;; These should use predicate "general_operand", since
259: ;; gcc seems to be creating mem references which use these
260: ;; templates.
261:
262: (define_expand "seq"
263: [(set (match_operand:SI 0 "general_operand" "=d")
264: (eq (match_dup 1) (const_int 0)))]
265: ""
266: "
267: {
268: operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1);
269: }")
270:
271: (define_expand "sne"
272: [(set (match_operand:SI 0 "general_operand" "=d")
273: (ne (match_dup 1) (const_int 0)))]
274: ""
275: "
276: {
277: operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1);
278: }")
279:
280: (define_expand "sgt"
281: [(set (match_operand:SI 0 "general_operand" "=d")
282: (gt (match_dup 1) (const_int 0)))]
283: ""
284: "
285: {
286: operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1);
287: }")
288:
289: (define_expand "sgtu"
290: [(set (match_operand:SI 0 "general_operand" "=d")
291: (gtu (match_dup 1) (const_int 0)))]
292: ""
293: "
294: {
295: operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1);
296: }")
297:
298: (define_expand "slt"
299: [(set (match_operand:SI 0 "general_operand" "=d")
300: (lt (match_dup 1) (const_int 0)))]
301: ""
302: "
303: {
304: operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1);
305: }")
306:
307: (define_expand "sltu"
308: [(set (match_operand:SI 0 "general_operand" "=d")
309: (ltu (match_dup 1) (const_int 0)))]
310: ""
311: "
312: {
313: operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1);
314: }")
315:
316: (define_expand "sge"
317: [(set (match_operand:SI 0 "general_operand" "=d")
318: (ge (match_dup 1) (const_int 0)))]
319: ""
320: "
321: {
322: operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1);
323: }")
324:
325: (define_expand "sgeu"
326: [(set (match_operand:SI 0 "general_operand" "=d")
327: (geu (match_dup 1) (const_int 0)))]
328: ""
329: "
330: {
331: operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1);
332: }")
333:
334: (define_expand "sle"
335: [(set (match_operand:SI 0 "general_operand" "=d")
336: (le (match_dup 1) (const_int 0)))]
337: ""
338: "
339: {
340: operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1);
341: }")
342:
343: (define_expand "sleu"
344: [(set (match_operand:SI 0 "general_operand" "=d")
345: (leu (match_dup 1) (const_int 0)))]
346: ""
347: "
348: {
349: operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1);
350: }")
351:
352: (define_insn ""
353: [(set (match_operand:SI 0 "general_operand" "=d")
354: (match_operator 1 "comparison_operator" [(reg:CC 36) (const_int 0)]))]
355: ""
356: "test%C1 %0"
357: [(set_attr "type" "compare")])
358:
359: (define_insn ""
360: [(set (match_operand:SI 0 "general_operand" "=d")
361: (match_operator 1 "comparison_operator" [(reg:CC_UNS 36) (const_int 0)]))]
362: ""
363: "test%C1 %0"
364: [(set_attr "type" "compare")])
365:
366: ;; These control RTL generation for conditional jump insns
367: ;; and match them for register allocation.
368:
369: (define_expand "beq"
370: [(set (pc)
371: (if_then_else (eq (match_dup 1)
372: (const_int 0))
373: (label_ref (match_operand 0 "" ""))
374: (pc)))]
375: ""
376: "
377: { operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1); }")
378:
379: (define_expand "bne"
380: [(set (pc)
381: (if_then_else (ne (match_dup 1)
382: (const_int 0))
383: (label_ref (match_operand 0 "" ""))
384: (pc)))]
385: ""
386: "
387: { operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1); }")
388:
389: (define_expand "bgt"
390: [(set (pc)
391: (if_then_else (gt (match_dup 1)
392: (const_int 0))
393: (label_ref (match_operand 0 "" ""))
394: (pc)))]
395: ""
396: "
397: { operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1); }")
398:
399: (define_expand "bgtu"
400: [(set (pc)
401: (if_then_else (gtu (match_dup 1)
402: (const_int 0))
403: (label_ref (match_operand 0 "" ""))
404: (pc)))]
405: ""
406: "
407: { operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1); }")
408:
409: (define_expand "blt"
410: [(set (pc)
411: (if_then_else (lt (match_dup 1)
412: (const_int 0))
413: (label_ref (match_operand 0 "" ""))
414: (pc)))]
415: ""
416: "
417: { operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1); }")
418:
419: (define_expand "bltu"
420: [(set (pc)
421: (if_then_else (ltu (match_dup 1)
422: (const_int 0))
423: (label_ref (match_operand 0 "" ""))
424: (pc)))]
425: ""
426: "
427: { operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1); }")
428:
429: (define_expand "bge"
430: [(set (pc)
431: (if_then_else (ge (match_dup 1)
432: (const_int 0))
433: (label_ref (match_operand 0 "" ""))
434: (pc)))]
435: ""
436: "
437: { operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1); }")
438:
439: (define_expand "bgeu"
440: [(set (pc)
441: (if_then_else (geu (match_dup 1)
442: (const_int 0))
443: (label_ref (match_operand 0 "" ""))
444: (pc)))]
445: ""
446: "
447: { operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1); }")
448:
449: (define_expand "ble"
450: [(set (pc)
451: (if_then_else (le (match_dup 1)
452: (const_int 0))
453: (label_ref (match_operand 0 "" ""))
454: (pc)))]
455: ""
456: "
457: { operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1); }")
458:
459: (define_expand "bleu"
460: [(set (pc)
461: (if_then_else (leu (match_dup 1)
462: (const_int 0))
463: (label_ref (match_operand 0 "" ""))
464: (pc)))]
465: ""
466: "
467: { operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1); }")
468:
469: ;; Now the normal branch insns (forward and reverse).
470:
471: (define_insn ""
472: [(set (pc)
473: (if_then_else (match_operator 0 "comparison_operator"
474: [(reg:CC 36) (const_int 0)])
475: (label_ref (match_operand 1 "" ""))
476: (pc)))]
477: ""
478: "b%C0 %l1"
479: [(set_attr "type" "branch")])
480:
481: (define_insn ""
482: [(set (pc)
483: (if_then_else (match_operator 0 "comparison_operator"
484: [(reg:CC 36) (const_int 0)])
485: (pc)
486: (label_ref (match_operand 1 "" ""))))]
487: ""
488: "b%I0 %l1"
489: [(set_attr "type" "branch")])
490:
491: (define_insn ""
492: [(set (pc)
493: (if_then_else (match_operator 0 "comparison_operator"
494: [(reg:CC_UNS 36) (const_int 0)])
495: (label_ref (match_operand 1 "" ""))
496: (pc)))]
497: ""
498: "b%C0 %l1"
499: [(set_attr "type" "branch")])
500:
501: (define_insn ""
502: [(set (pc)
503: (if_then_else (match_operator 0 "comparison_operator"
504: [(reg:CC_UNS 36) (const_int 0)])
505: (pc)
506: (label_ref (match_operand 1 "" ""))))]
507: ""
508: "b%I0 %l1"
509: [(set_attr "type" "branch")])
510:
511: (define_insn ""
512: [(set (pc)
513: (if_then_else
514: (match_operator 0 "comparison_operator"
515: [(match_operand:SI 1 "arith_operand" "d")
516: (match_operand:SI 2 "arith_operand" "dI")])
517: (label_ref (match_operand 3 "" ""))
518: (pc)))]
519: ""
520: "cmp%S0%B0%R0 %2,%1,%l3"
521: [(set_attr "type" "branch")])
522:
523: (define_insn ""
524: [(set (pc)
525: (if_then_else
526: (match_operator 0 "comparison_operator"
527: [(match_operand:SI 1 "arith_operand" "d")
528: (match_operand:SI 2 "arith_operand" "dI")])
529: (pc)
530: (label_ref (match_operand 3 "" ""))))]
531: ""
532: "cmp%S0%B0%X0 %2,%1,%l3"
533: [(set_attr "type" "branch")])
534:
535: ;; Normal move instructions.
1.1.1.2 ! root 536: ;; This code is based on the sparc machine description.
1.1 root 537:
538: (define_expand "movsi"
539: [(set (match_operand:SI 0 "general_operand" "")
540: (match_operand:SI 1 "general_operand" ""))]
541: ""
542: "
543: {
544: if (emit_move_sequence (operands, SImode))
545: DONE;
546: }")
547:
548: ;; The store case can not be separate, because reload may convert a register
549: ;; to register move insn to a store (or load) insn without rerecognizing
550: ;; the insn.
551:
552: ;; Special pattern for zero stores to memory for functions which don't use
553: ;; the arg pointer.
554:
555: (define_insn ""
556: [(set (match_operand:SI 0 "general_operand" "=d,d,d,m")
557: (match_operand:SI 1 "general_operand" "dI,i,m,dJ"))]
558: "current_function_args_size == 0
559: && (register_operand (operands[0], SImode)
560: || register_operand (operands[1], SImode)
561: || operands[1] == const0_rtx)"
562: "*
563: {
564: switch (which_alternative)
565: {
566: case 0:
567: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
568: {
569: if (GET_CODE (operands[1]) == REG)
570: return \"lda (%1),%0\";
571: else
572: return \"lda %1,%0\";
573: }
574: return \"mov %1,%0\";
575: case 1:
576: return i960_output_ldconst (operands[0], operands[1]);
577: case 2:
578: return \"ld %1,%0\";
579: case 3:
580: if (operands[1] == const0_rtx)
581: return \"st g14,%0\";
582: return \"st %1,%0\";
583: }
584: }"
585: [(set_attr "type" "move,address,load,store")
586: (set_attr "length" "*,3,*,*")])
587:
588: (define_insn ""
589: [(set (match_operand:SI 0 "general_operand" "=d,d,d,m")
590: (match_operand:SI 1 "general_operand" "dI,i,m,d"))]
591: "current_function_args_size != 0
592: && (register_operand (operands[0], SImode)
593: || register_operand (operands[1], SImode))"
594: "*
595: {
596: switch (which_alternative)
597: {
598: case 0:
599: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
600: {
601: if (GET_CODE (operands[1]) == REG)
602: return \"lda (%1),%0\";
603: else
604: return \"lda %1,%0\";
605: }
606: return \"mov %1,%0\";
607: case 1:
608: return i960_output_ldconst (operands[0], operands[1]);
609: case 2:
610: return \"ld %1,%0\";
611: case 3:
612: return \"st %1,%0\";
613: }
614: }"
615: [(set_attr "type" "move,address,load,store")
616: (set_attr "length" "*,3,*,*")])
617:
618: (define_expand "movhi"
619: [(set (match_operand:HI 0 "general_operand" "")
620: (match_operand:HI 1 "general_operand" ""))]
621: ""
622: "
623: {
624: if (emit_move_sequence (operands, HImode))
625: DONE;
626: }")
627:
628: ;; Special pattern for zero stores to memory for functions which don't use
629: ;; the arg pointer.
630:
631: ;; The store case can not be separate. See above.
632: (define_insn ""
633: [(set (match_operand:HI 0 "general_operand" "=d,d,d,m")
634: (match_operand:HI 1 "general_operand" "dI,i,m,dJ"))]
635: "current_function_args_size == 0
636: && (register_operand (operands[0], HImode)
637: || register_operand (operands[1], HImode)
638: || operands[1] == const0_rtx)"
639: "*
640: {
641: switch (which_alternative)
642: {
643: case 0:
644: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
645: {
646: if (GET_CODE (operands[1]) == REG)
647: return \"lda (%1),%0\";
648: else
649: return \"lda %1,%0\";
650: }
651: return \"mov %1,%0\";
652: case 1:
653: return i960_output_ldconst (operands[0], operands[1]);
654: case 2:
655: return \"ldos %1,%0\";
656: case 3:
657: if (operands[1] == const0_rtx)
658: return \"stos g14,%0\";
659: return \"stos %1,%0\";
660: }
661: }"
662: [(set_attr "type" "move,misc,load,store")
663: (set_attr "length" "*,3,*,*")])
664:
665: ;; The store case can not be separate. See above.
666: (define_insn ""
667: [(set (match_operand:HI 0 "general_operand" "=d,d,d,m")
668: (match_operand:HI 1 "general_operand" "dI,i,m,d"))]
669: "current_function_args_size != 0
670: && (register_operand (operands[0], HImode)
671: || register_operand (operands[1], HImode))"
672: "*
673: {
674: switch (which_alternative)
675: {
676: case 0:
677: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
678: {
679: if (GET_CODE (operands[1]) == REG)
680: return \"lda (%1),%0\";
681: else
682: return \"lda %1,%0\";
683: }
684: return \"mov %1,%0\";
685: case 1:
686: return i960_output_ldconst (operands[0], operands[1]);
687: case 2:
688: return \"ldos %1,%0\";
689: case 3:
690: return \"stos %1,%0\";
691: }
692: }"
693: [(set_attr "type" "move,misc,load,store")
694: (set_attr "length" "*,3,*,*")])
695:
696: (define_expand "movqi"
697: [(set (match_operand:QI 0 "general_operand" "")
698: (match_operand:QI 1 "general_operand" ""))]
699: ""
700: "
701: {
702: if (emit_move_sequence (operands, QImode))
703: DONE;
704: }")
705:
706: ;; The store case can not be separate. See comment above.
707: (define_insn ""
708: [(set (match_operand:QI 0 "general_operand" "=d,d,d,m")
709: (match_operand:QI 1 "general_operand" "dI,i,m,dJ"))]
710: "current_function_args_size == 0
711: && (register_operand (operands[0], QImode)
712: || register_operand (operands[1], QImode)
713: || operands[1] == const0_rtx)"
714: "*
715: {
716: switch (which_alternative)
717: {
718: case 0:
719: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
720: {
721: if (GET_CODE (operands[1]) == REG)
722: return \"lda (%1),%0\";
723: else
724: return \"lda %1,%0\";
725: }
726: return \"mov %1,%0\";
727: case 1:
728: return i960_output_ldconst (operands[0], operands[1]);
729: case 2:
730: return \"ldob %1,%0\";
731: case 3:
732: if (operands[1] == const0_rtx)
733: return \"stob g14,%0\";
734: return \"stob %1,%0\";
735: }
736: }"
737: [(set_attr "type" "move,misc,load,store")
738: (set_attr "length" "*,3,*,*")])
739:
740: ;; The store case can not be separate. See comment above.
741: (define_insn ""
742: [(set (match_operand:QI 0 "general_operand" "=d,d,d,m")
743: (match_operand:QI 1 "general_operand" "dI,i,m,d"))]
744: "current_function_args_size != 0
745: && (register_operand (operands[0], QImode)
746: || register_operand (operands[1], QImode))"
747: "*
748: {
749: switch (which_alternative)
750: {
751: case 0:
752: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES)
753: {
754: if (GET_CODE (operands[1]) == REG)
755: return \"lda (%1),%0\";
756: else
757: return \"lda %1,%0\";
758: }
759: return \"mov %1,%0\";
760: case 1:
761: return i960_output_ldconst (operands[0], operands[1]);
762: case 2:
763: return \"ldob %1,%0\";
764: case 3:
765: return \"stob %1,%0\";
766: }
767: }"
768: [(set_attr "type" "move,misc,load,store")
769: (set_attr "length" "*,3,*,*")])
770:
771: (define_expand "movdi"
772: [(set (match_operand:DI 0 "general_operand" "")
773: (match_operand:DI 1 "general_operand" ""))]
774: ""
775: "
776: {
777: if (emit_move_sequence (operands, DImode))
778: DONE;
779: }")
780:
781: ;; The store case can not be separate. See comment above.
782: (define_insn ""
1.1.1.2 ! root 783: [(set (match_operand:DI 0 "general_operand" "=d,d,d,m,o")
! 784: (match_operand:DI 1 "general_operand" "dI,i,m,d,J"))]
1.1 root 785: "current_function_args_size == 0
786: && (register_operand (operands[0], DImode)
787: || register_operand (operands[1], DImode)
788: || operands[1] == const0_rtx)"
789: "*
790: {
791: switch (which_alternative)
792: {
793: case 0:
794: return \"movl %1,%0\";
795: case 1:
796: return i960_output_ldconst (operands[0], operands[1]);
797: case 2:
798: return \"ldl %1,%0\";
799: case 3:
800: return \"stl %1,%0\";
1.1.1.2 ! root 801: case 4:
! 802: operands[1] = adj_offsettable_operand (operands[0], 4);
! 803: return \"st g14,%0\;st g14,%1\";
1.1 root 804: }
805: }"
1.1.1.2 ! root 806: [(set_attr "type" "move,load,load,store,store")])
1.1 root 807:
808: ;; The store case can not be separate. See comment above.
809: (define_insn ""
810: [(set (match_operand:DI 0 "general_operand" "=d,d,d,m")
811: (match_operand:DI 1 "general_operand" "dI,i,m,d"))]
812: "current_function_args_size != 0
813: && (register_operand (operands[0], DImode)
814: || register_operand (operands[1], DImode))"
815: "*
816: {
817: switch (which_alternative)
818: {
819: case 0:
820: return \"movl %1,%0\";
821: case 1:
822: return i960_output_ldconst (operands[0], operands[1]);
823: case 2:
824: return \"ldl %1,%0\";
825: case 3:
826: return \"stl %1,%0\";
827: }
828: }"
829: [(set_attr "type" "move,load,load,store")])
830:
831: (define_expand "movti"
832: [(set (match_operand:TI 0 "general_operand" "")
833: (match_operand:TI 1 "general_operand" ""))]
834: ""
835: "
836: {
837: if (emit_move_sequence (operands, TImode))
838: DONE;
839: }")
840:
841: ;; The store case can not be separate. See comment above.
842: (define_insn ""
1.1.1.2 ! root 843: [(set (match_operand:TI 0 "general_operand" "=d,d,d,m,o")
! 844: (match_operand:TI 1 "general_operand" "dI,i,m,d,J"))]
1.1 root 845: "current_function_args_size == 0
846: && (register_operand (operands[0], TImode)
847: || register_operand (operands[1], TImode)
848: || operands[1] == const0_rtx)"
849: "*
850: {
851: switch (which_alternative)
852: {
853: case 0:
854: return \"movq %1,%0\";
855: case 1:
856: return i960_output_ldconst (operands[0], operands[1]);
857: case 2:
858: return \"ldq %1,%0\";
859: case 3:
860: return \"stq %1,%0\";
1.1.1.2 ! root 861: case 4:
! 862: operands[1] = adj_offsettable_operand (operands[0], 4);
! 863: operands[2] = adj_offsettable_operand (operands[0], 8);
! 864: operands[3] = adj_offsettable_operand (operands[0], 12);
! 865: return \"st g14,%0\;st g14,%1\;st g14,%2\;st g14,%3\";
1.1 root 866: }
867: }"
1.1.1.2 ! root 868: [(set_attr "type" "move,load,load,store,store")])
1.1 root 869:
870: ;; The store case can not be separate. See comment above.
871: (define_insn ""
872: [(set (match_operand:TI 0 "general_operand" "=d,d,d,m")
873: (match_operand:TI 1 "general_operand" "dI,i,m,d"))]
874: "current_function_args_size != 0
875: && (register_operand (operands[0], TImode)
876: || register_operand (operands[1], TImode))"
877: "*
878: {
879: switch (which_alternative)
880: {
881: case 0:
882: return \"movq %1,%0\";
883: case 1:
884: return i960_output_ldconst (operands[0], operands[1]);
885: case 2:
886: return \"ldq %1,%0\";
887: case 3:
888: return \"stq %1,%0\";
889: }
890: }"
891: [(set_attr "type" "move,load,load,store")])
892:
893: (define_expand "store_multiple"
894: [(set (match_operand:SI 0 "" "") ;;- dest
895: (match_operand:SI 1 "" "")) ;;- src
896: (use (match_operand:SI 2 "" ""))] ;;- nregs
897: ""
898: "
899: {
900: int regno;
901: int count;
902: rtx from;
903: int i;
904:
905: if (GET_CODE (operands[0]) != MEM
906: || GET_CODE (operands[1]) != REG
907: || GET_CODE (operands[2]) != CONST_INT)
908: FAIL;
909:
910: count = INTVAL (operands[2]);
911: if (count > 12)
912: FAIL;
913:
914: regno = REGNO (operands[1]);
915: from = memory_address (SImode, XEXP (operands[0], 0));
916: while (count >= 4 && ((regno & 3) == 0))
917: {
918: emit_insn (gen_rtx (SET, VOIDmode,
919: gen_rtx (MEM, TImode, from),
920: gen_rtx (REG, TImode, regno)));
921: count -= 4;
922: regno += 4;
923: from = memory_address (TImode, plus_constant (from, 16));
924: }
925: while (count >= 2 && ((regno & 1) == 0))
926: {
927: emit_insn (gen_rtx (SET, VOIDmode,
928: gen_rtx (MEM, DImode, from),
929: gen_rtx (REG, DImode, regno)));
930: count -= 2;
931: regno += 2;
932: from = memory_address (DImode, plus_constant (from, 8));
933: }
934: while (count > 0)
935: {
936: emit_insn (gen_rtx (SET, VOIDmode,
937: gen_rtx (MEM, SImode, from),
938: gen_rtx (REG, SImode, regno)));
939: count -= 1;
940: regno += 1;
941: from = memory_address (SImode, plus_constant (from, 4));
942: }
943: DONE;
944: }")
945:
946: ;; Floating point move insns
947:
948: (define_expand "movdf"
949: [(set (match_operand:DF 0 "general_operand" "")
950: (match_operand:DF 1 "fpmove_src_operand" ""))]
951: ""
952: "
953: {
954: if (emit_move_sequence (operands, DFmode))
955: DONE;
956: }")
957:
958: (define_insn ""
1.1.1.2 ! root 959: [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m,o")
! 960: (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d,G"))]
1.1 root 961: "current_function_args_size == 0
962: && (register_operand (operands[0], DFmode)
963: || register_operand (operands[1], DFmode)
964: || operands[1] == CONST0_RTX (DFmode))"
965: "*
966: {
967: switch (which_alternative)
968: {
969: case 0:
970: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
971: return \"movrl %1,%0\";
972: else
973: return \"movl %1,%0\";
974: case 1:
975: return \"movrl %1,%0\";
976: case 2:
977: return i960_output_ldconst (operands[0], operands[1]);
978: case 3:
979: return \"ldl %1,%0\";
980: case 4:
981: return \"stl %1,%0\";
1.1.1.2 ! root 982: case 5:
! 983: operands[1] = adj_offsettable_operand (operands[0], 4);
! 984: return \"st g14,%0\;st g14,%1\";
1.1 root 985: }
986: }"
1.1.1.2 ! root 987: [(set_attr "type" "move,move,load,fpload,fpstore,fpstore")])
1.1 root 988:
989: (define_insn ""
1.1.1.2 ! root 990: [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m")
1.1 root 991: (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
992: "current_function_args_size != 0
993: && (register_operand (operands[0], DFmode)
994: || register_operand (operands[1], DFmode))"
995: "*
996: {
997: switch (which_alternative)
998: {
999: case 0:
1000: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1001: return \"movrl %1,%0\";
1002: else
1003: return \"movl %1,%0\";
1004: case 1:
1005: return \"movrl %1,%0\";
1006: case 2:
1007: return i960_output_ldconst (operands[0], operands[1]);
1008: case 3:
1009: return \"ldl %1,%0\";
1010: case 4:
1011: return \"stl %1,%0\";
1012: }
1013: }"
1014: [(set_attr "type" "move,move,load,fpload,fpstore")])
1015:
1016: (define_expand "movsf"
1017: [(set (match_operand:SF 0 "general_operand" "")
1018: (match_operand:SF 1 "fpmove_src_operand" ""))]
1019: ""
1020: "
1021: {
1022: if (emit_move_sequence (operands, SFmode))
1023: DONE;
1024: }")
1025:
1026: (define_insn ""
1.1.1.2 ! root 1027: [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m")
1.1 root 1028: (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,dG"))]
1029: "current_function_args_size == 0
1030: && (register_operand (operands[0], SFmode)
1031: || register_operand (operands[1], SFmode)
1032: || operands[1] == CONST0_RTX (SFmode))"
1033: "*
1034: {
1035: switch (which_alternative)
1036: {
1037: case 0:
1038: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1039: return \"movr %1,%0\";
1040: else
1041: return \"mov %1,%0\";
1042: case 1:
1043: return \"movr %1,%0\";
1044: case 2:
1045: return i960_output_ldconst (operands[0], operands[1]);
1046: case 3:
1047: return \"ld %1,%0\";
1048: case 4:
1049: if (operands[1] == CONST0_RTX (SFmode))
1050: return \"st g14,%0\";
1051: return \"st %1,%0\";
1052: }
1053: }"
1054: [(set_attr "type" "move,move,load,fpload,fpstore")])
1055:
1056: (define_insn ""
1.1.1.2 ! root 1057: [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m")
1.1 root 1058: (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
1059: "current_function_args_size != 0
1060: && (register_operand (operands[0], SFmode)
1061: || register_operand (operands[1], SFmode))"
1062: "*
1063: {
1064: switch (which_alternative)
1065: {
1066: case 0:
1067: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1068: return \"movr %1,%0\";
1069: else
1070: return \"mov %1,%0\";
1071: case 1:
1072: return \"movr %1,%0\";
1073: case 2:
1074: return i960_output_ldconst (operands[0], operands[1]);
1075: case 3:
1076: return \"ld %1,%0\";
1077: case 4:
1078: return \"st %1,%0\";
1079: }
1080: }"
1081: [(set_attr "type" "move,move,load,fpload,fpstore")])
1082:
1083: ;; Mixed-mode moves with sign and zero-extension.
1084:
1085: ;; Note that the one starting from HImode comes before those for QImode
1086: ;; so that a constant operand will match HImode, not QImode.
1087:
1088: (define_expand "extendhisi2"
1089: [(set (match_operand:SI 0 "register_operand" "")
1090: (sign_extend:SI
1091: (match_operand:HI 1 "nonimmediate_operand" "")))]
1092: ""
1093: "
1094: {
1095: if (GET_CODE (operand1) == REG
1096: || (GET_CODE (operand1) == SUBREG
1097: && GET_CODE (XEXP (operand1, 0)) == REG))
1098: {
1099: rtx temp = gen_reg_rtx (SImode);
1100: rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16);
1101: int op1_subreg_word = 0;
1102:
1103: if (GET_CODE (operand1) == SUBREG)
1104: {
1105: op1_subreg_word = SUBREG_WORD (operand1);
1106: operand1 = SUBREG_REG (operand1);
1107: }
1108: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1109:
1110: emit_insn (gen_ashlsi3 (temp, operand1, shift_16));
1111: emit_insn (gen_ashrsi3 (operand0, temp, shift_16));
1112: DONE;
1113: }
1114: }")
1115:
1116: (define_insn ""
1117: [(set (match_operand:SI 0 "register_operand" "=d")
1118: (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
1119: ""
1120: "ldis %1,%0"
1121: [(set_attr "type" "load")])
1122:
1123: (define_expand "extendqisi2"
1124: [(set (match_operand:SI 0 "register_operand" "")
1125: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1126: ""
1127: "
1128: {
1129: if (GET_CODE (operand1) == REG
1130: || (GET_CODE (operand1) == SUBREG
1131: && GET_CODE (XEXP (operand1, 0)) == REG))
1132: {
1133: rtx temp = gen_reg_rtx (SImode);
1134: rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24);
1135: int op1_subreg_word = 0;
1136:
1137: if (GET_CODE (operand1) == SUBREG)
1138: {
1139: op1_subreg_word = SUBREG_WORD (operand1);
1140: operand1 = SUBREG_REG (operand1);
1141: }
1142: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word),
1143:
1144: emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
1145: emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
1146: DONE;
1147: }
1148: }")
1149:
1150: (define_insn ""
1151: [(set (match_operand:SI 0 "register_operand" "=d")
1152: (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
1153: ""
1154: "ldib %1,%0"
1155: [(set_attr "type" "load")])
1156:
1157: (define_expand "extendqihi2"
1158: [(set (match_operand:HI 0 "register_operand" "")
1159: (sign_extend:HI
1160: (match_operand:QI 1 "nonimmediate_operand" "")))]
1161: ""
1162: "
1163: {
1164: if (GET_CODE (operand1) == REG
1165: || (GET_CODE (operand1) == SUBREG
1166: && GET_CODE (XEXP (operand1, 0)) == REG))
1167: {
1168: rtx temp = gen_reg_rtx (SImode);
1169: rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24);
1170: int op0_subreg_word = 0;
1171: int op1_subreg_word = 0;
1172:
1173: if (GET_CODE (operand1) == SUBREG)
1174: {
1175: op1_subreg_word = SUBREG_WORD (operand1);
1176: operand1 = SUBREG_REG (operand1);
1177: }
1178: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1179:
1180: if (GET_CODE (operand0) == SUBREG)
1181: {
1182: op0_subreg_word = SUBREG_WORD (operand0);
1183: operand0 = SUBREG_REG (operand0);
1184: }
1185: if (GET_MODE (operand0) != SImode)
1186: operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word);
1187:
1188: emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
1189: emit_insn (gen_ashrsi3 (operand0, temp, shift_24));
1190: DONE;
1191: }
1192: }")
1193:
1194: (define_insn ""
1195: [(set (match_operand:HI 0 "register_operand" "=d")
1196: (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
1197: ""
1198: "ldib %1,%0"
1199: [(set_attr "type" "load")])
1200:
1201: (define_expand "zero_extendhisi2"
1202: [(set (match_operand:SI 0 "register_operand" "")
1203: (zero_extend:SI
1204: (match_operand:HI 1 "nonimmediate_operand" "")))]
1205: ""
1206: "
1207: {
1208: if (GET_CODE (operand1) == REG
1209: || (GET_CODE (operand1) == SUBREG
1210: && GET_CODE (XEXP (operand1, 0)) == REG))
1211: {
1212: rtx temp = gen_reg_rtx (SImode);
1213: rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16);
1214: int op1_subreg_word = 0;
1215:
1216: if (GET_CODE (operand1) == SUBREG)
1217: {
1218: op1_subreg_word = SUBREG_WORD (operand1);
1219: operand1 = SUBREG_REG (operand1);
1220: }
1221: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1222:
1223: emit_insn (gen_ashlsi3 (temp, operand1, shift_16));
1224: emit_insn (gen_lshrsi3 (operand0, temp, shift_16));
1225: DONE;
1226: }
1227: }")
1228:
1229: (define_insn ""
1230: [(set (match_operand:SI 0 "register_operand" "=d")
1231: (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))]
1232: ""
1233: "ldos %1,%0"
1234: [(set_attr "type" "load")])
1235:
1236: ;; Using shifts here generates much better code than doing an `and 255'.
1237: ;; This is mainly because the `and' requires loading the constant separately,
1238: ;; the constant is likely to get optimized, and then the compiler can't
1239: ;; optimize the `and' because it doesn't know that one operand is a constant.
1240:
1241: (define_expand "zero_extendqisi2"
1242: [(set (match_operand:SI 0 "register_operand" "")
1243: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
1244: ""
1245: "
1246: {
1247: if (GET_CODE (operand1) == REG
1248: || (GET_CODE (operand1) == SUBREG
1249: && GET_CODE (XEXP (operand1, 0)) == REG))
1250: {
1251: rtx temp = gen_reg_rtx (SImode);
1252: rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24);
1253: int op1_subreg_word = 0;
1254:
1255: if (GET_CODE (operand1) == SUBREG)
1256: {
1257: op1_subreg_word = SUBREG_WORD (operand1);
1258: operand1 = SUBREG_REG (operand1);
1259: }
1260: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1261:
1262: emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
1263: emit_insn (gen_lshrsi3 (operand0, temp, shift_24));
1264: DONE;
1265: }
1266: }")
1267:
1268: (define_insn ""
1269: [(set (match_operand:SI 0 "register_operand" "=d")
1270: (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))]
1271: ""
1272: "ldob %1,%0"
1273: [(set_attr "type" "load")])
1274:
1275: (define_expand "zero_extendqihi2"
1276: [(set (match_operand:HI 0 "register_operand" "")
1277: (zero_extend:HI
1278: (match_operand:QI 1 "nonimmediate_operand" "")))]
1279: ""
1280: "
1281: {
1282: if (GET_CODE (operand1) == REG
1283: || (GET_CODE (operand1) == SUBREG
1284: && GET_CODE (XEXP (operand1, 0)) == REG))
1285: {
1286: rtx temp = gen_reg_rtx (SImode);
1287: rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24);
1288: int op0_subreg_word = 0;
1289: int op1_subreg_word = 0;
1290:
1291: if (GET_CODE (operand1) == SUBREG)
1292: {
1293: op1_subreg_word = SUBREG_WORD (operand1);
1294: operand1 = SUBREG_REG (operand1);
1295: }
1296: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word);
1297:
1298: if (GET_CODE (operand0) == SUBREG)
1299: {
1300: op0_subreg_word = SUBREG_WORD (operand0);
1301: operand0 = SUBREG_REG (operand0);
1302: }
1303: if (GET_MODE (operand0) != SImode)
1304: operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word);
1305:
1306: emit_insn (gen_ashlsi3 (temp, operand1, shift_24));
1307: emit_insn (gen_lshrsi3 (operand0, temp, shift_24));
1308: DONE;
1309: }
1310: }")
1311:
1312: (define_insn ""
1313: [(set (match_operand:HI 0 "register_operand" "=d")
1314: (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))]
1315: ""
1316: "ldob %1,%0"
1317: [(set_attr "type" "load")])
1318:
1319: ;; Conversions between float and double.
1320:
1321: (define_insn "extendsfdf2"
1.1.1.2 ! root 1322: [(set (match_operand:DF 0 "register_operand" "=*f,d")
1.1 root 1323: (float_extend:DF (match_operand:SF 1 "fp_arith_operand" "dGH,fGH")))]
1324: "TARGET_NUMERICS"
1325: "@
1326: movr %1,%0
1327: movrl %1,%0"
1328: [(set_attr "type" "fpmove")])
1329:
1330: (define_insn "truncdfsf2"
1331: [(set (match_operand:SF 0 "register_operand" "=d")
1332: (float_truncate:SF
1333: (match_operand:DF 1 "fp_arith_operand" "fGH")))]
1334: "TARGET_NUMERICS"
1335: "movr %1,%0"
1336: [(set_attr "type" "fpmove")])
1337:
1338: ;; Conversion between fixed point and floating point.
1339:
1340: (define_insn "floatsidf2"
1341: [(set (match_operand:DF 0 "register_operand" "=f")
1342: (float:DF (match_operand:SI 1 "register_operand" "d")))]
1343: "TARGET_NUMERICS"
1344: "cvtir %1,%0"
1345: [(set_attr "type" "fpcvt")])
1346:
1347: (define_insn "floatsisf2"
1.1.1.2 ! root 1348: [(set (match_operand:SF 0 "register_operand" "=d*f")
1.1 root 1349: (float:SF (match_operand:SI 1 "register_operand" "d")))]
1350: "TARGET_NUMERICS"
1351: "cvtir %1,%0"
1352: [(set_attr "type" "fpcvt")])
1353:
1354: ;; Convert a float to an actual integer.
1355: ;; Truncation is performed as part of the conversion.
1356: ;; The i960 requires conversion from DFmode to DImode to make
1357: ;; unsigned conversions work properly.
1358:
1359: (define_insn "fixuns_truncdfdi2"
1360: [(set (match_operand:DI 0 "register_operand" "=d")
1361: (unsigned_fix:DI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))]
1362: "TARGET_NUMERICS"
1363: "cvtzril %1,%0"
1364: [(set_attr "type" "fpcvt")])
1365:
1366: (define_insn "fixuns_truncsfdi2"
1367: [(set (match_operand:DI 0 "register_operand" "=d")
1368: (unsigned_fix:DI (fix:SF (match_operand:SF 1 "fp_arith_operand" "fGH"))))]
1369: "TARGET_NUMERICS"
1370: "cvtzril %1,%0"
1371: [(set_attr "type" "fpcvt")])
1372:
1373: (define_insn "fix_truncdfsi2"
1374: [(set (match_operand:SI 0 "register_operand" "=d")
1375: (fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))]
1376: "TARGET_NUMERICS"
1377: "cvtzri %1,%0"
1378: [(set_attr "type" "fpcvt")])
1379:
1380: (define_expand "fixuns_truncdfsi2"
1381: [(set (match_operand:SI 0 "register_operand" "")
1382: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" ""))))]
1383: "TARGET_NUMERICS"
1384: "
1385: {
1386: rtx temp = gen_reg_rtx (DImode);
1387: emit_insn (gen_rtx (SET, VOIDmode, temp,
1388: gen_rtx (UNSIGNED_FIX, DImode,
1389: gen_rtx (FIX, DFmode, operands[1]))));
1390: emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1391: gen_rtx (SUBREG, SImode, temp, 0)));
1392: DONE;
1393: }")
1394:
1395: (define_insn "fix_truncsfsi2"
1396: [(set (match_operand:SI 0 "register_operand" "=d")
1397: (fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" "dfGH"))))]
1398: "TARGET_NUMERICS"
1399: "cvtzri %1,%0"
1400: [(set_attr "type" "fpcvt")])
1401:
1402: (define_expand "fixuns_truncsfsi2"
1403: [(set (match_operand:SI 0 "register_operand" "")
1404: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" ""))))]
1405: "TARGET_NUMERICS"
1406: "
1407: {
1408: rtx temp = gen_reg_rtx (DImode);
1409: emit_insn (gen_rtx (SET, VOIDmode, temp,
1410: gen_rtx (UNSIGNED_FIX, DImode,
1411: gen_rtx (FIX, SFmode, operands[1]))));
1412: emit_insn (gen_rtx (SET, VOIDmode, operands[0],
1413: gen_rtx (SUBREG, SImode, temp, 0)));
1414: DONE;
1415: }")
1416:
1417: ;; Arithmetic instructions.
1418:
1419: (define_insn "subsi3"
1420: [(set (match_operand:SI 0 "register_operand" "=d")
1421: (minus:SI (match_operand:SI 1 "arith_operand" "dI")
1422: (match_operand:SI 2 "arith_operand" "dI")))]
1423: ""
1424: "subo %2,%1,%0")
1425:
1426: ;; Try to generate an lda instruction when it would be faster than an
1427: ;; add instruction.
1428: ;; Some assemblers apparently won't accept two addresses added together.
1429:
1430: (define_insn ""
1431: [(set (match_operand:SI 0 "register_operand" "=d,d,d")
1432: (plus:SI (match_operand:SI 1 "arith32_operand" "%dn,i,dn")
1433: (match_operand:SI 2 "arith32_operand" "dn,dn,i")))]
1434: "(TARGET_C_SERIES) && (CONSTANT_P (operands[1]) || CONSTANT_P (operands[2]))"
1435: "*
1436: {
1437: if (GET_CODE (operands[1]) == CONST_INT)
1438: {
1439: rtx tmp = operands[1];
1440: operands[1] = operands[2];
1441: operands[2] = tmp;
1442: }
1443: if (GET_CODE (operands[2]) == CONST_INT
1444: && GET_CODE (operands[1]) == REG
1445: && i960_last_insn_type != I_TYPE_REG)
1446: {
1447: if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) > -32)
1448: return \"subo %n2,%1,%0\";
1449: else if (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32)
1450: return \"addo %1,%2,%0\";
1451: }
1452: if (CONSTANT_P (operands[1]))
1453: return \"lda %1+%2,%0\";
1454: return \"lda %2(%1),%0\";
1455: }")
1456:
1457: (define_insn "addsi3"
1458: [(set (match_operand:SI 0 "register_operand" "=d")
1459: (plus:SI (match_operand:SI 1 "signed_arith_operand" "%dI")
1460: (match_operand:SI 2 "signed_arith_operand" "dIK")))]
1461: ""
1462: "*
1463: {
1464: if (GET_CODE (operands[2]) == CONST_INT
1465: && INTVAL (operands[2]) < 0 && INTVAL (operands[2]) > -32)
1466: return \"subo %n2,%1,%0\";
1467: if (i960_bypass (insn, operands[1], operands[2], 0))
1468: return \"addo %2,%1,%0\";
1469: return \"addo %1,%2,%0\";
1470: }")
1471:
1472: (define_insn "mulsi3"
1473: [(set (match_operand:SI 0 "register_operand" "=d")
1474: (mult:SI (match_operand:SI 1 "arith_operand" "%dI")
1475: (match_operand:SI 2 "arith_operand" "dI")))]
1476: ""
1477: "*
1478: {
1479: if (i960_bypass (insn, operands[1], operands[2], 0))
1480: return \"mulo %2,%1,%0\";
1481: return \"mulo %1,%2,%0\";
1482: }"
1483: [(set_attr "type" "mult")])
1484:
1485: ;; This goes after the move/add/sub/mul instructions
1486: ;; because those instructions are better when they apply.
1487:
1488: (define_insn ""
1489: [(set (match_operand:SI 0 "register_operand" "=d")
1490: (match_operand:SI 1 "address_operand" "p"))]
1491: ""
1492: "lda %a1,%0"
1493: [(set_attr "type" "load")])
1494:
1495: ;; This will never be selected because of an "optimization" that GCC does.
1496: ;; It always converts divides by a power of 2 into a sequence of instructions
1497: ;; that does a right shift, and then corrects the result if it was negative.
1498:
1499: ;; (define_insn ""
1500: ;; [(set (match_operand:SI 0 "register_operand" "=d")
1501: ;; (div:SI (match_operand:SI 1 "arith_operand" "dI")
1502: ;; (match_operand:SI 2 "power2_operand" "nI")))]
1503: ;; ""
1504: ;; "*{
1505: ;; operands[2] = gen_rtx(CONST_INT, VOIDmode,bitpos (INTVAL (operands[2])));
1506: ;; return \"shrdi %2,%1,%0\";
1507: ;; }"
1508:
1509: (define_insn "divsi3"
1510: [(set (match_operand:SI 0 "register_operand" "=d")
1511: (div:SI (match_operand:SI 1 "arith_operand" "dI")
1512: (match_operand:SI 2 "arith_operand" "dI")))]
1513: ""
1514: "divi %2,%1,%0"
1515: [(set_attr "type" "div")])
1516:
1517: (define_insn "udivsi3"
1518: [(set (match_operand:SI 0 "register_operand" "=d")
1519: (udiv:SI (match_operand:SI 1 "arith_operand" "dI")
1520: (match_operand:SI 2 "arith_operand" "dI")))]
1521: ""
1522: "divo %2,%1,%0"
1523: [(set_attr "type" "div")])
1524:
1525: ;; We must use `remi' not `modi' here, to ensure that `%' has the effects
1526: ;; specified by the ANSI C standard.
1527:
1528: (define_insn "modsi3"
1529: [(set (match_operand:SI 0 "register_operand" "=d")
1530: (mod:SI (match_operand:SI 1 "arith_operand" "dI")
1531: (match_operand:SI 2 "arith_operand" "dI")))]
1532: ""
1533: "remi %2,%1,%0"
1534: [(set_attr "type" "div")])
1535:
1536: (define_insn "umodsi3"
1537: [(set (match_operand:SI 0 "register_operand" "=d")
1538: (umod:SI (match_operand:SI 1 "arith_operand" "dI")
1539: (match_operand:SI 2 "arith_operand" "dI")))]
1540: ""
1541: "remo %2,%1,%0"
1542: [(set_attr "type" "div")])
1543:
1544: ;; And instructions (with complement also).
1545:
1546: (define_insn "andsi3"
1547: [(set (match_operand:SI 0 "register_operand" "=d")
1548: (and:SI (match_operand:SI 1 "arith_operand" "%dI")
1549: (match_operand:SI 2 "arith_operand" "dI")))]
1550: ""
1551: "*
1552: {
1553: if (i960_bypass (insn, operands[1], operands[2], 0))
1554: return \"and %2,%1,%0\";
1555: return \"and %1,%2,%0\";
1556: }")
1557:
1558: (define_insn ""
1559: [(set (match_operand:SI 0 "register_operand" "=d")
1560: (and:SI (not:SI (match_operand:SI 1 "arith_operand" "dI"))
1561: (match_operand:SI 2 "arith_operand" "dI")))]
1562: ""
1563: "*
1564: {
1565: if (i960_bypass (insn, operands[1], operands[2], 0))
1566: return \"notand %2,%1,%0\";
1567: return \"andnot %1,%2,%0\";
1568: }")
1569:
1570: (define_insn ""
1571: [(set (match_operand:SI 0 "register_operand" "=d")
1572: (ior:SI (not:SI (match_operand:SI 1 "arith_operand" "%dI"))
1573: (not:SI (match_operand:SI 2 "arith_operand" "dI"))))]
1574: ""
1575: "*
1576: {
1577: if (i960_bypass (insn, operands[1], operands[2], 0))
1578: return \"nand %2,%1,%0\";
1579: return \"nand %1,%2,%0\";
1580: }")
1581:
1582: (define_insn ""
1583: [(set (match_operand:SI 0 "register_operand" "=d")
1584: (not:SI (and:SI (match_operand:SI 1 "arith_operand" "%dI")
1585: (match_operand:SI 2 "arith_operand" "dI"))))]
1586: ""
1587: "*
1588: {
1589: if (i960_bypass (insn, operands[1], operands[2], 0))
1590: return \"nand %2,%1,%0\";
1591: return \"nand %1,%2,%0\";
1592: }")
1593:
1594: (define_insn ""
1595: [(set (match_operand:SI 0 "register_operand" "=d")
1596: (ior:SI (match_operand:SI 1 "arith_operand" "dI")
1597: (match_operand:SI 2 "power2_operand" "n")))]
1598: ""
1599: "*
1600: {
1601: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1602: bitpos (INTVAL (operands[2])));
1603: return \"setbit %2,%1,%0\";
1604: }")
1605:
1606: (define_insn ""
1607: [(set (match_operand:SI 0 "register_operand" "=d")
1608: (ior:SI (match_operand:SI 1 "power2_operand" "n")
1609: (match_operand:SI 2 "arith_operand" "dI")))]
1610: ""
1611: "*
1612: {
1613: operands[1] = gen_rtx (CONST_INT, VOIDmode,
1614: bitpos (INTVAL (operands[1])));
1615: return \"setbit %1,%2,%0\";
1616: }")
1617:
1618: (define_insn "iorsi3"
1619: [(set (match_operand:SI 0 "register_operand" "=d")
1620: (ior:SI (match_operand:SI 1 "arith_operand" "%dI")
1621: (match_operand:SI 2 "arith_operand" "dI")))]
1622: ""
1623: "*
1624: {
1625: if (i960_bypass (insn, operands[1], operands[2], 0))
1626: return \"or %2,%1,%0\";
1627: return \"or %1,%2,%0\";
1628: }")
1629:
1630: (define_insn ""
1631: [(set (match_operand:SI 0 "register_operand" "=d")
1632: (ior:SI (not:SI (match_operand:SI 1 "arith_operand" "dI"))
1633: (match_operand:SI 2 "arith_operand" "dI")))]
1634: ""
1635: "*
1636: {
1637: if (i960_bypass (insn, operands[1], operands[2], 0))
1638: return \"notor %2,%1,%0\";
1639: return \"ornot %1,%2,%0\";
1640: }")
1641:
1642: (define_insn ""
1643: [(set (match_operand:SI 0 "register_operand" "=d")
1644: (and:SI (not:SI (match_operand:SI 1 "arith_operand" "%dI"))
1645: (not:SI (match_operand:SI 2 "arith_operand" "dI"))))]
1646: ""
1647: "*
1648: {
1649: if (i960_bypass (insn, operands[1], operands[2], 0))
1650: return \"nor %2,%1,%0\";
1651: return \"nor %1,%2,%0\";
1652: }")
1653:
1654: (define_insn ""
1655: [(set (match_operand:SI 0 "register_operand" "=d")
1656: (not:SI (ior:SI (match_operand:SI 1 "arith_operand" "%dI")
1657: (match_operand:SI 2 "arith_operand" "dI"))))]
1658: ""
1659: "*
1660: {
1661: if (i960_bypass (insn, operands[1], operands[2], 0))
1662: return \"nor %2,%1,%0\";
1663: return \"nor %1,%2,%0\";
1664: }")
1665:
1666: (define_insn "xorsi3"
1667: [(set (match_operand:SI 0 "register_operand" "=d")
1668: (xor:SI (match_operand:SI 1 "arith_operand" "%dI")
1669: (match_operand:SI 2 "arith_operand" "dI")))]
1670: ""
1671: "*
1672: {
1673: if (i960_bypass (insn, operands[1], operands[2], 0))
1674: return \"xor %2,%1,%0\";
1675: return \"xor %1,%2,%0\";
1676: }")
1677:
1678: (define_insn ""
1679: [(set (match_operand:SI 0 "register_operand" "=d")
1680: (not:SI (xor:SI (match_operand:SI 1 "arith_operand" "%dI")
1681: (match_operand:SI 2 "arith_operand" "dI"))))]
1682: ""
1683: "*
1684: {
1685: if (i960_bypass (insn, operands[1], operands[2], 0))
1686: return \"xnor %2,%1,%0\";
1687: return \"xnor %2,%1,%0\";
1688: }")
1689:
1690: (define_insn "negsi2"
1691: [(set (match_operand:SI 0 "register_operand" "=d")
1692: (neg:SI (match_operand:SI 1 "arith_operand" "dI")))]
1693: ""
1694: "subo %1,0,%0"
1695: [(set_attr "length" "1")])
1696:
1697: (define_insn "one_cmplsi2"
1698: [(set (match_operand:SI 0 "register_operand" "=d")
1699: (not:SI (match_operand:SI 1 "arith_operand" "dI")))]
1700: ""
1701: "not %1,%0"
1702: [(set_attr "length" "1")])
1703:
1704: ;; Floating point arithmetic instructions.
1705:
1706: (define_insn "adddf3"
1.1.1.2 ! root 1707: [(set (match_operand:DF 0 "register_operand" "=d*f")
1.1 root 1708: (plus:DF (match_operand:DF 1 "fp_arith_operand" "%rGH")
1709: (match_operand:DF 2 "fp_arith_operand" "rGH")))]
1710: "TARGET_NUMERICS"
1711: "addrl %1,%2,%0"
1712: [(set_attr "type" "fpadd")])
1713:
1714: (define_insn "addsf3"
1.1.1.2 ! root 1715: [(set (match_operand:SF 0 "register_operand" "=d*f")
1.1 root 1716: (plus:SF (match_operand:SF 1 "fp_arith_operand" "%rGH")
1717: (match_operand:SF 2 "fp_arith_operand" "rGH")))]
1718: "TARGET_NUMERICS"
1719: "addr %1,%2,%0"
1720: [(set_attr "type" "fpadd")])
1721:
1722:
1723: (define_insn "subdf3"
1.1.1.2 ! root 1724: [(set (match_operand:DF 0 "register_operand" "=d*f")
1.1 root 1725: (minus:DF (match_operand:DF 1 "fp_arith_operand" "rGH")
1726: (match_operand:DF 2 "fp_arith_operand" "rGH")))]
1727: "TARGET_NUMERICS"
1728: "subrl %2,%1,%0"
1729: [(set_attr "type" "fpadd")])
1730:
1731: (define_insn "subsf3"
1.1.1.2 ! root 1732: [(set (match_operand:SF 0 "register_operand" "=d*f")
1.1 root 1733: (minus:SF (match_operand:SF 1 "fp_arith_operand" "rGH")
1734: (match_operand:SF 2 "fp_arith_operand" "rGH")))]
1735: "TARGET_NUMERICS"
1736: "subr %2,%1,%0"
1737: [(set_attr "type" "fpadd")])
1738:
1739:
1740: (define_insn "muldf3"
1.1.1.2 ! root 1741: [(set (match_operand:DF 0 "register_operand" "=d*f")
1.1 root 1742: (mult:DF (match_operand:DF 1 "fp_arith_operand" "rGH")
1743: (match_operand:DF 2 "fp_arith_operand" "rGH")))]
1744: "TARGET_NUMERICS"
1745: "mulrl %1,%2,%0"
1746: [(set_attr "type" "fpmul")])
1747:
1748: (define_insn "mulsf3"
1.1.1.2 ! root 1749: [(set (match_operand:SF 0 "register_operand" "=d*f")
1.1 root 1750: (mult:SF (match_operand:SF 1 "fp_arith_operand" "rGH")
1751: (match_operand:SF 2 "fp_arith_operand" "rGH")))]
1752: "TARGET_NUMERICS"
1753: "mulr %1,%2,%0"
1754: [(set_attr "type" "fpmul")])
1755:
1756:
1757: (define_insn "divdf3"
1.1.1.2 ! root 1758: [(set (match_operand:DF 0 "register_operand" "=d*f")
1.1 root 1759: (div:DF (match_operand:DF 1 "fp_arith_operand" "rGH")
1760: (match_operand:DF 2 "fp_arith_operand" "rGH")))]
1761: "TARGET_NUMERICS"
1762: "divrl %2,%1,%0"
1763: [(set_attr "type" "fpdiv")])
1764:
1765: (define_insn "divsf3"
1.1.1.2 ! root 1766: [(set (match_operand:SF 0 "register_operand" "=d*f")
1.1 root 1767: (div:SF (match_operand:SF 1 "fp_arith_operand" "rGH")
1768: (match_operand:SF 2 "fp_arith_operand" "rGH")))]
1769: "TARGET_NUMERICS"
1770: "divr %2,%1,%0"
1771: [(set_attr "type" "fpdiv")])
1772:
1773: (define_insn "negdf2"
1.1.1.2 ! root 1774: [(set (match_operand:DF 0 "register_operand" "=d,d*f")
1.1 root 1775: (neg:DF (match_operand:DF 1 "register_operand" "d,r")))]
1776: ""
1777: "*
1778: {
1779: if (which_alternative == 0)
1780: {
1781: if (REGNO (operands[0]) == REGNO (operands[1]))
1782: return \"notbit 31,%D1,%D0\";
1783: return \"mov %1,%0\;notbit 31,%D1,%D0\";
1784: }
1785: return \"subrl %1,0f0.0,%0\";
1786: }"
1787: [(set_attr "type" "fpadd")])
1788:
1789: (define_insn "negsf2"
1.1.1.2 ! root 1790: [(set (match_operand:SF 0 "register_operand" "=d,d*f")
1.1 root 1791: (neg:SF (match_operand:SF 1 "register_operand" "d,r")))]
1792: ""
1793: "@
1794: notbit 31,%1,%0
1795: subr %1,0f0.0,%0"
1796: [(set_attr "type" "fpadd")])
1797:
1798: ;;; The abs patterns also work even if the target machine doesn't have
1799: ;;; floating point, because in that case dstreg and srcreg will always be
1800: ;;; less than 32.
1801:
1802: (define_insn "absdf2"
1.1.1.2 ! root 1803: [(set (match_operand:DF 0 "register_operand" "=d*f")
1.1 root 1804: (abs:DF (match_operand:DF 1 "register_operand" "df")))]
1805: ""
1806: "*
1807: {
1808: int dstreg = REGNO (operands[0]);
1809: int srcreg = REGNO (operands[1]);
1810:
1811: if (dstreg < 32)
1812: {
1813: if (srcreg < 32)
1814: {
1815: if (dstreg != srcreg)
1816: output_asm_insn (\"mov %1,%0\", operands);
1817: return \"clrbit 31,%D1,%D0\";
1818: }
1819: /* Src is an fp reg. */
1820: return \"movrl %1,%0\;clrbit 31,%D1,%D0\";
1821: }
1822: if (srcreg >= 32)
1823: return \"cpysre %1,0f0.0,%0\";
1824: return \"movrl %1,%0\;cpysre %0,0f0.0,%0\";
1825: }"
1826: [(set_attr "type" "multi")])
1827:
1828: (define_insn "abssf2"
1.1.1.2 ! root 1829: [(set (match_operand:SF 0 "register_operand" "=d*f")
1.1 root 1830: (abs:SF (match_operand:SF 1 "register_operand" "df")))]
1831: ""
1832: "*
1833: {
1834: int dstreg = REGNO (operands[0]);
1835: int srcreg = REGNO (operands[1]);
1836:
1837: if (dstreg < 32 && srcreg < 32)
1838: return \"clrbit 31,%1,%0\";
1839:
1840: if (dstreg >= 32 && srcreg >= 32)
1841: return \"cpysre %1,0f0.0,%0\";
1842:
1843: if (dstreg < 32)
1844: return \"movr %1,%0\;clrbit 31,%0,%0\";
1845:
1846: return \"movr %1,%0\;cpysre %0,0f0.0,%0\";
1847: }"
1848: [(set_attr "type" "multi")])
1849:
1850: ;; Tetra (16 byte) float support.
1851:
1852: (define_insn "cmptf"
1853: [(set (reg:CC 36)
1854: (compare:CC (match_operand:TF 0 "register_operand" "f")
1855: (match_operand:TF 1 "nonmemory_operand" "fG")))]
1856: "TARGET_NUMERICS"
1857: "cmpr %0,%1"
1858: [(set_attr "type" "fpcc")])
1859:
1860: (define_expand "movtf"
1861: [(set (match_operand:TF 0 "general_operand" "")
1862: (match_operand:TF 1 "fpmove_src_operand" ""))]
1863: ""
1864: "
1865: {
1866: if (emit_move_sequence (operands, TFmode))
1867: DONE;
1868: }")
1869:
1870: (define_insn ""
1.1.1.2 ! root 1871: [(set (match_operand:TF 0 "general_operand" "=r,*f,d,d,m,o")
! 1872: (match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d,G"))]
1.1 root 1873: "current_function_args_size == 0
1874: && (register_operand (operands[0], TFmode)
1875: || register_operand (operands[1], TFmode)
1876: || operands[1] == CONST0_RTX (TFmode))"
1877: "*
1878: {
1879: switch (which_alternative)
1880: {
1881: case 0:
1882: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1883: return \"movre %1,%0\";
1884: else
1885: return \"movq %1,%0\";
1886: case 1:
1887: return \"movre %1,%0\";
1888: case 2:
1889: return i960_output_ldconst (operands[0], operands[1]);
1890: case 3:
1891: return \"ldq %1,%0\";
1892: case 4:
1893: return \"stq %1,%0\";
1.1.1.2 ! root 1894: case 5:
! 1895: operands[1] = adj_offsettable_operand (operands[0], 4);
! 1896: operands[2] = adj_offsettable_operand (operands[0], 8);
! 1897: operands[3] = adj_offsettable_operand (operands[0], 12);
! 1898: return \"st g14,%0\;st g14,%1\;st g14,%2\;st g14,%3\";
1.1 root 1899: }
1900: }"
1.1.1.2 ! root 1901: [(set_attr "type" "move,move,load,fpload,fpstore,fpstore")])
1.1 root 1902:
1903: (define_insn ""
1.1.1.2 ! root 1904: [(set (match_operand:TF 0 "general_operand" "=r,*f,d,d,m")
1.1 root 1905: (match_operand:TF 1 "fpmove_src_operand" "r,GH,F,m,d"))]
1906: "current_function_args_size != 0
1907: && (register_operand (operands[0], TFmode)
1908: || register_operand (operands[1], TFmode))"
1909: "*
1910: {
1911: switch (which_alternative)
1912: {
1913: case 0:
1914: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1915: return \"movre %1,%0\";
1916: else
1917: return \"movq %1,%0\";
1918: case 1:
1919: return \"movre %1,%0\";
1920: case 2:
1921: return i960_output_ldconst (operands[0], operands[1]);
1922: case 3:
1923: return \"ldq %1,%0\";
1924: case 4:
1925: return \"stq %1,%0\";
1926: }
1927: }"
1928: [(set_attr "type" "move,move,load,fpload,fpstore")])
1929:
1930: (define_insn "extendsftf2"
1.1.1.2 ! root 1931: [(set (match_operand:TF 0 "register_operand" "=*f,d")
1.1 root 1932: (float_extend:TF
1933: (match_operand:SF 1 "register_operand" "d,f")))]
1934: "TARGET_NUMERICS"
1935: "@
1936: movr %1,%0
1937: movre %1,%0"
1938: [(set_attr "type" "fpmove")])
1939:
1940: (define_insn "extenddftf2"
1.1.1.2 ! root 1941: [(set (match_operand:TF 0 "register_operand" "=*f,d")
1.1 root 1942: (float_extend:TF
1943: (match_operand:DF 1 "register_operand" "d,f")))]
1944: "TARGET_NUMERICS"
1945: "@
1946: movrl %1,%0
1947: movre %1,%0"
1948: [(set_attr "type" "fpmove")])
1949:
1950: (define_insn "trunctfdf2"
1951: [(set (match_operand:DF 0 "register_operand" "=d")
1952: (float_truncate:DF
1953: (match_operand:TF 1 "register_operand" "f")))]
1954: "TARGET_NUMERICS"
1955: "movrl %1,%0"
1956: [(set_attr "type" "fpmove")])
1957:
1958: (define_insn "trunctfsf2"
1959: [(set (match_operand:SF 0 "register_operand" "=d")
1960: (float_truncate:SF
1961: (match_operand:TF 1 "register_operand" "f")))]
1962: "TARGET_NUMERICS"
1963: "movr %1,%0"
1964: [(set_attr "type" "fpmove")])
1965:
1966: (define_insn "floatsitf2"
1967: [(set (match_operand:TF 0 "register_operand" "=f")
1968: (float:TF (match_operand:SI 1 "register_operand" "d")))]
1969: "TARGET_NUMERICS"
1970: "cvtir %1,%0"
1971: [(set_attr "type" "fpcvt")])
1972:
1973: (define_insn "fix_trunctfsi2"
1974: [(set (match_operand:SI 0 "register_operand" "=d")
1975: (fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))]
1976: "TARGET_NUMERICS"
1977: "cvtzri %1,%0"
1978: [(set_attr "type" "fpcvt")])
1979:
1980: (define_insn "fixuns_trunctfsi2"
1981: [(set (match_operand:SI 0 "register_operand" "=d")
1982: (unsigned_fix:SI (fix:TF (match_operand:TF 1 "register_operand" "f"))))]
1983: "TARGET_NUMERICS"
1984: "cvtzri %1,%0"
1985: [(set_attr "type" "fpcvt")])
1986:
1987: (define_insn "addtf3"
1988: [(set (match_operand:TF 0 "register_operand" "=f")
1989: (plus:TF (match_operand:TF 1 "nonmemory_operand" "%fG")
1990: (match_operand:TF 2 "nonmemory_operand" "fG")))]
1991: "TARGET_NUMERICS"
1992: "addr %1,%2,%0"
1993: [(set_attr "type" "fpadd")])
1994:
1995: (define_insn "subtf3"
1996: [(set (match_operand:TF 0 "register_operand" "=f")
1997: (minus:TF (match_operand:TF 1 "nonmemory_operand" "fG")
1998: (match_operand:TF 2 "nonmemory_operand" "fG")))]
1999: "TARGET_NUMERICS"
2000: "subr %2,%1,%0"
2001: [(set_attr "type" "fpadd")])
2002:
2003: (define_insn "multf3"
2004: [(set (match_operand:TF 0 "register_operand" "=f")
2005: (mult:TF (match_operand:TF 1 "nonmemory_operand" "fG")
2006: (match_operand:TF 2 "nonmemory_operand" "fG")))]
2007: "TARGET_NUMERICS"
2008: "mulr %1,%2,%0"
2009: [(set_attr "type" "fpmul")])
2010:
2011: (define_insn "divtf3"
2012: [(set (match_operand:TF 0 "register_operand" "=f")
2013: (div:TF (match_operand:TF 1 "nonmemory_operand" "fG")
2014: (match_operand:TF 2 "nonmemory_operand" "fG")))]
2015: "TARGET_NUMERICS"
2016: "divr %2,%1,%0"
2017: [(set_attr "type" "fpdiv")])
2018:
2019: (define_insn "negtf2"
2020: [(set (match_operand:TF 0 "register_operand" "=f")
2021: (neg:TF (match_operand:TF 1 "register_operand" "f")))]
2022: "TARGET_NUMERICS"
2023: "subr %1,0f0.0,%0"
2024: [(set_attr "type" "fpadd")])
2025:
2026: (define_insn "abstf2"
2027: [(set (match_operand:TF 0 "register_operand" "=f")
2028: (abs:TF (match_operand:TF 1 "register_operand" "f")))]
2029: "(TARGET_NUMERICS)"
2030: "cpysre %1,0f0.0,%0"
2031: [(set_attr "type" "fpmove")])
2032:
2033: ;; Arithmetic shift instructions.
2034:
2035: (define_insn "ashlsi3"
2036: [(set (match_operand:SI 0 "register_operand" "=d")
2037: (ashift:SI (match_operand:SI 1 "arith_operand" "dI")
2038: (match_operand:SI 2 "arith_operand" "dI")))]
2039: ""
2040: "shli %2,%1,%0"
2041: [(set_attr "type" "alu2")])
2042:
2043: (define_insn "ashrsi3"
2044: [(set (match_operand:SI 0 "register_operand" "=d")
2045: (ashiftrt:SI (match_operand:SI 1 "arith_operand" "dI")
2046: (match_operand:SI 2 "arith_operand" "dI")))]
2047: ""
2048: "shri %2,%1,%0"
2049: [(set_attr "type" "alu2")])
2050:
2051: (define_insn "lshrsi3"
2052: [(set (match_operand:SI 0 "register_operand" "=d")
2053: (lshiftrt:SI (match_operand:SI 1 "arith_operand" "dI")
2054: (match_operand:SI 2 "arith_operand" "dI")))]
2055: ""
2056: "shro %2,%1,%0"
2057: [(set_attr "type" "alu2")])
2058:
2059: ;; Unconditional and other jump instructions.
2060:
2061: (define_insn "jump"
2062: [(set (pc)
2063: (label_ref (match_operand 0 "" "")))]
2064: ""
2065: "b %l0"
2066: [(set_attr "type" "branch")])
2067:
2068: (define_insn "indirect_jump"
1.1.1.2 ! root 2069: [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
1.1 root 2070: ""
1.1.1.2 ! root 2071: "bx %a0"
1.1 root 2072: [(set_attr "type" "branch")])
2073:
2074: (define_insn "tablejump"
2075: [(set (pc) (match_operand:SI 0 "register_operand" "d"))
2076: (use (label_ref (match_operand 1 "" "")))]
2077: ""
2078: "bx (%0)"
2079: [(set_attr "type" "branch")])
2080:
2081: ;;- jump to subroutine
2082:
2083: (define_expand "call"
1.1.1.2 ! root 2084: [(call (match_operand:SI 0 "general_operand" "g")
! 2085: (match_operand:SI 1 "immediate_operand" "i"))]
1.1 root 2086: ""
2087: "
2088: {
1.1.1.2 ! root 2089: emit_insn (gen_call_internal (operands[0], operands[1],
! 2090: virtual_outgoing_args_rtx));
1.1 root 2091: DONE;
2092: }")
2093:
1.1.1.2 ! root 2094: (define_insn "call_internal"
1.1 root 2095: [(call (match_operand:SI 0 "general_operand" "g")
1.1.1.2 ! root 2096: (match_operand:SI 1 "immediate_operand" "i"))
! 2097: (use (match_operand:SI 2 "address_operand" "p"))
! 2098: (clobber (match_scratch:SI 3 "=&d"))]
1.1 root 2099: ""
1.1.1.2 ! root 2100: "* return i960_output_call_insn (operands[0], operands[1], operands[2],
! 2101: operands[3], insn);"
1.1 root 2102: [(set_attr "type" "call")])
2103:
2104: (define_expand "call_value"
2105: [(set (match_operand 0 "register_operand" "=d")
2106: (call (match_operand:SI 1 "general_operand" "g")
2107: (match_operand:SI 2 "immediate_operand" "i")))]
2108: ""
2109: "
2110: {
1.1.1.2 ! root 2111: emit_insn (gen_call_value_internal (operands[0], operands[1], operands[2],
! 2112: virtual_outgoing_args_rtx));
1.1 root 2113: DONE;
2114: }")
2115:
1.1.1.2 ! root 2116: (define_insn "call_value_internal"
1.1 root 2117: [(set (match_operand 0 "register_operand" "=d")
2118: (call (match_operand:SI 1 "general_operand" "g")
1.1.1.2 ! root 2119: (match_operand:SI 2 "immediate_operand" "i")))
! 2120: (use (match_operand:SI 3 "address_operand" "p"))
! 2121: (clobber (match_scratch:SI 4 "=&d"))]
1.1 root 2122: ""
1.1.1.2 ! root 2123: "* return i960_output_call_insn (operands[1], operands[2], operands[3],
! 2124: operands[4], insn);"
1.1 root 2125: [(set_attr "type" "call")])
2126:
2127: (define_insn "return"
2128: [(return)]
2129: ""
2130: "* return i960_output_ret_insn (insn);"
2131: [(set_attr "type" "branch")])
2132:
2133: (define_insn "nop"
2134: [(const_int 0)]
2135: ""
2136: "")
2137:
2138: ;; Various peephole optimizations for multiple-word moves, loads, and stores.
2139: ;; Multiple register moves.
2140:
2141: ;; Matched 5/28/91
2142: (define_peephole
2143: [(set (match_operand:SI 0 "register_operand" "=r")
2144: (match_operand:SI 1 "register_operand" "r"))
2145: (set (match_operand:SI 2 "register_operand" "=r")
2146: (match_operand:SI 3 "register_operand" "r"))
2147: (set (match_operand:SI 4 "register_operand" "=r")
2148: (match_operand:SI 5 "register_operand" "r"))
2149: (set (match_operand:SI 6 "register_operand" "=r")
2150: (match_operand:SI 7 "register_operand" "r"))]
2151: "((REGNO (operands[0]) & 3) == 0)
2152: && ((REGNO (operands[1]) & 3) == 0)
2153: && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2154: && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2155: && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2156: && (REGNO (operands[1]) + 2 == REGNO (operands[5]))
2157: && (REGNO (operands[0]) + 3 == REGNO (operands[6]))
2158: && (REGNO (operands[1]) + 3 == REGNO (operands[7]))"
2159: "movq %1,%0")
2160:
2161: ;; Matched 4/17/92
2162: (define_peephole
2163: [(set (match_operand:DI 0 "register_operand" "=r")
2164: (match_operand:DI 1 "register_operand" "r"))
2165: (set (match_operand:DI 2 "register_operand" "=r")
2166: (match_operand:DI 3 "register_operand" "r"))]
2167: "((REGNO (operands[0]) & 3) == 0)
2168: && ((REGNO (operands[1]) & 3) == 0)
2169: && (REGNO (operands[0]) + 2 == REGNO (operands[2]))
2170: && (REGNO (operands[1]) + 2 == REGNO (operands[3]))"
2171: "movq %1,%0")
2172:
2173: ;; Matched 4/17/92
2174: (define_peephole
2175: [(set (match_operand:DI 0 "register_operand" "=r")
2176: (match_operand:DI 1 "register_operand" "r"))
2177: (set (match_operand:SI 2 "register_operand" "=r")
2178: (match_operand:SI 3 "register_operand" "r"))
2179: (set (match_operand:SI 4 "register_operand" "=r")
2180: (match_operand:SI 5 "register_operand" "r"))]
2181: "((REGNO (operands[0]) & 3) == 0)
2182: && ((REGNO (operands[1]) & 3) == 0)
2183: && (REGNO (operands[0]) + 2 == REGNO (operands[2]))
2184: && (REGNO (operands[1]) + 2 == REGNO (operands[3]))
2185: && (REGNO (operands[0]) + 3 == REGNO (operands[4]))
2186: && (REGNO (operands[1]) + 3 == REGNO (operands[5]))"
2187: "movq %1,%0")
2188:
2189: ;; Matched 4/17/92
2190: (define_peephole
2191: [(set (match_operand:SI 0 "register_operand" "=r")
2192: (match_operand:SI 1 "register_operand" "r"))
2193: (set (match_operand:SI 2 "register_operand" "=r")
2194: (match_operand:SI 3 "register_operand" "r"))
2195: (set (match_operand:DI 4 "register_operand" "=r")
2196: (match_operand:DI 5 "register_operand" "r"))]
2197: "((REGNO (operands[0]) & 3) == 0)
2198: && ((REGNO (operands[1]) & 3) == 0)
2199: && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2200: && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2201: && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2202: && (REGNO (operands[1]) + 2 == REGNO (operands[5]))"
2203: "movq %1,%0")
2204:
2205: ;; Matched 4/17/92
2206: (define_peephole
2207: [(set (match_operand:DI 0 "register_operand" "=r")
2208: (match_operand:DI 1 "register_operand" "r"))
2209: (set (match_operand:SI 2 "register_operand" "=r")
2210: (match_operand:SI 3 "register_operand" "r"))]
2211: "((REGNO (operands[0]) & 3) == 0)
2212: && ((REGNO (operands[1]) & 3) == 0)
2213: && (REGNO (operands[0]) + 2 == REGNO (operands[2]))
2214: && (REGNO (operands[1]) + 2 == REGNO (operands[3]))"
2215: "movt %1,%0")
2216:
2217: ;; Matched 5/28/91
2218: (define_peephole
2219: [(set (match_operand:SI 0 "register_operand" "=r")
2220: (match_operand:SI 1 "register_operand" "r"))
2221: (set (match_operand:SI 2 "register_operand" "=r")
2222: (match_operand:SI 3 "register_operand" "r"))
2223: (set (match_operand:SI 4 "register_operand" "=r")
2224: (match_operand:SI 5 "register_operand" "r"))]
2225: "((REGNO (operands[0]) & 3) == 0)
2226: && ((REGNO (operands[1]) & 3) == 0)
2227: && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2228: && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2229: && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2230: && (REGNO (operands[1]) + 2 == REGNO (operands[5]))"
2231: "movt %1,%0")
2232:
2233: ;; Matched 5/28/91
2234: (define_peephole
2235: [(set (match_operand:SI 0 "register_operand" "=r")
2236: (match_operand:SI 1 "register_operand" "r"))
2237: (set (match_operand:SI 2 "register_operand" "=r")
2238: (match_operand:SI 3 "register_operand" "r"))]
2239: "((REGNO (operands[0]) & 1) == 0)
2240: && ((REGNO (operands[1]) & 1) == 0)
2241: && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2242: && (REGNO (operands[1]) + 1 == REGNO (operands[3]))"
2243: "movl %1,%0")
2244:
2245: ; Multiple register loads.
2246:
2247: ;; Matched 6/15/91
2248: (define_peephole
2249: [(set (match_operand:SI 0 "register_operand" "=r")
2250: (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
2251: (match_operand:SI 2 "immediate_operand" "n"))))
2252: (set (match_operand:SI 3 "register_operand" "=r")
2253: (mem:SI (plus:SI (match_dup 1)
2254: (match_operand:SI 4 "immediate_operand" "n"))))
2255: (set (match_operand:SI 5 "register_operand" "=r")
2256: (mem:SI (plus:SI (match_dup 1)
2257: (match_operand:SI 6 "immediate_operand" "n"))))
2258: (set (match_operand:SI 7 "register_operand" "=r")
2259: (mem:SI (plus:SI (match_dup 1)
2260: (match_operand:SI 8 "immediate_operand" "n"))))]
2261: "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
2262: && (REGNO (operands[1]) != REGNO (operands[0]))
2263: && (REGNO (operands[0]) + 1 == REGNO (operands[3]))
2264: && (REGNO (operands[1]) != REGNO (operands[3]))
2265: && (REGNO (operands[0]) + 2 == REGNO (operands[5]))
2266: && (REGNO (operands[1]) != REGNO (operands[5]))
2267: && (REGNO (operands[0]) + 3 == REGNO (operands[7]))
2268: && (INTVAL (operands[2]) + 4 == INTVAL (operands[4]))
2269: && (INTVAL (operands[2]) + 8 == INTVAL (operands[6]))
2270: && (INTVAL (operands[2]) + 12 == INTVAL (operands[8])))"
2271: "ldq %2(%1),%0")
2272:
2273: ;; Matched 5/28/91
2274: (define_peephole
2275: [(set (match_operand:DF 0 "register_operand" "=d")
2276: (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d")
2277: (match_operand:SI 2 "immediate_operand" "n"))))
2278: (set (match_operand:DF 3 "register_operand" "=d")
2279: (mem:DF (plus:SI (match_dup 1)
2280: (match_operand:SI 4 "immediate_operand" "n"))))]
2281: "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
2282: && (REGNO (operands[1]) != REGNO (operands[0]))
2283: && (REGNO (operands[0]) + 2 == REGNO (operands[3]))
2284: && (REGNO (operands[1]) != REGNO (operands[3]))
2285: && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))"
2286: "ldq %2(%1),%0")
2287:
2288: ;; Matched 1/24/92
2289: (define_peephole
2290: [(set (match_operand:DI 0 "register_operand" "=d")
2291: (mem:DI (plus:SI (match_operand:SI 1 "register_operand" "d")
2292: (match_operand:SI 2 "immediate_operand" "n"))))
2293: (set (match_operand:DI 3 "register_operand" "=d")
2294: (mem:DI (plus:SI (match_dup 1)
2295: (match_operand:SI 4 "immediate_operand" "n"))))]
2296: "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
2297: && (REGNO (operands[1]) != REGNO (operands[0]))
2298: && (REGNO (operands[0]) + 2 == REGNO (operands[3]))
2299: && (REGNO (operands[1]) != REGNO (operands[3]))
2300: && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))"
2301: "ldq %2(%1),%0")
2302:
2303: ;; Matched 4/17/92
2304: (define_peephole
2305: [(set (match_operand:SI 0 "register_operand" "=d")
2306: (mem:SI (match_operand:SI 1 "register_operand" "d")))
2307: (set (match_operand:SI 2 "register_operand" "=d")
2308: (mem:SI (plus:SI (match_dup 1)
2309: (match_operand:SI 3 "immediate_operand" "n"))))
2310: (set (match_operand:SI 4 "register_operand" "=d")
2311: (mem:SI (plus:SI (match_dup 1)
2312: (match_operand:SI 5 "immediate_operand" "n"))))
2313: (set (match_operand:SI 6 "register_operand" "=d")
2314: (mem:SI (plus:SI (match_dup 1)
2315: (match_operand:SI 7 "immediate_operand" "n"))))]
2316: "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0)
2317: && (REGNO (operands[1]) != REGNO (operands[0]))
2318: && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2319: && (REGNO (operands[1]) != REGNO (operands[2]))
2320: && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2321: && (REGNO (operands[1]) != REGNO (operands[4]))
2322: && (REGNO (operands[0]) + 3 == REGNO (operands[6]))
2323: && (INTVAL (operands[3]) == 4)
2324: && (INTVAL (operands[5]) == 8)
2325: && (INTVAL (operands[7]) == 12))"
2326: "ldq (%1),%0")
2327:
2328: ;; Matched 5/28/91
2329: (define_peephole
2330: [(set (match_operand:SI 0 "register_operand" "=d")
2331: (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d")
2332: (match_operand:SI 2 "immediate_operand" "n"))))
2333: (set (match_operand:SI 3 "register_operand" "=d")
2334: (mem:SI (plus:SI (match_dup 1)
2335: (match_operand:SI 4 "immediate_operand" "n"))))
2336: (set (match_operand:SI 5 "register_operand" "=d")
2337: (mem:SI (plus:SI (match_dup 1)
2338: (match_operand:SI 6 "immediate_operand" "n"))))]
2339: "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0)
2340: && (REGNO (operands[1]) != REGNO (operands[0]))
2341: && (REGNO (operands[0]) + 1 == REGNO (operands[3]))
2342: && (REGNO (operands[1]) != REGNO (operands[3]))
2343: && (REGNO (operands[0]) + 2 == REGNO (operands[5]))
2344: && (INTVAL (operands[2]) + 4 == INTVAL (operands[4]))
2345: && (INTVAL (operands[2]) + 8 == INTVAL (operands[6])))"
2346: "ldt %2(%1),%0")
2347:
2348: ;; Matched 6/15/91
2349: (define_peephole
2350: [(set (match_operand:SI 0 "register_operand" "=d")
2351: (mem:SI (match_operand:SI 1 "register_operand" "d")))
2352: (set (match_operand:SI 2 "register_operand" "=d")
2353: (mem:SI (plus:SI (match_dup 1)
2354: (match_operand:SI 3 "immediate_operand" "n"))))
2355: (set (match_operand:SI 4 "register_operand" "=d")
2356: (mem:SI (plus:SI (match_dup 1)
2357: (match_operand:SI 5 "immediate_operand" "n"))))]
2358: "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0)
2359: && (REGNO (operands[1]) != REGNO (operands[0]))
2360: && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2361: && (REGNO (operands[1]) != REGNO (operands[2]))
2362: && (REGNO (operands[0]) + 2 == REGNO (operands[4]))
2363: && (INTVAL (operands[3]) == 4)
2364: && (INTVAL (operands[5]) == 8))"
2365: "ldt (%1),%0")
2366:
2367: ;; Matched 5/28/91
2368: (define_peephole
2369: [(set (match_operand:SI 0 "register_operand" "=d")
2370: (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d")
2371: (match_operand:SI 2 "immediate_operand" "n"))))
2372: (set (match_operand:SI 3 "register_operand" "=d")
2373: (mem:SI (plus:SI (match_dup 1)
2374: (match_operand:SI 4 "immediate_operand" "n"))))]
2375: "(i960_si_di (operands[1], operands[2]) && ((REGNO (operands[0]) & 1) == 0)
2376: && (REGNO (operands[1]) != REGNO (operands[0]))
2377: && (REGNO (operands[0]) + 1 == REGNO (operands[3]))
2378: && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])))"
2379: "ldl %2(%1),%0")
2380:
2381: ;; Matched 5/28/91
2382: (define_peephole
2383: [(set (match_operand:SI 0 "register_operand" "=d")
2384: (mem:SI (match_operand:SI 1 "register_operand" "d")))
2385: (set (match_operand:SI 2 "register_operand" "=d")
2386: (mem:SI (plus:SI (match_dup 1)
2387: (match_operand:SI 3 "immediate_operand" "n"))))]
2388: "(i960_si_di (operands[1], 0) && ((REGNO (operands[0]) & 1) == 0)
2389: && (REGNO (operands[1]) != REGNO (operands[0]))
2390: && (REGNO (operands[0]) + 1 == REGNO (operands[2]))
2391: && (INTVAL (operands[3]) == 4))"
2392: "ldl (%1),%0")
2393:
2394: ; Multiple register stores.
2395:
2396: ;; Matched 5/28/91
2397: (define_peephole
2398: [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d")
2399: (match_operand:SI 1 "immediate_operand" "n")))
2400: (match_operand:SI 2 "register_operand" "d"))
2401: (set (mem:SI (plus:SI (match_dup 0)
2402: (match_operand:SI 3 "immediate_operand" "n")))
2403: (match_operand:SI 4 "register_operand" "d"))
2404: (set (mem:SI (plus:SI (match_dup 0)
2405: (match_operand:SI 5 "immediate_operand" "n")))
2406: (match_operand:SI 6 "register_operand" "d"))
2407: (set (mem:SI (plus:SI (match_dup 0)
2408: (match_operand:SI 7 "immediate_operand" "n")))
2409: (match_operand:SI 8 "register_operand" "d"))]
2410: "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
2411: && (REGNO (operands[2]) + 1 == REGNO (operands[4]))
2412: && (REGNO (operands[2]) + 2 == REGNO (operands[6]))
2413: && (REGNO (operands[2]) + 3 == REGNO (operands[8]))
2414: && (INTVAL (operands[1]) + 4 == INTVAL (operands[3]))
2415: && (INTVAL (operands[1]) + 8 == INTVAL (operands[5]))
2416: && (INTVAL (operands[1]) + 12 == INTVAL (operands[7])))"
2417: "stq %2,%1(%0)")
2418:
2419: ;; Matched 6/16/91
2420: (define_peephole
2421: [(set (mem:DF (plus:SI (match_operand:SI 0 "register_operand" "d")
2422: (match_operand:SI 1 "immediate_operand" "n")))
2423: (match_operand:DF 2 "register_operand" "d"))
2424: (set (mem:DF (plus:SI (match_dup 0)
2425: (match_operand:SI 3 "immediate_operand" "n")))
2426: (match_operand:DF 4 "register_operand" "d"))]
2427: "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
2428: && (REGNO (operands[2]) + 2 == REGNO (operands[4]))
2429: && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))"
2430: "stq %2,%1(%0)")
2431:
2432: ;; Matched 4/17/92
2433: (define_peephole
2434: [(set (mem:DI (plus:SI (match_operand:SI 0 "register_operand" "d")
2435: (match_operand:SI 1 "immediate_operand" "n")))
2436: (match_operand:DI 2 "register_operand" "d"))
2437: (set (mem:DI (plus:SI (match_dup 0)
2438: (match_operand:SI 3 "immediate_operand" "n")))
2439: (match_operand:DI 4 "register_operand" "d"))]
2440: "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
2441: && (REGNO (operands[2]) + 2 == REGNO (operands[4]))
2442: && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))"
2443: "stq %2,%1(%0)")
2444:
2445: ;; Matched 1/23/92
2446: (define_peephole
2447: [(set (mem:SI (match_operand:SI 0 "register_operand" "d"))
2448: (match_operand:SI 1 "register_operand" "d"))
2449: (set (mem:SI (plus:SI (match_dup 0)
2450: (match_operand:SI 2 "immediate_operand" "n")))
2451: (match_operand:SI 3 "register_operand" "d"))
2452: (set (mem:SI (plus:SI (match_dup 0)
2453: (match_operand:SI 4 "immediate_operand" "n")))
2454: (match_operand:SI 5 "register_operand" "d"))
2455: (set (mem:SI (plus:SI (match_dup 0)
2456: (match_operand:SI 6 "immediate_operand" "n")))
2457: (match_operand:SI 7 "register_operand" "d"))]
2458: "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0)
2459: && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2460: && (REGNO (operands[1]) + 2 == REGNO (operands[5]))
2461: && (REGNO (operands[1]) + 3 == REGNO (operands[7]))
2462: && (INTVAL (operands[2]) == 4)
2463: && (INTVAL (operands[4]) == 8)
2464: && (INTVAL (operands[6]) == 12))"
2465: "stq %1,(%0)")
2466:
2467: ;; Matched 5/29/91
2468: (define_peephole
2469: [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d")
2470: (match_operand:SI 1 "immediate_operand" "n")))
2471: (match_operand:SI 2 "register_operand" "d"))
2472: (set (mem:SI (plus:SI (match_dup 0)
2473: (match_operand:SI 3 "immediate_operand" "n")))
2474: (match_operand:SI 4 "register_operand" "d"))
2475: (set (mem:SI (plus:SI (match_dup 0)
2476: (match_operand:SI 5 "immediate_operand" "n")))
2477: (match_operand:SI 6 "register_operand" "d"))]
2478: "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0)
2479: && (REGNO (operands[2]) + 1 == REGNO (operands[4]))
2480: && (REGNO (operands[2]) + 2 == REGNO (operands[6]))
2481: && (INTVAL (operands[1]) + 4 == INTVAL (operands[3]))
2482: && (INTVAL (operands[1]) + 8 == INTVAL (operands[5])))"
2483: "stt %2,%1(%0)")
2484:
2485: ;; Matched 5/29/91
2486: (define_peephole
2487: [(set (mem:SI (match_operand:SI 0 "register_operand" "d"))
2488: (match_operand:SI 1 "register_operand" "d"))
2489: (set (mem:SI (plus:SI (match_dup 0)
2490: (match_operand:SI 2 "immediate_operand" "n")))
2491: (match_operand:SI 3 "register_operand" "d"))
2492: (set (mem:SI (plus:SI (match_dup 0)
2493: (match_operand:SI 4 "immediate_operand" "n")))
2494: (match_operand:SI 5 "register_operand" "d"))]
2495: "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0)
2496: && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2497: && (REGNO (operands[1]) + 2 == REGNO (operands[5]))
2498: && (INTVAL (operands[2]) == 4)
2499: && (INTVAL (operands[4]) == 8))"
2500: "stt %1,(%0)")
2501:
2502: ;; Matched 5/28/91
2503: (define_peephole
2504: [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d")
2505: (match_operand:SI 1 "immediate_operand" "n")))
2506: (match_operand:SI 2 "register_operand" "d"))
2507: (set (mem:SI (plus:SI (match_dup 0)
2508: (match_operand:SI 3 "immediate_operand" "n")))
2509: (match_operand:SI 4 "register_operand" "d"))]
2510: "(i960_si_di (operands[0], operands[1]) && ((REGNO (operands[2]) & 1) == 0)
2511: && (REGNO (operands[2]) + 1 == REGNO (operands[4]))
2512: && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])))"
2513: "stl %2,%1(%0)")
2514:
2515: ;; Matched 5/28/91
2516: (define_peephole
2517: [(set (mem:SI (match_operand:SI 0 "register_operand" "d"))
2518: (match_operand:SI 1 "register_operand" "d"))
2519: (set (mem:SI (plus:SI (match_dup 0)
2520: (match_operand:SI 2 "immediate_operand" "n")))
2521: (match_operand:SI 3 "register_operand" "d"))]
2522: "(i960_si_di (operands[0], 0) && ((REGNO (operands[1]) & 1) == 0)
2523: && (REGNO (operands[1]) + 1 == REGNO (operands[3]))
2524: && (INTVAL (operands[2]) == 4))"
2525: "stl %1,(%0)")
2526:
2527: ;;- Local variables:
2528: ;;- mode:emacs-lisp
2529: ;;- comment-start: ";;- "
2530: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2531: ;;- eval: (modify-syntax-entry ?[ "(]")
2532: ;;- eval: (modify-syntax-entry ?] ")[")
2533: ;;- eval: (modify-syntax-entry ?{ "(}")
2534: ;;- eval: (modify-syntax-entry ?} "){")
2535: ;;- End:
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