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1.1 root 1: /* Definitions of target machine for GNU compiler, for Intel 80960
1.1.1.2 root 2: Copyright (C) 1992, 1993 Free Software Foundation, Inc.
1.1 root 3: Contributed by Steven McGeady, Intel Corp.
4: Additional Work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson
5: Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support.
6:
7: This file is part of GNU CC.
8:
9: GNU CC is free software; you can redistribute it and/or modify
10: it under the terms of the GNU General Public License as published by
11: the Free Software Foundation; either version 2, or (at your option)
12: any later version.
13:
14: GNU CC is distributed in the hope that it will be useful,
15: but WITHOUT ANY WARRANTY; without even the implied warranty of
16: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17: GNU General Public License for more details.
18:
19: You should have received a copy of the GNU General Public License
20: along with GNU CC; see the file COPYING. If not, write to
21: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
22:
23: /* Note that some other tm.h files may include this one and then override
24: many of the definitions that relate to assembler syntax. */
25:
26: /* Names to predefine in the preprocessor for this target machine. */
1.1.1.2 root 27: #define CPP_PREDEFINES "-Di960 -Di80960 -DI960 -DI80960 -Acpu(i960) -Amachine(i960)"
1.1 root 28:
29: /* Name to predefine in the preprocessor for processor variations. */
30: #define CPP_SPEC "%{mic*:-D__i960\
31: %{mka:-D__i960KA}%{mkb:-D__i960KB}\
32: %{msa:-D__i960SA}%{msb:-D__i960SB}\
33: %{mmc:-D__i960MC}\
34: %{mca:-D__i960CA}%{mcc:-D__i960CC}\
35: %{mcf:-D__i960CF}}\
36: %{mka:-D__i960KA__ -D__i960_KA__}\
37: %{mkb:-D__i960KB__ -D__i960_KB__}\
38: %{msa:-D__i960SA__ -D__i960_SA__}\
39: %{msb:-D__i960SB__ -D__i960_SB__}\
40: %{mmc:-D__i960MC__ -D__i960_MC__}\
41: %{mca:-D__i960CA__ -D__i960_CA__}\
42: %{mcc:-D__i960CC__ -D__i960_CC__}\
43: %{mcf:-D__i960CF__ -D__i960_CF__}\
44: %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:\
45: %{!mcc:%{!mcf:-D__i960_KB -D__i960KB__ %{mic*:-D__i960KB}}}}}}}}}"
46:
47: /* -mic* options make characters signed by default. */
1.1.1.3 ! root 48: /* Use #if rather than ?: because MIPS C compiler rejects ?: in
! 49: initializers. */
! 50: #if DEFAULT_SIGNED_CHAR
! 51: #define SIGNED_CHAR_SPEC "%{funsigned-char:-D__CHAR_UNSIGNED__}"
! 52: #else
! 53: #define SIGNED_CHAR_SPEC "%{!fsigned-char:%{!mic*:-D__CHAR_UNSIGNED__}}"
! 54: #endif
1.1 root 55:
56: /* Specs for the compiler, to handle processor variations. */
57: #define CC1_SPEC \
58: "%{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-mkb}}}}}}}}\
59: %{mbout:%{g*:-gstabs}}\
60: %{mcoff:%{g*:-gcoff}}\
61: %{!mbout:%{!mcoff:%{g*:-gstabs}}}"
62:
63: /* Specs for the assembler, to handle processor variations.
64: For compatibility with Intel's gnu960 tool chain, pass -A options to
65: the assembler. */
66: #define ASM_SPEC \
67: "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
68: %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
69: %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\
1.1.1.2 root 70: %{mlink-relax:-linkrelax}"
1.1 root 71:
72: /* Specs for the linker, to handle processor variations.
73: For compatibility with Intel's gnu960 tool chain, pass -F and -A options
74: to the linker. */
75: #define LINK_SPEC \
76: "%{mka:-AKA}%{mkb:-AKB}%{msa:-ASA}%{msb:-ASB}\
77: %{mmc:-AMC}%{mca:-ACA}%{mcc:-ACC}%{mcf:-ACF}\
78: %{!mka:%{!mkb:%{!msa:%{!msb:%{!mmc:%{!mca:%{!mcc:%{!mcf:-AKB}}}}}}}}\
79: %{mbout:-Fbout}%{mcoff:-Fcoff}\
80: %{mlink-relax:-relax}"
81:
82: /* Specs for the libraries to link with, to handle processor variations.
83: Compatible with Intel's gnu960 tool chain. */
84: #define LIB_SPEC "%{!nostdlib:-lcg %{p:-lprof}%{pg:-lgprof}\
85: %{mka:-lfpg}%{msa:-lfpg}%{mca:-lfpg}%{mcf:-lfpg} -lgnu}"
86:
1.1.1.3 ! root 87: /* Show we can debug even without a frame pointer. */
! 88: #define CAN_DEBUG_WITHOUT_FP
! 89:
! 90: /* Do leaf procedure and tail call optimizations for -O2 and higher. */
1.1 root 91: #define OPTIMIZATION_OPTIONS(LEVEL) \
92: { \
93: if ((LEVEL) >= 2) \
94: { \
95: target_flags |= TARGET_FLAG_LEAFPROC; \
96: target_flags |= TARGET_FLAG_TAILCALL; \
97: } \
98: }
99:
100: /* Print subsidiary information on the compiler version in use. */
101: #define TARGET_VERSION fprintf (stderr," (intel 80960)");
102:
103: /* Generate DBX debugging information. */
104: #define DBX_DEBUGGING_INFO
105:
106: /* Generate SDB style debugging information. */
107: #define SDB_DEBUGGING_INFO
108:
109: /* Generate DBX_DEBUGGING_INFO by default. */
110: #define PREFERRED_DEBUGGING_TYPE DBX_DEBUG
111:
1.1.1.3 ! root 112: /* Redefine this to print in hex and adjust values like GNU960. The extra
! 113: bit is used to handle the type long double. Gcc does not support long
! 114: double in sdb output, but we do support the non-standard format. */
! 115: #define PUT_SDB_TYPE(A) \
! 116: fprintf (asm_out_file, "\t.type\t0x%x;", (A & 0xf) + 2 * (A & ~0xf))
1.1 root 117:
118: /* Run-time compilation parameters selecting different hardware subsets. */
119:
120: /* 960 architecture with floating-point. */
121: #define TARGET_FLAG_NUMERICS 0x01
122: #define TARGET_NUMERICS (target_flags & TARGET_FLAG_NUMERICS)
123:
124: /* 960 architecture with memory management. */
125: /* ??? Not used currently. */
126: #define TARGET_FLAG_PROTECTED 0x02
127: #define TARGET_PROTECTED (target_flags & TARGET_FLAG_PROTECTED)
128:
129: /* The following three are mainly used to provide a little sanity checking
130: against the -mARCH flags given. */
131:
132: /* Nonzero if we should generate code for the KA and similar processors.
133: No FPU, no microcode instructions. */
134: #define TARGET_FLAG_K_SERIES 0x04
135: #define TARGET_K_SERIES (target_flags & TARGET_FLAG_K_SERIES)
136:
137: /* Nonzero if we should generate code for the MC processor.
138: Not really different from KB for our purposes. */
139: #define TARGET_FLAG_MC 0x08
140: #define TARGET_MC (target_flags & TARGET_FLAG_MC)
141:
142: /* Nonzero if we should generate code for the CA processor.
143: Enables different optimization strategies. */
144: #define TARGET_FLAG_C_SERIES 0x10
145: #define TARGET_C_SERIES (target_flags & TARGET_FLAG_C_SERIES)
146:
147: /* Nonzero if we should generate leaf-procedures when we find them.
148: You may not want to do this because leaf-proc entries are
149: slower when not entered via BAL - this would be true when
150: a linker not supporting the optimization is used. */
151: #define TARGET_FLAG_LEAFPROC 0x20
152: #define TARGET_LEAFPROC (target_flags & TARGET_FLAG_LEAFPROC)
153:
154: /* Nonzero if we should perform tail-call optimizations when we find them.
155: You may not want to do this because the detection of cases where
156: this is not valid is not totally complete. */
157: #define TARGET_FLAG_TAILCALL 0x40
158: #define TARGET_TAILCALL (target_flags & TARGET_FLAG_TAILCALL)
159:
160: /* Nonzero if use of a complex addressing mode is a win on this implementation.
161: Complex addressing modes are probably not worthwhile on the K-series,
162: but they definitely are on the C-series. */
163: #define TARGET_FLAG_COMPLEX_ADDR 0x80
164: #define TARGET_COMPLEX_ADDR (target_flags & TARGET_FLAG_COMPLEX_ADDR)
165:
166: /* Align code to 8 byte boundaries for faster fetching. */
167: #define TARGET_FLAG_CODE_ALIGN 0x100
168: #define TARGET_CODE_ALIGN (target_flags & TARGET_FLAG_CODE_ALIGN)
169:
170: /* Append branch prediction suffixes to branch opcodes. */
171: /* ??? Not used currently. */
172: #define TARGET_FLAG_BRANCH_PREDICT 0x200
173: #define TARGET_BRANCH_PREDICT (target_flags & TARGET_FLAG_BRANCH_PREDICT)
174:
175: /* Forces prototype and return promotions. */
176: /* ??? This does not work. */
177: #define TARGET_FLAG_CLEAN_LINKAGE 0x400
178: #define TARGET_CLEAN_LINKAGE (target_flags & TARGET_FLAG_CLEAN_LINKAGE)
179:
180: /* For compatibility with iC960 v3.0. */
181: #define TARGET_FLAG_IC_COMPAT3_0 0x800
182: #define TARGET_IC_COMPAT3_0 (target_flags & TARGET_FLAG_IC_COMPAT3_0)
183:
184: /* For compatibility with iC960 v2.0. */
185: #define TARGET_FLAG_IC_COMPAT2_0 0x1000
186: #define TARGET_IC_COMPAT2_0 (target_flags & TARGET_FLAG_IC_COMPAT2_0)
187:
188: /* If no unaligned accesses are to be permitted. */
189: #define TARGET_FLAG_STRICT_ALIGN 0x2000
190: #define TARGET_STRICT_ALIGN (target_flags & TARGET_FLAG_STRICT_ALIGN)
191:
192: /* For compatibility with iC960 assembler. */
193: #define TARGET_FLAG_ASM_COMPAT 0x4000
194: #define TARGET_ASM_COMPAT (target_flags & TARGET_FLAG_ASM_COMPAT)
195:
196: /* For compatibility with the gcc960 v1.2 compiler. Use the old structure
197: alignment rules. Also, turns on STRICT_ALIGNMENT. */
198: #define TARGET_FLAG_OLD_ALIGN 0x8000
199: #define TARGET_OLD_ALIGN (target_flags & TARGET_FLAG_OLD_ALIGN)
200:
201: extern int target_flags;
202:
203: /* Macro to define tables used to set the flags.
204: This is a list in braces of pairs in braces,
205: each pair being { "NAME", VALUE }
206: where VALUE is the bits to set or minus the bits to clear.
207: An empty string NAME is used to identify the default VALUE. */
208:
209: /* ??? Not all ten of these architecture variations actually exist, but I
210: am not sure which are real and which aren't. */
211:
212: #define TARGET_SWITCHES \
213: { {"sa", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
214: {"sb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
215: TARGET_FLAG_COMPLEX_ADDR)},\
216: /* {"sc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
217: TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
218: {"ka", (TARGET_FLAG_K_SERIES|TARGET_FLAG_COMPLEX_ADDR)},\
219: {"kb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_K_SERIES| \
220: TARGET_FLAG_COMPLEX_ADDR)},\
221: /* {"kc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
222: TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},*/ \
223: {"mc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
224: TARGET_FLAG_MC|TARGET_FLAG_COMPLEX_ADDR)},\
225: {"ca", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
226: TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
227: /* {"cb", (TARGET_FLAG_NUMERICS|TARGET_FLAG_C_SERIES|\
228: TARGET_FLAG_BRANCH_PREDICT|TARGET_FLAG_CODE_ALIGN)},\
229: {"cc", (TARGET_FLAG_NUMERICS|TARGET_FLAG_PROTECTED|\
230: TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
231: TARGET_FLAG_CODE_ALIGN)}, */ \
232: {"cf", (TARGET_FLAG_C_SERIES|TARGET_FLAG_BRANCH_PREDICT|\
233: TARGET_FLAG_CODE_ALIGN|TARGET_FLAG_COMPLEX_ADDR)},\
234: {"numerics", (TARGET_FLAG_NUMERICS)}, \
235: {"soft-float", -(TARGET_FLAG_NUMERICS)}, \
236: {"leaf-procedures", TARGET_FLAG_LEAFPROC}, \
237: {"no-leaf-procedures",-(TARGET_FLAG_LEAFPROC)}, \
238: {"tail-call",TARGET_FLAG_TAILCALL}, \
239: {"no-tail-call",-(TARGET_FLAG_TAILCALL)}, \
240: {"complex-addr",TARGET_FLAG_COMPLEX_ADDR}, \
241: {"no-complex-addr",-(TARGET_FLAG_COMPLEX_ADDR)}, \
242: {"code-align",TARGET_FLAG_CODE_ALIGN}, \
243: {"no-code-align",-(TARGET_FLAG_CODE_ALIGN)}, \
244: {"clean-linkage", (TARGET_FLAG_CLEAN_LINKAGE)}, \
245: {"no-clean-linkage", -(TARGET_FLAG_CLEAN_LINKAGE)}, \
246: {"ic-compat", TARGET_FLAG_IC_COMPAT2_0}, \
247: {"ic2.0-compat", TARGET_FLAG_IC_COMPAT2_0}, \
248: {"ic3.0-compat", TARGET_FLAG_IC_COMPAT3_0}, \
249: {"asm-compat",TARGET_FLAG_ASM_COMPAT}, \
250: {"intel-asm",TARGET_FLAG_ASM_COMPAT}, \
251: {"strict-align", TARGET_FLAG_STRICT_ALIGN}, \
252: {"no-strict-align", -(TARGET_FLAG_STRICT_ALIGN)}, \
253: {"old-align", TARGET_FLAG_OLD_ALIGN}, \
254: {"no-old-align", -(TARGET_FLAG_OLD_ALIGN)}, \
255: {"link-relax", 0}, \
256: {"no-link-relax", 0}, \
257: { "", TARGET_DEFAULT}}
258:
259: /* Override conflicting target switch options.
260: Doesn't actually detect if more than one -mARCH option is given, but
261: does handle the case of two blatantly conflicting -mARCH options. */
262: #define OVERRIDE_OPTIONS \
263: { \
264: if (TARGET_K_SERIES && TARGET_C_SERIES) \
265: { \
266: warning ("conflicting architectures defined - using C series", 0); \
267: target_flags &= ~TARGET_FLAG_K_SERIES; \
268: } \
269: if (TARGET_K_SERIES && TARGET_MC) \
270: { \
271: warning ("conflicting architectures defined - using K series", 0); \
272: target_flags &= ~TARGET_FLAG_MC; \
273: } \
274: if (TARGET_C_SERIES && TARGET_MC) \
275: { \
276: warning ("conflicting architectures defined - using C series", 0);\
277: target_flags &= ~TARGET_FLAG_MC; \
278: } \
279: if (TARGET_IC_COMPAT3_0) \
280: { \
281: flag_short_enums = 1; \
282: flag_signed_char = 1; \
283: target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
284: if (TARGET_IC_COMPAT2_0) \
285: { \
286: warning ("iC2.0 and iC3.0 are incompatible - using iC3.0", 0); \
287: target_flags &= ~TARGET_FLAG_IC_COMPAT2_0; \
288: } \
289: } \
290: if (TARGET_IC_COMPAT2_0) \
291: { \
292: flag_signed_char = 1; \
293: target_flags |= TARGET_FLAG_CLEAN_LINKAGE; \
294: } \
295: i960_initialize (); \
296: }
297:
298: /* Don't enable anything by default. The user is expected to supply a -mARCH
299: option. If none is given, then -mkb is added by CC1_SPEC. */
300: #define TARGET_DEFAULT 0
301:
302: /* Target machine storage layout. */
303:
304: /* Define this if most significant bit is lowest numbered
305: in instructions that operate on numbered bit-fields. */
306: #define BITS_BIG_ENDIAN 0
307:
308: /* Define this if most significant byte of a word is the lowest numbered.
309: The i960 case be either big endian or little endian. We only support
310: little endian, which is the most common. */
311: #define BYTES_BIG_ENDIAN 0
312:
313: /* Define this if most significant word of a multiword number is lowest
314: numbered. */
315: #define WORDS_BIG_ENDIAN 0
316:
317: /* Number of bits in an addressable storage unit. */
318: #define BITS_PER_UNIT 8
319:
320: /* Bitfields cannot cross word boundaries. */
321: #define BITFIELD_NBYTES_LIMITED 1
322:
323: /* Width in bits of a "word", which is the contents of a machine register.
324: Note that this is not necessarily the width of data type `int';
325: if using 16-bit ints on a 68000, this would still be 32.
326: But on a machine with 16-bit registers, this would be 16. */
327: #define BITS_PER_WORD 32
328:
329: /* Width of a word, in units (bytes). */
330: #define UNITS_PER_WORD 4
331:
332: /* Width in bits of a pointer. See also the macro `Pmode' defined below. */
333: #define POINTER_SIZE 32
334:
335: /* Width in bits of a long double. Identical to double for now. */
336: #define LONG_DOUBLE_TYPE_SIZE 64
337:
338: /* Allocation boundary (in *bits*) for storing pointers in memory. */
339: #define POINTER_BOUNDARY 32
340:
341: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
342: #define PARM_BOUNDARY 32
343:
344: /* Boundary (in *bits*) on which stack pointer should be aligned. */
345: #define STACK_BOUNDARY 128
346:
347: /* Allocation boundary (in *bits*) for the code of a function. */
348: #define FUNCTION_BOUNDARY 128
349:
350: /* Alignment of field after `int : 0' in a structure. */
351: #define EMPTY_FIELD_BOUNDARY 32
352:
353: /* This makes zero-length anonymous fields lay the next field
354: at a word boundary. It also makes the whole struct have
355: at least word alignment if there are any bitfields at all. */
356: #define PCC_BITFIELD_TYPE_MATTERS 1
357:
358: /* Every structure's size must be a multiple of this. */
359: #define STRUCTURE_SIZE_BOUNDARY 8
360:
361: /* No data type wants to be aligned rounder than this.
362: Extended precision floats gets 4-word alignment. */
363: #define BIGGEST_ALIGNMENT 128
364:
365: /* Define this if move instructions will actually fail to work
366: when given unaligned data.
367: 80960 will work even with unaligned data, but it is slow. */
368: #define STRICT_ALIGNMENT TARGET_OLD_ALIGN
369:
370: /* Specify alignment for string literals (which might be higher than the
371: base type's minimal alignment requirement. This allows strings to be
372: aligned on word boundaries, and optimizes calls to the str* and mem*
373: library functions. */
374: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
375: (TREE_CODE (EXP) == STRING_CST \
376: && i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) > (ALIGN) \
377: ? i960_object_bytes_bitalign (int_size_in_bytes (TREE_TYPE (EXP))) \
378: : (ALIGN))
379:
380: /* Macros to determine size of aggregates (structures and unions
381: in C). Normally, these may be defined to simply return the maximum
382: alignment and simple rounded-up size, but on some machines (like
383: the i960), the total size of a structure is based on a non-trivial
384: rounding method. */
385:
386: #define ROUND_TYPE_ALIGN(TYPE, COMPUTED, SPECIFIED) \
387: ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \
388: ? i960_round_align ((SPECIFIED), TYPE_SIZE (TYPE)) \
389: : MAX ((COMPUTED), (SPECIFIED)))
390:
391: #define ROUND_TYPE_SIZE(TYPE, SIZE, ALIGN) \
392: ((!TARGET_OLD_ALIGN && TREE_CODE (TYPE) == RECORD_TYPE) \
393: ? (tree) i960_round_size (SIZE) \
394: : round_up ((SIZE), (ALIGN)))
395:
396: /* Standard register usage. */
397:
398: /* Number of actual hardware registers.
399: The hardware registers are assigned numbers for the compiler
400: from 0 to just below FIRST_PSEUDO_REGISTER.
401: All registers that the compiler knows about must be given numbers,
402: even those that are not normally considered general registers.
403:
404: Registers 0-15 are the global registers (g0-g15).
405: Registers 16-31 are the local registers (r0-r15).
406: Register 32-35 are the fp registers (fp0-fp3).
407: Register 36 is the condition code register.
408: Register 37 is unused. */
409:
410: #define FIRST_PSEUDO_REGISTER 38
411:
412: /* 1 for registers that have pervasive standard uses and are not available
413: for the register allocator. On 80960, this includes the frame pointer
414: (g15), the previous FP (r0), the stack pointer (r1), the return
415: instruction pointer (r2), and the argument pointer (g14). */
416: #define FIXED_REGISTERS \
417: {0, 0, 0, 0, 0, 0, 0, 0, \
418: 0, 0, 0, 0, 0, 0, 1, 1, \
419: 1, 1, 1, 0, 0, 0, 0, 0, \
420: 0, 0, 0, 0, 0, 0, 0, 0, \
421: 0, 0, 0, 0, 1, 1}
422:
423: /* 1 for registers not available across function calls.
424: These must include the FIXED_REGISTERS and also any
425: registers that can be used without being saved.
426: The latter must include the registers where values are returned
427: and the register where structure-value addresses are passed.
428: Aside from that, you can include as many other registers as you like. */
429:
430: /* On the 80960, note that:
431: g0..g3 are used for return values,
432: g0..g7 may always be used for parameters,
433: g8..g11 may be used for parameters, but are preserved if they aren't,
434: g12 is always preserved, but otherwise unused,
435: g13 is the struct return ptr if used, or temp, but may be trashed,
436: g14 is the leaf return ptr or the arg block ptr otherwise zero,
437: must be reset to zero before returning if it was used,
438: g15 is the frame pointer,
439: r0 is the previous FP,
440: r1 is the stack pointer,
441: r2 is the return instruction pointer,
442: r3-r15 are always available,
443: r3 is clobbered by calls in functions that use the arg pointer
444: r4-r11 may be clobbered by the mcount call when profiling
445: r4-r15 if otherwise unused may be used for preserving global registers
446: fp0..fp3 are never available. */
447: #define CALL_USED_REGISTERS \
448: {1, 1, 1, 1, 1, 1, 1, 1, \
449: 0, 0, 0, 0, 0, 1, 1, 1, \
450: 1, 1, 1, 0, 0, 0, 0, 0, \
451: 0, 0, 0, 0, 0, 0, 0, 0, \
452: 1, 1, 1, 1, 1, 1}
453:
454: /* If no fp unit, make all of the fp registers fixed so that they can't
455: be used. */
456: #define CONDITIONAL_REGISTER_USAGE \
457: if (! TARGET_NUMERICS) { \
458: fixed_regs[32] = fixed_regs[33] = fixed_regs[34] = fixed_regs[35] = 1;\
459: } \
460:
461: /* Return number of consecutive hard regs needed starting at reg REGNO
462: to hold something of mode MODE.
463: This is ordinarily the length in words of a value of mode MODE
464: but can be less for certain modes in special long registers.
465:
466: On 80960, ordinary registers hold 32 bits worth, but can be ganged
467: together to hold double or extended precision floating point numbers,
468: and the floating point registers hold any size floating point number */
469: #define HARD_REGNO_NREGS(REGNO, MODE) \
470: ((REGNO) < 32 \
471: ? (((MODE) == VOIDmode) \
472: ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) \
473: : ((REGNO) < FIRST_PSEUDO_REGISTER) ? 1 : 0)
474:
475: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
476: On 80960, the cpu registers can hold any mode but the float registers
477: can only hold SFmode, DFmode, or TFmode. */
478: extern unsigned int hard_regno_mode_ok[FIRST_PSEUDO_REGISTER];
479: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
480: ((hard_regno_mode_ok[REGNO] & (1 << (int) (MODE))) != 0)
481:
482: /* Value is 1 if it is a good idea to tie two pseudo registers
483: when one has mode MODE1 and one has mode MODE2.
484: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
485: for any hard reg, then this must be 0 for correct output. */
486:
487: #define MODES_TIEABLE_P(MODE1, MODE2) \
488: ((MODE1) == (MODE2) || GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2))
489:
490: /* Specify the registers used for certain standard purposes.
491: The values of these macros are register numbers. */
492:
493: /* 80960 pc isn't overloaded on a register that the compiler knows about. */
494: /* #define PC_REGNUM */
495:
496: /* Register to use for pushing function arguments. */
497: #define STACK_POINTER_REGNUM 17
498:
499: /* Actual top-of-stack address is same as
500: the contents of the stack pointer register. */
501: #define STACK_POINTER_OFFSET (-current_function_outgoing_args_size)
502:
503: /* Base register for access to local variables of the function. */
504: #define FRAME_POINTER_REGNUM 15
505:
506: /* Value should be nonzero if functions must have frame pointers.
507: Zero means the frame pointer need not be set up (and parms
508: may be accessed via the stack pointer) in functions that seem suitable.
509: This is computed in `reload', in reload1.c. */
1.1.1.2 root 510: /* ??? It isn't clear to me why this is here. Perhaps because of a bug (since
511: fixed) in the definition of INITIAL_FRAME_POINTER_OFFSET which would have
512: caused this to fail. */
1.1 root 513: #define FRAME_POINTER_REQUIRED (! leaf_function_p ())
514:
515: /* C statement to store the difference between the frame pointer
1.1.1.2 root 516: and the stack pointer values immediately after the function prologue.
517:
518: Since the stack grows upward on the i960, this must be a negative number.
519: This includes the 64 byte hardware register save area and the size of
520: the frame. */
1.1 root 521:
522: #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
1.1.1.2 root 523: do { (VAR) = - (64 + compute_frame_size (get_frame_size ())); } while (0)
1.1 root 524:
525: /* Base register for access to arguments of the function. */
526: #define ARG_POINTER_REGNUM 14
527:
528: /* Register in which static-chain is passed to a function.
529: On i960, we use r3. */
530: #define STATIC_CHAIN_REGNUM 19
531:
532: /* Functions which return large structures get the address
533: to place the wanted value at in g13. */
534:
535: #define STRUCT_VALUE_REGNUM 13
536:
537: /* The order in which to allocate registers. */
538:
539: #define REG_ALLOC_ORDER \
540: { 4, 5, 6, 7, 0, 1, 2, 3, 13, /* g4, g5, g6, g7, g0, g1, g2, g3, g13 */ \
541: 20, 21, 22, 23, 24, 25, 26, 27,/* r4, r5, r6, r7, r8, r9, r10, r11 */ \
542: 28, 29, 30, 31, 19, 8, 9, 10, /* r12, r13, r14, r15, r3, g8, g9, g10 */ \
543: 11, 12, /* g11, g12 */ \
544: 32, 33, 34, 35, /* fp0, fp1, fp2, fp3 */ \
545: /* We can't actually allocate these. */ \
546: 16, 17, 18, 14, 15, 36, 37} /* r0, r1, r2, g14, g15, cc */
547:
548: /* Define the classes of registers for register constraints in the
549: machine description. Also define ranges of constants.
550:
551: One of the classes must always be named ALL_REGS and include all hard regs.
552: If there is more than one class, another class must be named NO_REGS
553: and contain no registers.
554:
555: The name GENERAL_REGS must be the name of a class (or an alias for
556: another name such as ALL_REGS). This is the class of registers
557: that is allowed by "g" or "r" in a register constraint.
558: Also, registers outside this class are allocated only when
559: instructions express preferences for them.
560:
561: The classes must be numbered in nondecreasing order; that is,
562: a larger-numbered class must never be contained completely
563: in a smaller-numbered class.
564:
565: For any two classes, it is very desirable that there be another
566: class that represents their union. */
567:
568: /* The 80960 has four kinds of registers, global, local, floating point,
569: and condition code. The cc register is never allocated, so no class
570: needs to be defined for it. */
571:
572: enum reg_class { NO_REGS, GLOBAL_REGS, LOCAL_REGS, LOCAL_OR_GLOBAL_REGS,
573: FP_REGS, ALL_REGS, LIM_REG_CLASSES };
574:
575: /* 'r' includes floating point registers if TARGET_NUMERICS. 'd' never
576: does. */
577: #define GENERAL_REGS ((TARGET_NUMERICS) ? ALL_REGS : LOCAL_OR_GLOBAL_REGS)
578:
579: #define N_REG_CLASSES (int) LIM_REG_CLASSES
580:
581: /* Give names of register classes as strings for dump file. */
582:
583: #define REG_CLASS_NAMES \
584: { "NO_REGS", "GLOBAL_REGS", "LOCAL_REGS", "LOCAL_OR_GLOBAL_REGS", \
585: "FP_REGS", "ALL_REGS" }
586:
587: /* Define which registers fit in which classes.
588: This is an initializer for a vector of HARD_REG_SET
589: of length N_REG_CLASSES. */
590:
591: #define REG_CLASS_CONTENTS \
592: { {0, 0}, {0x0ffff, 0}, {0xffff0000, 0}, {-1,0}, {0, -1}, {-1,-1}}
593:
594: /* The same information, inverted:
595: Return the class number of the smallest class containing
596: reg number REGNO. This could be a conditional expression
597: or could index an array. */
598:
599: #define REGNO_REG_CLASS(REGNO) \
600: ((REGNO) < 16 ? GLOBAL_REGS \
601: : (REGNO) < 32 ? LOCAL_REGS \
602: : (REGNO) < 36 ? FP_REGS \
603: : NO_REGS)
604:
605: /* The class value for index registers, and the one for base regs.
606: There is currently no difference between base and index registers on the
607: i960, but this distinction may one day be useful. */
608: #define INDEX_REG_CLASS LOCAL_OR_GLOBAL_REGS
609: #define BASE_REG_CLASS LOCAL_OR_GLOBAL_REGS
610:
611: /* Get reg_class from a letter such as appears in the machine description.
612: 'f' is a floating point register (fp0..fp3)
613: 'l' is a local register (r0-r15)
614: 'b' is a global register (g0-g15)
615: 'd' is any local or global register
616: 'r' or 'g' are pre-defined to the class GENERAL_REGS. */
617: /* 'l' and 'b' are probably never used. Note that 'd' and 'r' are *not*
618: the same thing, since 'r' may include the fp registers. */
619: #define REG_CLASS_FROM_LETTER(C) \
620: (((C) == 'f') && (TARGET_NUMERICS) ? FP_REGS : ((C) == 'l' ? LOCAL_REGS : \
621: (C) == 'b' ? GLOBAL_REGS : ((C) == 'd' ? LOCAL_OR_GLOBAL_REGS : NO_REGS)))
622:
623: /* The letters I, J, K, L and M in a register constraint string
624: can be used to stand for particular ranges of immediate operands.
625: This macro defines what the ranges are.
626: C is the letter, and VALUE is a constant value.
627: Return 1 if VALUE is in the range specified by C.
628:
629: For 80960:
630: 'I' is used for literal values 0..31
631: 'J' means literal 0
632: 'K' means 0..-31. */
633:
634: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
635: ((C) == 'I' ? (((unsigned) (VALUE)) <= 31) \
636: : (C) == 'J' ? ((VALUE) == 0) \
637: : (C) == 'K' ? ((VALUE) > -32 && (VALUE) <= 0) \
638: : 0)
639:
640: /* Similar, but for floating constants, and defining letters G and H.
641: Here VALUE is the CONST_DOUBLE rtx itself.
642: For the 80960, G is 0.0 and H is 1.0. */
643:
644: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
645: ((TARGET_NUMERICS) && \
646: (((C) == 'G' && ((VALUE) == CONST0_RTX (DFmode) \
647: || (VALUE) == CONST0_RTX (SFmode))) \
648: || ((C) == 'H' && ((VALUE) == CONST1_RTX (DFmode) \
649: || (VALUE) == CONST1_RTX (SFmode)))))
650:
651: /* Given an rtx X being reloaded into a reg required to be
652: in class CLASS, return the class of reg to actually use.
653: In general this is just CLASS; but on some machines
654: in some cases it is preferable to use a more restrictive class. */
655:
656: /* On 960, can't load constant into floating-point reg except
657: 0.0 or 1.0.
658:
659: Any hard reg is ok as a src operand of a reload insn. */
660:
661: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
662: (GET_CODE (X) == REG && REGNO (X) < FIRST_PSEUDO_REGISTER \
663: ? (CLASS) \
664: : ((CLASS) == FP_REGS && CONSTANT_P (X) \
665: && (X) != CONST0_RTX (DFmode) && (X) != CONST1_RTX (DFmode)\
666: && (X) != CONST0_RTX (SFmode) && (X) != CONST1_RTX (SFmode)\
667: ? NO_REGS \
668: : (CLASS) == ALL_REGS ? LOCAL_OR_GLOBAL_REGS : (CLASS)))
669:
670: #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \
671: secondary_reload_class (CLASS, MODE, IN)
672:
673: /* Return the maximum number of consecutive registers
674: needed to represent mode MODE in a register of class CLASS. */
675: /* On 80960, this is the size of MODE in words,
676: except in the FP regs, where a single reg is always enough. */
677: #define CLASS_MAX_NREGS(CLASS, MODE) \
678: ((CLASS) == FP_REGS ? 1 : HARD_REGNO_NREGS (0, (MODE)))
679:
680: /* Stack layout; function entry, exit and calling. */
681:
682: /* Define this if pushing a word on the stack
683: makes the stack pointer a smaller address. */
684: /* #define STACK_GROWS_DOWNWARD */
685:
686: /* Define this if the nominal address of the stack frame
687: is at the high-address end of the local variables;
688: that is, each additional local variable allocated
689: goes at a more negative offset in the frame. */
690: /* #define FRAME_GROWS_DOWNWARD */
691:
692: /* Offset within stack frame to start allocating local variables at.
693: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
694: first local allocated. Otherwise, it is the offset to the BEGINNING
695: of the first local allocated.
696:
697: The i960 has a 64 byte register save area, plus possibly some extra
698: bytes allocated for varargs functions. */
699: #define STARTING_FRAME_OFFSET 64
700:
701: /* If we generate an insn to push BYTES bytes,
702: this says how many the stack pointer really advances by.
703: On 80960, don't define this because there are no push insns. */
704: /* #define PUSH_ROUNDING(BYTES) BYTES */
705:
706: /* Offset of first parameter from the argument pointer register value. */
707: #define FIRST_PARM_OFFSET(FNDECL) 0
708:
709: /* When a parameter is passed in a register, no stack space is
710: allocated for it. However, when args are passed in the
711: stack, space is allocated for every register parameter. */
712: #define MAYBE_REG_PARM_STACK_SPACE 48
713: #define FINAL_REG_PARM_STACK_SPACE(CONST_SIZE, VAR_SIZE) \
714: i960_final_reg_parm_stack_space (CONST_SIZE, VAR_SIZE);
715: #define REG_PARM_STACK_SPACE(DECL) i960_reg_parm_stack_space (DECL)
716: #define OUTGOING_REG_PARM_STACK_SPACE
717:
718: /* Keep the stack pointer constant throughout the function. */
719: #define ACCUMULATE_OUTGOING_ARGS
720:
721: /* Value is 1 if returning from a function call automatically
722: pops the arguments described by the number-of-args field in the call.
723: FUNTYPE is the data type of the function (as a tree),
724: or for a library call it is an identifier node for the subroutine name. */
725:
726: #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
727:
728: /* Define how to find the value returned by a library function
729: assuming the value has mode MODE. */
730:
731: #define LIBCALL_VALUE(MODE) gen_rtx ((REG), (MODE), 0)
732:
733: /* 1 if N is a possible register number for a function value
734: as seen by the caller.
735: On 80960, returns are in g0..g3 */
736:
737: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
738:
739: /* 1 if N is a possible register number for function argument passing.
740: On 80960, parameters are passed in g0..g11 */
741:
742: #define FUNCTION_ARG_REGNO_P(N) ((N) < 12)
743:
744: /* Perform any needed actions needed for a function that is receiving a
745: variable number of arguments.
746:
747: CUM is as above.
748:
749: MODE and TYPE are the mode and type of the current parameter.
750:
751: PRETEND_SIZE is a variable that should be set to the amount of stack
752: that must be pushed by the prolog to pretend that our caller pushed
753: it.
754:
755: Normally, this macro will push all remaining incoming registers on the
756: stack and set PRETEND_SIZE to the length of the registers pushed. */
757:
758: #define SETUP_INCOMING_VARARGS(CUM,MODE,TYPE,PRETEND_SIZE,NO_RTL) \
759: i960_setup_incoming_varargs(&CUM,MODE,TYPE,&PRETEND_SIZE,NO_RTL)
760:
761: /* Define a data type for recording info about an argument list
762: during the scan of that argument list. This data type should
763: hold all necessary information about the function itself
764: and about the args processed so far, enough to enable macros
765: such as FUNCTION_ARG to determine where the next arg should go.
766:
767: On 80960, this is two integers, which count the number of register
768: parameters and the number of stack parameters seen so far. */
769:
770: struct cum_args { int ca_nregparms; int ca_nstackparms; };
771:
772: #define CUMULATIVE_ARGS struct cum_args
773:
774: /* Define the number of registers that can hold parameters.
775: This macro is used only in macro definitions below and/or i960.c. */
776: #define NPARM_REGS 12
777:
778: /* Define how to round to the next parameter boundary.
779: This macro is used only in macro definitions below and/or i960.c. */
780: #define ROUND_PARM(X, MULTIPLE_OF) \
781: ((((X) + (MULTIPLE_OF) - 1) / (MULTIPLE_OF)) * MULTIPLE_OF)
782:
783: /* Initialize a variable CUM of type CUMULATIVE_ARGS
784: for a call to a function whose data type is FNTYPE.
785: For a library call, FNTYPE is 0.
786:
787: On 80960, the offset always starts at 0; the first parm reg is g0. */
788:
789: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
790: ((CUM).ca_nregparms = 0, (CUM).ca_nstackparms = 0)
791:
792: /* Update the data in CUM to advance over an argument
793: of mode MODE and data type TYPE.
794: CUM should be advanced to align with the data type accessed and
795: also the size of that data type in # of regs.
796: (TYPE is null for libcalls where that information may not be available.) */
797:
798: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
799: i960_function_arg_advance(&CUM, MODE, TYPE, NAMED)
800:
801: /* Indicate the alignment boundary for an argument of the specified mode and
802: type. */
803: #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
804: (((TYPE) != 0) \
805: ? ((TYPE_ALIGN (TYPE) <= PARM_BOUNDARY) \
806: ? PARM_BOUNDARY \
807: : TYPE_ALIGN (TYPE)) \
808: : ((GET_MODE_ALIGNMENT (MODE) <= PARM_BOUNDARY) \
809: ? PARM_BOUNDARY \
810: : GET_MODE_ALIGNMENT (MODE)))
811:
812: /* Determine where to put an argument to a function.
813: Value is zero to push the argument on the stack,
814: or a hard register in which to store the argument.
815:
816: MODE is the argument's machine mode.
817: TYPE is the data type of the argument (as a tree).
818: This is null for libcalls where that information may
819: not be available.
820: CUM is a variable of type CUMULATIVE_ARGS which gives info about
821: the preceding args and about the function being called.
822: NAMED is nonzero if this argument is a named parameter
823: (otherwise it is an extra parameter matching an ellipsis). */
824:
825: extern struct rtx_def *i960_function_arg ();
826: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
827: i960_function_arg(&CUM, MODE, TYPE, NAMED)
828:
829: /* Define how to find the value returned by a function.
830: VALTYPE is the data type of the value (as a tree).
831: If the precise function being called is known, FUNC is its FUNCTION_DECL;
832: otherwise, FUNC is 0. */
833:
834: #define FUNCTION_VALUE(TYPE, FUNC) \
835: gen_rtx (REG, TYPE_MODE (TYPE), 0)
836:
837: /* Force aggregates and objects larger than 16 bytes to be returned in memory,
838: since we only have 4 registers available for return values. */
839:
840: #define RETURN_IN_MEMORY(TYPE) \
841: (TYPE_MODE (TYPE) == BLKmode || int_size_in_bytes (TYPE) > 16)
842:
843: /* Don't default to pcc-struct-return, because we have already specified
844: exactly how to return structures in the RETURN_IN_MEMORY macro. */
845: #define DEFAULT_PCC_STRUCT_RETURN 0
846:
847: /* For an arg passed partly in registers and partly in memory,
848: this is the number of registers used.
849: This never happens on 80960. */
850:
851: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) 0
852:
853: /* Output the label for a function definition.
854: This handles leaf functions and a few other things for the i960. */
855:
856: #define ASM_DECLARE_FUNCTION_NAME(FILE, NAME, DECL) \
857: i960_function_name_declare (FILE, NAME, DECL)
858:
859: /* This macro generates the assembly code for function entry.
860: FILE is a stdio stream to output the code to.
861: SIZE is an int: how many units of temporary storage to allocate.
862: Refer to the array `regs_ever_live' to determine which registers
863: to save; `regs_ever_live[I]' is nonzero if register number I
864: is ever used in the function. This macro is responsible for
865: knowing which registers should not be saved even if used. */
866:
867: #define FUNCTION_PROLOGUE(FILE, SIZE) i960_function_prologue ((FILE), (SIZE))
868:
869: /* Output assembler code to FILE to increment profiler label # LABELNO
870: for profiling a function entry. */
871:
872: #define FUNCTION_PROFILER(FILE, LABELNO) \
873: output_function_profiler ((FILE), (LABELNO));
874:
875: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
876: the stack pointer does not matter. The value is tested only in
877: functions that have frame pointers.
878: No definition is equivalent to always zero. */
879:
880: #define EXIT_IGNORE_STACK 1
881:
882: /* This macro generates the assembly code for function exit,
883: on machines that need it. If FUNCTION_EPILOGUE is not defined
884: then individual return instructions are generated for each
885: return statement. Args are same as for FUNCTION_PROLOGUE.
886:
887: The function epilogue should not depend on the current stack pointer!
888: It should use the frame pointer only. This is mandatory because
889: of alloca; we also take advantage of it to omit stack adjustments
890: before returning. */
891:
892: #define FUNCTION_EPILOGUE(FILE, SIZE) i960_function_epilogue (FILE, SIZE)
893:
894: /* Addressing modes, and classification of registers for them. */
895:
896: /* #define HAVE_POST_INCREMENT */
897: /* #define HAVE_POST_DECREMENT */
898:
899: /* #define HAVE_PRE_DECREMENT */
900: /* #define HAVE_PRE_INCREMENT */
901:
902: /* Macros to check register numbers against specific register classes. */
903:
904: /* These assume that REGNO is a hard or pseudo reg number.
905: They give nonzero only if REGNO is a hard reg of the suitable class
906: or a pseudo reg currently allocated to a suitable hard reg.
907: Since they use reg_renumber, they are safe only once reg_renumber
908: has been allocated, which happens in local-alloc.c. */
909:
910: #define REGNO_OK_FOR_INDEX_P(REGNO) \
911: ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
912: #define REGNO_OK_FOR_BASE_P(REGNO) \
913: ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)
914: #define REGNO_OK_FOR_FP_P(REGNO) \
915: ((REGNO) < 36 || (unsigned) reg_renumber[REGNO] < 36)
916:
917: /* Now macros that check whether X is a register and also,
918: strictly, whether it is in a specified class.
919:
920: These macros are specific to the 960, and may be used only
921: in code for printing assembler insns and in conditions for
922: define_optimization. */
923:
924: /* 1 if X is an fp register. */
925:
926: #define FP_REG_P(X) (REGNO (X) >= 32 && REGNO (X) < 36)
927:
928: /* Maximum number of registers that can appear in a valid memory address. */
929: #define MAX_REGS_PER_ADDRESS 2
930:
931: #define CONSTANT_ADDRESS_P(X) \
932: (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \
933: || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \
934: || GET_CODE (X) == HIGH)
935:
936: /* LEGITIMATE_CONSTANT_P is nonzero if the constant value X
937: is a legitimate general operand.
938: It is given that X satisfies CONSTANT_P.
939:
940: Anything but a CONST_DOUBLE can be made to work, excepting 0.0 and 1.0. */
941:
942: #define LEGITIMATE_CONSTANT_P(X) \
943: ((GET_CODE (X) != CONST_DOUBLE) || fp_literal ((X), VOIDmode))
944:
945: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
946: and check its validity for a certain class.
947: We have two alternate definitions for each of them.
948: The usual definition accepts all pseudo regs; the other rejects
949: them unless they have been allocated suitable hard regs.
950: The symbol REG_OK_STRICT causes the latter definition to be used.
951:
952: Most source files want to accept pseudo regs in the hope that
953: they will get allocated to the class that the insn wants them to be in.
954: Source files for reload pass need to be strict.
955: After reload, it makes no difference, since pseudo regs have
956: been eliminated by then. */
957:
958: #ifndef REG_OK_STRICT
959:
960: /* Nonzero if X is a hard reg that can be used as an index
961: or if it is a pseudo reg. */
962: #define REG_OK_FOR_INDEX_P(X) \
963: (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
964: /* Nonzero if X is a hard reg that can be used as a base reg
965: or if it is a pseudo reg. */
966: #define REG_OK_FOR_BASE_P(X) \
967: (REGNO (X) < 32 || REGNO (X) >= FIRST_PSEUDO_REGISTER)
968:
969: #define REG_OK_FOR_INDEX_P_STRICT(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
970: #define REG_OK_FOR_BASE_P_STRICT(X) REGNO_OK_FOR_BASE_P (REGNO (X))
971:
972: #else
973:
974: /* Nonzero if X is a hard reg that can be used as an index. */
975: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
976: /* Nonzero if X is a hard reg that can be used as a base reg. */
977: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
978:
979: #endif
980:
981: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
982: that is a valid memory address for an instruction.
983: The MODE argument is the machine mode for the MEM expression
984: that wants to use this address.
985:
986: On 80960, legitimate addresses are:
987: base ld (g0),r0
988: disp (12 or 32 bit) ld foo,r0
989: base + index ld (g0)[g1*1],r0
990: base + displ ld 0xf00(g0),r0
991: base + index*scale + displ ld 0xf00(g0)[g1*4],r0
992: index*scale + base ld (g0)[g1*4],r0
993: index*scale + displ ld 0xf00[g1*4],r0
994: index*scale ld [g1*4],r0
995: index + base + displ ld 0xf00(g0)[g1*1],r0
996:
997: In each case, scale can be 1, 2, 4, 8, or 16. */
998:
999: /* Returns 1 if the scale factor of an index term is valid. */
1000: #define SCALE_TERM_P(X) \
1001: (GET_CODE (X) == CONST_INT \
1002: && (INTVAL (X) == 1 || INTVAL (X) == 2 || INTVAL (X) == 4 \
1003: || INTVAL(X) == 8 || INTVAL (X) == 16))
1004:
1005:
1006: #ifdef REG_OK_STRICT
1007: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1008: { if (legitimate_address_p (MODE, X, 1)) goto ADDR; }
1009: #else
1010: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1011: { if (legitimate_address_p (MODE, X, 0)) goto ADDR; }
1012: #endif
1013:
1014: /* Try machine-dependent ways of modifying an illegitimate address
1015: to be legitimate. If we find one, return the new, valid address.
1016: This macro is used in only one place: `memory_address' in explow.c.
1017:
1018: OLDX is the address as it was before break_out_memory_refs was called.
1019: In some cases it is useful to look at this to decide what needs to be done.
1020:
1021: MODE and WIN are passed so that this macro can use
1022: GO_IF_LEGITIMATE_ADDRESS.
1023:
1024: It is always safe for this macro to do nothing. It exists to recognize
1025: opportunities to optimize the output. */
1026:
1027: /* On 80960, convert non-canonical addresses to canonical form. */
1028:
1029: extern struct rtx_def *legitimize_address ();
1030: #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) \
1031: { rtx orig_x = (X); \
1032: (X) = legitimize_address (X, OLDX, MODE); \
1033: if ((X) != orig_x && memory_address_p (MODE, X)) \
1034: goto WIN; }
1035:
1036: /* Go to LABEL if ADDR (a legitimate address expression)
1037: has an effect that depends on the machine mode it is used for.
1038: On the 960 this is never true. */
1039:
1040: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL)
1041:
1042: /* Specify the machine mode that this machine uses
1043: for the index in the tablejump instruction. */
1044: #define CASE_VECTOR_MODE SImode
1045:
1046: /* Define this if the tablejump instruction expects the table
1047: to contain offsets from the address of the table.
1048: Do not define this if the table should contain absolute addresses. */
1049: /* #define CASE_VECTOR_PC_RELATIVE */
1050:
1051: /* Specify the tree operation to be used to convert reals to integers. */
1052: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1053:
1054: /* This is the kind of divide that is easiest to do in the general case. */
1055: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1056:
1057: /* Define this as 1 if `char' should by default be signed; else as 0. */
1058: #define DEFAULT_SIGNED_CHAR 0
1059:
1060: /* Allow and ignore #sccs directives. */
1061: #define SCCS_DIRECTIVE
1062:
1063: /* Max number of bytes we can move from memory to memory
1064: in one reasonably fast instruction. */
1065: #define MOVE_MAX 16
1066:
1.1.1.2 root 1067: /* Define if operations between registers always perform the operation
1068: on the full register even if a narrower mode is specified. */
1069: #define WORD_REGISTER_OPERATIONS
1070:
1071: /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD
1072: will either zero-extend or sign-extend. The value of this macro should
1073: be the code that says which one of the two operations is implicitly
1074: done, NIL if none. */
1075: #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND
1.1 root 1076:
1077: /* Nonzero if access to memory by bytes is no faster than for words.
1078: Defining this results in worse code on the i960. */
1079:
1080: #define SLOW_BYTE_ACCESS 0
1081:
1082: /* We assume that the store-condition-codes instructions store 0 for false
1083: and some other value for true. This is the value stored for true. */
1084:
1085: #define STORE_FLAG_VALUE 1
1086:
1.1.1.2 root 1087: /* Define this to be nonzero if shift instructions ignore all but the low-order
1088: few bits. */
1089: #define SHIFT_COUNT_TRUNCATED 1
1.1 root 1090:
1091: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1092: is done just by pretending it is already truncated. */
1093: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1094:
1095: /* Specify the machine mode that pointers have.
1096: After generation of rtl, the compiler makes no further distinction
1097: between pointers and any other objects of this machine mode. */
1098: #define Pmode SImode
1099:
1100: /* Specify the widest mode that BLKmode objects can be promoted to */
1101: #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode)
1102:
1103: /* These global variables are used to pass information between
1104: cc setter and cc user at insn emit time. */
1105:
1106: extern struct rtx_def *i960_compare_op0, *i960_compare_op1;
1107:
1108: /* Define the function that build the compare insn for scc and bcc. */
1109:
1110: extern struct rtx_def *gen_compare_reg ();
1111:
1112: /* Add any extra modes needed to represent the condition code.
1113:
1114: Also, signed and unsigned comparisons are distinguished, as
1115: are operations which are compatible with chkbit insns. */
1116: #define EXTRA_CC_MODES CC_UNSmode, CC_CHKmode
1117:
1118: /* Define the names for the modes specified above. */
1119: #define EXTRA_CC_NAMES "CC_UNS", "CC_CHK"
1120:
1121: /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE,
1122: return the mode to be used for the comparison. For floating-point, CCFPmode
1123: should be used. CC_NOOVmode should be used when the first operand is a
1124: PLUS, MINUS, or NEG. CCmode should be used when no special processing is
1125: needed. */
1126: #define SELECT_CC_MODE(OP,X,Y) select_cc_mode (OP, X)
1127:
1128: /* A function address in a call instruction is a byte address
1129: (for indexing purposes) so give the MEM rtx a byte's mode. */
1130: #define FUNCTION_MODE SImode
1131:
1132: /* Define this if addresses of constant functions
1133: shouldn't be put through pseudo regs where they can be cse'd.
1134: Desirable on machines where ordinary constants are expensive
1135: but a CALL with constant address is cheap. */
1136: #define NO_FUNCTION_CSE
1137:
1138: /* Use memcpy, etc. instead of bcopy. */
1139:
1140: #ifndef WIND_RIVER
1141: #define TARGET_MEM_FUNCTIONS 1
1142: #endif
1143:
1144: /* Compute the cost of computing a constant rtl expression RTX
1145: whose rtx-code is CODE. The body of this macro is a portion
1146: of a switch statement. If the code is computed here,
1147: return it with a return statement. Otherwise, break from the switch. */
1148:
1149: /* Constants that can be (non-ldconst) insn operands are cost 0. Constants
1150: that can be non-ldconst operands in rare cases are cost 1. Other constants
1151: have higher costs. */
1152:
1153: #define CONST_COSTS(RTX, CODE, OUTER_CODE) \
1154: case CONST_INT: \
1155: if ((INTVAL (RTX) >= 0 && INTVAL (RTX) < 32) \
1156: || power2_operand (RTX, VOIDmode)) \
1157: return 0; \
1158: else if (INTVAL (RTX) >= -31 && INTVAL (RTX) < 0) \
1159: return 1; \
1160: case CONST: \
1161: case LABEL_REF: \
1162: case SYMBOL_REF: \
1163: return (TARGET_FLAG_C_SERIES ? 6 : 8); \
1164: case CONST_DOUBLE: \
1165: if ((RTX) == CONST0_RTX (DFmode) || (RTX) == CONST0_RTX (SFmode) \
1166: || (RTX) == CONST1_RTX (DFmode) || (RTX) == CONST1_RTX (SFmode))\
1167: return 1; \
1168: return 12;
1169:
1170: /* The i960 offers addressing modes which are "as cheap as a register".
1171: See i960.c (or gcc.texinfo) for details. */
1172:
1173: #define ADDRESS_COST(RTX) \
1174: (GET_CODE (RTX) == REG ? 1 : i960_address_cost (RTX))
1175:
1176: /* Control the assembler format that we output. */
1177:
1178: /* Output at beginning of assembler file. */
1179:
1180: #define ASM_FILE_START(file)
1181:
1182: /* Output to assembler file text saying following lines
1183: may contain character constants, extra white space, comments, etc. */
1184:
1185: #define ASM_APP_ON ""
1186:
1187: /* Output to assembler file text saying following lines
1188: no longer contain unusual constructs. */
1189:
1190: #define ASM_APP_OFF ""
1191:
1192: /* Output before read-only data. */
1193:
1194: #define TEXT_SECTION_ASM_OP ".text"
1195:
1196: /* Output before writable data. */
1197:
1198: #define DATA_SECTION_ASM_OP ".data"
1199:
1200: /* How to refer to registers in assembler output.
1201: This sequence is indexed by compiler's hard-register-number (see above). */
1202:
1203: #define REGISTER_NAMES { \
1204: "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7", \
1205: "g8", "g9", "g10", "g11", "g12", "g13", "g14", "fp", \
1206: "pfp","sp", "rip", "r3", "r4", "r5", "r6", "r7", \
1207: "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", \
1208: "fp0","fp1","fp2", "fp3", "cc", "fake" }
1209:
1210: /* How to renumber registers for dbx and gdb.
1211: In the 960 encoding, g0..g15 are registers 16..31. */
1212:
1213: #define DBX_REGISTER_NUMBER(REGNO) \
1214: (((REGNO) < 16) ? (REGNO) + 16 \
1215: : (((REGNO) > 31) ? (REGNO) : (REGNO) - 16))
1216:
1217: /* Don't emit dbx records longer than this. This is an arbitrary value. */
1218: #define DBX_CONTIN_LENGTH 1500
1219:
1220: /* This is how to output a note to DBX telling it the line number
1221: to which the following sequence of instructions corresponds. */
1222:
1223: #define ASM_OUTPUT_SOURCE_LINE(FILE, LINE) \
1224: { if (write_symbols == SDB_DEBUG) { \
1225: fprintf ((FILE), "\t.ln %d\n", \
1226: (sdb_begin_function_line \
1227: ? (LINE) - sdb_begin_function_line : 1)); \
1228: } else if (write_symbols == DBX_DEBUG) { \
1229: fprintf((FILE),"\t.stabd 68,0,%d\n",(LINE)); \
1230: } }
1231:
1232: /* This is how to output the definition of a user-level label named NAME,
1233: such as the label on a static function or variable NAME. */
1234:
1235: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1236: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1237:
1238: /* This is how to output a command to make the user-level label named NAME
1239: defined for reference from other files. */
1240:
1241: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1242: { fputs ("\t.globl ", FILE); \
1243: assemble_name (FILE, NAME); \
1244: fputs ("\n", FILE); }
1245:
1246: /* This is how to output a reference to a user-level label named NAME.
1247: `assemble_name' uses this. */
1248:
1249: #define ASM_OUTPUT_LABELREF(FILE,NAME) fprintf (FILE, "_%s", NAME)
1250:
1251: /* This is how to output an internal numbered label where
1252: PREFIX is the class of label and NUM is the number within the class. */
1253:
1254: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1255: fprintf (FILE, "%s%d:\n", PREFIX, NUM)
1256:
1257: /* This is how to store into the string LABEL
1258: the symbol_ref name of an internal numbered label where
1259: PREFIX is the class of label and NUM is the number within the class.
1260: This is suitable for output with `assemble_name'. */
1261:
1262: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1263: sprintf (LABEL, "*%s%d", PREFIX, NUM)
1264:
1265: /* This is how to output an assembler line defining a `double' constant. */
1266:
1267: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) i960_output_double(FILE, VALUE)
1268:
1269: /* This is how to output an assembler line defining a `float' constant. */
1270:
1271: #define ASM_OUTPUT_FLOAT(FILE,VALUE) i960_output_float(FILE, VALUE)
1272:
1273: /* This is how to output an assembler line defining an `int' constant. */
1274:
1275: #define ASM_OUTPUT_INT(FILE,VALUE) \
1276: ( fprintf (FILE, "\t.word "), \
1277: output_addr_const (FILE, (VALUE)), \
1278: fprintf (FILE, "\n"))
1279:
1280: /* Likewise for `char' and `short' constants. */
1281:
1282: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1283: ( fprintf (FILE, "\t.short "), \
1284: output_addr_const (FILE, (VALUE)), \
1285: fprintf (FILE, "\n"))
1286:
1287: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1288: ( fprintf (FILE, "\t.byte "), \
1289: output_addr_const (FILE, (VALUE)), \
1290: fprintf (FILE, "\n"))
1291:
1292: /* This is how to output an assembler line for a numeric constant byte. */
1293:
1294: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1295: fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1296:
1297: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1298: fprintf (FILE, "\tst\t%s,(sp)\n\taddo\t4,sp,sp\n", reg_names[REGNO])
1299:
1300: /* This is how to output an insn to pop a register from the stack.
1301: It need not be very fast code. */
1302:
1303: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1304: fprintf (FILE, "\tsubo\t4,sp,sp\n\tld\t(sp),%s\n", reg_names[REGNO])
1305:
1306: /* This is how to output an element of a case-vector that is absolute. */
1307:
1308: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1309: fprintf (FILE, "\t.word L%d\n", VALUE)
1310:
1311: /* This is how to output an element of a case-vector that is relative. */
1312:
1313: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1314: fprintf (FILE, "\t.word L%d-L%d\n", VALUE, REL)
1315:
1316: /* This is how to output an assembler line that says to advance the
1317: location counter to a multiple of 2**LOG bytes. */
1318:
1319: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1320: fprintf (FILE, "\t.align %d\n", (LOG))
1321:
1322: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1323: fprintf (FILE, "\t.space %d\n", (SIZE))
1324:
1325: /* This says how to output an assembler line
1326: to define a global common symbol. */
1327:
1328: /* For common objects, output unpadded size... gld960 & lnk960 both
1329: have code to align each common object at link time. Also, if size
1330: is 0, treat this as a declaration, not a definition - i.e.,
1331: do nothing at all. */
1332:
1333: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1334: { if ((SIZE) != 0) \
1335: { \
1336: fputs (".globl ", (FILE)), \
1337: assemble_name ((FILE), (NAME)), \
1338: fputs ("\n.comm ", (FILE)), \
1339: assemble_name ((FILE), (NAME)), \
1.1.1.2 root 1340: fprintf ((FILE), ",%d\n", (SIZE)); \
1.1 root 1341: } \
1342: }
1343:
1344: /* This says how to output an assembler line to define a local common symbol.
1345: Output unpadded size, with request to linker to align as requested.
1346: 0 size should not be possible here. */
1347:
1348: #define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGN) \
1349: ( fputs (".bss\t", (FILE)), \
1350: assemble_name ((FILE), (NAME)), \
1351: fprintf ((FILE), ",%d,%d\n", (SIZE), \
1352: ((ALIGN) <= 8 ? 0 \
1353: : ((ALIGN) <= 16 ? 1 \
1354: : ((ALIGN) <= 32 ? 2 \
1355: : ((ALIGN <= 64 ? 3 : 4)))))))
1356:
1357: /* Output text for an #ident directive. */
1358: #define ASM_OUTPUT_IDENT(FILE, STR) fprintf(FILE, "\t# %s\n", STR);
1359:
1360: /* Align code to 8 byte boundary if TARGET_CODE_ALIGN is true. */
1361:
1362: #define ASM_OUTPUT_ALIGN_CODE(FILE) \
1363: { if (TARGET_CODE_ALIGN) fputs("\t.align 3\n",FILE); }
1364:
1365: /* Store in OUTPUT a string (made with alloca) containing
1366: an assembler-name for a local static variable named NAME.
1367: LABELNO is an integer which is different for each call. */
1368:
1369: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1370: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1371: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1372:
1373: /* Define the parentheses used to group arithmetic operations
1374: in assembler code. */
1375:
1376: #define ASM_OPEN_PAREN "("
1377: #define ASM_CLOSE_PAREN ")"
1378:
1379: /* Define results of standard character escape sequences. */
1380: #define TARGET_BELL 007
1381: #define TARGET_BS 010
1382: #define TARGET_TAB 011
1383: #define TARGET_NEWLINE 012
1384: #define TARGET_VT 013
1385: #define TARGET_FF 014
1386: #define TARGET_CR 015
1387:
1388: /* Output assembler code to FILE to initialize this source file's
1389: basic block profiling info, if that has not already been done. */
1390:
1391: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
1392: { fprintf (FILE, "\tld LPBX0,g12\n"); \
1393: fprintf (FILE, "\tcmpobne 0,g12,LPY%d\n",LABELNO);\
1394: fprintf (FILE, "\tlda LPBX0,g12\n"); \
1395: fprintf (FILE, "\tcall ___bb_init_func\n"); \
1396: fprintf (FILE, "LPY%d:\n",LABELNO); }
1397:
1398: /* Output assembler code to FILE to increment the entry-count for
1399: the BLOCKNO'th basic block in this source file. */
1400:
1401: #define BLOCK_PROFILER(FILE, BLOCKNO) \
1402: { int blockn = (BLOCKNO); \
1403: fprintf (FILE, "\tld LPBX2+%d,g12\n", 4 * blockn); \
1404: fprintf (FILE, "\taddo g12,1,g12\n"); \
1405: fprintf (FILE, "\tst g12,LPBX2+%d\n", 4 * blockn); }
1406:
1407: /* Print operand X (an rtx) in assembler syntax to file FILE.
1408: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1409: For `%' followed by punctuation, CODE is the punctuation and X is null. */
1410:
1411: #define PRINT_OPERAND(FILE, X, CODE) \
1412: i960_print_operand (FILE, X, CODE);
1413:
1414: /* Print a memory address as an operand to reference that memory location. */
1415:
1416: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \
1417: i960_print_operand_addr (FILE, ADDR)
1418:
1419: /* Output assembler code for a block containing the constant parts
1420: of a trampoline, leaving space for the variable parts. */
1421:
1422: /* On the i960, the trampoline contains three instructions:
1423: ldconst _function, r4
1424: ldconst static addr, r3
1425: jump (r4) */
1426:
1427: #define TRAMPOLINE_TEMPLATE(FILE) \
1428: { \
1429: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C203000)); \
1430: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1431: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x8C183000)); \
1432: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x00000000)); \
1433: ASM_OUTPUT_INT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x84212000)); \
1434: }
1435:
1436: /* Length in units of the trampoline for entering a nested function. */
1437:
1438: #define TRAMPOLINE_SIZE 20
1439:
1440: /* Emit RTL insns to initialize the variable parts of a trampoline.
1441: FNADDR is an RTX for the address of the function's pure code.
1442: CXT is an RTX for the static chain value for the function. */
1443:
1444: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
1445: { \
1446: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 4)), \
1447: FNADDR); \
1448: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 12)), \
1449: CXT); \
1450: }
1451:
1452: #if 0
1453: /* Promote char and short arguments to ints, when want compatibility with
1454: the iC960 compilers. */
1455:
1456: /* ??? In order for this to work, all users would need to be changed
1457: to test the value of the macro at run time. */
1458: #define PROMOTE_PROTOTYPES TARGET_CLEAN_LINKAGE
1459: /* ??? This does not exist. */
1460: #define PROMOTE_RETURN TARGET_CLEAN_LINKAGE
1461: #endif
1462:
1463: /* Instruction type definitions. Used to alternate instructions types for
1464: better performance on the C series chips. */
1465:
1466: enum insn_types { I_TYPE_REG, I_TYPE_MEM, I_TYPE_CTRL };
1467:
1468: /* Holds the insn type of the last insn output to the assembly file. */
1469:
1470: extern enum insn_types i960_last_insn_type;
1471:
1472: /* Parse opcodes, and set the insn last insn type based on them. */
1473:
1474: #define ASM_OUTPUT_OPCODE(FILE, INSN) i960_scan_opcode (INSN)
1475:
1476: /* Table listing what rtl codes each predicate in i960.c will accept. */
1477:
1478: #define PREDICATE_CODES \
1479: {"fpmove_src_operand", {CONST_INT, CONST_DOUBLE, CONST, SYMBOL_REF, \
1480: LABEL_REF, SUBREG, REG, MEM}}, \
1481: {"arith_operand", {SUBREG, REG, CONST_INT}}, \
1482: {"fp_arith_operand", {SUBREG, REG, CONST_DOUBLE}}, \
1483: {"signed_arith_operand", {SUBREG, REG, CONST_INT}}, \
1484: {"literal", {CONST_INT}}, \
1485: {"fp_literal_one", {CONST_DOUBLE}}, \
1486: {"fp_literal_double", {CONST_DOUBLE}}, \
1487: {"fp_literal", {CONST_DOUBLE}}, \
1488: {"signed_literal", {CONST_INT}}, \
1489: {"symbolic_memory_operand", {SUBREG, MEM}}, \
1490: {"eq_or_neq", {EQ, NE}}, \
1491: {"arith32_operand", {SUBREG, REG, LABEL_REF, SYMBOL_REF, CONST_INT, \
1492: CONST_DOUBLE, CONST}}, \
1.1.1.2 root 1493: {"power2_operand", {CONST_INT}}, \
1494: {"cmplpower2_operand", {CONST_INT}},
1.1 root 1495:
1496: /* Define functions in i960.c and used in insn-output.c. */
1497:
1498: extern char *i960_output_ldconst ();
1499: extern char *i960_output_call_insn ();
1500: extern char *i960_output_ret_insn ();
1501:
1502: /* Defined in reload.c, and used in insn-recog.c. */
1503:
1504: extern int rtx_equal_function_value_matters;
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