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1.1 root 1: ;;- Machine description for Intel 80960 chip for GNU C compiler 1.1.1.3 ! root 2: ;; Copyright (C) 1992, 1995 Free Software Foundation, Inc. 1.1 root 3: ;; Contributed by Steven McGeady, Intel Corp. 4: ;; Additional work by Glenn Colon-Bonet, Jonathan Shapiro, Andy Wilson 5: ;; Converted to GCC 2.0 by Jim Wilson and Michael Tiemann, Cygnus Support. 6: 7: ;; This file is part of GNU CC. 8: 9: ;; GNU CC is free software; you can redistribute it and/or modify 10: ;; it under the terms of the GNU General Public License as published by 11: ;; the Free Software Foundation; either version 2, or (at your option) 12: ;; any later version. 13: 14: ;; GNU CC is distributed in the hope that it will be useful, 15: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 16: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17: ;; GNU General Public License for more details. 18: 19: ;; You should have received a copy of the GNU General Public License 20: ;; along with GNU CC; see the file COPYING. If not, write to 1.1.1.3 ! root 21: ;; the Free Software Foundation, 59 Temple Place - Suite 330, ! 22: ;; Boston, MA 02111-1307, USA. 1.1 root 23: 24: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 25: 26: ;; There are very few (4) 'f' registers, they can't be loaded/stored from/to 27: ;; memory, and some instructions explicitly require them, so we get better 1.1.1.3 ! root 28: ;; code by discouraging pseudo-registers from being allocated to them. 1.1 root 29: ;; However, we do want to allow all patterns which can store to them to 30: ;; include them in their constraints, so we always use '*f' in a destination 31: ;; constraint except when 'f' is the only alternative. 32: 33: ;; Insn attributes which describe the i960. 34: 35: ;; Modscan is not used, since the compiler never emits any of these insns. 36: (define_attr "type" 37: "move,arith,alu2,mult,div,modscan,load,store,branch,call,address,compare,fpload,fpstore,fpmove,fpcvt,fpcc,fpadd,fpmul,fpdiv,multi,misc" 38: (const_string "arith")) 39: 40: ;; Length (in # of insns). 41: (define_attr "length" "" 42: (cond [(eq_attr "type" "load,fpload") 43: (if_then_else (match_operand 1 "symbolic_memory_operand" "") 44: (const_int 2) 45: (const_int 1)) 46: (eq_attr "type" "store,fpstore") 47: (if_then_else (match_operand 0 "symbolic_memory_operand" "") 48: (const_int 2) 49: (const_int 1)) 50: (eq_attr "type" "address") 51: (const_int 2)] 52: (const_int 1))) 53: 54: (define_asm_attributes 55: [(set_attr "length" "1") 56: (set_attr "type" "multi")]) 57: 58: ;; (define_function_unit {name} {num-units} {n-users} {test} 59: ;; {ready-delay} {issue-delay} [{conflict-list}]) 60: 61: ;; The integer ALU 62: (define_function_unit "alu" 2 0 (eq_attr "type" "arith,compare,move,address") 1 0) 63: (define_function_unit "alu" 2 0 (eq_attr "type" "alu2") 2 0) 64: (define_function_unit "alu" 2 0 (eq_attr "type" "mult") 5 0) 65: (define_function_unit "alu" 2 0 (eq_attr "type" "div") 35 0) 66: (define_function_unit "alu" 2 0 (eq_attr "type" "modscan") 3 0) 67: 68: ;; Memory with load-delay of 1 (i.e., 2 cycle load). 69: (define_function_unit "memory" 1 0 (eq_attr "type" "load,fpload") 2 0) 70: 71: ;; Floating point operations. 72: (define_function_unit "fp" 1 2 (eq_attr "type" "fpmove") 5 0) 73: (define_function_unit "fp" 1 2 (eq_attr "type" "fpcvt") 35 0) 74: (define_function_unit "fp" 1 2 (eq_attr "type" "fpcc") 10 0) 75: (define_function_unit "fp" 1 2 (eq_attr "type" "fpadd") 10 0) 76: (define_function_unit "fp" 1 2 (eq_attr "type" "fpmul") 20 0) 77: (define_function_unit "fp" 1 2 (eq_attr "type" "fpdiv") 35 0) 78: 79: ;; Compare instructions. 80: ;; This controls RTL generation and register allocation. 81: 82: ;; We generate RTL for comparisons and branches by having the cmpxx 83: ;; patterns store away the operands. Then, the scc and bcc patterns 84: ;; emit RTL for both the compare and the branch. 85: ;; 86: ;; We start with the DEFINE_EXPANDs, then then DEFINE_INSNs to match 87: ;; the patterns. Finally, we have the DEFINE_SPLITs for some of the scc 88: ;; insns that actually require more than one machine instruction. 89: 90: ;; Put cmpsi first because it is expected to be the most common. 91: 92: (define_expand "cmpsi" 93: [(set (reg:CC 36) 94: (compare:CC (match_operand:SI 0 "nonimmediate_operand" "") 95: (match_operand:SI 1 "general_operand" "")))] 96: "" 97: " 98: { 99: i960_compare_op0 = operands[0]; 100: i960_compare_op1 = operands[1]; 101: DONE; 102: }") 103: 104: (define_expand "cmpdf" 105: [(set (reg:CC 36) 106: (compare:CC (match_operand:DF 0 "register_operand" "r") 107: (match_operand:DF 1 "nonmemory_operand" "rGH")))] 108: "TARGET_NUMERICS" 109: " 110: { 111: i960_compare_op0 = operands[0]; 112: i960_compare_op1 = operands[1]; 113: DONE; 114: }") 115: 116: (define_expand "cmpsf" 117: [(set (reg:CC 36) 118: (compare:CC (match_operand:SF 0 "register_operand" "r") 119: (match_operand:SF 1 "nonmemory_operand" "rGH")))] 120: "TARGET_NUMERICS" 121: " 122: { 123: i960_compare_op0 = operands[0]; 124: i960_compare_op1 = operands[1]; 125: DONE; 126: }") 127: 128: ;; Now the DEFINE_INSNs for the compare and scc cases. First the compares. 129: 130: (define_insn "" 131: [(set (reg:CC 36) 132: (compare:CC (match_operand:SI 0 "register_operand" "d") 133: (match_operand:SI 1 "arith_operand" "dI")))] 134: "" 135: "cmpi %0,%1" 136: [(set_attr "type" "compare")]) 137: 138: (define_insn "" 139: [(set (reg:CC_UNS 36) 140: (compare:CC_UNS (match_operand:SI 0 "register_operand" "d") 141: (match_operand:SI 1 "arith_operand" "dI")))] 142: "" 143: "cmpo %0,%1" 144: [(set_attr "type" "compare")]) 145: 146: (define_insn "" 147: [(set (reg:CC 36) 148: (compare:CC (match_operand:DF 0 "register_operand" "r") 149: (match_operand:DF 1 "nonmemory_operand" "rGH")))] 150: "TARGET_NUMERICS" 151: "cmprl %0,%1" 152: [(set_attr "type" "fpcc")]) 153: 154: (define_insn "" 155: [(set (reg:CC 36) 156: (compare:CC (match_operand:SF 0 "register_operand" "r") 157: (match_operand:SF 1 "nonmemory_operand" "rGH")))] 158: "TARGET_NUMERICS" 159: "cmpr %0,%1" 160: [(set_attr "type" "fpcc")]) 161: 162: ;; Instruction definitions for branch-on-bit-set and clear insns. 163: 164: (define_insn "" 165: [(set (pc) 166: (if_then_else 167: (ne (sign_extract:SI (match_operand:SI 1 "register_operand" "d") 168: (const_int 1) 169: (match_operand:SI 2 "arith_operand" "dI")) 170: (const_int 0)) 171: (label_ref (match_operand 3 "" "")) 172: (pc)))] 173: "" 174: "bbs %2,%1,%l3" 175: [(set_attr "type" "branch")]) 176: 177: (define_insn "" 178: [(set (pc) 179: (if_then_else 180: (eq (sign_extract:SI (match_operand:SI 1 "register_operand" "d") 181: (const_int 1) 182: (match_operand:SI 2 "arith_operand" "dI")) 183: (const_int 0)) 184: (label_ref (match_operand 3 "" "")) 185: (pc)))] 186: "" 187: "bbc %2,%1,%l3" 188: [(set_attr "type" "branch")]) 189: 190: (define_insn "" 191: [(set (pc) 192: (if_then_else 193: (ne (zero_extract:SI (match_operand:SI 1 "register_operand" "d") 194: (const_int 1) 195: (match_operand:SI 2 "arith_operand" "dI")) 196: (const_int 0)) 197: (label_ref (match_operand 3 "" "")) 198: (pc)))] 199: "" 200: "bbs %2,%1,%l3" 201: [(set_attr "type" "branch")]) 202: 203: (define_insn "" 204: [(set (pc) 205: (if_then_else 206: (eq (zero_extract:SI (match_operand:SI 1 "register_operand" "d") 207: (const_int 1) 208: (match_operand:SI 2 "arith_operand" "dI")) 209: (const_int 0)) 210: (label_ref (match_operand 3 "" "")) 211: (pc)))] 212: "" 213: "bbc %2,%1,%l3" 214: [(set_attr "type" "branch")]) 215: 216: ;; ??? These will never match. The LOG_LINKs necessary to make these match 217: ;; are not created by flow. These remain as a reminder to make this work 218: ;; some day. 219: 220: (define_insn "" 221: [(set (reg:CC 36) 222: (compare (match_operand:SI 0 "arith_operand" "d") 223: (match_operand:SI 1 "arith_operand" "d"))) 224: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))] 225: "0" 226: "cmpinci %0,%1" 227: [(set_attr "type" "compare")]) 228: 229: (define_insn "" 230: [(set (reg:CC_UNS 36) 231: (compare (match_operand:SI 0 "arith_operand" "d") 232: (match_operand:SI 1 "arith_operand" "d"))) 233: (set (match_dup 1) (plus:SI (match_dup 1) (const_int 1)))] 234: "0" 235: "cmpinco %0,%1" 236: [(set_attr "type" "compare")]) 237: 238: (define_insn "" 239: [(set (reg:CC 36) 240: (compare (match_operand:SI 0 "arith_operand" "d") 241: (match_operand:SI 1 "arith_operand" "d"))) 242: (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))] 243: "0" 244: "cmpdeci %0,%1" 245: [(set_attr "type" "compare")]) 246: 247: (define_insn "" 248: [(set (reg:CC_UNS 36) 249: (compare (match_operand:SI 0 "arith_operand" "d") 250: (match_operand:SI 1 "arith_operand" "d"))) 251: (set (match_dup 1) (minus:SI (match_dup 1) (const_int 1)))] 252: "0" 253: "cmpdeco %0,%1" 254: [(set_attr "type" "compare")]) 255: 256: ;; Templates to store result of condition. 257: ;; '1' is stored if condition is true. 258: ;; '0' is stored if condition is false. 259: ;; These should use predicate "general_operand", since 260: ;; gcc seems to be creating mem references which use these 261: ;; templates. 262: 263: (define_expand "seq" 264: [(set (match_operand:SI 0 "general_operand" "=d") 265: (eq:SI (match_dup 1) (const_int 0)))] 266: "" 267: " 268: { 269: operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1); 270: }") 271: 272: (define_expand "sne" 273: [(set (match_operand:SI 0 "general_operand" "=d") 274: (ne:SI (match_dup 1) (const_int 0)))] 275: "" 276: " 277: { 278: operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1); 279: }") 280: 281: (define_expand "sgt" 282: [(set (match_operand:SI 0 "general_operand" "=d") 283: (gt:SI (match_dup 1) (const_int 0)))] 284: "" 285: " 286: { 287: operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1); 288: }") 289: 290: (define_expand "sgtu" 291: [(set (match_operand:SI 0 "general_operand" "=d") 292: (gtu:SI (match_dup 1) (const_int 0)))] 293: "" 294: " 295: { 296: operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1); 297: }") 298: 299: (define_expand "slt" 300: [(set (match_operand:SI 0 "general_operand" "=d") 301: (lt:SI (match_dup 1) (const_int 0)))] 302: "" 303: " 304: { 305: operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1); 306: }") 307: 308: (define_expand "sltu" 309: [(set (match_operand:SI 0 "general_operand" "=d") 310: (ltu:SI (match_dup 1) (const_int 0)))] 311: "" 312: " 313: { 314: operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1); 315: }") 316: 317: (define_expand "sge" 318: [(set (match_operand:SI 0 "general_operand" "=d") 319: (ge:SI (match_dup 1) (const_int 0)))] 320: "" 321: " 322: { 323: operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1); 324: }") 325: 326: (define_expand "sgeu" 327: [(set (match_operand:SI 0 "general_operand" "=d") 328: (geu:SI (match_dup 1) (const_int 0)))] 329: "" 330: " 331: { 332: operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1); 333: }") 334: 335: (define_expand "sle" 336: [(set (match_operand:SI 0 "general_operand" "=d") 337: (le:SI (match_dup 1) (const_int 0)))] 338: "" 339: " 340: { 341: operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1); 342: }") 343: 344: (define_expand "sleu" 345: [(set (match_operand:SI 0 "general_operand" "=d") 346: (leu:SI (match_dup 1) (const_int 0)))] 347: "" 348: " 349: { 350: operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1); 351: }") 352: 353: (define_insn "" 354: [(set (match_operand:SI 0 "general_operand" "=d") 355: (match_operator:SI 1 "comparison_operator" [(reg:CC 36) (const_int 0)]))] 356: "" 357: "test%C1 %0" 358: [(set_attr "type" "compare")]) 359: 360: (define_insn "" 361: [(set (match_operand:SI 0 "general_operand" "=d") 362: (match_operator:SI 1 "comparison_operator" [(reg:CC_UNS 36) (const_int 0)]))] 363: "" 364: "test%C1 %0" 365: [(set_attr "type" "compare")]) 366: 367: ;; These control RTL generation for conditional jump insns 368: ;; and match them for register allocation. 369: 370: (define_expand "beq" 371: [(set (pc) 372: (if_then_else (eq (match_dup 1) 373: (const_int 0)) 374: (label_ref (match_operand 0 "" "")) 375: (pc)))] 376: "" 377: " 378: { operands[1] = gen_compare_reg (EQ, i960_compare_op0, i960_compare_op1); }") 379: 380: (define_expand "bne" 381: [(set (pc) 382: (if_then_else (ne (match_dup 1) 383: (const_int 0)) 384: (label_ref (match_operand 0 "" "")) 385: (pc)))] 386: "" 387: " 388: { operands[1] = gen_compare_reg (NE, i960_compare_op0, i960_compare_op1); }") 389: 390: (define_expand "bgt" 391: [(set (pc) 392: (if_then_else (gt (match_dup 1) 393: (const_int 0)) 394: (label_ref (match_operand 0 "" "")) 395: (pc)))] 396: "" 397: " 398: { operands[1] = gen_compare_reg (GT, i960_compare_op0, i960_compare_op1); }") 399: 400: (define_expand "bgtu" 401: [(set (pc) 402: (if_then_else (gtu (match_dup 1) 403: (const_int 0)) 404: (label_ref (match_operand 0 "" "")) 405: (pc)))] 406: "" 407: " 408: { operands[1] = gen_compare_reg (GTU, i960_compare_op0, i960_compare_op1); }") 409: 410: (define_expand "blt" 411: [(set (pc) 412: (if_then_else (lt (match_dup 1) 413: (const_int 0)) 414: (label_ref (match_operand 0 "" "")) 415: (pc)))] 416: "" 417: " 418: { operands[1] = gen_compare_reg (LT, i960_compare_op0, i960_compare_op1); }") 419: 420: (define_expand "bltu" 421: [(set (pc) 422: (if_then_else (ltu (match_dup 1) 423: (const_int 0)) 424: (label_ref (match_operand 0 "" "")) 425: (pc)))] 426: "" 427: " 428: { operands[1] = gen_compare_reg (LTU, i960_compare_op0, i960_compare_op1); }") 429: 430: (define_expand "bge" 431: [(set (pc) 432: (if_then_else (ge (match_dup 1) 433: (const_int 0)) 434: (label_ref (match_operand 0 "" "")) 435: (pc)))] 436: "" 437: " 438: { operands[1] = gen_compare_reg (GE, i960_compare_op0, i960_compare_op1); }") 439: 440: (define_expand "bgeu" 441: [(set (pc) 442: (if_then_else (geu (match_dup 1) 443: (const_int 0)) 444: (label_ref (match_operand 0 "" "")) 445: (pc)))] 446: "" 447: " 448: { operands[1] = gen_compare_reg (GEU, i960_compare_op0, i960_compare_op1); }") 449: 450: (define_expand "ble" 451: [(set (pc) 452: (if_then_else (le (match_dup 1) 453: (const_int 0)) 454: (label_ref (match_operand 0 "" "")) 455: (pc)))] 456: "" 457: " 458: { operands[1] = gen_compare_reg (LE, i960_compare_op0, i960_compare_op1); }") 459: 460: (define_expand "bleu" 461: [(set (pc) 462: (if_then_else (leu (match_dup 1) 463: (const_int 0)) 464: (label_ref (match_operand 0 "" "")) 465: (pc)))] 466: "" 467: " 468: { operands[1] = gen_compare_reg (LEU, i960_compare_op0, i960_compare_op1); }") 469: 470: ;; Now the normal branch insns (forward and reverse). 471: 472: (define_insn "" 473: [(set (pc) 474: (if_then_else (match_operator 0 "comparison_operator" 475: [(reg:CC 36) (const_int 0)]) 476: (label_ref (match_operand 1 "" "")) 477: (pc)))] 478: "" 479: "b%C0 %l1" 480: [(set_attr "type" "branch")]) 481: 482: (define_insn "" 483: [(set (pc) 484: (if_then_else (match_operator 0 "comparison_operator" 485: [(reg:CC 36) (const_int 0)]) 486: (pc) 487: (label_ref (match_operand 1 "" ""))))] 488: "" 489: "b%I0 %l1" 490: [(set_attr "type" "branch")]) 491: 492: (define_insn "" 493: [(set (pc) 494: (if_then_else (match_operator 0 "comparison_operator" 495: [(reg:CC_UNS 36) (const_int 0)]) 496: (label_ref (match_operand 1 "" "")) 497: (pc)))] 498: "" 499: "b%C0 %l1" 500: [(set_attr "type" "branch")]) 501: 502: (define_insn "" 503: [(set (pc) 504: (if_then_else (match_operator 0 "comparison_operator" 505: [(reg:CC_UNS 36) (const_int 0)]) 506: (pc) 507: (label_ref (match_operand 1 "" ""))))] 508: "" 509: "b%I0 %l1" 510: [(set_attr "type" "branch")]) 511: 512: (define_insn "" 513: [(set (pc) 514: (if_then_else 515: (match_operator 0 "comparison_operator" 516: [(match_operand:SI 1 "arith_operand" "d") 517: (match_operand:SI 2 "arith_operand" "dI")]) 518: (label_ref (match_operand 3 "" "")) 519: (pc)))] 520: "" 521: "cmp%S0%B0%R0 %2,%1,%l3" 522: [(set_attr "type" "branch")]) 523: 524: (define_insn "" 525: [(set (pc) 526: (if_then_else 527: (match_operator 0 "comparison_operator" 528: [(match_operand:SI 1 "arith_operand" "d") 529: (match_operand:SI 2 "arith_operand" "dI")]) 530: (pc) 531: (label_ref (match_operand 3 "" ""))))] 532: "" 533: "cmp%S0%B0%X0 %2,%1,%l3" 534: [(set_attr "type" "branch")]) 535: 536: ;; Normal move instructions. 537: ;; This code is based on the sparc machine description. 538: 539: (define_expand "movsi" 540: [(set (match_operand:SI 0 "general_operand" "") 541: (match_operand:SI 1 "general_operand" ""))] 542: "" 543: " 544: { 545: if (emit_move_sequence (operands, SImode)) 546: DONE; 547: }") 548: 549: ;; The store case can not be separate, because reload may convert a register 550: ;; to register move insn to a store (or load) insn without rerecognizing 551: ;; the insn. 552: 553: ;; The i960 does not have any store constant to memory instruction. However, 554: ;; the calling convention is defined so that the arg pointer when it is not 555: ;; overwise being used is zero. Thus, we can handle store zero to memory 556: ;; by storing an unused arg pointer. The arg pointer will be unused if 1.1.1.3 ! root 557: ;; current_function_args_size is zero and this is not a stdarg/varargs ! 558: ;; function. This value of the former variable is not valid until after ! 559: ;; all rtl generation is complete, including function inlining (because a ! 560: ;; function that doesn't need an arg pointer may be inlined into a function ! 561: ;; that does need an arg pointer), so we must also check that ! 562: ;; rtx_equal_function_value_matters is zero. 1.1 root 563: 564: (define_insn "" 565: [(set (match_operand:SI 0 "general_operand" "=d,d,d,m") 566: (match_operand:SI 1 "general_operand" "dI,i,m,dJ"))] 567: "(current_function_args_size == 0 1.1.1.3 ! root 568: && current_function_varargs == 0 ! 569: && current_function_stdarg == 0 1.1 root 570: && rtx_equal_function_value_matters == 0) 571: && (register_operand (operands[0], SImode) 572: || register_operand (operands[1], SImode) 573: || operands[1] == const0_rtx)" 574: "* 575: { 576: switch (which_alternative) 577: { 578: case 0: 579: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) 580: { 581: if (GET_CODE (operands[1]) == REG) 582: return \"lda (%1),%0\"; 583: else 584: return \"lda %1,%0\"; 585: } 586: return \"mov %1,%0\"; 587: case 1: 588: return i960_output_ldconst (operands[0], operands[1]); 589: case 2: 590: return \"ld %1,%0\"; 591: case 3: 592: if (operands[1] == const0_rtx) 593: return \"st g14,%0\"; 594: return \"st %1,%0\"; 595: } 596: }" 597: [(set_attr "type" "move,address,load,store") 598: (set_attr "length" "*,3,*,*")]) 599: 600: (define_insn "" 601: [(set (match_operand:SI 0 "general_operand" "=d,d,d,m") 602: (match_operand:SI 1 "general_operand" "dI,i,m,d"))] 603: "(current_function_args_size != 0 1.1.1.3 ! root 604: || current_function_varargs != 0 ! 605: || current_function_stdarg != 0 1.1 root 606: || rtx_equal_function_value_matters != 0) 607: && (register_operand (operands[0], SImode) 608: || register_operand (operands[1], SImode))" 609: "* 610: { 611: switch (which_alternative) 612: { 613: case 0: 614: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) 615: { 616: if (GET_CODE (operands[1]) == REG) 617: return \"lda (%1),%0\"; 618: else 619: return \"lda %1,%0\"; 620: } 621: return \"mov %1,%0\"; 622: case 1: 623: return i960_output_ldconst (operands[0], operands[1]); 624: case 2: 625: return \"ld %1,%0\"; 626: case 3: 627: return \"st %1,%0\"; 628: } 629: }" 630: [(set_attr "type" "move,address,load,store") 631: (set_attr "length" "*,3,*,*")]) 632: 633: (define_expand "movhi" 634: [(set (match_operand:HI 0 "general_operand" "") 635: (match_operand:HI 1 "general_operand" ""))] 636: "" 637: " 638: { 639: if (emit_move_sequence (operands, HImode)) 640: DONE; 641: }") 642: 643: ;; Special pattern for zero stores to memory for functions which don't use 644: ;; the arg pointer. 645: 646: ;; The store case can not be separate. See above. 647: (define_insn "" 648: [(set (match_operand:HI 0 "general_operand" "=d,d,d,m") 649: (match_operand:HI 1 "general_operand" "dI,i,m,dJ"))] 650: "(current_function_args_size == 0 1.1.1.3 ! root 651: && current_function_varargs == 0 ! 652: && current_function_stdarg == 0 1.1 root 653: && rtx_equal_function_value_matters == 0) 654: && (register_operand (operands[0], HImode) 655: || register_operand (operands[1], HImode) 656: || operands[1] == const0_rtx)" 657: "* 658: { 659: switch (which_alternative) 660: { 661: case 0: 662: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) 663: { 664: if (GET_CODE (operands[1]) == REG) 665: return \"lda (%1),%0\"; 666: else 667: return \"lda %1,%0\"; 668: } 669: return \"mov %1,%0\"; 670: case 1: 671: return i960_output_ldconst (operands[0], operands[1]); 672: case 2: 673: return \"ldos %1,%0\"; 674: case 3: 675: if (operands[1] == const0_rtx) 676: return \"stos g14,%0\"; 677: return \"stos %1,%0\"; 678: } 679: }" 680: [(set_attr "type" "move,misc,load,store") 681: (set_attr "length" "*,3,*,*")]) 682: 683: ;; The store case can not be separate. See above. 684: (define_insn "" 685: [(set (match_operand:HI 0 "general_operand" "=d,d,d,m") 686: (match_operand:HI 1 "general_operand" "dI,i,m,d"))] 687: "(current_function_args_size != 0 1.1.1.3 ! root 688: || current_function_varargs != 0 ! 689: || current_function_stdarg != 0 1.1 root 690: || rtx_equal_function_value_matters != 0) 691: && (register_operand (operands[0], HImode) 692: || register_operand (operands[1], HImode))" 693: "* 694: { 695: switch (which_alternative) 696: { 697: case 0: 698: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) 699: { 700: if (GET_CODE (operands[1]) == REG) 701: return \"lda (%1),%0\"; 702: else 703: return \"lda %1,%0\"; 704: } 705: return \"mov %1,%0\"; 706: case 1: 707: return i960_output_ldconst (operands[0], operands[1]); 708: case 2: 709: return \"ldos %1,%0\"; 710: case 3: 711: return \"stos %1,%0\"; 712: } 713: }" 714: [(set_attr "type" "move,misc,load,store") 715: (set_attr "length" "*,3,*,*")]) 716: 717: (define_expand "movqi" 718: [(set (match_operand:QI 0 "general_operand" "") 719: (match_operand:QI 1 "general_operand" ""))] 720: "" 721: " 722: { 723: if (emit_move_sequence (operands, QImode)) 724: DONE; 725: }") 726: 727: ;; The store case can not be separate. See comment above. 728: (define_insn "" 729: [(set (match_operand:QI 0 "general_operand" "=d,d,d,m") 730: (match_operand:QI 1 "general_operand" "dI,i,m,dJ"))] 731: "(current_function_args_size == 0 1.1.1.3 ! root 732: && current_function_varargs == 0 ! 733: && current_function_stdarg == 0 1.1 root 734: && rtx_equal_function_value_matters == 0) 735: && (register_operand (operands[0], QImode) 736: || register_operand (operands[1], QImode) 737: || operands[1] == const0_rtx)" 738: "* 739: { 740: switch (which_alternative) 741: { 742: case 0: 743: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) 744: { 745: if (GET_CODE (operands[1]) == REG) 746: return \"lda (%1),%0\"; 747: else 748: return \"lda %1,%0\"; 749: } 750: return \"mov %1,%0\"; 751: case 1: 752: return i960_output_ldconst (operands[0], operands[1]); 753: case 2: 754: return \"ldob %1,%0\"; 755: case 3: 756: if (operands[1] == const0_rtx) 757: return \"stob g14,%0\"; 758: return \"stob %1,%0\"; 759: } 760: }" 761: [(set_attr "type" "move,misc,load,store") 762: (set_attr "length" "*,3,*,*")]) 763: 764: ;; The store case can not be separate. See comment above. 765: (define_insn "" 766: [(set (match_operand:QI 0 "general_operand" "=d,d,d,m") 767: (match_operand:QI 1 "general_operand" "dI,i,m,d"))] 768: "(current_function_args_size != 0 1.1.1.3 ! root 769: || current_function_varargs != 0 ! 770: || current_function_stdarg != 0 1.1 root 771: || rtx_equal_function_value_matters != 0) 772: && (register_operand (operands[0], QImode) 773: || register_operand (operands[1], QImode))" 774: "* 775: { 776: switch (which_alternative) 777: { 778: case 0: 779: if (i960_last_insn_type == I_TYPE_REG && TARGET_C_SERIES) 780: { 781: if (GET_CODE (operands[1]) == REG) 782: return \"lda (%1),%0\"; 783: else 784: return \"lda %1,%0\"; 785: } 786: return \"mov %1,%0\"; 787: case 1: 788: return i960_output_ldconst (operands[0], operands[1]); 789: case 2: 790: return \"ldob %1,%0\"; 791: case 3: 792: return \"stob %1,%0\"; 793: } 794: }" 795: [(set_attr "type" "move,misc,load,store") 796: (set_attr "length" "*,3,*,*")]) 797: 798: (define_expand "movdi" 799: [(set (match_operand:DI 0 "general_operand" "") 800: (match_operand:DI 1 "general_operand" ""))] 801: "" 802: " 803: { 804: if (emit_move_sequence (operands, DImode)) 805: DONE; 806: }") 807: 808: ;; The store case can not be separate. See comment above. 809: (define_insn "" 1.1.1.3 ! root 810: [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,m,o") ! 811: (match_operand:DI 1 "general_operand" "d,I,i,m,d,J"))] 1.1 root 812: "(current_function_args_size == 0 1.1.1.3 ! root 813: && current_function_varargs == 0 ! 814: && current_function_stdarg == 0 1.1 root 815: && rtx_equal_function_value_matters == 0) 816: && (register_operand (operands[0], DImode) 817: || register_operand (operands[1], DImode) 818: || operands[1] == const0_rtx)" 819: "* 820: { 821: switch (which_alternative) 822: { 823: case 0: 824: case 1: 825: case 3: 826: case 4: 1.1.1.3 ! root 827: return i960_output_move_double (operands[0], operands[1]); ! 828: case 2: ! 829: return i960_output_ldconst (operands[0], operands[1]); ! 830: case 5: 1.1 root 831: operands[1] = adj_offsettable_operand (operands[0], 4); 832: return \"st g14,%0\;st g14,%1\"; 833: } 834: }" 1.1.1.3 ! root 835: [(set_attr "type" "move,move,load,load,store,store")]) 1.1 root 836: 837: ;; The store case can not be separate. See comment above. 838: (define_insn "" 1.1.1.3 ! root 839: [(set (match_operand:DI 0 "general_operand" "=d,d,d,d,m") ! 840: (match_operand:DI 1 "general_operand" "d,I,i,m,d"))] 1.1 root 841: "(current_function_args_size != 0 1.1.1.3 ! root 842: || current_function_varargs != 0 ! 843: || current_function_stdarg != 0 1.1 root 844: || rtx_equal_function_value_matters != 0) 845: && (register_operand (operands[0], DImode) 846: || register_operand (operands[1], DImode))" 847: "* 848: { 849: switch (which_alternative) 850: { 851: case 0: 852: case 1: 853: case 3: 1.1.1.3 ! root 854: case 4: ! 855: return i960_output_move_double (operands[0], operands[1]); ! 856: case 2: ! 857: return i960_output_ldconst (operands[0], operands[1]); 1.1 root 858: } 859: }" 1.1.1.3 ! root 860: [(set_attr "type" "move,move,load,load,store")]) ! 861: ! 862: (define_insn "*store_unaligned_di_reg" ! 863: [(set (match_operand:DI 0 "memory_operand" "=m") ! 864: (match_operand:DI 1 "register_operand" "d")) ! 865: (clobber (match_scratch:SI 2 "=&d"))] ! 866: "" ! 867: "* ! 868: { ! 869: operands[3] = gen_rtx (MEM, word_mode, operands[2]); ! 870: operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD); ! 871: return \"lda %0,%2\;st %1,%3\;st %D1,%4\"; ! 872: }" ! 873: [(set_attr "type" "store")]) 1.1 root 874: 875: (define_expand "movti" 876: [(set (match_operand:TI 0 "general_operand" "") 877: (match_operand:TI 1 "general_operand" ""))] 878: "" 879: " 880: { 881: if (emit_move_sequence (operands, TImode)) 882: DONE; 883: }") 884: 885: ;; The store case can not be separate. See comment above. 886: (define_insn "" 1.1.1.3 ! root 887: [(set (match_operand:TI 0 "general_operand" "=d,d,d,d,m,o") ! 888: (match_operand:TI 1 "general_operand" "d,I,i,m,d,J"))] 1.1 root 889: "(current_function_args_size == 0 1.1.1.3 ! root 890: && current_function_varargs == 0 ! 891: && current_function_stdarg == 0 1.1 root 892: && rtx_equal_function_value_matters == 0) 893: && (register_operand (operands[0], TImode) 894: || register_operand (operands[1], TImode) 895: || operands[1] == const0_rtx)" 896: "* 897: { 898: switch (which_alternative) 899: { 900: case 0: 901: case 1: 902: case 3: 903: case 4: 1.1.1.3 ! root 904: return i960_output_move_quad (operands[0], operands[1]); ! 905: case 2: ! 906: return i960_output_ldconst (operands[0], operands[1]); ! 907: case 5: 1.1 root 908: operands[1] = adj_offsettable_operand (operands[0], 4); 909: operands[2] = adj_offsettable_operand (operands[0], 8); 910: operands[3] = adj_offsettable_operand (operands[0], 12); 911: return \"st g14,%0\;st g14,%1\;st g14,%2\;st g14,%3\"; 912: } 913: }" 1.1.1.3 ! root 914: [(set_attr "type" "move,move,load,load,store,store")]) 1.1 root 915: 916: ;; The store case can not be separate. See comment above. 917: (define_insn "" 1.1.1.3 ! root 918: [(set (match_operand:TI 0 "general_operand" "=d,d,d,d,m") ! 919: (match_operand:TI 1 "general_operand" "d,I,i,m,d"))] 1.1 root 920: "(current_function_args_size != 0 1.1.1.3 ! root 921: || current_function_varargs != 0 ! 922: || current_function_stdarg != 0 1.1 root 923: || rtx_equal_function_value_matters != 0) 924: && (register_operand (operands[0], TImode) 925: || register_operand (operands[1], TImode))" 926: "* 927: { 928: switch (which_alternative) 929: { 930: case 0: 931: case 1: 932: case 3: 1.1.1.3 ! root 933: case 4: ! 934: return i960_output_move_quad (operands[0], operands[1]); ! 935: case 2: ! 936: return i960_output_ldconst (operands[0], operands[1]); 1.1 root 937: } 938: }" 1.1.1.3 ! root 939: [(set_attr "type" "move,move,load,load,store")]) ! 940: ! 941: (define_insn "*store_unaligned_ti_reg" ! 942: [(set (match_operand:TI 0 "memory_operand" "=m") ! 943: (match_operand:TI 1 "register_operand" "d")) ! 944: (clobber (match_scratch:SI 2 "=&d"))] ! 945: "" ! 946: "* ! 947: { ! 948: operands[3] = gen_rtx (MEM, word_mode, operands[2]); ! 949: operands[4] = adj_offsettable_operand (operands[3], UNITS_PER_WORD); ! 950: operands[5] = adj_offsettable_operand (operands[4], UNITS_PER_WORD); ! 951: operands[6] = adj_offsettable_operand (operands[5], UNITS_PER_WORD); ! 952: return \"lda %0,%2\;st %1,%3\;st %D1,%4\;st %E1,%5\;st %F1,%6\"; ! 953: }" ! 954: [(set_attr "type" "store")]) 1.1 root 955: 956: (define_expand "store_multiple" 957: [(set (match_operand:SI 0 "" "") ;;- dest 958: (match_operand:SI 1 "" "")) ;;- src 959: (use (match_operand:SI 2 "" ""))] ;;- nregs 960: "" 961: " 962: { 963: int regno; 964: int count; 965: rtx from; 966: int i; 967: 968: if (GET_CODE (operands[0]) != MEM 969: || GET_CODE (operands[1]) != REG 970: || GET_CODE (operands[2]) != CONST_INT) 971: FAIL; 972: 973: count = INTVAL (operands[2]); 974: if (count > 12) 975: FAIL; 976: 977: regno = REGNO (operands[1]); 978: from = memory_address (SImode, XEXP (operands[0], 0)); 979: while (count >= 4 && ((regno & 3) == 0)) 980: { 981: emit_insn (gen_rtx (SET, VOIDmode, 982: gen_rtx (MEM, TImode, from), 983: gen_rtx (REG, TImode, regno))); 984: count -= 4; 985: regno += 4; 986: from = memory_address (TImode, plus_constant (from, 16)); 987: } 988: while (count >= 2 && ((regno & 1) == 0)) 989: { 990: emit_insn (gen_rtx (SET, VOIDmode, 991: gen_rtx (MEM, DImode, from), 992: gen_rtx (REG, DImode, regno))); 993: count -= 2; 994: regno += 2; 995: from = memory_address (DImode, plus_constant (from, 8)); 996: } 997: while (count > 0) 998: { 999: emit_insn (gen_rtx (SET, VOIDmode, 1000: gen_rtx (MEM, SImode, from), 1001: gen_rtx (REG, SImode, regno))); 1002: count -= 1; 1003: regno += 1; 1004: from = memory_address (SImode, plus_constant (from, 4)); 1005: } 1006: DONE; 1007: }") 1008: 1009: ;; Floating point move insns 1010: 1011: (define_expand "movdf" 1012: [(set (match_operand:DF 0 "general_operand" "") 1013: (match_operand:DF 1 "fpmove_src_operand" ""))] 1014: "" 1015: " 1016: { 1017: if (emit_move_sequence (operands, DFmode)) 1018: DONE; 1019: }") 1020: 1021: (define_insn "" 1022: [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m,o") 1023: (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d,G"))] 1024: "(current_function_args_size == 0 1.1.1.3 ! root 1025: && current_function_varargs == 0 ! 1026: && current_function_stdarg == 0 1.1 root 1027: && rtx_equal_function_value_matters == 0) 1028: && (register_operand (operands[0], DFmode) 1029: || register_operand (operands[1], DFmode) 1030: || operands[1] == CONST0_RTX (DFmode))" 1031: "* 1032: { 1033: switch (which_alternative) 1034: { 1035: case 0: 1036: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) 1037: return \"movrl %1,%0\"; 1038: else 1039: return \"movl %1,%0\"; 1040: case 1: 1041: return \"movrl %1,%0\"; 1042: case 2: 1043: return i960_output_ldconst (operands[0], operands[1]); 1044: case 3: 1045: return \"ldl %1,%0\"; 1046: case 4: 1047: return \"stl %1,%0\"; 1048: case 5: 1049: operands[1] = adj_offsettable_operand (operands[0], 4); 1050: return \"st g14,%0\;st g14,%1\"; 1051: } 1052: }" 1053: [(set_attr "type" "move,move,load,fpload,fpstore,fpstore")]) 1054: 1055: (define_insn "" 1056: [(set (match_operand:DF 0 "general_operand" "=r,*f,d,d,m") 1057: (match_operand:DF 1 "fpmove_src_operand" "r,GH,F,m,d"))] 1058: "(current_function_args_size != 0 1.1.1.3 ! root 1059: || current_function_varargs != 0 ! 1060: || current_function_stdarg != 0 1.1 root 1061: || rtx_equal_function_value_matters != 0) 1062: && (register_operand (operands[0], DFmode) 1063: || register_operand (operands[1], DFmode))" 1064: "* 1065: { 1066: switch (which_alternative) 1067: { 1068: case 0: 1069: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) 1070: return \"movrl %1,%0\"; 1071: else 1072: return \"movl %1,%0\"; 1073: case 1: 1074: return \"movrl %1,%0\"; 1075: case 2: 1076: return i960_output_ldconst (operands[0], operands[1]); 1077: case 3: 1078: return \"ldl %1,%0\"; 1079: case 4: 1080: return \"stl %1,%0\"; 1081: } 1082: }" 1083: [(set_attr "type" "move,move,load,fpload,fpstore")]) 1084: 1085: (define_expand "movsf" 1086: [(set (match_operand:SF 0 "general_operand" "") 1087: (match_operand:SF 1 "fpmove_src_operand" ""))] 1088: "" 1089: " 1090: { 1091: if (emit_move_sequence (operands, SFmode)) 1092: DONE; 1093: }") 1094: 1095: (define_insn "" 1096: [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m") 1097: (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,dG"))] 1098: "(current_function_args_size == 0 1.1.1.3 ! root 1099: && current_function_varargs == 0 ! 1100: && current_function_stdarg == 0 1.1 root 1101: && rtx_equal_function_value_matters == 0) 1102: && (register_operand (operands[0], SFmode) 1103: || register_operand (operands[1], SFmode) 1104: || operands[1] == CONST0_RTX (SFmode))" 1105: "* 1106: { 1107: switch (which_alternative) 1108: { 1109: case 0: 1110: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) 1111: return \"movr %1,%0\"; 1112: else 1113: return \"mov %1,%0\"; 1114: case 1: 1115: return \"movr %1,%0\"; 1116: case 2: 1117: return i960_output_ldconst (operands[0], operands[1]); 1118: case 3: 1119: return \"ld %1,%0\"; 1120: case 4: 1121: if (operands[1] == CONST0_RTX (SFmode)) 1122: return \"st g14,%0\"; 1123: return \"st %1,%0\"; 1124: } 1125: }" 1126: [(set_attr "type" "move,move,load,fpload,fpstore")]) 1127: 1128: (define_insn "" 1129: [(set (match_operand:SF 0 "general_operand" "=r,*f,d,d,m") 1130: (match_operand:SF 1 "fpmove_src_operand" "r,GH,F,m,d"))] 1131: "(current_function_args_size != 0 1.1.1.3 ! root 1132: || current_function_varargs != 0 ! 1133: || current_function_stdarg != 0 1.1 root 1134: || rtx_equal_function_value_matters != 0) 1135: && (register_operand (operands[0], SFmode) 1136: || register_operand (operands[1], SFmode))" 1137: "* 1138: { 1139: switch (which_alternative) 1140: { 1141: case 0: 1142: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) 1143: return \"movr %1,%0\"; 1144: else 1145: return \"mov %1,%0\"; 1146: case 1: 1147: return \"movr %1,%0\"; 1148: case 2: 1149: return i960_output_ldconst (operands[0], operands[1]); 1150: case 3: 1151: return \"ld %1,%0\"; 1152: case 4: 1153: return \"st %1,%0\"; 1154: } 1155: }" 1156: [(set_attr "type" "move,move,load,fpload,fpstore")]) 1157: 1158: ;; Mixed-mode moves with sign and zero-extension. 1159: 1160: ;; Note that the one starting from HImode comes before those for QImode 1161: ;; so that a constant operand will match HImode, not QImode. 1162: 1163: (define_expand "extendhisi2" 1164: [(set (match_operand:SI 0 "register_operand" "") 1165: (sign_extend:SI 1166: (match_operand:HI 1 "nonimmediate_operand" "")))] 1167: "" 1168: " 1169: { 1170: if (GET_CODE (operand1) == REG 1171: || (GET_CODE (operand1) == SUBREG 1172: && GET_CODE (XEXP (operand1, 0)) == REG)) 1173: { 1174: rtx temp = gen_reg_rtx (SImode); 1175: rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16); 1176: int op1_subreg_word = 0; 1177: 1178: if (GET_CODE (operand1) == SUBREG) 1179: { 1180: op1_subreg_word = SUBREG_WORD (operand1); 1181: operand1 = SUBREG_REG (operand1); 1182: } 1183: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); 1184: 1185: emit_insn (gen_ashlsi3 (temp, operand1, shift_16)); 1186: emit_insn (gen_ashrsi3 (operand0, temp, shift_16)); 1187: DONE; 1188: } 1189: }") 1190: 1191: (define_insn "" 1192: [(set (match_operand:SI 0 "register_operand" "=d") 1193: (sign_extend:SI (match_operand:HI 1 "memory_operand" "m")))] 1194: "" 1195: "ldis %1,%0" 1196: [(set_attr "type" "load")]) 1197: 1198: (define_expand "extendqisi2" 1199: [(set (match_operand:SI 0 "register_operand" "") 1200: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] 1201: "" 1202: " 1203: { 1204: if (GET_CODE (operand1) == REG 1205: || (GET_CODE (operand1) == SUBREG 1206: && GET_CODE (XEXP (operand1, 0)) == REG)) 1207: { 1208: rtx temp = gen_reg_rtx (SImode); 1209: rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); 1210: int op1_subreg_word = 0; 1211: 1212: if (GET_CODE (operand1) == SUBREG) 1213: { 1214: op1_subreg_word = SUBREG_WORD (operand1); 1215: operand1 = SUBREG_REG (operand1); 1216: } 1217: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word), 1218: 1219: emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); 1220: emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); 1221: DONE; 1222: } 1223: }") 1224: 1225: (define_insn "" 1226: [(set (match_operand:SI 0 "register_operand" "=d") 1227: (sign_extend:SI (match_operand:QI 1 "memory_operand" "m")))] 1228: "" 1229: "ldib %1,%0" 1230: [(set_attr "type" "load")]) 1231: 1232: (define_expand "extendqihi2" 1233: [(set (match_operand:HI 0 "register_operand" "") 1234: (sign_extend:HI 1235: (match_operand:QI 1 "nonimmediate_operand" "")))] 1236: "" 1237: " 1238: { 1239: if (GET_CODE (operand1) == REG 1240: || (GET_CODE (operand1) == SUBREG 1241: && GET_CODE (XEXP (operand1, 0)) == REG)) 1242: { 1243: rtx temp = gen_reg_rtx (SImode); 1244: rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); 1245: int op0_subreg_word = 0; 1246: int op1_subreg_word = 0; 1247: 1248: if (GET_CODE (operand1) == SUBREG) 1249: { 1250: op1_subreg_word = SUBREG_WORD (operand1); 1251: operand1 = SUBREG_REG (operand1); 1252: } 1253: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); 1254: 1255: if (GET_CODE (operand0) == SUBREG) 1256: { 1257: op0_subreg_word = SUBREG_WORD (operand0); 1258: operand0 = SUBREG_REG (operand0); 1259: } 1260: if (GET_MODE (operand0) != SImode) 1261: operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word); 1262: 1263: emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); 1264: emit_insn (gen_ashrsi3 (operand0, temp, shift_24)); 1265: DONE; 1266: } 1267: }") 1268: 1269: (define_insn "" 1270: [(set (match_operand:HI 0 "register_operand" "=d") 1271: (sign_extend:HI (match_operand:QI 1 "memory_operand" "m")))] 1272: "" 1273: "ldib %1,%0" 1274: [(set_attr "type" "load")]) 1275: 1276: (define_expand "zero_extendhisi2" 1277: [(set (match_operand:SI 0 "register_operand" "") 1278: (zero_extend:SI 1279: (match_operand:HI 1 "nonimmediate_operand" "")))] 1280: "" 1281: " 1282: { 1283: if (GET_CODE (operand1) == REG 1284: || (GET_CODE (operand1) == SUBREG 1285: && GET_CODE (XEXP (operand1, 0)) == REG)) 1286: { 1287: rtx temp = gen_reg_rtx (SImode); 1288: rtx shift_16 = gen_rtx (CONST_INT, VOIDmode, 16); 1289: int op1_subreg_word = 0; 1290: 1291: if (GET_CODE (operand1) == SUBREG) 1292: { 1293: op1_subreg_word = SUBREG_WORD (operand1); 1294: operand1 = SUBREG_REG (operand1); 1295: } 1296: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); 1297: 1298: emit_insn (gen_ashlsi3 (temp, operand1, shift_16)); 1299: emit_insn (gen_lshrsi3 (operand0, temp, shift_16)); 1300: DONE; 1301: } 1302: }") 1303: 1304: (define_insn "" 1305: [(set (match_operand:SI 0 "register_operand" "=d") 1306: (zero_extend:SI (match_operand:HI 1 "memory_operand" "m")))] 1307: "" 1308: "ldos %1,%0" 1309: [(set_attr "type" "load")]) 1310: 1311: ;; Using shifts here generates much better code than doing an `and 255'. 1312: ;; This is mainly because the `and' requires loading the constant separately, 1313: ;; the constant is likely to get optimized, and then the compiler can't 1314: ;; optimize the `and' because it doesn't know that one operand is a constant. 1315: 1316: (define_expand "zero_extendqisi2" 1317: [(set (match_operand:SI 0 "register_operand" "") 1318: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] 1319: "" 1320: " 1321: { 1322: if (GET_CODE (operand1) == REG 1323: || (GET_CODE (operand1) == SUBREG 1324: && GET_CODE (XEXP (operand1, 0)) == REG)) 1325: { 1326: rtx temp = gen_reg_rtx (SImode); 1327: rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); 1328: int op1_subreg_word = 0; 1329: 1330: if (GET_CODE (operand1) == SUBREG) 1331: { 1332: op1_subreg_word = SUBREG_WORD (operand1); 1333: operand1 = SUBREG_REG (operand1); 1334: } 1335: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); 1336: 1337: emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); 1338: emit_insn (gen_lshrsi3 (operand0, temp, shift_24)); 1339: DONE; 1340: } 1341: }") 1342: 1343: (define_insn "" 1344: [(set (match_operand:SI 0 "register_operand" "=d") 1345: (zero_extend:SI (match_operand:QI 1 "memory_operand" "m")))] 1346: "" 1347: "ldob %1,%0" 1348: [(set_attr "type" "load")]) 1349: 1350: (define_expand "zero_extendqihi2" 1351: [(set (match_operand:HI 0 "register_operand" "") 1352: (zero_extend:HI 1353: (match_operand:QI 1 "nonimmediate_operand" "")))] 1354: "" 1355: " 1356: { 1357: if (GET_CODE (operand1) == REG 1358: || (GET_CODE (operand1) == SUBREG 1359: && GET_CODE (XEXP (operand1, 0)) == REG)) 1360: { 1361: rtx temp = gen_reg_rtx (SImode); 1362: rtx shift_24 = gen_rtx (CONST_INT, VOIDmode, 24); 1363: int op0_subreg_word = 0; 1364: int op1_subreg_word = 0; 1365: 1366: if (GET_CODE (operand1) == SUBREG) 1367: { 1368: op1_subreg_word = SUBREG_WORD (operand1); 1369: operand1 = SUBREG_REG (operand1); 1370: } 1371: operand1 = gen_rtx (SUBREG, SImode, operand1, op1_subreg_word); 1372: 1373: if (GET_CODE (operand0) == SUBREG) 1374: { 1375: op0_subreg_word = SUBREG_WORD (operand0); 1376: operand0 = SUBREG_REG (operand0); 1377: } 1378: if (GET_MODE (operand0) != SImode) 1379: operand0 = gen_rtx (SUBREG, SImode, operand0, op0_subreg_word); 1380: 1381: emit_insn (gen_ashlsi3 (temp, operand1, shift_24)); 1382: emit_insn (gen_lshrsi3 (operand0, temp, shift_24)); 1383: DONE; 1384: } 1385: }") 1386: 1387: (define_insn "" 1388: [(set (match_operand:HI 0 "register_operand" "=d") 1389: (zero_extend:HI (match_operand:QI 1 "memory_operand" "m")))] 1390: "" 1391: "ldob %1,%0" 1392: [(set_attr "type" "load")]) 1393: 1394: ;; Conversions between float and double. 1395: 1396: (define_insn "extendsfdf2" 1397: [(set (match_operand:DF 0 "register_operand" "=*f,d") 1398: (float_extend:DF (match_operand:SF 1 "fp_arith_operand" "dGH,fGH")))] 1399: "TARGET_NUMERICS" 1400: "@ 1401: movr %1,%0 1402: movrl %1,%0" 1403: [(set_attr "type" "fpmove")]) 1404: 1405: (define_insn "truncdfsf2" 1406: [(set (match_operand:SF 0 "register_operand" "=d") 1407: (float_truncate:SF 1408: (match_operand:DF 1 "fp_arith_operand" "fGH")))] 1409: "TARGET_NUMERICS" 1410: "movr %1,%0" 1411: [(set_attr "type" "fpmove")]) 1412: 1413: ;; Conversion between fixed point and floating point. 1414: 1415: (define_insn "floatsidf2" 1416: [(set (match_operand:DF 0 "register_operand" "=f") 1417: (float:DF (match_operand:SI 1 "register_operand" "d")))] 1418: "TARGET_NUMERICS" 1419: "cvtir %1,%0" 1420: [(set_attr "type" "fpcvt")]) 1421: 1422: (define_insn "floatsisf2" 1423: [(set (match_operand:SF 0 "register_operand" "=d*f") 1424: (float:SF (match_operand:SI 1 "register_operand" "d")))] 1425: "TARGET_NUMERICS" 1426: "cvtir %1,%0" 1427: [(set_attr "type" "fpcvt")]) 1428: 1429: ;; Convert a float to an actual integer. 1430: ;; Truncation is performed as part of the conversion. 1431: ;; The i960 requires conversion from DFmode to DImode to make 1432: ;; unsigned conversions work properly. 1433: 1434: (define_insn "fixuns_truncdfdi2" 1435: [(set (match_operand:DI 0 "register_operand" "=d") 1436: (unsigned_fix:DI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))] 1437: "TARGET_NUMERICS" 1438: "cvtzril %1,%0" 1439: [(set_attr "type" "fpcvt")]) 1440: 1441: (define_insn "fixuns_truncsfdi2" 1442: [(set (match_operand:DI 0 "register_operand" "=d") 1443: (unsigned_fix:DI (fix:SF (match_operand:SF 1 "fp_arith_operand" "fGH"))))] 1444: "TARGET_NUMERICS" 1445: "cvtzril %1,%0" 1446: [(set_attr "type" "fpcvt")]) 1447: 1448: (define_insn "fix_truncdfsi2" 1449: [(set (match_operand:SI 0 "register_operand" "=d") 1450: (fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" "fGH"))))] 1451: "TARGET_NUMERICS" 1452: "cvtzri %1,%0" 1453: [(set_attr "type" "fpcvt")]) 1454: 1455: (define_expand "fixuns_truncdfsi2" 1456: [(set (match_operand:SI 0 "register_operand" "") 1457: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "fp_arith_operand" ""))))] 1458: "TARGET_NUMERICS" 1459: " 1460: { 1461: rtx temp = gen_reg_rtx (DImode); 1462: emit_insn (gen_rtx (SET, VOIDmode, temp, 1463: gen_rtx (UNSIGNED_FIX, DImode, 1464: gen_rtx (FIX, DFmode, operands[1])))); 1465: emit_insn (gen_rtx (SET, VOIDmode, operands[0], 1466: gen_rtx (SUBREG, SImode, temp, 0))); 1467: DONE; 1468: }") 1469: 1470: (define_insn "fix_truncsfsi2" 1471: [(set (match_operand:SI 0 "register_operand" "=d") 1472: (fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" "dfGH"))))] 1473: "TARGET_NUMERICS" 1474: "cvtzri %1,%0" 1475: [(set_attr "type" "fpcvt")]) 1476: 1477: (define_expand "fixuns_truncsfsi2" 1478: [(set (match_operand:SI 0 "register_operand" "") 1479: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "fp_arith_operand" ""))))] 1480: "TARGET_NUMERICS" 1481: " 1482: { 1483: rtx temp = gen_reg_rtx (DImode); 1484: emit_insn (gen_rtx (SET, VOIDmode, temp, 1485: gen_rtx (UNSIGNED_FIX, DImode, 1486: gen_rtx (FIX, SFmode, operands[1])))); 1487: emit_insn (gen_rtx (SET, VOIDmode, operands[0], 1488: gen_rtx (SUBREG, SImode, temp, 0))); 1489: DONE; 1490: }") 1491: 1492: ;; Arithmetic instructions. 1493: 1494: (define_insn "subsi3" 1495: [(set (match_operand:SI 0 "register_operand" "=d") 1496: (minus:SI (match_operand:SI 1 "arith_operand" "dI") 1497: (match_operand:SI 2 "arith_operand" "dI")))] 1498: "" 1499: "subo %2,%1,%0") 1500: 1501: ;; Try to generate an lda instruction when it would be faster than an 1502: ;; add instruction. 1503: ;; Some assemblers apparently won't accept two addresses added together. 1504: 1505: (define_insn "" 1506: [(set (match_operand:SI 0 "register_operand" "=d,d,d") 1507: (plus:SI (match_operand:SI 1 "arith32_operand" "%dn,i,dn") 1508: (match_operand:SI 2 "arith32_operand" "dn,dn,i")))] 1509: "(TARGET_C_SERIES) && (CONSTANT_P (operands[1]) || CONSTANT_P (operands[2]))" 1510: "* 1511: { 1512: if (GET_CODE (operands[1]) == CONST_INT) 1513: { 1514: rtx tmp = operands[1]; 1515: operands[1] = operands[2]; 1516: operands[2] = tmp; 1517: } 1518: if (GET_CODE (operands[2]) == CONST_INT 1519: && GET_CODE (operands[1]) == REG 1520: && i960_last_insn_type != I_TYPE_REG) 1521: { 1522: if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) > -32) 1523: return \"subo %n2,%1,%0\"; 1524: else if (INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) < 32) 1525: return \"addo %1,%2,%0\"; 1526: } 1527: if (CONSTANT_P (operands[1])) 1528: return \"lda %1+%2,%0\"; 1529: return \"lda %2(%1),%0\"; 1530: }") 1531: 1532: (define_insn "addsi3" 1533: [(set (match_operand:SI 0 "register_operand" "=d") 1534: (plus:SI (match_operand:SI 1 "signed_arith_operand" "%dI") 1535: (match_operand:SI 2 "signed_arith_operand" "dIK")))] 1536: "" 1537: "* 1538: { 1539: if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 1540: return \"subo %n2,%1,%0\"; 1541: if (i960_bypass (insn, operands[1], operands[2], 0)) 1542: return \"addo %2,%1,%0\"; 1543: return \"addo %1,%2,%0\"; 1544: }") 1545: 1546: (define_insn "mulsi3" 1547: [(set (match_operand:SI 0 "register_operand" "=d") 1548: (mult:SI (match_operand:SI 1 "arith_operand" "%dI") 1549: (match_operand:SI 2 "arith_operand" "dI")))] 1550: "" 1551: "* 1552: { 1553: if (i960_bypass (insn, operands[1], operands[2], 0)) 1554: return \"mulo %2,%1,%0\"; 1555: return \"mulo %1,%2,%0\"; 1556: }" 1557: [(set_attr "type" "mult")]) 1558: 1559: (define_insn "umulsidi3" 1560: [(set (match_operand:DI 0 "register_operand" "=d") 1561: (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d")) 1562: (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))] 1563: "" 1564: "* 1565: { 1566: if (i960_bypass (insn, operands[1], operands[2], 0)) 1567: return \"emul %2,%1,%0\"; 1568: return \"emul %1,%2,%0\"; 1569: }" 1570: [(set_attr "type" "mult")]) 1571: 1572: (define_insn "" 1573: [(set (match_operand:DI 0 "register_operand" "=d") 1574: (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%d")) 1575: (match_operand:SI 2 "literal" "I")))] 1576: "" 1577: "* 1578: { 1579: if (i960_bypass (insn, operands[1], operands[2], 0)) 1580: return \"emul %2,%1,%0\"; 1581: return \"emul %1,%2,%0\"; 1582: }" 1583: [(set_attr "type" "mult")]) 1584: 1585: ;; This goes after the move/add/sub/mul instructions 1586: ;; because those instructions are better when they apply. 1587: 1588: (define_insn "" 1589: [(set (match_operand:SI 0 "register_operand" "=d") 1590: (match_operand:SI 1 "address_operand" "p"))] 1591: "" 1592: "lda %a1,%0" 1593: [(set_attr "type" "load")]) 1594: 1595: ;; This will never be selected because of an "optimization" that GCC does. 1596: ;; It always converts divides by a power of 2 into a sequence of instructions 1597: ;; that does a right shift, and then corrects the result if it was negative. 1598: 1599: ;; (define_insn "" 1600: ;; [(set (match_operand:SI 0 "register_operand" "=d") 1601: ;; (div:SI (match_operand:SI 1 "arith_operand" "dI") 1602: ;; (match_operand:SI 2 "power2_operand" "nI")))] 1603: ;; "" 1604: ;; "*{ 1605: ;; operands[2] = gen_rtx(CONST_INT, VOIDmode,bitpos (INTVAL (operands[2]))); 1606: ;; return \"shrdi %2,%1,%0\"; 1607: ;; }" 1608: 1609: (define_insn "divsi3" 1610: [(set (match_operand:SI 0 "register_operand" "=d") 1611: (div:SI (match_operand:SI 1 "arith_operand" "dI") 1612: (match_operand:SI 2 "arith_operand" "dI")))] 1613: "" 1614: "divi %2,%1,%0" 1615: [(set_attr "type" "div")]) 1616: 1617: (define_insn "udivsi3" 1618: [(set (match_operand:SI 0 "register_operand" "=d") 1619: (udiv:SI (match_operand:SI 1 "arith_operand" "dI") 1620: (match_operand:SI 2 "arith_operand" "dI")))] 1621: "" 1622: "divo %2,%1,%0" 1623: [(set_attr "type" "div")]) 1624: 1625: ;; We must use `remi' not `modi' here, to ensure that `%' has the effects 1626: ;; specified by the ANSI C standard. 1627: 1628: (define_insn "modsi3" 1629: [(set (match_operand:SI 0 "register_operand" "=d") 1630: (mod:SI (match_operand:SI 1 "arith_operand" "dI") 1631: (match_operand:SI 2 "arith_operand" "dI")))] 1632: "" 1633: "remi %2,%1,%0" 1634: [(set_attr "type" "div")]) 1635: 1636: (define_insn "umodsi3" 1637: [(set (match_operand:SI 0 "register_operand" "=d") 1638: (umod:SI (match_operand:SI 1 "arith_operand" "dI") 1639: (match_operand:SI 2 "arith_operand" "dI")))] 1640: "" 1641: "remo %2,%1,%0" 1642: [(set_attr "type" "div")]) 1643: 1644: ;; And instructions (with complement also). 1645: 1646: (define_insn "andsi3" 1647: [(set (match_operand:SI 0 "register_operand" "=d") 1648: (and:SI (match_operand:SI 1 "arith_operand" "%dI") 1649: (match_operand:SI 2 "arith_operand" "dI")))] 1650: "" 1651: "* 1652: { 1653: if (i960_bypass (insn, operands[1], operands[2], 0)) 1654: return \"and %2,%1,%0\"; 1655: return \"and %1,%2,%0\"; 1656: }") 1657: 1658: (define_insn "" 1659: [(set (match_operand:SI 0 "register_operand" "=d") 1660: (and:SI (not:SI (match_operand:SI 1 "arith_operand" "dI")) 1661: (match_operand:SI 2 "arith_operand" "dI")))] 1662: "" 1663: "* 1664: { 1665: if (i960_bypass (insn, operands[1], operands[2], 0)) 1666: return \"notand %2,%1,%0\"; 1667: return \"andnot %1,%2,%0\"; 1668: }") 1669: 1670: (define_insn "" 1671: [(set (match_operand:SI 0 "register_operand" "=d") 1672: (ior:SI (not:SI (match_operand:SI 1 "arith_operand" "%dI")) 1673: (not:SI (match_operand:SI 2 "arith_operand" "dI"))))] 1674: "" 1675: "* 1676: { 1677: if (i960_bypass (insn, operands[1], operands[2], 0)) 1678: return \"nand %2,%1,%0\"; 1679: return \"nand %1,%2,%0\"; 1680: }") 1681: 1682: (define_insn "" 1683: [(set (match_operand:SI 0 "register_operand" "=d") 1684: (ior:SI (match_operand:SI 1 "arith_operand" "dI") 1685: (match_operand:SI 2 "power2_operand" "n")))] 1686: "" 1687: "* 1688: { 1689: operands[2] = gen_rtx (CONST_INT, VOIDmode, 1690: bitpos (INTVAL (operands[2]))); 1691: return \"setbit %2,%1,%0\"; 1692: }") 1693: 1694: (define_insn "" 1695: [(set (match_operand:SI 0 "register_operand" "=d") 1696: (ior:SI (ashift:SI (const_int 1) 1697: (match_operand:SI 1 "register_operand" "d")) 1698: (match_operand:SI 2 "arith_operand" "dI")))] 1699: "" 1700: "setbit %1,%2,%0") 1701: 1702: (define_insn "" 1703: [(set (match_operand:SI 0 "register_operand" "=d") 1704: (and:SI (match_operand:SI 1 "arith_operand" "dI") 1705: (match_operand:SI 2 "cmplpower2_operand" "n")))] 1706: "" 1707: "* 1708: { 1709: operands[2] = gen_rtx (CONST_INT, VOIDmode, 1710: bitpos (~INTVAL (operands[2]))); 1711: return \"clrbit %2,%1,%0\"; 1712: }") 1713: 1.1.1.2 root 1714: ;; (not (ashift 1 reg)) canonicalizes to (rotate -2 reg) 1.1 root 1715: (define_insn "" 1716: [(set (match_operand:SI 0 "register_operand" "=d") 1.1.1.2 root 1717: (and:SI (rotate:SI (const_int -2) 1.1 root 1718: (match_operand:SI 1 "register_operand" "d")) 1.1.1.2 root 1719: (match_operand:SI 2 "register_operand" "d")))] 1.1 root 1720: "" 1721: "clrbit %1,%2,%0") 1722: 1.1.1.2 root 1723: ;; The above pattern canonicalizes to this when both the input and output 1724: ;; are the same pseudo-register. 1725: (define_insn "" 1726: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "=d") 1727: (const_int 1) 1728: (match_operand:SI 1 "register_operand" "d")) 1729: (const_int 0))] 1730: "" 1731: "clrbit %1,%0,%0") 1732: 1.1 root 1733: (define_insn "" 1734: [(set (match_operand:SI 0 "register_operand" "=d") 1735: (xor:SI (match_operand:SI 1 "arith_operand" "dI") 1736: (match_operand:SI 2 "power2_operand" "n")))] 1737: "" 1738: "* 1739: { 1740: operands[2] = gen_rtx (CONST_INT, VOIDmode, 1741: bitpos (INTVAL (operands[2]))); 1742: return \"notbit %2,%1,%0\"; 1743: }") 1744: 1745: (define_insn "" 1746: [(set (match_operand:SI 0 "register_operand" "=d") 1747: (xor:SI (ashift:SI (const_int 1) 1748: (match_operand:SI 1 "register_operand" "d")) 1749: (match_operand:SI 2 "arith_operand" "dI")))] 1750: "" 1751: "notbit %1,%2,%0") 1752: 1753: (define_insn "iorsi3" 1754: [(set (match_operand:SI 0 "register_operand" "=d") 1755: (ior:SI (match_operand:SI 1 "arith_operand" "%dI") 1756: (match_operand:SI 2 "arith_operand" "dI")))] 1757: "" 1758: "* 1759: { 1760: if (i960_bypass (insn, operands[1], operands[2], 0)) 1761: return \"or %2,%1,%0\"; 1762: return \"or %1,%2,%0\"; 1763: }") 1764: 1765: (define_insn "" 1766: [(set (match_operand:SI 0 "register_operand" "=d") 1767: (ior:SI (not:SI (match_operand:SI 1 "arith_operand" "dI")) 1768: (match_operand:SI 2 "arith_operand" "dI")))] 1769: "" 1770: "* 1771: { 1772: if (i960_bypass (insn, operands[1], operands[2], 0)) 1773: return \"notor %2,%1,%0\"; 1774: return \"ornot %1,%2,%0\"; 1775: }") 1776: 1777: (define_insn "" 1778: [(set (match_operand:SI 0 "register_operand" "=d") 1779: (and:SI (not:SI (match_operand:SI 1 "arith_operand" "%dI")) 1780: (not:SI (match_operand:SI 2 "arith_operand" "dI"))))] 1781: "" 1782: "* 1783: { 1784: if (i960_bypass (insn, operands[1], operands[2], 0)) 1785: return \"nor %2,%1,%0\"; 1786: return \"nor %1,%2,%0\"; 1787: }") 1788: 1789: (define_insn "xorsi3" 1790: [(set (match_operand:SI 0 "register_operand" "=d") 1791: (xor:SI (match_operand:SI 1 "arith_operand" "%dI") 1792: (match_operand:SI 2 "arith_operand" "dI")))] 1793: "" 1794: "* 1795: { 1796: if (i960_bypass (insn, operands[1], operands[2], 0)) 1797: return \"xor %2,%1,%0\"; 1798: return \"xor %1,%2,%0\"; 1799: }") 1800: 1801: (define_insn "" 1802: [(set (match_operand:SI 0 "register_operand" "=d") 1803: (not:SI (xor:SI (match_operand:SI 1 "arith_operand" "%dI") 1804: (match_operand:SI 2 "arith_operand" "dI"))))] 1805: "" 1806: "* 1807: { 1808: if (i960_bypass (insn, operands[1], operands[2], 0)) 1809: return \"xnor %2,%1,%0\"; 1810: return \"xnor %2,%1,%0\"; 1811: }") 1812: 1813: (define_insn "negsi2" 1814: [(set (match_operand:SI 0 "register_operand" "=d") 1815: (neg:SI (match_operand:SI 1 "arith_operand" "dI")))] 1816: "" 1817: "subo %1,0,%0" 1818: [(set_attr "length" "1")]) 1819: 1820: (define_insn "one_cmplsi2" 1821: [(set (match_operand:SI 0 "register_operand" "=d") 1822: (not:SI (match_operand:SI 1 "arith_operand" "dI")))] 1823: "" 1824: "not %1,%0" 1825: [(set_attr "length" "1")]) 1826: 1827: ;; Floating point arithmetic instructions. 1828: 1829: (define_insn "adddf3" 1830: [(set (match_operand:DF 0 "register_operand" "=d*f") 1831: (plus:DF (match_operand:DF 1 "fp_arith_operand" "%rGH") 1832: (match_operand:DF 2 "fp_arith_operand" "rGH")))] 1833: "TARGET_NUMERICS" 1834: "addrl %1,%2,%0" 1835: [(set_attr "type" "fpadd")]) 1836: 1837: (define_insn "addsf3" 1838: [(set (match_operand:SF 0 "register_operand" "=d*f") 1839: (plus:SF (match_operand:SF 1 "fp_arith_operand" "%rGH") 1840: (match_operand:SF 2 "fp_arith_operand" "rGH")))] 1841: "TARGET_NUMERICS" 1842: "addr %1,%2,%0" 1843: [(set_attr "type" "fpadd")]) 1844: 1845: 1846: (define_insn "subdf3" 1847: [(set (match_operand:DF 0 "register_operand" "=d*f") 1848: (minus:DF (match_operand:DF 1 "fp_arith_operand" "rGH") 1849: (match_operand:DF 2 "fp_arith_operand" "rGH")))] 1850: "TARGET_NUMERICS" 1851: "subrl %2,%1,%0" 1852: [(set_attr "type" "fpadd")]) 1853: 1854: (define_insn "subsf3" 1855: [(set (match_operand:SF 0 "register_operand" "=d*f") 1856: (minus:SF (match_operand:SF 1 "fp_arith_operand" "rGH") 1857: (match_operand:SF 2 "fp_arith_operand" "rGH")))] 1858: "TARGET_NUMERICS" 1859: "subr %2,%1,%0" 1860: [(set_attr "type" "fpadd")]) 1861: 1862: 1863: (define_insn "muldf3" 1864: [(set (match_operand:DF 0 "register_operand" "=d*f") 1865: (mult:DF (match_operand:DF 1 "fp_arith_operand" "%rGH") 1866: (match_operand:DF 2 "fp_arith_operand" "rGH")))] 1867: "TARGET_NUMERICS" 1868: "mulrl %1,%2,%0" 1869: [(set_attr "type" "fpmul")]) 1870: 1871: (define_insn "mulsf3" 1872: [(set (match_operand:SF 0 "register_operand" "=d*f") 1873: (mult:SF (match_operand:SF 1 "fp_arith_operand" "%rGH") 1874: (match_operand:SF 2 "fp_arith_operand" "rGH")))] 1875: "TARGET_NUMERICS" 1876: "mulr %1,%2,%0" 1877: [(set_attr "type" "fpmul")]) 1878: 1879: 1880: (define_insn "divdf3" 1881: [(set (match_operand:DF 0 "register_operand" "=d*f") 1882: (div:DF (match_operand:DF 1 "fp_arith_operand" "rGH") 1883: (match_operand:DF 2 "fp_arith_operand" "rGH")))] 1884: "TARGET_NUMERICS" 1885: "divrl %2,%1,%0" 1886: [(set_attr "type" "fpdiv")]) 1887: 1888: (define_insn "divsf3" 1889: [(set (match_operand:SF 0 "register_operand" "=d*f") 1890: (div:SF (match_operand:SF 1 "fp_arith_operand" "rGH") 1891: (match_operand:SF 2 "fp_arith_operand" "rGH")))] 1892: "TARGET_NUMERICS" 1893: "divr %2,%1,%0" 1894: [(set_attr "type" "fpdiv")]) 1895: 1896: (define_insn "negdf2" 1897: [(set (match_operand:DF 0 "register_operand" "=d,d*f") 1898: (neg:DF (match_operand:DF 1 "register_operand" "d,r")))] 1899: "" 1900: "* 1901: { 1902: if (which_alternative == 0) 1903: { 1904: if (REGNO (operands[0]) == REGNO (operands[1])) 1905: return \"notbit 31,%D1,%D0\"; 1906: return \"mov %1,%0\;notbit 31,%D1,%D0\"; 1907: } 1908: return \"subrl %1,0f0.0,%0\"; 1909: }" 1910: [(set_attr "type" "fpadd")]) 1911: 1912: (define_insn "negsf2" 1913: [(set (match_operand:SF 0 "register_operand" "=d,d*f") 1914: (neg:SF (match_operand:SF 1 "register_operand" "d,r")))] 1915: "" 1916: "@ 1917: notbit 31,%1,%0 1918: subr %1,0f0.0,%0" 1919: [(set_attr "type" "fpadd")]) 1920: 1921: ;;; The abs patterns also work even if the target machine doesn't have 1922: ;;; floating point, because in that case dstreg and srcreg will always be 1923: ;;; less than 32. 1924: 1925: (define_insn "absdf2" 1926: [(set (match_operand:DF 0 "register_operand" "=d*f") 1927: (abs:DF (match_operand:DF 1 "register_operand" "df")))] 1928: "" 1929: "* 1930: { 1931: int dstreg = REGNO (operands[0]); 1932: int srcreg = REGNO (operands[1]); 1933: 1934: if (dstreg < 32) 1935: { 1936: if (srcreg < 32) 1937: { 1938: if (dstreg != srcreg) 1939: output_asm_insn (\"mov %1,%0\", operands); 1940: return \"clrbit 31,%D1,%D0\"; 1941: } 1942: /* Src is an fp reg. */ 1943: return \"movrl %1,%0\;clrbit 31,%D1,%D0\"; 1944: } 1945: if (srcreg >= 32) 1946: return \"cpysre %1,0f0.0,%0\"; 1947: return \"movrl %1,%0\;cpysre %0,0f0.0,%0\"; 1948: }" 1949: [(set_attr "type" "multi")]) 1950: 1951: (define_insn "abssf2" 1952: [(set (match_operand:SF 0 "register_operand" "=d*f") 1953: (abs:SF (match_operand:SF 1 "register_operand" "df")))] 1954: "" 1955: "* 1956: { 1957: int dstreg = REGNO (operands[0]); 1958: int srcreg = REGNO (operands[1]); 1959: 1960: if (dstreg < 32 && srcreg < 32) 1961: return \"clrbit 31,%1,%0\"; 1962: 1963: if (dstreg >= 32 && srcreg >= 32) 1964: return \"cpysre %1,0f0.0,%0\"; 1965: 1966: if (dstreg < 32) 1967: return \"movr %1,%0\;clrbit 31,%0,%0\"; 1968: 1969: return \"movr %1,%0\;cpysre %0,0f0.0,%0\"; 1970: }" 1971: [(set_attr "type" "multi")]) 1972: 1973: ;; Tetra (16 byte) float support. 1974: 1.1.1.3 ! root 1975: (define_expand "cmpxf" ! 1976: [(set (reg:CC 36) ! 1977: (compare:CC (match_operand:XF 0 "register_operand" "") ! 1978: (match_operand:XF 1 "nonmemory_operand" "")))] ! 1979: "TARGET_NUMERICS" ! 1980: " ! 1981: { ! 1982: i960_compare_op0 = operands[0]; ! 1983: i960_compare_op1 = operands[1]; ! 1984: DONE; ! 1985: }") ! 1986: ! 1987: (define_insn "" 1.1 root 1988: [(set (reg:CC 36) 1.1.1.3 ! root 1989: (compare:CC (match_operand:XF 0 "register_operand" "f") ! 1990: (match_operand:XF 1 "nonmemory_operand" "fGH")))] 1.1 root 1991: "TARGET_NUMERICS" 1.1.1.3 ! root 1992: "cmpr %0,%1" 1.1 root 1993: [(set_attr "type" "fpcc")]) 1994: 1.1.1.3 ! root 1995: (define_expand "movxf" ! 1996: [(set (match_operand:XF 0 "general_operand" "") ! 1997: (match_operand:XF 1 "fpmove_src_operand" ""))] 1.1 root 1998: "" 1999: " 2000: { 1.1.1.3 ! root 2001: if (emit_move_sequence (operands, XFmode)) 1.1 root 2002: DONE; 2003: }") 2004: 2005: (define_insn "" 1.1.1.3 ! root 2006: [(set (match_operand:XF 0 "general_operand" "=r,f,d,d,m") ! 2007: (match_operand:XF 1 "fpmove_src_operand" "r,GH,F,m,d"))] ! 2008: "register_operand (operands[0], XFmode) ! 2009: || register_operand (operands[1], XFmode)" 1.1 root 2010: "* 2011: { 2012: switch (which_alternative) 2013: { 2014: case 0: 2015: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1])) 2016: return \"movre %1,%0\"; 2017: else 2018: return \"movq %1,%0\"; 2019: case 1: 2020: return \"movre %1,%0\"; 2021: case 2: 2022: return i960_output_ldconst (operands[0], operands[1]); 2023: case 3: 1.1.1.3 ! root 2024: return \"ldt %1,%0\"; 1.1 root 2025: case 4: 1.1.1.3 ! root 2026: return \"stt %1,%0\"; 1.1 root 2027: } 2028: }" 2029: [(set_attr "type" "move,move,load,fpload,fpstore")]) 2030: 1.1.1.3 ! root 2031: (define_insn "extendsfxf2" ! 2032: [(set (match_operand:XF 0 "register_operand" "=f,d") ! 2033: (float_extend:XF 1.1 root 2034: (match_operand:SF 1 "register_operand" "d,f")))] 2035: "TARGET_NUMERICS" 2036: "@ 2037: movr %1,%0 2038: movre %1,%0" 2039: [(set_attr "type" "fpmove")]) 2040: 1.1.1.3 ! root 2041: (define_insn "extenddfxf2" ! 2042: [(set (match_operand:XF 0 "register_operand" "=f,d") ! 2043: (float_extend:XF 1.1 root 2044: (match_operand:DF 1 "register_operand" "d,f")))] 2045: "TARGET_NUMERICS" 2046: "@ 2047: movrl %1,%0 2048: movre %1,%0" 2049: [(set_attr "type" "fpmove")]) 2050: 1.1.1.3 ! root 2051: (define_insn "truncxfdf2" 1.1 root 2052: [(set (match_operand:DF 0 "register_operand" "=d") 2053: (float_truncate:DF 1.1.1.3 ! root 2054: (match_operand:XF 1 "register_operand" "f")))] 1.1 root 2055: "TARGET_NUMERICS" 2056: "movrl %1,%0" 2057: [(set_attr "type" "fpmove")]) 2058: 1.1.1.3 ! root 2059: (define_insn "truncxfsf2" 1.1 root 2060: [(set (match_operand:SF 0 "register_operand" "=d") 2061: (float_truncate:SF 1.1.1.3 ! root 2062: (match_operand:XF 1 "register_operand" "f")))] 1.1 root 2063: "TARGET_NUMERICS" 2064: "movr %1,%0" 2065: [(set_attr "type" "fpmove")]) 2066: 1.1.1.3 ! root 2067: (define_insn "floatsixf2" ! 2068: [(set (match_operand:XF 0 "register_operand" "=f") ! 2069: (float:XF (match_operand:SI 1 "register_operand" "d")))] 1.1 root 2070: "TARGET_NUMERICS" 2071: "cvtir %1,%0" 2072: [(set_attr "type" "fpcvt")]) 2073: 1.1.1.3 ! root 2074: (define_insn "fix_truncxfsi2" 1.1 root 2075: [(set (match_operand:SI 0 "register_operand" "=d") 1.1.1.3 ! root 2076: (fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))] 1.1 root 2077: "TARGET_NUMERICS" 2078: "cvtzri %1,%0" 2079: [(set_attr "type" "fpcvt")]) 2080: 1.1.1.3 ! root 2081: (define_insn "fixuns_truncxfsi2" 1.1 root 2082: [(set (match_operand:SI 0 "register_operand" "=d") 1.1.1.3 ! root 2083: (unsigned_fix:SI (fix:XF (match_operand:XF 1 "register_operand" "f"))))] 1.1 root 2084: "TARGET_NUMERICS" 2085: "cvtzri %1,%0" 2086: [(set_attr "type" "fpcvt")]) 2087: 1.1.1.3 ! root 2088: (define_insn "addxf3" ! 2089: [(set (match_operand:XF 0 "register_operand" "=f") ! 2090: (plus:XF (match_operand:XF 1 "nonmemory_operand" "%fGH") ! 2091: (match_operand:XF 2 "nonmemory_operand" "fGH")))] 1.1 root 2092: "TARGET_NUMERICS" 2093: "addr %1,%2,%0" 2094: [(set_attr "type" "fpadd")]) 2095: 1.1.1.3 ! root 2096: (define_insn "subxf3" ! 2097: [(set (match_operand:XF 0 "register_operand" "=f") ! 2098: (minus:XF (match_operand:XF 1 "nonmemory_operand" "fGH") ! 2099: (match_operand:XF 2 "nonmemory_operand" "fGH")))] 1.1 root 2100: "TARGET_NUMERICS" 2101: "subr %2,%1,%0" 2102: [(set_attr "type" "fpadd")]) 2103: 1.1.1.3 ! root 2104: (define_insn "mulxf3" ! 2105: [(set (match_operand:XF 0 "register_operand" "=f") ! 2106: (mult:XF (match_operand:XF 1 "nonmemory_operand" "%fGH") ! 2107: (match_operand:XF 2 "nonmemory_operand" "fGH")))] 1.1 root 2108: "TARGET_NUMERICS" 2109: "mulr %1,%2,%0" 2110: [(set_attr "type" "fpmul")]) 2111: 1.1.1.3 ! root 2112: (define_insn "divxf3" ! 2113: [(set (match_operand:XF 0 "register_operand" "=f") ! 2114: (div:XF (match_operand:XF 1 "nonmemory_operand" "fGH") ! 2115: (match_operand:XF 2 "nonmemory_operand" "fGH")))] 1.1 root 2116: "TARGET_NUMERICS" 2117: "divr %2,%1,%0" 2118: [(set_attr "type" "fpdiv")]) 2119: 1.1.1.3 ! root 2120: (define_insn "negxf2" ! 2121: [(set (match_operand:XF 0 "register_operand" "=f") ! 2122: (neg:XF (match_operand:XF 1 "register_operand" "f")))] 1.1 root 2123: "TARGET_NUMERICS" 2124: "subr %1,0f0.0,%0" 2125: [(set_attr "type" "fpadd")]) 2126: 1.1.1.3 ! root 2127: (define_insn "absxf2" ! 2128: [(set (match_operand:XF 0 "register_operand" "=f") ! 2129: (abs:XF (match_operand:XF 1 "register_operand" "f")))] 1.1 root 2130: "(TARGET_NUMERICS)" 2131: "cpysre %1,0f0.0,%0" 2132: [(set_attr "type" "fpmove")]) 2133: 2134: ;; Arithmetic shift instructions. 2135: 2136: ;; The shli instruction generates an overflow fault if the sign changes. 2137: ;; In the case of overflow, it does not give the natural result, it instead 2138: ;; gives the last shift value before the overflow. We can not use this 2139: ;; instruction because gcc thinks that arithmetic left shift and logical 2140: ;; left shift are identical, and sometimes canonicalizes the logical left 2141: ;; shift to an arithmetic left shift. Therefore we must always use the 2142: ;; logical left shift instruction. 2143: 2144: (define_insn "ashlsi3" 2145: [(set (match_operand:SI 0 "register_operand" "=d") 2146: (ashift:SI (match_operand:SI 1 "arith_operand" "dI") 2147: (match_operand:SI 2 "arith_operand" "dI")))] 2148: "" 2149: "shlo %2,%1,%0" 2150: [(set_attr "type" "alu2")]) 2151: 2152: (define_insn "ashrsi3" 2153: [(set (match_operand:SI 0 "register_operand" "=d") 2154: (ashiftrt:SI (match_operand:SI 1 "arith_operand" "dI") 2155: (match_operand:SI 2 "arith_operand" "dI")))] 2156: "" 2157: "shri %2,%1,%0" 2158: [(set_attr "type" "alu2")]) 2159: 2160: (define_insn "lshrsi3" 2161: [(set (match_operand:SI 0 "register_operand" "=d") 2162: (lshiftrt:SI (match_operand:SI 1 "arith_operand" "dI") 2163: (match_operand:SI 2 "arith_operand" "dI")))] 2164: "" 2165: "shro %2,%1,%0" 2166: [(set_attr "type" "alu2")]) 2167: 2168: ;; Unconditional and other jump instructions. 2169: 2170: (define_insn "jump" 2171: [(set (pc) 2172: (label_ref (match_operand 0 "" "")))] 2173: "" 2174: "b %l0" 2175: [(set_attr "type" "branch")]) 2176: 2177: (define_insn "indirect_jump" 2178: [(set (pc) (match_operand:SI 0 "address_operand" "p"))] 2179: "" 2180: "bx %a0" 2181: [(set_attr "type" "branch")]) 2182: 2183: (define_insn "tablejump" 2184: [(set (pc) (match_operand:SI 0 "register_operand" "d")) 2185: (use (label_ref (match_operand 1 "" "")))] 2186: "" 2187: "bx (%0)" 2188: [(set_attr "type" "branch")]) 2189: 2190: ;;- jump to subroutine 2191: 2192: (define_expand "call" 1.1.1.2 root 2193: [(call (match_operand:SI 0 "memory_operand" "m") 1.1 root 2194: (match_operand:SI 1 "immediate_operand" "i"))] 2195: "" 2196: " 2197: { 2198: emit_insn (gen_call_internal (operands[0], operands[1], 2199: virtual_outgoing_args_rtx)); 2200: DONE; 2201: }") 2202: 2203: ;; We need a call saved register allocated for the match_scratch, so we use 2204: ;; 'l' because all local registers are call saved. 2205: 2206: ;; ??? I would prefer to use a match_scratch here, but match_scratch allocated 2207: ;; registers can't be used for spills. In a function with lots of calls, 2208: ;; local-alloc may allocate all local registers to a match_scratch, leaving 2209: ;; no local registers available for spills. 2210: 2211: (define_insn "call_internal" 1.1.1.2 root 2212: [(call (match_operand:SI 0 "memory_operand" "m") 1.1 root 2213: (match_operand:SI 1 "immediate_operand" "i")) 2214: (use (match_operand:SI 2 "address_operand" "p")) 2215: (clobber (reg:SI 19))] 2216: "" 2217: "* return i960_output_call_insn (operands[0], operands[1], operands[2], 2218: insn);" 2219: [(set_attr "type" "call")]) 2220: 2221: (define_expand "call_value" 2222: [(set (match_operand 0 "register_operand" "=d") 1.1.1.2 root 2223: (call (match_operand:SI 1 "memory_operand" "m") 1.1 root 2224: (match_operand:SI 2 "immediate_operand" "i")))] 2225: "" 2226: " 2227: { 2228: emit_insn (gen_call_value_internal (operands[0], operands[1], operands[2], 2229: virtual_outgoing_args_rtx)); 2230: DONE; 2231: }") 2232: 2233: ;; We need a call saved register allocated for the match_scratch, so we use 2234: ;; 'l' because all local registers are call saved. 2235: 2236: (define_insn "call_value_internal" 2237: [(set (match_operand 0 "register_operand" "=d") 1.1.1.2 root 2238: (call (match_operand:SI 1 "memory_operand" "m") 1.1 root 2239: (match_operand:SI 2 "immediate_operand" "i"))) 2240: (use (match_operand:SI 3 "address_operand" "p")) 2241: (clobber (reg:SI 19))] 2242: "" 2243: "* return i960_output_call_insn (operands[1], operands[2], operands[3], 2244: insn);" 2245: [(set_attr "type" "call")]) 2246: 2247: (define_insn "return" 2248: [(return)] 2249: "" 2250: "* return i960_output_ret_insn (insn);" 2251: [(set_attr "type" "branch")]) 2252: 2253: (define_insn "nop" 2254: [(const_int 0)] 2255: "" 2256: "") 2257: 2258: ;; Various peephole optimizations for multiple-word moves, loads, and stores. 2259: ;; Multiple register moves. 2260: 2261: ;; Matched 5/28/91 2262: (define_peephole 2263: [(set (match_operand:SI 0 "register_operand" "=r") 2264: (match_operand:SI 1 "register_operand" "r")) 2265: (set (match_operand:SI 2 "register_operand" "=r") 2266: (match_operand:SI 3 "register_operand" "r")) 2267: (set (match_operand:SI 4 "register_operand" "=r") 2268: (match_operand:SI 5 "register_operand" "r")) 2269: (set (match_operand:SI 6 "register_operand" "=r") 2270: (match_operand:SI 7 "register_operand" "r"))] 2271: "((REGNO (operands[0]) & 3) == 0) 2272: && ((REGNO (operands[1]) & 3) == 0) 2273: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) 2274: && (REGNO (operands[1]) + 1 == REGNO (operands[3])) 2275: && (REGNO (operands[0]) + 2 == REGNO (operands[4])) 2276: && (REGNO (operands[1]) + 2 == REGNO (operands[5])) 2277: && (REGNO (operands[0]) + 3 == REGNO (operands[6])) 2278: && (REGNO (operands[1]) + 3 == REGNO (operands[7]))" 2279: "movq %1,%0") 2280: 2281: ;; Matched 4/17/92 2282: (define_peephole 2283: [(set (match_operand:DI 0 "register_operand" "=r") 2284: (match_operand:DI 1 "register_operand" "r")) 2285: (set (match_operand:DI 2 "register_operand" "=r") 2286: (match_operand:DI 3 "register_operand" "r"))] 2287: "((REGNO (operands[0]) & 3) == 0) 2288: && ((REGNO (operands[1]) & 3) == 0) 2289: && (REGNO (operands[0]) + 2 == REGNO (operands[2])) 2290: && (REGNO (operands[1]) + 2 == REGNO (operands[3]))" 2291: "movq %1,%0") 2292: 2293: ;; Matched 4/17/92 2294: (define_peephole 2295: [(set (match_operand:DI 0 "register_operand" "=r") 2296: (match_operand:DI 1 "register_operand" "r")) 2297: (set (match_operand:SI 2 "register_operand" "=r") 2298: (match_operand:SI 3 "register_operand" "r")) 2299: (set (match_operand:SI 4 "register_operand" "=r") 2300: (match_operand:SI 5 "register_operand" "r"))] 2301: "((REGNO (operands[0]) & 3) == 0) 2302: && ((REGNO (operands[1]) & 3) == 0) 2303: && (REGNO (operands[0]) + 2 == REGNO (operands[2])) 2304: && (REGNO (operands[1]) + 2 == REGNO (operands[3])) 2305: && (REGNO (operands[0]) + 3 == REGNO (operands[4])) 2306: && (REGNO (operands[1]) + 3 == REGNO (operands[5]))" 2307: "movq %1,%0") 2308: 2309: ;; Matched 4/17/92 2310: (define_peephole 2311: [(set (match_operand:SI 0 "register_operand" "=r") 2312: (match_operand:SI 1 "register_operand" "r")) 2313: (set (match_operand:SI 2 "register_operand" "=r") 2314: (match_operand:SI 3 "register_operand" "r")) 2315: (set (match_operand:DI 4 "register_operand" "=r") 2316: (match_operand:DI 5 "register_operand" "r"))] 2317: "((REGNO (operands[0]) & 3) == 0) 2318: && ((REGNO (operands[1]) & 3) == 0) 2319: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) 2320: && (REGNO (operands[1]) + 1 == REGNO (operands[3])) 2321: && (REGNO (operands[0]) + 2 == REGNO (operands[4])) 2322: && (REGNO (operands[1]) + 2 == REGNO (operands[5]))" 2323: "movq %1,%0") 2324: 2325: ;; Matched 4/17/92 2326: (define_peephole 2327: [(set (match_operand:DI 0 "register_operand" "=r") 2328: (match_operand:DI 1 "register_operand" "r")) 2329: (set (match_operand:SI 2 "register_operand" "=r") 2330: (match_operand:SI 3 "register_operand" "r"))] 2331: "((REGNO (operands[0]) & 3) == 0) 2332: && ((REGNO (operands[1]) & 3) == 0) 2333: && (REGNO (operands[0]) + 2 == REGNO (operands[2])) 2334: && (REGNO (operands[1]) + 2 == REGNO (operands[3]))" 2335: "movt %1,%0") 2336: 2337: ;; Matched 5/28/91 2338: (define_peephole 2339: [(set (match_operand:SI 0 "register_operand" "=r") 2340: (match_operand:SI 1 "register_operand" "r")) 2341: (set (match_operand:SI 2 "register_operand" "=r") 2342: (match_operand:SI 3 "register_operand" "r")) 2343: (set (match_operand:SI 4 "register_operand" "=r") 2344: (match_operand:SI 5 "register_operand" "r"))] 2345: "((REGNO (operands[0]) & 3) == 0) 2346: && ((REGNO (operands[1]) & 3) == 0) 2347: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) 2348: && (REGNO (operands[1]) + 1 == REGNO (operands[3])) 2349: && (REGNO (operands[0]) + 2 == REGNO (operands[4])) 2350: && (REGNO (operands[1]) + 2 == REGNO (operands[5]))" 2351: "movt %1,%0") 2352: 2353: ;; Matched 5/28/91 2354: (define_peephole 2355: [(set (match_operand:SI 0 "register_operand" "=r") 2356: (match_operand:SI 1 "register_operand" "r")) 2357: (set (match_operand:SI 2 "register_operand" "=r") 2358: (match_operand:SI 3 "register_operand" "r"))] 2359: "((REGNO (operands[0]) & 1) == 0) 2360: && ((REGNO (operands[1]) & 1) == 0) 2361: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) 2362: && (REGNO (operands[1]) + 1 == REGNO (operands[3]))" 2363: "movl %1,%0") 2364: 2365: ; Multiple register loads. 2366: 2367: ;; Matched 6/15/91 2368: (define_peephole 2369: [(set (match_operand:SI 0 "register_operand" "=r") 2370: (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r") 2371: (match_operand:SI 2 "immediate_operand" "n")))) 2372: (set (match_operand:SI 3 "register_operand" "=r") 2373: (mem:SI (plus:SI (match_dup 1) 2374: (match_operand:SI 4 "immediate_operand" "n")))) 2375: (set (match_operand:SI 5 "register_operand" "=r") 2376: (mem:SI (plus:SI (match_dup 1) 2377: (match_operand:SI 6 "immediate_operand" "n")))) 2378: (set (match_operand:SI 7 "register_operand" "=r") 2379: (mem:SI (plus:SI (match_dup 1) 2380: (match_operand:SI 8 "immediate_operand" "n"))))] 2381: "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) 2382: && (REGNO (operands[1]) != REGNO (operands[0])) 2383: && (REGNO (operands[0]) + 1 == REGNO (operands[3])) 2384: && (REGNO (operands[1]) != REGNO (operands[3])) 2385: && (REGNO (operands[0]) + 2 == REGNO (operands[5])) 2386: && (REGNO (operands[1]) != REGNO (operands[5])) 2387: && (REGNO (operands[0]) + 3 == REGNO (operands[7])) 2388: && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])) 2389: && (INTVAL (operands[2]) + 8 == INTVAL (operands[6])) 2390: && (INTVAL (operands[2]) + 12 == INTVAL (operands[8])))" 2391: "ldq %2(%1),%0") 2392: 2393: ;; Matched 5/28/91 2394: (define_peephole 2395: [(set (match_operand:DF 0 "register_operand" "=d") 2396: (mem:DF (plus:SI (match_operand:SI 1 "register_operand" "d") 2397: (match_operand:SI 2 "immediate_operand" "n")))) 2398: (set (match_operand:DF 3 "register_operand" "=d") 2399: (mem:DF (plus:SI (match_dup 1) 2400: (match_operand:SI 4 "immediate_operand" "n"))))] 2401: "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) 2402: && (REGNO (operands[1]) != REGNO (operands[0])) 2403: && (REGNO (operands[0]) + 2 == REGNO (operands[3])) 2404: && (REGNO (operands[1]) != REGNO (operands[3])) 2405: && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))" 2406: "ldq %2(%1),%0") 2407: 2408: ;; Matched 1/24/92 2409: (define_peephole 2410: [(set (match_operand:DI 0 "register_operand" "=d") 2411: (mem:DI (plus:SI (match_operand:SI 1 "register_operand" "d") 2412: (match_operand:SI 2 "immediate_operand" "n")))) 2413: (set (match_operand:DI 3 "register_operand" "=d") 2414: (mem:DI (plus:SI (match_dup 1) 2415: (match_operand:SI 4 "immediate_operand" "n"))))] 2416: "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) 2417: && (REGNO (operands[1]) != REGNO (operands[0])) 2418: && (REGNO (operands[0]) + 2 == REGNO (operands[3])) 2419: && (REGNO (operands[1]) != REGNO (operands[3])) 2420: && (INTVAL (operands[2]) + 8 == INTVAL (operands[4])))" 2421: "ldq %2(%1),%0") 2422: 2423: ;; Matched 4/17/92 2424: (define_peephole 2425: [(set (match_operand:SI 0 "register_operand" "=d") 2426: (mem:SI (match_operand:SI 1 "register_operand" "d"))) 2427: (set (match_operand:SI 2 "register_operand" "=d") 2428: (mem:SI (plus:SI (match_dup 1) 2429: (match_operand:SI 3 "immediate_operand" "n")))) 2430: (set (match_operand:SI 4 "register_operand" "=d") 2431: (mem:SI (plus:SI (match_dup 1) 2432: (match_operand:SI 5 "immediate_operand" "n")))) 2433: (set (match_operand:SI 6 "register_operand" "=d") 2434: (mem:SI (plus:SI (match_dup 1) 2435: (match_operand:SI 7 "immediate_operand" "n"))))] 2436: "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0) 2437: && (REGNO (operands[1]) != REGNO (operands[0])) 2438: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) 2439: && (REGNO (operands[1]) != REGNO (operands[2])) 2440: && (REGNO (operands[0]) + 2 == REGNO (operands[4])) 2441: && (REGNO (operands[1]) != REGNO (operands[4])) 2442: && (REGNO (operands[0]) + 3 == REGNO (operands[6])) 2443: && (INTVAL (operands[3]) == 4) 2444: && (INTVAL (operands[5]) == 8) 2445: && (INTVAL (operands[7]) == 12))" 2446: "ldq (%1),%0") 2447: 2448: ;; Matched 5/28/91 2449: (define_peephole 2450: [(set (match_operand:SI 0 "register_operand" "=d") 2451: (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d") 2452: (match_operand:SI 2 "immediate_operand" "n")))) 2453: (set (match_operand:SI 3 "register_operand" "=d") 2454: (mem:SI (plus:SI (match_dup 1) 2455: (match_operand:SI 4 "immediate_operand" "n")))) 2456: (set (match_operand:SI 5 "register_operand" "=d") 2457: (mem:SI (plus:SI (match_dup 1) 2458: (match_operand:SI 6 "immediate_operand" "n"))))] 2459: "(i960_si_ti (operands[1], operands[2]) && ((REGNO (operands[0]) & 3) == 0) 2460: && (REGNO (operands[1]) != REGNO (operands[0])) 2461: && (REGNO (operands[0]) + 1 == REGNO (operands[3])) 2462: && (REGNO (operands[1]) != REGNO (operands[3])) 2463: && (REGNO (operands[0]) + 2 == REGNO (operands[5])) 2464: && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])) 2465: && (INTVAL (operands[2]) + 8 == INTVAL (operands[6])))" 2466: "ldt %2(%1),%0") 2467: 2468: ;; Matched 6/15/91 2469: (define_peephole 2470: [(set (match_operand:SI 0 "register_operand" "=d") 2471: (mem:SI (match_operand:SI 1 "register_operand" "d"))) 2472: (set (match_operand:SI 2 "register_operand" "=d") 2473: (mem:SI (plus:SI (match_dup 1) 2474: (match_operand:SI 3 "immediate_operand" "n")))) 2475: (set (match_operand:SI 4 "register_operand" "=d") 2476: (mem:SI (plus:SI (match_dup 1) 2477: (match_operand:SI 5 "immediate_operand" "n"))))] 2478: "(i960_si_ti (operands[1], 0) && ((REGNO (operands[0]) & 3) == 0) 2479: && (REGNO (operands[1]) != REGNO (operands[0])) 2480: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) 2481: && (REGNO (operands[1]) != REGNO (operands[2])) 2482: && (REGNO (operands[0]) + 2 == REGNO (operands[4])) 2483: && (INTVAL (operands[3]) == 4) 2484: && (INTVAL (operands[5]) == 8))" 2485: "ldt (%1),%0") 2486: 2487: ;; Matched 5/28/91 2488: (define_peephole 2489: [(set (match_operand:SI 0 "register_operand" "=d") 2490: (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "d") 2491: (match_operand:SI 2 "immediate_operand" "n")))) 2492: (set (match_operand:SI 3 "register_operand" "=d") 2493: (mem:SI (plus:SI (match_dup 1) 2494: (match_operand:SI 4 "immediate_operand" "n"))))] 2495: "(i960_si_di (operands[1], operands[2]) && ((REGNO (operands[0]) & 1) == 0) 2496: && (REGNO (operands[1]) != REGNO (operands[0])) 2497: && (REGNO (operands[0]) + 1 == REGNO (operands[3])) 2498: && (INTVAL (operands[2]) + 4 == INTVAL (operands[4])))" 2499: "ldl %2(%1),%0") 2500: 2501: ;; Matched 5/28/91 2502: (define_peephole 2503: [(set (match_operand:SI 0 "register_operand" "=d") 2504: (mem:SI (match_operand:SI 1 "register_operand" "d"))) 2505: (set (match_operand:SI 2 "register_operand" "=d") 2506: (mem:SI (plus:SI (match_dup 1) 2507: (match_operand:SI 3 "immediate_operand" "n"))))] 2508: "(i960_si_di (operands[1], 0) && ((REGNO (operands[0]) & 1) == 0) 2509: && (REGNO (operands[1]) != REGNO (operands[0])) 2510: && (REGNO (operands[0]) + 1 == REGNO (operands[2])) 2511: && (INTVAL (operands[3]) == 4))" 2512: "ldl (%1),%0") 2513: 2514: ; Multiple register stores. 2515: 2516: ;; Matched 5/28/91 2517: (define_peephole 2518: [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d") 2519: (match_operand:SI 1 "immediate_operand" "n"))) 2520: (match_operand:SI 2 "register_operand" "d")) 2521: (set (mem:SI (plus:SI (match_dup 0) 2522: (match_operand:SI 3 "immediate_operand" "n"))) 2523: (match_operand:SI 4 "register_operand" "d")) 2524: (set (mem:SI (plus:SI (match_dup 0) 2525: (match_operand:SI 5 "immediate_operand" "n"))) 2526: (match_operand:SI 6 "register_operand" "d")) 2527: (set (mem:SI (plus:SI (match_dup 0) 2528: (match_operand:SI 7 "immediate_operand" "n"))) 2529: (match_operand:SI 8 "register_operand" "d"))] 2530: "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) 2531: && (REGNO (operands[2]) + 1 == REGNO (operands[4])) 2532: && (REGNO (operands[2]) + 2 == REGNO (operands[6])) 2533: && (REGNO (operands[2]) + 3 == REGNO (operands[8])) 2534: && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])) 2535: && (INTVAL (operands[1]) + 8 == INTVAL (operands[5])) 2536: && (INTVAL (operands[1]) + 12 == INTVAL (operands[7])))" 2537: "stq %2,%1(%0)") 2538: 2539: ;; Matched 6/16/91 2540: (define_peephole 2541: [(set (mem:DF (plus:SI (match_operand:SI 0 "register_operand" "d") 2542: (match_operand:SI 1 "immediate_operand" "n"))) 2543: (match_operand:DF 2 "register_operand" "d")) 2544: (set (mem:DF (plus:SI (match_dup 0) 2545: (match_operand:SI 3 "immediate_operand" "n"))) 2546: (match_operand:DF 4 "register_operand" "d"))] 2547: "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) 2548: && (REGNO (operands[2]) + 2 == REGNO (operands[4])) 2549: && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))" 2550: "stq %2,%1(%0)") 2551: 2552: ;; Matched 4/17/92 2553: (define_peephole 2554: [(set (mem:DI (plus:SI (match_operand:SI 0 "register_operand" "d") 2555: (match_operand:SI 1 "immediate_operand" "n"))) 2556: (match_operand:DI 2 "register_operand" "d")) 2557: (set (mem:DI (plus:SI (match_dup 0) 2558: (match_operand:SI 3 "immediate_operand" "n"))) 2559: (match_operand:DI 4 "register_operand" "d"))] 2560: "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) 2561: && (REGNO (operands[2]) + 2 == REGNO (operands[4])) 2562: && (INTVAL (operands[1]) + 8 == INTVAL (operands[3])))" 2563: "stq %2,%1(%0)") 2564: 2565: ;; Matched 1/23/92 2566: (define_peephole 2567: [(set (mem:SI (match_operand:SI 0 "register_operand" "d")) 2568: (match_operand:SI 1 "register_operand" "d")) 2569: (set (mem:SI (plus:SI (match_dup 0) 2570: (match_operand:SI 2 "immediate_operand" "n"))) 2571: (match_operand:SI 3 "register_operand" "d")) 2572: (set (mem:SI (plus:SI (match_dup 0) 2573: (match_operand:SI 4 "immediate_operand" "n"))) 2574: (match_operand:SI 5 "register_operand" "d")) 2575: (set (mem:SI (plus:SI (match_dup 0) 2576: (match_operand:SI 6 "immediate_operand" "n"))) 2577: (match_operand:SI 7 "register_operand" "d"))] 2578: "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0) 2579: && (REGNO (operands[1]) + 1 == REGNO (operands[3])) 2580: && (REGNO (operands[1]) + 2 == REGNO (operands[5])) 2581: && (REGNO (operands[1]) + 3 == REGNO (operands[7])) 2582: && (INTVAL (operands[2]) == 4) 2583: && (INTVAL (operands[4]) == 8) 2584: && (INTVAL (operands[6]) == 12))" 2585: "stq %1,(%0)") 2586: 2587: ;; Matched 5/29/91 2588: (define_peephole 2589: [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d") 2590: (match_operand:SI 1 "immediate_operand" "n"))) 2591: (match_operand:SI 2 "register_operand" "d")) 2592: (set (mem:SI (plus:SI (match_dup 0) 2593: (match_operand:SI 3 "immediate_operand" "n"))) 2594: (match_operand:SI 4 "register_operand" "d")) 2595: (set (mem:SI (plus:SI (match_dup 0) 2596: (match_operand:SI 5 "immediate_operand" "n"))) 2597: (match_operand:SI 6 "register_operand" "d"))] 2598: "(i960_si_ti (operands[0], operands[1]) && ((REGNO (operands[2]) & 3) == 0) 2599: && (REGNO (operands[2]) + 1 == REGNO (operands[4])) 2600: && (REGNO (operands[2]) + 2 == REGNO (operands[6])) 2601: && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])) 2602: && (INTVAL (operands[1]) + 8 == INTVAL (operands[5])))" 2603: "stt %2,%1(%0)") 2604: 2605: ;; Matched 5/29/91 2606: (define_peephole 2607: [(set (mem:SI (match_operand:SI 0 "register_operand" "d")) 2608: (match_operand:SI 1 "register_operand" "d")) 2609: (set (mem:SI (plus:SI (match_dup 0) 2610: (match_operand:SI 2 "immediate_operand" "n"))) 2611: (match_operand:SI 3 "register_operand" "d")) 2612: (set (mem:SI (plus:SI (match_dup 0) 2613: (match_operand:SI 4 "immediate_operand" "n"))) 2614: (match_operand:SI 5 "register_operand" "d"))] 2615: "(i960_si_ti (operands[0], 0) && ((REGNO (operands[1]) & 3) == 0) 2616: && (REGNO (operands[1]) + 1 == REGNO (operands[3])) 2617: && (REGNO (operands[1]) + 2 == REGNO (operands[5])) 2618: && (INTVAL (operands[2]) == 4) 2619: && (INTVAL (operands[4]) == 8))" 2620: "stt %1,(%0)") 2621: 2622: ;; Matched 5/28/91 2623: (define_peephole 2624: [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "d") 2625: (match_operand:SI 1 "immediate_operand" "n"))) 2626: (match_operand:SI 2 "register_operand" "d")) 2627: (set (mem:SI (plus:SI (match_dup 0) 2628: (match_operand:SI 3 "immediate_operand" "n"))) 2629: (match_operand:SI 4 "register_operand" "d"))] 2630: "(i960_si_di (operands[0], operands[1]) && ((REGNO (operands[2]) & 1) == 0) 2631: && (REGNO (operands[2]) + 1 == REGNO (operands[4])) 2632: && (INTVAL (operands[1]) + 4 == INTVAL (operands[3])))" 2633: "stl %2,%1(%0)") 2634: 2635: ;; Matched 5/28/91 2636: (define_peephole 2637: [(set (mem:SI (match_operand:SI 0 "register_operand" "d")) 2638: (match_operand:SI 1 "register_operand" "d")) 2639: (set (mem:SI (plus:SI (match_dup 0) 2640: (match_operand:SI 2 "immediate_operand" "n"))) 2641: (match_operand:SI 3 "register_operand" "d"))] 2642: "(i960_si_di (operands[0], 0) && ((REGNO (operands[1]) & 1) == 0) 2643: && (REGNO (operands[1]) + 1 == REGNO (operands[3])) 2644: && (INTVAL (operands[2]) == 4))" 2645: "stl %1,(%0)")
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