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1.1 root 1: /* Definitions of target machine for GNU compiler. Sun 68000/68020 version.
2: Copyright (C) 1987, 1988 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 2, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: /* Note that some other tm.h files include this one and then override
22: many of the definitions that relate to assembler syntax. */
23:
24:
25: /* Names to predefine in the preprocessor for this target machine. */
26:
27: /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */
28:
29: /* Print subsidiary information on the compiler version in use. */
30: #ifdef MOTOROLA
31: #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)");
32: #else
33: #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)");
34: #endif
35:
36: /* Define SUPPORT_SUN_FPA to include support for generating code for
37: the Sun Floating Point Accelerator, an optional product for Sun 3
38: machines. By default, it is not defined. Avoid defining it unless
39: you need to output code for the Sun3+FPA architecture, as it has the
40: effect of slowing down the register set operations in hard-reg-set.h
41: (total number of registers will exceed number of bits in a long,
42: if defined, causing the set operations to expand to loops).
43: SUPPORT_SUN_FPA is typically defined in sun3.h. */
44:
45: /* Run-time compilation parameters selecting different hardware subsets. */
46:
47: extern int target_flags;
48:
49: /* Macros used in the machine description to test the flags. */
50:
51: /* Compile for a 68020 (not a 68000 or 68010). */
52: #define TARGET_68020 (target_flags & 1)
53:
54: /* Compile 68881 insns for floating point (not library calls). */
55: #define TARGET_68881 (target_flags & 2)
56:
57: /* Compile using 68020 bitfield insns. */
58: #define TARGET_BITFIELD (target_flags & 4)
59:
60: /* Compile using rtd insn calling sequence.
61: This will not work unless you use prototypes at least
62: for all functions that can take varying numbers of args. */
63: #define TARGET_RTD (target_flags & 8)
64:
65: /* Compile passing first two args in regs 0 and 1.
66: This exists only to test compiler features that will
67: be needed for RISC chips. It is not usable
68: and is not intended to be usable on this cpu. */
69: #define TARGET_REGPARM (target_flags & 020)
70:
71: /* Compile with 16-bit `int'. */
72: #define TARGET_SHORT (target_flags & 040)
73:
74: /* Compile with special insns for Sun FPA. */
75: #ifdef SUPPORT_SUN_FPA
76: #define TARGET_FPA (target_flags & 0100)
77: #else
78: #define TARGET_FPA 0
79: #endif
80:
81: /* Compile (actually, link) for Sun SKY board. */
82: #define TARGET_SKY (target_flags & 0200)
83:
1.1.1.4 ! root 84: /* Optimize for 68040, but still allow execution on 68020
! 85: (-m68020-40 or -m68040).
1.1.1.2 root 86: The 68040 will execute all 68030 and 68881/2 instructions, but some
1.1 root 87: of them must be emulated in software by the OS. When TARGET_68040 is
88: turned on, these instructions won't be used. This code will still
89: run on a 68030 and 68881/2. */
1.1.1.4 ! root 90: #define TARGET_68040 (target_flags & 01400)
1.1 root 91:
1.1.1.4 ! root 92: /* Use the 68040-only fp instructions (-m68040). */
1.1 root 93: #define TARGET_68040_ONLY (target_flags & 01000)
94:
95: /* Macro to define tables used to set the flags.
96: This is a list in braces of pairs in braces,
97: each pair being { "NAME", VALUE }
98: where VALUE is the bits to set or minus the bits to clear.
99: An empty string NAME is used to identify the default VALUE. */
100:
101: #define TARGET_SWITCHES \
102: { { "68020", 5}, \
103: { "c68020", 5}, \
104: { "68881", 2}, \
105: { "bitfield", 4}, \
106: { "68000", -5}, \
107: { "c68000", -5}, \
108: { "soft-float", -0102}, \
109: { "nobitfield", -4}, \
110: { "rtd", 8}, \
111: { "nortd", -8}, \
112: { "short", 040}, \
113: { "noshort", -040}, \
114: { "fpa", 0100}, \
115: { "nofpa", -0100}, \
116: { "sky", 0200}, \
117: { "nosky", -0200}, \
1.1.1.4 ! root 118: { "68020-40", 0407}, \
1.1 root 119: { "68030", -01400}, \
120: { "68030", 7}, \
1.1.1.4 ! root 121: { "68040", 01007}, \
1.1 root 122: { "", TARGET_DEFAULT}}
123: /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */
124:
125: #ifdef SUPPORT_SUN_FPA
126: /* Blow away 68881 flag silently on TARGET_FPA (since we can't clear
127: any bits in TARGET_SWITCHES above) */
128: #define OVERRIDE_OPTIONS \
129: { \
130: if (TARGET_FPA) target_flags &= ~2; \
131: if (! TARGET_68020 && flag_pic == 2) \
132: error("-fPIC is not currently supported on the 68000 or 68010\n"); \
133: }
134: #else
135: #define OVERRIDE_OPTIONS \
136: { \
137: if (! TARGET_68020 && flag_pic == 2) \
138: error("-fPIC is not currently supported on the 68000 or 68010\n"); \
139: }
140: #endif /* defined SUPPORT_SUN_FPA */
141:
142: /* target machine storage layout */
143:
144: /* Define this if most significant bit is lowest numbered
145: in instructions that operate on numbered bit-fields.
146: This is true for 68020 insns such as bfins and bfexts.
147: We make it true always by avoiding using the single-bit insns
148: except in special cases with constant bit numbers. */
149: #define BITS_BIG_ENDIAN 1
150:
151: /* Define this if most significant byte of a word is the lowest numbered. */
152: /* That is true on the 68000. */
153: #define BYTES_BIG_ENDIAN 1
154:
155: /* Define this if most significant word of a multiword number is the lowest
156: numbered. */
157: /* For 68000 we can decide arbitrarily
158: since there are no machine instructions for them.
159: So let's be consistent. */
160: #define WORDS_BIG_ENDIAN 1
161:
1.1.1.2 root 162: /* number of bits in an addressable storage unit */
1.1 root 163: #define BITS_PER_UNIT 8
164:
165: /* Width in bits of a "word", which is the contents of a machine register.
166: Note that this is not necessarily the width of data type `int';
167: if using 16-bit ints on a 68000, this would still be 32.
168: But on a machine with 16-bit registers, this would be 16. */
169: #define BITS_PER_WORD 32
170:
171: /* Width of a word, in units (bytes). */
172: #define UNITS_PER_WORD 4
173:
174: /* Width in bits of a pointer.
175: See also the macro `Pmode' defined below. */
176: #define POINTER_SIZE 32
177:
178: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
179: #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32)
180:
181: /* Boundary (in *bits*) on which stack pointer should be aligned. */
182: #define STACK_BOUNDARY 16
183:
184: /* Allocation boundary (in *bits*) for the code of a function. */
185: #define FUNCTION_BOUNDARY 16
186:
187: /* Alignment of field after `int : 0' in a structure. */
188: #define EMPTY_FIELD_BOUNDARY 16
189:
190: /* No data type wants to be aligned rounder than this. */
191: #define BIGGEST_ALIGNMENT 16
192:
1.1.1.2 root 193: /* Set this nonzero if move instructions will actually fail to work
1.1 root 194: when given unaligned data. */
1.1.1.2 root 195: #define STRICT_ALIGNMENT 1
1.1 root 196:
197: #define SELECT_RTX_SECTION(MODE, X) \
198: { \
199: if (!flag_pic) \
200: readonly_data_section(); \
201: else if (LEGITIMATE_PIC_OPERAND_P (X)) \
202: readonly_data_section(); \
203: else \
204: data_section(); \
205: }
206:
207: /* Define number of bits in most basic integer type.
208: (If undefined, default is BITS_PER_WORD). */
209:
210: #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32)
211:
212: /* Define these to avoid dependence on meaning of `int'.
213: Note that WCHAR_TYPE_SIZE is used in cexp.y,
214: where TARGET_SHORT is not available. */
215:
216: #define WCHAR_TYPE "long int"
217: #define WCHAR_TYPE_SIZE 32
218:
219: /* Standard register usage. */
220:
221: /* Number of actual hardware registers.
222: The hardware registers are assigned numbers for the compiler
223: from 0 to just below FIRST_PSEUDO_REGISTER.
224: All registers that the compiler knows about must be given numbers,
225: even those that are not normally considered general registers.
226: For the 68000, we give the data registers numbers 0-7,
227: the address registers numbers 010-017,
228: and the 68881 floating point registers numbers 020-027. */
229: #ifndef SUPPORT_SUN_FPA
230: #define FIRST_PSEUDO_REGISTER 24
231: #else
232: #define FIRST_PSEUDO_REGISTER 56
233: #endif
234:
235: /* This defines the register which is used to hold the offset table for PIC. */
236: #define PIC_OFFSET_TABLE_REGNUM 13
237:
238: /* Used to output a (use pic_offset_table_rtx) so that we
239: always save/restore a5 in functions that use PIC relocation
240: at *any* time during the compilation process. */
241: #define FINALIZE_PIC finalize_pic()
242:
243: #ifndef SUPPORT_SUN_FPA
244:
245: /* 1 for registers that have pervasive standard uses
246: and are not available for the register allocator.
247: On the 68000, only the stack pointer is such. */
248:
249: #define FIXED_REGISTERS \
250: {/* Data registers. */ \
251: 0, 0, 0, 0, 0, 0, 0, 0, \
252: \
253: /* Address registers. */ \
254: 0, 0, 0, 0, 0, 0, 0, 1, \
255: \
256: /* Floating point registers \
257: (if available). */ \
258: 0, 0, 0, 0, 0, 0, 0, 0 }
259:
260: /* 1 for registers not available across function calls.
261: These must include the FIXED_REGISTERS and also any
262: registers that can be used without being saved.
263: The latter must include the registers where values are returned
264: and the register where structure-value addresses are passed.
265: Aside from that, you can include as many other registers as you like. */
266: #define CALL_USED_REGISTERS \
267: {1, 1, 0, 0, 0, 0, 0, 0, \
268: 1, 1, 0, 0, 0, 0, 0, 1, \
269: 1, 1, 0, 0, 0, 0, 0, 0 }
270:
271: #else /* SUPPORT_SUN_FPA */
272:
273: /* 1 for registers that have pervasive standard uses
274: and are not available for the register allocator.
275: On the 68000, only the stack pointer is such. */
276:
277: /* fpa0 is also reserved so that it can be used to move shit back and
278: forth between high fpa regs and everything else. */
279:
280: #define FIXED_REGISTERS \
281: {/* Data registers. */ \
282: 0, 0, 0, 0, 0, 0, 0, 0, \
283: \
284: /* Address registers. */ \
285: 0, 0, 0, 0, 0, 0, 0, 1, \
286: \
287: /* Floating point registers \
288: (if available). */ \
289: 0, 0, 0, 0, 0, 0, 0, 0, \
290: \
291: /* Sun3 FPA registers. */ \
292: 1, 0, 0, 0, 0, 0, 0, 0, \
293: 0, 0, 0, 0, 0, 0, 0, 0, \
294: 0, 0, 0, 0, 0, 0, 0, 0, \
295: 0, 0, 0, 0, 0, 0, 0, 0 }
296:
297: /* 1 for registers not available across function calls.
298: These must include the FIXED_REGISTERS and also any
299: registers that can be used without being saved.
300: The latter must include the registers where values are returned
301: and the register where structure-value addresses are passed.
302: Aside from that, you can include as many other registers as you like. */
303: #define CALL_USED_REGISTERS \
304: {1, 1, 0, 0, 0, 0, 0, 0, \
305: 1, 1, 0, 0, 0, 0, 0, 1, \
306: 1, 1, 0, 0, 0, 0, 0, 0, \
307: /* FPA registers. */ \
308: 1, 1, 1, 1, 0, 0, 0, 0, \
309: 0, 0, 0, 0, 0, 0, 0, 0, \
310: 0, 0, 0, 0, 0, 0, 0, 0, \
311: 0, 0, 0, 0, 0, 0, 0, 0 }
312:
313: #endif /* defined SUPPORT_SUN_FPA */
314:
315:
316: /* Make sure everything's fine if we *don't* have a given processor.
317: This assumes that putting a register in fixed_regs will keep the
318: compiler's mitts completely off it. We don't bother to zero it out
319: of register classes. If neither TARGET_FPA or TARGET_68881 is set,
320: the compiler won't touch since no instructions that use these
321: registers will be valid.
322:
323: Reserve PIC_OFFSET_TABLE_REGNUM (a5) for doing PIC relocation if
324: position independent code is being generated by making it a
325: fixed register */
326:
327: #ifndef SUPPORT_SUN_FPA
328:
329: #define CONDITIONAL_REGISTER_USAGE \
330: { \
331: if (flag_pic) \
332: fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
333: }
334:
335: #else /* defined SUPPORT_SUN_FPA */
336:
337: #define CONDITIONAL_REGISTER_USAGE \
338: { \
339: int i; \
340: HARD_REG_SET x; \
341: if (!TARGET_FPA) \
342: { \
343: COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \
344: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
345: if (TEST_HARD_REG_BIT (x, i)) \
346: fixed_regs[i] = call_used_regs[i] = 1; \
347: } \
348: if (TARGET_FPA) \
349: { \
350: COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \
351: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \
352: if (TEST_HARD_REG_BIT (x, i)) \
353: fixed_regs[i] = call_used_regs[i] = 1; \
354: } \
355: if (flag_pic) \
356: fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
357: }
358:
359: #endif /* defined SUPPORT_SUN_FPA */
360:
361: /* Return number of consecutive hard regs needed starting at reg REGNO
362: to hold something of mode MODE.
363: This is ordinarily the length in words of a value of mode MODE
364: but can be less for certain modes in special long registers.
365:
366: On the 68000, ordinary registers hold 32 bits worth;
367: for the 68881 registers, a single register is always enough for
368: anything that can be stored in them at all. */
369: #define HARD_REGNO_NREGS(REGNO, MODE) \
370: ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \
371: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
372:
373: #ifndef SUPPORT_SUN_FPA
374:
375: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
376: On the 68000, the cpu registers can hold any mode but the 68881 registers
377: can hold only SFmode or DFmode. The 68881 registers can't hold anything
378: if 68881 use is disabled. */
379:
380: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
381: (((REGNO) < 16) \
382: || ((REGNO) < 24 \
383: && TARGET_68881 \
384: && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
385: || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT)))
386:
387: #else /* defined SUPPORT_SUN_FPA */
388:
389: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
390: On the 68000, the cpu registers can hold any mode but the 68881 registers
391: can hold only SFmode or DFmode. And the 68881 registers can't hold anything
392: if 68881 use is disabled. However, the Sun FPA register can
393: (apparently) hold whatever you feel like putting in them.
394: If using the fpa, don't put a double in d7/a0. */
395:
396: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
397: (((REGNO) < 16 \
398: && !(TARGET_FPA \
399: && GET_MODE_CLASS ((MODE)) != MODE_INT \
400: && GET_MODE_UNIT_SIZE ((MODE)) > 4 \
401: && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \
402: && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \
403: || ((REGNO) < 24 \
404: ? TARGET_68881 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \
405: || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \
406: : ((REGNO) < 56 ? TARGET_FPA : 0)))
407:
408: #endif /* defined SUPPORT_SUN_FPA */
409:
410: /* Value is 1 if it is a good idea to tie two pseudo registers
411: when one has mode MODE1 and one has mode MODE2.
412: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
413: for any hard reg, then this must be 0 for correct output. */
414: #define MODES_TIEABLE_P(MODE1, MODE2) \
415: (! TARGET_68881 \
416: || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \
417: || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
418: == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \
419: || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT)))
420:
421: /* Specify the registers used for certain standard purposes.
422: The values of these macros are register numbers. */
423:
424: /* m68000 pc isn't overloaded on a register. */
425: /* #define PC_REGNUM */
426:
427: /* Register to use for pushing function arguments. */
428: #define STACK_POINTER_REGNUM 15
429:
430: /* Base register for access to local variables of the function. */
431: #define FRAME_POINTER_REGNUM 14
432:
433: /* Value should be nonzero if functions must have frame pointers.
434: Zero means the frame pointer need not be set up (and parms
435: may be accessed via the stack pointer) in functions that seem suitable.
436: This is computed in `reload', in reload1.c. */
437: #define FRAME_POINTER_REQUIRED 0
438:
439: /* Base register for access to arguments of the function. */
440: #define ARG_POINTER_REGNUM 14
441:
442: /* Register in which static-chain is passed to a function. */
443: #define STATIC_CHAIN_REGNUM 8
444:
445: /* Register in which address to store a structure value
446: is passed to a function. */
447: #define STRUCT_VALUE_REGNUM 9
448:
449: /* Define the classes of registers for register constraints in the
450: machine description. Also define ranges of constants.
451:
452: One of the classes must always be named ALL_REGS and include all hard regs.
453: If there is more than one class, another class must be named NO_REGS
454: and contain no registers.
455:
456: The name GENERAL_REGS must be the name of a class (or an alias for
457: another name such as ALL_REGS). This is the class of registers
458: that is allowed by "g" or "r" in a register constraint.
459: Also, registers outside this class are allocated only when
460: instructions express preferences for them.
461:
462: The classes must be numbered in nondecreasing order; that is,
463: a larger-numbered class must never be contained completely
464: in a smaller-numbered class.
465:
466: For any two classes, it is very desirable that there be another
467: class that represents their union. */
468:
469: /* The 68000 has three kinds of registers, so eight classes would be
470: a complete set. One of them is not needed. */
471:
472: #ifndef SUPPORT_SUN_FPA
473:
474: enum reg_class {
475: NO_REGS, DATA_REGS,
476: ADDR_REGS, FP_REGS,
477: GENERAL_REGS, DATA_OR_FP_REGS,
478: ADDR_OR_FP_REGS, ALL_REGS,
479: LIM_REG_CLASSES };
480:
481: #define N_REG_CLASSES (int) LIM_REG_CLASSES
482:
483: /* Give names of register classes as strings for dump file. */
484:
485: #define REG_CLASS_NAMES \
486: { "NO_REGS", "DATA_REGS", \
487: "ADDR_REGS", "FP_REGS", \
488: "GENERAL_REGS", "DATA_OR_FP_REGS", \
489: "ADDR_OR_FP_REGS", "ALL_REGS" }
490:
491: /* Define which registers fit in which classes.
492: This is an initializer for a vector of HARD_REG_SET
493: of length N_REG_CLASSES. */
494:
495: #define REG_CLASS_CONTENTS \
496: { \
497: 0x00000000, /* NO_REGS */ \
498: 0x000000ff, /* DATA_REGS */ \
499: 0x0000ff00, /* ADDR_REGS */ \
500: 0x00ff0000, /* FP_REGS */ \
501: 0x0000ffff, /* GENERAL_REGS */ \
502: 0x00ff00ff, /* DATA_OR_FP_REGS */ \
503: 0x00ffff00, /* ADDR_OR_FP_REGS */ \
504: 0x00ffffff, /* ALL_REGS */ \
505: }
506:
507: /* The same information, inverted:
508: Return the class number of the smallest class containing
509: reg number REGNO. This could be a conditional expression
510: or could index an array. */
511:
512: #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1)
513:
514: #else /* defined SUPPORT_SUN_FPA */
515:
516: /*
517: * Notes on final choices:
518: *
519: * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything
520: * else.
521: * 2) Removed all unions that involve address registers with
522: * floating point registers (left in unions of address and data with
523: * floating point).
524: * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS.
525: * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS.
526: * 4) Left in everything else.
527: */
528: enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS,
529: FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS,
530: DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS,
531: GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS,
532: LIM_REG_CLASSES };
533:
534: #define N_REG_CLASSES (int) LIM_REG_CLASSES
535:
536: /* Give names of register classes as strings for dump file. */
537:
538: #define REG_CLASS_NAMES \
539: { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \
540: "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \
541: "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \
542: "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" }
543:
544: /* Define which registers fit in which classes.
545: This is an initializer for a vector of HARD_REG_SET
546: of length N_REG_CLASSES. */
547:
548: #define REG_CLASS_CONTENTS \
549: { \
550: {0, 0}, /* NO_REGS */ \
551: {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \
552: {0xff000000, 0x00ffffff}, /* FPA_REGS */ \
553: {0x00ff0000, 0x00000000}, /* FP_REGS */ \
554: {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \
555: {0x000000ff, 0x00000000}, /* DATA_REGS */ \
556: {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \
557: {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \
558: {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\
559: {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \
560: {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \
561: {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\
562: {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\
563: {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \
564: }
565:
566: /* The same information, inverted:
567: Return the class number of the smallest class containing
568: reg number REGNO. This could be a conditional expression
569: or could index an array. */
570:
571: extern enum reg_class regno_reg_class[];
572: #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3])
573:
574: #endif /* SUPPORT_SUN_FPA */
575:
576: /* The class value for index registers, and the one for base regs. */
577:
578: #define INDEX_REG_CLASS GENERAL_REGS
579: #define BASE_REG_CLASS ADDR_REGS
580:
581: /* Get reg_class from a letter such as appears in the machine description.
582: We do a trick here to modify the effective constraints on the
583: machine description; we zorch the constraint letters that aren't
584: appropriate for a specific target. This allows us to guarantee
585: that a specific kind of register will not be used for a given target
586: without fiddling with the register classes above. */
587:
588: #ifndef SUPPORT_SUN_FPA
589:
590: #define REG_CLASS_FROM_LETTER(C) \
591: ((C) == 'a' ? ADDR_REGS : \
592: ((C) == 'd' ? DATA_REGS : \
593: ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
594: NO_REGS) : \
595: NO_REGS)))
596:
597: #else /* defined SUPPORT_SUN_FPA */
598:
599: #define REG_CLASS_FROM_LETTER(C) \
600: ((C) == 'a' ? ADDR_REGS : \
601: ((C) == 'd' ? DATA_REGS : \
602: ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \
603: NO_REGS) : \
604: ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \
605: NO_REGS) : \
606: ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \
607: NO_REGS) : \
608: NO_REGS)))))
609:
610: #endif /* defined SUPPORT_SUN_FPA */
611:
612: /* The letters I, J, K, L and M in a register constraint string
613: can be used to stand for particular ranges of immediate operands.
614: This macro defines what the ranges are.
615: C is the letter, and VALUE is a constant value.
616: Return 1 if VALUE is in the range specified by C.
617:
618: For the 68000, `I' is used for the range 1 to 8
619: allowed as immediate shift counts and in addq.
620: `J' is used for the range of signed numbers that fit in 16 bits.
621: `K' is for numbers that moveq can't handle.
622: `L' is for range -8 to -1, range of values that can be added with subq. */
623:
624: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
625: ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
626: (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
627: (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
628: (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : 0)
629:
630: /*
631: * A small bit of explanation:
632: * "G" defines all of the floating constants that are *NOT* 68881
633: * constants. this is so 68881 constants get reloaded and the
634: * fpmovecr is used. "H" defines *only* the class of constants that
635: * the fpa can use, because these can be gotten at in any fpa
636: * instruction and there is no need to force reloads.
637: */
638: #ifndef SUPPORT_SUN_FPA
639: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
640: ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 )
641: #else /* defined SUPPORT_SUN_FPA */
642: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
643: ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \
644: (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0)
645: #endif /* defined SUPPORT_SUN_FPA */
646:
647: /* Given an rtx X being reloaded into a reg required to be
648: in class CLASS, return the class of reg to actually use.
649: In general this is just CLASS; but on some machines
650: in some cases it is preferable to use a more restrictive class.
651: On the 68000 series, use a data reg if possible when the
652: value is a constant in the range where moveq could be used
653: and we ensure that QImodes are reloaded into data regs.
654: Also, if a floating constant needs reloading, put it in memory
655: if possible. */
656:
657: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
658: ((GET_CODE (X) == CONST_INT \
659: && (unsigned) (INTVAL (X) + 0x80) < 0x100 \
660: && (CLASS) != ADDR_REGS) \
661: ? DATA_REGS \
662: : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \
663: ? DATA_REGS \
664: : (GET_CODE (X) == CONST_DOUBLE \
665: && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \
666: ? NO_REGS \
667: : (CLASS))
668:
669: /* Return the maximum number of consecutive registers
670: needed to represent mode MODE in a register of class CLASS. */
671: /* On the 68000, this is the size of MODE in words,
672: except in the FP regs, where a single reg is always enough. */
673: #ifndef SUPPORT_SUN_FPA
674:
675: #define CLASS_MAX_NREGS(CLASS, MODE) \
676: ((CLASS) == FP_REGS ? 1 \
677: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
678:
679: /* Moves between fp regs and other regs are two insns. */
680: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
681: (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
682: || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
683: ? 4 : 2)
684:
685: #else /* defined SUPPORT_SUN_FPA */
686:
687: #define CLASS_MAX_NREGS(CLASS, MODE) \
688: ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \
689: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
690:
691: /* Moves between fp regs and other regs are two insns. */
692: /* Likewise for high fpa regs and other regs. */
693: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \
694: ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \
695: || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \
696: || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \
697: || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \
698: ? 4 : 2)
699:
700: #endif /* define SUPPORT_SUN_FPA */
701:
702: /* Stack layout; function entry, exit and calling. */
703:
704: /* Define this if pushing a word on the stack
705: makes the stack pointer a smaller address. */
706: #define STACK_GROWS_DOWNWARD
707:
708: /* Nonzero if we need to generate stack-probe insns.
709: On most systems they are not needed.
710: When they are needed, define this as the stack offset to probe at. */
711: #define NEED_PROBE 0
712:
713: /* Define this if the nominal address of the stack frame
714: is at the high-address end of the local variables;
715: that is, each additional local variable allocated
716: goes at a more negative offset in the frame. */
717: #define FRAME_GROWS_DOWNWARD
718:
719: /* Offset within stack frame to start allocating local variables at.
720: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
721: first local allocated. Otherwise, it is the offset to the BEGINNING
722: of the first local allocated. */
723: #define STARTING_FRAME_OFFSET 0
724:
725: /* If we generate an insn to push BYTES bytes,
726: this says how many the stack pointer really advances by.
727: On the 68000, sp@- in a byte insn really pushes a word. */
728: #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1)
729:
730: /* Offset of first parameter from the argument pointer register value. */
731: #define FIRST_PARM_OFFSET(FNDECL) 8
732:
733: /* Value is the number of byte of arguments automatically
734: popped when returning from a subroutine call.
735: FUNTYPE is the data type of the function (as a tree),
736: or for a library call it is an identifier node for the subroutine name.
737: SIZE is the number of bytes of arguments passed on the stack.
738:
739: On the 68000, the RTS insn cannot pop anything.
740: On the 68010, the RTD insn may be used to pop them if the number
741: of args is fixed, but if the number is variable then the caller
742: must pop them all. RTD can't be used for library calls now
743: because the library is compiled with the Unix compiler.
744: Use of RTD is a selectable option, since it is incompatible with
745: standard Unix calling sequences. If the option is not selected,
746: the caller must always pop the args. */
747:
748: #define RETURN_POPS_ARGS(FUNTYPE,SIZE) \
749: ((TARGET_RTD && TREE_CODE (FUNTYPE) != IDENTIFIER_NODE \
750: && (TYPE_ARG_TYPES (FUNTYPE) == 0 \
751: || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \
752: == void_type_node))) \
753: ? (SIZE) : 0)
754:
755: /* Define how to find the value returned by a function.
756: VALTYPE is the data type of the value (as a tree).
757: If the precise function being called is known, FUNC is its FUNCTION_DECL;
758: otherwise, FUNC is 0. */
759:
760: /* On the 68000 the return value is in D0 regardless. */
761:
762: #define FUNCTION_VALUE(VALTYPE, FUNC) \
763: gen_rtx (REG, TYPE_MODE (VALTYPE), 0)
764:
765: /* Define how to find the value returned by a library function
766: assuming the value has mode MODE. */
767:
768: /* On the 68000 the return value is in D0 regardless. */
769:
770: #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0)
771:
772: /* 1 if N is a possible register number for a function value.
773: On the 68000, d0 is the only register thus used. */
774:
775: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0)
776:
777: /* Define this if PCC uses the nonreentrant convention for returning
778: structure and union values. */
779:
780: #define PCC_STATIC_STRUCT_RETURN
781:
782: /* 1 if N is a possible register number for function argument passing.
783: On the 68000, no registers are used in this way. */
784:
785: #define FUNCTION_ARG_REGNO_P(N) 0
786:
787: /* Define a data type for recording info about an argument list
788: during the scan of that argument list. This data type should
789: hold all necessary information about the function itself
790: and about the args processed so far, enough to enable macros
791: such as FUNCTION_ARG to determine where the next arg should go.
792:
793: On the m68k, this is a single integer, which is a number of bytes
794: of arguments scanned so far. */
795:
796: #define CUMULATIVE_ARGS int
797:
798: /* Initialize a variable CUM of type CUMULATIVE_ARGS
799: for a call to a function whose data type is FNTYPE.
800: For a library call, FNTYPE is 0.
801:
802: On the m68k, the offset starts at 0. */
803:
804: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
805: ((CUM) = 0)
806:
807: /* Update the data in CUM to advance over an argument
808: of mode MODE and data type TYPE.
809: (TYPE is null for libcalls where that information may not be available.) */
810:
811: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
812: ((CUM) += ((MODE) != BLKmode \
813: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \
814: : (int_size_in_bytes (TYPE) + 3) & ~3))
815:
816: /* Define where to put the arguments to a function.
817: Value is zero to push the argument on the stack,
818: or a hard register in which to store the argument.
819:
820: MODE is the argument's machine mode.
821: TYPE is the data type of the argument (as a tree).
822: This is null for libcalls where that information may
823: not be available.
824: CUM is a variable of type CUMULATIVE_ARGS which gives info about
825: the preceding args and about the function being called.
826: NAMED is nonzero if this argument is a named parameter
827: (otherwise it is an extra parameter matching an ellipsis). */
828:
829: /* On the 68000 all args are pushed, except if -mregparm is specified
830: then the first two words of arguments are passed in d0, d1.
831: *NOTE* -mregparm does not work.
832: It exists only to test register calling conventions. */
833:
834: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
835: ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0)
836:
837: /* For an arg passed partly in registers and partly in memory,
838: this is the number of registers used.
839: For args passed entirely in registers or entirely in memory, zero. */
840:
841: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
842: ((TARGET_REGPARM && (CUM) < 8 \
843: && 8 < ((CUM) + ((MODE) == BLKmode \
844: ? int_size_in_bytes (TYPE) \
845: : GET_MODE_SIZE (MODE)))) \
846: ? 2 - (CUM) / 4 : 0)
847:
848: /* Generate the assembly code for function entry. */
849: #define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue(FILE, SIZE)
850:
851: /* Output assembler code to FILE to increment profiler label # LABELNO
852: for profiling a function entry. */
853:
854: #define FUNCTION_PROFILER(FILE, LABELNO) \
855: asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO))
856:
857: /* Output assembler code to FILE to initialize this source file's
858: basic block profiling info, if that has not already been done. */
859:
860: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \
861: asm_fprintf (FILE, "\ttstl %LLPBX0\n\tbne %LLPI%d\n\tpea %LLPBX0\n\tjsr %U__bb_init_func\n\taddql %I4,%Rsp\n%LLPI%d:\n", \
862: LABELNO, LABELNO);
863:
864: /* Output assembler code to FILE to increment the entry-count for
865: the BLOCKNO'th basic block in this source file. */
866:
867: #define BLOCK_PROFILER(FILE, BLOCKNO) \
868: asm_fprintf (FILE, "\taddql %I1,%LLPBX2+%d\n", 4 * BLOCKNO)
869:
870: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
871: the stack pointer does not matter. The value is tested only in
872: functions that have frame pointers.
873: No definition is equivalent to always zero. */
874:
875: #define EXIT_IGNORE_STACK 1
876:
877: /* Generate the assembly code for function exit. */
878: #define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue (FILE, SIZE)
879:
880: /* This is a hook for other tm files to change. */
881: /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */
882:
883: /* Determine if the epilogue should be output as RTL.
884: You should override this if you define FUNCTION_EXTRA_EPILOGUE. */
885: #define USE_RETURN_INSN use_return_insn ()
886:
887: /* Store in the variable DEPTH the initial difference between the
888: frame pointer reg contents and the stack pointer reg contents,
889: as of the start of the function body. This depends on the layout
890: of the fixed parts of the stack frame and on how registers are saved.
891:
892: On the 68k, if we have a frame, we must add one word to its length
893: to allow for the place that a6 is stored when we do have a frame pointer.
894: Otherwise, we would need to compute the offset from the frame pointer
895: of a local variable as a function of frame_pointer_needed, which
896: is hard. */
897:
898: #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \
899: { int regno; \
900: int offset = -4; \
901: for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \
902: if (regs_ever_live[regno] && ! call_used_regs[regno]) \
903: offset += 12; \
904: for (regno = 0; regno < 16; regno++) \
905: if (regs_ever_live[regno] && ! call_used_regs[regno]) \
906: offset += 4; \
907: (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \
908: + (get_frame_size () == 0 ? 0 : 4)); \
909: }
910:
911: /* Output assembler code for a block containing the constant parts
912: of a trampoline, leaving space for the variable parts. */
913:
914: /* On the 68k, the trampoline looks like this:
915: mov @#.,a0
1.1.1.3 root 916: jsr @#___trampoline
917: jsr @#___trampoline
1.1 root 918: .long STATIC
919: .long FUNCTION
920: The reason for having three jsr insns is so that an entire line
921: of the instruction cache is filled in a predictable way
1.1.1.3 root 922: that will always be the same.
923:
924: We always use the assembler label ___trampoline
925: regardless of whether the system adds underscores. */
1.1 root 926:
927: #define TRAMPOLINE_TEMPLATE(FILE) \
928: { \
929: ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x207c)); \
930: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
931: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
1.1.1.3 root 932: ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4eb9)); \
933: ASM_OUTPUT_INT (FILE, gen_rtx (SYMBOL_REF, SImode, "*___trampoline"));\
934: ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4eb9)); \
935: ASM_OUTPUT_INT (FILE, gen_rtx (SYMBOL_REF, SImode, "*___trampoline"));\
1.1 root 936: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
937: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
938: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
939: ASM_OUTPUT_SHORT (FILE, const0_rtx); \
940: }
941:
942: /* Length in units of the trampoline for entering a nested function. */
943:
944: #define TRAMPOLINE_SIZE 26
945:
946: /* Alignment required for a trampoline. 16 is used to find the
947: beginning of a line in the instruction cache. */
948:
949: #define TRAMPOLINE_ALIGN 16
950:
951: /* Emit RTL insns to initialize the variable parts of a trampoline.
952: FNADDR is an RTX for the address of the function's pure code.
953: CXT is an RTX for the static chain value for the function. */
954:
955: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \
956: { \
957: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 2)), TRAMP); \
958: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 18)), CXT); \
959: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 22)), FNADDR); \
960: }
961:
962: /* This is the library routine that is used
963: to transfer control from the trampoline
964: to the actual nested function. */
965:
966: /* A colon is used with no explicit operands
967: to cause the template string to be scanned for %-constructs. */
968: /* The function name __transfer_from_trampoline is not actually used.
969: The function definition just permits use of "asm with operands"
970: (though the operand list is empty). */
971: #define TRANSFER_FROM_TRAMPOLINE \
972: void \
973: __transfer_from_trampoline () \
974: { \
975: register char *a0 asm ("%a0"); \
1.1.1.3 root 976: asm (GLOBAL_ASM_OP " ___trampoline"); \
1.1 root 977: asm ("___trampoline:"); \
1.1.1.2 root 978: asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \
979: asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \
1.1 root 980: asm ("rts":); \
981: }
982:
983: /* Addressing modes, and classification of registers for them. */
984:
985: #define HAVE_POST_INCREMENT
986: /* #define HAVE_POST_DECREMENT */
987:
988: #define HAVE_PRE_DECREMENT
989: /* #define HAVE_PRE_INCREMENT */
990:
991: /* Macros to check register numbers against specific register classes. */
992:
993: /* These assume that REGNO is a hard or pseudo reg number.
994: They give nonzero only if REGNO is a hard reg of the suitable class
995: or a pseudo reg currently allocated to a suitable hard reg.
996: Since they use reg_renumber, they are safe only once reg_renumber
997: has been allocated, which happens in local-alloc.c. */
998:
999: #define REGNO_OK_FOR_INDEX_P(REGNO) \
1000: ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16)
1001: #define REGNO_OK_FOR_BASE_P(REGNO) \
1002: (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8)
1003: #define REGNO_OK_FOR_DATA_P(REGNO) \
1004: ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8)
1005: #define REGNO_OK_FOR_FP_P(REGNO) \
1006: (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8)
1007: #ifdef SUPPORT_SUN_FPA
1008: #define REGNO_OK_FOR_FPA_P(REGNO) \
1009: (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56))
1010: #endif
1011:
1012: /* Now macros that check whether X is a register and also,
1013: strictly, whether it is in a specified class.
1014:
1015: These macros are specific to the 68000, and may be used only
1016: in code for printing assembler insns and in conditions for
1017: define_optimization. */
1018:
1019: /* 1 if X is a data register. */
1020:
1021: #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X)))
1022:
1023: /* 1 if X is an fp register. */
1024:
1025: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X)))
1026:
1027: /* 1 if X is an address register */
1028:
1029: #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X)))
1030:
1031: #ifdef SUPPORT_SUN_FPA
1032: /* 1 if X is a register in the Sun FPA. */
1033: #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X)))
1034: #else
1035: /* Answer must be no if we don't have an FPA. */
1036: #define FPA_REG_P(X) 0
1037: #endif
1038:
1039: /* Maximum number of registers that can appear in a valid memory address. */
1040:
1041: #define MAX_REGS_PER_ADDRESS 2
1042:
1043: /* Recognize any constant value that is a valid address. */
1044:
1045: #define CONSTANT_ADDRESS_P(X) CONSTANT_P (X)
1046:
1047: /* Nonzero if the constant value X is a legitimate general operand.
1048: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1049:
1050: #define LEGITIMATE_CONSTANT_P(X) 1
1051:
1052: /* Nonzero if the constant value X is a legitimate general operand
1053: when generating PIC code. It is given that flag_pic is on and
1054: that X satisfies CONSTANT_P or is a CONST_DOUBLE. */
1055:
1056: #define LEGITIMATE_PIC_OPERAND_P(X) \
1057: (! symbolic_operand (X, VOIDmode))
1058:
1059: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1060: and check its validity for a certain class.
1061: We have two alternate definitions for each of them.
1062: The usual definition accepts all pseudo regs; the other rejects
1063: them unless they have been allocated suitable hard regs.
1064: The symbol REG_OK_STRICT causes the latter definition to be used.
1065:
1066: Most source files want to accept pseudo regs in the hope that
1067: they will get allocated to the class that the insn wants them to be in.
1068: Source files for reload pass need to be strict.
1069: After reload, it makes no difference, since pseudo regs have
1070: been eliminated by then. */
1071:
1072: #ifndef REG_OK_STRICT
1073:
1074: /* Nonzero if X is a hard reg that can be used as an index
1075: or if it is a pseudo reg. */
1076: #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8)
1077: /* Nonzero if X is a hard reg that can be used as a base reg
1078: or if it is a pseudo reg. */
1079: #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0)
1080:
1081: #else
1082:
1083: /* Nonzero if X is a hard reg that can be used as an index. */
1084: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1085: /* Nonzero if X is a hard reg that can be used as a base reg. */
1086: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1087:
1088: #endif
1089:
1090: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression
1091: that is a valid memory address for an instruction.
1092: The MODE argument is the machine mode for the MEM expression
1093: that wants to use this address.
1094:
1095: When generating PIC, an address involving a SYMBOL_REF is legitimate
1096: if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF.
1097: We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses,
1098: and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF.
1099:
1100: Likewise for a LABEL_REF when generating PIC.
1101:
1102: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */
1103:
1104: #define INDIRECTABLE_1_ADDRESS_P(X) \
1105: ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \
1106: || (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \
1107: || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \
1108: && REG_P (XEXP (X, 0)) \
1109: && REG_OK_FOR_BASE_P (XEXP (X, 0))) \
1110: || (GET_CODE (X) == PLUS \
1111: && REG_P (XEXP (X, 0)) && REG_OK_FOR_BASE_P (XEXP (X, 0)) \
1112: && GET_CODE (XEXP (X, 1)) == CONST_INT \
1113: && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000) \
1114: || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1115: && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \
1116: || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \
1117: && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) \
1118:
1119: #if 0
1120: /* This should replace the last two (non-pic) lines
1121: except that Sun's assembler does not seem to handle such operands. */
1122: && (TARGET_68020 ? CONSTANT_ADDRESS_P (XEXP (X, 1)) \
1123: : (GET_CODE (XEXP (X, 1)) == CONST_INT \
1124: && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000))))
1125: #endif
1126:
1127:
1128: #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \
1129: { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; }
1130:
1.1.1.4 ! root 1131: /* Only labels on dispatch tables are valid for indexing from. */
! 1132: #define GO_IF_INDEXABLE_BASE(X, ADDR) \
! 1133: { rtx temp; \
! 1134: if (GET_CODE (X) == LABEL_REF \
! 1135: && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \
! 1136: && GET_CODE (temp) == JUMP_INSN \
! 1137: && (GET_CODE (PATTERN (temp)) == ADDR_VEC \
! 1138: || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \
! 1139: goto ADDR; \
1.1 root 1140: if (GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) goto ADDR; }
1141:
1142: #define GO_IF_INDEXING(X, ADDR) \
1143: { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \
1144: { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \
1145: if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \
1146: { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } }
1147:
1148: #define GO_IF_INDEXED_ADDRESS(X, ADDR) \
1149: { GO_IF_INDEXING (X, ADDR); \
1150: if (GET_CODE (X) == PLUS) \
1151: { if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1152: && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \
1153: { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \
1154: if (GET_CODE (XEXP (X, 0)) == CONST_INT \
1155: && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \
1156: { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } }
1157:
1158: #define LEGITIMATE_INDEX_REG_P(X) \
1159: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \
1160: || (GET_CODE (X) == SIGN_EXTEND \
1161: && GET_CODE (XEXP (X, 0)) == REG \
1162: && GET_MODE (XEXP (X, 0)) == HImode \
1163: && REG_OK_FOR_INDEX_P (XEXP (X, 0))))
1164:
1165: #define LEGITIMATE_INDEX_P(X) \
1166: (LEGITIMATE_INDEX_REG_P (X) \
1167: || (TARGET_68020 && GET_CODE (X) == MULT \
1168: && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \
1169: && GET_CODE (XEXP (X, 1)) == CONST_INT \
1170: && (INTVAL (XEXP (X, 1)) == 2 \
1171: || INTVAL (XEXP (X, 1)) == 4 \
1172: || INTVAL (XEXP (X, 1)) == 8)))
1173:
1174: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1175: { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \
1176: GO_IF_INDEXED_ADDRESS (X, ADDR); }
1177:
1178: /* Try machine-dependent ways of modifying an illegitimate address
1179: to be legitimate. If we find one, return the new, valid address.
1180: This macro is used in only one place: `memory_address' in explow.c.
1181:
1182: OLDX is the address as it was before break_out_memory_refs was called.
1183: In some cases it is useful to look at this to decide what needs to be done.
1184:
1185: MODE and WIN are passed so that this macro can use
1186: GO_IF_LEGITIMATE_ADDRESS.
1187:
1188: It is always safe for this macro to do nothing. It exists to recognize
1189: opportunities to optimize the output.
1190:
1191: For the 68000, we handle X+REG by loading X into a register R and
1192: using R+REG. R will go in an address reg and indexing will be used.
1193: However, if REG is a broken-out memory address or multiplication,
1194: nothing needs to be done because REG can certainly go in an address reg. */
1195:
1196: #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; }
1197: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \
1198: { register int ch = (X) != (OLDX); \
1199: if (GET_CODE (X) == PLUS) \
1200: { int copied = 0; \
1201: if (GET_CODE (XEXP (X, 0)) == MULT) \
1202: { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \
1203: if (GET_CODE (XEXP (X, 1)) == MULT) \
1204: { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \
1205: if (ch && GET_CODE (XEXP (X, 1)) == REG \
1206: && GET_CODE (XEXP (X, 0)) == REG) \
1207: goto WIN; \
1208: if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \
1209: if (GET_CODE (XEXP (X, 0)) == REG \
1210: || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \
1211: && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \
1212: && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \
1213: { register rtx temp = gen_reg_rtx (Pmode); \
1214: register rtx val = force_operand (XEXP (X, 1), 0); \
1215: emit_move_insn (temp, val); \
1216: COPY_ONCE (X); \
1217: XEXP (X, 1) = temp; \
1218: goto WIN; } \
1219: else if (GET_CODE (XEXP (X, 1)) == REG \
1220: || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \
1221: && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1222: && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \
1223: { register rtx temp = gen_reg_rtx (Pmode); \
1224: register rtx val = force_operand (XEXP (X, 0), 0); \
1225: emit_move_insn (temp, val); \
1226: COPY_ONCE (X); \
1227: XEXP (X, 0) = temp; \
1228: goto WIN; }}}
1229:
1230: /* Go to LABEL if ADDR (a legitimate address expression)
1231: has an effect that depends on the machine mode it is used for.
1232: On the 68000, only predecrement and postincrement address depend thus
1233: (the amount of decrement or increment being the length of the operand). */
1234:
1235: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \
1236: if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL
1237:
1238: /* Specify the machine mode that this machine uses
1239: for the index in the tablejump instruction. */
1240: #define CASE_VECTOR_MODE HImode
1241:
1242: /* Define this if the tablejump instruction expects the table
1243: to contain offsets from the address of the table.
1244: Do not define this if the table should contain absolute addresses. */
1245: #define CASE_VECTOR_PC_RELATIVE
1246:
1247: /* Specify the tree operation to be used to convert reals to integers. */
1248: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
1249:
1250: /* This is the kind of divide that is easiest to do in the general case. */
1251: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
1252:
1253: /* Define this as 1 if `char' should by default be signed; else as 0. */
1254: #define DEFAULT_SIGNED_CHAR 1
1255:
1256: /* Don't cse the address of the function being compiled. */
1257: #define NO_RECURSIVE_FUNCTION_CSE
1258:
1259: /* Max number of bytes we can move from memory to memory
1260: in one reasonably fast instruction. */
1261: #define MOVE_MAX 4
1262:
1263: /* Define this if zero-extension is slow (more than one real instruction). */
1264: #define SLOW_ZERO_EXTEND
1265:
1266: /* Nonzero if access to memory by bytes is slow and undesirable. */
1267: #define SLOW_BYTE_ACCESS 0
1268:
1269: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
1270: is done just by pretending it is already truncated. */
1271: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
1272:
1273: /* We assume that the store-condition-codes instructions store 0 for false
1274: and some other value for true. This is the value stored for true. */
1275:
1276: #define STORE_FLAG_VALUE -1
1277:
1278: /* When a prototype says `char' or `short', really pass an `int'. */
1279: #define PROMOTE_PROTOTYPES
1280:
1281: /* Specify the machine mode that pointers have.
1282: After generation of rtl, the compiler makes no further distinction
1283: between pointers and any other objects of this machine mode. */
1284: #define Pmode SImode
1285:
1286: /* A function address in a call instruction
1287: is a byte address (for indexing purposes)
1288: so give the MEM rtx a byte's mode. */
1289: #define FUNCTION_MODE QImode
1290:
1291: /* Compute the cost of computing a constant rtl expression RTX
1292: whose rtx-code is CODE. The body of this macro is a portion
1293: of a switch statement. If the code is computed here,
1294: return it with a return statement. Otherwise, break from the switch. */
1295:
1.1.1.3 root 1296: #define CONST_COSTS(RTX,CODE,OUTER_CODE) \
1.1 root 1297: case CONST_INT: \
1298: /* Constant zero is super cheap due to clr instruction. */ \
1299: if (RTX == const0_rtx) return 0; \
1300: /* Constants between -128 and 127 are cheap due to moveq */ \
1301: if (INTVAL (RTX) >= -128 && INTVAL (RTX) <= 127) return 1; \
1302: /* Constants between -136 and 254 are easily generated */ \
1303: /* by intelligent uses of moveq, add[q], and subq */ \
1.1.1.3 root 1304: if ((OUTER_CODE) == SET && INTVAL (RTX) >= -136 \
1305: && INTVAL (RTX) <= 254) return 2; \
1.1 root 1306: case CONST: \
1307: case LABEL_REF: \
1308: case SYMBOL_REF: \
1309: return 3; \
1310: case CONST_DOUBLE: \
1311: return 5;
1312:
1313: /* Compute the cost of various arithmetic operations.
1314: These are vaguely right for a 68020. */
1315: /* The costs for long multiply have been adjusted to
1316: work properly in synth_mult on the 68020,
1317: relative to an average of the time for add and the time for shift,
1318: taking away a little more because sometimes move insns are needed. */
1.1.1.3 root 1319: #define MULL_COST (TARGET_68040 ? 5 : 13)
1320: #define MULW_COST (TARGET_68040 ? 3 : 8)
1.1 root 1321:
1.1.1.3 root 1322: #define RTX_COSTS(X,CODE,OUTER_CODE) \
1.1 root 1323: case PLUS: \
1324: /* An lea costs about three times as much as a simple add. */ \
1325: if (GET_MODE (X) == SImode \
1326: && GET_CODE (XEXP (X, 0)) == REG \
1327: && GET_CODE (XEXP (X, 1)) == MULT \
1328: && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \
1329: && GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT \
1330: && (INTVAL (XEXP (XEXP (X, 1), 1)) == 2 \
1331: || INTVAL (XEXP (XEXP (X, 1), 1)) == 4 \
1332: || INTVAL (XEXP (XEXP (X, 1), 1)) == 8)) \
1333: return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \
1334: break; \
1335: case ASHIFT: \
1336: case ASHIFTRT: \
1337: case LSHIFT: \
1338: case LSHIFTRT: \
1339: /* A shift by a big integer takes an extra instruction. */ \
1340: if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1.1.1.2 root 1341: && (INTVAL (XEXP (X, 1)) == 16)) \
1342: return COSTS_N_INSNS (2); /* clrw;swap */ \
1343: if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1.1 root 1344: && !(INTVAL (XEXP (X, 1)) > 0 \
1345: && INTVAL (XEXP (X, 1)) <= 8)) \
1346: return COSTS_N_INSNS (3); /* lsr #i,dn */ \
1347: break; \
1348: case MULT: \
1349: if (GET_CODE (XEXP (x, 1)) == CONST_INT \
1350: && exact_log2 (INTVAL (XEXP (x, 1))) >= 0) \
1.1.1.2 root 1351: { \
1352: /* A shift by a big integer takes an extra instruction. */ \
1353: if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1354: && (INTVAL (XEXP (X, 1)) == (1 << 16))) \
1355: return COSTS_N_INSNS (2); /* clrw;swap */ \
1356: if (GET_CODE (XEXP (X, 1)) == CONST_INT \
1357: && !(INTVAL (XEXP (X, 1)) > 1 \
1358: && INTVAL (XEXP (X, 1)) <= 256)) \
1359: return COSTS_N_INSNS (3); /* lsr #i,dn */ \
1360: break; \
1361: } \
1.1 root 1362: else if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1.1.1.3 root 1363: return COSTS_N_INSNS (MULW_COST); \
1.1 root 1364: else \
1.1.1.3 root 1365: return COSTS_N_INSNS (MULL_COST); \
1.1 root 1366: break; \
1367: case DIV: \
1368: case UDIV: \
1369: case MOD: \
1370: case UMOD: \
1371: if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \
1372: return COSTS_N_INSNS (27); /* div.w */ \
1373: return COSTS_N_INSNS (43); /* div.l */
1374:
1375: /* Tell final.c how to eliminate redundant test instructions. */
1376:
1377: /* Here we define machine-dependent flags and fields in cc_status
1378: (see `conditions.h'). */
1379:
1380: /* Set if the cc value is actually in the 68881, so a floating point
1381: conditional branch must be output. */
1382: #define CC_IN_68881 04000
1383:
1384: /* Store in cc_status the expressions that the condition codes will
1385: describe after execution of an instruction whose pattern is EXP.
1386: Do not alter them if the instruction would not alter the cc's. */
1387:
1388: /* On the 68000, all the insns to store in an address register fail to
1389: set the cc's. However, in some cases these instructions can make it
1390: possibly invalid to use the saved cc's. In those cases we clear out
1391: some or all of the saved cc's so they won't be used. */
1392:
1393: #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN)
1394:
1395: #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \
1396: { if (cc_prev_status.flags & CC_IN_68881) \
1397: return FLOAT; \
1398: if (cc_prev_status.flags & CC_NO_OVERFLOW) \
1399: return NO_OV; \
1400: return NORMAL; }
1401:
1402: /* Control the assembler format that we output. */
1403:
1404: /* Output at beginning of assembler file. */
1405:
1406: #define ASM_FILE_START(FILE) \
1407: fprintf (FILE, "#NO_APP\n");
1408:
1409: /* Output to assembler file text saying following lines
1410: may contain character constants, extra white space, comments, etc. */
1411:
1412: #define ASM_APP_ON "#APP\n"
1413:
1414: /* Output to assembler file text saying following lines
1415: no longer contain unusual constructs. */
1416:
1417: #define ASM_APP_OFF "#NO_APP\n"
1418:
1419: /* Output before read-only data. */
1420:
1421: #define TEXT_SECTION_ASM_OP ".text"
1422:
1423: /* Output before writable data. */
1424:
1425: #define DATA_SECTION_ASM_OP ".data"
1426:
1427: /* Here are four prefixes that are used by asm_fprintf to
1428: facilitate customization for alternate assembler syntaxes.
1429: Machines with no likelihood of an alternate syntax need not
1430: define these and need not use asm_fprintf. */
1431:
1432: /* The prefix for register names. Note that REGISTER_NAMES
1433: is supposed to include this prefix. */
1434:
1435: #define REGISTER_PREFIX ""
1436:
1437: /* The prefix for local labels. You should be able to define this as
1438: an empty string, or any arbitrary string (such as ".", ".L%", etc)
1439: without having to make any other changes to account for the specific
1440: definition. Note it is a string literal, not interpreted by printf
1441: and friends. */
1442:
1443: #define LOCAL_LABEL_PREFIX ""
1444:
1445: /* The prefix to add to user-visible assembler symbols. */
1446:
1447: #define USER_LABEL_PREFIX "_"
1448:
1449: /* The prefix for immediate operands. */
1450:
1451: #define IMMEDIATE_PREFIX "#"
1452:
1453: /* How to refer to registers in assembler output.
1454: This sequence is indexed by compiler's hard-register-number (see above). */
1455:
1456: #ifndef SUPPORT_SUN_FPA
1457:
1458: #define REGISTER_NAMES \
1459: {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1460: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1461: "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" }
1462:
1463: #else /* SUPPORTED_SUN_FPA */
1464:
1465: #define REGISTER_NAMES \
1466: {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \
1467: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \
1468: "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \
1469: "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \
1470: "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \
1471: "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \
1472: "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" }
1473:
1474: #endif /* defined SUPPORT_SUN_FPA */
1475:
1476: /* How to renumber registers for dbx and gdb.
1477: On the Sun-3, the floating point registers have numbers
1478: 18 to 25, not 16 to 23 as they do in the compiler. */
1479:
1480: #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2)
1481:
1482: /* This is how to output the definition of a user-level label named NAME,
1483: such as the label on a static function or variable NAME. */
1484:
1485: #define ASM_OUTPUT_LABEL(FILE,NAME) \
1486: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0)
1487:
1488: /* This is how to output a command to make the user-level label named NAME
1489: defined for reference from other files. */
1490:
1.1.1.3 root 1491: #define GLOBAL_ASM_OP ".globl"
1.1 root 1492: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \
1.1.1.3 root 1493: do { fprintf (FILE, "%s ", GLOBAL_ASM_OP); \
1494: assemble_name (FILE, NAME); \
1495: fputs ("\n", FILE);} while (0)
1.1 root 1496:
1497: /* This is how to output a reference to a user-level label named NAME.
1498: `assemble_name' uses this. */
1499:
1500: #define ASM_OUTPUT_LABELREF(FILE,NAME) \
1.1.1.2 root 1501: asm_fprintf (FILE, "%0U%s", NAME)
1.1 root 1502:
1503: /* This is how to output an internal numbered label where
1504: PREFIX is the class of label and NUM is the number within the class. */
1505:
1506: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \
1.1.1.2 root 1507: asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM)
1.1 root 1508:
1509: /* This is how to store into the string LABEL
1510: the symbol_ref name of an internal numbered label where
1511: PREFIX is the class of label and NUM is the number within the class.
1512: This is suitable for output with `assemble_name'. */
1513:
1514: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
1515: sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM)
1516:
1517: /* This is how to output an assembler line defining a `double' constant. */
1518:
1519: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \
1520: fprintf (FILE, "\t.double 0r%.20g\n", (VALUE))
1521:
1522: /* This is how to output an assembler line defining a `float' constant. */
1523:
1524: /* Sun's assembler can't handle floating constants written as floating.
1525: However, when cross-compiling, always use that in case format differs. */
1526:
1527: #ifdef CROSS_COMPILE
1528:
1529: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1530: fprintf (FILE, "\t.float 0r%.10g\n", (VALUE))
1531:
1532: #else
1533:
1534: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \
1535: do { union { float f; long l;} tem; \
1536: tem.f = (VALUE); \
1537: fprintf (FILE, "\t.long 0x%x\n", tem.l); \
1538: } while (0)
1539:
1.1.1.3 root 1540: #endif /* not CROSS_COMPILE */
1.1 root 1541:
1542: /* This is how to output an assembler line defining an `int' constant. */
1543:
1544: #define ASM_OUTPUT_INT(FILE,VALUE) \
1545: ( fprintf (FILE, "\t.long "), \
1546: output_addr_const (FILE, (VALUE)), \
1547: fprintf (FILE, "\n"))
1548:
1549: /* Likewise for `char' and `short' constants. */
1550:
1551: #define ASM_OUTPUT_SHORT(FILE,VALUE) \
1552: ( fprintf (FILE, "\t.word "), \
1553: output_addr_const (FILE, (VALUE)), \
1554: fprintf (FILE, "\n"))
1555:
1556: #define ASM_OUTPUT_CHAR(FILE,VALUE) \
1557: ( fprintf (FILE, "\t.byte "), \
1558: output_addr_const (FILE, (VALUE)), \
1559: fprintf (FILE, "\n"))
1560:
1561: /* This is how to output an assembler line for a numeric constant byte. */
1562:
1563: #define ASM_OUTPUT_BYTE(FILE,VALUE) \
1564: fprintf (FILE, "\t.byte 0x%x\n", (VALUE))
1565:
1566: /* This is how to output an insn to push a register on the stack.
1567: It need not be very fast code. */
1568:
1569: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \
1570: asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO])
1571:
1572: /* This is how to output an insn to pop a register from the stack.
1573: It need not be very fast code. */
1574:
1575: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \
1576: asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO])
1577:
1578: /* This is how to output an element of a case-vector that is absolute.
1579: (The 68000 does not use such vectors,
1580: but we must define this macro anyway.) */
1581:
1582: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \
1583: asm_fprintf (FILE, "\t.long %LL%d\n", VALUE)
1584:
1585: /* This is how to output an element of a case-vector that is relative. */
1586:
1587: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \
1588: asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL)
1589:
1590: /* This is how to output an assembler line
1591: that says to advance the location counter
1592: to a multiple of 2**LOG bytes. */
1593:
1.1.1.2 root 1594: /* We don't have a way to align to more than a two-byte boundary, so do the
1595: best we can and don't complain. */
1.1 root 1596: #define ASM_OUTPUT_ALIGN(FILE,LOG) \
1.1.1.2 root 1597: if ((LOG) >= 1) \
1598: fprintf (FILE, "\t.even\n");
1.1 root 1599:
1600: #define ASM_OUTPUT_SKIP(FILE,SIZE) \
1601: fprintf (FILE, "\t.skip %u\n", (SIZE))
1602:
1603: /* This says how to output an assembler line
1604: to define a global common symbol. */
1605:
1606: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \
1607: ( fputs (".comm ", (FILE)), \
1608: assemble_name ((FILE), (NAME)), \
1609: fprintf ((FILE), ",%u\n", (ROUNDED)))
1610:
1611: /* This says how to output an assembler line
1612: to define a local common symbol. */
1613:
1614: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \
1615: ( fputs (".lcomm ", (FILE)), \
1616: assemble_name ((FILE), (NAME)), \
1617: fprintf ((FILE), ",%u\n", (ROUNDED)))
1618:
1619: /* Store in OUTPUT a string (made with alloca) containing
1620: an assembler-name for a local static variable named NAME.
1621: LABELNO is an integer which is different for each call. */
1622:
1623: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
1624: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
1625: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
1626:
1627: /* Define the parentheses used to group arithmetic operations
1628: in assembler code. */
1629:
1630: #define ASM_OPEN_PAREN "("
1631: #define ASM_CLOSE_PAREN ")"
1632:
1633: /* Define results of standard character escape sequences. */
1634: #define TARGET_BELL 007
1635: #define TARGET_BS 010
1636: #define TARGET_TAB 011
1637: #define TARGET_NEWLINE 012
1638: #define TARGET_VT 013
1639: #define TARGET_FF 014
1640: #define TARGET_CR 015
1641:
1642: /* Output a float value (represented as a C double) as an immediate operand.
1643: This macro is a 68k-specific macro. */
1644: #define ASM_OUTPUT_FLOAT_OPERAND(FILE,VALUE) \
1645: asm_fprintf (FILE, "%I0r%.9g", (VALUE))
1646:
1647: /* Output a double value (represented as a C double) as an immediate operand.
1648: This macro is a 68k-specific macro. */
1649: #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \
1650: asm_fprintf (FILE, "%I0r%.20g", (VALUE))
1651:
1652: /* Print operand X (an rtx) in assembler syntax to file FILE.
1653: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified.
1654: For `%' followed by punctuation, CODE is the punctuation and X is null.
1655:
1656: On the 68000, we use several CODE characters:
1657: '.' for dot needed in Motorola-style opcode names.
1658: '-' for an operand pushing on the stack:
1659: sp@-, -(sp) or -(%sp) depending on the style of syntax.
1660: '+' for an operand pushing on the stack:
1661: sp@+, (sp)+ or (%sp)+ depending on the style of syntax.
1662: '@' for a reference to the top word on the stack:
1663: sp@, (sp) or (%sp) depending on the style of syntax.
1664: '#' for an immediate operand prefix (# in MIT and Motorola syntax
1665: but & in SGS syntax).
1.1.1.2 root 1666: '!' for the fpcr register (used in some float-to-fixed conversions).
1.1 root 1667: '$' for the letter `s' in an op code, but only on the 68040.
1668: '&' for the letter `d' in an op code, but only on the 68040.
1669:
1670: 'b' for byte insn (no effect, on the Sun; this is for the ISI).
1671: 'd' to force memory addressing to be absolute, not relative.
1672: 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex)
1673: 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather
1674: than directly). Second part of 'y' below.
1675: 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex),
1676: or print pair of registers as rx:ry.
1677: 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs
1678: CONST_DOUBLE's as SunFPA constant RAM registers if
1679: possible, so it should not be used except for the SunFPA. */
1680:
1681: #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \
1682: ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \
1683: || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \
1684: || (CODE) == '$' || (CODE) == '&')
1685:
1686: #ifdef HOST_WORDS_BIG_ENDIAN
1687: #define PRINT_OPERAND_EXTRACT_FLOAT(X) \
1688: u.i[0] = CONST_DOUBLE_LOW (X); u.i[1] = CONST_DOUBLE_HIGH (X);
1689: #else
1690: #define PRINT_OPERAND_EXTRACT_FLOAT(X) \
1691: u.i[0] = CONST_DOUBLE_HIGH (X); u.i[1] = CONST_DOUBLE_LOW (X);
1692: #endif
1693:
1.1.1.3 root 1694: #ifdef CROSS_COMPILE
1.1 root 1695: #define PRINT_OPERAND_PRINT_FLOAT(CODE, FILE) \
1696: ASM_OUTPUT_FLOAT_OPERAND (FILE, u1.f);
1697: #else
1698: #define PRINT_OPERAND_PRINT_FLOAT(CODE, FILE) \
1699: { if (CODE == 'f') \
1700: ASM_OUTPUT_FLOAT_OPERAND (FILE, u1.f); \
1701: else \
1702: asm_fprintf (FILE, "%I0x%x", u1.i); }
1703: #endif
1704:
1705: /* A C compound statement to output to stdio stream STREAM the
1706: assembler syntax for an instruction operand X. X is an RTL
1707: expression.
1708:
1709: CODE is a value that can be used to specify one of several ways
1710: of printing the operand. It is used when identical operands
1711: must be printed differently depending on the context. CODE
1712: comes from the `%' specification that was used to request
1713: printing of the operand. If the specification was just `%DIGIT'
1714: then CODE is 0; if the specification was `%LTR DIGIT' then CODE
1715: is the ASCII code for LTR.
1716:
1717: If X is a register, this macro should print the register's name.
1718: The names can be found in an array `reg_names' whose type is
1719: `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
1720:
1721: When the machine description has a specification `%PUNCT' (a `%'
1722: followed by a punctuation character), this macro is called with
1723: a null pointer for X and the punctuation character for CODE.
1724:
1725: See m68k.c for the m68k specific codes. */
1726:
1727: #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
1728:
1729: /* A C compound statement to output to stdio stream STREAM the
1730: assembler syntax for an instruction operand that is a memory
1731: reference whose address is ADDR. ADDR is an RTL expression.
1732:
1733: On some machines, the syntax for a symbolic address depends on
1734: the section that the address refers to. On these machines,
1735: define the macro `ENCODE_SECTION_INFO' to store the information
1736: into the `symbol_ref', and then check for it here. */
1737:
1738: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
1739:
1740:
1741: /* Define functions defined in aux-output.c and used in templates. */
1742:
1743: extern char *output_move_double ();
1744: extern char *output_move_const_single ();
1745: extern char *output_move_const_double ();
1746: extern char *output_btst ();
1747:
1748: /*
1749: Local variables:
1750: version-control: t
1751: End:
1752: */
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