--- gcc/config/m68k.md	2018/04/24 16:53:26	1.1
+++ gcc/config/m68k.md	2018/04/24 16:56:38	1.1.1.3
@@ -714,7 +714,10 @@
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=g")
 	(const_int 0))]
-  ""
+  ;; clr insns on 68000 read before writing.
+  ;; This isn't so on the 68010, but we have no alternative for it.
+  "(TARGET_68020
+    || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
   "*
 {
   if (ADDRESS_REG_P (operands[0]))
@@ -749,7 +752,12 @@
     {
       if (operands[1] == const0_rtx
 	  && (DATA_REG_P (operands[0])
-	      || GET_CODE (operands[0]) == MEM))
+	      || GET_CODE (operands[0]) == MEM)
+	  /* clr insns on 68000 read before writing.
+	     This isn't so on the 68010, but we have no alternative for it.  */
+	  && (TARGET_68020
+	      || !(GET_CODE (operands[0]) == MEM
+		   && MEM_VOLATILE_P (operands[0]))))
 	return \"clr%.l %0\";
       else if (DATA_REG_P (operands[0])
 	       && INTVAL (operands[1]) < 128
@@ -791,7 +799,12 @@
     {
       if (operands[1] == const0_rtx
 	  && (DATA_REG_P (operands[0])
-	      || GET_CODE (operands[0]) == MEM))
+	      || GET_CODE (operands[0]) == MEM)
+	  /* clr insns on 68000 read before writing.
+	     This isn't so on the 68010, but we have no alternative for it.  */
+	  && (TARGET_68020
+	      || !(GET_CODE (operands[0]) == MEM
+		   && MEM_VOLATILE_P (operands[0]))))
 	return \"clr%.w %0\";
       else if (DATA_REG_P (operands[0])
 	       && INTVAL (operands[1]) < 128
@@ -856,7 +869,12 @@
     {
       if (operands[1] == const0_rtx
 	  && (DATA_REG_P (operands[0])
-	      || GET_CODE (operands[0]) == MEM))
+	      || GET_CODE (operands[0]) == MEM)
+	  /* clr insns on 68000 read before writing.
+	     This isn't so on the 68010, but we have no alternative for it.  */
+	  && (TARGET_68020
+	      || !(GET_CODE (operands[0]) == MEM
+		   && MEM_VOLATILE_P (operands[0]))))
 	return \"clr%.w %0\";
     }
   return \"move%.w %1,%0\";
@@ -892,11 +910,20 @@
       output_asm_insn (\"move%.w %1,%-\;move%.b %2,%0\;addq%.w %#2,%3\", xoperands);
       return \"\";
     }
-  if (operands[1] == const0_rtx)
-    return \"clr%.b %0\";
-  if (GET_CODE (operands[1]) == CONST_INT
-      && INTVAL (operands[1]) == -1)
-    return \"st %0\";
+  /* clr and st insns on 68000 read before writing.
+     This isn't so on the 68010, but we have no alternative for it.  */
+  if (TARGET_68020
+      || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
+    {
+      if (operands[1] == const0_rtx)
+	return \"clr%.b %0\";
+      if (GET_CODE (operands[1]) == CONST_INT
+	  && INTVAL (operands[1]) == -1)
+	{
+	  CC_STATUS_INIT;
+	  return \"st %0\";
+	}
+    }
   if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
     return \"move%.l %1,%0\";
   if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
@@ -910,7 +937,11 @@
   ""
   "*
 {
-  if (operands[1] == const0_rtx)
+  if (operands[1] == const0_rtx
+      /* clr insns on 68000 read before writing.
+         This isn't so on the 68010, but we have no alternative for it.  */
+      && (TARGET_68020
+          || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
     return \"clr%.b %0\";
   return \"move%.b %1,%0\";
 }")
@@ -1201,9 +1232,13 @@
   else if (GET_CODE (operands[0]) == MEM
 	   && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
     {
-      if (REGNO (XEXP (XEXP (operands[0], 0), 0))
-	  == STACK_POINTER_REGNUM)
-	return \"clr%.w %-\;move%.b %1,%0\";
+      if (REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM)
+	{
+	  output_asm_insn (\"clr%.w @-\", operands);
+	  operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
+				 plus_constant (stack_pointer_rtx, 1));
+	  return \"move%.b %1,%0\";
+	}
       else
 	return \"move%.b %1,%0\;clr%.b %0\";
     }
@@ -1357,7 +1392,7 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:SF 0 "register_operand" "=x,y")
+  [(set (match_operand:SF 0 "general_operand" "=x,y")
 	(float_truncate:SF
 	  (match_operand:DF 1 "general_operand" "xH,rmF")))]
   "TARGET_FPA"
@@ -1403,7 +1438,7 @@
   "")
 
 (define_insn ""
-  [(set (match_operand:DF 0 "register_operand" "=y,x")
+  [(set (match_operand:DF 0 "general_operand" "=y,x")
 	(float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
   "TARGET_FPA"
   "fpltod %1,%0")
@@ -2829,6 +2864,7 @@
        || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
   "*
 {
+  cc_status.flags |= CC_NOT_NEGATIVE;
   if (REG_P (operands[1]))
     {
       if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
@@ -2893,7 +2929,11 @@
 			 (match_operand:SI 2 "general_operand" "di,di")
 			 (match_operand:SI 3 "general_operand" "di,di")))]
   "TARGET_68020 && TARGET_BITFIELD"
-  "bfextu %1{%b3:%b2},%0")
+  "*
+{
+  cc_status.flags |= CC_NOT_NEGATIVE;
+  return \"bfextu %1{%b3:%b2},%0\";
+}")
 
 (define_insn ""
   [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
@@ -2961,7 +3001,11 @@
 			 (match_operand:SI 2 "general_operand" "di")
 			 (match_operand:SI 3 "general_operand" "di")))]
   "TARGET_68020 && TARGET_BITFIELD"
-  "bfextu %1{%b3:%b2},%0")
+  "*
+{
+  cc_status.flags |= CC_NOT_NEGATIVE;
+  return \"bfextu %1{%b3:%b2},%0\";
+}")
 
 (define_insn ""
   [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
@@ -3632,6 +3676,10 @@
    (use (label_ref (match_operand 1 "" "")))]
   ""
   "*
+{
+#ifdef ASM_RETURN_CASE_JUMP
+ ASM_RETURN_CASE_JUMP;
+#else
 #ifdef SGS
 #ifdef ASM_OUTPUT_CASE_LABEL
   return \"jmp 6(%%pc,%0.w)\";
@@ -3645,7 +3693,8 @@
   return \"jmp pc@(2,%0:w)\";
 #endif
 #endif
-")
+#endif /* no ASM_RETURN_CASE_JUMP */
+}")
 
 ;; Unconditional and other jump instructions
 (define_insn "jump"