--- gcc/config/m68k.md 2018/04/24 16:56:38 1.1.1.3 +++ gcc/config/m68k.md 2018/04/24 17:01:55 1.1.1.5 @@ -1115,7 +1115,12 @@ "* { if (GET_CODE (operands[0]) == REG) - return \"move%.l %1,%0\"; + { + /* Must clear condition codes, since the mov.l bases them on + the entire 32 bits, not just the desired 8 bits. */ + CC_STATUS_INIT; + return \"move%.l %1,%0\"; + } if (GET_CODE (operands[1]) == MEM) operands[1] = adj_offsettable_operand (operands[1], 3); return \"move%.b %1,%0\"; @@ -1131,9 +1136,19 @@ if (GET_CODE (operands[0]) == REG && (GET_CODE (operands[1]) == MEM || GET_CODE (operands[1]) == CONST_INT)) - return \"move%.w %1,%0\"; + { + /* Must clear condition codes, since the mov.w bases them on + the entire 16 bits, not just the desired 8 bits. */ + CC_STATUS_INIT; + return \"move%.w %1,%0\"; + } if (GET_CODE (operands[0]) == REG) - return \"move%.l %1,%0\"; + { + /* Must clear condition codes, since the mov.l bases them on + the entire 32 bits, not just the desired 8 bits. */ + CC_STATUS_INIT; + return \"move%.l %1,%0\"; + } if (GET_CODE (operands[1]) == MEM) operands[1] = adj_offsettable_operand (operands[1], 1); return \"move%.b %1,%0\"; @@ -1147,7 +1162,12 @@ "* { if (GET_CODE (operands[0]) == REG) - return \"move%.l %1,%0\"; + { + /* Must clear condition codes, since the mov.l bases them on + the entire 32 bits, not just the desired 8 bits. */ + CC_STATUS_INIT; + return \"move%.l %1,%0\"; + } if (GET_CODE (operands[1]) == MEM) operands[1] = adj_offsettable_operand (operands[1], 2); return \"move%.w %1,%0\"; @@ -1234,7 +1254,7 @@ { if (REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM) { - output_asm_insn (\"clr%.w @-\", operands); + output_asm_insn (\"clr%.w %-\", operands); operands[0] = gen_rtx (MEM, GET_MODE (operands[0]), plus_constant (stack_pointer_rtx, 1)); return \"move%.b %1,%0\"; @@ -2630,7 +2650,9 @@ (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m") (const_int 24))))] "(GET_CODE (operands[0]) == CONST_INT - && (INTVAL (operands[0]) & ~0xff) == 0)" + && (INTVAL (operands[0]) & ~0xff) == 0 + && GET_CODE (XEXP (operands[1], 0)) != POST_INC + && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)" "* cc_status.flags |= CC_REVERSED; #ifdef HPUX_ASM return \"cmp%.b %1,%0\"; @@ -2644,7 +2666,9 @@ (const_int 24)) (match_operand:QI 1 "general_operand" "i")))] "(GET_CODE (operands[1]) == CONST_INT - && (INTVAL (operands[1]) & ~0xff) == 0)" + && (INTVAL (operands[1]) & ~0xff) == 0 + && GET_CODE (XEXP (operands[0], 0)) != POST_INC + && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC)" "* #ifdef HPUX_ASM return \"cmp%.b %0,%1\"; @@ -2658,7 +2682,9 @@ (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m") (const_int 24))))] "(GET_CODE (operands[0]) == CONST_INT - && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0)" + && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0 + && GET_CODE (XEXP (operands[1], 0)) != POST_INC + && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)" "* cc_status.flags |= CC_REVERSED; #ifdef HPUX_ASM return \"cmp%.b %1,%0\"; @@ -2672,7 +2698,9 @@ (const_int 24)) (match_operand:QI 1 "general_operand" "i")))] "(GET_CODE (operands[1]) == CONST_INT - && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0)" + && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0 + && GET_CODE (XEXP (operands[0], 0)) != POST_INC + && GET_CODE (XEXP (operands[0], 0)) != PRE_DEC)" "* #ifdef HPUX_ASM return \"cmp%.b %0,%1\"; @@ -3712,7 +3740,7 @@ (define_insn "" [(set (pc) (if_then_else - (ne (compare (plus:HI (match_operand:HI 0 "general_operand" "g") + (ne (compare (plus:HI (match_operand:HI 0 "general_operand" "=g") (const_int -1)) (const_int -1)) (const_int 0)) @@ -3757,7 +3785,7 @@ (define_insn "" [(set (pc) (if_then_else - (ne (compare (plus:SI (match_operand:SI 0 "general_operand" "g") + (ne (compare (plus:SI (match_operand:SI 0 "general_operand" "=g") (const_int -1)) (const_int -1)) (const_int 0)) @@ -3805,7 +3833,7 @@ (define_insn "" [(set (pc) (if_then_else - (ge (plus:SI (match_operand:SI 0 "general_operand" "g") + (ge (plus:SI (match_operand:SI 0 "general_operand" "=g") (const_int -1)) (const_int 0)) (label_ref (match_operand 1 "" ""))