--- gcc/config/m68k.md 2018/04/24 17:53:39 1.1.1.2 +++ gcc/config/m68k.md 2018/04/24 17:58:23 1.1.1.3 @@ -394,7 +394,7 @@ #ifdef SGS_CMP_ORDER return \"cmp%.l %d1,%d0\"; #else - return \"cmp%.l %d0,%d1\"; + return \"cmp%.l %d0,%d1\"; #endif } #ifdef SGS_CMP_ORDER @@ -419,7 +419,7 @@ #ifdef SGS_CMP_ORDER return \"cmp%.w %d1,%d0\"; #else - return \"cmp%.w %d0,%d1\"; + return \"cmp%.w %d0,%d1\"; #endif } #ifdef SGS_CMP_ORDER @@ -759,9 +759,9 @@ { operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); #if defined(MOTOROLA) && !defined(CRDS) - return \"moveq%.l %1,%0;addq%.w %#8,%0\"; + return \"moveq%.l %1,%0\;addq%.w %#8,%0\"; #else - return \"moveq %1,%0;addq%.w %#8,%0\"; + return \"moveq %1,%0\;addq%.w %#8,%0\"; #endif } else if (DATA_REG_P (operands[0]) @@ -786,9 +786,9 @@ { operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) / 2); #if defined(MOTOROLA) && !defined(CRDS) - return \"moveq%.l %1,%0;add%.w %0,%0\"; + return \"moveq%.l %1,%0\;add%.w %0,%0\"; #else - return \"moveq %1,%0;add%.w %0,%0\"; + return \"moveq %1,%0\;add%.w %0,%0\"; #endif } else if (ADDRESS_REG_P (operands[0]) @@ -872,9 +872,11 @@ #else /* SGS_SWITCH_TABLES or not MOTOROLA */ ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", CODE_LABEL_NUMBER (XEXP (labelref, 0))); - /* For sake of 3b1, set flag saying we need to define the symbol - LD%n (with value L%n-LI%n) at the end of the switch table. */ - RTX_INTEGRATED_P (next_real_insn (XEXP (labelref, 0))) = 1; +#ifdef SGS_SWITCH_TABLES + /* Set flag saying we need to define the symbol + LD%n (with value L%n-LI%n) at the end of the switch table. */ + switch_table_difference_label_flag = 1; +#endif /* SGS_SWITCH_TABLES */ #endif /* SGS_SWITCH_TABLES or not MOTOROLA */ } #endif /* SGS_NO_LI */ @@ -1265,11 +1267,13 @@ ;; Patterns to recognize zero-extend insns produced by the combiner. ;; We don't allow both operands in memory, because of aliasing problems. +;; Explicitly disallow two memory operands via the condition since reloading +;; of this case will result in worse code than the uncombined patterns. (define_insn "" [(set (match_operand:SI 0 "general_operand" "=do<>,d<") - (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rn,m")))] - "" + (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] + "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" "* { if (DATA_REG_P (operands[0])) @@ -1297,8 +1301,8 @@ (define_insn "" [(set (match_operand:HI 0 "general_operand" "=do<>,d") - (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "dn,m")))] - "" + (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] + "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" "* { if (DATA_REG_P (operands[0])) @@ -1337,8 +1341,8 @@ (define_insn "" [(set (match_operand:SI 0 "general_operand" "=do<>,d") - (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "dn,m")))] - "" + (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] + "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" "* { if (DATA_REG_P (operands[0])) @@ -1391,7 +1395,7 @@ (define_insn "extendhisi2" [(set (match_operand:SI 0 "general_operand" "=*d,a") (sign_extend:SI - (match_operand:HI 1 "nonimmediate_operand" "0,rmn")))] + (match_operand:HI 1 "nonimmediate_operand" "0,rm")))] "" "* { @@ -1755,7 +1759,7 @@ && TARGET_68020) { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); - return \"addq%.w %#8,%0; addq%.w %2,%0\"; + return \"addq%.w %#8,%0\;addq%.w %2,%0\"; } if (INTVAL (operands[2]) < -8 && INTVAL (operands[2]) >= -16 @@ -1764,7 +1768,7 @@ { operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]) - 8); - return \"subq%.w %#8,%0; subq%.w %2,%0\"; + return \"subq%.w %#8,%0\;subq%.w %2,%0\"; } #endif if (ADDRESS_REG_P (operands[0]) @@ -1813,7 +1817,7 @@ return \"subq%.w %2,%0\"; } /* On everything except the 68000 it is faster to use two - addqw insttuctions to add a small integer (8 < N <= 16) + addqw instructions to add a small integer (8 < N <= 16) to an address register. Likewise for subqw. */ if (INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 @@ -1821,7 +1825,7 @@ && TARGET_68020) { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); - return \"addq%.w %#8,%0; addq%.w %2,%0\"; + return \"addq%.w %#8,%0\;addq%.w %2,%0\"; } if (INTVAL (operands[2]) < -8 && INTVAL (operands[2]) >= -16 @@ -1830,7 +1834,7 @@ { operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]) - 8); - return \"subq%.w %#8,%0; subq%.w %2,%0\"; + return \"subq%.w %#8,%0\;subq%.w %2,%0\"; } } #endif @@ -1873,7 +1877,7 @@ return \"subq%.w %1,%0\"; } /* On everything except the 68000 it is faster to use two - addqw instuctions to add a small integer (8 < N <= 16) + addqw instructions to add a small integer (8 < N <= 16) to an address register. Likewise for subqw. */ if (INTVAL (operands[1]) > 8 && INTVAL (operands[1]) <= 16 @@ -1881,7 +1885,7 @@ && TARGET_68020) { operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); - return \"addq%.w %#8,%0; addq%.w %1,%0\"; + return \"addq%.w %#8,%0\;addq%.w %1,%0\"; } if (INTVAL (operands[1]) < -8 && INTVAL (operands[1]) >= -16 @@ -1890,7 +1894,7 @@ { operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]) - 8); - return \"subq%.w %#8,%0; subq%.w %1,%0\"; + return \"subq%.w %#8,%0\;subq%.w %1,%0\"; } } #endif @@ -1927,7 +1931,7 @@ return \"subq%.w %1,%0\"; } /* On everything except the 68000 it is faster to use two - addqw instuctions to add a small integer (8 < N <= 16) + addqw instructions to add a small integer (8 < N <= 16) to an address register. Likewise for subqw. */ if (INTVAL (operands[1]) > 8 && INTVAL (operands[1]) <= 16 @@ -1935,7 +1939,7 @@ && TARGET_68020) { operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); - return \"addq%.w %#8,%0; addq%.w %1,%0\"; + return \"addq%.w %#8,%0\;addq%.w %1,%0\"; } if (INTVAL (operands[1]) < -8 && INTVAL (operands[1]) >= -16 @@ -1944,7 +1948,7 @@ { operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1]) - 8); - return \"subq%.w %#8,%0; subq%.w %1,%0\"; + return \"subq%.w %#8,%0\;subq%.w %1,%0\"; } } #endif @@ -2154,7 +2158,7 @@ && TARGET_68020) { operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); - return \"subq%.w %#8,%0; subq%.w %2,%0\"; + return \"subq%.w %#8,%0\;subq%.w %2,%0\"; } #endif if (ADDRESS_REG_P (operands[0]) @@ -2169,7 +2173,7 @@ [(set (match_operand:SI 0 "general_operand" "=a") (minus:SI (match_operand:SI 1 "general_operand" "0") (sign_extend:SI - (match_operand:HI 2 "nonimmediate_operand" "rmn"))))] + (match_operand:HI 2 "nonimmediate_operand" "rm"))))] "" "sub%.w %2,%0") @@ -2292,7 +2296,7 @@ (mult:SI (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0")) (sign_extend:SI - (match_operand:HI 2 "nonimmediate_operand" "dmn"))))] + (match_operand:HI 2 "nonimmediate_operand" "dm"))))] "" "* { @@ -2330,7 +2334,7 @@ (mult:SI (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "%0")) (zero_extend:SI - (match_operand:HI 2 "nonimmediate_operand" "dmn"))))] + (match_operand:HI 2 "nonimmediate_operand" "dm"))))] "" "* { @@ -2366,7 +2370,7 @@ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) (zero_extend:DI - (match_operand:SI 2 "general_operand" ""))) 1)) + (match_operand:SI 2 "nonimmediate_operand" ""))) 1)) (set (subreg:SI (match_dup 0) 0) (subreg:SI (mult:DI (zero_extend:DI @@ -2382,7 +2386,7 @@ (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%0")) (zero_extend:DI - (match_operand:SI 2 "general_operand" "dmsK"))) 1)) + (match_operand:SI 2 "nonimmediate_operand" "dm"))) 1)) (set (match_operand:SI 3 "register_operand" "=d") (subreg:SI (mult:DI (zero_extend:DI @@ -2392,6 +2396,22 @@ "TARGET_68020" "mulu%.l %2,%3:%0") +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (subreg:SI + (mult:DI (zero_extend:DI + (match_operand:SI 1 "register_operand" "%0")) + (match_operand:SI 2 "immediate_operand" "sK")) 1)) + (set (match_operand:SI 3 "register_operand" "=d") + (subreg:SI + (mult:DI (zero_extend:DI + (match_dup 1)) + (match_dup 2)) 0))] + "TARGET_68020 + && (GET_CODE (operands[2]) != CONST_INT + || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))" + "mulu%.l %2,%3:%0") + (define_expand "mulsidi3" [(parallel [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1) @@ -2399,7 +2419,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) (sign_extend:DI - (match_operand:SI 2 "general_operand" ""))) 1)) + (match_operand:SI 2 "nonimmediate_operand" ""))) 1)) (set (subreg:SI (match_dup 0) 0) (subreg:SI (mult:DI (sign_extend:DI @@ -2415,7 +2435,7 @@ (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "%0")) (sign_extend:DI - (match_operand:SI 2 "general_operand" "dmKs"))) 1)) + (match_operand:SI 2 "nonimmediate_operand" "dm"))) 1)) (set (match_operand:SI 3 "register_operand" "=d") (subreg:SI (mult:DI (sign_extend:DI @@ -2425,6 +2445,22 @@ "TARGET_68020" "muls%.l %2,%3:%0") +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=d") + (subreg:SI + (mult:DI (sign_extend:DI + (match_operand:SI 1 "register_operand" "%0")) + (match_operand:SI 2 "immediate_operand" "sK")) 1)) + (set (match_operand:SI 3 "register_operand" "=d") + (subreg:SI + (mult:DI (sign_extend:DI + (match_dup 1)) + (match_dup 2)) 0))] + "TARGET_68020 + && (GET_CODE (operands[2]) != CONST_INT + || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))" + "muls%.l %2,%3:%0") + (define_expand "muldf3" [(set (match_operand:DF 0 "general_operand" "") (mult:DF (match_operand:DF 1 "general_operand" "") @@ -2446,7 +2482,7 @@ if (rtx_equal_p (operands[0], operands[2])) return \"fpmul%.d %y1,%0\"; if (which_alternative == 0) - return \"fpmul3%.d %w2,%w1,%0\"; + return \"fpmul3%.d %w2,%w1,%0\"; return \"fpmul3%.d %x2,%x1,%0\"; }") @@ -2665,10 +2701,17 @@ "TARGET_68881" "* { +#ifdef FSGLDIV_USE_S + if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) + return (TARGET_68040_ONLY + ? \"fsdiv%.s %2,%0\" + : \"fsgldiv%.s %2,%0\"); +#else if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) return (TARGET_68040_ONLY ? \"fsdiv%.x %2,%0\" : \"fsgldiv%.x %2,%0\"); +#endif return (TARGET_68040_ONLY ? \"fsdiv%.s %f2,%0\" : \"fsgldiv%.s %f2,%0\"); @@ -3131,6 +3174,20 @@ return \"f%&neg%.d %f1,%0\"; }") +;; Sqrt instruction for the 68881 + +(define_insn "sqrtdf2" + [(set (match_operand:DF 0 "general_operand" "=f") + (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))] + "TARGET_68881" + "* +{ + if (FP_REG_P (operands[1])) + return \"fsqrt%.x %1,%0\"; + else + return \"fsqrt%.d %1,%0\"; +}") + ;; Absolute value instructions (define_expand "abssf2" @@ -4751,7 +4808,7 @@ { xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xoperands[1]) - 8); - output_asm_insn (\"addq%.w %#8,%0; addq%.w %1,%0\", xoperands); + output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands); } else #endif @@ -4788,7 +4845,7 @@ { xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (xoperands[1]) - 8); - output_asm_insn (\"addq%.w %#8,%0; addq%.w %1,%0\", xoperands); + output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands); } else #endif @@ -4841,7 +4898,7 @@ ;; jCC label ;; ;; Which moves the jCC condition outside the inner loop for free. -;; +;; (define_peephole [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" [(cc0) (const_int 0)])