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1.1 root 1: ;;- Machine description for GNU compiler
2: ;;- Motorola 68000 Version
3: ;; Copyright (C) 1987, 1988 Free Software Foundation, Inc.
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 1, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21:
22: ;;- instruction definitions
23:
24: ;;- @@The original PO technology requires these to be ordered by speed,
25: ;;- @@ so that assigner will pick the fastest.
26:
27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28:
29: ;;- When naming insn's (operand 0 of define_insn) be careful about using
30: ;;- names from other targets machine descriptions.
31:
32: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
33: ;;- updates for most instructions.
34:
35: ;;- Operand classes for the register allocator:
36: ;;- 'a' one of the address registers can be used.
37: ;;- 'd' one of the data registers can be used.
38: ;;- 'f' one of the m68881 registers can be used
39: ;;- 'r' either a data or an address register can be used.
40: ;;- 'x' if one of the Sun FPA registers
41: ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
42:
43: ;;- Immediate Floating point operator constraints
44: ;;- 'G' a floating point constant that is *NOT* one of the standard
45: ;; 68881 constant values (to force calling output_move_const_double
46: ;; to get it from rom if it is a 68881 constant).
47: ;;- 'H' one of the standard FPA constant values
48: ;;
49: ;; See the functions standard_XXX_constant_p in output-m68k.c for more
50: ;; info.
51:
52: ;;- Immediate integer operand constraints:
53: ;;- 'I' 1 .. 8
54: ;;- 'J' -32768 .. 32767
55: ;;- 'K' -128 .. 127
56: ;;- 'L' -8 .. -1
57:
58: ;;- FPA port explanation:
59:
60: ;;- Usage of the Sun FPA and the 68881 together
61:
62: ;;- The current port of gcc to the sun fpa disallows use of the m68881
63: ;;- instructions completely if code is targetted for the fpa. This is
64: ;;- for the following reasons:
65:
66: ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
67: ;;- can, the 68881 otherwise, and data registers only if you are
68: ;;- forced to it) is a bitch with the current constraint scheme,
69: ;;- especially since it would have to work for any combination of
70: ;;- -mfpa, -m68881.
71:
72: ;;- 2) There are no instructions to move between the two types of
73: ;;- registers; the stack must be used as an intermediary.
74:
75: ;;- It could indeed be done; I think the best way would be to have
76: ;;- seperate patterns for TARGET_FPA (which implies a 68881),
77: ;;- TARGET_68881, and no floating point co-processor. Use
78: ;;- define_expands for all of the named instruction patterns, and
79: ;;- include code in the FPA instruction to deal with the 68881 with
80: ;;- preferences specifically set to favor the fpa. Some of this has
81: ;;- already been done:
82: ;;-
83: ;;- 1) Separation of most of the patterns out into a TARGET_FPA
84: ;;- case and a TARGET_68881 case (the exceptions are the patterns
85: ;;- which would need one define_expand and three define_insn's under
86: ;;- it (with alot of duplicate code between them) to replace the
87: ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
88: ;;- first two patterns in the md.
89: ;;-
90: ;;- Some would still have to be done:
91: ;;-
92: ;;- 1) Add code to the fpa patterns which correspond to 68881
93: ;;- patterns to deal with the 68881 case (including preferences!).
94: ;;- What you might actually do here is combine the fpa and 68881 code
95: ;;- back together into one pattern for those instructions where it's
96: ;;- absolutely necessary and save yourself some duplicate code. I'm
97: ;;- not completely sure as to whether you could get away with doing
98: ;;- this only for the mov* insns, or if you'd have to do it for all
99: ;;- named insns.
100: ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
101: ;;- moving between fpa regs and 68881 regs.
102:
103: ;;- Since the fpa is more powerful than the 68881 and also has more
104: ;;- registers, and since I think the reultant md would be medium ugly
105: ;;- (lot's of duplicate code, ugly constraint strings), I elected not
106: ;;- to do this change.
107:
108: ;;- Another reason why someone *might* want to do the change is to
109: ;;- control which register classes are accessed in a slightly cleaner
110: ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
111: ;;- the internals manual.
112:
113: ;;- Yet another reason why someone might want to do this change is to
114: ;;- allow use of some of the 68881 insns which have no equivalent on
115: ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
116:
117: ;;- If this is ever done, don't forget to change tm-sun3.h so that
118: ;;- it *will* define __HAVE_68881__ when the FPA is in use.
119:
120: ;;- Condition code hack
121:
122: ;;- When a floating point compare is done in the fpa, the resulting
123: ;;- condition codes are left in the fpastatus register. The values in
124: ;;- this register must be moved into the 68000 cc register before any
125: ;;- jump is executed. Once this has been done, regular jump
126: ;;- instructions are fine (ie. floating point jumps are not necessary.
127: ;;- They are only done if the cc is in the 68881).
128:
129: ;;- The instructions that move the fpastatus register to the 68000
130: ;;- register clobber a data register (the move cannot be done direct).
131: ;;- These instructions might be bundled either with the compare
132: ;;- instruction, or the branch instruction. If we were using both the
133: ;;- fpa and the 68881 together, we would wish to only mark the
134: ;;- register clobbered if we were doing the compare in the fpa, but I
135: ;;- think that that decision (whether to clobber the register or not)
136: ;;- must be done before register allocation (makes sense) and hence we
137: ;;- can't know if the floating point compare will be done in the fpa
138: ;;- or the fp. So whenever we are asked for code that uses the fpa,
139: ;;- we will mark a data register as clobbered. This is reasonable, as
140: ;;- almost all floating point compare operations done with fpa code
141: ;;- enabled will be done in the fpa. It's even more reasonable since
142: ;;- we decided to make the 68881 and the fpa mutually exclusive.
143:
144: ;;- We place to code to move the fpastatus register inside of a
145: ;;- define_expand so that we can do it conditionally based on whether
146: ;;- we are tagetting an fpa or not.
147:
148: ;;- This still leaves us with the question of where we wish to put the
149: ;;- code to move the fpastatus reg. If we put it in the compare
150: ;;- instruction, we can restrict the clobbering of the register to
151: ;;- floating point compares, but we can't take advantage of floating
152: ;;- point subtracts & etc. that alter the fpastatus register. If we
153: ;;- put it in the branch instruction, all branches compiled with fpa
154: ;;- code enabled will clobber a data register, but we will be able to
155: ;;- take advantage of fpa subtracts. This balance favors putting the
156: ;;- code in with the compare instruction.
157:
158: ;;- Note that if some enterprising hacker should decide to switch
159: ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
160:
161: ;;- Usage of the top 16 fpa registers
162:
163: ;;- The only locations which we may transfer fpa registers 16-31 from
164: ;;- or to are the fpa registers 0-15. (68000 registers and memory
165: ;;- locations are impossible). This causes problems in gcc, which
166: ;;- assumes that mov?? instructions require no additional registers
167: ;;- (see section 11.7) and since floating point moves *must* be
168: ;;- supported into general registers (see section 12.3 under
169: ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
170:
171: ;;- My solution was to reserve fpa0 for moves into or out of these top
172: ;;- 16 registers and to disparage the choice to reload into or out of
173: ;;- these registers as much as I could. That alternative is always
174: ;;- last in the list, so it will not be used unless all else fails. I
175: ;;- will note that according to my current information, sun's compiler
176: ;;- doesn't use these top 16 registers at all.
177:
178: ;;- There is another possible way to do it. I *believe* that if you
179: ;;- make absolutely sure that the code will not be exectued in the
180: ;;- reload pass, you can support the mov?? names with define_expands
181: ;;- which require new registers. This may be possible by the
182: ;;- appropriate juggling of constraints. I may come back to this later.
183:
184: ;;- Usage of constant RAM
185:
186: ;;- This has been handled correctly (I believe) but the way I've done
187: ;;- it could use a little explanation. The constant RAM can only be
188: ;;- accessed when the instruction is in "command register" mode.
189: ;;- "command register" mode means that no accessing of memory or the
190: ;;- 68000 registers is being done. This can be expressed easily in
191: ;;- constraints, so generally the mode of the instruction is
192: ;;- determined by a branch off of which_alternative. In outputing
193: ;;- instructions, a 'w' means to output an access to the constant ram
194: ;;- (if the arg is CONST_DOUBLE and is one of the available
195: ;;- constants), and 'x' means to output a register pair (if the arg is
196: ;;- a 68000 register) and a 'y' is the combination of the above two
197: ;;- processies. You use a 'y' in two operand DF instructions where you
198: ;;- *know* the other operand is an fpa register, you use an 'x' in DF
199: ;;- instructions where the arg might be a 68000 register and the
200: ;;- instruction is *not* in "command register" mode, and you use a 'w'
201: ;;- in two situations: 1) The instruction *is* in command register
202: ;;- mode (and hence won't be accessing 68000 registers), or 2) The
203: ;;- instruction is a two operand SF instruction where you know the
204: ;;- other operand is an fpa register.
205:
206: ;;- Optimization issues
207:
208: ;;- I actually think that I've included all of the fpa instructions
209: ;;- that should be included. Note that if someone is interested in
210: ;;- doing serious floating point work on the sun fpa, I would advise
211: ;;- the use of the "asm" instruction in gcc to allow you to use the
212: ;;- sin, cos, and exponential functions on the fpa board.
213:
214: ;;- END FPA Explanation Section.
215:
216:
217: ;;- Some of these insn's are composites of several m68000 op codes.
218: ;;- The assembler (or final @@??) insures that the appropriate one is
219: ;;- selected.
220:
221: (define_insn ""
222: [(set (match_operand:DF 0 "push_operand" "=m")
223: (match_operand:DF 1 "general_operand" "ro<>fyF"))]
224: ""
225: "*
226: {
227: if (FP_REG_P (operands[1]))
228: return \"fmove%.d %f1,%0\";
229: if (FPA_REG_P (operands[1]))
230: return \"fpmove%.d %1, %x0\";
231: return output_move_double (operands);
232: }")
233:
234: (define_insn ""
235: [(set (match_operand:DI 0 "push_operand" "=m")
236: (match_operand:DI 1 "general_operand" "ro<>Fy"))]
237: ""
238: "*
239: {
240: return output_move_double (operands);
241: }")
242:
243: ;; Put tstsi first among test insns so it matches a CONST_INT operand.
244:
245: (define_insn "tstsi"
246: [(set (cc0)
247: (match_operand:SI 0 "general_operand" "rm"))]
248: ""
249: "*
250: {
251: #ifdef ISI_OV
252: /* ISI's assembler fails to handle tstl a0. */
253: if (! ADDRESS_REG_P (operands[0]))
254: #else
255: if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
256: #endif
257: return \"tst%.l %0\";
258: /* If you think that the 68020 does not support tstl a0,
259: reread page B-167 of the 68020 manual more carefully. */
260: /* On an address reg, cmpw may replace cmpl. */
261: #ifdef HPUX_ASM
262: return \"cmp%.w %0,%#0\";
263: #else
264: return \"cmp%.w %#0,%0\";
265: #endif
266: }")
267:
268: (define_insn "tsthi"
269: [(set (cc0)
270: (match_operand:HI 0 "general_operand" "rm"))]
271: ""
272: "*
273: {
274: #ifdef ISI_OV
275: if (! ADDRESS_REG_P (operands[0]))
276: #else
277: if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
278: #endif
279: return \"tst%.w %0\";
280: #ifdef HPUX_ASM
281: return \"cmp%.w %0,%#0\";
282: #else
283: return \"cmp%.w %#0,%0\";
284: #endif
285: }")
286:
287: (define_insn "tstqi"
288: [(set (cc0)
289: (match_operand:QI 0 "general_operand" "dm"))]
290: ""
291: "tst%.b %0")
292:
293: (define_expand "tstsf"
294: [(set (cc0)
295: (match_operand:SF 0 "general_operand" ""))]
296: "TARGET_68881 || TARGET_FPA"
297: "
298: {
299: if (TARGET_FPA)
300: {
301: emit_insn (gen_rtx (PARALLEL, VOIDmode,
302: gen_rtvec (2,
303: gen_rtx (SET, VOIDmode,
304: cc0_rtx, operands[0]),
305: gen_rtx (CLOBBER, VOIDmode,
306: gen_reg_rtx (SImode)))));
307: DONE;
308: }
309: }")
310:
311: (define_insn ""
312: [(set (cc0)
313: (match_operand:SF 0 "general_operand" "xmdF"))
314: (clobber (match_operand:SI 1 "general_operand" "d"))]
315: "TARGET_FPA"
316: "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
317:
318: (define_insn ""
319: [(set (cc0)
320: (match_operand:SF 0 "general_operand" "fdm"))]
321: "TARGET_68881"
322: "*
323: {
324: cc_status.flags = CC_IN_68881;
325: if (FP_REG_P (operands[0]))
326: return \"ftst%.x %0\";
327: return \"ftst%.s %0\";
328: }")
329:
330: (define_expand "tstdf"
331: [(set (cc0)
332: (match_operand:DF 0 "general_operand" ""))]
333: "TARGET_68881 || TARGET_FPA"
334: "
335: {
336: if (TARGET_FPA)
337: {
338: emit_insn (gen_rtx (PARALLEL, VOIDmode,
339: gen_rtvec (2, gen_rtx (SET, VOIDmode,
340: cc0_rtx, operands[0]),
341: gen_rtx (CLOBBER, VOIDmode,
342: gen_reg_rtx (SImode)))));
343: DONE;
344: }
345: }")
346:
347: (define_insn ""
348: [(set (cc0)
349: (match_operand:DF 0 "general_operand" "xrmF"))
350: (clobber (match_operand:SI 1 "general_operand" "d"))]
351: "TARGET_FPA"
352: "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
353:
354: (define_insn ""
355: [(set (cc0)
356: (match_operand:DF 0 "general_operand" "fm"))]
357: "TARGET_68881"
358: "*
359: {
360: cc_status.flags = CC_IN_68881;
361: if (FP_REG_P (operands[0]))
362: return \"ftst%.x %0\";
363: return \"ftst%.d %0\";
364: }")
365:
366: ;; compare instructions.
367:
368: ;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
369:
370: ;; A composite of the cmp, cmpa, & cmpi m68000 op codes.
371: (define_insn "cmpsi"
372: [(set (cc0)
373: (compare (match_operand:SI 0 "general_operand" "rKs,mr,>")
374: (match_operand:SI 1 "general_operand" "mr,Ksr,>")))]
375: ""
376: "*
377: {
378: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
379: return \"cmpm%.l %1,%0\";
380: if (REG_P (operands[1])
381: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
382: { cc_status.flags |= CC_REVERSED;
383: #ifdef HPUX_ASM
384: return \"cmp%.l %d1,%d0\";
385: #else
386: return \"cmp%.l %d0,%d1\";
387: #endif
388: }
389: #ifdef HPUX_ASM
390: return \"cmp%.l %d0,%d1\";
391: #else
392: return \"cmp%.l %d1,%d0\";
393: #endif
394: }")
395:
396: (define_insn "cmphi"
397: [(set (cc0)
398: (compare (match_operand:HI 0 "general_operand" "rnm,d,n,m")
399: (match_operand:HI 1 "general_operand" "d,rnm,m,n")))]
400: ""
401: "*
402: {
403: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
404: return \"cmpm%.w %1,%0\";
405: if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
406: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
407: { cc_status.flags |= CC_REVERSED;
408: #ifdef HPUX_ASM
409: return \"cmp%.w %d1,%d0\";
410: #else
411: return \"cmp%.w %d0,%d1\";
412: #endif
413: }
414: #ifdef HPUX_ASM
415: return \"cmp%.w %d0,%d1\";
416: #else
417: return \"cmp%.w %d1,%d0\";
418: #endif
419: }")
420:
421: (define_insn "cmpqi"
422: [(set (cc0)
423: (compare (match_operand:QI 0 "general_operand" "dn,md,>")
424: (match_operand:QI 1 "general_operand" "dm,nd,>")))]
425: ""
426: "*
427: {
428: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
429: return \"cmpm%.b %1,%0\";
430: if (REG_P (operands[1])
431: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
432: { cc_status.flags |= CC_REVERSED;
433: #ifdef HPUX_ASM
434: return \"cmp%.b %d1,%d0\";
435: #else
436: return \"cmp%.b %d0,%d1\";
437: #endif
438: }
439: #ifdef HPUX_ASM
440: return \"cmp%.b %d0,%d1\";
441: #else
442: return \"cmp%.b %d1,%d0\";
443: #endif
444: }")
445:
446: (define_expand "cmpdf"
447: [(set (cc0)
448: (compare (match_operand:DF 0 "general_operand" "")
449: (match_operand:DF 1 "general_operand" "")))]
450: "TARGET_68881 || TARGET_FPA"
451: "
452: {
453: if (TARGET_FPA)
454: {
455: rtx set = gen_rtx (SET, VOIDmode, cc0_rtx,
456: gen_rtx (COMPARE, VOIDmode, operands[0], operands[1]));
457: emit_insn (gen_rtx (PARALLEL, VOIDmode,
458: gen_rtvec (2, set,
459: gen_rtx (CLOBBER, VOIDmode,
460: gen_reg_rtx (SImode)))));
461: DONE;
462: }
463: }")
464:
465: (define_insn ""
466: [(set (cc0)
467: (compare (match_operand:DF 0 "general_operand" "x,y")
468: (match_operand:DF 1 "general_operand" "xH,rmF")))
469: (clobber (match_operand:SI 2 "general_operand" "d,d"))]
470: "TARGET_FPA"
471: "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
472:
473: (define_insn ""
474: [(set (cc0)
475: (compare (match_operand:DF 0 "general_operand" "f,mG")
476: (match_operand:DF 1 "general_operand" "fmG,f")))]
477: "TARGET_68881"
478: "*
479: {
480: cc_status.flags = CC_IN_68881;
481: #ifdef HPUX_ASM
482: if (REG_P (operands[0]))
483: {
484: if (REG_P (operands[1]))
485: return \"fcmp%.x %0,%1\";
486: else
487: return \"fcmp%.d %0,%f1\";
488: }
489: cc_status.flags |= CC_REVERSED;
490: return \"fcmp%.d %1,%f0\";
491: #else
492: if (REG_P (operands[0]))
493: {
494: if (REG_P (operands[1]))
495: return \"fcmp%.x %1,%0\";
496: else
497: return \"fcmp%.d %f1,%0\";
498: }
499: cc_status.flags |= CC_REVERSED;
500: return \"fcmp%.d %f0,%1\";
501: #endif
502: }")
503:
504: (define_expand "cmpsf"
505: [(set (cc0)
506: (compare (match_operand:SF 0 "general_operand" "")
507: (match_operand:SF 1 "general_operand" "")))]
508: "TARGET_68881 || TARGET_FPA"
509: "
510: {
511: if (TARGET_FPA)
512: {
513: rtx set = gen_rtx (SET, VOIDmode, cc0_rtx,
514: gen_rtx (COMPARE, VOIDmode, operands[0], operands[1]));
515: emit_insn (gen_rtx (PARALLEL, VOIDmode,
516: gen_rtvec (2, set,
517: gen_rtx (CLOBBER, VOIDmode,
518: gen_reg_rtx(SImode)))));
519: DONE;
520: }
521: }")
522:
523: (define_insn ""
524: [(set (cc0)
525: (compare (match_operand:SF 0 "general_operand" "x,y")
526: (match_operand:SF 1 "general_operand" "xH,rmF")))
527: (clobber (match_operand:SI 2 "general_operand" "d,d"))]
528: "TARGET_FPA"
529: "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
530:
531: (define_insn ""
532: [(set (cc0)
533: (compare (match_operand:SF 0 "general_operand" "f,mdG")
534: (match_operand:SF 1 "general_operand" "fmdG,f")))]
535: "TARGET_68881"
536: "*
537: {
538: cc_status.flags = CC_IN_68881;
539: #ifdef HPUX_ASM
540: if (FP_REG_P (operands[0]))
541: {
542: if (FP_REG_P (operands[1]))
543: return \"fcmp%.x %0,%1\";
544: else
545: return \"fcmp%.s %0,%f1\";
546: }
547: cc_status.flags |= CC_REVERSED;
548: return \"fcmp%.s %1,%f0\";
549: #else
550: if (FP_REG_P (operands[0]))
551: {
552: if (FP_REG_P (operands[1]))
553: return \"fcmp%.x %1,%0\";
554: else
555: return \"fcmp%.s %f1,%0\";
556: }
557: cc_status.flags |= CC_REVERSED;
558: return \"fcmp%.s %f0,%1\";
559: #endif
560: }")
561:
562: ;; Recognizers for btst instructions.
563:
564: (define_insn ""
565: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
566: (const_int 1)
567: (minus:SI (const_int 7)
568: (match_operand:SI 1 "general_operand" "di"))))]
569: ""
570: "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
571:
572: (define_insn ""
573: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
574: (const_int 1)
575: (minus:SI (const_int 31)
576: (match_operand:SI 1 "general_operand" "di"))))]
577: ""
578: "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
579:
580: ;; The following two patterns are like the previous two
581: ;; except that they use the fact that bit-number operands
582: ;; are automatically masked to 3 or 5 bits.
583:
584: (define_insn ""
585: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
586: (const_int 1)
587: (minus:SI (const_int 7)
588: (and:SI
589: (match_operand:SI 1 "general_operand" "d")
590: (const_int 7)))))]
591: ""
592: "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
593:
594: (define_insn ""
595: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
596: (const_int 1)
597: (minus:SI (const_int 31)
598: (and:SI
599: (match_operand:SI 1 "general_operand" "d")
600: (const_int 31)))))]
601: ""
602: "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
603:
604: ;; Nonoffsettable mem refs are ok in this one pattern
605: ;; since we don't try to adjust them.
606: (define_insn ""
607: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md")
608: (const_int 1)
609: (match_operand:SI 1 "general_operand" "i")))]
610: "GET_CODE (operands[1]) == CONST_INT
611: && (unsigned) INTVAL (operands[1]) < 8"
612: "*
613: {
614: operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
615: return output_btst (operands, operands[1], operands[0], insn, 7);
616: }")
617:
618: (define_insn ""
619: ;; The constraint "o,d" here means that a nonoffsettable memref
620: ;; will match the first alternative, and its address will be reloaded.
621: ;; Copying the memory contents into a reg would be incorrect if the
622: ;; bit position is over 7.
623: [(set (cc0) (zero_extract (match_operand:HI 0 "nonimmediate_operand" "o,d")
624: (const_int 1)
625: (match_operand:SI 1 "general_operand" "i,i")))]
626: "GET_CODE (operands[1]) == CONST_INT"
627: "*
628: {
629: if (GET_CODE (operands[0]) == MEM)
630: {
631: operands[0] = adj_offsettable_operand (operands[0],
632: INTVAL (operands[1]) / 8);
633: operands[1] = gen_rtx (CONST_INT, VOIDmode,
634: 7 - INTVAL (operands[1]) % 8);
635: return output_btst (operands, operands[1], operands[0], insn, 7);
636: }
637: operands[1] = gen_rtx (CONST_INT, VOIDmode,
638: 15 - INTVAL (operands[1]));
639: return output_btst (operands, operands[1], operands[0], insn, 15);
640: }")
641:
642: (define_insn ""
643: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do")
644: (const_int 1)
645: (match_operand:SI 1 "general_operand" "i")))]
646: "GET_CODE (operands[1]) == CONST_INT"
647: "*
648: {
649: if (GET_CODE (operands[0]) == MEM)
650: {
651: operands[0] = adj_offsettable_operand (operands[0],
652: INTVAL (operands[1]) / 8);
653: operands[1] = gen_rtx (CONST_INT, VOIDmode,
654: 7 - INTVAL (operands[1]) % 8);
655: return output_btst (operands, operands[1], operands[0], insn, 7);
656: }
657: operands[1] = gen_rtx (CONST_INT, VOIDmode,
658: 31 - INTVAL (operands[1]));
659: return output_btst (operands, operands[1], operands[0], insn, 31);
660: }")
661:
662: (define_insn ""
663: [(set (cc0) (subreg:SI (lshiftrt:QI (match_operand:QI 0 "nonimmediate_operand" "dm")
664: (const_int 7))
665: 0))]
666: ""
667: "*
668: {
669: cc_status.flags = CC_Z_IN_NOT_N | CC_NOT_NEGATIVE;
670: return \"tst%.b %0\";
671: }")
672:
673: (define_insn ""
674: [(set (cc0) (and:SI (sign_extend:SI (sign_extend:HI (match_operand:QI 0 "nonimmediate_operand" "dm")))
675: (match_operand:SI 1 "general_operand" "i")))]
676: "(GET_CODE (operands[1]) == CONST_INT
677: && (unsigned) INTVAL (operands[1]) < 0x100
678: && exact_log2 (INTVAL (operands[1])) >= 0)"
679: "*
680: { register int log = exact_log2 (INTVAL (operands[1]));
681: operands[1] = gen_rtx (CONST_INT, VOIDmode, log);
682: return output_btst (operands, operands[1], operands[0], insn, 7);
683: }")
684:
685: ;; move instructions
686:
687: ;; A special case in which it is not desirable
688: ;; to reload the constant into a data register.
689: (define_insn ""
690: [(set (match_operand:SI 0 "push_operand" "=m")
691: (match_operand:SI 1 "general_operand" "J"))]
692: "GET_CODE (operands[1]) == CONST_INT
693: && INTVAL (operands[1]) >= -0x8000
694: && INTVAL (operands[1]) < 0x8000"
695: "*
696: {
697: if (operands[1] == const0_rtx)
698: return \"clr%.l %0\";
699: return \"pea %a1\";
700: }")
701:
702: ;This is never used.
703: ;(define_insn "swapsi"
704: ; [(set (match_operand:SI 0 "general_operand" "r")
705: ; (match_operand:SI 1 "general_operand" "r"))
706: ; (set (match_dup 1) (match_dup 0))]
707: ; ""
708: ; "exg %1,%0")
709:
710: ;; Special case of fullword move when source is zero.
711: ;; The reason this is special is to avoid loading a zero
712: ;; into a data reg with moveq in order to store it elsewhere.
713:
714: (define_insn ""
715: [(set (match_operand:SI 0 "general_operand" "=g")
716: (const_int 0))]
1.1.1.3 ! root 717: ;; clr insns on 68000 read before writing.
! 718: ;; This isn't so on the 68010, but we have no alternative for it.
! 719: "(TARGET_68020
! 720: || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
1.1 root 721: "*
722: {
723: if (ADDRESS_REG_P (operands[0]))
724: return \"sub%.l %0,%0\";
725: /* moveq is faster on the 68000. */
726: if (DATA_REG_P (operands[0]) && !TARGET_68020)
727: #ifdef MOTOROLA
728: return \"moveq%.l %#0,%0\";
729: #else
730: return \"moveq %#0,%0\";
731: #endif
732: return \"clr%.l %0\";
733: }")
734:
735: ;; General case of fullword move. The register constraints
736: ;; force integer constants in range for a moveq to be reloaded
737: ;; if they are headed for memory.
738: (define_insn "movsi"
739: ;; Notes: make sure no alternative allows g vs g.
740: ;; We don't allow f-regs since fixed point cannot go in them.
741: ;; We do allow y and x regs since fixed point is allowed in them.
742: [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
743: (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
744: ""
745: "*
746: {
747: if (which_alternative == 3)
748: return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
749: if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
750: return \"fpmove%.l %x1,%x0\";
751: if (GET_CODE (operands[1]) == CONST_INT)
752: {
753: if (operands[1] == const0_rtx
754: && (DATA_REG_P (operands[0])
1.1.1.3 ! root 755: || GET_CODE (operands[0]) == MEM)
! 756: /* clr insns on 68000 read before writing.
! 757: This isn't so on the 68010, but we have no alternative for it. */
! 758: && (TARGET_68020
! 759: || !(GET_CODE (operands[0]) == MEM
! 760: && MEM_VOLATILE_P (operands[0]))))
1.1 root 761: return \"clr%.l %0\";
762: else if (DATA_REG_P (operands[0])
763: && INTVAL (operands[1]) < 128
764: && INTVAL (operands[1]) >= -128)
765: {
766: #ifdef MOTOROLA
767: return \"moveq%.l %1,%0\";
768: #else
769: return \"moveq %1,%0\";
770: #endif
771: }
772: else if (ADDRESS_REG_P (operands[0])
773: && INTVAL (operands[1]) < 0x8000
774: && INTVAL (operands[1]) >= -0x8000)
775: return \"move%.w %1,%0\";
776: else if (push_operand (operands[0], SImode)
777: && INTVAL (operands[1]) < 0x8000
778: && INTVAL (operands[1]) >= -0x8000)
779: return \"pea %a1\";
780: }
781: else if ((GET_CODE (operands[1]) == SYMBOL_REF
782: || GET_CODE (operands[1]) == CONST)
783: && push_operand (operands[0], SImode))
784: return \"pea %a1\";
785: else if ((GET_CODE (operands[1]) == SYMBOL_REF
786: || GET_CODE (operands[1]) == CONST)
787: && ADDRESS_REG_P (operands[0]))
788: return \"lea %a1,%0\";
789: return \"move%.l %1,%0\";
790: }")
791:
792: (define_insn "movhi"
793: [(set (match_operand:HI 0 "general_operand" "=g")
794: (match_operand:HI 1 "general_operand" "g"))]
795: ""
796: "*
797: {
798: if (GET_CODE (operands[1]) == CONST_INT)
799: {
800: if (operands[1] == const0_rtx
801: && (DATA_REG_P (operands[0])
1.1.1.3 ! root 802: || GET_CODE (operands[0]) == MEM)
! 803: /* clr insns on 68000 read before writing.
! 804: This isn't so on the 68010, but we have no alternative for it. */
! 805: && (TARGET_68020
! 806: || !(GET_CODE (operands[0]) == MEM
! 807: && MEM_VOLATILE_P (operands[0]))))
1.1 root 808: return \"clr%.w %0\";
809: else if (DATA_REG_P (operands[0])
810: && INTVAL (operands[1]) < 128
811: && INTVAL (operands[1]) >= -128)
812: {
813: #ifdef MOTOROLA
814: return \"moveq%.l %1,%0\";
815: #else
816: return \"moveq %1,%0\";
817: #endif
818: }
819: else if (INTVAL (operands[1]) < 0x8000
820: && INTVAL (operands[1]) >= -0x8000)
821: return \"move%.w %1,%0\";
822: }
823: else if (CONSTANT_P (operands[1]))
824: return \"move%.l %1,%0\";
825: #ifndef SONY_ASM
826: /* Recognize the insn before a tablejump, one that refers
827: to a table of offsets. Such an insn will need to refer
828: to a label on the insn. So output one. Use the label-number
829: of the table of offsets to generate this label. */
830: if (GET_CODE (operands[1]) == MEM
831: && GET_CODE (XEXP (operands[1], 0)) == PLUS
832: && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
833: || GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF)
834: && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS
835: && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) != PLUS)
836: {
837: rtx labelref;
838: if (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF)
839: labelref = XEXP (XEXP (operands[1], 0), 0);
840: else
841: labelref = XEXP (XEXP (operands[1], 0), 1);
842: #if defined (MOTOROLA) && ! defined (SGS_3B1)
843: #ifdef SGS
844: fprintf (asm_out_file, \"\\tset %s%d,.+2\\n\", \"LI\",
845: CODE_LABEL_NUMBER (XEXP (labelref, 0)));
846: #else /* not SGS */
847: fprintf (asm_out_file, \"\\t.set %s%d,.+2\\n\", \"LI\",
848: CODE_LABEL_NUMBER (XEXP (labelref, 0)));
849: #endif /* not SGS */
850: #else /* SGS_3B1 or not MOTOROLA */
851: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
852: CODE_LABEL_NUMBER (XEXP (labelref, 0)));
853: /* For sake of 3b1, set flag saying we need to define the symbol
854: LD%n (with value L%n-LI%n) at the end of the switch table. */
855: RTX_INTEGRATED_P (next_real_insn (XEXP (labelref, 0))) = 1;
856: #endif /* SGS_3B1 or not MOTOROLA */
857: }
858: #endif /* SONY_ASM */
859: return \"move%.w %1,%0\";
860: }")
861:
862: (define_insn "movstricthi"
863: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
864: (match_operand:HI 1 "general_operand" "rmn"))]
865: ""
866: "*
867: {
868: if (GET_CODE (operands[1]) == CONST_INT)
869: {
870: if (operands[1] == const0_rtx
871: && (DATA_REG_P (operands[0])
1.1.1.3 ! root 872: || GET_CODE (operands[0]) == MEM)
! 873: /* clr insns on 68000 read before writing.
! 874: This isn't so on the 68010, but we have no alternative for it. */
! 875: && (TARGET_68020
! 876: || !(GET_CODE (operands[0]) == MEM
! 877: && MEM_VOLATILE_P (operands[0]))))
1.1 root 878: return \"clr%.w %0\";
879: }
880: return \"move%.w %1,%0\";
881: }")
882:
883: (define_insn "movqi"
884: [(set (match_operand:QI 0 "general_operand" "=d,*a,m,m,?*a")
885: (match_operand:QI 1 "general_operand" "dmi*a,d*a,dmi,?*a,m"))]
886: ""
887: "*
888: {
889: rtx xoperands[4];
890: if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM)
891: {
892: xoperands[1] = operands[1];
893: xoperands[2]
894: = gen_rtx (MEM, QImode,
895: gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
896: xoperands[3] = stack_pointer_rtx;
897: /* Just pushing a byte puts it in the high byte of the halfword. */
898: /* We must put it in the low half, the second byte. */
899: output_asm_insn (\"subq%.w %#2,%3\;move%.b %1,%2\", xoperands);
900: return \"move%.w %+,%0\";
901: }
902: if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM)
903: {
904: xoperands[0] = operands[0];
905: xoperands[1] = operands[1];
906: xoperands[2]
907: = gen_rtx (MEM, QImode,
908: gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
909: xoperands[3] = stack_pointer_rtx;
910: output_asm_insn (\"move%.w %1,%-\;move%.b %2,%0\;addq%.w %#2,%3\", xoperands);
911: return \"\";
912: }
1.1.1.3 ! root 913: /* clr and st insns on 68000 read before writing.
! 914: This isn't so on the 68010, but we have no alternative for it. */
! 915: if (TARGET_68020
! 916: || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
! 917: {
! 918: if (operands[1] == const0_rtx)
! 919: return \"clr%.b %0\";
! 920: if (GET_CODE (operands[1]) == CONST_INT
! 921: && INTVAL (operands[1]) == -1)
! 922: {
! 923: CC_STATUS_INIT;
! 924: return \"st %0\";
! 925: }
! 926: }
1.1 root 927: if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
928: return \"move%.l %1,%0\";
929: if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
930: return \"move%.w %1,%0\";
931: return \"move%.b %1,%0\";
932: }")
933:
934: (define_insn "movstrictqi"
935: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
936: (match_operand:QI 1 "general_operand" "dmn"))]
937: ""
938: "*
939: {
1.1.1.3 ! root 940: if (operands[1] == const0_rtx
! 941: /* clr insns on 68000 read before writing.
! 942: This isn't so on the 68010, but we have no alternative for it. */
! 943: && (TARGET_68020
! 944: || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1.1 root 945: return \"clr%.b %0\";
946: return \"move%.b %1,%0\";
947: }")
948:
949: (define_insn "movsf"
950: [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
951: (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
952: ; [(set (match_operand:SF 0 "general_operand" "=rmf")
953: ; (match_operand:SF 1 "general_operand" "rmfF"))]
954: ""
955: "*
956: {
957: if (which_alternative >= 4)
958: return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
959: if (FPA_REG_P (operands[0]))
960: {
961: if (FPA_REG_P (operands[1]))
962: return \"fpmove%.s %x1,%x0\";
963: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
964: return output_move_const_single (operands);
965: else if (FP_REG_P (operands[1]))
966: return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
967: return \"fpmove%.s %x1,%x0\";
968: }
969: if (FPA_REG_P (operands[1]))
970: {
971: if (FP_REG_P (operands[0]))
972: return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
973: else
974: return \"fpmove%.s %x1,%x0\";
975: }
976: if (FP_REG_P (operands[0]))
977: {
978: if (FP_REG_P (operands[1]))
979: return \"fmove%.x %1,%0\";
980: else if (ADDRESS_REG_P (operands[1]))
981: return \"move%.l %1,%-\;fmove%.s %+,%0\";
982: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
983: return output_move_const_single (operands);
984: return \"fmove%.s %f1,%0\";
985: }
986: if (FP_REG_P (operands[1]))
987: {
988: if (ADDRESS_REG_P (operands[0]))
989: return \"fmove%.s %1,%-\;move%.l %+,%0\";
990: return \"fmove%.s %f1,%0\";
991: }
992: return \"move%.l %1,%0\";
993: }")
994:
995: (define_insn "movdf"
996: [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>,y,rm,x,!x,!rm")
997: (match_operand:DF 1 "general_operand" "rf,m,rofF<>,rmF,y,xH,rm,x"))]
998: ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
999: ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1000: ""
1001: "*
1002: {
1003: if (which_alternative == 6)
1004: return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1005: if (FPA_REG_P (operands[0]))
1006: {
1007: if (GET_CODE (operands[1]) == CONST_DOUBLE)
1008: return output_move_const_double (operands);
1009: if (FP_REG_P (operands[1]))
1010: return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1011: return \"fpmove%.d %x1,%x0\";
1012: }
1013: else if (FPA_REG_P (operands[1]))
1014: {
1015: if (FP_REG_P(operands[0]))
1016: return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1017: else
1018: return \"fpmove%.d %x1,%x0\";
1019: }
1020: if (FP_REG_P (operands[0]))
1021: {
1022: if (FP_REG_P (operands[1]))
1023: return \"fmove%.x %1,%0\";
1024: if (REG_P (operands[1]))
1025: {
1026: rtx xoperands[2];
1027: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1028: output_asm_insn (\"move%.l %1,%-\", xoperands);
1029: output_asm_insn (\"move%.l %1,%-\", operands);
1030: return \"fmove%.d %+,%0\";
1031: }
1032: if (GET_CODE (operands[1]) == CONST_DOUBLE)
1033: return output_move_const_double (operands);
1034: return \"fmove%.d %f1,%0\";
1035: }
1036: else if (FP_REG_P (operands[1]))
1037: {
1038: if (REG_P (operands[0]))
1039: {
1040: output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1041: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1042: return \"move%.l %+,%0\";
1043: }
1044: else
1045: return \"fmove%.d %f1,%0\";
1046: }
1047: return output_move_double (operands);
1048: }
1049: ")
1050:
1051: ;; movdi can apply to fp regs in some cases
1052: (define_insn "movdi"
1053: ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1054: [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,y,rm,!*x,!rm")
1055: (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1056: ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1057: ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1058: ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1059: ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1060: ""
1061: "*
1062: {
1063: if (which_alternative == 8)
1064: return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1065: if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1066: return \"fpmove%.d %x1,%x0\";
1067: if (FP_REG_P (operands[0]))
1068: {
1069: if (FP_REG_P (operands[1]))
1070: return \"fmove%.x %1,%0\";
1071: if (REG_P (operands[1]))
1072: {
1073: rtx xoperands[2];
1074: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1075: output_asm_insn (\"move%.l %1,%-\", xoperands);
1076: output_asm_insn (\"move%.l %1,%-\", operands);
1077: return \"fmove%.d %+,%0\";
1078: }
1079: if (GET_CODE (operands[1]) == CONST_DOUBLE)
1080: return output_move_const_double (operands);
1081: return \"fmove%.d %f1,%0\";
1082: }
1083: else if (FP_REG_P (operands[1]))
1084: {
1085: if (REG_P (operands[0]))
1086: {
1087: output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1088: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1089: return \"move%.l %+,%0\";
1090: }
1091: else
1092: return \"fmove%.d %f1,%0\";
1093: }
1094: return output_move_double (operands);
1095: }
1096: ")
1097:
1098: ;; Thus goes after the move instructions
1099: ;; because the move instructions are better (require no spilling)
1100: ;; when they can apply. It goes before the add/sub insns
1101: ;; so we will prefer it to them.
1102:
1103: (define_insn "pushasi"
1104: [(set (match_operand:SI 0 "push_operand" "=m")
1105: (match_operand:SI 1 "address_operand" "p"))]
1106: ""
1107: "pea %a1")
1108:
1109: ;; truncation instructions
1110: (define_insn "truncsiqi2"
1111: [(set (match_operand:QI 0 "general_operand" "=dm,d")
1112: (truncate:QI
1113: (match_operand:SI 1 "general_operand" "doJ,i")))]
1114: ""
1115: "*
1116: {
1117: if (GET_CODE (operands[0]) == REG)
1118: return \"move%.l %1,%0\";
1119: if (GET_CODE (operands[1]) == MEM)
1120: operands[1] = adj_offsettable_operand (operands[1], 3);
1121: return \"move%.b %1,%0\";
1122: }")
1123:
1124: (define_insn "trunchiqi2"
1125: [(set (match_operand:QI 0 "general_operand" "=dm,d")
1126: (truncate:QI
1127: (match_operand:HI 1 "general_operand" "doJ,i")))]
1128: ""
1129: "*
1130: {
1131: if (GET_CODE (operands[0]) == REG
1132: && (GET_CODE (operands[1]) == MEM
1133: || GET_CODE (operands[1]) == CONST_INT))
1134: return \"move%.w %1,%0\";
1135: if (GET_CODE (operands[0]) == REG)
1136: return \"move%.l %1,%0\";
1137: if (GET_CODE (operands[1]) == MEM)
1138: operands[1] = adj_offsettable_operand (operands[1], 1);
1139: return \"move%.b %1,%0\";
1140: }")
1141:
1142: (define_insn "truncsihi2"
1143: [(set (match_operand:HI 0 "general_operand" "=dm,d")
1144: (truncate:HI
1145: (match_operand:SI 1 "general_operand" "roJ,i")))]
1146: ""
1147: "*
1148: {
1149: if (GET_CODE (operands[0]) == REG)
1150: return \"move%.l %1,%0\";
1151: if (GET_CODE (operands[1]) == MEM)
1152: operands[1] = adj_offsettable_operand (operands[1], 2);
1153: return \"move%.w %1,%0\";
1154: }")
1155:
1156: ;; zero extension instructions
1157:
1158: (define_expand "zero_extendhisi2"
1159: [(set (match_operand:SI 0 "register_operand" "")
1160: (const_int 0))
1161: (set (strict_low_part (subreg:HI (match_dup 0) 0))
1162: (match_operand:HI 1 "general_operand" ""))]
1163: ""
1164: "operands[1] = make_safe_from (operands[1], operands[0]);")
1165:
1166: (define_expand "zero_extendqihi2"
1167: [(set (match_operand:HI 0 "register_operand" "")
1168: (const_int 0))
1169: (set (strict_low_part (subreg:QI (match_dup 0) 0))
1170: (match_operand:QI 1 "general_operand" ""))]
1171: ""
1172: "operands[1] = make_safe_from (operands[1], operands[0]);")
1173:
1174: (define_expand "zero_extendqisi2"
1175: [(set (match_operand:SI 0 "register_operand" "")
1176: (const_int 0))
1177: (set (strict_low_part (subreg:QI (match_dup 0) 0))
1178: (match_operand:QI 1 "general_operand" ""))]
1179: ""
1180: " operands[1] = make_safe_from (operands[1], operands[0]); ")
1181:
1182: ;; Patterns to recognize zero-extend insns produced by the combiner.
1183:
1184: ;; Note that the one starting from HImode comes before those for QImode
1185: ;; so that a constant operand will match HImode, not QImode.
1186: (define_insn ""
1187: [(set (match_operand:SI 0 "general_operand" "=do<>")
1188: (zero_extend:SI
1189: (match_operand:HI 1 "general_operand" "rmn")))]
1190: ""
1191: "*
1192: {
1193: if (DATA_REG_P (operands[0]))
1194: {
1195: if (GET_CODE (operands[1]) == REG
1196: && REGNO (operands[0]) == REGNO (operands[1]))
1197: return \"and%.l %#0xFFFF,%0\";
1198: if (reg_mentioned_p (operands[0], operands[1]))
1199: return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1200: return \"clr%.l %0\;move%.w %1,%0\";
1201: }
1202: else if (GET_CODE (operands[0]) == MEM
1203: && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1204: return \"move%.w %1,%0\;clr%.w %0\";
1205: else if (GET_CODE (operands[0]) == MEM
1206: && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1207: return \"clr%.w %0\;move%.w %1,%0\";
1208: else
1209: {
1210: output_asm_insn (\"clr%.w %0\", operands);
1211: operands[0] = adj_offsettable_operand (operands[0], 2);
1212: return \"move%.w %1,%0\";
1213: }
1214: }")
1215:
1216: (define_insn ""
1217: [(set (match_operand:HI 0 "general_operand" "=do<>")
1218: (zero_extend:HI
1219: (match_operand:QI 1 "general_operand" "dmn")))]
1220: ""
1221: "*
1222: {
1223: if (DATA_REG_P (operands[0]))
1224: {
1225: if (GET_CODE (operands[1]) == REG
1226: && REGNO (operands[0]) == REGNO (operands[1]))
1227: return \"and%.w %#0xFF,%0\";
1228: if (reg_mentioned_p (operands[0], operands[1]))
1229: return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1230: return \"clr%.w %0\;move%.b %1,%0\";
1231: }
1232: else if (GET_CODE (operands[0]) == MEM
1233: && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1234: {
1.1.1.3 ! root 1235: if (REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM)
! 1236: {
! 1237: output_asm_insn (\"clr%.w @-\", operands);
! 1238: operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
! 1239: plus_constant (stack_pointer_rtx, 1));
! 1240: return \"move%.b %1,%0\";
! 1241: }
1.1 root 1242: else
1243: return \"move%.b %1,%0\;clr%.b %0\";
1244: }
1245: else if (GET_CODE (operands[0]) == MEM
1246: && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1247: return \"clr%.b %0\;move%.b %1,%0\";
1248: else
1249: {
1250: output_asm_insn (\"clr%.b %0\", operands);
1251: operands[0] = adj_offsettable_operand (operands[0], 1);
1252: return \"move%.b %1,%0\";
1253: }
1254: }")
1255:
1256: (define_insn ""
1257: [(set (match_operand:SI 0 "general_operand" "=do<>")
1258: (zero_extend:SI
1259: (match_operand:QI 1 "general_operand" "dmn")))]
1260: ""
1261: "*
1262: {
1263: if (DATA_REG_P (operands[0]))
1264: {
1265: if (GET_CODE (operands[1]) == REG
1266: && REGNO (operands[0]) == REGNO (operands[1]))
1267: return \"and%.l %#0xFF,%0\";
1268: if (reg_mentioned_p (operands[0], operands[1]))
1269: return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1270: return \"clr%.l %0\;move%.b %1,%0\";
1271: }
1272: else if (GET_CODE (operands[0]) == MEM
1273: && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1274: {
1275: operands[0] = XEXP (XEXP (operands[0], 0), 0);
1276: #ifdef MOTOROLA
1277: #ifdef SGS
1278: return \"clr.l -(%0)\;move%.b %1,3(%0)\";
1279: #else
1280: return \"clr.l -(%0)\;move%.b %1,(3,%0)\";
1281: #endif
1282: #else
1283: return \"clrl %0@-\;moveb %1,%0@(3)\";
1284: #endif
1285: }
1286: else if (GET_CODE (operands[0]) == MEM
1287: && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1288: {
1289: operands[0] = XEXP (XEXP (operands[0], 0), 0);
1290: #ifdef MOTOROLA
1291: #ifdef SGS
1292: return \"clr.l (%0)+\;move%.b %1,-1(%0)\";
1293: #else
1294: return \"clr.l (%0)+\;move%.b %1,(-1,%0)\";
1295: #endif
1296: #else
1297: return \"clrl %0@+\;moveb %1,%0@(-1)\";
1298: #endif
1299: }
1300: else
1301: {
1302: output_asm_insn (\"clr%.l %0\", operands);
1303: operands[0] = adj_offsettable_operand (operands[0], 3);
1304: return \"move%.b %1,%0\";
1305: }
1306: }")
1307:
1308: ;; sign extension instructions
1309: ;; Note that the one starting from HImode comes before those for QImode
1310: ;; so that a constant operand will match HImode, not QImode.
1311:
1312: (define_insn "extendhisi2"
1313: [(set (match_operand:SI 0 "general_operand" "=*d,a")
1314: (sign_extend:SI
1315: (match_operand:HI 1 "general_operand" "0,rmn")))]
1316: ""
1317: "*
1318: {
1319: if (ADDRESS_REG_P (operands[0]))
1320: return \"move%.w %1,%0\";
1321: return \"ext%.l %0\";
1322: }")
1323:
1324: (define_insn "extendqihi2"
1325: [(set (match_operand:HI 0 "general_operand" "=d")
1326: (sign_extend:HI
1327: (match_operand:QI 1 "general_operand" "0")))]
1328: ""
1329: "ext%.w %0")
1330:
1331: (define_insn "extendqisi2"
1332: [(set (match_operand:SI 0 "general_operand" "=d")
1333: (sign_extend:SI
1334: (match_operand:QI 1 "general_operand" "0")))]
1335: "TARGET_68020"
1336: "extb%.l %0")
1337:
1338: ;; Conversions between float and double.
1339:
1340: (define_expand "extendsfdf2"
1341: [(set (match_operand:DF 0 "general_operand" "")
1342: (float_extend:DF
1343: (match_operand:SF 1 "general_operand" "")))]
1344: "TARGET_68881 || TARGET_FPA"
1345: "")
1346:
1347: (define_insn ""
1348: [(set (match_operand:DF 0 "general_operand" "=x,y")
1349: (float_extend:DF
1350: (match_operand:SF 1 "general_operand" "xH,rmF")))]
1351: "TARGET_FPA"
1352: "fpstod %w1,%0")
1353:
1354: (define_insn ""
1355: [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1356: (float_extend:DF
1357: (match_operand:SF 1 "general_operand" "f,dmF")))]
1358: "TARGET_68881"
1359: "*
1360: {
1361: if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1362: {
1363: if (REGNO (operands[0]) == REGNO (operands[1]))
1364: {
1365: /* Extending float to double in an fp-reg is a no-op.
1366: NOTICE_UPDATE_CC has already assumed that the
1367: cc will be set. So cancel what it did. */
1368: cc_status = cc_prev_status;
1369: return \"\";
1370: }
1371: return \"fmove%.x %1,%0\";
1372: }
1373: if (FP_REG_P (operands[0]))
1374: return \"fmove%.s %f1,%0\";
1375: if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1376: {
1377: output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1378: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1379: return \"move%.l %+,%0\";
1380: }
1381: return \"fmove%.d %f1,%0\";
1382: }")
1383:
1384: ;; This cannot output into an f-reg because there is no way to be
1385: ;; sure of truncating in that case.
1386: ;; But on the Sun FPA, we can be sure.
1387: (define_expand "truncdfsf2"
1388: [(set (match_operand:SF 0 "general_operand" "")
1389: (float_truncate:SF
1390: (match_operand:DF 1 "general_operand" "")))]
1391: "TARGET_68881 || TARGET_FPA"
1392: "")
1393:
1394: (define_insn ""
1.1.1.2 root 1395: [(set (match_operand:SF 0 "general_operand" "=x,y")
1.1 root 1396: (float_truncate:SF
1397: (match_operand:DF 1 "general_operand" "xH,rmF")))]
1398: "TARGET_FPA"
1399: "fpdtos %y1,%0")
1400:
1401: (define_insn ""
1402: [(set (match_operand:SF 0 "general_operand" "=dm")
1403: (float_truncate:SF
1404: (match_operand:DF 1 "general_operand" "f")))]
1405: "TARGET_68881"
1406: "fmove%.s %f1,%0")
1407:
1408: ;; Conversion between fixed point and floating point.
1409: ;; Note that among the fix-to-float insns
1410: ;; the ones that start with SImode come first.
1411: ;; That is so that an operand that is a CONST_INT
1412: ;; (and therefore lacks a specific machine mode).
1413: ;; will be recognized as SImode (which is always valid)
1414: ;; rather than as QImode or HImode.
1415:
1416: (define_expand "floatsisf2"
1417: [(set (match_operand:SF 0 "general_operand" "")
1418: (float:SF (match_operand:SI 1 "general_operand" "")))]
1419: "TARGET_68881 || TARGET_FPA"
1420: "")
1421:
1422: (define_insn ""
1423: [(set (match_operand:SF 0 "general_operand" "=y,x")
1424: (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1425: "TARGET_FPA"
1426: "fpltos %1,%0")
1427:
1428: (define_insn ""
1429: [(set (match_operand:SF 0 "general_operand" "=f")
1430: (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1431: "TARGET_68881"
1432: "fmove%.l %1,%0")
1433:
1434: (define_expand "floatsidf2"
1435: [(set (match_operand:DF 0 "general_operand" "")
1436: (float:DF (match_operand:SI 1 "general_operand" "")))]
1437: "TARGET_68881 || TARGET_FPA"
1438: "")
1439:
1440: (define_insn ""
1.1.1.2 root 1441: [(set (match_operand:DF 0 "general_operand" "=y,x")
1.1 root 1442: (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1443: "TARGET_FPA"
1444: "fpltod %1,%0")
1445:
1446: (define_insn ""
1447: [(set (match_operand:DF 0 "general_operand" "=f")
1448: (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1449: "TARGET_68881"
1450: "fmove%.l %1,%0")
1451:
1452: (define_insn "floathisf2"
1453: [(set (match_operand:SF 0 "general_operand" "=f")
1454: (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1455: "TARGET_68881"
1456: "fmove%.w %1,%0")
1457:
1458: (define_insn "floathidf2"
1459: [(set (match_operand:DF 0 "general_operand" "=f")
1460: (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1461: "TARGET_68881"
1462: "fmove%.w %1,%0")
1463:
1464: (define_insn "floatqisf2"
1465: [(set (match_operand:SF 0 "general_operand" "=f")
1466: (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1467: "TARGET_68881"
1468: "fmove%.b %1,%0")
1469:
1470: (define_insn "floatqidf2"
1471: [(set (match_operand:DF 0 "general_operand" "=f")
1472: (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1473: "TARGET_68881"
1474: "fmove%.b %1,%0")
1475:
1476: ;; Convert a float to a float whose value is an integer.
1477: ;; This is the first stage of converting it to an integer type.
1478:
1479: (define_insn "ftruncdf2"
1480: [(set (match_operand:DF 0 "general_operand" "=f")
1481: (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1482: "TARGET_68881"
1483: "*
1484: {
1485: if (FP_REG_P (operands[1]))
1486: return \"fintrz%.x %f1,%0\";
1487: return \"fintrz%.d %f1,%0\";
1488: }")
1489:
1490: (define_insn "ftruncsf2"
1491: [(set (match_operand:SF 0 "general_operand" "=f")
1492: (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1493: "TARGET_68881"
1494: "*
1495: {
1496: if (FP_REG_P (operands[1]))
1497: return \"fintrz%.x %f1,%0\";
1498: return \"fintrz%.s %f1,%0\";
1499: }")
1500:
1501: ;; Convert a float whose value is an integer
1502: ;; to an actual integer. Second stage of converting float to integer type.
1503: (define_insn "fixsfqi2"
1504: [(set (match_operand:QI 0 "general_operand" "=dm")
1505: (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1506: "TARGET_68881"
1507: "fmove%.b %1,%0")
1508:
1509: (define_insn "fixsfhi2"
1510: [(set (match_operand:HI 0 "general_operand" "=dm")
1511: (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1512: "TARGET_68881"
1513: "fmove%.w %1,%0")
1514:
1515: (define_insn "fixsfsi2"
1516: [(set (match_operand:SI 0 "general_operand" "=dm")
1517: (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1518: "TARGET_68881"
1519: "fmove%.l %1,%0")
1520:
1521: (define_insn "fixdfqi2"
1522: [(set (match_operand:QI 0 "general_operand" "=dm")
1523: (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1524: "TARGET_68881"
1525: "fmove%.b %1,%0")
1526:
1527: (define_insn "fixdfhi2"
1528: [(set (match_operand:HI 0 "general_operand" "=dm")
1529: (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1530: "TARGET_68881"
1531: "fmove%.w %1,%0")
1532:
1533: (define_insn "fixdfsi2"
1534: [(set (match_operand:SI 0 "general_operand" "=dm")
1535: (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1536: "TARGET_68881"
1537: "fmove%.l %1,%0")
1538:
1539: ;; Convert a float to an integer.
1540: ;; On the Sun FPA, this is done in one step.
1541:
1542: (define_insn "fix_truncsfsi2"
1543: [(set (match_operand:SI 0 "general_operand" "=x,y")
1544: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
1545: "TARGET_FPA"
1546: "fpstol %w1,%0")
1547:
1548: (define_insn "fix_truncdfsi2"
1549: [(set (match_operand:SI 0 "general_operand" "=x,y")
1550: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
1551: "TARGET_FPA"
1552: "fpdtol %y1,%0")
1553:
1554: ;; add instructions
1555:
1556: ;; Note that the last two alternatives are near-duplicates
1557: ;; in order to handle insns generated by reload.
1558: ;; This is needed since they are not themselves reloaded,
1559: ;; so commutativity won't apply to them.
1560: (define_insn "addsi3"
1561: [(set (match_operand:SI 0 "general_operand" "=m,r,!a,!a")
1562: (plus:SI (match_operand:SI 1 "general_operand" "%0,0,a,rJK")
1563: (match_operand:SI 2 "general_operand" "dIKLs,mrIKLs,rJK,a")))]
1564: ""
1565: "*
1566: {
1567: if (! operands_match_p (operands[0], operands[1]))
1568: {
1569: if (!ADDRESS_REG_P (operands[1]))
1570: {
1571: rtx tmp = operands[1];
1572:
1573: operands[1] = operands[2];
1574: operands[2] = tmp;
1575: }
1576:
1577: /* These insns can result from reloads to access
1578: stack slots over 64k from the frame pointer. */
1579: if (GET_CODE (operands[2]) == CONST_INT
1580: && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
1581: return \"move%.l %2,%0\;add%.l %1,%0\";
1582: #ifdef SGS
1583: if (GET_CODE (operands[2]) == REG)
1584: return \"lea 0(%1,%2.l),%0\";
1585: else
1586: return \"lea %c2(%1),%0\";
1587: #else /* not SGS */
1588: #ifdef MOTOROLA
1589: if (GET_CODE (operands[2]) == REG)
1590: return \"lea (%1,%2.l),%0\";
1591: else
1592: return \"lea (%c2,%1),%0\";
1593: #else /* not MOTOROLA (MIT syntax) */
1594: if (GET_CODE (operands[2]) == REG)
1595: return \"lea %1@(0,%2:l),%0\";
1596: else
1597: return \"lea %1@(%c2),%0\";
1598: #endif /* not MOTOROLA */
1599: #endif /* not SGS */
1600: }
1601: if (GET_CODE (operands[2]) == CONST_INT)
1602: {
1603: #ifndef NO_ADDSUB_Q
1604: if (INTVAL (operands[2]) > 0
1605: && INTVAL (operands[2]) <= 8)
1606: return (ADDRESS_REG_P (operands[0])
1607: ? \"addq%.w %2,%0\"
1608: : \"addq%.l %2,%0\");
1609: if (INTVAL (operands[2]) < 0
1610: && INTVAL (operands[2]) >= -8)
1611: {
1612: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1613: - INTVAL (operands[2]));
1614: return (ADDRESS_REG_P (operands[0])
1615: ? \"subq%.w %2,%0\"
1616: : \"subq%.l %2,%0\");
1617: }
1618: #endif
1619: if (ADDRESS_REG_P (operands[0])
1620: && INTVAL (operands[2]) >= -0x8000
1621: && INTVAL (operands[2]) < 0x8000)
1622: return \"add%.w %2,%0\";
1623: }
1624: return \"add%.l %2,%0\";
1625: }")
1626:
1627: (define_insn ""
1628: [(set (match_operand:SI 0 "general_operand" "=a")
1629: (plus:SI (match_operand:SI 1 "general_operand" "0")
1630: (sign_extend:SI (match_operand:HI 2 "general_operand" "rmn"))))]
1631: ""
1632: "add%.w %2,%0")
1633:
1634: (define_insn "addhi3"
1635: [(set (match_operand:HI 0 "general_operand" "=m,r")
1636: (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1637: (match_operand:HI 2 "general_operand" "dn,rmn")))]
1638: ""
1639: "*
1640: {
1641: #ifndef NO_ADDSUB_Q
1642: if (GET_CODE (operands[2]) == CONST_INT)
1643: {
1644: if (INTVAL (operands[2]) > 0
1645: && INTVAL (operands[2]) <= 8)
1646: return \"addq%.w %2,%0\";
1647: }
1648: if (GET_CODE (operands[2]) == CONST_INT)
1649: {
1650: if (INTVAL (operands[2]) < 0
1651: && INTVAL (operands[2]) >= -8)
1652: {
1653: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1654: - INTVAL (operands[2]));
1655: return \"subq%.w %2,%0\";
1656: }
1657: }
1658: #endif
1659: return \"add%.w %2,%0\";
1660: }")
1661:
1662: (define_insn ""
1663: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
1664: (plus:HI (match_dup 0)
1665: (match_operand:HI 1 "general_operand" "dn,rmn")))]
1666: ""
1667: "add%.w %1,%0")
1668:
1669: (define_insn "addqi3"
1670: [(set (match_operand:QI 0 "general_operand" "=m,d")
1671: (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
1672: (match_operand:QI 2 "general_operand" "dn,dmn")))]
1673: ""
1674: "*
1675: {
1676: #ifndef NO_ADDSUB_Q
1677: if (GET_CODE (operands[2]) == CONST_INT)
1678: {
1679: if (INTVAL (operands[2]) > 0
1680: && INTVAL (operands[2]) <= 8)
1681: return \"addq%.b %2,%0\";
1682: }
1683: if (GET_CODE (operands[2]) == CONST_INT)
1684: {
1685: if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
1686: {
1687: operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
1688: return \"subq%.b %2,%0\";
1689: }
1690: }
1691: #endif
1692: return \"add%.b %2,%0\";
1693: }")
1694:
1695: (define_insn ""
1696: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
1697: (plus:QI (match_dup 0)
1698: (match_operand:QI 1 "general_operand" "dn,dmn")))]
1699: ""
1700: "add%.b %1,%0")
1701:
1702: (define_expand "adddf3"
1703: [(set (match_operand:DF 0 "general_operand" "")
1704: (plus:DF (match_operand:DF 1 "general_operand" "")
1705: (match_operand:DF 2 "general_operand" "")))]
1706: "TARGET_68881 || TARGET_FPA"
1707: "")
1708:
1709: (define_insn ""
1710: [(set (match_operand:DF 0 "general_operand" "=x,y")
1711: (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
1712: (match_operand:DF 2 "general_operand" "xH,dmF")))]
1713: "TARGET_FPA"
1714: "*
1715: {
1716: if (rtx_equal_p (operands[0], operands[1]))
1717: return \"fpadd%.d %y2,%0\";
1718: if (rtx_equal_p (operands[0], operands[2]))
1719: return \"fpadd%.d %y1,%0\";
1720: if (which_alternative == 0)
1721: return \"fpadd3%.d %w2,%w1,%0\";
1722: return \"fpadd3%.d %x2,%x1,%0\";
1723: }")
1724:
1725: (define_insn ""
1726: [(set (match_operand:DF 0 "general_operand" "=f")
1727: (plus:DF (match_operand:DF 1 "general_operand" "%0")
1728: (match_operand:DF 2 "general_operand" "fmG")))]
1729: "TARGET_68881"
1730: "*
1731: {
1732: if (REG_P (operands[2]))
1733: return \"fadd%.x %2,%0\";
1734: return \"fadd%.d %f2,%0\";
1735: }")
1736:
1737: (define_expand "addsf3"
1738: [(set (match_operand:SF 0 "general_operand" "")
1739: (plus:SF (match_operand:SF 1 "general_operand" "")
1740: (match_operand:SF 2 "general_operand" "")))]
1741: "TARGET_68881 || TARGET_FPA"
1742: "")
1743:
1744: (define_insn ""
1745: [(set (match_operand:SF 0 "general_operand" "=x,y")
1746: (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
1747: (match_operand:SF 2 "general_operand" "xH,rmF")))]
1748: "TARGET_FPA"
1749: "*
1750: {
1751: if (rtx_equal_p (operands[0], operands[1]))
1752: return \"fpadd%.s %w2,%0\";
1753: if (rtx_equal_p (operands[0], operands[2]))
1754: return \"fpadd%.s %w1,%0\";
1755: if (which_alternative == 0)
1756: return \"fpadd3%.s %w2,%w1,%0\";
1757: return \"fpadd3%.s %2,%1,%0\";
1758: }")
1759:
1760: (define_insn ""
1761: [(set (match_operand:SF 0 "general_operand" "=f")
1762: (plus:SF (match_operand:SF 1 "general_operand" "%0")
1763: (match_operand:SF 2 "general_operand" "fdmF")))]
1764: "TARGET_68881"
1765: "*
1766: {
1767: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
1768: return \"fadd%.x %2,%0\";
1769: return \"fadd%.s %f2,%0\";
1770: }")
1771:
1772: ;; subtract instructions
1773:
1774: (define_insn "subsi3"
1775: [(set (match_operand:SI 0 "general_operand" "=m,r,!a,?d")
1776: (minus:SI (match_operand:SI 1 "general_operand" "0,0,a,mrIKs")
1777: (match_operand:SI 2 "general_operand" "dIKs,mrIKs,J,0")))]
1778: ""
1779: "*
1780: {
1781: if (! operands_match_p (operands[0], operands[1]))
1782: {
1783: if (operands_match_p (operands[0], operands[2]))
1784: {
1785: #ifndef NO_ADDSUB_Q
1786: if (GET_CODE (operands[1]) == CONST_INT)
1787: {
1788: if (INTVAL (operands[1]) > 0
1789: && INTVAL (operands[1]) <= 8)
1790: return \"subq%.l %1,%0\;neg%.l %0\";
1791: }
1792: #endif
1793: return \"sub%.l %1,%0\;neg%.l %0\";
1794: }
1795: /* This case is matched by J, but negating -0x8000
1796: in an lea would give an invalid displacement.
1797: So do this specially. */
1798: if (INTVAL (operands[2]) == -0x8000)
1799: return \"move%.l %1,%0\;sub%.l %2,%0\";
1800: #ifdef SGS
1801: return \"lea %n2(%1),%0\";
1802: #else
1803: #ifdef MOTOROLA
1804: return \"lea (%n2,%1),%0\";
1805: #else /* not MOTOROLA (MIT syntax) */
1806: return \"lea %1@(%n2),%0\";
1807: #endif /* not MOTOROLA */
1808: #endif /* not SGS */
1809: }
1810: if (GET_CODE (operands[2]) == CONST_INT)
1811: {
1812: #ifndef NO_ADDSUB_Q
1813: if (INTVAL (operands[2]) > 0
1814: && INTVAL (operands[2]) <= 8)
1815: return \"subq%.l %2,%0\";
1816: #endif
1817: if (ADDRESS_REG_P (operands[0])
1818: && INTVAL (operands[2]) >= -0x8000
1819: && INTVAL (operands[2]) < 0x8000)
1820: return \"sub%.w %2,%0\";
1821: }
1822: return \"sub%.l %2,%0\";
1823: }")
1824:
1825: (define_insn ""
1826: [(set (match_operand:SI 0 "general_operand" "=a")
1827: (minus:SI (match_operand:SI 1 "general_operand" "0")
1828: (sign_extend:SI (match_operand:HI 2 "general_operand" "rmn"))))]
1829: ""
1830: "sub%.w %2,%0")
1831:
1832: (define_insn "subhi3"
1833: [(set (match_operand:HI 0 "general_operand" "=m,r")
1834: (minus:HI (match_operand:HI 1 "general_operand" "0,0")
1835: (match_operand:HI 2 "general_operand" "dn,rmn")))]
1836: ""
1837: "sub%.w %2,%0")
1838:
1839: (define_insn ""
1840: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
1841: (minus:HI (match_dup 0)
1842: (match_operand:HI 1 "general_operand" "dn,rmn")))]
1843: ""
1844: "sub%.w %1,%0")
1845:
1846: (define_insn "subqi3"
1847: [(set (match_operand:QI 0 "general_operand" "=m,d")
1848: (minus:QI (match_operand:QI 1 "general_operand" "0,0")
1849: (match_operand:QI 2 "general_operand" "dn,dmn")))]
1850: ""
1851: "sub%.b %2,%0")
1852:
1853: (define_insn ""
1854: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
1855: (minus:QI (match_dup 0)
1856: (match_operand:QI 1 "general_operand" "dn,dmn")))]
1857: ""
1858: "sub%.b %1,%0")
1859:
1860: (define_expand "subdf3"
1861: [(set (match_operand:DF 0 "general_operand" "")
1862: (minus:DF (match_operand:DF 1 "general_operand" "")
1863: (match_operand:DF 2 "general_operand" "")))]
1864: "TARGET_68881 || TARGET_FPA"
1865: "")
1866:
1867: (define_insn ""
1868: [(set (match_operand:DF 0 "general_operand" "=x,y,y")
1869: (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
1870: (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
1871: "TARGET_FPA"
1872: "*
1873: {
1874: if (rtx_equal_p (operands[0], operands[2]))
1875: return \"fprsub%.d %y1,%0\";
1876: if (rtx_equal_p (operands[0], operands[1]))
1877: return \"fpsub%.d %y2,%0\";
1878: if (which_alternative == 0)
1879: return \"fpsub3%.d %w2,%w1,%0\";
1880: return \"fpsub3%.d %x2,%x1,%0\";
1881: }")
1882:
1883: (define_insn ""
1884: [(set (match_operand:DF 0 "general_operand" "=f")
1885: (minus:DF (match_operand:DF 1 "general_operand" "0")
1886: (match_operand:DF 2 "general_operand" "fmG")))]
1887: "TARGET_68881"
1888: "*
1889: {
1890: if (REG_P (operands[2]))
1891: return \"fsub%.x %2,%0\";
1892: return \"fsub%.d %f2,%0\";
1893: }")
1894:
1895: (define_expand "subsf3"
1896: [(set (match_operand:SF 0 "general_operand" "")
1897: (minus:SF (match_operand:SF 1 "general_operand" "")
1898: (match_operand:SF 2 "general_operand" "")))]
1899: "TARGET_68881 || TARGET_FPA"
1900: "")
1901:
1902: (define_insn ""
1903: [(set (match_operand:SF 0 "general_operand" "=x,y,y")
1904: (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
1905: (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
1906: "TARGET_FPA"
1907: "*
1908: {
1909: if (rtx_equal_p (operands[0], operands[2]))
1910: return \"fprsub%.s %w1,%0\";
1911: if (rtx_equal_p (operands[0], operands[1]))
1912: return \"fpsub%.s %w2,%0\";
1913: if (which_alternative == 0)
1914: return \"fpsub3%.s %w2,%w1,%0\";
1915: return \"fpsub3%.s %2,%1,%0\";
1916: }")
1917:
1918: (define_insn ""
1919: [(set (match_operand:SF 0 "general_operand" "=f")
1920: (minus:SF (match_operand:SF 1 "general_operand" "0")
1921: (match_operand:SF 2 "general_operand" "fdmF")))]
1922: "TARGET_68881"
1923: "*
1924: {
1925: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
1926: return \"fsub%.x %2,%0\";
1927: return \"fsub%.s %f2,%0\";
1928: }")
1929:
1930: ;; multiply instructions
1931:
1932: (define_insn "mulhi3"
1933: [(set (match_operand:HI 0 "general_operand" "=d")
1934: (mult:HI (match_operand:HI 1 "general_operand" "%0")
1935: (match_operand:HI 2 "general_operand" "dmn")))]
1936: ""
1937: "*
1938: {
1939: #ifdef MOTOROLA
1940: return \"muls.w %2,%0\";
1941: #else
1942: return \"muls %2,%0\";
1943: #endif
1944: }")
1945:
1946: (define_insn "mulhisi3"
1947: [(set (match_operand:SI 0 "general_operand" "=d")
1948: (mult:SI (match_operand:HI 1 "general_operand" "%0")
1949: (match_operand:HI 2 "general_operand" "dmn")))]
1950: ""
1951: "*
1952: {
1953: #ifdef MOTOROLA
1954: return \"muls.w %2,%0\";
1955: #else
1956: return \"muls %2,%0\";
1957: #endif
1958: }")
1959:
1960: (define_insn "mulsi3"
1961: [(set (match_operand:SI 0 "general_operand" "=d")
1962: (mult:SI (match_operand:SI 1 "general_operand" "%0")
1963: (match_operand:SI 2 "general_operand" "dmsK")))]
1964: "TARGET_68020"
1965: "muls%.l %2,%0")
1966:
1967: (define_insn "umulhi3"
1968: [(set (match_operand:HI 0 "general_operand" "=d")
1969: (umult:HI (match_operand:HI 1 "general_operand" "%0")
1970: (match_operand:HI 2 "general_operand" "dmn")))]
1971: ""
1972: "*
1973: {
1974: #ifdef MOTOROLA
1975: return \"mulu.w %2,%0\";
1976: #else
1977: return \"mulu %2,%0\";
1978: #endif
1979: }")
1980:
1981: (define_insn "umulhisi3"
1982: [(set (match_operand:SI 0 "general_operand" "=d")
1983: (umult:SI (match_operand:HI 1 "general_operand" "%0")
1984: (match_operand:HI 2 "general_operand" "dmn")))]
1985: ""
1986: "*
1987: {
1988: #ifdef MOTOROLA
1989: return \"mulu.w %2,%0\";
1990: #else
1991: return \"mulu %2,%0\";
1992: #endif
1993: }")
1994:
1995: (define_insn "umulsi3"
1996: [(set (match_operand:SI 0 "general_operand" "=d")
1997: (umult:SI (match_operand:SI 1 "general_operand" "%0")
1998: (match_operand:SI 2 "general_operand" "dmsK")))]
1999: "TARGET_68020"
2000: "mulu%.l %2,%0")
2001:
2002: (define_expand "muldf3"
2003: [(set (match_operand:DF 0 "general_operand" "")
2004: (mult:DF (match_operand:DF 1 "general_operand" "")
2005: (match_operand:DF 2 "general_operand" "")))]
2006: "TARGET_68881 || TARGET_FPA"
2007: "")
2008:
2009: (define_insn ""
2010: [(set (match_operand:DF 0 "general_operand" "=x,y")
2011: (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
2012: (match_operand:DF 2 "general_operand" "xH,rmF")))]
2013: "TARGET_FPA"
2014: "*
2015: {
2016: if (rtx_equal_p (operands[1], operands[2]))
2017: return \"fpsqr%.d %y1,%0\";
2018: if (rtx_equal_p (operands[0], operands[1]))
2019: return \"fpmul%.d %y2,%0\";
2020: if (rtx_equal_p (operands[0], operands[2]))
2021: return \"fpmul%.d %y1,%0\";
2022: if (which_alternative == 0)
2023: return \"fpmul3%.d %w2,%w1,%0\";
2024: return \"fpmul3%.d %x2,%x1,%0\";
2025: }")
2026:
2027: (define_insn ""
2028: [(set (match_operand:DF 0 "general_operand" "=f")
2029: (mult:DF (match_operand:DF 1 "general_operand" "%0")
2030: (match_operand:DF 2 "general_operand" "fmG")))]
2031: "TARGET_68881"
2032: "*
2033: {
2034: if (REG_P (operands[2]))
2035: return \"fmul%.x %2,%0\";
2036: return \"fmul%.d %f2,%0\";
2037: }")
2038:
2039: (define_expand "mulsf3"
2040: [(set (match_operand:SF 0 "general_operand" "")
2041: (mult:SF (match_operand:SF 1 "general_operand" "")
2042: (match_operand:SF 2 "general_operand" "")))]
2043: "TARGET_68881 || TARGET_FPA"
2044: "")
2045:
2046: (define_insn ""
2047: [(set (match_operand:SF 0 "general_operand" "=x,y")
2048: (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
2049: (match_operand:SF 2 "general_operand" "xH,rmF")))]
2050: "TARGET_FPA"
2051: "*
2052: {
2053: if (rtx_equal_p (operands[1], operands[2]))
2054: return \"fpsqr%.s %w1,%0\";
2055: if (rtx_equal_p (operands[0], operands[1]))
2056: return \"fpmul%.s %w2,%0\";
2057: if (rtx_equal_p (operands[0], operands[2]))
2058: return \"fpmul%.s %w1,%0\";
2059: if (which_alternative == 0)
2060: return \"fpmul3%.s %w2,%w1,%0\";
2061: return \"fpmul3%.s %2,%1,%0\";
2062: }")
2063:
2064: (define_insn ""
2065: [(set (match_operand:SF 0 "general_operand" "=f")
2066: (mult:SF (match_operand:SF 1 "general_operand" "%0")
2067: (match_operand:SF 2 "general_operand" "fdmF")))]
2068: "TARGET_68881"
2069: "*
2070: {
2071: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2072: return \"fsglmul%.x %2,%0\";
2073: return \"fsglmul%.s %f2,%0\";
2074: }")
2075:
2076: ;; divide instructions
2077:
2078: (define_insn "divhi3"
2079: [(set (match_operand:HI 0 "general_operand" "=d")
2080: (div:HI (match_operand:HI 1 "general_operand" "0")
2081: (match_operand:HI 2 "general_operand" "dmn")))]
2082: ""
2083: "*
2084: {
2085: #ifdef MOTOROLA
2086: return \"ext.l %0\;divs.w %2,%0\";
2087: #else
2088: return \"extl %0\;divs %2,%0\";
2089: #endif
2090: }")
2091:
2092: (define_insn "divhisi3"
2093: [(set (match_operand:HI 0 "general_operand" "=d")
2094: (div:HI (match_operand:SI 1 "general_operand" "0")
2095: (match_operand:HI 2 "general_operand" "dmn")))]
2096: ""
2097: "*
2098: {
2099: #ifdef MOTOROLA
2100: return \"divs.w %2,%0\";
2101: #else
2102: return \"divs %2,%0\";
2103: #endif
2104: }")
2105:
2106: (define_insn "divsi3"
2107: [(set (match_operand:SI 0 "general_operand" "=d")
2108: (div:SI (match_operand:SI 1 "general_operand" "0")
2109: (match_operand:SI 2 "general_operand" "dmsK")))]
2110: "TARGET_68020"
2111: "divs%.l %2,%0")
2112:
2113: (define_insn "udivhi3"
2114: [(set (match_operand:HI 0 "general_operand" "=d")
2115: (udiv:HI (match_operand:HI 1 "general_operand" "0")
2116: (match_operand:HI 2 "general_operand" "dmn")))]
2117: ""
2118: "*
2119: {
2120: #ifdef MOTOROLA
2121: return \"and.l %#0xFFFF,%0\;divu.w %2,%0\";
2122: #else
2123: return \"andl %#0xFFFF,%0\;divu %2,%0\";
2124: #endif
2125: }")
2126:
2127: (define_insn "udivhisi3"
2128: [(set (match_operand:HI 0 "general_operand" "=d")
2129: (udiv:HI (match_operand:SI 1 "general_operand" "0")
2130: (match_operand:HI 2 "general_operand" "dmn")))]
2131: ""
2132: "*
2133: {
2134: #ifdef MOTOROLA
2135: return \"divu.w %2,%0\";
2136: #else
2137: return \"divu %2,%0\";
2138: #endif
2139: }")
2140:
2141: (define_insn "udivsi3"
2142: [(set (match_operand:SI 0 "general_operand" "=d")
2143: (udiv:SI (match_operand:SI 1 "general_operand" "0")
2144: (match_operand:SI 2 "general_operand" "dmsK")))]
2145: "TARGET_68020"
2146: "divu%.l %2,%0")
2147:
2148: (define_expand "divdf3"
2149: [(set (match_operand:DF 0 "general_operand" "")
2150: (div:DF (match_operand:DF 1 "general_operand" "")
2151: (match_operand:DF 2 "general_operand" "")))]
2152: "TARGET_68881 || TARGET_FPA"
2153: "")
2154:
2155: (define_insn ""
2156: [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2157: (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
2158: (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
2159: "TARGET_FPA"
2160: "*
2161: {
2162: if (rtx_equal_p (operands[0], operands[2]))
2163: return \"fprdiv%.d %y1,%0\";
2164: if (rtx_equal_p (operands[0], operands[1]))
2165: return \"fpdiv%.d %y2,%0\";
2166: if (which_alternative == 0)
2167: return \"fpdiv3%.d %w2,%w1,%0\";
2168: return \"fpdiv3%.d %x2,%x1,%x0\";
2169: }")
2170:
2171: (define_insn ""
2172: [(set (match_operand:DF 0 "general_operand" "=f")
2173: (div:DF (match_operand:DF 1 "general_operand" "0")
2174: (match_operand:DF 2 "general_operand" "fmG")))]
2175: "TARGET_68881"
2176: "*
2177: {
2178: if (REG_P (operands[2]))
2179: return \"fdiv%.x %2,%0\";
2180: return \"fdiv%.d %f2,%0\";
2181: }")
2182:
2183: (define_expand "divsf3"
2184: [(set (match_operand:SF 0 "general_operand" "")
2185: (div:SF (match_operand:SF 1 "general_operand" "")
2186: (match_operand:SF 2 "general_operand" "")))]
2187: "TARGET_68881 || TARGET_FPA"
2188: "")
2189:
2190: (define_insn ""
2191: [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2192: (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2193: (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2194: "TARGET_FPA"
2195: "*
2196: {
2197: if (rtx_equal_p (operands[0], operands[1]))
2198: return \"fpdiv%.s %w2,%0\";
2199: if (rtx_equal_p (operands[0], operands[2]))
2200: return \"fprdiv%.s %w1,%0\";
2201: if (which_alternative == 0)
2202: return \"fpdiv3%.s %w2,%w1,%0\";
2203: return \"fpdiv3%.s %2,%1,%0\";
2204: }")
2205:
2206: (define_insn ""
2207: [(set (match_operand:SF 0 "general_operand" "=f")
2208: (div:SF (match_operand:SF 1 "general_operand" "0")
2209: (match_operand:SF 2 "general_operand" "fdmF")))]
2210: "TARGET_68881"
2211: "*
2212: {
2213: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2214: return \"fsgldiv%.x %2,%0\";
2215: return \"fsgldiv%.s %f2,%0\";
2216: }")
2217:
2218: ;; Remainder instructions.
2219:
2220: (define_insn "modhi3"
2221: [(set (match_operand:HI 0 "general_operand" "=d")
2222: (mod:HI (match_operand:HI 1 "general_operand" "0")
2223: (match_operand:HI 2 "general_operand" "dmn")))]
2224: ""
2225: "*
2226: {
2227: /* The swap insn produces cc's that don't correspond to the result. */
2228: CC_STATUS_INIT;
2229: #ifdef MOTOROLA
2230: #ifdef SGS_3B1
2231: return \"ext.l %0\;divs.w %2,%0\;swap.w %0\";
2232: #else
2233: return \"ext.l %0\;divs.w %2,%0\;swap %0\";
2234: #endif
2235: #else
2236: return \"extl %0\;divs %2,%0\;swap %0\";
2237: #endif
2238: }")
2239:
2240: (define_insn "modhisi3"
2241: [(set (match_operand:HI 0 "general_operand" "=d")
2242: (mod:HI (match_operand:SI 1 "general_operand" "0")
2243: (match_operand:HI 2 "general_operand" "dmn")))]
2244: ""
2245: "*
2246: {
2247: /* The swap insn produces cc's that don't correspond to the result. */
2248: CC_STATUS_INIT;
2249: #ifdef MOTOROLA
2250: #ifdef SGS_3B1
2251: return \"divs.w %2,%0\;swap.w %0\";
2252: #else
2253: return \"divs.w %2,%0\;swap %0\";
2254: #endif
2255: #else
2256: return \"divs %2,%0\;swap %0\";
2257: #endif
2258: }")
2259:
2260: (define_insn "umodhi3"
2261: [(set (match_operand:HI 0 "general_operand" "=d")
2262: (umod:HI (match_operand:HI 1 "general_operand" "0")
2263: (match_operand:HI 2 "general_operand" "dmn")))]
2264: ""
2265: "*
2266: {
2267: /* The swap insn produces cc's that don't correspond to the result. */
2268: CC_STATUS_INIT;
2269: #ifdef MOTOROLA
2270: #ifdef SGS_3B1
2271: return \"and.l %#0xFFFF,%0\;divu.w %2,%0\;swap.w %0\";
2272: #else
2273: return \"and.l %#0xFFFF,%0\;divu.w %2,%0\;swap %0\";
2274: #endif
2275: #else
2276: return \"andl %#0xFFFF,%0\;divu %2,%0\;swap %0\";
2277: #endif
2278: }")
2279:
2280: (define_insn "umodhisi3"
2281: [(set (match_operand:HI 0 "general_operand" "=d")
2282: (umod:HI (match_operand:SI 1 "general_operand" "0")
2283: (match_operand:HI 2 "general_operand" "dmn")))]
2284: ""
2285: "*
2286: {
2287: /* The swap insn produces cc's that don't correspond to the result. */
2288: CC_STATUS_INIT;
2289: #ifdef MOTOROLA
2290: #ifdef SGS_3B1
2291: return \"divu.w %2,%0\;swap.w %0\";
2292: #else
2293: return \"divu.w %2,%0\;swap %0\";
2294: #endif
2295: #else
2296: return \"divu %2,%0\;swap %0\";
2297: #endif
2298: }")
2299:
2300: (define_insn "divmodsi4"
2301: [(set (match_operand:SI 0 "general_operand" "=d")
2302: (div:SI (match_operand:SI 1 "general_operand" "0")
2303: (match_operand:SI 2 "general_operand" "dmsK")))
2304: (set (match_operand:SI 3 "general_operand" "=d")
2305: (mod:SI (match_dup 1) (match_dup 2)))]
2306: "TARGET_68020"
2307: "divsl%.l %2,%3:%0")
2308:
2309: (define_insn "udivmodsi4"
2310: [(set (match_operand:SI 0 "general_operand" "=d")
2311: (udiv:SI (match_operand:SI 1 "general_operand" "0")
2312: (match_operand:SI 2 "general_operand" "dmsK")))
2313: (set (match_operand:SI 3 "general_operand" "=d")
2314: (umod:SI (match_dup 1) (match_dup 2)))]
2315: "TARGET_68020"
2316: "divul%.l %2,%3:%0")
2317:
2318: ;; logical-and instructions
2319:
2320: (define_insn "andsi3"
2321: [(set (match_operand:SI 0 "general_operand" "=m,d")
2322: (and:SI (match_operand:SI 1 "general_operand" "%0,0")
2323: (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
2324: ""
2325: "*
2326: {
2327: if (GET_CODE (operands[2]) == CONST_INT
2328: && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
2329: && (DATA_REG_P (operands[0])
2330: || offsettable_memref_p (operands[0])))
2331: {
2332: if (GET_CODE (operands[0]) != REG)
2333: operands[0] = adj_offsettable_operand (operands[0], 2);
2334: operands[2] = gen_rtx (CONST_INT, VOIDmode,
2335: INTVAL (operands[2]) & 0xffff);
2336: /* Do not delete a following tstl %0 insn; that would be incorrect. */
2337: CC_STATUS_INIT;
2338: if (operands[2] == const0_rtx)
2339: return \"clr%.w %0\";
2340: return \"and%.w %2,%0\";
2341: }
2342: return \"and%.l %2,%0\";
2343: }")
2344:
2345: (define_insn "andhi3"
2346: [(set (match_operand:HI 0 "general_operand" "=m,d")
2347: (and:HI (match_operand:HI 1 "general_operand" "%0,0")
2348: (match_operand:HI 2 "general_operand" "dn,dmn")))]
2349: ""
2350: "and%.w %2,%0")
2351:
2352: (define_insn "andqi3"
2353: [(set (match_operand:QI 0 "general_operand" "=m,d")
2354: (and:QI (match_operand:QI 1 "general_operand" "%0,0")
2355: (match_operand:QI 2 "general_operand" "dn,dmn")))]
2356: ""
2357: "and%.b %2,%0")
2358:
2359: (define_insn ""
2360: [(set (match_operand:SI 0 "general_operand" "=d")
2361: (and:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dm"))
2362: (match_operand:SI 2 "general_operand" "0")))]
2363: "GET_CODE (operands[2]) == CONST_INT
2364: && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))"
2365: "and%.w %1,%0")
2366:
2367: (define_insn ""
2368: [(set (match_operand:SI 0 "general_operand" "=d")
2369: (and:SI (zero_extend:SI (match_operand:QI 1 "general_operand" "dm"))
2370: (match_operand:SI 2 "general_operand" "0")))]
2371: "GET_CODE (operands[2]) == CONST_INT
2372: && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (QImode))"
2373: "and%.b %1,%0")
2374:
2375: ;; inclusive-or instructions
2376:
2377: (define_insn "iorsi3"
2378: [(set (match_operand:SI 0 "general_operand" "=m,d")
2379: (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
2380: (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
2381: ""
2382: "*
2383: {
2384: register int logval;
2385: if (GET_CODE (operands[2]) == CONST_INT
2386: && INTVAL (operands[2]) >> 16 == 0
2387: && (DATA_REG_P (operands[0])
2388: || offsettable_memref_p (operands[0])))
2389: {
2390: if (GET_CODE (operands[0]) != REG)
2391: operands[0] = adj_offsettable_operand (operands[0], 2);
2392: /* Do not delete a following tstl %0 insn; that would be incorrect. */
2393: CC_STATUS_INIT;
2394: return \"or%.w %2,%0\";
2395: }
2396: if (GET_CODE (operands[2]) == CONST_INT
2397: && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
2398: && (DATA_REG_P (operands[0])
2399: || offsettable_memref_p (operands[0])))
2400: {
2401: if (DATA_REG_P (operands[0]))
2402: {
2403: operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
2404: }
2405: else
2406: {
2407: operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
2408: operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
2409: }
2410: return \"bset %1,%0\";
2411: }
2412: return \"or%.l %2,%0\";
2413: }")
2414:
2415: (define_insn "iorhi3"
2416: [(set (match_operand:HI 0 "general_operand" "=m,d")
2417: (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
2418: (match_operand:HI 2 "general_operand" "dn,dmn")))]
2419: ""
2420: "or%.w %2,%0")
2421:
2422: (define_insn "iorqi3"
2423: [(set (match_operand:QI 0 "general_operand" "=m,d")
2424: (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
2425: (match_operand:QI 2 "general_operand" "dn,dmn")))]
2426: ""
2427: "or%.b %2,%0")
2428:
2429: ;; xor instructions
2430:
2431: (define_insn "xorsi3"
2432: [(set (match_operand:SI 0 "general_operand" "=do,m")
2433: (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
2434: (match_operand:SI 2 "general_operand" "di,dKs")))]
2435: ""
2436: "*
2437: {
2438: if (GET_CODE (operands[2]) == CONST_INT
2439: && INTVAL (operands[2]) >> 16 == 0
2440: && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
2441: {
2442: if (! DATA_REG_P (operands[0]))
2443: operands[0] = adj_offsettable_operand (operands[0], 2);
2444: /* Do not delete a following tstl %0 insn; that would be incorrect. */
2445: CC_STATUS_INIT;
2446: return \"eor%.w %2,%0\";
2447: }
2448: return \"eor%.l %2,%0\";
2449: }")
2450:
2451: (define_insn "xorhi3"
2452: [(set (match_operand:HI 0 "general_operand" "=dm")
2453: (xor:HI (match_operand:HI 1 "general_operand" "%0")
2454: (match_operand:HI 2 "general_operand" "dn")))]
2455: ""
2456: "eor%.w %2,%0")
2457:
2458: (define_insn "xorqi3"
2459: [(set (match_operand:QI 0 "general_operand" "=dm")
2460: (xor:QI (match_operand:QI 1 "general_operand" "%0")
2461: (match_operand:QI 2 "general_operand" "dn")))]
2462: ""
2463: "eor%.b %2,%0")
2464:
2465: ;; negation instructions
2466:
2467: (define_insn "negsi2"
2468: [(set (match_operand:SI 0 "general_operand" "=dm")
2469: (neg:SI (match_operand:SI 1 "general_operand" "0")))]
2470: ""
2471: "neg%.l %0")
2472:
2473: (define_insn "neghi2"
2474: [(set (match_operand:HI 0 "general_operand" "=dm")
2475: (neg:HI (match_operand:HI 1 "general_operand" "0")))]
2476: ""
2477: "neg%.w %0")
2478:
2479: (define_insn "negqi2"
2480: [(set (match_operand:QI 0 "general_operand" "=dm")
2481: (neg:QI (match_operand:QI 1 "general_operand" "0")))]
2482: ""
2483: "neg%.b %0")
2484:
2485: (define_expand "negsf2"
2486: [(set (match_operand:SF 0 "general_operand" "")
2487: (neg:SF (match_operand:SF 1 "general_operand" "")))]
2488: "TARGET_68881 || TARGET_FPA"
2489: "")
2490:
2491: (define_insn ""
2492: [(set (match_operand:SF 0 "general_operand" "=x,y")
2493: (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
2494: "TARGET_FPA"
2495: "fpneg%.s %w1,%0")
2496:
2497: (define_insn ""
2498: [(set (match_operand:SF 0 "general_operand" "=f")
2499: (neg:SF (match_operand:SF 1 "general_operand" "fdmF")))]
2500: "TARGET_68881"
2501: "*
2502: {
2503: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
2504: return \"fneg%.x %1,%0\";
2505: return \"fneg%.s %f1,%0\";
2506: }")
2507:
2508: (define_expand "negdf2"
2509: [(set (match_operand:DF 0 "general_operand" "")
2510: (neg:DF (match_operand:DF 1 "general_operand" "")))]
2511: "TARGET_68881 || TARGET_FPA"
2512: "")
2513:
2514: (define_insn ""
2515: [(set (match_operand:DF 0 "general_operand" "=x,y")
2516: (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
2517: "TARGET_FPA"
2518: "fpneg%.d %y1, %0")
2519:
2520: (define_insn ""
2521: [(set (match_operand:DF 0 "general_operand" "=f")
2522: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
2523: "TARGET_68881"
2524: "*
2525: {
2526: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
2527: return \"fneg%.x %1,%0\";
2528: return \"fneg%.d %f1,%0\";
2529: }")
2530:
2531: ;; Absolute value instructions
2532:
2533: (define_expand "abssf2"
2534: [(set (match_operand:SF 0 "general_operand" "")
2535: (abs:SF (match_operand:SF 1 "general_operand" "")))]
2536: "TARGET_68881 || TARGET_FPA"
2537: "")
2538:
2539: (define_insn ""
2540: [(set (match_operand:SF 0 "general_operand" "=x,y")
2541: (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
2542: "TARGET_FPA"
2543: "fpabs%.s %y1,%0")
2544:
2545: (define_insn ""
2546: [(set (match_operand:SF 0 "general_operand" "=f")
2547: (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
2548: "TARGET_68881"
2549: "*
2550: {
2551: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
2552: return \"fabs%.x %1,%0\";
2553: return \"fabs%.s %f1,%0\";
2554: }")
2555:
2556: (define_expand "absdf2"
2557: [(set (match_operand:DF 0 "general_operand" "")
2558: (abs:DF (match_operand:DF 1 "general_operand" "")))]
2559: "TARGET_68881 || TARGET_FPA"
2560: "")
2561:
2562: (define_insn ""
2563: [(set (match_operand:DF 0 "general_operand" "=x,y")
2564: (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
2565: "TARGET_FPA"
2566: "fpabs%.d %y1,%0")
2567:
2568: (define_insn ""
2569: [(set (match_operand:DF 0 "general_operand" "=f")
2570: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2571: "TARGET_68881"
2572: "*
2573: {
2574: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
2575: return \"fabs%.x %1,%0\";
2576: return \"fabs%.d %f1,%0\";
2577: }")
2578:
2579: ;; one complement instructions
2580:
2581: (define_insn "one_cmplsi2"
2582: [(set (match_operand:SI 0 "general_operand" "=dm")
2583: (not:SI (match_operand:SI 1 "general_operand" "0")))]
2584: ""
2585: "not%.l %0")
2586:
2587: (define_insn "one_cmplhi2"
2588: [(set (match_operand:HI 0 "general_operand" "=dm")
2589: (not:HI (match_operand:HI 1 "general_operand" "0")))]
2590: ""
2591: "not%.w %0")
2592:
2593: (define_insn "one_cmplqi2"
2594: [(set (match_operand:QI 0 "general_operand" "=dm")
2595: (not:QI (match_operand:QI 1 "general_operand" "0")))]
2596: ""
2597: "not%.b %0")
2598:
2599: ;; Optimized special case of shifting.
2600: ;; Must precede the general case.
2601:
2602: (define_insn ""
2603: [(set (match_operand:SI 0 "general_operand" "=d")
2604: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
2605: (const_int 24)))]
2606: "GET_CODE (XEXP (operands[1], 0)) != POST_INC
2607: && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
2608: "*
2609: {
2610: if (TARGET_68020)
2611: return \"move%.b %1,%0\;extb%.l %0\";
2612: return \"move%.b %1,%0\;ext%.w %0\;ext%.l %0\";
2613: }")
2614:
2615: (define_insn ""
2616: [(set (match_operand:SI 0 "general_operand" "=d")
2617: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
2618: (const_int 24)))]
2619: "GET_CODE (XEXP (operands[1], 0)) != POST_INC
2620: && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
2621: "*
2622: {
2623: if (reg_mentioned_p (operands[0], operands[1]))
2624: return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
2625: return \"clr%.l %0\;move%.b %1,%0\";
2626: }")
2627:
2628: (define_insn ""
2629: [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
2630: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
2631: (const_int 24))))]
2632: "(GET_CODE (operands[0]) == CONST_INT
2633: && (INTVAL (operands[0]) & ~0xff) == 0)"
2634: "* cc_status.flags |= CC_REVERSED;
2635: #ifdef HPUX_ASM
2636: return \"cmp%.b %1,%0\";
2637: #else
2638: return \"cmp%.b %0,%1\";
2639: #endif
2640: ")
2641:
2642: (define_insn ""
2643: [(set (cc0) (compare (lshiftrt:SI (match_operand:SI 0 "memory_operand" "m")
2644: (const_int 24))
2645: (match_operand:QI 1 "general_operand" "i")))]
2646: "(GET_CODE (operands[1]) == CONST_INT
2647: && (INTVAL (operands[1]) & ~0xff) == 0)"
2648: "*
2649: #ifdef HPUX_ASM
2650: return \"cmp%.b %0,%1\";
2651: #else
2652: return \"cmp%.b %1,%0\";
2653: #endif
2654: ")
2655:
2656: (define_insn ""
2657: [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
2658: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
2659: (const_int 24))))]
2660: "(GET_CODE (operands[0]) == CONST_INT
2661: && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0)"
2662: "* cc_status.flags |= CC_REVERSED;
2663: #ifdef HPUX_ASM
2664: return \"cmp%.b %1,%0\";
2665: #else
2666: return \"cmp%.b %0,%1\";
2667: #endif
2668: ")
2669:
2670: (define_insn ""
2671: [(set (cc0) (compare (ashiftrt:SI (match_operand:SI 0 "memory_operand" "m")
2672: (const_int 24))
2673: (match_operand:QI 1 "general_operand" "i")))]
2674: "(GET_CODE (operands[1]) == CONST_INT
2675: && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0)"
2676: "*
2677: #ifdef HPUX_ASM
2678: return \"cmp%.b %0,%1\";
2679: #else
2680: return \"cmp%.b %1,%0\";
2681: #endif
2682: ")
2683:
2684: ;; arithmetic shift instructions
2685: ;; We don't need the shift memory by 1 bit instruction
2686:
2687: (define_insn "ashlsi3"
2688: [(set (match_operand:SI 0 "general_operand" "=d")
2689: (ashift:SI (match_operand:SI 1 "general_operand" "0")
2690: (match_operand:SI 2 "general_operand" "dI")))]
2691: ""
2692: "asl%.l %2,%0")
2693:
2694: (define_insn "ashlhi3"
2695: [(set (match_operand:HI 0 "general_operand" "=d")
2696: (ashift:HI (match_operand:HI 1 "general_operand" "0")
2697: (match_operand:HI 2 "general_operand" "dI")))]
2698: ""
2699: "asl%.w %2,%0")
2700:
2701: (define_insn "ashlqi3"
2702: [(set (match_operand:QI 0 "general_operand" "=d")
2703: (ashift:QI (match_operand:QI 1 "general_operand" "0")
2704: (match_operand:QI 2 "general_operand" "dI")))]
2705: ""
2706: "asl%.b %2,%0")
2707:
2708: (define_insn "ashrsi3"
2709: [(set (match_operand:SI 0 "general_operand" "=d")
2710: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
2711: (match_operand:SI 2 "general_operand" "dI")))]
2712: ""
2713: "asr%.l %2,%0")
2714:
2715: (define_insn "ashrhi3"
2716: [(set (match_operand:HI 0 "general_operand" "=d")
2717: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
2718: (match_operand:HI 2 "general_operand" "dI")))]
2719: ""
2720: "asr%.w %2,%0")
2721:
2722: (define_insn "ashrqi3"
2723: [(set (match_operand:QI 0 "general_operand" "=d")
2724: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
2725: (match_operand:QI 2 "general_operand" "dI")))]
2726: ""
2727: "asr%.b %2,%0")
2728:
2729: ;; logical shift instructions
2730:
2731: (define_insn "lshlsi3"
2732: [(set (match_operand:SI 0 "general_operand" "=d")
2733: (lshift:SI (match_operand:SI 1 "general_operand" "0")
2734: (match_operand:SI 2 "general_operand" "dI")))]
2735: ""
2736: "lsl%.l %2,%0")
2737:
2738: (define_insn "lshlhi3"
2739: [(set (match_operand:HI 0 "general_operand" "=d")
2740: (lshift:HI (match_operand:HI 1 "general_operand" "0")
2741: (match_operand:HI 2 "general_operand" "dI")))]
2742: ""
2743: "lsl%.w %2,%0")
2744:
2745: (define_insn "lshlqi3"
2746: [(set (match_operand:QI 0 "general_operand" "=d")
2747: (lshift:QI (match_operand:QI 1 "general_operand" "0")
2748: (match_operand:QI 2 "general_operand" "dI")))]
2749: ""
2750: "lsl%.b %2,%0")
2751:
2752: (define_insn "lshrsi3"
2753: [(set (match_operand:SI 0 "general_operand" "=d")
2754: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
2755: (match_operand:SI 2 "general_operand" "dI")))]
2756: ""
2757: "lsr%.l %2,%0")
2758:
2759: (define_insn "lshrhi3"
2760: [(set (match_operand:HI 0 "general_operand" "=d")
2761: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
2762: (match_operand:HI 2 "general_operand" "dI")))]
2763: ""
2764: "lsr%.w %2,%0")
2765:
2766: (define_insn "lshrqi3"
2767: [(set (match_operand:QI 0 "general_operand" "=d")
2768: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
2769: (match_operand:QI 2 "general_operand" "dI")))]
2770: ""
2771: "lsr%.b %2,%0")
2772:
2773: ;; rotate instructions
2774:
2775: (define_insn "rotlsi3"
2776: [(set (match_operand:SI 0 "general_operand" "=d")
2777: (rotate:SI (match_operand:SI 1 "general_operand" "0")
2778: (match_operand:SI 2 "general_operand" "dI")))]
2779: ""
2780: "rol%.l %2,%0")
2781:
2782: (define_insn "rotlhi3"
2783: [(set (match_operand:HI 0 "general_operand" "=d")
2784: (rotate:HI (match_operand:HI 1 "general_operand" "0")
2785: (match_operand:HI 2 "general_operand" "dI")))]
2786: ""
2787: "rol%.w %2,%0")
2788:
2789: (define_insn "rotlqi3"
2790: [(set (match_operand:QI 0 "general_operand" "=d")
2791: (rotate:QI (match_operand:QI 1 "general_operand" "0")
2792: (match_operand:QI 2 "general_operand" "dI")))]
2793: ""
2794: "rol%.b %2,%0")
2795:
2796: (define_insn "rotrsi3"
2797: [(set (match_operand:SI 0 "general_operand" "=d")
2798: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
2799: (match_operand:SI 2 "general_operand" "dI")))]
2800: ""
2801: "ror%.l %2,%0")
2802:
2803: (define_insn "rotrhi3"
2804: [(set (match_operand:HI 0 "general_operand" "=d")
2805: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
2806: (match_operand:HI 2 "general_operand" "dI")))]
2807: ""
2808: "ror%.w %2,%0")
2809:
2810: (define_insn "rotrqi3"
2811: [(set (match_operand:QI 0 "general_operand" "=d")
2812: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
2813: (match_operand:QI 2 "general_operand" "dI")))]
2814: ""
2815: "ror%.b %2,%0")
2816:
2817: ;; Special cases of bit-field insns which we should
2818: ;; recognize in preference to the general case.
2819: ;; These handle aligned 8-bit and 16-bit fields,
2820: ;; which can usually be done with move instructions.
2821:
2822: (define_insn ""
2823: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do")
2824: (match_operand:SI 1 "immediate_operand" "i")
2825: (match_operand:SI 2 "immediate_operand" "i"))
2826: (match_operand:SI 3 "general_operand" "d"))]
2827: "TARGET_68020 && TARGET_BITFIELD
2828: && GET_CODE (operands[1]) == CONST_INT
2829: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
2830: && GET_CODE (operands[2]) == CONST_INT
2831: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
2832: && (GET_CODE (operands[0]) == REG
2833: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
2834: "*
2835: {
2836: if (REG_P (operands[0]))
2837: {
2838: if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
2839: return \"bfins %3,%0{%b2:%b1}\";
2840: }
2841: else
2842: operands[0]
2843: = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
2844:
2845: if (GET_CODE (operands[3]) == MEM)
2846: operands[3] = adj_offsettable_operand (operands[3],
2847: (32 - INTVAL (operands[1])) / 8);
2848: if (INTVAL (operands[1]) == 8)
2849: return \"move%.b %3,%0\";
2850: return \"move%.w %3,%0\";
2851: }")
2852:
2853: (define_insn ""
2854: [(set (match_operand:SI 0 "general_operand" "=&d")
2855: (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
2856: (match_operand:SI 2 "immediate_operand" "i")
2857: (match_operand:SI 3 "immediate_operand" "i")))]
2858: "TARGET_68020 && TARGET_BITFIELD
2859: && GET_CODE (operands[2]) == CONST_INT
2860: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2861: && GET_CODE (operands[3]) == CONST_INT
2862: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
2863: && (GET_CODE (operands[1]) == REG
2864: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
2865: "*
2866: {
1.1.1.3 ! root 2867: cc_status.flags |= CC_NOT_NEGATIVE;
1.1 root 2868: if (REG_P (operands[1]))
2869: {
2870: if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
2871: return \"bfextu %1{%b3:%b2},%0\";
2872: }
2873: else
2874: operands[1]
2875: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
2876:
2877: output_asm_insn (\"clr%.l %0\", operands);
2878: if (GET_CODE (operands[0]) == MEM)
2879: operands[0] = adj_offsettable_operand (operands[0],
2880: (32 - INTVAL (operands[1])) / 8);
2881: if (INTVAL (operands[2]) == 8)
2882: return \"move%.b %1,%0\";
2883: return \"move%.w %1,%0\";
2884: }")
2885:
2886: (define_insn ""
2887: [(set (match_operand:SI 0 "general_operand" "=d")
2888: (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
2889: (match_operand:SI 2 "immediate_operand" "i")
2890: (match_operand:SI 3 "immediate_operand" "i")))]
2891: "TARGET_68020 && TARGET_BITFIELD
2892: && GET_CODE (operands[2]) == CONST_INT
2893: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2894: && GET_CODE (operands[3]) == CONST_INT
2895: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
2896: && (GET_CODE (operands[1]) == REG
2897: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
2898: "*
2899: {
2900: if (REG_P (operands[1]))
2901: {
2902: if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
2903: return \"bfexts %1{%b3:%b2},%0\";
2904: }
2905: else
2906: operands[1]
2907: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
2908:
2909: if (INTVAL (operands[2]) == 8)
2910: return \"move%.b %1,%0\;extb%.l %0\";
2911: return \"move%.w %1,%0\;ext%.l %0\";
2912: }")
2913:
2914: ;; Bit field instructions, general cases.
2915: ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
2916: ;; so that its address is reloaded.
2917:
2918: (define_insn "extv"
2919: [(set (match_operand:SI 0 "general_operand" "=d,d")
2920: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
2921: (match_operand:SI 2 "general_operand" "di,di")
2922: (match_operand:SI 3 "general_operand" "di,di")))]
2923: "TARGET_68020 && TARGET_BITFIELD"
2924: "bfexts %1{%b3:%b2},%0")
2925:
2926: (define_insn "extzv"
2927: [(set (match_operand:SI 0 "general_operand" "=d,d")
2928: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
2929: (match_operand:SI 2 "general_operand" "di,di")
2930: (match_operand:SI 3 "general_operand" "di,di")))]
2931: "TARGET_68020 && TARGET_BITFIELD"
1.1.1.3 ! root 2932: "*
! 2933: {
! 2934: cc_status.flags |= CC_NOT_NEGATIVE;
! 2935: return \"bfextu %1{%b3:%b2},%0\";
! 2936: }")
1.1 root 2937:
2938: (define_insn ""
2939: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
2940: (match_operand:SI 1 "general_operand" "di,di")
2941: (match_operand:SI 2 "general_operand" "di,di"))
2942: (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
2943: (match_operand 3 "immediate_operand" "i,i")))]
2944: "TARGET_68020 && TARGET_BITFIELD
2945: && GET_CODE (operands[3]) == CONST_INT
2946: && (INTVAL (operands[3]) == -1
2947: || (GET_CODE (operands[1]) == CONST_INT
2948: && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
2949: "*
2950: {
2951: CC_STATUS_INIT;
2952: return \"bfchg %0{%b2:%b1}\";
2953: }")
2954:
2955: (define_insn ""
2956: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
2957: (match_operand:SI 1 "general_operand" "di,di")
2958: (match_operand:SI 2 "general_operand" "di,di"))
2959: (const_int 0))]
2960: "TARGET_68020 && TARGET_BITFIELD"
2961: "*
2962: {
2963: CC_STATUS_INIT;
2964: return \"bfclr %0{%b2:%b1}\";
2965: }")
2966:
2967: (define_insn ""
2968: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
2969: (match_operand:SI 1 "general_operand" "di,di")
2970: (match_operand:SI 2 "general_operand" "di,di"))
2971: (const_int -1))]
2972: "TARGET_68020 && TARGET_BITFIELD"
2973: "*
2974: {
2975: CC_STATUS_INIT;
2976: return \"bfset %0{%b2:%b1}\";
2977: }")
2978:
2979: (define_insn "insv"
2980: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
2981: (match_operand:SI 1 "general_operand" "di,di")
2982: (match_operand:SI 2 "general_operand" "di,di"))
2983: (match_operand:SI 3 "general_operand" "d,d"))]
2984: "TARGET_68020 && TARGET_BITFIELD"
2985: "bfins %3,%0{%b2:%b1}")
2986:
2987: ;; Now recognize bit field insns that operate on registers
2988: ;; (or at least were intended to do so).
2989:
2990: (define_insn ""
2991: [(set (match_operand:SI 0 "general_operand" "=d")
2992: (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
2993: (match_operand:SI 2 "general_operand" "di")
2994: (match_operand:SI 3 "general_operand" "di")))]
2995: "TARGET_68020 && TARGET_BITFIELD"
2996: "bfexts %1{%b3:%b2},%0")
2997:
2998: (define_insn ""
2999: [(set (match_operand:SI 0 "general_operand" "=d")
3000: (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
3001: (match_operand:SI 2 "general_operand" "di")
3002: (match_operand:SI 3 "general_operand" "di")))]
3003: "TARGET_68020 && TARGET_BITFIELD"
1.1.1.3 ! root 3004: "*
! 3005: {
! 3006: cc_status.flags |= CC_NOT_NEGATIVE;
! 3007: return \"bfextu %1{%b3:%b2},%0\";
! 3008: }")
1.1 root 3009:
3010: (define_insn ""
3011: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
3012: (match_operand:SI 1 "general_operand" "di")
3013: (match_operand:SI 2 "general_operand" "di"))
3014: (const_int 0))]
3015: "TARGET_68020 && TARGET_BITFIELD"
3016: "*
3017: {
3018: CC_STATUS_INIT;
3019: return \"bfclr %0{%b2:%b1}\";
3020: }")
3021:
3022: (define_insn ""
3023: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
3024: (match_operand:SI 1 "general_operand" "di")
3025: (match_operand:SI 2 "general_operand" "di"))
3026: (const_int -1))]
3027: "TARGET_68020 && TARGET_BITFIELD"
3028: "*
3029: {
3030: CC_STATUS_INIT;
3031: return \"bfset %0{%b2:%b1}\";
3032: }")
3033:
3034: (define_insn ""
3035: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
3036: (match_operand:SI 1 "general_operand" "di")
3037: (match_operand:SI 2 "general_operand" "di"))
3038: (match_operand:SI 3 "general_operand" "d"))]
3039: "TARGET_68020 && TARGET_BITFIELD"
3040: "*
3041: {
3042: #if 0
3043: /* These special cases are now recognized by a specific pattern. */
3044: if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
3045: && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
3046: return \"move%.w %3,%0\";
3047: if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
3048: && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
3049: return \"move%.b %3,%0\";
3050: #endif
3051: return \"bfins %3,%0{%b2:%b1}\";
3052: }")
3053:
3054: ;; Special patterns for optimizing bit-field instructions.
3055:
3056: (define_insn ""
3057: [(set (cc0)
3058: (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
3059: (match_operand:SI 1 "general_operand" "di")
3060: (match_operand:SI 2 "general_operand" "di")))]
3061: "TARGET_68020 && TARGET_BITFIELD
3062: && GET_CODE (operands[1]) == CONST_INT"
3063: "*
3064: {
3065: if (operands[1] == const1_rtx
3066: && GET_CODE (operands[2]) == CONST_INT)
3067: {
3068: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
3069: return output_btst (operands,
3070: gen_rtx (CONST_INT, VOIDmode,
3071: width - INTVAL (operands[2])),
3072: operands[0],
3073: insn, 1000);
3074: /* Pass 1000 as SIGNPOS argument so that btst will
3075: not think we are testing the sign bit for an `and'
3076: and assume that nonzero implies a negative result. */
3077: }
3078: if (INTVAL (operands[1]) != 32)
3079: cc_status.flags = CC_NOT_NEGATIVE;
3080: return \"bftst %0{%b2:%b1}\";
3081: }")
3082:
3083: (define_insn ""
3084: [(set (cc0)
3085: (subreg:QI
3086: (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
3087: (match_operand:SI 1 "general_operand" "di")
3088: (match_operand:SI 2 "general_operand" "di"))
3089: 0))]
3090: "TARGET_68020 && TARGET_BITFIELD
3091: && GET_CODE (operands[1]) == CONST_INT"
3092: "*
3093: {
3094: if (operands[1] == const1_rtx
3095: && GET_CODE (operands[2]) == CONST_INT)
3096: {
3097: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
3098: return output_btst (operands,
3099: gen_rtx (CONST_INT, VOIDmode,
3100: width - INTVAL (operands[2])),
3101: operands[0],
3102: insn, 1000);
3103: /* Pass 1000 as SIGNPOS argument so that btst will
3104: not think we are testing the sign bit for an `and'
3105: and assume that nonzero implies a negative result. */
3106: }
3107: if (INTVAL (operands[1]) != 32)
3108: cc_status.flags = CC_NOT_NEGATIVE;
3109: return \"bftst %0{%b2:%b1}\";
3110: }")
3111:
3112: (define_insn ""
3113: [(set (cc0)
3114: (subreg:HI
3115: (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
3116: (match_operand:SI 1 "general_operand" "di")
3117: (match_operand:SI 2 "general_operand" "di"))
3118: 0))]
3119: "TARGET_68020 && TARGET_BITFIELD
3120: && GET_CODE (operands[1]) == CONST_INT"
3121: "*
3122: {
3123: if (operands[1] == const1_rtx
3124: && GET_CODE (operands[2]) == CONST_INT)
3125: {
3126: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
3127: return output_btst (operands,
3128: gen_rtx (CONST_INT, VOIDmode,
3129: width - INTVAL (operands[2])),
3130: operands[0],
3131: insn, 1000);
3132: /* Pass 1000 as SIGNPOS argument so that btst will
3133: not think we are testing the sign bit for an `and'
3134: and assume that nonzero implies a negative result. */
3135: }
3136: if (INTVAL (operands[1]) != 32)
3137: cc_status.flags = CC_NOT_NEGATIVE;
3138: return \"bftst %0{%b2:%b1}\";
3139: }")
3140:
3141: ;;; now handle the register cases
3142: (define_insn ""
3143: [(set (cc0)
3144: (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
3145: (match_operand:SI 1 "general_operand" "di")
3146: (match_operand:SI 2 "general_operand" "di")))]
3147: "TARGET_68020 && TARGET_BITFIELD
3148: && GET_CODE (operands[1]) == CONST_INT"
3149: "*
3150: {
3151: if (operands[1] == const1_rtx
3152: && GET_CODE (operands[2]) == CONST_INT)
3153: {
3154: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
3155: return output_btst (operands,
3156: gen_rtx (CONST_INT, VOIDmode,
3157: width - INTVAL (operands[2])),
3158: operands[0],
3159: insn, 1000);
3160: /* Pass 1000 as SIGNPOS argument so that btst will
3161: not think we are testing the sign bit for an `and'
3162: and assume that nonzero implies a negative result. */
3163: }
3164: if (INTVAL (operands[1]) != 32)
3165: cc_status.flags = CC_NOT_NEGATIVE;
3166: return \"bftst %0{%b2:%b1}\";
3167: }")
3168:
3169: (define_insn ""
3170: [(set (cc0)
3171: (subreg:QI
3172: (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
3173: (match_operand:SI 1 "general_operand" "di")
3174: (match_operand:SI 2 "general_operand" "di"))
3175: 0))]
3176: "TARGET_68020 && TARGET_BITFIELD
3177: && GET_CODE (operands[1]) == CONST_INT"
3178: "*
3179: {
3180: if (operands[1] == const1_rtx
3181: && GET_CODE (operands[2]) == CONST_INT)
3182: {
3183: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
3184: return output_btst (operands,
3185: gen_rtx (CONST_INT, VOIDmode,
3186: width - INTVAL (operands[2])),
3187: operands[0],
3188: insn, 1000);
3189: /* Pass 1000 as SIGNPOS argument so that btst will
3190: not think we are testing the sign bit for an `and'
3191: and assume that nonzero implies a negative result. */
3192: }
3193: if (INTVAL (operands[1]) != 32)
3194: cc_status.flags = CC_NOT_NEGATIVE;
3195: return \"bftst %0{%b2:%b1}\";
3196: }")
3197:
3198: (define_insn ""
3199: [(set (cc0)
3200: (subreg:HI
3201: (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
3202: (match_operand:SI 1 "general_operand" "di")
3203: (match_operand:SI 2 "general_operand" "di"))
3204: 0))]
3205: "TARGET_68020 && TARGET_BITFIELD
3206: && GET_CODE (operands[1]) == CONST_INT"
3207: "*
3208: {
3209: if (operands[1] == const1_rtx
3210: && GET_CODE (operands[2]) == CONST_INT)
3211: {
3212: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
3213: return output_btst (operands,
3214: gen_rtx (CONST_INT, VOIDmode,
3215: width - INTVAL (operands[2])),
3216: operands[0],
3217: insn, 1000);
3218: /* Pass 1000 as SIGNPOS argument so that btst will
3219: not think we are testing the sign bit for an `and'
3220: and assume that nonzero implies a negative result. */
3221: }
3222: if (INTVAL (operands[1]) != 32)
3223: cc_status.flags = CC_NOT_NEGATIVE;
3224: return \"bftst %0{%b2:%b1}\";
3225: }")
3226:
3227: (define_insn "seq"
3228: [(set (match_operand:QI 0 "general_operand" "=d")
3229: (eq (cc0) (const_int 0)))]
3230: ""
3231: "*
3232: cc_status = cc_prev_status;
3233: OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
3234: ")
3235:
3236: (define_insn "sne"
3237: [(set (match_operand:QI 0 "general_operand" "=d")
3238: (ne (cc0) (const_int 0)))]
3239: ""
3240: "*
3241: cc_status = cc_prev_status;
3242: OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
3243: ")
3244:
3245: (define_insn "sgt"
3246: [(set (match_operand:QI 0 "general_operand" "=d")
3247: (gt (cc0) (const_int 0)))]
3248: ""
3249: "*
3250: cc_status = cc_prev_status;
3251: OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
3252: ")
3253:
3254: (define_insn "sgtu"
3255: [(set (match_operand:QI 0 "general_operand" "=d")
3256: (gtu (cc0) (const_int 0)))]
3257: ""
3258: "* cc_status = cc_prev_status;
3259: return \"shi %0\"; ")
3260:
3261: (define_insn "slt"
3262: [(set (match_operand:QI 0 "general_operand" "=d")
3263: (lt (cc0) (const_int 0)))]
3264: ""
3265: "* cc_status = cc_prev_status;
3266: OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
3267:
3268: (define_insn "sltu"
3269: [(set (match_operand:QI 0 "general_operand" "=d")
3270: (ltu (cc0) (const_int 0)))]
3271: ""
3272: "* cc_status = cc_prev_status;
3273: return \"scs %0\"; ")
3274:
3275: (define_insn "sge"
3276: [(set (match_operand:QI 0 "general_operand" "=d")
3277: (ge (cc0) (const_int 0)))]
3278: ""
3279: "* cc_status = cc_prev_status;
3280: OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
3281:
3282: (define_insn "sgeu"
3283: [(set (match_operand:QI 0 "general_operand" "=d")
3284: (geu (cc0) (const_int 0)))]
3285: ""
3286: "* cc_status = cc_prev_status;
3287: return \"scc %0\"; ")
3288:
3289: (define_insn "sle"
3290: [(set (match_operand:QI 0 "general_operand" "=d")
3291: (le (cc0) (const_int 0)))]
3292: ""
3293: "*
3294: cc_status = cc_prev_status;
3295: OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
3296: ")
3297:
3298: (define_insn "sleu"
3299: [(set (match_operand:QI 0 "general_operand" "=d")
3300: (leu (cc0) (const_int 0)))]
3301: ""
3302: "* cc_status = cc_prev_status;
3303: return \"sls %0\"; ")
3304:
3305: ;; Basic conditional jump instructions.
3306:
3307: (define_insn "beq"
3308: [(set (pc)
3309: (if_then_else (eq (cc0)
3310: (const_int 0))
3311: (label_ref (match_operand 0 "" ""))
3312: (pc)))]
3313: ""
3314: "*
3315: {
3316: #ifdef MOTOROLA
3317: OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
3318: #else
3319: OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
3320: #endif
3321: }")
3322:
3323: (define_insn "bne"
3324: [(set (pc)
3325: (if_then_else (ne (cc0)
3326: (const_int 0))
3327: (label_ref (match_operand 0 "" ""))
3328: (pc)))]
3329: ""
3330: "*
3331: {
3332: #ifdef MOTOROLA
3333: OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
3334: #else
3335: OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
3336: #endif
3337: }")
3338:
3339: (define_insn "bgt"
3340: [(set (pc)
3341: (if_then_else (gt (cc0)
3342: (const_int 0))
3343: (label_ref (match_operand 0 "" ""))
3344: (pc)))]
3345: ""
3346: "*
3347: #ifdef MOTOROLA
3348: OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
3349: #else
3350: OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
3351: #endif
3352: ")
3353:
3354: (define_insn "bgtu"
3355: [(set (pc)
3356: (if_then_else (gtu (cc0)
3357: (const_int 0))
3358: (label_ref (match_operand 0 "" ""))
3359: (pc)))]
3360: ""
3361: "*
3362: #ifdef MOTOROLA
3363: return \"jbhi %l0\";
3364: #else
3365: return \"jhi %l0\";
3366: #endif
3367: ")
3368:
3369: (define_insn "blt"
3370: [(set (pc)
3371: (if_then_else (lt (cc0)
3372: (const_int 0))
3373: (label_ref (match_operand 0 "" ""))
3374: (pc)))]
3375: ""
3376: "*
3377: #ifdef MOTOROLA
3378: OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
3379: #else
3380: OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
3381: #endif
3382: ")
3383:
3384: (define_insn "bltu"
3385: [(set (pc)
3386: (if_then_else (ltu (cc0)
3387: (const_int 0))
3388: (label_ref (match_operand 0 "" ""))
3389: (pc)))]
3390: ""
3391: "*
3392: #ifdef MOTOROLA
3393: return \"jbcs %l0\";
3394: #else
3395: return \"jcs %l0\";
3396: #endif
3397: ")
3398:
3399: (define_insn "bge"
3400: [(set (pc)
3401: (if_then_else (ge (cc0)
3402: (const_int 0))
3403: (label_ref (match_operand 0 "" ""))
3404: (pc)))]
3405: ""
3406: "*
3407: #ifdef MOTOROLA
3408: OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
3409: #else
3410: OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
3411: #endif
3412: ")
3413:
3414: (define_insn "bgeu"
3415: [(set (pc)
3416: (if_then_else (geu (cc0)
3417: (const_int 0))
3418: (label_ref (match_operand 0 "" ""))
3419: (pc)))]
3420: ""
3421: "*
3422: #ifdef MOTOROLA
3423: return \"jbcc %l0\";
3424: #else
3425: return \"jcc %l0\";
3426: #endif
3427: ")
3428:
3429: (define_insn "ble"
3430: [(set (pc)
3431: (if_then_else (le (cc0)
3432: (const_int 0))
3433: (label_ref (match_operand 0 "" ""))
3434: (pc)))]
3435: ""
3436: "*
3437: #ifdef MOTOROLA
3438: OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
3439: #else
3440: OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
3441: #endif
3442: ")
3443:
3444: (define_insn "bleu"
3445: [(set (pc)
3446: (if_then_else (leu (cc0)
3447: (const_int 0))
3448: (label_ref (match_operand 0 "" ""))
3449: (pc)))]
3450: ""
3451: "*
3452: #ifdef MOTOROLA
3453: return \"jbls %l0\";
3454: #else
3455: return \"jls %l0\";
3456: #endif
3457: ")
3458:
3459: ;; Negated conditional jump instructions.
3460:
3461: (define_insn ""
3462: [(set (pc)
3463: (if_then_else (eq (cc0)
3464: (const_int 0))
3465: (pc)
3466: (label_ref (match_operand 0 "" ""))))]
3467: ""
3468: "*
3469: {
3470: #ifdef MOTOROLA
3471: OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
3472: #else
3473: OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
3474: #endif
3475: }")
3476:
3477: (define_insn ""
3478: [(set (pc)
3479: (if_then_else (ne (cc0)
3480: (const_int 0))
3481: (pc)
3482: (label_ref (match_operand 0 "" ""))))]
3483: ""
3484: "*
3485: {
3486: #ifdef MOTOROLA
3487: OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
3488: #else
3489: OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
3490: #endif
3491: }")
3492:
3493: (define_insn ""
3494: [(set (pc)
3495: (if_then_else (gt (cc0)
3496: (const_int 0))
3497: (pc)
3498: (label_ref (match_operand 0 "" ""))))]
3499: ""
3500: "*
3501: #ifdef MOTOROLA
3502: OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
3503: #else
3504: OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
3505: #endif
3506: ")
3507:
3508: (define_insn ""
3509: [(set (pc)
3510: (if_then_else (gtu (cc0)
3511: (const_int 0))
3512: (pc)
3513: (label_ref (match_operand 0 "" ""))))]
3514: ""
3515: "*
3516: #ifdef MOTOROLA
3517: return \"jbls %l0\";
3518: #else
3519: return \"jls %l0\";
3520: #endif
3521: ")
3522:
3523: (define_insn ""
3524: [(set (pc)
3525: (if_then_else (lt (cc0)
3526: (const_int 0))
3527: (pc)
3528: (label_ref (match_operand 0 "" ""))))]
3529: ""
3530: "*
3531: #ifdef MOTOROLA
3532: OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
3533: #else
3534: OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
3535: #endif
3536: ")
3537:
3538: (define_insn ""
3539: [(set (pc)
3540: (if_then_else (ltu (cc0)
3541: (const_int 0))
3542: (pc)
3543: (label_ref (match_operand 0 "" ""))))]
3544: ""
3545: "*
3546: #ifdef MOTOROLA
3547: return \"jbcc %l0\";
3548: #else
3549: return \"jcc %l0\";
3550: #endif
3551: ")
3552:
3553: (define_insn ""
3554: [(set (pc)
3555: (if_then_else (ge (cc0)
3556: (const_int 0))
3557: (pc)
3558: (label_ref (match_operand 0 "" ""))))]
3559: ""
3560: "*
3561: #ifdef MOTOROLA
3562: OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
3563: #else
3564: OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
3565: #endif
3566: ")
3567:
3568: (define_insn ""
3569: [(set (pc)
3570: (if_then_else (geu (cc0)
3571: (const_int 0))
3572: (pc)
3573: (label_ref (match_operand 0 "" ""))))]
3574: ""
3575: "*
3576: #ifdef MOTOROLA
3577: return \"jbcs %l0\";
3578: #else
3579: return \"jcs %l0\";
3580: #endif
3581: ")
3582:
3583: (define_insn ""
3584: [(set (pc)
3585: (if_then_else (le (cc0)
3586: (const_int 0))
3587: (pc)
3588: (label_ref (match_operand 0 "" ""))))]
3589: ""
3590: "*
3591: #ifdef MOTOROLA
3592: OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
3593: #else
3594: OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
3595: #endif
3596: ")
3597:
3598: (define_insn ""
3599: [(set (pc)
3600: (if_then_else (leu (cc0)
3601: (const_int 0))
3602: (pc)
3603: (label_ref (match_operand 0 "" ""))))]
3604: ""
3605: "*
3606: #ifdef MOTOROLA
3607: return \"jbhi %l0\";
3608: #else
3609: return \"jhi %l0\";
3610: #endif
3611: ")
3612:
3613: ;; Subroutines of "casesi".
3614:
3615: (define_expand "casesi_1"
3616: [(set (match_operand:SI 3 "general_operand" "")
3617: (plus:SI (match_operand:SI 0 "general_operand" "")
3618: ;; Note operand 1 has been negated!
3619: (match_operand:SI 1 "immediate_operand" "")))
3620: (set (cc0) (compare (match_operand:SI 2 "general_operand" "")
3621: (match_dup 3)))
3622: (set (pc) (if_then_else (ltu (cc0) (const_int 0))
3623: (label_ref (match_operand 4 "" "")) (pc)))]
3624: ""
3625: "")
3626:
3627: (define_expand "casesi_2"
3628: [(set (match_operand:SI 0 "" "") (mem:HI (match_operand:SI 1 "" "")))
3629: ;; The USE here is so that at least one jump-insn will refer to the label,
3630: ;; to keep it alive in jump_optimize.
3631: (parallel [(set (pc)
3632: (plus:SI (pc) (match_dup 0)))
3633: (use (label_ref (match_operand 2 "" "")))])]
3634: ""
3635: "")
3636:
3637: ;; Operand 0 is index (in bytes); operand 1 is minimum, operand 2 themaximum;
3638: ;; operand 3 is CODE_LABEL for the table;
3639: ;; operand 4 is the CODE_LABEL to go to if index out of range.
3640: (define_expand "casesi"
3641: ;; We don't use these for generating the RTL, but we must describe
3642: ;; the operands here.
3643: [(match_operand:SI 0 "general_operand" "")
3644: (match_operand:SI 1 "immediate_operand" "")
3645: (match_operand:SI 2 "general_operand" "")
3646: (match_operand 3 "" "")
3647: (match_operand 4 "" "")]
3648: ""
3649: "
3650: {
3651: rtx table_elt_addr;
3652: rtx index_diff;
3653:
3654: operands[1] = negate_rtx (SImode, operands[1]);
3655: index_diff = gen_reg_rtx (SImode);
3656: /* Emit the first few insns. */
3657: emit_insn (gen_casesi_1 (operands[0], operands[1], operands[2],
3658: index_diff, operands[4]));
3659: /* Construct a memory address. This may emit some insns. */
3660: table_elt_addr
3661: = memory_address_noforce
3662: (HImode,
3663: gen_rtx (PLUS, Pmode,
3664: gen_rtx (MULT, Pmode, index_diff,
3665: gen_rtx (CONST_INT, VOIDmode, 2)),
3666: gen_rtx (LABEL_REF, VOIDmode, operands[3])));
3667: /* Emit the last few insns. */
3668: emit_insn (gen_casesi_2 (gen_reg_rtx (HImode), table_elt_addr, operands[3]));
3669: DONE;
3670: }")
3671:
3672: ;; Recognize one of the insns resulting from casesi_2.
3673: (define_insn ""
3674: [(set (pc)
3675: (plus:SI (pc) (match_operand:HI 0 "general_operand" "r")))
3676: (use (label_ref (match_operand 1 "" "")))]
3677: ""
3678: "*
1.1.1.3 ! root 3679: {
! 3680: #ifdef ASM_RETURN_CASE_JUMP
! 3681: ASM_RETURN_CASE_JUMP;
! 3682: #else
1.1 root 3683: #ifdef SGS
3684: #ifdef ASM_OUTPUT_CASE_LABEL
3685: return \"jmp 6(%%pc,%0.w)\";
3686: #else
3687: return \"jmp 2(%%pc,%0.w)\";
3688: #endif
3689: #else /* not SGS */
3690: #ifdef MOTOROLA
3691: return \"jmp (2,pc,%0.w)\";
3692: #else
3693: return \"jmp pc@(2,%0:w)\";
3694: #endif
3695: #endif
1.1.1.3 ! root 3696: #endif /* no ASM_RETURN_CASE_JUMP */
! 3697: }")
1.1 root 3698:
3699: ;; Unconditional and other jump instructions
3700: (define_insn "jump"
3701: [(set (pc)
3702: (label_ref (match_operand 0 "" "")))]
3703: ""
3704: "*
3705: #ifdef MOTOROLA
3706: return \"jbra %l0\";
3707: #else
3708: return \"jra %l0\";
3709: #endif
3710: ")
3711:
3712: (define_insn ""
3713: [(set (pc)
3714: (if_then_else
3715: (ne (compare (plus:HI (match_operand:HI 0 "general_operand" "g")
3716: (const_int -1))
3717: (const_int -1))
3718: (const_int 0))
3719: (label_ref (match_operand 1 "" ""))
3720: (pc)))
3721: (set (match_dup 0)
3722: (plus:HI (match_dup 0)
3723: (const_int -1)))]
3724: ""
3725: "*
3726: {
3727: CC_STATUS_INIT;
3728: if (DATA_REG_P (operands[0]))
3729: return \"dbra %0,%l1\";
3730: if (GET_CODE (operands[0]) == MEM)
3731: {
3732: #ifdef MOTOROLA
3733: #ifdef NO_ADDSUB_Q
3734: return \"sub%.w %#1,%0\;jbcc %l1\";
3735: #else
3736: return \"subq%.w %#1,%0\;jbcc %l1\";
3737: #endif
3738: #else /* not MOTOROLA */
3739: return \"subqw %#1,%0\;jcc %l1\";
3740: #endif
3741: }
3742: #ifdef MOTOROLA
3743: #ifdef HPUX_ASM
3744: #ifndef NO_ADDSUB_Q
3745: return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
3746: #else
3747: return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
3748: #endif
3749: #else /* not HPUX_ASM */
3750: return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
3751: #endif
3752: #else /* not MOTOROLA */
3753: return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
3754: #endif
3755: }")
3756:
3757: (define_insn ""
3758: [(set (pc)
3759: (if_then_else
3760: (ne (compare (plus:SI (match_operand:SI 0 "general_operand" "g")
3761: (const_int -1))
3762: (const_int -1))
3763: (const_int 0))
3764: (label_ref (match_operand 1 "" ""))
3765: (pc)))
3766: (set (match_dup 0)
3767: (plus:SI (match_dup 0)
3768: (const_int -1)))]
3769: ""
3770: "*
3771: {
3772: CC_STATUS_INIT;
3773: #ifdef MOTOROLA
3774: #ifndef NO_ADDSUB_Q
3775: if (DATA_REG_P (operands[0]))
3776: return \"dbra %0,%l1\;clr.w %0\;sub.l %#1,%0\;jbcc %l1\";
3777: if (GET_CODE (operands[0]) == MEM)
3778: return \"sub.l %#1,%0\;jbcc %l1\";
3779: #else
3780: if (DATA_REG_P (operands[0]))
3781: return \"dbra %0,%l1\;clr.w %0\;subq.l %#1,%0\;jbcc %l1\";
3782: if (GET_CODE (operands[0]) == MEM)
3783: return \"subq.l %#1,%0\;jbcc %l1\";
3784: #endif /* not NO_ADDSUB_Q */
3785: #ifdef HPUX_ASM
3786: #ifndef NO_ADDSUB_Q
3787: return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
3788: #else
3789: return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
3790: #endif
3791: #else
3792: return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
3793: #endif
3794: #else
3795: if (DATA_REG_P (operands[0]))
3796: return \"dbra %0,%l1\;clrw %0\;subql %#1,%0\;jcc %l1\";
3797: if (GET_CODE (operands[0]) == MEM)
3798: return \"subql %#1,%0\;jcc %l1\";
3799: return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
3800: #endif
3801: }")
3802:
3803: ;; dbra patterns that use REG_NOTES info generated by strength_reduce.
3804:
3805: (define_insn ""
3806: [(set (pc)
3807: (if_then_else
3808: (ge (plus:SI (match_operand:SI 0 "general_operand" "g")
3809: (const_int -1))
3810: (const_int 0))
3811: (label_ref (match_operand 1 "" ""))
3812: (pc)))
3813: (set (match_dup 0)
3814: (plus:SI (match_dup 0)
3815: (const_int -1)))]
3816: "find_reg_note (insn, REG_NONNEG, 0)"
3817: "*
3818: {
3819: CC_STATUS_INIT;
3820: #ifdef MOTOROLA
3821: #ifndef NO_ADDSUB_Q
3822: if (DATA_REG_P (operands[0]))
3823: return \"dbra %0,%l1\;clr.w %0\;sub.l %#1,%0\;jbcc %l1\";
3824: if (GET_CODE (operands[0]) == MEM)
3825: return \"sub.l %#1,%0\;jbcc %l1\";
3826: #else
3827: if (DATA_REG_P (operands[0]))
3828: return \"dbra %0,%l1\;clr.w %0\;subq.l %#1,%0\;jbcc %l1\";
3829: if (GET_CODE (operands[0]) == MEM)
3830: return \"subq.l %#1,%0\;jbcc %l1\";
3831: #endif
3832: #ifdef HPUX_ASM
3833: #ifndef NO_ADDSUB_Q
3834: return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
3835: #else
3836: return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
3837: #endif
3838: #else
3839: return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
3840: #endif
3841: #else
3842: if (DATA_REG_P (operands[0]))
3843: return \"dbra %0,%l1\;clrw %0\;subql %#1,%0\;jcc %l1\";
3844: if (GET_CODE (operands[0]) == MEM)
3845: return \"subql %#1,%0\;jcc %l1\";
3846: return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
3847: #endif
3848: }")
3849:
3850: ;; Call subroutine with no return value.
3851: (define_insn "call"
3852: [(call (match_operand:QI 0 "general_operand" "o")
3853: (match_operand:SI 1 "general_operand" "g"))]
3854: ;; Operand 1 not really used on the m68000.
3855:
3856: ""
3857: "*
3858: #ifdef MOTOROLA
3859: return \"jsr %0\";
3860: #else
3861: return \"jbsr %0\";
3862: #endif
3863: ")
3864:
3865: ;; Call subroutine, returning value in operand 0
3866: ;; (which must be a hard register).
3867: (define_insn "call_value"
3868: [(set (match_operand 0 "" "=rf")
3869: (call (match_operand:QI 1 "general_operand" "o")
3870: (match_operand:SI 2 "general_operand" "g")))]
3871: ;; Operand 2 not really used on the m68000.
3872: ""
3873: "*
3874: #ifdef MOTOROLA
3875: return \"jsr %1\";
3876: #else
3877: return \"jbsr %1\";
3878: #endif
3879: ")
3880:
3881: (define_insn "nop"
3882: [(const_int 0)]
3883: ""
3884: "nop")
3885:
3886: ;; This should not be used unless the add/sub insns can't be.
3887:
3888: (define_insn ""
3889: [(set (match_operand:SI 0 "general_operand" "=a")
3890: (match_operand:QI 1 "address_operand" "p"))]
3891: ""
3892: "lea %a1,%0")
3893:
3894: ;; This is the first machine-dependent peephole optimization.
3895: ;; It is useful when a floating value is returned from a function call
3896: ;; and then is moved into an FP register.
3897: ;; But it is mainly intended to test the support for these optimizations.
3898:
3899: (define_peephole
3900: [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
3901: (set (match_operand:DF 0 "register_operand" "f")
3902: (match_operand:DF 1 "register_operand" "ad"))]
3903: "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
3904: "*
3905: {
3906: rtx xoperands[2];
3907: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
3908: output_asm_insn (\"move%.l %1,%@\", xoperands);
3909: output_asm_insn (\"move%.l %1,%-\", operands);
3910: return \"fmove%.d %+,%0\";
3911: }
3912: ")
3913:
3914: ;; FPA multiply and add.
3915: (define_insn ""
3916: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
3917: (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
3918: (match_operand:DF 2 "general_operand" "xH,y,y"))
3919: (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
3920: "TARGET_FPA"
3921: "*
3922: {
3923: if (which_alternative == 0)
3924: return \"fpma%.d %1,%w2,%w3,%0\";
3925: return \"fpma%.d %x1,%x2,%x3,%0\";
3926: }")
3927:
3928: (define_insn ""
3929: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
3930: (plus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
3931: (mult:DF (match_operand:DF 2 "general_operand" "%x,dmF,y")
3932: (match_operand:DF 3 "general_operand" "xH,y,y"))))]
3933: "TARGET_FPA"
3934: "*
3935: {
3936: if (which_alternative == 0)
3937: return \"fpma%.d %2,%w3,%w1,%0\";
3938: return \"fpma%.d %x2,%x3,%x1,%0\";
3939: }")
3940:
3941: (define_insn ""
3942: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
3943: (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
3944: (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
3945: (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
3946: "TARGET_FPA"
3947: "*
3948: {
3949: if (which_alternative == 0)
3950: return \"fpma%.s %1,%w2,%w3,%0\";
3951: return \"fpma%.s %1,%2,%3,%0\";
3952: }")
3953:
3954: (define_insn ""
3955: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
3956: (plus:SF (match_operand:SF 1 "general_operand" "xH,ydmF,ydmF")
3957: (mult:SF (match_operand:SF 2 "general_operand" "%x,ydmF,y")
3958: (match_operand:SF 3 "general_operand" "xH,y,ydmF"))))]
3959: "TARGET_FPA"
3960: "*
3961: {
3962: if (which_alternative == 0)
3963: return \"fpma%.s %2,%w3,%w1,%0\";
3964: return \"fpma%.s %2,%3,%1,%0\";
3965: }")
3966:
3967: ;; FPA Multiply and subtract
3968: (define_insn ""
3969: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
3970: (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
3971: (mult:DF (match_operand:DF 2 "register_operand" "%xH,y,y")
3972: (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
3973: "TARGET_FPA"
3974: "*
3975: {
3976: if (which_alternative == 0)
3977: return \"fpms%.d %3,%w2,%w1,%0\";
3978: return \"fpms%.d %x3,%2,%x1,%0\";
3979: }")
3980:
3981: (define_insn ""
3982: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
3983: (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
3984: (mult:SF (match_operand:SF 2 "register_operand" "%xH,rmF,y")
3985: (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
3986: "TARGET_FPA"
3987: "*
3988: {
3989: if (which_alternative == 0)
3990: return \"fpms%.s %3,%w2,%w1,%0\";
3991: return \"fpms%.s %3,%2,%1,%0\";
3992: }")
3993:
3994: (define_insn ""
3995: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
3996: (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "%xH,y,y")
3997: (match_operand:DF 2 "general_operand" "x,y,rmF"))
3998: (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
3999: "TARGET_FPA"
4000: "*
4001: {
4002: if (which_alternative == 0)
4003: return \"fpmr%.d %2,%w1,%w3,%0\";
4004: return \"fpmr%.d %x2,%1,%x3,%0\";
4005: }")
4006:
4007: (define_insn ""
4008: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
4009: (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "%xH,rmF,y")
4010: (match_operand:SF 2 "general_operand" "x,y,yrmF"))
4011: (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
4012: "TARGET_FPA"
4013: "*
4014: {
4015: if (which_alternative == 0)
4016: return \"fpmr%.s %2,%w1,%w3,%0\";
4017: return \"fpmr%.s %x2,%1,%x3,%0\";
4018: }")
4019:
4020: ;; FPA Add and multiply
4021: (define_insn ""
4022: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
4023: (mult:DF (plus:DF (match_operand:DF 1 "register_operand" "%xH,y,y")
4024: (match_operand:DF 2 "general_operand" "x,y,rmF"))
4025: (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
4026: "TARGET_FPA"
4027: "*
4028: {
4029: if (which_alternative == 0)
4030: return \"fpam%.d %2,%w1,%w3,%0\";
4031: return \"fpam%.d %x2,%1,%x3,%0\";
4032: }")
4033:
4034: (define_insn ""
4035: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
4036: (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
4037: (plus:DF (match_operand:DF 2 "register_operand" "%xH,y,y")
4038: (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
4039: "TARGET_FPA"
4040: "*
4041: {
4042: if (which_alternative == 0)
4043: return \"fpam%.d %3,%w2,%w1,%0\";
4044: return \"fpam%.d %x3,%2,%x1,%0\";
4045: }")
4046:
4047: (define_insn ""
4048: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
4049: (mult:SF (plus:SF (match_operand:SF 1 "register_operand" "%xH,rmF,y")
4050: (match_operand:SF 2 "general_operand" "x,y,yrmF"))
4051: (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
4052: "TARGET_FPA"
4053: "*
4054: {
4055: if (which_alternative == 0)
4056: return \"fpam%.s %2,%w1,%w3,%0\";
4057: return \"fpam%.s %x2,%1,%x3,%0\";
4058: }")
4059:
4060: (define_insn ""
4061: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
4062: (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
4063: (plus:SF (match_operand:SF 2 "register_operand" "%xH,rmF,y")
4064: (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
4065: "TARGET_FPA"
4066: "*
4067: {
4068: if (which_alternative == 0)
4069: return \"fpam%.s %3,%w2,%w1,%0\";
4070: return \"fpam%.s %x3,%2,%x1,%0\";
4071: }")
4072:
4073: ;;FPA Subtract and multiply
4074: (define_insn ""
4075: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
4076: (mult:DF (minus:DF (match_operand:DF 1 "register_operand" "xH,y,y")
4077: (match_operand:DF 2 "general_operand" "x,y,rmF"))
4078: (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
4079: "TARGET_FPA"
4080: "*
4081: {
4082: if (which_alternative == 0)
4083: return \"fpsm%.d %2,%w1,%w3,%0\";
4084: return \"fpsm%.d %x2,%1,%x3,%0\";
4085: }")
4086:
4087: (define_insn ""
4088: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
4089: (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
4090: (minus:DF (match_operand:DF 2 "register_operand" "xH,y,y")
4091: (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
4092: "TARGET_FPA"
4093: "*
4094: {
4095: if (which_alternative == 0)
4096: return \"fpsm%.d %3,%w2,%w1,%0\";
4097: return \"fpsm%.d %x3,%2,%x1,%0\";
4098: }")
4099:
4100: (define_insn ""
4101: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
4102: (mult:SF (minus:SF (match_operand:SF 1 "register_operand" "xH,rmF,y")
4103: (match_operand:SF 2 "general_operand" "x,y,yrmF"))
4104: (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
4105: "TARGET_FPA"
4106: "*
4107: {
4108: if (which_alternative == 0)
4109: return \"fpsm%.s %2,%w1,%w3,%0\";
4110: return \"fpsm%.s %x2,%1,%x3,%0\";
4111: }")
4112:
4113: (define_insn ""
4114: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
4115: (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
4116: (minus:SF (match_operand:SF 2 "register_operand" "xH,rmF,y")
4117: (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
4118: "TARGET_FPA"
4119: "*
4120: {
4121: if (which_alternative == 0)
4122: return \"fpsm%.s %3,%w2,%w1,%0\";
4123: return \"fpsm%.s %x3,%2,%x1,%0\";
4124: }")
4125:
4126:
4127: ;;- Local variables:
4128: ;;- mode:emacs-lisp
4129: ;;- comment-start: ";;- "
4130: ;;- comment-start-skip: ";+- *"
4131: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
4132: ;;- eval: (modify-syntax-entry ?[ "(]")
4133: ;;- eval: (modify-syntax-entry ?] ")[")
4134: ;;- eval: (modify-syntax-entry ?{ "(}")
4135: ;;- eval: (modify-syntax-entry ?} "){")
4136: ;;- End:
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