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1.1 root 1: ;;- Machine description for GNU compiler
2: ;;- Motorola 68000 Version
3: ;; Copyright (C) 1987, 1988 Free Software Foundation, Inc.
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 1, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21:
22: ;;- instruction definitions
23:
24: ;;- @@The original PO technology requires these to be ordered by speed,
25: ;;- @@ so that assigner will pick the fastest.
26:
27: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
28:
29: ;;- When naming insn's (operand 0 of define_insn) be careful about using
30: ;;- names from other targets machine descriptions.
31:
32: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
33: ;;- updates for most instructions.
34:
35: ;;- Operand classes for the register allocator:
36: ;;- 'a' one of the address registers can be used.
37: ;;- 'd' one of the data registers can be used.
38: ;;- 'f' one of the m68881 registers can be used
39: ;;- 'r' either a data or an address register can be used.
40: ;;- 'x' if one of the Sun FPA registers
41: ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
42:
43: ;;- Immediate Floating point operator constraints
44: ;;- 'G' a floating point constant that is *NOT* one of the standard
45: ;; 68881 constant values (to force calling output_move_const_double
46: ;; to get it from rom if it is a 68881 constant).
47: ;;- 'H' one of the standard FPA constant values
48: ;;
49: ;; See the functions standard_XXX_constant_p in output-m68k.c for more
50: ;; info.
51:
52: ;;- Immediate integer operand constraints:
53: ;;- 'I' 1 .. 8
54: ;;- 'J' -32768 .. 32767
55: ;;- 'K' -128 .. 127
56: ;;- 'L' -8 .. -1
57:
58: ;;- FPA port explanation:
59:
60: ;;- Usage of the Sun FPA and the 68881 together
61:
62: ;;- The current port of gcc to the sun fpa disallows use of the m68881
63: ;;- instructions completely if code is targetted for the fpa. This is
64: ;;- for the following reasons:
65:
66: ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
67: ;;- can, the 68881 otherwise, and data registers only if you are
68: ;;- forced to it) is a bitch with the current constraint scheme,
69: ;;- especially since it would have to work for any combination of
70: ;;- -mfpa, -m68881.
71:
72: ;;- 2) There are no instructions to move between the two types of
73: ;;- registers; the stack must be used as an intermediary.
74:
75: ;;- It could indeed be done; I think the best way would be to have
76: ;;- seperate patterns for TARGET_FPA (which implies a 68881),
77: ;;- TARGET_68881, and no floating point co-processor. Use
78: ;;- define_expands for all of the named instruction patterns, and
79: ;;- include code in the FPA instruction to deal with the 68881 with
80: ;;- preferences specifically set to favor the fpa. Some of this has
81: ;;- already been done:
82: ;;-
83: ;;- 1) Separation of most of the patterns out into a TARGET_FPA
84: ;;- case and a TARGET_68881 case (the exceptions are the patterns
85: ;;- which would need one define_expand and three define_insn's under
86: ;;- it (with alot of duplicate code between them) to replace the
87: ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
88: ;;- first two patterns in the md.
89: ;;-
90: ;;- Some would still have to be done:
91: ;;-
92: ;;- 1) Add code to the fpa patterns which correspond to 68881
93: ;;- patterns to deal with the 68881 case (including preferences!).
94: ;;- What you might actually do here is combine the fpa and 68881 code
95: ;;- back together into one pattern for those instructions where it's
96: ;;- absolutely necessary and save yourself some duplicate code. I'm
97: ;;- not completely sure as to whether you could get away with doing
98: ;;- this only for the mov* insns, or if you'd have to do it for all
99: ;;- named insns.
100: ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
101: ;;- moving between fpa regs and 68881 regs.
102:
103: ;;- Since the fpa is more powerful than the 68881 and also has more
104: ;;- registers, and since I think the reultant md would be medium ugly
105: ;;- (lot's of duplicate code, ugly constraint strings), I elected not
106: ;;- to do this change.
107:
108: ;;- Another reason why someone *might* want to do the change is to
109: ;;- control which register classes are accessed in a slightly cleaner
110: ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
111: ;;- the internals manual.
112:
113: ;;- Yet another reason why someone might want to do this change is to
114: ;;- allow use of some of the 68881 insns which have no equivalent on
115: ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
116:
117: ;;- If this is ever done, don't forget to change tm-sun3.h so that
118: ;;- it *will* define __HAVE_68881__ when the FPA is in use.
119:
120: ;;- Condition code hack
121:
122: ;;- When a floating point compare is done in the fpa, the resulting
123: ;;- condition codes are left in the fpastatus register. The values in
124: ;;- this register must be moved into the 68000 cc register before any
125: ;;- jump is executed. Once this has been done, regular jump
126: ;;- instructions are fine (ie. floating point jumps are not necessary.
127: ;;- They are only done if the cc is in the 68881).
128:
129: ;;- The instructions that move the fpastatus register to the 68000
130: ;;- register clobber a data register (the move cannot be done direct).
131: ;;- These instructions might be bundled either with the compare
132: ;;- instruction, or the branch instruction. If we were using both the
133: ;;- fpa and the 68881 together, we would wish to only mark the
134: ;;- register clobbered if we were doing the compare in the fpa, but I
135: ;;- think that that decision (whether to clobber the register or not)
136: ;;- must be done before register allocation (makes sense) and hence we
137: ;;- can't know if the floating point compare will be done in the fpa
138: ;;- or the fp. So whenever we are asked for code that uses the fpa,
139: ;;- we will mark a data register as clobbered. This is reasonable, as
140: ;;- almost all floating point compare operations done with fpa code
141: ;;- enabled will be done in the fpa. It's even more reasonable since
142: ;;- we decided to make the 68881 and the fpa mutually exclusive.
143:
144: ;;- We place to code to move the fpastatus register inside of a
145: ;;- define_expand so that we can do it conditionally based on whether
146: ;;- we are tagetting an fpa or not.
147:
148: ;;- This still leaves us with the question of where we wish to put the
149: ;;- code to move the fpastatus reg. If we put it in the compare
150: ;;- instruction, we can restrict the clobbering of the register to
151: ;;- floating point compares, but we can't take advantage of floating
152: ;;- point subtracts & etc. that alter the fpastatus register. If we
153: ;;- put it in the branch instruction, all branches compiled with fpa
154: ;;- code enabled will clobber a data register, but we will be able to
155: ;;- take advantage of fpa subtracts. This balance favors putting the
156: ;;- code in with the compare instruction.
157:
158: ;;- Note that if some enterprising hacker should decide to switch
159: ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
160:
161: ;;- Usage of the top 16 fpa registers
162:
163: ;;- The only locations which we may transfer fpa registers 16-31 from
164: ;;- or to are the fpa registers 0-15. (68000 registers and memory
165: ;;- locations are impossible). This causes problems in gcc, which
166: ;;- assumes that mov?? instructions require no additional registers
167: ;;- (see section 11.7) and since floating point moves *must* be
168: ;;- supported into general registers (see section 12.3 under
169: ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
170:
171: ;;- My solution was to reserve fpa0 for moves into or out of these top
172: ;;- 16 registers and to disparage the choice to reload into or out of
173: ;;- these registers as much as I could. That alternative is always
174: ;;- last in the list, so it will not be used unless all else fails. I
175: ;;- will note that according to my current information, sun's compiler
176: ;;- doesn't use these top 16 registers at all.
177:
178: ;;- There is another possible way to do it. I *believe* that if you
179: ;;- make absolutely sure that the code will not be exectued in the
180: ;;- reload pass, you can support the mov?? names with define_expands
181: ;;- which require new registers. This may be possible by the
182: ;;- appropriate juggling of constraints. I may come back to this later.
183:
184: ;;- Usage of constant RAM
185:
186: ;;- This has been handled correctly (I believe) but the way I've done
187: ;;- it could use a little explanation. The constant RAM can only be
188: ;;- accessed when the instruction is in "command register" mode.
189: ;;- "command register" mode means that no accessing of memory or the
190: ;;- 68000 registers is being done. This can be expressed easily in
191: ;;- constraints, so generally the mode of the instruction is
192: ;;- determined by a branch off of which_alternative. In outputing
193: ;;- instructions, a 'w' means to output an access to the constant ram
194: ;;- (if the arg is CONST_DOUBLE and is one of the available
195: ;;- constants), and 'x' means to output a register pair (if the arg is
196: ;;- a 68000 register) and a 'y' is the combination of the above two
197: ;;- processies. You use a 'y' in two operand DF instructions where you
198: ;;- *know* the other operand is an fpa register, you use an 'x' in DF
199: ;;- instructions where the arg might be a 68000 register and the
200: ;;- instruction is *not* in "command register" mode, and you use a 'w'
201: ;;- in two situations: 1) The instruction *is* in command register
202: ;;- mode (and hence won't be accessing 68000 registers), or 2) The
203: ;;- instruction is a two operand SF instruction where you know the
204: ;;- other operand is an fpa register.
205:
206: ;;- Optimization issues
207:
208: ;;- I actually think that I've included all of the fpa instructions
209: ;;- that should be included. Note that if someone is interested in
210: ;;- doing serious floating point work on the sun fpa, I would advise
211: ;;- the use of the "asm" instruction in gcc to allow you to use the
212: ;;- sin, cos, and exponential functions on the fpa board.
213:
214: ;;- END FPA Explanation Section.
215:
216:
217: ;;- Some of these insn's are composites of several m68000 op codes.
218: ;;- The assembler (or final @@??) insures that the appropriate one is
219: ;;- selected.
220:
221: (define_insn ""
222: [(set (match_operand:DF 0 "push_operand" "=m")
223: (match_operand:DF 1 "general_operand" "ro<>fyF"))]
224: ""
225: "*
226: {
227: if (FP_REG_P (operands[1]))
228: return \"fmove%.d %f1,%0\";
229: if (FPA_REG_P (operands[1]))
230: return \"fpmove%.d %1, %x0\";
231: return output_move_double (operands);
232: }")
233:
234: (define_insn ""
235: [(set (match_operand:DI 0 "push_operand" "=m")
236: (match_operand:DI 1 "general_operand" "ro<>Fy"))]
237: ""
238: "*
239: {
240: return output_move_double (operands);
241: }")
242:
243: ;; Put tstsi first among test insns so it matches a CONST_INT operand.
244:
245: (define_insn "tstsi"
246: [(set (cc0)
247: (match_operand:SI 0 "general_operand" "rm"))]
248: ""
249: "*
250: {
251: #ifdef ISI_OV
252: /* ISI's assembler fails to handle tstl a0. */
253: if (! ADDRESS_REG_P (operands[0]))
254: #else
255: if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
256: #endif
257: return \"tst%.l %0\";
258: /* If you think that the 68020 does not support tstl a0,
259: reread page B-167 of the 68020 manual more carefully. */
260: /* On an address reg, cmpw may replace cmpl. */
261: #ifdef HPUX_ASM
262: return \"cmp%.w %0,%#0\";
263: #else
264: return \"cmp%.w %#0,%0\";
265: #endif
266: }")
267:
268: (define_insn "tsthi"
269: [(set (cc0)
270: (match_operand:HI 0 "general_operand" "rm"))]
271: ""
272: "*
273: {
274: #ifdef ISI_OV
275: if (! ADDRESS_REG_P (operands[0]))
276: #else
277: if (TARGET_68020 || ! ADDRESS_REG_P (operands[0]))
278: #endif
279: return \"tst%.w %0\";
280: #ifdef HPUX_ASM
281: return \"cmp%.w %0,%#0\";
282: #else
283: return \"cmp%.w %#0,%0\";
284: #endif
285: }")
286:
287: (define_insn "tstqi"
288: [(set (cc0)
289: (match_operand:QI 0 "general_operand" "dm"))]
290: ""
291: "tst%.b %0")
292:
293: (define_expand "tstsf"
294: [(set (cc0)
295: (match_operand:SF 0 "general_operand" ""))]
296: "TARGET_68881 || TARGET_FPA"
297: "
298: {
299: if (TARGET_FPA)
300: {
301: emit_insn (gen_rtx (PARALLEL, VOIDmode,
302: gen_rtvec (2,
303: gen_rtx (SET, VOIDmode,
304: cc0_rtx, operands[0]),
305: gen_rtx (CLOBBER, VOIDmode,
306: gen_reg_rtx (SImode)))));
307: DONE;
308: }
309: }")
310:
311: (define_insn ""
312: [(set (cc0)
313: (match_operand:SF 0 "general_operand" "xmdF"))
314: (clobber (match_operand:SI 1 "general_operand" "d"))]
315: "TARGET_FPA"
316: "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
317:
318: (define_insn ""
319: [(set (cc0)
320: (match_operand:SF 0 "general_operand" "fdm"))]
321: "TARGET_68881"
322: "*
323: {
324: cc_status.flags = CC_IN_68881;
325: if (FP_REG_P (operands[0]))
326: return \"ftst%.x %0\";
327: return \"ftst%.s %0\";
328: }")
329:
330: (define_expand "tstdf"
331: [(set (cc0)
332: (match_operand:DF 0 "general_operand" ""))]
333: "TARGET_68881 || TARGET_FPA"
334: "
335: {
336: if (TARGET_FPA)
337: {
338: emit_insn (gen_rtx (PARALLEL, VOIDmode,
339: gen_rtvec (2, gen_rtx (SET, VOIDmode,
340: cc0_rtx, operands[0]),
341: gen_rtx (CLOBBER, VOIDmode,
342: gen_reg_rtx (SImode)))));
343: DONE;
344: }
345: }")
346:
347: (define_insn ""
348: [(set (cc0)
349: (match_operand:DF 0 "general_operand" "xrmF"))
350: (clobber (match_operand:SI 1 "general_operand" "d"))]
351: "TARGET_FPA"
352: "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
353:
354: (define_insn ""
355: [(set (cc0)
356: (match_operand:DF 0 "general_operand" "fm"))]
357: "TARGET_68881"
358: "*
359: {
360: cc_status.flags = CC_IN_68881;
361: if (FP_REG_P (operands[0]))
362: return \"ftst%.x %0\";
363: return \"ftst%.d %0\";
364: }")
365:
366: ;; compare instructions.
367:
368: ;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
369:
370: ;; A composite of the cmp, cmpa, & cmpi m68000 op codes.
371: (define_insn "cmpsi"
372: [(set (cc0)
373: (compare (match_operand:SI 0 "general_operand" "rKs,mr,>")
374: (match_operand:SI 1 "general_operand" "mr,Ksr,>")))]
375: ""
376: "*
377: {
378: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
379: return \"cmpm%.l %1,%0\";
380: if (REG_P (operands[1])
381: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
382: { cc_status.flags |= CC_REVERSED;
383: #ifdef HPUX_ASM
384: return \"cmp%.l %d1,%d0\";
385: #else
386: return \"cmp%.l %d0,%d1\";
387: #endif
388: }
389: #ifdef HPUX_ASM
390: return \"cmp%.l %d0,%d1\";
391: #else
392: return \"cmp%.l %d1,%d0\";
393: #endif
394: }")
395:
396: (define_insn "cmphi"
397: [(set (cc0)
398: (compare (match_operand:HI 0 "general_operand" "rnm,d,n,m")
399: (match_operand:HI 1 "general_operand" "d,rnm,m,n")))]
400: ""
401: "*
402: {
403: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
404: return \"cmpm%.w %1,%0\";
405: if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
406: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
407: { cc_status.flags |= CC_REVERSED;
408: #ifdef HPUX_ASM
409: return \"cmp%.w %d1,%d0\";
410: #else
411: return \"cmp%.w %d0,%d1\";
412: #endif
413: }
414: #ifdef HPUX_ASM
415: return \"cmp%.w %d0,%d1\";
416: #else
417: return \"cmp%.w %d1,%d0\";
418: #endif
419: }")
420:
421: (define_insn "cmpqi"
422: [(set (cc0)
423: (compare (match_operand:QI 0 "general_operand" "dn,md,>")
424: (match_operand:QI 1 "general_operand" "dm,nd,>")))]
425: ""
426: "*
427: {
428: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
429: return \"cmpm%.b %1,%0\";
430: if (REG_P (operands[1])
431: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
432: { cc_status.flags |= CC_REVERSED;
433: #ifdef HPUX_ASM
434: return \"cmp%.b %d1,%d0\";
435: #else
436: return \"cmp%.b %d0,%d1\";
437: #endif
438: }
439: #ifdef HPUX_ASM
440: return \"cmp%.b %d0,%d1\";
441: #else
442: return \"cmp%.b %d1,%d0\";
443: #endif
444: }")
445:
446: (define_expand "cmpdf"
447: [(set (cc0)
448: (compare (match_operand:DF 0 "general_operand" "")
449: (match_operand:DF 1 "general_operand" "")))]
450: "TARGET_68881 || TARGET_FPA"
451: "
452: {
453: if (TARGET_FPA)
454: {
455: rtx set = gen_rtx (SET, VOIDmode, cc0_rtx,
456: gen_rtx (COMPARE, VOIDmode, operands[0], operands[1]));
457: emit_insn (gen_rtx (PARALLEL, VOIDmode,
458: gen_rtvec (2, set,
459: gen_rtx (CLOBBER, VOIDmode,
460: gen_reg_rtx (SImode)))));
461: DONE;
462: }
463: }")
464:
465: (define_insn ""
466: [(set (cc0)
467: (compare (match_operand:DF 0 "general_operand" "x,y")
468: (match_operand:DF 1 "general_operand" "xH,rmF")))
469: (clobber (match_operand:SI 2 "general_operand" "d,d"))]
470: "TARGET_FPA"
471: "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
472:
473: (define_insn ""
474: [(set (cc0)
475: (compare (match_operand:DF 0 "general_operand" "f,mG")
476: (match_operand:DF 1 "general_operand" "fmG,f")))]
477: "TARGET_68881"
478: "*
479: {
480: cc_status.flags = CC_IN_68881;
481: #ifdef HPUX_ASM
482: if (REG_P (operands[0]))
483: {
484: if (REG_P (operands[1]))
485: return \"fcmp%.x %0,%1\";
486: else
487: return \"fcmp%.d %0,%f1\";
488: }
489: cc_status.flags |= CC_REVERSED;
490: return \"fcmp%.d %1,%f0\";
491: #else
492: if (REG_P (operands[0]))
493: {
494: if (REG_P (operands[1]))
495: return \"fcmp%.x %1,%0\";
496: else
497: return \"fcmp%.d %f1,%0\";
498: }
499: cc_status.flags |= CC_REVERSED;
500: return \"fcmp%.d %f0,%1\";
501: #endif
502: }")
503:
504: (define_expand "cmpsf"
505: [(set (cc0)
506: (compare (match_operand:SF 0 "general_operand" "")
507: (match_operand:SF 1 "general_operand" "")))]
508: "TARGET_68881 || TARGET_FPA"
509: "
510: {
511: if (TARGET_FPA)
512: {
513: rtx set = gen_rtx (SET, VOIDmode, cc0_rtx,
514: gen_rtx (COMPARE, VOIDmode, operands[0], operands[1]));
515: emit_insn (gen_rtx (PARALLEL, VOIDmode,
516: gen_rtvec (2, set,
517: gen_rtx (CLOBBER, VOIDmode,
518: gen_reg_rtx(SImode)))));
519: DONE;
520: }
521: }")
522:
523: (define_insn ""
524: [(set (cc0)
525: (compare (match_operand:SF 0 "general_operand" "x,y")
526: (match_operand:SF 1 "general_operand" "xH,rmF")))
527: (clobber (match_operand:SI 2 "general_operand" "d,d"))]
528: "TARGET_FPA"
529: "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
530:
531: (define_insn ""
532: [(set (cc0)
533: (compare (match_operand:SF 0 "general_operand" "f,mdG")
534: (match_operand:SF 1 "general_operand" "fmdG,f")))]
535: "TARGET_68881"
536: "*
537: {
538: cc_status.flags = CC_IN_68881;
539: #ifdef HPUX_ASM
540: if (FP_REG_P (operands[0]))
541: {
542: if (FP_REG_P (operands[1]))
543: return \"fcmp%.x %0,%1\";
544: else
545: return \"fcmp%.s %0,%f1\";
546: }
547: cc_status.flags |= CC_REVERSED;
548: return \"fcmp%.s %1,%f0\";
549: #else
550: if (FP_REG_P (operands[0]))
551: {
552: if (FP_REG_P (operands[1]))
553: return \"fcmp%.x %1,%0\";
554: else
555: return \"fcmp%.s %f1,%0\";
556: }
557: cc_status.flags |= CC_REVERSED;
558: return \"fcmp%.s %f0,%1\";
559: #endif
560: }")
561:
562: ;; Recognizers for btst instructions.
563:
564: (define_insn ""
565: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
566: (const_int 1)
567: (minus:SI (const_int 7)
568: (match_operand:SI 1 "general_operand" "di"))))]
569: ""
570: "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
571:
572: (define_insn ""
573: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
574: (const_int 1)
575: (minus:SI (const_int 31)
576: (match_operand:SI 1 "general_operand" "di"))))]
577: ""
578: "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
579:
580: ;; The following two patterns are like the previous two
581: ;; except that they use the fact that bit-number operands
582: ;; are automatically masked to 3 or 5 bits.
583:
584: (define_insn ""
585: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do")
586: (const_int 1)
587: (minus:SI (const_int 7)
588: (and:SI
589: (match_operand:SI 1 "general_operand" "d")
590: (const_int 7)))))]
591: ""
592: "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
593:
594: (define_insn ""
595: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d")
596: (const_int 1)
597: (minus:SI (const_int 31)
598: (and:SI
599: (match_operand:SI 1 "general_operand" "d")
600: (const_int 31)))))]
601: ""
602: "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
603:
604: ;; Nonoffsettable mem refs are ok in this one pattern
605: ;; since we don't try to adjust them.
606: (define_insn ""
607: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md")
608: (const_int 1)
609: (match_operand:SI 1 "general_operand" "i")))]
610: "GET_CODE (operands[1]) == CONST_INT
611: && (unsigned) INTVAL (operands[1]) < 8"
612: "*
613: {
614: operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
615: return output_btst (operands, operands[1], operands[0], insn, 7);
616: }")
617:
618: (define_insn ""
619: ;; The constraint "o,d" here means that a nonoffsettable memref
620: ;; will match the first alternative, and its address will be reloaded.
621: ;; Copying the memory contents into a reg would be incorrect if the
622: ;; bit position is over 7.
623: [(set (cc0) (zero_extract (match_operand:HI 0 "nonimmediate_operand" "o,d")
624: (const_int 1)
625: (match_operand:SI 1 "general_operand" "i,i")))]
626: "GET_CODE (operands[1]) == CONST_INT"
627: "*
628: {
629: if (GET_CODE (operands[0]) == MEM)
630: {
631: operands[0] = adj_offsettable_operand (operands[0],
632: INTVAL (operands[1]) / 8);
633: operands[1] = gen_rtx (CONST_INT, VOIDmode,
634: 7 - INTVAL (operands[1]) % 8);
635: return output_btst (operands, operands[1], operands[0], insn, 7);
636: }
637: operands[1] = gen_rtx (CONST_INT, VOIDmode,
638: 15 - INTVAL (operands[1]));
639: return output_btst (operands, operands[1], operands[0], insn, 15);
640: }")
641:
642: (define_insn ""
643: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do")
644: (const_int 1)
645: (match_operand:SI 1 "general_operand" "i")))]
646: "GET_CODE (operands[1]) == CONST_INT"
647: "*
648: {
649: if (GET_CODE (operands[0]) == MEM)
650: {
651: operands[0] = adj_offsettable_operand (operands[0],
652: INTVAL (operands[1]) / 8);
653: operands[1] = gen_rtx (CONST_INT, VOIDmode,
654: 7 - INTVAL (operands[1]) % 8);
655: return output_btst (operands, operands[1], operands[0], insn, 7);
656: }
657: operands[1] = gen_rtx (CONST_INT, VOIDmode,
658: 31 - INTVAL (operands[1]));
659: return output_btst (operands, operands[1], operands[0], insn, 31);
660: }")
661:
662: (define_insn ""
663: [(set (cc0) (subreg:SI (lshiftrt:QI (match_operand:QI 0 "nonimmediate_operand" "dm")
664: (const_int 7))
665: 0))]
666: ""
667: "*
668: {
669: cc_status.flags = CC_Z_IN_NOT_N | CC_NOT_NEGATIVE;
670: return \"tst%.b %0\";
671: }")
672:
673: (define_insn ""
674: [(set (cc0) (and:SI (sign_extend:SI (sign_extend:HI (match_operand:QI 0 "nonimmediate_operand" "dm")))
675: (match_operand:SI 1 "general_operand" "i")))]
676: "(GET_CODE (operands[1]) == CONST_INT
677: && (unsigned) INTVAL (operands[1]) < 0x100
678: && exact_log2 (INTVAL (operands[1])) >= 0)"
679: "*
680: { register int log = exact_log2 (INTVAL (operands[1]));
681: operands[1] = gen_rtx (CONST_INT, VOIDmode, log);
682: return output_btst (operands, operands[1], operands[0], insn, 7);
683: }")
684:
685: ;; move instructions
686:
687: ;; A special case in which it is not desirable
688: ;; to reload the constant into a data register.
689: (define_insn ""
690: [(set (match_operand:SI 0 "push_operand" "=m")
691: (match_operand:SI 1 "general_operand" "J"))]
692: "GET_CODE (operands[1]) == CONST_INT
693: && INTVAL (operands[1]) >= -0x8000
694: && INTVAL (operands[1]) < 0x8000"
695: "*
696: {
697: if (operands[1] == const0_rtx)
698: return \"clr%.l %0\";
699: return \"pea %a1\";
700: }")
701:
702: ;This is never used.
703: ;(define_insn "swapsi"
704: ; [(set (match_operand:SI 0 "general_operand" "r")
705: ; (match_operand:SI 1 "general_operand" "r"))
706: ; (set (match_dup 1) (match_dup 0))]
707: ; ""
708: ; "exg %1,%0")
709:
710: ;; Special case of fullword move when source is zero.
711: ;; The reason this is special is to avoid loading a zero
712: ;; into a data reg with moveq in order to store it elsewhere.
713:
714: (define_insn ""
715: [(set (match_operand:SI 0 "general_operand" "=g")
716: (const_int 0))]
1.1.1.3 root 717: ;; clr insns on 68000 read before writing.
718: ;; This isn't so on the 68010, but we have no alternative for it.
719: "(TARGET_68020
720: || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
1.1 root 721: "*
722: {
723: if (ADDRESS_REG_P (operands[0]))
724: return \"sub%.l %0,%0\";
725: /* moveq is faster on the 68000. */
726: if (DATA_REG_P (operands[0]) && !TARGET_68020)
727: #ifdef MOTOROLA
728: return \"moveq%.l %#0,%0\";
729: #else
730: return \"moveq %#0,%0\";
731: #endif
732: return \"clr%.l %0\";
733: }")
734:
735: ;; General case of fullword move. The register constraints
736: ;; force integer constants in range for a moveq to be reloaded
737: ;; if they are headed for memory.
738: (define_insn "movsi"
739: ;; Notes: make sure no alternative allows g vs g.
740: ;; We don't allow f-regs since fixed point cannot go in them.
741: ;; We do allow y and x regs since fixed point is allowed in them.
742: [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
743: (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
744: ""
745: "*
746: {
747: if (which_alternative == 3)
748: return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
749: if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
750: return \"fpmove%.l %x1,%x0\";
751: if (GET_CODE (operands[1]) == CONST_INT)
752: {
753: if (operands[1] == const0_rtx
754: && (DATA_REG_P (operands[0])
1.1.1.3 root 755: || GET_CODE (operands[0]) == MEM)
756: /* clr insns on 68000 read before writing.
757: This isn't so on the 68010, but we have no alternative for it. */
758: && (TARGET_68020
759: || !(GET_CODE (operands[0]) == MEM
760: && MEM_VOLATILE_P (operands[0]))))
1.1 root 761: return \"clr%.l %0\";
762: else if (DATA_REG_P (operands[0])
763: && INTVAL (operands[1]) < 128
764: && INTVAL (operands[1]) >= -128)
765: {
766: #ifdef MOTOROLA
767: return \"moveq%.l %1,%0\";
768: #else
769: return \"moveq %1,%0\";
770: #endif
771: }
772: else if (ADDRESS_REG_P (operands[0])
773: && INTVAL (operands[1]) < 0x8000
774: && INTVAL (operands[1]) >= -0x8000)
775: return \"move%.w %1,%0\";
776: else if (push_operand (operands[0], SImode)
777: && INTVAL (operands[1]) < 0x8000
778: && INTVAL (operands[1]) >= -0x8000)
779: return \"pea %a1\";
780: }
781: else if ((GET_CODE (operands[1]) == SYMBOL_REF
782: || GET_CODE (operands[1]) == CONST)
783: && push_operand (operands[0], SImode))
784: return \"pea %a1\";
785: else if ((GET_CODE (operands[1]) == SYMBOL_REF
786: || GET_CODE (operands[1]) == CONST)
787: && ADDRESS_REG_P (operands[0]))
788: return \"lea %a1,%0\";
789: return \"move%.l %1,%0\";
790: }")
791:
792: (define_insn "movhi"
793: [(set (match_operand:HI 0 "general_operand" "=g")
794: (match_operand:HI 1 "general_operand" "g"))]
795: ""
796: "*
797: {
798: if (GET_CODE (operands[1]) == CONST_INT)
799: {
800: if (operands[1] == const0_rtx
801: && (DATA_REG_P (operands[0])
1.1.1.3 root 802: || GET_CODE (operands[0]) == MEM)
803: /* clr insns on 68000 read before writing.
804: This isn't so on the 68010, but we have no alternative for it. */
805: && (TARGET_68020
806: || !(GET_CODE (operands[0]) == MEM
807: && MEM_VOLATILE_P (operands[0]))))
1.1 root 808: return \"clr%.w %0\";
809: else if (DATA_REG_P (operands[0])
810: && INTVAL (operands[1]) < 128
811: && INTVAL (operands[1]) >= -128)
812: {
813: #ifdef MOTOROLA
814: return \"moveq%.l %1,%0\";
815: #else
816: return \"moveq %1,%0\";
817: #endif
818: }
819: else if (INTVAL (operands[1]) < 0x8000
820: && INTVAL (operands[1]) >= -0x8000)
821: return \"move%.w %1,%0\";
822: }
823: else if (CONSTANT_P (operands[1]))
824: return \"move%.l %1,%0\";
825: #ifndef SONY_ASM
826: /* Recognize the insn before a tablejump, one that refers
827: to a table of offsets. Such an insn will need to refer
828: to a label on the insn. So output one. Use the label-number
829: of the table of offsets to generate this label. */
830: if (GET_CODE (operands[1]) == MEM
831: && GET_CODE (XEXP (operands[1], 0)) == PLUS
832: && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
833: || GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF)
834: && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS
835: && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) != PLUS)
836: {
837: rtx labelref;
838: if (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF)
839: labelref = XEXP (XEXP (operands[1], 0), 0);
840: else
841: labelref = XEXP (XEXP (operands[1], 0), 1);
842: #if defined (MOTOROLA) && ! defined (SGS_3B1)
843: #ifdef SGS
844: fprintf (asm_out_file, \"\\tset %s%d,.+2\\n\", \"LI\",
845: CODE_LABEL_NUMBER (XEXP (labelref, 0)));
846: #else /* not SGS */
847: fprintf (asm_out_file, \"\\t.set %s%d,.+2\\n\", \"LI\",
848: CODE_LABEL_NUMBER (XEXP (labelref, 0)));
849: #endif /* not SGS */
850: #else /* SGS_3B1 or not MOTOROLA */
851: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
852: CODE_LABEL_NUMBER (XEXP (labelref, 0)));
853: /* For sake of 3b1, set flag saying we need to define the symbol
854: LD%n (with value L%n-LI%n) at the end of the switch table. */
855: RTX_INTEGRATED_P (next_real_insn (XEXP (labelref, 0))) = 1;
856: #endif /* SGS_3B1 or not MOTOROLA */
857: }
858: #endif /* SONY_ASM */
859: return \"move%.w %1,%0\";
860: }")
861:
862: (define_insn "movstricthi"
863: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
864: (match_operand:HI 1 "general_operand" "rmn"))]
865: ""
866: "*
867: {
868: if (GET_CODE (operands[1]) == CONST_INT)
869: {
870: if (operands[1] == const0_rtx
871: && (DATA_REG_P (operands[0])
1.1.1.3 root 872: || GET_CODE (operands[0]) == MEM)
873: /* clr insns on 68000 read before writing.
874: This isn't so on the 68010, but we have no alternative for it. */
875: && (TARGET_68020
876: || !(GET_CODE (operands[0]) == MEM
877: && MEM_VOLATILE_P (operands[0]))))
1.1 root 878: return \"clr%.w %0\";
879: }
880: return \"move%.w %1,%0\";
881: }")
882:
883: (define_insn "movqi"
884: [(set (match_operand:QI 0 "general_operand" "=d,*a,m,m,?*a")
885: (match_operand:QI 1 "general_operand" "dmi*a,d*a,dmi,?*a,m"))]
886: ""
887: "*
888: {
889: rtx xoperands[4];
890: if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM)
891: {
892: xoperands[1] = operands[1];
893: xoperands[2]
894: = gen_rtx (MEM, QImode,
895: gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
896: xoperands[3] = stack_pointer_rtx;
897: /* Just pushing a byte puts it in the high byte of the halfword. */
898: /* We must put it in the low half, the second byte. */
899: output_asm_insn (\"subq%.w %#2,%3\;move%.b %1,%2\", xoperands);
900: return \"move%.w %+,%0\";
901: }
902: if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM)
903: {
904: xoperands[0] = operands[0];
905: xoperands[1] = operands[1];
906: xoperands[2]
907: = gen_rtx (MEM, QImode,
908: gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx));
909: xoperands[3] = stack_pointer_rtx;
910: output_asm_insn (\"move%.w %1,%-\;move%.b %2,%0\;addq%.w %#2,%3\", xoperands);
911: return \"\";
912: }
1.1.1.3 root 913: /* clr and st insns on 68000 read before writing.
914: This isn't so on the 68010, but we have no alternative for it. */
915: if (TARGET_68020
916: || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))
917: {
918: if (operands[1] == const0_rtx)
919: return \"clr%.b %0\";
920: if (GET_CODE (operands[1]) == CONST_INT
921: && INTVAL (operands[1]) == -1)
922: {
923: CC_STATUS_INIT;
924: return \"st %0\";
925: }
926: }
1.1 root 927: if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1]))
928: return \"move%.l %1,%0\";
929: if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1]))
930: return \"move%.w %1,%0\";
931: return \"move%.b %1,%0\";
932: }")
933:
934: (define_insn "movstrictqi"
935: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
936: (match_operand:QI 1 "general_operand" "dmn"))]
937: ""
938: "*
939: {
1.1.1.3 root 940: if (operands[1] == const0_rtx
941: /* clr insns on 68000 read before writing.
942: This isn't so on the 68010, but we have no alternative for it. */
943: && (TARGET_68020
944: || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1.1 root 945: return \"clr%.b %0\";
946: return \"move%.b %1,%0\";
947: }")
948:
949: (define_insn "movsf"
950: [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
951: (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
952: ; [(set (match_operand:SF 0 "general_operand" "=rmf")
953: ; (match_operand:SF 1 "general_operand" "rmfF"))]
954: ""
955: "*
956: {
957: if (which_alternative >= 4)
958: return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
959: if (FPA_REG_P (operands[0]))
960: {
961: if (FPA_REG_P (operands[1]))
962: return \"fpmove%.s %x1,%x0\";
963: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
964: return output_move_const_single (operands);
965: else if (FP_REG_P (operands[1]))
966: return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
967: return \"fpmove%.s %x1,%x0\";
968: }
969: if (FPA_REG_P (operands[1]))
970: {
971: if (FP_REG_P (operands[0]))
972: return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
973: else
974: return \"fpmove%.s %x1,%x0\";
975: }
976: if (FP_REG_P (operands[0]))
977: {
978: if (FP_REG_P (operands[1]))
979: return \"fmove%.x %1,%0\";
980: else if (ADDRESS_REG_P (operands[1]))
981: return \"move%.l %1,%-\;fmove%.s %+,%0\";
982: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
983: return output_move_const_single (operands);
984: return \"fmove%.s %f1,%0\";
985: }
986: if (FP_REG_P (operands[1]))
987: {
988: if (ADDRESS_REG_P (operands[0]))
989: return \"fmove%.s %1,%-\;move%.l %+,%0\";
990: return \"fmove%.s %f1,%0\";
991: }
992: return \"move%.l %1,%0\";
993: }")
994:
995: (define_insn "movdf"
996: [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>,y,rm,x,!x,!rm")
997: (match_operand:DF 1 "general_operand" "rf,m,rofF<>,rmF,y,xH,rm,x"))]
998: ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
999: ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1000: ""
1001: "*
1002: {
1003: if (which_alternative == 6)
1004: return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1005: if (FPA_REG_P (operands[0]))
1006: {
1007: if (GET_CODE (operands[1]) == CONST_DOUBLE)
1008: return output_move_const_double (operands);
1009: if (FP_REG_P (operands[1]))
1010: return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1011: return \"fpmove%.d %x1,%x0\";
1012: }
1013: else if (FPA_REG_P (operands[1]))
1014: {
1015: if (FP_REG_P(operands[0]))
1016: return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1017: else
1018: return \"fpmove%.d %x1,%x0\";
1019: }
1020: if (FP_REG_P (operands[0]))
1021: {
1022: if (FP_REG_P (operands[1]))
1023: return \"fmove%.x %1,%0\";
1024: if (REG_P (operands[1]))
1025: {
1026: rtx xoperands[2];
1027: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1028: output_asm_insn (\"move%.l %1,%-\", xoperands);
1029: output_asm_insn (\"move%.l %1,%-\", operands);
1030: return \"fmove%.d %+,%0\";
1031: }
1032: if (GET_CODE (operands[1]) == CONST_DOUBLE)
1033: return output_move_const_double (operands);
1034: return \"fmove%.d %f1,%0\";
1035: }
1036: else if (FP_REG_P (operands[1]))
1037: {
1038: if (REG_P (operands[0]))
1039: {
1040: output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1041: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1042: return \"move%.l %+,%0\";
1043: }
1044: else
1045: return \"fmove%.d %f1,%0\";
1046: }
1047: return output_move_double (operands);
1048: }
1049: ")
1050:
1051: ;; movdi can apply to fp regs in some cases
1052: (define_insn "movdi"
1053: ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1054: [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,y,rm,!*x,!rm")
1055: (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1056: ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1057: ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1058: ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1059: ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1060: ""
1061: "*
1062: {
1063: if (which_alternative == 8)
1064: return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1065: if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1066: return \"fpmove%.d %x1,%x0\";
1067: if (FP_REG_P (operands[0]))
1068: {
1069: if (FP_REG_P (operands[1]))
1070: return \"fmove%.x %1,%0\";
1071: if (REG_P (operands[1]))
1072: {
1073: rtx xoperands[2];
1074: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
1075: output_asm_insn (\"move%.l %1,%-\", xoperands);
1076: output_asm_insn (\"move%.l %1,%-\", operands);
1077: return \"fmove%.d %+,%0\";
1078: }
1079: if (GET_CODE (operands[1]) == CONST_DOUBLE)
1080: return output_move_const_double (operands);
1081: return \"fmove%.d %f1,%0\";
1082: }
1083: else if (FP_REG_P (operands[1]))
1084: {
1085: if (REG_P (operands[0]))
1086: {
1087: output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1088: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1089: return \"move%.l %+,%0\";
1090: }
1091: else
1092: return \"fmove%.d %f1,%0\";
1093: }
1094: return output_move_double (operands);
1095: }
1096: ")
1097:
1098: ;; Thus goes after the move instructions
1099: ;; because the move instructions are better (require no spilling)
1100: ;; when they can apply. It goes before the add/sub insns
1101: ;; so we will prefer it to them.
1102:
1103: (define_insn "pushasi"
1104: [(set (match_operand:SI 0 "push_operand" "=m")
1105: (match_operand:SI 1 "address_operand" "p"))]
1106: ""
1107: "pea %a1")
1108:
1109: ;; truncation instructions
1110: (define_insn "truncsiqi2"
1111: [(set (match_operand:QI 0 "general_operand" "=dm,d")
1112: (truncate:QI
1113: (match_operand:SI 1 "general_operand" "doJ,i")))]
1114: ""
1115: "*
1116: {
1117: if (GET_CODE (operands[0]) == REG)
1.1.1.4 ! root 1118: {
! 1119: /* Must clear condition codes, since the mov.l bases them on
! 1120: the entire 32 bits, not just the desired 8 bits. */
! 1121: CC_STATUS_INIT;
! 1122: return \"move%.l %1,%0\";
! 1123: }
1.1 root 1124: if (GET_CODE (operands[1]) == MEM)
1125: operands[1] = adj_offsettable_operand (operands[1], 3);
1126: return \"move%.b %1,%0\";
1127: }")
1128:
1129: (define_insn "trunchiqi2"
1130: [(set (match_operand:QI 0 "general_operand" "=dm,d")
1131: (truncate:QI
1132: (match_operand:HI 1 "general_operand" "doJ,i")))]
1133: ""
1134: "*
1135: {
1136: if (GET_CODE (operands[0]) == REG
1137: && (GET_CODE (operands[1]) == MEM
1138: || GET_CODE (operands[1]) == CONST_INT))
1.1.1.4 ! root 1139: {
! 1140: /* Must clear condition codes, since the mov.w bases them on
! 1141: the entire 16 bits, not just the desired 8 bits. */
! 1142: CC_STATUS_INIT;
! 1143: return \"move%.w %1,%0\";
! 1144: }
1.1 root 1145: if (GET_CODE (operands[0]) == REG)
1.1.1.4 ! root 1146: {
! 1147: /* Must clear condition codes, since the mov.l bases them on
! 1148: the entire 32 bits, not just the desired 8 bits. */
! 1149: CC_STATUS_INIT;
! 1150: return \"move%.l %1,%0\";
! 1151: }
1.1 root 1152: if (GET_CODE (operands[1]) == MEM)
1153: operands[1] = adj_offsettable_operand (operands[1], 1);
1154: return \"move%.b %1,%0\";
1155: }")
1156:
1157: (define_insn "truncsihi2"
1158: [(set (match_operand:HI 0 "general_operand" "=dm,d")
1159: (truncate:HI
1160: (match_operand:SI 1 "general_operand" "roJ,i")))]
1161: ""
1162: "*
1163: {
1164: if (GET_CODE (operands[0]) == REG)
1.1.1.4 ! root 1165: {
! 1166: /* Must clear condition codes, since the mov.l bases them on
! 1167: the entire 32 bits, not just the desired 8 bits. */
! 1168: CC_STATUS_INIT;
! 1169: return \"move%.l %1,%0\";
! 1170: }
1.1 root 1171: if (GET_CODE (operands[1]) == MEM)
1172: operands[1] = adj_offsettable_operand (operands[1], 2);
1173: return \"move%.w %1,%0\";
1174: }")
1175:
1176: ;; zero extension instructions
1177:
1178: (define_expand "zero_extendhisi2"
1179: [(set (match_operand:SI 0 "register_operand" "")
1180: (const_int 0))
1181: (set (strict_low_part (subreg:HI (match_dup 0) 0))
1182: (match_operand:HI 1 "general_operand" ""))]
1183: ""
1184: "operands[1] = make_safe_from (operands[1], operands[0]);")
1185:
1186: (define_expand "zero_extendqihi2"
1187: [(set (match_operand:HI 0 "register_operand" "")
1188: (const_int 0))
1189: (set (strict_low_part (subreg:QI (match_dup 0) 0))
1190: (match_operand:QI 1 "general_operand" ""))]
1191: ""
1192: "operands[1] = make_safe_from (operands[1], operands[0]);")
1193:
1194: (define_expand "zero_extendqisi2"
1195: [(set (match_operand:SI 0 "register_operand" "")
1196: (const_int 0))
1197: (set (strict_low_part (subreg:QI (match_dup 0) 0))
1198: (match_operand:QI 1 "general_operand" ""))]
1199: ""
1200: " operands[1] = make_safe_from (operands[1], operands[0]); ")
1201:
1202: ;; Patterns to recognize zero-extend insns produced by the combiner.
1203:
1204: ;; Note that the one starting from HImode comes before those for QImode
1205: ;; so that a constant operand will match HImode, not QImode.
1206: (define_insn ""
1207: [(set (match_operand:SI 0 "general_operand" "=do<>")
1208: (zero_extend:SI
1209: (match_operand:HI 1 "general_operand" "rmn")))]
1210: ""
1211: "*
1212: {
1213: if (DATA_REG_P (operands[0]))
1214: {
1215: if (GET_CODE (operands[1]) == REG
1216: && REGNO (operands[0]) == REGNO (operands[1]))
1217: return \"and%.l %#0xFFFF,%0\";
1218: if (reg_mentioned_p (operands[0], operands[1]))
1219: return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1220: return \"clr%.l %0\;move%.w %1,%0\";
1221: }
1222: else if (GET_CODE (operands[0]) == MEM
1223: && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1224: return \"move%.w %1,%0\;clr%.w %0\";
1225: else if (GET_CODE (operands[0]) == MEM
1226: && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1227: return \"clr%.w %0\;move%.w %1,%0\";
1228: else
1229: {
1230: output_asm_insn (\"clr%.w %0\", operands);
1231: operands[0] = adj_offsettable_operand (operands[0], 2);
1232: return \"move%.w %1,%0\";
1233: }
1234: }")
1235:
1236: (define_insn ""
1237: [(set (match_operand:HI 0 "general_operand" "=do<>")
1238: (zero_extend:HI
1239: (match_operand:QI 1 "general_operand" "dmn")))]
1240: ""
1241: "*
1242: {
1243: if (DATA_REG_P (operands[0]))
1244: {
1245: if (GET_CODE (operands[1]) == REG
1246: && REGNO (operands[0]) == REGNO (operands[1]))
1247: return \"and%.w %#0xFF,%0\";
1248: if (reg_mentioned_p (operands[0], operands[1]))
1249: return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1250: return \"clr%.w %0\;move%.b %1,%0\";
1251: }
1252: else if (GET_CODE (operands[0]) == MEM
1253: && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1254: {
1.1.1.3 root 1255: if (REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM)
1256: {
1.1.1.4 ! root 1257: output_asm_insn (\"clr%.w %-\", operands);
1.1.1.3 root 1258: operands[0] = gen_rtx (MEM, GET_MODE (operands[0]),
1259: plus_constant (stack_pointer_rtx, 1));
1260: return \"move%.b %1,%0\";
1261: }
1.1 root 1262: else
1263: return \"move%.b %1,%0\;clr%.b %0\";
1264: }
1265: else if (GET_CODE (operands[0]) == MEM
1266: && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1267: return \"clr%.b %0\;move%.b %1,%0\";
1268: else
1269: {
1270: output_asm_insn (\"clr%.b %0\", operands);
1271: operands[0] = adj_offsettable_operand (operands[0], 1);
1272: return \"move%.b %1,%0\";
1273: }
1274: }")
1275:
1276: (define_insn ""
1277: [(set (match_operand:SI 0 "general_operand" "=do<>")
1278: (zero_extend:SI
1279: (match_operand:QI 1 "general_operand" "dmn")))]
1280: ""
1281: "*
1282: {
1283: if (DATA_REG_P (operands[0]))
1284: {
1285: if (GET_CODE (operands[1]) == REG
1286: && REGNO (operands[0]) == REGNO (operands[1]))
1287: return \"and%.l %#0xFF,%0\";
1288: if (reg_mentioned_p (operands[0], operands[1]))
1289: return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1290: return \"clr%.l %0\;move%.b %1,%0\";
1291: }
1292: else if (GET_CODE (operands[0]) == MEM
1293: && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1294: {
1295: operands[0] = XEXP (XEXP (operands[0], 0), 0);
1296: #ifdef MOTOROLA
1297: #ifdef SGS
1298: return \"clr.l -(%0)\;move%.b %1,3(%0)\";
1299: #else
1300: return \"clr.l -(%0)\;move%.b %1,(3,%0)\";
1301: #endif
1302: #else
1303: return \"clrl %0@-\;moveb %1,%0@(3)\";
1304: #endif
1305: }
1306: else if (GET_CODE (operands[0]) == MEM
1307: && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1308: {
1309: operands[0] = XEXP (XEXP (operands[0], 0), 0);
1310: #ifdef MOTOROLA
1311: #ifdef SGS
1312: return \"clr.l (%0)+\;move%.b %1,-1(%0)\";
1313: #else
1314: return \"clr.l (%0)+\;move%.b %1,(-1,%0)\";
1315: #endif
1316: #else
1317: return \"clrl %0@+\;moveb %1,%0@(-1)\";
1318: #endif
1319: }
1320: else
1321: {
1322: output_asm_insn (\"clr%.l %0\", operands);
1323: operands[0] = adj_offsettable_operand (operands[0], 3);
1324: return \"move%.b %1,%0\";
1325: }
1326: }")
1327:
1328: ;; sign extension instructions
1329: ;; Note that the one starting from HImode comes before those for QImode
1330: ;; so that a constant operand will match HImode, not QImode.
1331:
1332: (define_insn "extendhisi2"
1333: [(set (match_operand:SI 0 "general_operand" "=*d,a")
1334: (sign_extend:SI
1335: (match_operand:HI 1 "general_operand" "0,rmn")))]
1336: ""
1337: "*
1338: {
1339: if (ADDRESS_REG_P (operands[0]))
1340: return \"move%.w %1,%0\";
1341: return \"ext%.l %0\";
1342: }")
1343:
1344: (define_insn "extendqihi2"
1345: [(set (match_operand:HI 0 "general_operand" "=d")
1346: (sign_extend:HI
1347: (match_operand:QI 1 "general_operand" "0")))]
1348: ""
1349: "ext%.w %0")
1350:
1351: (define_insn "extendqisi2"
1352: [(set (match_operand:SI 0 "general_operand" "=d")
1353: (sign_extend:SI
1354: (match_operand:QI 1 "general_operand" "0")))]
1355: "TARGET_68020"
1356: "extb%.l %0")
1357:
1358: ;; Conversions between float and double.
1359:
1360: (define_expand "extendsfdf2"
1361: [(set (match_operand:DF 0 "general_operand" "")
1362: (float_extend:DF
1363: (match_operand:SF 1 "general_operand" "")))]
1364: "TARGET_68881 || TARGET_FPA"
1365: "")
1366:
1367: (define_insn ""
1368: [(set (match_operand:DF 0 "general_operand" "=x,y")
1369: (float_extend:DF
1370: (match_operand:SF 1 "general_operand" "xH,rmF")))]
1371: "TARGET_FPA"
1372: "fpstod %w1,%0")
1373:
1374: (define_insn ""
1375: [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1376: (float_extend:DF
1377: (match_operand:SF 1 "general_operand" "f,dmF")))]
1378: "TARGET_68881"
1379: "*
1380: {
1381: if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1382: {
1383: if (REGNO (operands[0]) == REGNO (operands[1]))
1384: {
1385: /* Extending float to double in an fp-reg is a no-op.
1386: NOTICE_UPDATE_CC has already assumed that the
1387: cc will be set. So cancel what it did. */
1388: cc_status = cc_prev_status;
1389: return \"\";
1390: }
1391: return \"fmove%.x %1,%0\";
1392: }
1393: if (FP_REG_P (operands[0]))
1394: return \"fmove%.s %f1,%0\";
1395: if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1396: {
1397: output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1398: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1399: return \"move%.l %+,%0\";
1400: }
1401: return \"fmove%.d %f1,%0\";
1402: }")
1403:
1404: ;; This cannot output into an f-reg because there is no way to be
1405: ;; sure of truncating in that case.
1406: ;; But on the Sun FPA, we can be sure.
1407: (define_expand "truncdfsf2"
1408: [(set (match_operand:SF 0 "general_operand" "")
1409: (float_truncate:SF
1410: (match_operand:DF 1 "general_operand" "")))]
1411: "TARGET_68881 || TARGET_FPA"
1412: "")
1413:
1414: (define_insn ""
1.1.1.2 root 1415: [(set (match_operand:SF 0 "general_operand" "=x,y")
1.1 root 1416: (float_truncate:SF
1417: (match_operand:DF 1 "general_operand" "xH,rmF")))]
1418: "TARGET_FPA"
1419: "fpdtos %y1,%0")
1420:
1421: (define_insn ""
1422: [(set (match_operand:SF 0 "general_operand" "=dm")
1423: (float_truncate:SF
1424: (match_operand:DF 1 "general_operand" "f")))]
1425: "TARGET_68881"
1426: "fmove%.s %f1,%0")
1427:
1428: ;; Conversion between fixed point and floating point.
1429: ;; Note that among the fix-to-float insns
1430: ;; the ones that start with SImode come first.
1431: ;; That is so that an operand that is a CONST_INT
1432: ;; (and therefore lacks a specific machine mode).
1433: ;; will be recognized as SImode (which is always valid)
1434: ;; rather than as QImode or HImode.
1435:
1436: (define_expand "floatsisf2"
1437: [(set (match_operand:SF 0 "general_operand" "")
1438: (float:SF (match_operand:SI 1 "general_operand" "")))]
1439: "TARGET_68881 || TARGET_FPA"
1440: "")
1441:
1442: (define_insn ""
1443: [(set (match_operand:SF 0 "general_operand" "=y,x")
1444: (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1445: "TARGET_FPA"
1446: "fpltos %1,%0")
1447:
1448: (define_insn ""
1449: [(set (match_operand:SF 0 "general_operand" "=f")
1450: (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1451: "TARGET_68881"
1452: "fmove%.l %1,%0")
1453:
1454: (define_expand "floatsidf2"
1455: [(set (match_operand:DF 0 "general_operand" "")
1456: (float:DF (match_operand:SI 1 "general_operand" "")))]
1457: "TARGET_68881 || TARGET_FPA"
1458: "")
1459:
1460: (define_insn ""
1.1.1.2 root 1461: [(set (match_operand:DF 0 "general_operand" "=y,x")
1.1 root 1462: (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1463: "TARGET_FPA"
1464: "fpltod %1,%0")
1465:
1466: (define_insn ""
1467: [(set (match_operand:DF 0 "general_operand" "=f")
1468: (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1469: "TARGET_68881"
1470: "fmove%.l %1,%0")
1471:
1472: (define_insn "floathisf2"
1473: [(set (match_operand:SF 0 "general_operand" "=f")
1474: (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1475: "TARGET_68881"
1476: "fmove%.w %1,%0")
1477:
1478: (define_insn "floathidf2"
1479: [(set (match_operand:DF 0 "general_operand" "=f")
1480: (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1481: "TARGET_68881"
1482: "fmove%.w %1,%0")
1483:
1484: (define_insn "floatqisf2"
1485: [(set (match_operand:SF 0 "general_operand" "=f")
1486: (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1487: "TARGET_68881"
1488: "fmove%.b %1,%0")
1489:
1490: (define_insn "floatqidf2"
1491: [(set (match_operand:DF 0 "general_operand" "=f")
1492: (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1493: "TARGET_68881"
1494: "fmove%.b %1,%0")
1495:
1496: ;; Convert a float to a float whose value is an integer.
1497: ;; This is the first stage of converting it to an integer type.
1498:
1499: (define_insn "ftruncdf2"
1500: [(set (match_operand:DF 0 "general_operand" "=f")
1501: (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1502: "TARGET_68881"
1503: "*
1504: {
1505: if (FP_REG_P (operands[1]))
1506: return \"fintrz%.x %f1,%0\";
1507: return \"fintrz%.d %f1,%0\";
1508: }")
1509:
1510: (define_insn "ftruncsf2"
1511: [(set (match_operand:SF 0 "general_operand" "=f")
1512: (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1513: "TARGET_68881"
1514: "*
1515: {
1516: if (FP_REG_P (operands[1]))
1517: return \"fintrz%.x %f1,%0\";
1518: return \"fintrz%.s %f1,%0\";
1519: }")
1520:
1521: ;; Convert a float whose value is an integer
1522: ;; to an actual integer. Second stage of converting float to integer type.
1523: (define_insn "fixsfqi2"
1524: [(set (match_operand:QI 0 "general_operand" "=dm")
1525: (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1526: "TARGET_68881"
1527: "fmove%.b %1,%0")
1528:
1529: (define_insn "fixsfhi2"
1530: [(set (match_operand:HI 0 "general_operand" "=dm")
1531: (fix:HI (match_operand:SF 1 "general_operand" "f")))]
1532: "TARGET_68881"
1533: "fmove%.w %1,%0")
1534:
1535: (define_insn "fixsfsi2"
1536: [(set (match_operand:SI 0 "general_operand" "=dm")
1537: (fix:SI (match_operand:SF 1 "general_operand" "f")))]
1538: "TARGET_68881"
1539: "fmove%.l %1,%0")
1540:
1541: (define_insn "fixdfqi2"
1542: [(set (match_operand:QI 0 "general_operand" "=dm")
1543: (fix:QI (match_operand:DF 1 "general_operand" "f")))]
1544: "TARGET_68881"
1545: "fmove%.b %1,%0")
1546:
1547: (define_insn "fixdfhi2"
1548: [(set (match_operand:HI 0 "general_operand" "=dm")
1549: (fix:HI (match_operand:DF 1 "general_operand" "f")))]
1550: "TARGET_68881"
1551: "fmove%.w %1,%0")
1552:
1553: (define_insn "fixdfsi2"
1554: [(set (match_operand:SI 0 "general_operand" "=dm")
1555: (fix:SI (match_operand:DF 1 "general_operand" "f")))]
1556: "TARGET_68881"
1557: "fmove%.l %1,%0")
1558:
1559: ;; Convert a float to an integer.
1560: ;; On the Sun FPA, this is done in one step.
1561:
1562: (define_insn "fix_truncsfsi2"
1563: [(set (match_operand:SI 0 "general_operand" "=x,y")
1564: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
1565: "TARGET_FPA"
1566: "fpstol %w1,%0")
1567:
1568: (define_insn "fix_truncdfsi2"
1569: [(set (match_operand:SI 0 "general_operand" "=x,y")
1570: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
1571: "TARGET_FPA"
1572: "fpdtol %y1,%0")
1573:
1574: ;; add instructions
1575:
1576: ;; Note that the last two alternatives are near-duplicates
1577: ;; in order to handle insns generated by reload.
1578: ;; This is needed since they are not themselves reloaded,
1579: ;; so commutativity won't apply to them.
1580: (define_insn "addsi3"
1581: [(set (match_operand:SI 0 "general_operand" "=m,r,!a,!a")
1582: (plus:SI (match_operand:SI 1 "general_operand" "%0,0,a,rJK")
1583: (match_operand:SI 2 "general_operand" "dIKLs,mrIKLs,rJK,a")))]
1584: ""
1585: "*
1586: {
1587: if (! operands_match_p (operands[0], operands[1]))
1588: {
1589: if (!ADDRESS_REG_P (operands[1]))
1590: {
1591: rtx tmp = operands[1];
1592:
1593: operands[1] = operands[2];
1594: operands[2] = tmp;
1595: }
1596:
1597: /* These insns can result from reloads to access
1598: stack slots over 64k from the frame pointer. */
1599: if (GET_CODE (operands[2]) == CONST_INT
1600: && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
1601: return \"move%.l %2,%0\;add%.l %1,%0\";
1602: #ifdef SGS
1603: if (GET_CODE (operands[2]) == REG)
1604: return \"lea 0(%1,%2.l),%0\";
1605: else
1606: return \"lea %c2(%1),%0\";
1607: #else /* not SGS */
1608: #ifdef MOTOROLA
1609: if (GET_CODE (operands[2]) == REG)
1610: return \"lea (%1,%2.l),%0\";
1611: else
1612: return \"lea (%c2,%1),%0\";
1613: #else /* not MOTOROLA (MIT syntax) */
1614: if (GET_CODE (operands[2]) == REG)
1615: return \"lea %1@(0,%2:l),%0\";
1616: else
1617: return \"lea %1@(%c2),%0\";
1618: #endif /* not MOTOROLA */
1619: #endif /* not SGS */
1620: }
1621: if (GET_CODE (operands[2]) == CONST_INT)
1622: {
1623: #ifndef NO_ADDSUB_Q
1624: if (INTVAL (operands[2]) > 0
1625: && INTVAL (operands[2]) <= 8)
1626: return (ADDRESS_REG_P (operands[0])
1627: ? \"addq%.w %2,%0\"
1628: : \"addq%.l %2,%0\");
1629: if (INTVAL (operands[2]) < 0
1630: && INTVAL (operands[2]) >= -8)
1631: {
1632: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1633: - INTVAL (operands[2]));
1634: return (ADDRESS_REG_P (operands[0])
1635: ? \"subq%.w %2,%0\"
1636: : \"subq%.l %2,%0\");
1637: }
1638: #endif
1639: if (ADDRESS_REG_P (operands[0])
1640: && INTVAL (operands[2]) >= -0x8000
1641: && INTVAL (operands[2]) < 0x8000)
1642: return \"add%.w %2,%0\";
1643: }
1644: return \"add%.l %2,%0\";
1645: }")
1646:
1647: (define_insn ""
1648: [(set (match_operand:SI 0 "general_operand" "=a")
1649: (plus:SI (match_operand:SI 1 "general_operand" "0")
1650: (sign_extend:SI (match_operand:HI 2 "general_operand" "rmn"))))]
1651: ""
1652: "add%.w %2,%0")
1653:
1654: (define_insn "addhi3"
1655: [(set (match_operand:HI 0 "general_operand" "=m,r")
1656: (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
1657: (match_operand:HI 2 "general_operand" "dn,rmn")))]
1658: ""
1659: "*
1660: {
1661: #ifndef NO_ADDSUB_Q
1662: if (GET_CODE (operands[2]) == CONST_INT)
1663: {
1664: if (INTVAL (operands[2]) > 0
1665: && INTVAL (operands[2]) <= 8)
1666: return \"addq%.w %2,%0\";
1667: }
1668: if (GET_CODE (operands[2]) == CONST_INT)
1669: {
1670: if (INTVAL (operands[2]) < 0
1671: && INTVAL (operands[2]) >= -8)
1672: {
1673: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1674: - INTVAL (operands[2]));
1675: return \"subq%.w %2,%0\";
1676: }
1677: }
1678: #endif
1679: return \"add%.w %2,%0\";
1680: }")
1681:
1682: (define_insn ""
1683: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
1684: (plus:HI (match_dup 0)
1685: (match_operand:HI 1 "general_operand" "dn,rmn")))]
1686: ""
1687: "add%.w %1,%0")
1688:
1689: (define_insn "addqi3"
1690: [(set (match_operand:QI 0 "general_operand" "=m,d")
1691: (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
1692: (match_operand:QI 2 "general_operand" "dn,dmn")))]
1693: ""
1694: "*
1695: {
1696: #ifndef NO_ADDSUB_Q
1697: if (GET_CODE (operands[2]) == CONST_INT)
1698: {
1699: if (INTVAL (operands[2]) > 0
1700: && INTVAL (operands[2]) <= 8)
1701: return \"addq%.b %2,%0\";
1702: }
1703: if (GET_CODE (operands[2]) == CONST_INT)
1704: {
1705: if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
1706: {
1707: operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]));
1708: return \"subq%.b %2,%0\";
1709: }
1710: }
1711: #endif
1712: return \"add%.b %2,%0\";
1713: }")
1714:
1715: (define_insn ""
1716: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
1717: (plus:QI (match_dup 0)
1718: (match_operand:QI 1 "general_operand" "dn,dmn")))]
1719: ""
1720: "add%.b %1,%0")
1721:
1722: (define_expand "adddf3"
1723: [(set (match_operand:DF 0 "general_operand" "")
1724: (plus:DF (match_operand:DF 1 "general_operand" "")
1725: (match_operand:DF 2 "general_operand" "")))]
1726: "TARGET_68881 || TARGET_FPA"
1727: "")
1728:
1729: (define_insn ""
1730: [(set (match_operand:DF 0 "general_operand" "=x,y")
1731: (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
1732: (match_operand:DF 2 "general_operand" "xH,dmF")))]
1733: "TARGET_FPA"
1734: "*
1735: {
1736: if (rtx_equal_p (operands[0], operands[1]))
1737: return \"fpadd%.d %y2,%0\";
1738: if (rtx_equal_p (operands[0], operands[2]))
1739: return \"fpadd%.d %y1,%0\";
1740: if (which_alternative == 0)
1741: return \"fpadd3%.d %w2,%w1,%0\";
1742: return \"fpadd3%.d %x2,%x1,%0\";
1743: }")
1744:
1745: (define_insn ""
1746: [(set (match_operand:DF 0 "general_operand" "=f")
1747: (plus:DF (match_operand:DF 1 "general_operand" "%0")
1748: (match_operand:DF 2 "general_operand" "fmG")))]
1749: "TARGET_68881"
1750: "*
1751: {
1752: if (REG_P (operands[2]))
1753: return \"fadd%.x %2,%0\";
1754: return \"fadd%.d %f2,%0\";
1755: }")
1756:
1757: (define_expand "addsf3"
1758: [(set (match_operand:SF 0 "general_operand" "")
1759: (plus:SF (match_operand:SF 1 "general_operand" "")
1760: (match_operand:SF 2 "general_operand" "")))]
1761: "TARGET_68881 || TARGET_FPA"
1762: "")
1763:
1764: (define_insn ""
1765: [(set (match_operand:SF 0 "general_operand" "=x,y")
1766: (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
1767: (match_operand:SF 2 "general_operand" "xH,rmF")))]
1768: "TARGET_FPA"
1769: "*
1770: {
1771: if (rtx_equal_p (operands[0], operands[1]))
1772: return \"fpadd%.s %w2,%0\";
1773: if (rtx_equal_p (operands[0], operands[2]))
1774: return \"fpadd%.s %w1,%0\";
1775: if (which_alternative == 0)
1776: return \"fpadd3%.s %w2,%w1,%0\";
1777: return \"fpadd3%.s %2,%1,%0\";
1778: }")
1779:
1780: (define_insn ""
1781: [(set (match_operand:SF 0 "general_operand" "=f")
1782: (plus:SF (match_operand:SF 1 "general_operand" "%0")
1783: (match_operand:SF 2 "general_operand" "fdmF")))]
1784: "TARGET_68881"
1785: "*
1786: {
1787: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
1788: return \"fadd%.x %2,%0\";
1789: return \"fadd%.s %f2,%0\";
1790: }")
1791:
1792: ;; subtract instructions
1793:
1794: (define_insn "subsi3"
1795: [(set (match_operand:SI 0 "general_operand" "=m,r,!a,?d")
1796: (minus:SI (match_operand:SI 1 "general_operand" "0,0,a,mrIKs")
1797: (match_operand:SI 2 "general_operand" "dIKs,mrIKs,J,0")))]
1798: ""
1799: "*
1800: {
1801: if (! operands_match_p (operands[0], operands[1]))
1802: {
1803: if (operands_match_p (operands[0], operands[2]))
1804: {
1805: #ifndef NO_ADDSUB_Q
1806: if (GET_CODE (operands[1]) == CONST_INT)
1807: {
1808: if (INTVAL (operands[1]) > 0
1809: && INTVAL (operands[1]) <= 8)
1810: return \"subq%.l %1,%0\;neg%.l %0\";
1811: }
1812: #endif
1813: return \"sub%.l %1,%0\;neg%.l %0\";
1814: }
1815: /* This case is matched by J, but negating -0x8000
1816: in an lea would give an invalid displacement.
1817: So do this specially. */
1818: if (INTVAL (operands[2]) == -0x8000)
1819: return \"move%.l %1,%0\;sub%.l %2,%0\";
1820: #ifdef SGS
1821: return \"lea %n2(%1),%0\";
1822: #else
1823: #ifdef MOTOROLA
1824: return \"lea (%n2,%1),%0\";
1825: #else /* not MOTOROLA (MIT syntax) */
1826: return \"lea %1@(%n2),%0\";
1827: #endif /* not MOTOROLA */
1828: #endif /* not SGS */
1829: }
1830: if (GET_CODE (operands[2]) == CONST_INT)
1831: {
1832: #ifndef NO_ADDSUB_Q
1833: if (INTVAL (operands[2]) > 0
1834: && INTVAL (operands[2]) <= 8)
1835: return \"subq%.l %2,%0\";
1836: #endif
1837: if (ADDRESS_REG_P (operands[0])
1838: && INTVAL (operands[2]) >= -0x8000
1839: && INTVAL (operands[2]) < 0x8000)
1840: return \"sub%.w %2,%0\";
1841: }
1842: return \"sub%.l %2,%0\";
1843: }")
1844:
1845: (define_insn ""
1846: [(set (match_operand:SI 0 "general_operand" "=a")
1847: (minus:SI (match_operand:SI 1 "general_operand" "0")
1848: (sign_extend:SI (match_operand:HI 2 "general_operand" "rmn"))))]
1849: ""
1850: "sub%.w %2,%0")
1851:
1852: (define_insn "subhi3"
1853: [(set (match_operand:HI 0 "general_operand" "=m,r")
1854: (minus:HI (match_operand:HI 1 "general_operand" "0,0")
1855: (match_operand:HI 2 "general_operand" "dn,rmn")))]
1856: ""
1857: "sub%.w %2,%0")
1858:
1859: (define_insn ""
1860: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
1861: (minus:HI (match_dup 0)
1862: (match_operand:HI 1 "general_operand" "dn,rmn")))]
1863: ""
1864: "sub%.w %1,%0")
1865:
1866: (define_insn "subqi3"
1867: [(set (match_operand:QI 0 "general_operand" "=m,d")
1868: (minus:QI (match_operand:QI 1 "general_operand" "0,0")
1869: (match_operand:QI 2 "general_operand" "dn,dmn")))]
1870: ""
1871: "sub%.b %2,%0")
1872:
1873: (define_insn ""
1874: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
1875: (minus:QI (match_dup 0)
1876: (match_operand:QI 1 "general_operand" "dn,dmn")))]
1877: ""
1878: "sub%.b %1,%0")
1879:
1880: (define_expand "subdf3"
1881: [(set (match_operand:DF 0 "general_operand" "")
1882: (minus:DF (match_operand:DF 1 "general_operand" "")
1883: (match_operand:DF 2 "general_operand" "")))]
1884: "TARGET_68881 || TARGET_FPA"
1885: "")
1886:
1887: (define_insn ""
1888: [(set (match_operand:DF 0 "general_operand" "=x,y,y")
1889: (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
1890: (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
1891: "TARGET_FPA"
1892: "*
1893: {
1894: if (rtx_equal_p (operands[0], operands[2]))
1895: return \"fprsub%.d %y1,%0\";
1896: if (rtx_equal_p (operands[0], operands[1]))
1897: return \"fpsub%.d %y2,%0\";
1898: if (which_alternative == 0)
1899: return \"fpsub3%.d %w2,%w1,%0\";
1900: return \"fpsub3%.d %x2,%x1,%0\";
1901: }")
1902:
1903: (define_insn ""
1904: [(set (match_operand:DF 0 "general_operand" "=f")
1905: (minus:DF (match_operand:DF 1 "general_operand" "0")
1906: (match_operand:DF 2 "general_operand" "fmG")))]
1907: "TARGET_68881"
1908: "*
1909: {
1910: if (REG_P (operands[2]))
1911: return \"fsub%.x %2,%0\";
1912: return \"fsub%.d %f2,%0\";
1913: }")
1914:
1915: (define_expand "subsf3"
1916: [(set (match_operand:SF 0 "general_operand" "")
1917: (minus:SF (match_operand:SF 1 "general_operand" "")
1918: (match_operand:SF 2 "general_operand" "")))]
1919: "TARGET_68881 || TARGET_FPA"
1920: "")
1921:
1922: (define_insn ""
1923: [(set (match_operand:SF 0 "general_operand" "=x,y,y")
1924: (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
1925: (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
1926: "TARGET_FPA"
1927: "*
1928: {
1929: if (rtx_equal_p (operands[0], operands[2]))
1930: return \"fprsub%.s %w1,%0\";
1931: if (rtx_equal_p (operands[0], operands[1]))
1932: return \"fpsub%.s %w2,%0\";
1933: if (which_alternative == 0)
1934: return \"fpsub3%.s %w2,%w1,%0\";
1935: return \"fpsub3%.s %2,%1,%0\";
1936: }")
1937:
1938: (define_insn ""
1939: [(set (match_operand:SF 0 "general_operand" "=f")
1940: (minus:SF (match_operand:SF 1 "general_operand" "0")
1941: (match_operand:SF 2 "general_operand" "fdmF")))]
1942: "TARGET_68881"
1943: "*
1944: {
1945: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
1946: return \"fsub%.x %2,%0\";
1947: return \"fsub%.s %f2,%0\";
1948: }")
1949:
1950: ;; multiply instructions
1951:
1952: (define_insn "mulhi3"
1953: [(set (match_operand:HI 0 "general_operand" "=d")
1954: (mult:HI (match_operand:HI 1 "general_operand" "%0")
1955: (match_operand:HI 2 "general_operand" "dmn")))]
1956: ""
1957: "*
1958: {
1959: #ifdef MOTOROLA
1960: return \"muls.w %2,%0\";
1961: #else
1962: return \"muls %2,%0\";
1963: #endif
1964: }")
1965:
1966: (define_insn "mulhisi3"
1967: [(set (match_operand:SI 0 "general_operand" "=d")
1968: (mult:SI (match_operand:HI 1 "general_operand" "%0")
1969: (match_operand:HI 2 "general_operand" "dmn")))]
1970: ""
1971: "*
1972: {
1973: #ifdef MOTOROLA
1974: return \"muls.w %2,%0\";
1975: #else
1976: return \"muls %2,%0\";
1977: #endif
1978: }")
1979:
1980: (define_insn "mulsi3"
1981: [(set (match_operand:SI 0 "general_operand" "=d")
1982: (mult:SI (match_operand:SI 1 "general_operand" "%0")
1983: (match_operand:SI 2 "general_operand" "dmsK")))]
1984: "TARGET_68020"
1985: "muls%.l %2,%0")
1986:
1987: (define_insn "umulhi3"
1988: [(set (match_operand:HI 0 "general_operand" "=d")
1989: (umult:HI (match_operand:HI 1 "general_operand" "%0")
1990: (match_operand:HI 2 "general_operand" "dmn")))]
1991: ""
1992: "*
1993: {
1994: #ifdef MOTOROLA
1995: return \"mulu.w %2,%0\";
1996: #else
1997: return \"mulu %2,%0\";
1998: #endif
1999: }")
2000:
2001: (define_insn "umulhisi3"
2002: [(set (match_operand:SI 0 "general_operand" "=d")
2003: (umult:SI (match_operand:HI 1 "general_operand" "%0")
2004: (match_operand:HI 2 "general_operand" "dmn")))]
2005: ""
2006: "*
2007: {
2008: #ifdef MOTOROLA
2009: return \"mulu.w %2,%0\";
2010: #else
2011: return \"mulu %2,%0\";
2012: #endif
2013: }")
2014:
2015: (define_insn "umulsi3"
2016: [(set (match_operand:SI 0 "general_operand" "=d")
2017: (umult:SI (match_operand:SI 1 "general_operand" "%0")
2018: (match_operand:SI 2 "general_operand" "dmsK")))]
2019: "TARGET_68020"
2020: "mulu%.l %2,%0")
2021:
2022: (define_expand "muldf3"
2023: [(set (match_operand:DF 0 "general_operand" "")
2024: (mult:DF (match_operand:DF 1 "general_operand" "")
2025: (match_operand:DF 2 "general_operand" "")))]
2026: "TARGET_68881 || TARGET_FPA"
2027: "")
2028:
2029: (define_insn ""
2030: [(set (match_operand:DF 0 "general_operand" "=x,y")
2031: (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
2032: (match_operand:DF 2 "general_operand" "xH,rmF")))]
2033: "TARGET_FPA"
2034: "*
2035: {
2036: if (rtx_equal_p (operands[1], operands[2]))
2037: return \"fpsqr%.d %y1,%0\";
2038: if (rtx_equal_p (operands[0], operands[1]))
2039: return \"fpmul%.d %y2,%0\";
2040: if (rtx_equal_p (operands[0], operands[2]))
2041: return \"fpmul%.d %y1,%0\";
2042: if (which_alternative == 0)
2043: return \"fpmul3%.d %w2,%w1,%0\";
2044: return \"fpmul3%.d %x2,%x1,%0\";
2045: }")
2046:
2047: (define_insn ""
2048: [(set (match_operand:DF 0 "general_operand" "=f")
2049: (mult:DF (match_operand:DF 1 "general_operand" "%0")
2050: (match_operand:DF 2 "general_operand" "fmG")))]
2051: "TARGET_68881"
2052: "*
2053: {
2054: if (REG_P (operands[2]))
2055: return \"fmul%.x %2,%0\";
2056: return \"fmul%.d %f2,%0\";
2057: }")
2058:
2059: (define_expand "mulsf3"
2060: [(set (match_operand:SF 0 "general_operand" "")
2061: (mult:SF (match_operand:SF 1 "general_operand" "")
2062: (match_operand:SF 2 "general_operand" "")))]
2063: "TARGET_68881 || TARGET_FPA"
2064: "")
2065:
2066: (define_insn ""
2067: [(set (match_operand:SF 0 "general_operand" "=x,y")
2068: (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
2069: (match_operand:SF 2 "general_operand" "xH,rmF")))]
2070: "TARGET_FPA"
2071: "*
2072: {
2073: if (rtx_equal_p (operands[1], operands[2]))
2074: return \"fpsqr%.s %w1,%0\";
2075: if (rtx_equal_p (operands[0], operands[1]))
2076: return \"fpmul%.s %w2,%0\";
2077: if (rtx_equal_p (operands[0], operands[2]))
2078: return \"fpmul%.s %w1,%0\";
2079: if (which_alternative == 0)
2080: return \"fpmul3%.s %w2,%w1,%0\";
2081: return \"fpmul3%.s %2,%1,%0\";
2082: }")
2083:
2084: (define_insn ""
2085: [(set (match_operand:SF 0 "general_operand" "=f")
2086: (mult:SF (match_operand:SF 1 "general_operand" "%0")
2087: (match_operand:SF 2 "general_operand" "fdmF")))]
2088: "TARGET_68881"
2089: "*
2090: {
2091: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2092: return \"fsglmul%.x %2,%0\";
2093: return \"fsglmul%.s %f2,%0\";
2094: }")
2095:
2096: ;; divide instructions
2097:
2098: (define_insn "divhi3"
2099: [(set (match_operand:HI 0 "general_operand" "=d")
2100: (div:HI (match_operand:HI 1 "general_operand" "0")
2101: (match_operand:HI 2 "general_operand" "dmn")))]
2102: ""
2103: "*
2104: {
2105: #ifdef MOTOROLA
2106: return \"ext.l %0\;divs.w %2,%0\";
2107: #else
2108: return \"extl %0\;divs %2,%0\";
2109: #endif
2110: }")
2111:
2112: (define_insn "divhisi3"
2113: [(set (match_operand:HI 0 "general_operand" "=d")
2114: (div:HI (match_operand:SI 1 "general_operand" "0")
2115: (match_operand:HI 2 "general_operand" "dmn")))]
2116: ""
2117: "*
2118: {
2119: #ifdef MOTOROLA
2120: return \"divs.w %2,%0\";
2121: #else
2122: return \"divs %2,%0\";
2123: #endif
2124: }")
2125:
2126: (define_insn "divsi3"
2127: [(set (match_operand:SI 0 "general_operand" "=d")
2128: (div:SI (match_operand:SI 1 "general_operand" "0")
2129: (match_operand:SI 2 "general_operand" "dmsK")))]
2130: "TARGET_68020"
2131: "divs%.l %2,%0")
2132:
2133: (define_insn "udivhi3"
2134: [(set (match_operand:HI 0 "general_operand" "=d")
2135: (udiv:HI (match_operand:HI 1 "general_operand" "0")
2136: (match_operand:HI 2 "general_operand" "dmn")))]
2137: ""
2138: "*
2139: {
2140: #ifdef MOTOROLA
2141: return \"and.l %#0xFFFF,%0\;divu.w %2,%0\";
2142: #else
2143: return \"andl %#0xFFFF,%0\;divu %2,%0\";
2144: #endif
2145: }")
2146:
2147: (define_insn "udivhisi3"
2148: [(set (match_operand:HI 0 "general_operand" "=d")
2149: (udiv:HI (match_operand:SI 1 "general_operand" "0")
2150: (match_operand:HI 2 "general_operand" "dmn")))]
2151: ""
2152: "*
2153: {
2154: #ifdef MOTOROLA
2155: return \"divu.w %2,%0\";
2156: #else
2157: return \"divu %2,%0\";
2158: #endif
2159: }")
2160:
2161: (define_insn "udivsi3"
2162: [(set (match_operand:SI 0 "general_operand" "=d")
2163: (udiv:SI (match_operand:SI 1 "general_operand" "0")
2164: (match_operand:SI 2 "general_operand" "dmsK")))]
2165: "TARGET_68020"
2166: "divu%.l %2,%0")
2167:
2168: (define_expand "divdf3"
2169: [(set (match_operand:DF 0 "general_operand" "")
2170: (div:DF (match_operand:DF 1 "general_operand" "")
2171: (match_operand:DF 2 "general_operand" "")))]
2172: "TARGET_68881 || TARGET_FPA"
2173: "")
2174:
2175: (define_insn ""
2176: [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2177: (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
2178: (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
2179: "TARGET_FPA"
2180: "*
2181: {
2182: if (rtx_equal_p (operands[0], operands[2]))
2183: return \"fprdiv%.d %y1,%0\";
2184: if (rtx_equal_p (operands[0], operands[1]))
2185: return \"fpdiv%.d %y2,%0\";
2186: if (which_alternative == 0)
2187: return \"fpdiv3%.d %w2,%w1,%0\";
2188: return \"fpdiv3%.d %x2,%x1,%x0\";
2189: }")
2190:
2191: (define_insn ""
2192: [(set (match_operand:DF 0 "general_operand" "=f")
2193: (div:DF (match_operand:DF 1 "general_operand" "0")
2194: (match_operand:DF 2 "general_operand" "fmG")))]
2195: "TARGET_68881"
2196: "*
2197: {
2198: if (REG_P (operands[2]))
2199: return \"fdiv%.x %2,%0\";
2200: return \"fdiv%.d %f2,%0\";
2201: }")
2202:
2203: (define_expand "divsf3"
2204: [(set (match_operand:SF 0 "general_operand" "")
2205: (div:SF (match_operand:SF 1 "general_operand" "")
2206: (match_operand:SF 2 "general_operand" "")))]
2207: "TARGET_68881 || TARGET_FPA"
2208: "")
2209:
2210: (define_insn ""
2211: [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2212: (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2213: (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2214: "TARGET_FPA"
2215: "*
2216: {
2217: if (rtx_equal_p (operands[0], operands[1]))
2218: return \"fpdiv%.s %w2,%0\";
2219: if (rtx_equal_p (operands[0], operands[2]))
2220: return \"fprdiv%.s %w1,%0\";
2221: if (which_alternative == 0)
2222: return \"fpdiv3%.s %w2,%w1,%0\";
2223: return \"fpdiv3%.s %2,%1,%0\";
2224: }")
2225:
2226: (define_insn ""
2227: [(set (match_operand:SF 0 "general_operand" "=f")
2228: (div:SF (match_operand:SF 1 "general_operand" "0")
2229: (match_operand:SF 2 "general_operand" "fdmF")))]
2230: "TARGET_68881"
2231: "*
2232: {
2233: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2234: return \"fsgldiv%.x %2,%0\";
2235: return \"fsgldiv%.s %f2,%0\";
2236: }")
2237:
2238: ;; Remainder instructions.
2239:
2240: (define_insn "modhi3"
2241: [(set (match_operand:HI 0 "general_operand" "=d")
2242: (mod:HI (match_operand:HI 1 "general_operand" "0")
2243: (match_operand:HI 2 "general_operand" "dmn")))]
2244: ""
2245: "*
2246: {
2247: /* The swap insn produces cc's that don't correspond to the result. */
2248: CC_STATUS_INIT;
2249: #ifdef MOTOROLA
2250: #ifdef SGS_3B1
2251: return \"ext.l %0\;divs.w %2,%0\;swap.w %0\";
2252: #else
2253: return \"ext.l %0\;divs.w %2,%0\;swap %0\";
2254: #endif
2255: #else
2256: return \"extl %0\;divs %2,%0\;swap %0\";
2257: #endif
2258: }")
2259:
2260: (define_insn "modhisi3"
2261: [(set (match_operand:HI 0 "general_operand" "=d")
2262: (mod:HI (match_operand:SI 1 "general_operand" "0")
2263: (match_operand:HI 2 "general_operand" "dmn")))]
2264: ""
2265: "*
2266: {
2267: /* The swap insn produces cc's that don't correspond to the result. */
2268: CC_STATUS_INIT;
2269: #ifdef MOTOROLA
2270: #ifdef SGS_3B1
2271: return \"divs.w %2,%0\;swap.w %0\";
2272: #else
2273: return \"divs.w %2,%0\;swap %0\";
2274: #endif
2275: #else
2276: return \"divs %2,%0\;swap %0\";
2277: #endif
2278: }")
2279:
2280: (define_insn "umodhi3"
2281: [(set (match_operand:HI 0 "general_operand" "=d")
2282: (umod:HI (match_operand:HI 1 "general_operand" "0")
2283: (match_operand:HI 2 "general_operand" "dmn")))]
2284: ""
2285: "*
2286: {
2287: /* The swap insn produces cc's that don't correspond to the result. */
2288: CC_STATUS_INIT;
2289: #ifdef MOTOROLA
2290: #ifdef SGS_3B1
2291: return \"and.l %#0xFFFF,%0\;divu.w %2,%0\;swap.w %0\";
2292: #else
2293: return \"and.l %#0xFFFF,%0\;divu.w %2,%0\;swap %0\";
2294: #endif
2295: #else
2296: return \"andl %#0xFFFF,%0\;divu %2,%0\;swap %0\";
2297: #endif
2298: }")
2299:
2300: (define_insn "umodhisi3"
2301: [(set (match_operand:HI 0 "general_operand" "=d")
2302: (umod:HI (match_operand:SI 1 "general_operand" "0")
2303: (match_operand:HI 2 "general_operand" "dmn")))]
2304: ""
2305: "*
2306: {
2307: /* The swap insn produces cc's that don't correspond to the result. */
2308: CC_STATUS_INIT;
2309: #ifdef MOTOROLA
2310: #ifdef SGS_3B1
2311: return \"divu.w %2,%0\;swap.w %0\";
2312: #else
2313: return \"divu.w %2,%0\;swap %0\";
2314: #endif
2315: #else
2316: return \"divu %2,%0\;swap %0\";
2317: #endif
2318: }")
2319:
2320: (define_insn "divmodsi4"
2321: [(set (match_operand:SI 0 "general_operand" "=d")
2322: (div:SI (match_operand:SI 1 "general_operand" "0")
2323: (match_operand:SI 2 "general_operand" "dmsK")))
2324: (set (match_operand:SI 3 "general_operand" "=d")
2325: (mod:SI (match_dup 1) (match_dup 2)))]
2326: "TARGET_68020"
2327: "divsl%.l %2,%3:%0")
2328:
2329: (define_insn "udivmodsi4"
2330: [(set (match_operand:SI 0 "general_operand" "=d")
2331: (udiv:SI (match_operand:SI 1 "general_operand" "0")
2332: (match_operand:SI 2 "general_operand" "dmsK")))
2333: (set (match_operand:SI 3 "general_operand" "=d")
2334: (umod:SI (match_dup 1) (match_dup 2)))]
2335: "TARGET_68020"
2336: "divul%.l %2,%3:%0")
2337:
2338: ;; logical-and instructions
2339:
2340: (define_insn "andsi3"
2341: [(set (match_operand:SI 0 "general_operand" "=m,d")
2342: (and:SI (match_operand:SI 1 "general_operand" "%0,0")
2343: (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
2344: ""
2345: "*
2346: {
2347: if (GET_CODE (operands[2]) == CONST_INT
2348: && (INTVAL (operands[2]) | 0xffff) == 0xffffffff
2349: && (DATA_REG_P (operands[0])
2350: || offsettable_memref_p (operands[0])))
2351: {
2352: if (GET_CODE (operands[0]) != REG)
2353: operands[0] = adj_offsettable_operand (operands[0], 2);
2354: operands[2] = gen_rtx (CONST_INT, VOIDmode,
2355: INTVAL (operands[2]) & 0xffff);
2356: /* Do not delete a following tstl %0 insn; that would be incorrect. */
2357: CC_STATUS_INIT;
2358: if (operands[2] == const0_rtx)
2359: return \"clr%.w %0\";
2360: return \"and%.w %2,%0\";
2361: }
2362: return \"and%.l %2,%0\";
2363: }")
2364:
2365: (define_insn "andhi3"
2366: [(set (match_operand:HI 0 "general_operand" "=m,d")
2367: (and:HI (match_operand:HI 1 "general_operand" "%0,0")
2368: (match_operand:HI 2 "general_operand" "dn,dmn")))]
2369: ""
2370: "and%.w %2,%0")
2371:
2372: (define_insn "andqi3"
2373: [(set (match_operand:QI 0 "general_operand" "=m,d")
2374: (and:QI (match_operand:QI 1 "general_operand" "%0,0")
2375: (match_operand:QI 2 "general_operand" "dn,dmn")))]
2376: ""
2377: "and%.b %2,%0")
2378:
2379: (define_insn ""
2380: [(set (match_operand:SI 0 "general_operand" "=d")
2381: (and:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "dm"))
2382: (match_operand:SI 2 "general_operand" "0")))]
2383: "GET_CODE (operands[2]) == CONST_INT
2384: && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (HImode))"
2385: "and%.w %1,%0")
2386:
2387: (define_insn ""
2388: [(set (match_operand:SI 0 "general_operand" "=d")
2389: (and:SI (zero_extend:SI (match_operand:QI 1 "general_operand" "dm"))
2390: (match_operand:SI 2 "general_operand" "0")))]
2391: "GET_CODE (operands[2]) == CONST_INT
2392: && (unsigned int) INTVAL (operands[2]) < (1 << GET_MODE_BITSIZE (QImode))"
2393: "and%.b %1,%0")
2394:
2395: ;; inclusive-or instructions
2396:
2397: (define_insn "iorsi3"
2398: [(set (match_operand:SI 0 "general_operand" "=m,d")
2399: (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
2400: (match_operand:SI 2 "general_operand" "dKs,dmKs")))]
2401: ""
2402: "*
2403: {
2404: register int logval;
2405: if (GET_CODE (operands[2]) == CONST_INT
2406: && INTVAL (operands[2]) >> 16 == 0
2407: && (DATA_REG_P (operands[0])
2408: || offsettable_memref_p (operands[0])))
2409: {
2410: if (GET_CODE (operands[0]) != REG)
2411: operands[0] = adj_offsettable_operand (operands[0], 2);
2412: /* Do not delete a following tstl %0 insn; that would be incorrect. */
2413: CC_STATUS_INIT;
2414: return \"or%.w %2,%0\";
2415: }
2416: if (GET_CODE (operands[2]) == CONST_INT
2417: && (logval = exact_log2 (INTVAL (operands[2]))) >= 0
2418: && (DATA_REG_P (operands[0])
2419: || offsettable_memref_p (operands[0])))
2420: {
2421: if (DATA_REG_P (operands[0]))
2422: {
2423: operands[1] = gen_rtx (CONST_INT, VOIDmode, logval);
2424: }
2425: else
2426: {
2427: operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
2428: operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
2429: }
2430: return \"bset %1,%0\";
2431: }
2432: return \"or%.l %2,%0\";
2433: }")
2434:
2435: (define_insn "iorhi3"
2436: [(set (match_operand:HI 0 "general_operand" "=m,d")
2437: (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
2438: (match_operand:HI 2 "general_operand" "dn,dmn")))]
2439: ""
2440: "or%.w %2,%0")
2441:
2442: (define_insn "iorqi3"
2443: [(set (match_operand:QI 0 "general_operand" "=m,d")
2444: (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
2445: (match_operand:QI 2 "general_operand" "dn,dmn")))]
2446: ""
2447: "or%.b %2,%0")
2448:
2449: ;; xor instructions
2450:
2451: (define_insn "xorsi3"
2452: [(set (match_operand:SI 0 "general_operand" "=do,m")
2453: (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
2454: (match_operand:SI 2 "general_operand" "di,dKs")))]
2455: ""
2456: "*
2457: {
2458: if (GET_CODE (operands[2]) == CONST_INT
2459: && INTVAL (operands[2]) >> 16 == 0
2460: && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])))
2461: {
2462: if (! DATA_REG_P (operands[0]))
2463: operands[0] = adj_offsettable_operand (operands[0], 2);
2464: /* Do not delete a following tstl %0 insn; that would be incorrect. */
2465: CC_STATUS_INIT;
2466: return \"eor%.w %2,%0\";
2467: }
2468: return \"eor%.l %2,%0\";
2469: }")
2470:
2471: (define_insn "xorhi3"
2472: [(set (match_operand:HI 0 "general_operand" "=dm")
2473: (xor:HI (match_operand:HI 1 "general_operand" "%0")
2474: (match_operand:HI 2 "general_operand" "dn")))]
2475: ""
2476: "eor%.w %2,%0")
2477:
2478: (define_insn "xorqi3"
2479: [(set (match_operand:QI 0 "general_operand" "=dm")
2480: (xor:QI (match_operand:QI 1 "general_operand" "%0")
2481: (match_operand:QI 2 "general_operand" "dn")))]
2482: ""
2483: "eor%.b %2,%0")
2484:
2485: ;; negation instructions
2486:
2487: (define_insn "negsi2"
2488: [(set (match_operand:SI 0 "general_operand" "=dm")
2489: (neg:SI (match_operand:SI 1 "general_operand" "0")))]
2490: ""
2491: "neg%.l %0")
2492:
2493: (define_insn "neghi2"
2494: [(set (match_operand:HI 0 "general_operand" "=dm")
2495: (neg:HI (match_operand:HI 1 "general_operand" "0")))]
2496: ""
2497: "neg%.w %0")
2498:
2499: (define_insn "negqi2"
2500: [(set (match_operand:QI 0 "general_operand" "=dm")
2501: (neg:QI (match_operand:QI 1 "general_operand" "0")))]
2502: ""
2503: "neg%.b %0")
2504:
2505: (define_expand "negsf2"
2506: [(set (match_operand:SF 0 "general_operand" "")
2507: (neg:SF (match_operand:SF 1 "general_operand" "")))]
2508: "TARGET_68881 || TARGET_FPA"
2509: "")
2510:
2511: (define_insn ""
2512: [(set (match_operand:SF 0 "general_operand" "=x,y")
2513: (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
2514: "TARGET_FPA"
2515: "fpneg%.s %w1,%0")
2516:
2517: (define_insn ""
2518: [(set (match_operand:SF 0 "general_operand" "=f")
2519: (neg:SF (match_operand:SF 1 "general_operand" "fdmF")))]
2520: "TARGET_68881"
2521: "*
2522: {
2523: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
2524: return \"fneg%.x %1,%0\";
2525: return \"fneg%.s %f1,%0\";
2526: }")
2527:
2528: (define_expand "negdf2"
2529: [(set (match_operand:DF 0 "general_operand" "")
2530: (neg:DF (match_operand:DF 1 "general_operand" "")))]
2531: "TARGET_68881 || TARGET_FPA"
2532: "")
2533:
2534: (define_insn ""
2535: [(set (match_operand:DF 0 "general_operand" "=x,y")
2536: (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
2537: "TARGET_FPA"
2538: "fpneg%.d %y1, %0")
2539:
2540: (define_insn ""
2541: [(set (match_operand:DF 0 "general_operand" "=f")
2542: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
2543: "TARGET_68881"
2544: "*
2545: {
2546: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
2547: return \"fneg%.x %1,%0\";
2548: return \"fneg%.d %f1,%0\";
2549: }")
2550:
2551: ;; Absolute value instructions
2552:
2553: (define_expand "abssf2"
2554: [(set (match_operand:SF 0 "general_operand" "")
2555: (abs:SF (match_operand:SF 1 "general_operand" "")))]
2556: "TARGET_68881 || TARGET_FPA"
2557: "")
2558:
2559: (define_insn ""
2560: [(set (match_operand:SF 0 "general_operand" "=x,y")
2561: (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
2562: "TARGET_FPA"
2563: "fpabs%.s %y1,%0")
2564:
2565: (define_insn ""
2566: [(set (match_operand:SF 0 "general_operand" "=f")
2567: (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
2568: "TARGET_68881"
2569: "*
2570: {
2571: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
2572: return \"fabs%.x %1,%0\";
2573: return \"fabs%.s %f1,%0\";
2574: }")
2575:
2576: (define_expand "absdf2"
2577: [(set (match_operand:DF 0 "general_operand" "")
2578: (abs:DF (match_operand:DF 1 "general_operand" "")))]
2579: "TARGET_68881 || TARGET_FPA"
2580: "")
2581:
2582: (define_insn ""
2583: [(set (match_operand:DF 0 "general_operand" "=x,y")
2584: (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
2585: "TARGET_FPA"
2586: "fpabs%.d %y1,%0")
2587:
2588: (define_insn ""
2589: [(set (match_operand:DF 0 "general_operand" "=f")
2590: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2591: "TARGET_68881"
2592: "*
2593: {
2594: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
2595: return \"fabs%.x %1,%0\";
2596: return \"fabs%.d %f1,%0\";
2597: }")
2598:
2599: ;; one complement instructions
2600:
2601: (define_insn "one_cmplsi2"
2602: [(set (match_operand:SI 0 "general_operand" "=dm")
2603: (not:SI (match_operand:SI 1 "general_operand" "0")))]
2604: ""
2605: "not%.l %0")
2606:
2607: (define_insn "one_cmplhi2"
2608: [(set (match_operand:HI 0 "general_operand" "=dm")
2609: (not:HI (match_operand:HI 1 "general_operand" "0")))]
2610: ""
2611: "not%.w %0")
2612:
2613: (define_insn "one_cmplqi2"
2614: [(set (match_operand:QI 0 "general_operand" "=dm")
2615: (not:QI (match_operand:QI 1 "general_operand" "0")))]
2616: ""
2617: "not%.b %0")
2618:
2619: ;; Optimized special case of shifting.
2620: ;; Must precede the general case.
2621:
2622: (define_insn ""
2623: [(set (match_operand:SI 0 "general_operand" "=d")
2624: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
2625: (const_int 24)))]
2626: "GET_CODE (XEXP (operands[1], 0)) != POST_INC
2627: && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
2628: "*
2629: {
2630: if (TARGET_68020)
2631: return \"move%.b %1,%0\;extb%.l %0\";
2632: return \"move%.b %1,%0\;ext%.w %0\;ext%.l %0\";
2633: }")
2634:
2635: (define_insn ""
2636: [(set (match_operand:SI 0 "general_operand" "=d")
2637: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
2638: (const_int 24)))]
2639: "GET_CODE (XEXP (operands[1], 0)) != POST_INC
2640: && GET_CODE (XEXP (operands[1], 0)) != PRE_DEC"
2641: "*
2642: {
2643: if (reg_mentioned_p (operands[0], operands[1]))
2644: return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
2645: return \"clr%.l %0\;move%.b %1,%0\";
2646: }")
2647:
2648: (define_insn ""
2649: [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
2650: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
2651: (const_int 24))))]
2652: "(GET_CODE (operands[0]) == CONST_INT
2653: && (INTVAL (operands[0]) & ~0xff) == 0)"
2654: "* cc_status.flags |= CC_REVERSED;
2655: #ifdef HPUX_ASM
2656: return \"cmp%.b %1,%0\";
2657: #else
2658: return \"cmp%.b %0,%1\";
2659: #endif
2660: ")
2661:
2662: (define_insn ""
2663: [(set (cc0) (compare (lshiftrt:SI (match_operand:SI 0 "memory_operand" "m")
2664: (const_int 24))
2665: (match_operand:QI 1 "general_operand" "i")))]
2666: "(GET_CODE (operands[1]) == CONST_INT
2667: && (INTVAL (operands[1]) & ~0xff) == 0)"
2668: "*
2669: #ifdef HPUX_ASM
2670: return \"cmp%.b %0,%1\";
2671: #else
2672: return \"cmp%.b %1,%0\";
2673: #endif
2674: ")
2675:
2676: (define_insn ""
2677: [(set (cc0) (compare (match_operand:QI 0 "general_operand" "i")
2678: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
2679: (const_int 24))))]
2680: "(GET_CODE (operands[0]) == CONST_INT
2681: && ((INTVAL (operands[0]) + 0x80) & ~0xff) == 0)"
2682: "* cc_status.flags |= CC_REVERSED;
2683: #ifdef HPUX_ASM
2684: return \"cmp%.b %1,%0\";
2685: #else
2686: return \"cmp%.b %0,%1\";
2687: #endif
2688: ")
2689:
2690: (define_insn ""
2691: [(set (cc0) (compare (ashiftrt:SI (match_operand:SI 0 "memory_operand" "m")
2692: (const_int 24))
2693: (match_operand:QI 1 "general_operand" "i")))]
2694: "(GET_CODE (operands[1]) == CONST_INT
2695: && ((INTVAL (operands[1]) + 0x80) & ~0xff) == 0)"
2696: "*
2697: #ifdef HPUX_ASM
2698: return \"cmp%.b %0,%1\";
2699: #else
2700: return \"cmp%.b %1,%0\";
2701: #endif
2702: ")
2703:
2704: ;; arithmetic shift instructions
2705: ;; We don't need the shift memory by 1 bit instruction
2706:
2707: (define_insn "ashlsi3"
2708: [(set (match_operand:SI 0 "general_operand" "=d")
2709: (ashift:SI (match_operand:SI 1 "general_operand" "0")
2710: (match_operand:SI 2 "general_operand" "dI")))]
2711: ""
2712: "asl%.l %2,%0")
2713:
2714: (define_insn "ashlhi3"
2715: [(set (match_operand:HI 0 "general_operand" "=d")
2716: (ashift:HI (match_operand:HI 1 "general_operand" "0")
2717: (match_operand:HI 2 "general_operand" "dI")))]
2718: ""
2719: "asl%.w %2,%0")
2720:
2721: (define_insn "ashlqi3"
2722: [(set (match_operand:QI 0 "general_operand" "=d")
2723: (ashift:QI (match_operand:QI 1 "general_operand" "0")
2724: (match_operand:QI 2 "general_operand" "dI")))]
2725: ""
2726: "asl%.b %2,%0")
2727:
2728: (define_insn "ashrsi3"
2729: [(set (match_operand:SI 0 "general_operand" "=d")
2730: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
2731: (match_operand:SI 2 "general_operand" "dI")))]
2732: ""
2733: "asr%.l %2,%0")
2734:
2735: (define_insn "ashrhi3"
2736: [(set (match_operand:HI 0 "general_operand" "=d")
2737: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
2738: (match_operand:HI 2 "general_operand" "dI")))]
2739: ""
2740: "asr%.w %2,%0")
2741:
2742: (define_insn "ashrqi3"
2743: [(set (match_operand:QI 0 "general_operand" "=d")
2744: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
2745: (match_operand:QI 2 "general_operand" "dI")))]
2746: ""
2747: "asr%.b %2,%0")
2748:
2749: ;; logical shift instructions
2750:
2751: (define_insn "lshlsi3"
2752: [(set (match_operand:SI 0 "general_operand" "=d")
2753: (lshift:SI (match_operand:SI 1 "general_operand" "0")
2754: (match_operand:SI 2 "general_operand" "dI")))]
2755: ""
2756: "lsl%.l %2,%0")
2757:
2758: (define_insn "lshlhi3"
2759: [(set (match_operand:HI 0 "general_operand" "=d")
2760: (lshift:HI (match_operand:HI 1 "general_operand" "0")
2761: (match_operand:HI 2 "general_operand" "dI")))]
2762: ""
2763: "lsl%.w %2,%0")
2764:
2765: (define_insn "lshlqi3"
2766: [(set (match_operand:QI 0 "general_operand" "=d")
2767: (lshift:QI (match_operand:QI 1 "general_operand" "0")
2768: (match_operand:QI 2 "general_operand" "dI")))]
2769: ""
2770: "lsl%.b %2,%0")
2771:
2772: (define_insn "lshrsi3"
2773: [(set (match_operand:SI 0 "general_operand" "=d")
2774: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
2775: (match_operand:SI 2 "general_operand" "dI")))]
2776: ""
2777: "lsr%.l %2,%0")
2778:
2779: (define_insn "lshrhi3"
2780: [(set (match_operand:HI 0 "general_operand" "=d")
2781: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
2782: (match_operand:HI 2 "general_operand" "dI")))]
2783: ""
2784: "lsr%.w %2,%0")
2785:
2786: (define_insn "lshrqi3"
2787: [(set (match_operand:QI 0 "general_operand" "=d")
2788: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
2789: (match_operand:QI 2 "general_operand" "dI")))]
2790: ""
2791: "lsr%.b %2,%0")
2792:
2793: ;; rotate instructions
2794:
2795: (define_insn "rotlsi3"
2796: [(set (match_operand:SI 0 "general_operand" "=d")
2797: (rotate:SI (match_operand:SI 1 "general_operand" "0")
2798: (match_operand:SI 2 "general_operand" "dI")))]
2799: ""
2800: "rol%.l %2,%0")
2801:
2802: (define_insn "rotlhi3"
2803: [(set (match_operand:HI 0 "general_operand" "=d")
2804: (rotate:HI (match_operand:HI 1 "general_operand" "0")
2805: (match_operand:HI 2 "general_operand" "dI")))]
2806: ""
2807: "rol%.w %2,%0")
2808:
2809: (define_insn "rotlqi3"
2810: [(set (match_operand:QI 0 "general_operand" "=d")
2811: (rotate:QI (match_operand:QI 1 "general_operand" "0")
2812: (match_operand:QI 2 "general_operand" "dI")))]
2813: ""
2814: "rol%.b %2,%0")
2815:
2816: (define_insn "rotrsi3"
2817: [(set (match_operand:SI 0 "general_operand" "=d")
2818: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
2819: (match_operand:SI 2 "general_operand" "dI")))]
2820: ""
2821: "ror%.l %2,%0")
2822:
2823: (define_insn "rotrhi3"
2824: [(set (match_operand:HI 0 "general_operand" "=d")
2825: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
2826: (match_operand:HI 2 "general_operand" "dI")))]
2827: ""
2828: "ror%.w %2,%0")
2829:
2830: (define_insn "rotrqi3"
2831: [(set (match_operand:QI 0 "general_operand" "=d")
2832: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
2833: (match_operand:QI 2 "general_operand" "dI")))]
2834: ""
2835: "ror%.b %2,%0")
2836:
2837: ;; Special cases of bit-field insns which we should
2838: ;; recognize in preference to the general case.
2839: ;; These handle aligned 8-bit and 16-bit fields,
2840: ;; which can usually be done with move instructions.
2841:
2842: (define_insn ""
2843: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do")
2844: (match_operand:SI 1 "immediate_operand" "i")
2845: (match_operand:SI 2 "immediate_operand" "i"))
2846: (match_operand:SI 3 "general_operand" "d"))]
2847: "TARGET_68020 && TARGET_BITFIELD
2848: && GET_CODE (operands[1]) == CONST_INT
2849: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
2850: && GET_CODE (operands[2]) == CONST_INT
2851: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
2852: && (GET_CODE (operands[0]) == REG
2853: || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
2854: "*
2855: {
2856: if (REG_P (operands[0]))
2857: {
2858: if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
2859: return \"bfins %3,%0{%b2:%b1}\";
2860: }
2861: else
2862: operands[0]
2863: = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
2864:
2865: if (GET_CODE (operands[3]) == MEM)
2866: operands[3] = adj_offsettable_operand (operands[3],
2867: (32 - INTVAL (operands[1])) / 8);
2868: if (INTVAL (operands[1]) == 8)
2869: return \"move%.b %3,%0\";
2870: return \"move%.w %3,%0\";
2871: }")
2872:
2873: (define_insn ""
2874: [(set (match_operand:SI 0 "general_operand" "=&d")
2875: (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
2876: (match_operand:SI 2 "immediate_operand" "i")
2877: (match_operand:SI 3 "immediate_operand" "i")))]
2878: "TARGET_68020 && TARGET_BITFIELD
2879: && GET_CODE (operands[2]) == CONST_INT
2880: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2881: && GET_CODE (operands[3]) == CONST_INT
2882: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
2883: && (GET_CODE (operands[1]) == REG
2884: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
2885: "*
2886: {
1.1.1.3 root 2887: cc_status.flags |= CC_NOT_NEGATIVE;
1.1 root 2888: if (REG_P (operands[1]))
2889: {
2890: if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
2891: return \"bfextu %1{%b3:%b2},%0\";
2892: }
2893: else
2894: operands[1]
2895: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
2896:
2897: output_asm_insn (\"clr%.l %0\", operands);
2898: if (GET_CODE (operands[0]) == MEM)
2899: operands[0] = adj_offsettable_operand (operands[0],
2900: (32 - INTVAL (operands[1])) / 8);
2901: if (INTVAL (operands[2]) == 8)
2902: return \"move%.b %1,%0\";
2903: return \"move%.w %1,%0\";
2904: }")
2905:
2906: (define_insn ""
2907: [(set (match_operand:SI 0 "general_operand" "=d")
2908: (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
2909: (match_operand:SI 2 "immediate_operand" "i")
2910: (match_operand:SI 3 "immediate_operand" "i")))]
2911: "TARGET_68020 && TARGET_BITFIELD
2912: && GET_CODE (operands[2]) == CONST_INT
2913: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
2914: && GET_CODE (operands[3]) == CONST_INT
2915: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
2916: && (GET_CODE (operands[1]) == REG
2917: || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
2918: "*
2919: {
2920: if (REG_P (operands[1]))
2921: {
2922: if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
2923: return \"bfexts %1{%b3:%b2},%0\";
2924: }
2925: else
2926: operands[1]
2927: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
2928:
2929: if (INTVAL (operands[2]) == 8)
2930: return \"move%.b %1,%0\;extb%.l %0\";
2931: return \"move%.w %1,%0\;ext%.l %0\";
2932: }")
2933:
2934: ;; Bit field instructions, general cases.
2935: ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
2936: ;; so that its address is reloaded.
2937:
2938: (define_insn "extv"
2939: [(set (match_operand:SI 0 "general_operand" "=d,d")
2940: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
2941: (match_operand:SI 2 "general_operand" "di,di")
2942: (match_operand:SI 3 "general_operand" "di,di")))]
2943: "TARGET_68020 && TARGET_BITFIELD"
2944: "bfexts %1{%b3:%b2},%0")
2945:
2946: (define_insn "extzv"
2947: [(set (match_operand:SI 0 "general_operand" "=d,d")
2948: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d")
2949: (match_operand:SI 2 "general_operand" "di,di")
2950: (match_operand:SI 3 "general_operand" "di,di")))]
2951: "TARGET_68020 && TARGET_BITFIELD"
1.1.1.3 root 2952: "*
2953: {
2954: cc_status.flags |= CC_NOT_NEGATIVE;
2955: return \"bfextu %1{%b3:%b2},%0\";
2956: }")
1.1 root 2957:
2958: (define_insn ""
2959: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
2960: (match_operand:SI 1 "general_operand" "di,di")
2961: (match_operand:SI 2 "general_operand" "di,di"))
2962: (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
2963: (match_operand 3 "immediate_operand" "i,i")))]
2964: "TARGET_68020 && TARGET_BITFIELD
2965: && GET_CODE (operands[3]) == CONST_INT
2966: && (INTVAL (operands[3]) == -1
2967: || (GET_CODE (operands[1]) == CONST_INT
2968: && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
2969: "*
2970: {
2971: CC_STATUS_INIT;
2972: return \"bfchg %0{%b2:%b1}\";
2973: }")
2974:
2975: (define_insn ""
2976: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
2977: (match_operand:SI 1 "general_operand" "di,di")
2978: (match_operand:SI 2 "general_operand" "di,di"))
2979: (const_int 0))]
2980: "TARGET_68020 && TARGET_BITFIELD"
2981: "*
2982: {
2983: CC_STATUS_INIT;
2984: return \"bfclr %0{%b2:%b1}\";
2985: }")
2986:
2987: (define_insn ""
2988: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
2989: (match_operand:SI 1 "general_operand" "di,di")
2990: (match_operand:SI 2 "general_operand" "di,di"))
2991: (const_int -1))]
2992: "TARGET_68020 && TARGET_BITFIELD"
2993: "*
2994: {
2995: CC_STATUS_INIT;
2996: return \"bfset %0{%b2:%b1}\";
2997: }")
2998:
2999: (define_insn "insv"
3000: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
3001: (match_operand:SI 1 "general_operand" "di,di")
3002: (match_operand:SI 2 "general_operand" "di,di"))
3003: (match_operand:SI 3 "general_operand" "d,d"))]
3004: "TARGET_68020 && TARGET_BITFIELD"
3005: "bfins %3,%0{%b2:%b1}")
3006:
3007: ;; Now recognize bit field insns that operate on registers
3008: ;; (or at least were intended to do so).
3009:
3010: (define_insn ""
3011: [(set (match_operand:SI 0 "general_operand" "=d")
3012: (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
3013: (match_operand:SI 2 "general_operand" "di")
3014: (match_operand:SI 3 "general_operand" "di")))]
3015: "TARGET_68020 && TARGET_BITFIELD"
3016: "bfexts %1{%b3:%b2},%0")
3017:
3018: (define_insn ""
3019: [(set (match_operand:SI 0 "general_operand" "=d")
3020: (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d")
3021: (match_operand:SI 2 "general_operand" "di")
3022: (match_operand:SI 3 "general_operand" "di")))]
3023: "TARGET_68020 && TARGET_BITFIELD"
1.1.1.3 root 3024: "*
3025: {
3026: cc_status.flags |= CC_NOT_NEGATIVE;
3027: return \"bfextu %1{%b3:%b2},%0\";
3028: }")
1.1 root 3029:
3030: (define_insn ""
3031: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
3032: (match_operand:SI 1 "general_operand" "di")
3033: (match_operand:SI 2 "general_operand" "di"))
3034: (const_int 0))]
3035: "TARGET_68020 && TARGET_BITFIELD"
3036: "*
3037: {
3038: CC_STATUS_INIT;
3039: return \"bfclr %0{%b2:%b1}\";
3040: }")
3041:
3042: (define_insn ""
3043: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
3044: (match_operand:SI 1 "general_operand" "di")
3045: (match_operand:SI 2 "general_operand" "di"))
3046: (const_int -1))]
3047: "TARGET_68020 && TARGET_BITFIELD"
3048: "*
3049: {
3050: CC_STATUS_INIT;
3051: return \"bfset %0{%b2:%b1}\";
3052: }")
3053:
3054: (define_insn ""
3055: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
3056: (match_operand:SI 1 "general_operand" "di")
3057: (match_operand:SI 2 "general_operand" "di"))
3058: (match_operand:SI 3 "general_operand" "d"))]
3059: "TARGET_68020 && TARGET_BITFIELD"
3060: "*
3061: {
3062: #if 0
3063: /* These special cases are now recognized by a specific pattern. */
3064: if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
3065: && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
3066: return \"move%.w %3,%0\";
3067: if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
3068: && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
3069: return \"move%.b %3,%0\";
3070: #endif
3071: return \"bfins %3,%0{%b2:%b1}\";
3072: }")
3073:
3074: ;; Special patterns for optimizing bit-field instructions.
3075:
3076: (define_insn ""
3077: [(set (cc0)
3078: (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
3079: (match_operand:SI 1 "general_operand" "di")
3080: (match_operand:SI 2 "general_operand" "di")))]
3081: "TARGET_68020 && TARGET_BITFIELD
3082: && GET_CODE (operands[1]) == CONST_INT"
3083: "*
3084: {
3085: if (operands[1] == const1_rtx
3086: && GET_CODE (operands[2]) == CONST_INT)
3087: {
3088: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
3089: return output_btst (operands,
3090: gen_rtx (CONST_INT, VOIDmode,
3091: width - INTVAL (operands[2])),
3092: operands[0],
3093: insn, 1000);
3094: /* Pass 1000 as SIGNPOS argument so that btst will
3095: not think we are testing the sign bit for an `and'
3096: and assume that nonzero implies a negative result. */
3097: }
3098: if (INTVAL (operands[1]) != 32)
3099: cc_status.flags = CC_NOT_NEGATIVE;
3100: return \"bftst %0{%b2:%b1}\";
3101: }")
3102:
3103: (define_insn ""
3104: [(set (cc0)
3105: (subreg:QI
3106: (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
3107: (match_operand:SI 1 "general_operand" "di")
3108: (match_operand:SI 2 "general_operand" "di"))
3109: 0))]
3110: "TARGET_68020 && TARGET_BITFIELD
3111: && GET_CODE (operands[1]) == CONST_INT"
3112: "*
3113: {
3114: if (operands[1] == const1_rtx
3115: && GET_CODE (operands[2]) == CONST_INT)
3116: {
3117: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
3118: return output_btst (operands,
3119: gen_rtx (CONST_INT, VOIDmode,
3120: width - INTVAL (operands[2])),
3121: operands[0],
3122: insn, 1000);
3123: /* Pass 1000 as SIGNPOS argument so that btst will
3124: not think we are testing the sign bit for an `and'
3125: and assume that nonzero implies a negative result. */
3126: }
3127: if (INTVAL (operands[1]) != 32)
3128: cc_status.flags = CC_NOT_NEGATIVE;
3129: return \"bftst %0{%b2:%b1}\";
3130: }")
3131:
3132: (define_insn ""
3133: [(set (cc0)
3134: (subreg:HI
3135: (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
3136: (match_operand:SI 1 "general_operand" "di")
3137: (match_operand:SI 2 "general_operand" "di"))
3138: 0))]
3139: "TARGET_68020 && TARGET_BITFIELD
3140: && GET_CODE (operands[1]) == CONST_INT"
3141: "*
3142: {
3143: if (operands[1] == const1_rtx
3144: && GET_CODE (operands[2]) == CONST_INT)
3145: {
3146: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
3147: return output_btst (operands,
3148: gen_rtx (CONST_INT, VOIDmode,
3149: width - INTVAL (operands[2])),
3150: operands[0],
3151: insn, 1000);
3152: /* Pass 1000 as SIGNPOS argument so that btst will
3153: not think we are testing the sign bit for an `and'
3154: and assume that nonzero implies a negative result. */
3155: }
3156: if (INTVAL (operands[1]) != 32)
3157: cc_status.flags = CC_NOT_NEGATIVE;
3158: return \"bftst %0{%b2:%b1}\";
3159: }")
3160:
3161: ;;; now handle the register cases
3162: (define_insn ""
3163: [(set (cc0)
3164: (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
3165: (match_operand:SI 1 "general_operand" "di")
3166: (match_operand:SI 2 "general_operand" "di")))]
3167: "TARGET_68020 && TARGET_BITFIELD
3168: && GET_CODE (operands[1]) == CONST_INT"
3169: "*
3170: {
3171: if (operands[1] == const1_rtx
3172: && GET_CODE (operands[2]) == CONST_INT)
3173: {
3174: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
3175: return output_btst (operands,
3176: gen_rtx (CONST_INT, VOIDmode,
3177: width - INTVAL (operands[2])),
3178: operands[0],
3179: insn, 1000);
3180: /* Pass 1000 as SIGNPOS argument so that btst will
3181: not think we are testing the sign bit for an `and'
3182: and assume that nonzero implies a negative result. */
3183: }
3184: if (INTVAL (operands[1]) != 32)
3185: cc_status.flags = CC_NOT_NEGATIVE;
3186: return \"bftst %0{%b2:%b1}\";
3187: }")
3188:
3189: (define_insn ""
3190: [(set (cc0)
3191: (subreg:QI
3192: (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
3193: (match_operand:SI 1 "general_operand" "di")
3194: (match_operand:SI 2 "general_operand" "di"))
3195: 0))]
3196: "TARGET_68020 && TARGET_BITFIELD
3197: && GET_CODE (operands[1]) == CONST_INT"
3198: "*
3199: {
3200: if (operands[1] == const1_rtx
3201: && GET_CODE (operands[2]) == CONST_INT)
3202: {
3203: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
3204: return output_btst (operands,
3205: gen_rtx (CONST_INT, VOIDmode,
3206: width - INTVAL (operands[2])),
3207: operands[0],
3208: insn, 1000);
3209: /* Pass 1000 as SIGNPOS argument so that btst will
3210: not think we are testing the sign bit for an `and'
3211: and assume that nonzero implies a negative result. */
3212: }
3213: if (INTVAL (operands[1]) != 32)
3214: cc_status.flags = CC_NOT_NEGATIVE;
3215: return \"bftst %0{%b2:%b1}\";
3216: }")
3217:
3218: (define_insn ""
3219: [(set (cc0)
3220: (subreg:HI
3221: (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
3222: (match_operand:SI 1 "general_operand" "di")
3223: (match_operand:SI 2 "general_operand" "di"))
3224: 0))]
3225: "TARGET_68020 && TARGET_BITFIELD
3226: && GET_CODE (operands[1]) == CONST_INT"
3227: "*
3228: {
3229: if (operands[1] == const1_rtx
3230: && GET_CODE (operands[2]) == CONST_INT)
3231: {
3232: int width = GET_CODE (operands[0]) == REG ? 31 : 7;
3233: return output_btst (operands,
3234: gen_rtx (CONST_INT, VOIDmode,
3235: width - INTVAL (operands[2])),
3236: operands[0],
3237: insn, 1000);
3238: /* Pass 1000 as SIGNPOS argument so that btst will
3239: not think we are testing the sign bit for an `and'
3240: and assume that nonzero implies a negative result. */
3241: }
3242: if (INTVAL (operands[1]) != 32)
3243: cc_status.flags = CC_NOT_NEGATIVE;
3244: return \"bftst %0{%b2:%b1}\";
3245: }")
3246:
3247: (define_insn "seq"
3248: [(set (match_operand:QI 0 "general_operand" "=d")
3249: (eq (cc0) (const_int 0)))]
3250: ""
3251: "*
3252: cc_status = cc_prev_status;
3253: OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
3254: ")
3255:
3256: (define_insn "sne"
3257: [(set (match_operand:QI 0 "general_operand" "=d")
3258: (ne (cc0) (const_int 0)))]
3259: ""
3260: "*
3261: cc_status = cc_prev_status;
3262: OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
3263: ")
3264:
3265: (define_insn "sgt"
3266: [(set (match_operand:QI 0 "general_operand" "=d")
3267: (gt (cc0) (const_int 0)))]
3268: ""
3269: "*
3270: cc_status = cc_prev_status;
3271: OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
3272: ")
3273:
3274: (define_insn "sgtu"
3275: [(set (match_operand:QI 0 "general_operand" "=d")
3276: (gtu (cc0) (const_int 0)))]
3277: ""
3278: "* cc_status = cc_prev_status;
3279: return \"shi %0\"; ")
3280:
3281: (define_insn "slt"
3282: [(set (match_operand:QI 0 "general_operand" "=d")
3283: (lt (cc0) (const_int 0)))]
3284: ""
3285: "* cc_status = cc_prev_status;
3286: OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
3287:
3288: (define_insn "sltu"
3289: [(set (match_operand:QI 0 "general_operand" "=d")
3290: (ltu (cc0) (const_int 0)))]
3291: ""
3292: "* cc_status = cc_prev_status;
3293: return \"scs %0\"; ")
3294:
3295: (define_insn "sge"
3296: [(set (match_operand:QI 0 "general_operand" "=d")
3297: (ge (cc0) (const_int 0)))]
3298: ""
3299: "* cc_status = cc_prev_status;
3300: OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
3301:
3302: (define_insn "sgeu"
3303: [(set (match_operand:QI 0 "general_operand" "=d")
3304: (geu (cc0) (const_int 0)))]
3305: ""
3306: "* cc_status = cc_prev_status;
3307: return \"scc %0\"; ")
3308:
3309: (define_insn "sle"
3310: [(set (match_operand:QI 0 "general_operand" "=d")
3311: (le (cc0) (const_int 0)))]
3312: ""
3313: "*
3314: cc_status = cc_prev_status;
3315: OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
3316: ")
3317:
3318: (define_insn "sleu"
3319: [(set (match_operand:QI 0 "general_operand" "=d")
3320: (leu (cc0) (const_int 0)))]
3321: ""
3322: "* cc_status = cc_prev_status;
3323: return \"sls %0\"; ")
3324:
3325: ;; Basic conditional jump instructions.
3326:
3327: (define_insn "beq"
3328: [(set (pc)
3329: (if_then_else (eq (cc0)
3330: (const_int 0))
3331: (label_ref (match_operand 0 "" ""))
3332: (pc)))]
3333: ""
3334: "*
3335: {
3336: #ifdef MOTOROLA
3337: OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
3338: #else
3339: OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
3340: #endif
3341: }")
3342:
3343: (define_insn "bne"
3344: [(set (pc)
3345: (if_then_else (ne (cc0)
3346: (const_int 0))
3347: (label_ref (match_operand 0 "" ""))
3348: (pc)))]
3349: ""
3350: "*
3351: {
3352: #ifdef MOTOROLA
3353: OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
3354: #else
3355: OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
3356: #endif
3357: }")
3358:
3359: (define_insn "bgt"
3360: [(set (pc)
3361: (if_then_else (gt (cc0)
3362: (const_int 0))
3363: (label_ref (match_operand 0 "" ""))
3364: (pc)))]
3365: ""
3366: "*
3367: #ifdef MOTOROLA
3368: OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
3369: #else
3370: OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
3371: #endif
3372: ")
3373:
3374: (define_insn "bgtu"
3375: [(set (pc)
3376: (if_then_else (gtu (cc0)
3377: (const_int 0))
3378: (label_ref (match_operand 0 "" ""))
3379: (pc)))]
3380: ""
3381: "*
3382: #ifdef MOTOROLA
3383: return \"jbhi %l0\";
3384: #else
3385: return \"jhi %l0\";
3386: #endif
3387: ")
3388:
3389: (define_insn "blt"
3390: [(set (pc)
3391: (if_then_else (lt (cc0)
3392: (const_int 0))
3393: (label_ref (match_operand 0 "" ""))
3394: (pc)))]
3395: ""
3396: "*
3397: #ifdef MOTOROLA
3398: OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
3399: #else
3400: OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
3401: #endif
3402: ")
3403:
3404: (define_insn "bltu"
3405: [(set (pc)
3406: (if_then_else (ltu (cc0)
3407: (const_int 0))
3408: (label_ref (match_operand 0 "" ""))
3409: (pc)))]
3410: ""
3411: "*
3412: #ifdef MOTOROLA
3413: return \"jbcs %l0\";
3414: #else
3415: return \"jcs %l0\";
3416: #endif
3417: ")
3418:
3419: (define_insn "bge"
3420: [(set (pc)
3421: (if_then_else (ge (cc0)
3422: (const_int 0))
3423: (label_ref (match_operand 0 "" ""))
3424: (pc)))]
3425: ""
3426: "*
3427: #ifdef MOTOROLA
3428: OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
3429: #else
3430: OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
3431: #endif
3432: ")
3433:
3434: (define_insn "bgeu"
3435: [(set (pc)
3436: (if_then_else (geu (cc0)
3437: (const_int 0))
3438: (label_ref (match_operand 0 "" ""))
3439: (pc)))]
3440: ""
3441: "*
3442: #ifdef MOTOROLA
3443: return \"jbcc %l0\";
3444: #else
3445: return \"jcc %l0\";
3446: #endif
3447: ")
3448:
3449: (define_insn "ble"
3450: [(set (pc)
3451: (if_then_else (le (cc0)
3452: (const_int 0))
3453: (label_ref (match_operand 0 "" ""))
3454: (pc)))]
3455: ""
3456: "*
3457: #ifdef MOTOROLA
3458: OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
3459: #else
3460: OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
3461: #endif
3462: ")
3463:
3464: (define_insn "bleu"
3465: [(set (pc)
3466: (if_then_else (leu (cc0)
3467: (const_int 0))
3468: (label_ref (match_operand 0 "" ""))
3469: (pc)))]
3470: ""
3471: "*
3472: #ifdef MOTOROLA
3473: return \"jbls %l0\";
3474: #else
3475: return \"jls %l0\";
3476: #endif
3477: ")
3478:
3479: ;; Negated conditional jump instructions.
3480:
3481: (define_insn ""
3482: [(set (pc)
3483: (if_then_else (eq (cc0)
3484: (const_int 0))
3485: (pc)
3486: (label_ref (match_operand 0 "" ""))))]
3487: ""
3488: "*
3489: {
3490: #ifdef MOTOROLA
3491: OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
3492: #else
3493: OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
3494: #endif
3495: }")
3496:
3497: (define_insn ""
3498: [(set (pc)
3499: (if_then_else (ne (cc0)
3500: (const_int 0))
3501: (pc)
3502: (label_ref (match_operand 0 "" ""))))]
3503: ""
3504: "*
3505: {
3506: #ifdef MOTOROLA
3507: OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
3508: #else
3509: OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
3510: #endif
3511: }")
3512:
3513: (define_insn ""
3514: [(set (pc)
3515: (if_then_else (gt (cc0)
3516: (const_int 0))
3517: (pc)
3518: (label_ref (match_operand 0 "" ""))))]
3519: ""
3520: "*
3521: #ifdef MOTOROLA
3522: OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
3523: #else
3524: OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
3525: #endif
3526: ")
3527:
3528: (define_insn ""
3529: [(set (pc)
3530: (if_then_else (gtu (cc0)
3531: (const_int 0))
3532: (pc)
3533: (label_ref (match_operand 0 "" ""))))]
3534: ""
3535: "*
3536: #ifdef MOTOROLA
3537: return \"jbls %l0\";
3538: #else
3539: return \"jls %l0\";
3540: #endif
3541: ")
3542:
3543: (define_insn ""
3544: [(set (pc)
3545: (if_then_else (lt (cc0)
3546: (const_int 0))
3547: (pc)
3548: (label_ref (match_operand 0 "" ""))))]
3549: ""
3550: "*
3551: #ifdef MOTOROLA
3552: OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
3553: #else
3554: OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
3555: #endif
3556: ")
3557:
3558: (define_insn ""
3559: [(set (pc)
3560: (if_then_else (ltu (cc0)
3561: (const_int 0))
3562: (pc)
3563: (label_ref (match_operand 0 "" ""))))]
3564: ""
3565: "*
3566: #ifdef MOTOROLA
3567: return \"jbcc %l0\";
3568: #else
3569: return \"jcc %l0\";
3570: #endif
3571: ")
3572:
3573: (define_insn ""
3574: [(set (pc)
3575: (if_then_else (ge (cc0)
3576: (const_int 0))
3577: (pc)
3578: (label_ref (match_operand 0 "" ""))))]
3579: ""
3580: "*
3581: #ifdef MOTOROLA
3582: OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
3583: #else
3584: OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
3585: #endif
3586: ")
3587:
3588: (define_insn ""
3589: [(set (pc)
3590: (if_then_else (geu (cc0)
3591: (const_int 0))
3592: (pc)
3593: (label_ref (match_operand 0 "" ""))))]
3594: ""
3595: "*
3596: #ifdef MOTOROLA
3597: return \"jbcs %l0\";
3598: #else
3599: return \"jcs %l0\";
3600: #endif
3601: ")
3602:
3603: (define_insn ""
3604: [(set (pc)
3605: (if_then_else (le (cc0)
3606: (const_int 0))
3607: (pc)
3608: (label_ref (match_operand 0 "" ""))))]
3609: ""
3610: "*
3611: #ifdef MOTOROLA
3612: OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
3613: #else
3614: OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
3615: #endif
3616: ")
3617:
3618: (define_insn ""
3619: [(set (pc)
3620: (if_then_else (leu (cc0)
3621: (const_int 0))
3622: (pc)
3623: (label_ref (match_operand 0 "" ""))))]
3624: ""
3625: "*
3626: #ifdef MOTOROLA
3627: return \"jbhi %l0\";
3628: #else
3629: return \"jhi %l0\";
3630: #endif
3631: ")
3632:
3633: ;; Subroutines of "casesi".
3634:
3635: (define_expand "casesi_1"
3636: [(set (match_operand:SI 3 "general_operand" "")
3637: (plus:SI (match_operand:SI 0 "general_operand" "")
3638: ;; Note operand 1 has been negated!
3639: (match_operand:SI 1 "immediate_operand" "")))
3640: (set (cc0) (compare (match_operand:SI 2 "general_operand" "")
3641: (match_dup 3)))
3642: (set (pc) (if_then_else (ltu (cc0) (const_int 0))
3643: (label_ref (match_operand 4 "" "")) (pc)))]
3644: ""
3645: "")
3646:
3647: (define_expand "casesi_2"
3648: [(set (match_operand:SI 0 "" "") (mem:HI (match_operand:SI 1 "" "")))
3649: ;; The USE here is so that at least one jump-insn will refer to the label,
3650: ;; to keep it alive in jump_optimize.
3651: (parallel [(set (pc)
3652: (plus:SI (pc) (match_dup 0)))
3653: (use (label_ref (match_operand 2 "" "")))])]
3654: ""
3655: "")
3656:
3657: ;; Operand 0 is index (in bytes); operand 1 is minimum, operand 2 themaximum;
3658: ;; operand 3 is CODE_LABEL for the table;
3659: ;; operand 4 is the CODE_LABEL to go to if index out of range.
3660: (define_expand "casesi"
3661: ;; We don't use these for generating the RTL, but we must describe
3662: ;; the operands here.
3663: [(match_operand:SI 0 "general_operand" "")
3664: (match_operand:SI 1 "immediate_operand" "")
3665: (match_operand:SI 2 "general_operand" "")
3666: (match_operand 3 "" "")
3667: (match_operand 4 "" "")]
3668: ""
3669: "
3670: {
3671: rtx table_elt_addr;
3672: rtx index_diff;
3673:
3674: operands[1] = negate_rtx (SImode, operands[1]);
3675: index_diff = gen_reg_rtx (SImode);
3676: /* Emit the first few insns. */
3677: emit_insn (gen_casesi_1 (operands[0], operands[1], operands[2],
3678: index_diff, operands[4]));
3679: /* Construct a memory address. This may emit some insns. */
3680: table_elt_addr
3681: = memory_address_noforce
3682: (HImode,
3683: gen_rtx (PLUS, Pmode,
3684: gen_rtx (MULT, Pmode, index_diff,
3685: gen_rtx (CONST_INT, VOIDmode, 2)),
3686: gen_rtx (LABEL_REF, VOIDmode, operands[3])));
3687: /* Emit the last few insns. */
3688: emit_insn (gen_casesi_2 (gen_reg_rtx (HImode), table_elt_addr, operands[3]));
3689: DONE;
3690: }")
3691:
3692: ;; Recognize one of the insns resulting from casesi_2.
3693: (define_insn ""
3694: [(set (pc)
3695: (plus:SI (pc) (match_operand:HI 0 "general_operand" "r")))
3696: (use (label_ref (match_operand 1 "" "")))]
3697: ""
3698: "*
1.1.1.3 root 3699: {
3700: #ifdef ASM_RETURN_CASE_JUMP
3701: ASM_RETURN_CASE_JUMP;
3702: #else
1.1 root 3703: #ifdef SGS
3704: #ifdef ASM_OUTPUT_CASE_LABEL
3705: return \"jmp 6(%%pc,%0.w)\";
3706: #else
3707: return \"jmp 2(%%pc,%0.w)\";
3708: #endif
3709: #else /* not SGS */
3710: #ifdef MOTOROLA
3711: return \"jmp (2,pc,%0.w)\";
3712: #else
3713: return \"jmp pc@(2,%0:w)\";
3714: #endif
3715: #endif
1.1.1.3 root 3716: #endif /* no ASM_RETURN_CASE_JUMP */
3717: }")
1.1 root 3718:
3719: ;; Unconditional and other jump instructions
3720: (define_insn "jump"
3721: [(set (pc)
3722: (label_ref (match_operand 0 "" "")))]
3723: ""
3724: "*
3725: #ifdef MOTOROLA
3726: return \"jbra %l0\";
3727: #else
3728: return \"jra %l0\";
3729: #endif
3730: ")
3731:
3732: (define_insn ""
3733: [(set (pc)
3734: (if_then_else
1.1.1.4 ! root 3735: (ne (compare (plus:HI (match_operand:HI 0 "general_operand" "=g")
1.1 root 3736: (const_int -1))
3737: (const_int -1))
3738: (const_int 0))
3739: (label_ref (match_operand 1 "" ""))
3740: (pc)))
3741: (set (match_dup 0)
3742: (plus:HI (match_dup 0)
3743: (const_int -1)))]
3744: ""
3745: "*
3746: {
3747: CC_STATUS_INIT;
3748: if (DATA_REG_P (operands[0]))
3749: return \"dbra %0,%l1\";
3750: if (GET_CODE (operands[0]) == MEM)
3751: {
3752: #ifdef MOTOROLA
3753: #ifdef NO_ADDSUB_Q
3754: return \"sub%.w %#1,%0\;jbcc %l1\";
3755: #else
3756: return \"subq%.w %#1,%0\;jbcc %l1\";
3757: #endif
3758: #else /* not MOTOROLA */
3759: return \"subqw %#1,%0\;jcc %l1\";
3760: #endif
3761: }
3762: #ifdef MOTOROLA
3763: #ifdef HPUX_ASM
3764: #ifndef NO_ADDSUB_Q
3765: return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
3766: #else
3767: return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
3768: #endif
3769: #else /* not HPUX_ASM */
3770: return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
3771: #endif
3772: #else /* not MOTOROLA */
3773: return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
3774: #endif
3775: }")
3776:
3777: (define_insn ""
3778: [(set (pc)
3779: (if_then_else
1.1.1.4 ! root 3780: (ne (compare (plus:SI (match_operand:SI 0 "general_operand" "=g")
1.1 root 3781: (const_int -1))
3782: (const_int -1))
3783: (const_int 0))
3784: (label_ref (match_operand 1 "" ""))
3785: (pc)))
3786: (set (match_dup 0)
3787: (plus:SI (match_dup 0)
3788: (const_int -1)))]
3789: ""
3790: "*
3791: {
3792: CC_STATUS_INIT;
3793: #ifdef MOTOROLA
3794: #ifndef NO_ADDSUB_Q
3795: if (DATA_REG_P (operands[0]))
3796: return \"dbra %0,%l1\;clr.w %0\;sub.l %#1,%0\;jbcc %l1\";
3797: if (GET_CODE (operands[0]) == MEM)
3798: return \"sub.l %#1,%0\;jbcc %l1\";
3799: #else
3800: if (DATA_REG_P (operands[0]))
3801: return \"dbra %0,%l1\;clr.w %0\;subq.l %#1,%0\;jbcc %l1\";
3802: if (GET_CODE (operands[0]) == MEM)
3803: return \"subq.l %#1,%0\;jbcc %l1\";
3804: #endif /* not NO_ADDSUB_Q */
3805: #ifdef HPUX_ASM
3806: #ifndef NO_ADDSUB_Q
3807: return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
3808: #else
3809: return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
3810: #endif
3811: #else
3812: return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
3813: #endif
3814: #else
3815: if (DATA_REG_P (operands[0]))
3816: return \"dbra %0,%l1\;clrw %0\;subql %#1,%0\;jcc %l1\";
3817: if (GET_CODE (operands[0]) == MEM)
3818: return \"subql %#1,%0\;jcc %l1\";
3819: return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
3820: #endif
3821: }")
3822:
3823: ;; dbra patterns that use REG_NOTES info generated by strength_reduce.
3824:
3825: (define_insn ""
3826: [(set (pc)
3827: (if_then_else
1.1.1.4 ! root 3828: (ge (plus:SI (match_operand:SI 0 "general_operand" "=g")
1.1 root 3829: (const_int -1))
3830: (const_int 0))
3831: (label_ref (match_operand 1 "" ""))
3832: (pc)))
3833: (set (match_dup 0)
3834: (plus:SI (match_dup 0)
3835: (const_int -1)))]
3836: "find_reg_note (insn, REG_NONNEG, 0)"
3837: "*
3838: {
3839: CC_STATUS_INIT;
3840: #ifdef MOTOROLA
3841: #ifndef NO_ADDSUB_Q
3842: if (DATA_REG_P (operands[0]))
3843: return \"dbra %0,%l1\;clr.w %0\;sub.l %#1,%0\;jbcc %l1\";
3844: if (GET_CODE (operands[0]) == MEM)
3845: return \"sub.l %#1,%0\;jbcc %l1\";
3846: #else
3847: if (DATA_REG_P (operands[0]))
3848: return \"dbra %0,%l1\;clr.w %0\;subq.l %#1,%0\;jbcc %l1\";
3849: if (GET_CODE (operands[0]) == MEM)
3850: return \"subq.l %#1,%0\;jbcc %l1\";
3851: #endif
3852: #ifdef HPUX_ASM
3853: #ifndef NO_ADDSUB_Q
3854: return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
3855: #else
3856: return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
3857: #endif
3858: #else
3859: return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
3860: #endif
3861: #else
3862: if (DATA_REG_P (operands[0]))
3863: return \"dbra %0,%l1\;clrw %0\;subql %#1,%0\;jcc %l1\";
3864: if (GET_CODE (operands[0]) == MEM)
3865: return \"subql %#1,%0\;jcc %l1\";
3866: return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
3867: #endif
3868: }")
3869:
3870: ;; Call subroutine with no return value.
3871: (define_insn "call"
3872: [(call (match_operand:QI 0 "general_operand" "o")
3873: (match_operand:SI 1 "general_operand" "g"))]
3874: ;; Operand 1 not really used on the m68000.
3875:
3876: ""
3877: "*
3878: #ifdef MOTOROLA
3879: return \"jsr %0\";
3880: #else
3881: return \"jbsr %0\";
3882: #endif
3883: ")
3884:
3885: ;; Call subroutine, returning value in operand 0
3886: ;; (which must be a hard register).
3887: (define_insn "call_value"
3888: [(set (match_operand 0 "" "=rf")
3889: (call (match_operand:QI 1 "general_operand" "o")
3890: (match_operand:SI 2 "general_operand" "g")))]
3891: ;; Operand 2 not really used on the m68000.
3892: ""
3893: "*
3894: #ifdef MOTOROLA
3895: return \"jsr %1\";
3896: #else
3897: return \"jbsr %1\";
3898: #endif
3899: ")
3900:
3901: (define_insn "nop"
3902: [(const_int 0)]
3903: ""
3904: "nop")
3905:
3906: ;; This should not be used unless the add/sub insns can't be.
3907:
3908: (define_insn ""
3909: [(set (match_operand:SI 0 "general_operand" "=a")
3910: (match_operand:QI 1 "address_operand" "p"))]
3911: ""
3912: "lea %a1,%0")
3913:
3914: ;; This is the first machine-dependent peephole optimization.
3915: ;; It is useful when a floating value is returned from a function call
3916: ;; and then is moved into an FP register.
3917: ;; But it is mainly intended to test the support for these optimizations.
3918:
3919: (define_peephole
3920: [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
3921: (set (match_operand:DF 0 "register_operand" "f")
3922: (match_operand:DF 1 "register_operand" "ad"))]
3923: "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
3924: "*
3925: {
3926: rtx xoperands[2];
3927: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
3928: output_asm_insn (\"move%.l %1,%@\", xoperands);
3929: output_asm_insn (\"move%.l %1,%-\", operands);
3930: return \"fmove%.d %+,%0\";
3931: }
3932: ")
3933:
3934: ;; FPA multiply and add.
3935: (define_insn ""
3936: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
3937: (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
3938: (match_operand:DF 2 "general_operand" "xH,y,y"))
3939: (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
3940: "TARGET_FPA"
3941: "*
3942: {
3943: if (which_alternative == 0)
3944: return \"fpma%.d %1,%w2,%w3,%0\";
3945: return \"fpma%.d %x1,%x2,%x3,%0\";
3946: }")
3947:
3948: (define_insn ""
3949: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
3950: (plus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
3951: (mult:DF (match_operand:DF 2 "general_operand" "%x,dmF,y")
3952: (match_operand:DF 3 "general_operand" "xH,y,y"))))]
3953: "TARGET_FPA"
3954: "*
3955: {
3956: if (which_alternative == 0)
3957: return \"fpma%.d %2,%w3,%w1,%0\";
3958: return \"fpma%.d %x2,%x3,%x1,%0\";
3959: }")
3960:
3961: (define_insn ""
3962: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
3963: (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
3964: (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
3965: (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
3966: "TARGET_FPA"
3967: "*
3968: {
3969: if (which_alternative == 0)
3970: return \"fpma%.s %1,%w2,%w3,%0\";
3971: return \"fpma%.s %1,%2,%3,%0\";
3972: }")
3973:
3974: (define_insn ""
3975: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
3976: (plus:SF (match_operand:SF 1 "general_operand" "xH,ydmF,ydmF")
3977: (mult:SF (match_operand:SF 2 "general_operand" "%x,ydmF,y")
3978: (match_operand:SF 3 "general_operand" "xH,y,ydmF"))))]
3979: "TARGET_FPA"
3980: "*
3981: {
3982: if (which_alternative == 0)
3983: return \"fpma%.s %2,%w3,%w1,%0\";
3984: return \"fpma%.s %2,%3,%1,%0\";
3985: }")
3986:
3987: ;; FPA Multiply and subtract
3988: (define_insn ""
3989: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
3990: (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
3991: (mult:DF (match_operand:DF 2 "register_operand" "%xH,y,y")
3992: (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
3993: "TARGET_FPA"
3994: "*
3995: {
3996: if (which_alternative == 0)
3997: return \"fpms%.d %3,%w2,%w1,%0\";
3998: return \"fpms%.d %x3,%2,%x1,%0\";
3999: }")
4000:
4001: (define_insn ""
4002: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
4003: (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
4004: (mult:SF (match_operand:SF 2 "register_operand" "%xH,rmF,y")
4005: (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
4006: "TARGET_FPA"
4007: "*
4008: {
4009: if (which_alternative == 0)
4010: return \"fpms%.s %3,%w2,%w1,%0\";
4011: return \"fpms%.s %3,%2,%1,%0\";
4012: }")
4013:
4014: (define_insn ""
4015: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
4016: (minus:DF (mult:DF (match_operand:DF 1 "register_operand" "%xH,y,y")
4017: (match_operand:DF 2 "general_operand" "x,y,rmF"))
4018: (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
4019: "TARGET_FPA"
4020: "*
4021: {
4022: if (which_alternative == 0)
4023: return \"fpmr%.d %2,%w1,%w3,%0\";
4024: return \"fpmr%.d %x2,%1,%x3,%0\";
4025: }")
4026:
4027: (define_insn ""
4028: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
4029: (minus:SF (mult:SF (match_operand:SF 1 "register_operand" "%xH,rmF,y")
4030: (match_operand:SF 2 "general_operand" "x,y,yrmF"))
4031: (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
4032: "TARGET_FPA"
4033: "*
4034: {
4035: if (which_alternative == 0)
4036: return \"fpmr%.s %2,%w1,%w3,%0\";
4037: return \"fpmr%.s %x2,%1,%x3,%0\";
4038: }")
4039:
4040: ;; FPA Add and multiply
4041: (define_insn ""
4042: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
4043: (mult:DF (plus:DF (match_operand:DF 1 "register_operand" "%xH,y,y")
4044: (match_operand:DF 2 "general_operand" "x,y,rmF"))
4045: (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
4046: "TARGET_FPA"
4047: "*
4048: {
4049: if (which_alternative == 0)
4050: return \"fpam%.d %2,%w1,%w3,%0\";
4051: return \"fpam%.d %x2,%1,%x3,%0\";
4052: }")
4053:
4054: (define_insn ""
4055: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
4056: (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
4057: (plus:DF (match_operand:DF 2 "register_operand" "%xH,y,y")
4058: (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
4059: "TARGET_FPA"
4060: "*
4061: {
4062: if (which_alternative == 0)
4063: return \"fpam%.d %3,%w2,%w1,%0\";
4064: return \"fpam%.d %x3,%2,%x1,%0\";
4065: }")
4066:
4067: (define_insn ""
4068: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
4069: (mult:SF (plus:SF (match_operand:SF 1 "register_operand" "%xH,rmF,y")
4070: (match_operand:SF 2 "general_operand" "x,y,yrmF"))
4071: (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
4072: "TARGET_FPA"
4073: "*
4074: {
4075: if (which_alternative == 0)
4076: return \"fpam%.s %2,%w1,%w3,%0\";
4077: return \"fpam%.s %x2,%1,%x3,%0\";
4078: }")
4079:
4080: (define_insn ""
4081: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
4082: (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
4083: (plus:SF (match_operand:SF 2 "register_operand" "%xH,rmF,y")
4084: (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
4085: "TARGET_FPA"
4086: "*
4087: {
4088: if (which_alternative == 0)
4089: return \"fpam%.s %3,%w2,%w1,%0\";
4090: return \"fpam%.s %x3,%2,%x1,%0\";
4091: }")
4092:
4093: ;;FPA Subtract and multiply
4094: (define_insn ""
4095: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
4096: (mult:DF (minus:DF (match_operand:DF 1 "register_operand" "xH,y,y")
4097: (match_operand:DF 2 "general_operand" "x,y,rmF"))
4098: (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
4099: "TARGET_FPA"
4100: "*
4101: {
4102: if (which_alternative == 0)
4103: return \"fpsm%.d %2,%w1,%w3,%0\";
4104: return \"fpsm%.d %x2,%1,%x3,%0\";
4105: }")
4106:
4107: (define_insn ""
4108: [(set (match_operand:DF 0 "register_operand" "=x,y,y")
4109: (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
4110: (minus:DF (match_operand:DF 2 "register_operand" "xH,y,y")
4111: (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
4112: "TARGET_FPA"
4113: "*
4114: {
4115: if (which_alternative == 0)
4116: return \"fpsm%.d %3,%w2,%w1,%0\";
4117: return \"fpsm%.d %x3,%2,%x1,%0\";
4118: }")
4119:
4120: (define_insn ""
4121: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
4122: (mult:SF (minus:SF (match_operand:SF 1 "register_operand" "xH,rmF,y")
4123: (match_operand:SF 2 "general_operand" "x,y,yrmF"))
4124: (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
4125: "TARGET_FPA"
4126: "*
4127: {
4128: if (which_alternative == 0)
4129: return \"fpsm%.s %2,%w1,%w3,%0\";
4130: return \"fpsm%.s %x2,%1,%x3,%0\";
4131: }")
4132:
4133: (define_insn ""
4134: [(set (match_operand:SF 0 "register_operand" "=x,y,y")
4135: (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
4136: (minus:SF (match_operand:SF 2 "register_operand" "xH,rmF,y")
4137: (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
4138: "TARGET_FPA"
4139: "*
4140: {
4141: if (which_alternative == 0)
4142: return \"fpsm%.s %3,%w2,%w1,%0\";
4143: return \"fpsm%.s %x3,%2,%x1,%0\";
4144: }")
4145:
4146:
4147: ;;- Local variables:
4148: ;;- mode:emacs-lisp
4149: ;;- comment-start: ";;- "
4150: ;;- comment-start-skip: ";+- *"
4151: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
4152: ;;- eval: (modify-syntax-entry ?[ "(]")
4153: ;;- eval: (modify-syntax-entry ?] ")[")
4154: ;;- eval: (modify-syntax-entry ?{ "(}")
4155: ;;- eval: (modify-syntax-entry ?} "){")
4156: ;;- End:
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