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1.1 root 1: /* Definitions of target machine for GNU compiler. Sun 68000/68020 version. 1.1.1.4 ! root 2: Copyright (C) 1987, 1988, 1993, 1994, 1995 Free Software Foundation, Inc. 1.1 root 3: 4: This file is part of GNU CC. 5: 6: GNU CC is free software; you can redistribute it and/or modify 7: it under the terms of the GNU General Public License as published by 8: the Free Software Foundation; either version 2, or (at your option) 9: any later version. 10: 11: GNU CC is distributed in the hope that it will be useful, 12: but WITHOUT ANY WARRANTY; without even the implied warranty of 13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14: GNU General Public License for more details. 15: 16: You should have received a copy of the GNU General Public License 17: along with GNU CC; see the file COPYING. If not, write to 1.1.1.4 ! root 18: the Free Software Foundation, 59 Temple Place - Suite 330, ! 19: Boston, MA 02111-1307, USA. */ 1.1 root 20: 21: 22: /* Note that some other tm.h files include this one and then override 23: many of the definitions that relate to assembler syntax. */ 24: 25: 26: /* Names to predefine in the preprocessor for this target machine. */ 27: 28: /* See sun3.h, sun2.h, isi.h for different CPP_PREDEFINES. */ 29: 30: /* Print subsidiary information on the compiler version in use. */ 31: #ifdef MOTOROLA 32: #define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)"); 33: #else 34: #define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)"); 35: #endif 36: 37: /* Define SUPPORT_SUN_FPA to include support for generating code for 38: the Sun Floating Point Accelerator, an optional product for Sun 3 39: machines. By default, it is not defined. Avoid defining it unless 40: you need to output code for the Sun3+FPA architecture, as it has the 41: effect of slowing down the register set operations in hard-reg-set.h 42: (total number of registers will exceed number of bits in a long, 43: if defined, causing the set operations to expand to loops). 44: SUPPORT_SUN_FPA is typically defined in sun3.h. */ 45: 46: /* Run-time compilation parameters selecting different hardware subsets. */ 47: 48: extern int target_flags; 49: 50: /* Macros used in the machine description to test the flags. */ 51: 52: /* Compile for a 68020 (not a 68000 or 68010). */ 53: #define TARGET_68020 (target_flags & 1) 54: 55: /* Compile 68881 insns for floating point (not library calls). */ 56: #define TARGET_68881 (target_flags & 2) 57: 58: /* Compile using 68020 bitfield insns. */ 59: #define TARGET_BITFIELD (target_flags & 4) 60: 61: /* Compile using rtd insn calling sequence. 62: This will not work unless you use prototypes at least 63: for all functions that can take varying numbers of args. */ 64: #define TARGET_RTD (target_flags & 8) 65: 66: /* Compile passing first two args in regs 0 and 1. 67: This exists only to test compiler features that will 68: be needed for RISC chips. It is not usable 69: and is not intended to be usable on this cpu. */ 70: #define TARGET_REGPARM (target_flags & 020) 71: 72: /* Compile with 16-bit `int'. */ 73: #define TARGET_SHORT (target_flags & 040) 74: 75: /* Compile with special insns for Sun FPA. */ 76: #ifdef SUPPORT_SUN_FPA 77: #define TARGET_FPA (target_flags & 0100) 78: #else 79: #define TARGET_FPA 0 80: #endif 81: 82: /* Compile (actually, link) for Sun SKY board. */ 83: #define TARGET_SKY (target_flags & 0200) 84: 85: /* Optimize for 68040, but still allow execution on 68020 86: (-m68020-40 or -m68040). 87: The 68040 will execute all 68030 and 68881/2 instructions, but some 88: of them must be emulated in software by the OS. When TARGET_68040 is 89: turned on, these instructions won't be used. This code will still 90: run on a 68030 and 68881/2. */ 91: #define TARGET_68040 (target_flags & 01400) 92: 93: /* Use the 68040-only fp instructions (-m68040). */ 94: #define TARGET_68040_ONLY (target_flags & 01000) 95: 96: /* Macro to define tables used to set the flags. 97: This is a list in braces of pairs in braces, 98: each pair being { "NAME", VALUE } 99: where VALUE is the bits to set or minus the bits to clear. 100: An empty string NAME is used to identify the default VALUE. */ 101: 102: #define TARGET_SWITCHES \ 103: { { "68020", -01400}, \ 104: { "c68020", -01400}, \ 105: { "68020", 5}, \ 106: { "c68020", 5}, \ 107: { "68881", 2}, \ 108: { "bitfield", 4}, \ 109: { "68000", -01405}, \ 110: { "c68000", -01405}, \ 111: { "soft-float", -01102}, \ 112: { "nobitfield", -4}, \ 113: { "rtd", 8}, \ 114: { "nortd", -8}, \ 115: { "short", 040}, \ 116: { "noshort", -040}, \ 117: { "fpa", 0100}, \ 118: { "nofpa", -0100}, \ 119: { "sky", 0200}, \ 120: { "nosky", -0200}, \ 121: { "68020-40", 0407}, \ 122: { "68030", -01400}, \ 123: { "68030", 5}, \ 124: { "68040", 01007}, \ 1.1.1.2 root 125: { "68851", 0}, /* Affects *_SPEC and/or GAS. */ \ 126: { "no-68851", 0}, /* Affects *_SPEC and/or GAS. */ \ 127: { "68302", 0}, /* Affects *_SPEC and/or GAS. */ \ 128: { "no-68302", 0}, /* Affects *_SPEC and/or GAS. */ \ 129: { "68332", 0}, /* Affects *_SPEC and/or GAS. */ \ 130: { "no-68332", 0}, /* Affects *_SPEC and/or GAS. */ \ 131: SUBTARGET_SWITCHES \ 1.1 root 132: { "", TARGET_DEFAULT}} 133: /* TARGET_DEFAULT is defined in sun*.h and isi.h, etc. */ 134: 1.1.1.2 root 135: /* This is meant to be redefined in the host dependent files */ 136: #define SUBTARGET_SWITCHES 137: 1.1 root 138: #ifdef SUPPORT_SUN_FPA 139: /* Blow away 68881 flag silently on TARGET_FPA (since we can't clear 140: any bits in TARGET_SWITCHES above) */ 141: #define OVERRIDE_OPTIONS \ 142: { \ 143: if (TARGET_FPA) target_flags &= ~2; \ 144: if (! TARGET_68020 && flag_pic == 2) \ 145: error("-fPIC is not currently supported on the 68000 or 68010\n"); \ 1.1.1.4 ! root 146: SUBTARGET_OVERRIDE_OPTIONS; \ 1.1 root 147: } 148: #else 149: #define OVERRIDE_OPTIONS \ 150: { \ 151: if (! TARGET_68020 && flag_pic == 2) \ 152: error("-fPIC is not currently supported on the 68000 or 68010\n"); \ 1.1.1.4 ! root 153: SUBTARGET_OVERRIDE_OPTIONS; \ 1.1 root 154: } 155: #endif /* defined SUPPORT_SUN_FPA */ 1.1.1.2 root 156: 157: /* This is meant to be redefined in the host dependent files */ 158: #define SUBTARGET_OVERRIDE_OPTIONS 1.1 root 159: 160: /* target machine storage layout */ 161: 162: /* Define for XFmode extended real floating point support. 163: This will automatically cause REAL_ARITHMETIC to be defined. */ 164: #define LONG_DOUBLE_TYPE_SIZE 96 165: 166: /* Define if you don't want extended real, but do want to use the 167: software floating point emulator for REAL_ARITHMETIC and 168: decimal <-> binary conversion. */ 169: /* #define REAL_ARITHMETIC */ 170: 171: /* Define this if most significant bit is lowest numbered 172: in instructions that operate on numbered bit-fields. 173: This is true for 68020 insns such as bfins and bfexts. 174: We make it true always by avoiding using the single-bit insns 175: except in special cases with constant bit numbers. */ 176: #define BITS_BIG_ENDIAN 1 177: 178: /* Define this if most significant byte of a word is the lowest numbered. */ 179: /* That is true on the 68000. */ 180: #define BYTES_BIG_ENDIAN 1 181: 182: /* Define this if most significant word of a multiword number is the lowest 183: numbered. */ 184: /* For 68000 we can decide arbitrarily 185: since there are no machine instructions for them. 186: So let's be consistent. */ 187: #define WORDS_BIG_ENDIAN 1 188: 189: /* number of bits in an addressable storage unit */ 190: #define BITS_PER_UNIT 8 191: 192: /* Width in bits of a "word", which is the contents of a machine register. 193: Note that this is not necessarily the width of data type `int'; 194: if using 16-bit ints on a 68000, this would still be 32. 195: But on a machine with 16-bit registers, this would be 16. */ 196: #define BITS_PER_WORD 32 197: 198: /* Width of a word, in units (bytes). */ 199: #define UNITS_PER_WORD 4 200: 201: /* Width in bits of a pointer. 202: See also the macro `Pmode' defined below. */ 203: #define POINTER_SIZE 32 204: 205: /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 206: #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) 207: 208: /* Boundary (in *bits*) on which stack pointer should be aligned. */ 209: #define STACK_BOUNDARY 16 210: 211: /* Allocation boundary (in *bits*) for the code of a function. */ 212: #define FUNCTION_BOUNDARY 16 213: 214: /* Alignment of field after `int : 0' in a structure. */ 215: #define EMPTY_FIELD_BOUNDARY 16 216: 217: /* No data type wants to be aligned rounder than this. */ 218: #define BIGGEST_ALIGNMENT 16 219: 220: /* Set this nonzero if move instructions will actually fail to work 221: when given unaligned data. */ 222: #define STRICT_ALIGNMENT 1 223: 224: #define SELECT_RTX_SECTION(MODE, X) \ 225: { \ 226: if (!flag_pic) \ 227: readonly_data_section(); \ 228: else if (LEGITIMATE_PIC_OPERAND_P (X)) \ 229: readonly_data_section(); \ 230: else \ 231: data_section(); \ 232: } 233: 234: /* Define number of bits in most basic integer type. 235: (If undefined, default is BITS_PER_WORD). */ 236: 237: #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) 238: 239: /* Define these to avoid dependence on meaning of `int'. 240: Note that WCHAR_TYPE_SIZE is used in cexp.y, 241: where TARGET_SHORT is not available. */ 242: 243: #define WCHAR_TYPE "long int" 244: #define WCHAR_TYPE_SIZE 32 245: 246: /* Standard register usage. */ 247: 248: /* Number of actual hardware registers. 249: The hardware registers are assigned numbers for the compiler 250: from 0 to just below FIRST_PSEUDO_REGISTER. 251: All registers that the compiler knows about must be given numbers, 252: even those that are not normally considered general registers. 253: For the 68000, we give the data registers numbers 0-7, 254: the address registers numbers 010-017, 255: and the 68881 floating point registers numbers 020-027. */ 256: #ifndef SUPPORT_SUN_FPA 257: #define FIRST_PSEUDO_REGISTER 24 258: #else 259: #define FIRST_PSEUDO_REGISTER 56 260: #endif 261: 262: /* This defines the register which is used to hold the offset table for PIC. */ 263: #define PIC_OFFSET_TABLE_REGNUM 13 264: 265: /* Used to output a (use pic_offset_table_rtx) so that we 266: always save/restore a5 in functions that use PIC relocation 267: at *any* time during the compilation process. */ 268: #define FINALIZE_PIC finalize_pic() 269: 270: #ifndef SUPPORT_SUN_FPA 271: 272: /* 1 for registers that have pervasive standard uses 273: and are not available for the register allocator. 274: On the 68000, only the stack pointer is such. */ 275: 276: #define FIXED_REGISTERS \ 277: {/* Data registers. */ \ 278: 0, 0, 0, 0, 0, 0, 0, 0, \ 279: \ 280: /* Address registers. */ \ 281: 0, 0, 0, 0, 0, 0, 0, 1, \ 282: \ 283: /* Floating point registers \ 284: (if available). */ \ 285: 0, 0, 0, 0, 0, 0, 0, 0 } 286: 287: /* 1 for registers not available across function calls. 288: These must include the FIXED_REGISTERS and also any 289: registers that can be used without being saved. 290: The latter must include the registers where values are returned 291: and the register where structure-value addresses are passed. 292: Aside from that, you can include as many other registers as you like. */ 293: #define CALL_USED_REGISTERS \ 294: {1, 1, 0, 0, 0, 0, 0, 0, \ 295: 1, 1, 0, 0, 0, 0, 0, 1, \ 296: 1, 1, 0, 0, 0, 0, 0, 0 } 297: 298: #else /* SUPPORT_SUN_FPA */ 299: 300: /* 1 for registers that have pervasive standard uses 301: and are not available for the register allocator. 302: On the 68000, only the stack pointer is such. */ 303: 304: /* fpa0 is also reserved so that it can be used to move shit back and 305: forth between high fpa regs and everything else. */ 306: 307: #define FIXED_REGISTERS \ 308: {/* Data registers. */ \ 309: 0, 0, 0, 0, 0, 0, 0, 0, \ 310: \ 311: /* Address registers. */ \ 312: 0, 0, 0, 0, 0, 0, 0, 1, \ 313: \ 314: /* Floating point registers \ 315: (if available). */ \ 316: 0, 0, 0, 0, 0, 0, 0, 0, \ 317: \ 318: /* Sun3 FPA registers. */ \ 319: 1, 0, 0, 0, 0, 0, 0, 0, \ 320: 0, 0, 0, 0, 0, 0, 0, 0, \ 321: 0, 0, 0, 0, 0, 0, 0, 0, \ 322: 0, 0, 0, 0, 0, 0, 0, 0 } 323: 324: /* 1 for registers not available across function calls. 325: These must include the FIXED_REGISTERS and also any 326: registers that can be used without being saved. 327: The latter must include the registers where values are returned 328: and the register where structure-value addresses are passed. 329: Aside from that, you can include as many other registers as you like. */ 330: #define CALL_USED_REGISTERS \ 331: {1, 1, 0, 0, 0, 0, 0, 0, \ 332: 1, 1, 0, 0, 0, 0, 0, 1, \ 333: 1, 1, 0, 0, 0, 0, 0, 0, \ 334: /* FPA registers. */ \ 335: 1, 1, 1, 1, 0, 0, 0, 0, \ 336: 0, 0, 0, 0, 0, 0, 0, 0, \ 337: 0, 0, 0, 0, 0, 0, 0, 0, \ 338: 0, 0, 0, 0, 0, 0, 0, 0 } 339: 340: #endif /* defined SUPPORT_SUN_FPA */ 341: 342: 343: /* Make sure everything's fine if we *don't* have a given processor. 344: This assumes that putting a register in fixed_regs will keep the 345: compiler's mitts completely off it. We don't bother to zero it out 346: of register classes. If neither TARGET_FPA or TARGET_68881 is set, 347: the compiler won't touch since no instructions that use these 1.1.1.4 ! root 348: registers will be valid. */ 1.1 root 349: 1.1.1.4 ! root 350: #ifdef SUPPORT_SUN_FPA 1.1 root 351: 352: #define CONDITIONAL_REGISTER_USAGE \ 353: { \ 354: int i; \ 355: HARD_REG_SET x; \ 356: if (!TARGET_FPA) \ 357: { \ 358: COPY_HARD_REG_SET (x, reg_class_contents[(int)FPA_REGS]); \ 359: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ 360: if (TEST_HARD_REG_BIT (x, i)) \ 361: fixed_regs[i] = call_used_regs[i] = 1; \ 362: } \ 363: if (TARGET_FPA) \ 364: { \ 365: COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ 366: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ 367: if (TEST_HARD_REG_BIT (x, i)) \ 368: fixed_regs[i] = call_used_regs[i] = 1; \ 369: } \ 370: } 371: 372: #endif /* defined SUPPORT_SUN_FPA */ 373: 374: /* Return number of consecutive hard regs needed starting at reg REGNO 375: to hold something of mode MODE. 376: This is ordinarily the length in words of a value of mode MODE 377: but can be less for certain modes in special long registers. 378: 379: On the 68000, ordinary registers hold 32 bits worth; 380: for the 68881 registers, a single register is always enough for 381: anything that can be stored in them at all. */ 382: #define HARD_REGNO_NREGS(REGNO, MODE) \ 383: ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ 384: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 385: 386: #ifndef SUPPORT_SUN_FPA 387: 388: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 389: On the 68000, the cpu registers can hold any mode but the 68881 registers 390: can hold only SFmode or DFmode. The 68881 registers can't hold anything 391: if 68881 use is disabled. */ 392: 393: #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1.1.1.4 ! root 394: (((REGNO) < 16 \ ! 395: && !((REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8)) \ 1.1 root 396: || ((REGNO) < 24 \ 397: && TARGET_68881 \ 398: && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 399: || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT))) 400: 401: #else /* defined SUPPORT_SUN_FPA */ 402: 403: /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. 404: On the 68000, the cpu registers can hold any mode but the 68881 registers 405: can hold only SFmode or DFmode. And the 68881 registers can't hold anything 406: if 68881 use is disabled. However, the Sun FPA register can 407: (apparently) hold whatever you feel like putting in them. 408: If using the fpa, don't put a double in d7/a0. */ 409: 410: #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 411: (((REGNO) < 16 \ 412: && !(TARGET_FPA \ 413: && GET_MODE_CLASS ((MODE)) != MODE_INT \ 414: && GET_MODE_UNIT_SIZE ((MODE)) > 4 \ 415: && (REGNO) < 8 && (REGNO) + GET_MODE_SIZE ((MODE)) / 4 > 8 \ 416: && (REGNO) % (GET_MODE_UNIT_SIZE ((MODE)) / 4) != 0)) \ 417: || ((REGNO) < 24 \ 418: ? TARGET_68881 && (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 419: || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) \ 420: : ((REGNO) < 56 ? TARGET_FPA : 0))) 421: 422: #endif /* defined SUPPORT_SUN_FPA */ 423: 424: /* Value is 1 if it is a good idea to tie two pseudo registers 425: when one has mode MODE1 and one has mode MODE2. 426: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 427: for any hard reg, then this must be 0 for correct output. */ 428: #define MODES_TIEABLE_P(MODE1, MODE2) \ 429: (! TARGET_68881 \ 430: || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 431: || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 432: == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 433: || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) 434: 435: /* Specify the registers used for certain standard purposes. 436: The values of these macros are register numbers. */ 437: 438: /* m68000 pc isn't overloaded on a register. */ 439: /* #define PC_REGNUM */ 440: 441: /* Register to use for pushing function arguments. */ 442: #define STACK_POINTER_REGNUM 15 443: 444: /* Base register for access to local variables of the function. */ 445: #define FRAME_POINTER_REGNUM 14 446: 447: /* Value should be nonzero if functions must have frame pointers. 448: Zero means the frame pointer need not be set up (and parms 449: may be accessed via the stack pointer) in functions that seem suitable. 450: This is computed in `reload', in reload1.c. */ 451: #define FRAME_POINTER_REQUIRED 0 452: 453: /* Base register for access to arguments of the function. */ 454: #define ARG_POINTER_REGNUM 14 455: 456: /* Register in which static-chain is passed to a function. */ 457: #define STATIC_CHAIN_REGNUM 8 458: 459: /* Register in which address to store a structure value 460: is passed to a function. */ 461: #define STRUCT_VALUE_REGNUM 9 462: 463: /* Define the classes of registers for register constraints in the 464: machine description. Also define ranges of constants. 465: 466: One of the classes must always be named ALL_REGS and include all hard regs. 467: If there is more than one class, another class must be named NO_REGS 468: and contain no registers. 469: 470: The name GENERAL_REGS must be the name of a class (or an alias for 471: another name such as ALL_REGS). This is the class of registers 472: that is allowed by "g" or "r" in a register constraint. 473: Also, registers outside this class are allocated only when 474: instructions express preferences for them. 475: 476: The classes must be numbered in nondecreasing order; that is, 477: a larger-numbered class must never be contained completely 478: in a smaller-numbered class. 479: 480: For any two classes, it is very desirable that there be another 481: class that represents their union. */ 482: 483: /* The 68000 has three kinds of registers, so eight classes would be 484: a complete set. One of them is not needed. */ 485: 486: #ifndef SUPPORT_SUN_FPA 487: 488: enum reg_class { 489: NO_REGS, DATA_REGS, 490: ADDR_REGS, FP_REGS, 491: GENERAL_REGS, DATA_OR_FP_REGS, 492: ADDR_OR_FP_REGS, ALL_REGS, 493: LIM_REG_CLASSES }; 494: 495: #define N_REG_CLASSES (int) LIM_REG_CLASSES 496: 497: /* Give names of register classes as strings for dump file. */ 498: 499: #define REG_CLASS_NAMES \ 500: { "NO_REGS", "DATA_REGS", \ 501: "ADDR_REGS", "FP_REGS", \ 502: "GENERAL_REGS", "DATA_OR_FP_REGS", \ 503: "ADDR_OR_FP_REGS", "ALL_REGS" } 504: 505: /* Define which registers fit in which classes. 506: This is an initializer for a vector of HARD_REG_SET 507: of length N_REG_CLASSES. */ 508: 509: #define REG_CLASS_CONTENTS \ 510: { \ 511: 0x00000000, /* NO_REGS */ \ 512: 0x000000ff, /* DATA_REGS */ \ 513: 0x0000ff00, /* ADDR_REGS */ \ 514: 0x00ff0000, /* FP_REGS */ \ 515: 0x0000ffff, /* GENERAL_REGS */ \ 516: 0x00ff00ff, /* DATA_OR_FP_REGS */ \ 517: 0x00ffff00, /* ADDR_OR_FP_REGS */ \ 518: 0x00ffffff, /* ALL_REGS */ \ 519: } 520: 521: /* The same information, inverted: 522: Return the class number of the smallest class containing 523: reg number REGNO. This could be a conditional expression 524: or could index an array. */ 525: 526: #define REGNO_REG_CLASS(REGNO) (((REGNO)>>3)+1) 527: 528: #else /* defined SUPPORT_SUN_FPA */ 529: 530: /* 531: * Notes on final choices: 532: * 533: * 1) Didn't feel any need to union-ize LOW_FPA_REGS with anything 534: * else. 535: * 2) Removed all unions that involve address registers with 536: * floating point registers (left in unions of address and data with 537: * floating point). 538: * 3) Defined GENERAL_REGS as ADDR_OR_DATA_REGS. 539: * 4) Defined ALL_REGS as FPA_OR_FP_OR_GENERAL_REGS. 540: * 4) Left in everything else. 541: */ 542: enum reg_class { NO_REGS, LO_FPA_REGS, FPA_REGS, FP_REGS, 543: FP_OR_FPA_REGS, DATA_REGS, DATA_OR_FPA_REGS, DATA_OR_FP_REGS, 544: DATA_OR_FP_OR_FPA_REGS, ADDR_REGS, GENERAL_REGS, 545: GENERAL_OR_FPA_REGS, GENERAL_OR_FP_REGS, ALL_REGS, 546: LIM_REG_CLASSES }; 547: 548: #define N_REG_CLASSES (int) LIM_REG_CLASSES 549: 550: /* Give names of register classes as strings for dump file. */ 551: 552: #define REG_CLASS_NAMES \ 553: { "NO_REGS", "LO_FPA_REGS", "FPA_REGS", "FP_REGS", \ 554: "FP_OR_FPA_REGS", "DATA_REGS", "DATA_OR_FPA_REGS", "DATA_OR_FP_REGS", \ 555: "DATA_OR_FP_OR_FPA_REGS", "ADDR_REGS", "GENERAL_REGS", \ 556: "GENERAL_OR_FPA_REGS", "GENERAL_OR_FP_REGS", "ALL_REGS" } 557: 558: /* Define which registers fit in which classes. 559: This is an initializer for a vector of HARD_REG_SET 560: of length N_REG_CLASSES. */ 561: 562: #define REG_CLASS_CONTENTS \ 563: { \ 564: {0, 0}, /* NO_REGS */ \ 565: {0xff000000, 0x000000ff}, /* LO_FPA_REGS */ \ 566: {0xff000000, 0x00ffffff}, /* FPA_REGS */ \ 567: {0x00ff0000, 0x00000000}, /* FP_REGS */ \ 568: {0xffff0000, 0x00ffffff}, /* FP_OR_FPA_REGS */ \ 569: {0x000000ff, 0x00000000}, /* DATA_REGS */ \ 570: {0xff0000ff, 0x00ffffff}, /* DATA_OR_FPA_REGS */ \ 571: {0x00ff00ff, 0x00000000}, /* DATA_OR_FP_REGS */ \ 572: {0xffff00ff, 0x00ffffff}, /* DATA_OR_FP_OR_FPA_REGS */\ 573: {0x0000ff00, 0x00000000}, /* ADDR_REGS */ \ 574: {0x0000ffff, 0x00000000}, /* GENERAL_REGS */ \ 575: {0xff00ffff, 0x00ffffff}, /* GENERAL_OR_FPA_REGS */\ 576: {0x00ffffff, 0x00000000}, /* GENERAL_OR_FP_REGS */\ 577: {0xffffffff, 0x00ffffff}, /* ALL_REGS */ \ 578: } 579: 580: /* The same information, inverted: 581: Return the class number of the smallest class containing 582: reg number REGNO. This could be a conditional expression 583: or could index an array. */ 584: 585: extern enum reg_class regno_reg_class[]; 586: #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)>>3]) 587: 588: #endif /* SUPPORT_SUN_FPA */ 589: 590: /* The class value for index registers, and the one for base regs. */ 591: 592: #define INDEX_REG_CLASS GENERAL_REGS 593: #define BASE_REG_CLASS ADDR_REGS 594: 595: /* Get reg_class from a letter such as appears in the machine description. 596: We do a trick here to modify the effective constraints on the 597: machine description; we zorch the constraint letters that aren't 598: appropriate for a specific target. This allows us to guarantee 599: that a specific kind of register will not be used for a given target 600: without fiddling with the register classes above. */ 601: 602: #ifndef SUPPORT_SUN_FPA 603: 604: #define REG_CLASS_FROM_LETTER(C) \ 605: ((C) == 'a' ? ADDR_REGS : \ 606: ((C) == 'd' ? DATA_REGS : \ 607: ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ 608: NO_REGS) : \ 609: NO_REGS))) 610: 611: #else /* defined SUPPORT_SUN_FPA */ 612: 613: #define REG_CLASS_FROM_LETTER(C) \ 614: ((C) == 'a' ? ADDR_REGS : \ 615: ((C) == 'd' ? DATA_REGS : \ 616: ((C) == 'f' ? (TARGET_68881 ? FP_REGS : \ 617: NO_REGS) : \ 618: ((C) == 'x' ? (TARGET_FPA ? FPA_REGS : \ 619: NO_REGS) : \ 620: ((C) == 'y' ? (TARGET_FPA ? LO_FPA_REGS : \ 621: NO_REGS) : \ 622: NO_REGS))))) 623: 624: #endif /* defined SUPPORT_SUN_FPA */ 625: 626: /* The letters I, J, K, L and M in a register constraint string 627: can be used to stand for particular ranges of immediate operands. 628: This macro defines what the ranges are. 629: C is the letter, and VALUE is a constant value. 630: Return 1 if VALUE is in the range specified by C. 631: 632: For the 68000, `I' is used for the range 1 to 8 633: allowed as immediate shift counts and in addq. 634: `J' is used for the range of signed numbers that fit in 16 bits. 635: `K' is for numbers that moveq can't handle. 636: `L' is for range -8 to -1, range of values that can be added with subq. */ 637: 638: #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 639: ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \ 640: (C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \ 641: (C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \ 642: (C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : 0) 643: 644: /* 645: * A small bit of explanation: 646: * "G" defines all of the floating constants that are *NOT* 68881 647: * constants. this is so 68881 constants get reloaded and the 648: * fpmovecr is used. "H" defines *only* the class of constants that 649: * the fpa can use, because these can be gotten at in any fpa 650: * instruction and there is no need to force reloads. 651: */ 652: #ifndef SUPPORT_SUN_FPA 653: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 654: ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : 0 ) 655: #else /* defined SUPPORT_SUN_FPA */ 656: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 657: ((C) == 'G' ? ! (TARGET_68881 && standard_68881_constant_p (VALUE)) : \ 658: (C) == 'H' ? (TARGET_FPA && standard_sun_fpa_constant_p (VALUE)) : 0) 659: #endif /* defined SUPPORT_SUN_FPA */ 660: 661: /* Given an rtx X being reloaded into a reg required to be 662: in class CLASS, return the class of reg to actually use. 663: In general this is just CLASS; but on some machines 664: in some cases it is preferable to use a more restrictive class. 665: On the 68000 series, use a data reg if possible when the 666: value is a constant in the range where moveq could be used 667: and we ensure that QImodes are reloaded into data regs. 1.1.1.3 root 668: Also, if a floating constant needs reloading, put it in memory. 669: Don't do this for !G constants, since all patterns in the md file 670: expect them to be loaded into a register via fpmovecr. See above. */ 1.1 root 671: 672: #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 673: ((GET_CODE (X) == CONST_INT \ 674: && (unsigned) (INTVAL (X) + 0x80) < 0x100 \ 675: && (CLASS) != ADDR_REGS) \ 676: ? DATA_REGS \ 677: : (GET_MODE (X) == QImode && (CLASS) != ADDR_REGS) \ 678: ? DATA_REGS \ 679: : (GET_CODE (X) == CONST_DOUBLE \ 680: && GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT) \ 1.1.1.3 root 681: ? (! CONST_DOUBLE_OK_FOR_LETTER_P (X, 'G') \ 1.1.1.4 ! root 682: && (CLASS == FP_REGS || CLASS == DATA_OR_FP_REGS) \ 1.1.1.3 root 683: ? FP_REGS : NO_REGS) \ 1.1 root 684: : (CLASS)) 685: 686: /* Return the maximum number of consecutive registers 687: needed to represent mode MODE in a register of class CLASS. */ 688: /* On the 68000, this is the size of MODE in words, 689: except in the FP regs, where a single reg is always enough. */ 690: #ifndef SUPPORT_SUN_FPA 691: 692: #define CLASS_MAX_NREGS(CLASS, MODE) \ 693: ((CLASS) == FP_REGS ? 1 \ 694: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 695: 696: /* Moves between fp regs and other regs are two insns. */ 697: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ 698: (((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ 699: || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ 700: ? 4 : 2) 701: 702: #else /* defined SUPPORT_SUN_FPA */ 703: 704: #define CLASS_MAX_NREGS(CLASS, MODE) \ 705: ((CLASS) == FP_REGS || (CLASS) == FPA_REGS || (CLASS) == LO_FPA_REGS ? 1 \ 706: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 707: 708: /* Moves between fp regs and other regs are two insns. */ 709: /* Likewise for high fpa regs and other regs. */ 710: #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ 711: ((((CLASS1) == FP_REGS && (CLASS2) != FP_REGS) \ 712: || ((CLASS2) == FP_REGS && (CLASS1) != FP_REGS) \ 713: || ((CLASS1) == FPA_REGS && (CLASS2) != FPA_REGS) \ 714: || ((CLASS2) == FPA_REGS && (CLASS1) != FPA_REGS)) \ 715: ? 4 : 2) 716: 717: #endif /* define SUPPORT_SUN_FPA */ 718: 719: /* Stack layout; function entry, exit and calling. */ 720: 721: /* Define this if pushing a word on the stack 722: makes the stack pointer a smaller address. */ 723: #define STACK_GROWS_DOWNWARD 724: 725: /* Nonzero if we need to generate stack-probe insns. 726: On most systems they are not needed. 727: When they are needed, define this as the stack offset to probe at. */ 728: #define NEED_PROBE 0 729: 730: /* Define this if the nominal address of the stack frame 731: is at the high-address end of the local variables; 732: that is, each additional local variable allocated 733: goes at a more negative offset in the frame. */ 734: #define FRAME_GROWS_DOWNWARD 735: 736: /* Offset within stack frame to start allocating local variables at. 737: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 738: first local allocated. Otherwise, it is the offset to the BEGINNING 739: of the first local allocated. */ 740: #define STARTING_FRAME_OFFSET 0 741: 742: /* If we generate an insn to push BYTES bytes, 743: this says how many the stack pointer really advances by. 744: On the 68000, sp@- in a byte insn really pushes a word. */ 745: #define PUSH_ROUNDING(BYTES) (((BYTES) + 1) & ~1) 746: 747: /* Offset of first parameter from the argument pointer register value. */ 748: #define FIRST_PARM_OFFSET(FNDECL) 8 749: 750: /* Value is the number of byte of arguments automatically 751: popped when returning from a subroutine call. 1.1.1.4 ! root 752: FUNDECL is the declaration node of the function (as a tree), 1.1 root 753: FUNTYPE is the data type of the function (as a tree), 754: or for a library call it is an identifier node for the subroutine name. 755: SIZE is the number of bytes of arguments passed on the stack. 756: 757: On the 68000, the RTS insn cannot pop anything. 758: On the 68010, the RTD insn may be used to pop them if the number 759: of args is fixed, but if the number is variable then the caller 760: must pop them all. RTD can't be used for library calls now 761: because the library is compiled with the Unix compiler. 762: Use of RTD is a selectable option, since it is incompatible with 763: standard Unix calling sequences. If the option is not selected, 764: the caller must always pop the args. */ 765: 1.1.1.4 ! root 766: #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ 1.1 root 767: ((TARGET_RTD && TREE_CODE (FUNTYPE) != IDENTIFIER_NODE \ 768: && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ 769: || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ 770: == void_type_node))) \ 771: ? (SIZE) : 0) 772: 773: /* Define how to find the value returned by a function. 774: VALTYPE is the data type of the value (as a tree). 775: If the precise function being called is known, FUNC is its FUNCTION_DECL; 776: otherwise, FUNC is 0. */ 777: 778: /* On the 68000 the return value is in D0 regardless. */ 779: 780: #define FUNCTION_VALUE(VALTYPE, FUNC) \ 781: gen_rtx (REG, TYPE_MODE (VALTYPE), 0) 782: 783: /* Define how to find the value returned by a library function 784: assuming the value has mode MODE. */ 785: 786: /* On the 68000 the return value is in D0 regardless. */ 787: 788: #define LIBCALL_VALUE(MODE) gen_rtx (REG, MODE, 0) 789: 790: /* 1 if N is a possible register number for a function value. 791: On the 68000, d0 is the only register thus used. */ 792: 793: #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) 794: 795: /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for 796: more than one register. */ 797: 798: #define NEEDS_UNTYPED_CALL 0 799: 800: /* Define this if PCC uses the nonreentrant convention for returning 801: structure and union values. */ 802: 803: #define PCC_STATIC_STRUCT_RETURN 804: 805: /* 1 if N is a possible register number for function argument passing. 806: On the 68000, no registers are used in this way. */ 807: 808: #define FUNCTION_ARG_REGNO_P(N) 0 809: 810: /* Define a data type for recording info about an argument list 811: during the scan of that argument list. This data type should 812: hold all necessary information about the function itself 813: and about the args processed so far, enough to enable macros 814: such as FUNCTION_ARG to determine where the next arg should go. 815: 816: On the m68k, this is a single integer, which is a number of bytes 817: of arguments scanned so far. */ 818: 819: #define CUMULATIVE_ARGS int 820: 821: /* Initialize a variable CUM of type CUMULATIVE_ARGS 822: for a call to a function whose data type is FNTYPE. 823: For a library call, FNTYPE is 0. 824: 825: On the m68k, the offset starts at 0. */ 826: 827: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ 828: ((CUM) = 0) 829: 830: /* Update the data in CUM to advance over an argument 831: of mode MODE and data type TYPE. 832: (TYPE is null for libcalls where that information may not be available.) */ 833: 834: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 835: ((CUM) += ((MODE) != BLKmode \ 836: ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ 837: : (int_size_in_bytes (TYPE) + 3) & ~3)) 838: 839: /* Define where to put the arguments to a function. 840: Value is zero to push the argument on the stack, 841: or a hard register in which to store the argument. 842: 843: MODE is the argument's machine mode. 844: TYPE is the data type of the argument (as a tree). 845: This is null for libcalls where that information may 846: not be available. 847: CUM is a variable of type CUMULATIVE_ARGS which gives info about 848: the preceding args and about the function being called. 849: NAMED is nonzero if this argument is a named parameter 850: (otherwise it is an extra parameter matching an ellipsis). */ 851: 852: /* On the 68000 all args are pushed, except if -mregparm is specified 853: then the first two words of arguments are passed in d0, d1. 854: *NOTE* -mregparm does not work. 855: It exists only to test register calling conventions. */ 856: 857: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 858: ((TARGET_REGPARM && (CUM) < 8) ? gen_rtx (REG, (MODE), (CUM) / 4) : 0) 859: 860: /* For an arg passed partly in registers and partly in memory, 861: this is the number of registers used. 862: For args passed entirely in registers or entirely in memory, zero. */ 863: 864: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 865: ((TARGET_REGPARM && (CUM) < 8 \ 866: && 8 < ((CUM) + ((MODE) == BLKmode \ 867: ? int_size_in_bytes (TYPE) \ 868: : GET_MODE_SIZE (MODE)))) \ 869: ? 2 - (CUM) / 4 : 0) 870: 871: /* Generate the assembly code for function entry. */ 872: #define FUNCTION_PROLOGUE(FILE, SIZE) output_function_prologue(FILE, SIZE) 873: 874: /* Output assembler code to FILE to increment profiler label # LABELNO 875: for profiling a function entry. */ 876: 877: #define FUNCTION_PROFILER(FILE, LABELNO) \ 878: asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) 879: 880: /* Output assembler code to FILE to initialize this source file's 881: basic block profiling info, if that has not already been done. */ 882: 883: #define FUNCTION_BLOCK_PROFILER(FILE, LABELNO) \ 884: asm_fprintf (FILE, "\ttstl %LLPBX0\n\tbne %LLPI%d\n\tpea %LLPBX0\n\tjsr %U__bb_init_func\n\taddql %I4,%Rsp\n%LLPI%d:\n", \ 885: LABELNO, LABELNO); 886: 887: /* Output assembler code to FILE to increment the entry-count for 888: the BLOCKNO'th basic block in this source file. */ 889: 890: #define BLOCK_PROFILER(FILE, BLOCKNO) \ 891: asm_fprintf (FILE, "\taddql %I1,%LLPBX2+%d\n", 4 * BLOCKNO) 892: 893: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 894: the stack pointer does not matter. The value is tested only in 895: functions that have frame pointers. 896: No definition is equivalent to always zero. */ 897: 898: #define EXIT_IGNORE_STACK 1 899: 900: /* Generate the assembly code for function exit. */ 901: #define FUNCTION_EPILOGUE(FILE, SIZE) output_function_epilogue (FILE, SIZE) 902: 903: /* This is a hook for other tm files to change. */ 904: /* #define FUNCTION_EXTRA_EPILOGUE(FILE, SIZE) */ 905: 906: /* Determine if the epilogue should be output as RTL. 907: You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 908: #define USE_RETURN_INSN use_return_insn () 909: 910: /* Store in the variable DEPTH the initial difference between the 911: frame pointer reg contents and the stack pointer reg contents, 912: as of the start of the function body. This depends on the layout 913: of the fixed parts of the stack frame and on how registers are saved. 914: 915: On the 68k, if we have a frame, we must add one word to its length 916: to allow for the place that a6 is stored when we do have a frame pointer. 917: Otherwise, we would need to compute the offset from the frame pointer 918: of a local variable as a function of frame_pointer_needed, which 919: is hard. */ 920: 921: #define INITIAL_FRAME_POINTER_OFFSET(DEPTH) \ 922: { int regno; \ 923: int offset = -4; \ 924: for (regno = 16; regno < FIRST_PSEUDO_REGISTER; regno++) \ 925: if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 926: offset += 12; \ 927: for (regno = 0; regno < 16; regno++) \ 928: if (regs_ever_live[regno] && ! call_used_regs[regno]) \ 929: offset += 4; \ 930: (DEPTH) = (offset + ((get_frame_size () + 3) & -4) \ 931: + (get_frame_size () == 0 ? 0 : 4)); \ 932: } 933: 934: /* Output assembler code for a block containing the constant parts 935: of a trampoline, leaving space for the variable parts. */ 936: 937: /* On the 68k, the trampoline looks like this: 938: mov @#.,a0 939: jsr @#___trampoline 940: jsr @#___trampoline 941: .long STATIC 942: .long FUNCTION 943: The reason for having three jsr insns is so that an entire line 944: of the instruction cache is filled in a predictable way 945: that will always be the same. 946: 947: We always use the assembler label ___trampoline 948: regardless of whether the system adds underscores. */ 949: 950: #define TRAMPOLINE_TEMPLATE(FILE) \ 951: { \ 952: ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x207c)); \ 953: ASM_OUTPUT_SHORT (FILE, const0_rtx); \ 954: ASM_OUTPUT_SHORT (FILE, const0_rtx); \ 955: ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4eb9)); \ 956: ASM_OUTPUT_INT (FILE, gen_rtx (SYMBOL_REF, SImode, "*___trampoline"));\ 957: ASM_OUTPUT_SHORT (FILE, gen_rtx (CONST_INT, VOIDmode, 0x4eb9)); \ 958: ASM_OUTPUT_INT (FILE, gen_rtx (SYMBOL_REF, SImode, "*___trampoline"));\ 959: ASM_OUTPUT_SHORT (FILE, const0_rtx); \ 960: ASM_OUTPUT_SHORT (FILE, const0_rtx); \ 961: ASM_OUTPUT_SHORT (FILE, const0_rtx); \ 962: ASM_OUTPUT_SHORT (FILE, const0_rtx); \ 963: } 964: 965: /* Length in units of the trampoline for entering a nested function. */ 966: 967: #define TRAMPOLINE_SIZE 26 968: 969: /* Alignment required for a trampoline. 16 is used to find the 970: beginning of a line in the instruction cache. */ 971: 972: #define TRAMPOLINE_ALIGN 16 973: 974: /* Emit RTL insns to initialize the variable parts of a trampoline. 975: FNADDR is an RTX for the address of the function's pure code. 976: CXT is an RTX for the static chain value for the function. */ 977: 978: #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ 979: { \ 980: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 2)), TRAMP); \ 981: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 18)), CXT); \ 982: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (TRAMP, 22)), FNADDR); \ 983: } 984: 985: /* This is the library routine that is used 986: to transfer control from the trampoline 987: to the actual nested function. */ 988: 989: /* A colon is used with no explicit operands 990: to cause the template string to be scanned for %-constructs. */ 991: /* The function name __transfer_from_trampoline is not actually used. 992: The function definition just permits use of "asm with operands" 993: (though the operand list is empty). */ 994: #define TRANSFER_FROM_TRAMPOLINE \ 995: void \ 996: __transfer_from_trampoline () \ 997: { \ 998: register char *a0 asm ("%a0"); \ 999: asm (GLOBAL_ASM_OP " ___trampoline"); \ 1000: asm ("___trampoline:"); \ 1001: asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ 1002: asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ 1003: asm ("rts":); \ 1004: } 1005: 1006: /* Addressing modes, and classification of registers for them. */ 1007: 1008: #define HAVE_POST_INCREMENT 1009: /* #define HAVE_POST_DECREMENT */ 1010: 1011: #define HAVE_PRE_DECREMENT 1012: /* #define HAVE_PRE_INCREMENT */ 1013: 1014: /* Macros to check register numbers against specific register classes. */ 1015: 1016: /* These assume that REGNO is a hard or pseudo reg number. 1017: They give nonzero only if REGNO is a hard reg of the suitable class 1018: or a pseudo reg currently allocated to a suitable hard reg. 1019: Since they use reg_renumber, they are safe only once reg_renumber 1020: has been allocated, which happens in local-alloc.c. */ 1021: 1022: #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1023: ((REGNO) < 16 || (unsigned) reg_renumber[REGNO] < 16) 1024: #define REGNO_OK_FOR_BASE_P(REGNO) \ 1025: (((REGNO) ^ 010) < 8 || (unsigned) (reg_renumber[REGNO] ^ 010) < 8) 1026: #define REGNO_OK_FOR_DATA_P(REGNO) \ 1027: ((REGNO) < 8 || (unsigned) reg_renumber[REGNO] < 8) 1028: #define REGNO_OK_FOR_FP_P(REGNO) \ 1029: (((REGNO) ^ 020) < 8 || (unsigned) (reg_renumber[REGNO] ^ 020) < 8) 1030: #ifdef SUPPORT_SUN_FPA 1031: #define REGNO_OK_FOR_FPA_P(REGNO) \ 1032: (((REGNO) >= 24 && (REGNO) < 56) || (reg_renumber[REGNO] >= 24 && reg_renumber[REGNO] < 56)) 1033: #endif 1034: 1035: /* Now macros that check whether X is a register and also, 1036: strictly, whether it is in a specified class. 1037: 1038: These macros are specific to the 68000, and may be used only 1039: in code for printing assembler insns and in conditions for 1040: define_optimization. */ 1041: 1042: /* 1 if X is a data register. */ 1043: 1044: #define DATA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_DATA_P (REGNO (X))) 1045: 1046: /* 1 if X is an fp register. */ 1047: 1048: #define FP_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FP_P (REGNO (X))) 1049: 1050: /* 1 if X is an address register */ 1051: 1052: #define ADDRESS_REG_P(X) (REG_P (X) && REGNO_OK_FOR_BASE_P (REGNO (X))) 1053: 1054: #ifdef SUPPORT_SUN_FPA 1055: /* 1 if X is a register in the Sun FPA. */ 1056: #define FPA_REG_P(X) (REG_P (X) && REGNO_OK_FOR_FPA_P (REGNO (X))) 1057: #else 1058: /* Answer must be no if we don't have an FPA. */ 1059: #define FPA_REG_P(X) 0 1060: #endif 1061: 1062: /* Maximum number of registers that can appear in a valid memory address. */ 1063: 1064: #define MAX_REGS_PER_ADDRESS 2 1065: 1066: /* Recognize any constant value that is a valid address. */ 1067: 1068: #define CONSTANT_ADDRESS_P(X) \ 1069: (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1070: || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1071: || GET_CODE (X) == HIGH) 1072: 1073: /* Nonzero if the constant value X is a legitimate general operand. 1074: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1075: 1076: #define LEGITIMATE_CONSTANT_P(X) 1 1077: 1078: /* Nonzero if the constant value X is a legitimate general operand 1079: when generating PIC code. It is given that flag_pic is on and 1080: that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 1081: 1082: #define LEGITIMATE_PIC_OPERAND_P(X) \ 1.1.1.4 ! root 1083: ((! symbolic_operand (X, VOIDmode) \ ! 1084: && ! (GET_CODE (X) == CONST_DOUBLE && CONST_DOUBLE_MEM (X) \ ! 1085: && GET_CODE (CONST_DOUBLE_MEM (X)) == MEM \ ! 1086: && symbolic_operand (XEXP (CONST_DOUBLE_MEM (X), 0), \ ! 1087: VOIDmode))) \ ! 1088: || (GET_CODE (X) == SYMBOL_REF && SYMBOL_REF_FLAG (X))) 1.1 root 1089: 1090: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1091: and check its validity for a certain class. 1092: We have two alternate definitions for each of them. 1093: The usual definition accepts all pseudo regs; the other rejects 1094: them unless they have been allocated suitable hard regs. 1095: The symbol REG_OK_STRICT causes the latter definition to be used. 1096: 1097: Most source files want to accept pseudo regs in the hope that 1098: they will get allocated to the class that the insn wants them to be in. 1099: Source files for reload pass need to be strict. 1100: After reload, it makes no difference, since pseudo regs have 1101: been eliminated by then. */ 1102: 1103: #ifndef REG_OK_STRICT 1104: 1105: /* Nonzero if X is a hard reg that can be used as an index 1106: or if it is a pseudo reg. */ 1107: #define REG_OK_FOR_INDEX_P(X) ((REGNO (X) ^ 020) >= 8) 1108: /* Nonzero if X is a hard reg that can be used as a base reg 1109: or if it is a pseudo reg. */ 1110: #define REG_OK_FOR_BASE_P(X) ((REGNO (X) & ~027) != 0) 1111: 1112: #else 1113: 1114: /* Nonzero if X is a hard reg that can be used as an index. */ 1115: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X)) 1116: /* Nonzero if X is a hard reg that can be used as a base reg. */ 1117: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1118: 1119: #endif 1120: 1121: /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1122: that is a valid memory address for an instruction. 1123: The MODE argument is the machine mode for the MEM expression 1124: that wants to use this address. 1125: 1126: When generating PIC, an address involving a SYMBOL_REF is legitimate 1127: if and only if it is the sum of pic_offset_table_rtx and the SYMBOL_REF. 1128: We use LEGITIMATE_PIC_OPERAND_P to throw out the illegitimate addresses, 1129: and we explicitly check for the sum of pic_offset_table_rtx and a SYMBOL_REF. 1130: 1131: Likewise for a LABEL_REF when generating PIC. 1132: 1133: The other macros defined here are used only in GO_IF_LEGITIMATE_ADDRESS. */ 1134: 1.1.1.2 root 1135: /* Allow SUBREG everywhere we allow REG. This results in better code. It 1136: also makes function inlining work when inline functions are called with 1137: arguments that are SUBREGs. */ 1138: 1139: #define LEGITIMATE_BASE_REG_P(X) \ 1140: ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 1141: || (GET_CODE (X) == SUBREG \ 1142: && GET_CODE (SUBREG_REG (X)) == REG \ 1143: && REG_OK_FOR_BASE_P (SUBREG_REG (X)))) 1144: 1.1 root 1145: #define INDIRECTABLE_1_ADDRESS_P(X) \ 1146: ((CONSTANT_ADDRESS_P (X) && (!flag_pic || LEGITIMATE_PIC_OPERAND_P (X))) \ 1.1.1.2 root 1147: || LEGITIMATE_BASE_REG_P (X) \ 1.1 root 1148: || ((GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_INC) \ 1.1.1.2 root 1149: && LEGITIMATE_BASE_REG_P (XEXP (X, 0))) \ 1.1 root 1150: || (GET_CODE (X) == PLUS \ 1.1.1.2 root 1151: && LEGITIMATE_BASE_REG_P (XEXP (X, 0)) \ 1.1 root 1152: && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1153: && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000) \ 1154: || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ 1155: && flag_pic && GET_CODE (XEXP (X, 1)) == SYMBOL_REF) \ 1156: || (GET_CODE (X) == PLUS && XEXP (X, 0) == pic_offset_table_rtx \ 1157: && flag_pic && GET_CODE (XEXP (X, 1)) == LABEL_REF)) \ 1158: 1159: #if 0 1160: /* This should replace the last two (non-pic) lines 1161: except that Sun's assembler does not seem to handle such operands. */ 1162: && (TARGET_68020 ? CONSTANT_ADDRESS_P (XEXP (X, 1)) \ 1163: : (GET_CODE (XEXP (X, 1)) == CONST_INT \ 1164: && ((unsigned) INTVAL (XEXP (X, 1)) + 0x8000) < 0x10000)))) 1165: #endif 1166: 1167: 1168: #define GO_IF_NONINDEXED_ADDRESS(X, ADDR) \ 1169: { if (INDIRECTABLE_1_ADDRESS_P (X)) goto ADDR; } 1170: 1171: /* Only labels on dispatch tables are valid for indexing from. */ 1172: #define GO_IF_INDEXABLE_BASE(X, ADDR) \ 1173: { rtx temp; \ 1174: if (GET_CODE (X) == LABEL_REF \ 1175: && (temp = next_nonnote_insn (XEXP (X, 0))) != 0 \ 1176: && GET_CODE (temp) == JUMP_INSN \ 1177: && (GET_CODE (PATTERN (temp)) == ADDR_VEC \ 1178: || GET_CODE (PATTERN (temp)) == ADDR_DIFF_VEC)) \ 1179: goto ADDR; \ 1.1.1.2 root 1180: if (LEGITIMATE_BASE_REG_P (X)) goto ADDR; } 1.1 root 1181: 1182: #define GO_IF_INDEXING(X, ADDR) \ 1183: { if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 0))) \ 1184: { GO_IF_INDEXABLE_BASE (XEXP (X, 1), ADDR); } \ 1185: if (GET_CODE (X) == PLUS && LEGITIMATE_INDEX_P (XEXP (X, 1))) \ 1186: { GO_IF_INDEXABLE_BASE (XEXP (X, 0), ADDR); } } 1187: 1188: #define GO_IF_INDEXED_ADDRESS(X, ADDR) \ 1189: { GO_IF_INDEXING (X, ADDR); \ 1190: if (GET_CODE (X) == PLUS) \ 1191: { if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 1192: && (unsigned) INTVAL (XEXP (X, 1)) + 0x80 < 0x100) \ 1193: { rtx go_temp = XEXP (X, 0); GO_IF_INDEXING (go_temp, ADDR); } \ 1194: if (GET_CODE (XEXP (X, 0)) == CONST_INT \ 1195: && (unsigned) INTVAL (XEXP (X, 0)) + 0x80 < 0x100) \ 1196: { rtx go_temp = XEXP (X, 1); GO_IF_INDEXING (go_temp, ADDR); } } } 1197: 1198: #define LEGITIMATE_INDEX_REG_P(X) \ 1199: ((GET_CODE (X) == REG && REG_OK_FOR_INDEX_P (X)) \ 1200: || (GET_CODE (X) == SIGN_EXTEND \ 1201: && GET_CODE (XEXP (X, 0)) == REG \ 1202: && GET_MODE (XEXP (X, 0)) == HImode \ 1.1.1.2 root 1203: && REG_OK_FOR_INDEX_P (XEXP (X, 0))) \ 1204: || (GET_CODE (X) == SUBREG \ 1205: && GET_CODE (SUBREG_REG (X)) == REG \ 1206: && REG_OK_FOR_INDEX_P (SUBREG_REG (X)))) 1.1 root 1207: 1208: #define LEGITIMATE_INDEX_P(X) \ 1209: (LEGITIMATE_INDEX_REG_P (X) \ 1210: || (TARGET_68020 && GET_CODE (X) == MULT \ 1211: && LEGITIMATE_INDEX_REG_P (XEXP (X, 0)) \ 1212: && GET_CODE (XEXP (X, 1)) == CONST_INT \ 1213: && (INTVAL (XEXP (X, 1)) == 2 \ 1214: || INTVAL (XEXP (X, 1)) == 4 \ 1215: || INTVAL (XEXP (X, 1)) == 8))) 1216: 1.1.1.2 root 1217: /* If pic, we accept INDEX+LABEL, which is what do_tablejump makes. */ 1218: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1219: { GO_IF_NONINDEXED_ADDRESS (X, ADDR); \ 1220: GO_IF_INDEXED_ADDRESS (X, ADDR); \ 1221: if (flag_pic && MODE == CASE_VECTOR_MODE && GET_CODE (X) == PLUS \ 1222: && LEGITIMATE_INDEX_P (XEXP (X, 0)) \ 1223: && GET_CODE (XEXP (X, 1)) == LABEL_REF) \ 1224: goto ADDR; } 1225: 1226: /* Don't call memory_address_noforce for the address to fetch 1227: the switch offset. This address is ok as it stands (see above), 1228: but memory_address_noforce would alter it. */ 1229: #define PIC_CASE_VECTOR_ADDRESS(index) index 1.1 root 1230: 1231: /* Try machine-dependent ways of modifying an illegitimate address 1232: to be legitimate. If we find one, return the new, valid address. 1233: This macro is used in only one place: `memory_address' in explow.c. 1234: 1235: OLDX is the address as it was before break_out_memory_refs was called. 1236: In some cases it is useful to look at this to decide what needs to be done. 1237: 1238: MODE and WIN are passed so that this macro can use 1239: GO_IF_LEGITIMATE_ADDRESS. 1240: 1241: It is always safe for this macro to do nothing. It exists to recognize 1242: opportunities to optimize the output. 1243: 1244: For the 68000, we handle X+REG by loading X into a register R and 1245: using R+REG. R will go in an address reg and indexing will be used. 1246: However, if REG is a broken-out memory address or multiplication, 1247: nothing needs to be done because REG can certainly go in an address reg. */ 1248: 1249: #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } 1250: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) \ 1251: { register int ch = (X) != (OLDX); \ 1252: if (GET_CODE (X) == PLUS) \ 1253: { int copied = 0; \ 1254: if (GET_CODE (XEXP (X, 0)) == MULT) \ 1255: { COPY_ONCE (X); XEXP (X, 0) = force_operand (XEXP (X, 0), 0);} \ 1256: if (GET_CODE (XEXP (X, 1)) == MULT) \ 1257: { COPY_ONCE (X); XEXP (X, 1) = force_operand (XEXP (X, 1), 0);} \ 1258: if (ch && GET_CODE (XEXP (X, 1)) == REG \ 1259: && GET_CODE (XEXP (X, 0)) == REG) \ 1260: goto WIN; \ 1261: if (ch) { GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN); } \ 1262: if (GET_CODE (XEXP (X, 0)) == REG \ 1263: || (GET_CODE (XEXP (X, 0)) == SIGN_EXTEND \ 1264: && GET_CODE (XEXP (XEXP (X, 0), 0)) == REG \ 1265: && GET_MODE (XEXP (XEXP (X, 0), 0)) == HImode)) \ 1266: { register rtx temp = gen_reg_rtx (Pmode); \ 1267: register rtx val = force_operand (XEXP (X, 1), 0); \ 1268: emit_move_insn (temp, val); \ 1269: COPY_ONCE (X); \ 1270: XEXP (X, 1) = temp; \ 1271: goto WIN; } \ 1272: else if (GET_CODE (XEXP (X, 1)) == REG \ 1273: || (GET_CODE (XEXP (X, 1)) == SIGN_EXTEND \ 1274: && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ 1275: && GET_MODE (XEXP (XEXP (X, 1), 0)) == HImode)) \ 1276: { register rtx temp = gen_reg_rtx (Pmode); \ 1277: register rtx val = force_operand (XEXP (X, 0), 0); \ 1278: emit_move_insn (temp, val); \ 1279: COPY_ONCE (X); \ 1280: XEXP (X, 0) = temp; \ 1281: goto WIN; }}} 1282: 1283: /* Go to LABEL if ADDR (a legitimate address expression) 1284: has an effect that depends on the machine mode it is used for. 1285: On the 68000, only predecrement and postincrement address depend thus 1286: (the amount of decrement or increment being the length of the operand). */ 1287: 1288: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1289: if (GET_CODE (ADDR) == POST_INC || GET_CODE (ADDR) == PRE_DEC) goto LABEL 1290: 1291: /* Specify the machine mode that this machine uses 1292: for the index in the tablejump instruction. */ 1293: #define CASE_VECTOR_MODE HImode 1294: 1295: /* Define this if the tablejump instruction expects the table 1296: to contain offsets from the address of the table. 1297: Do not define this if the table should contain absolute addresses. */ 1298: #define CASE_VECTOR_PC_RELATIVE 1299: 1300: /* Specify the tree operation to be used to convert reals to integers. */ 1301: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR 1302: 1303: /* This is the kind of divide that is easiest to do in the general case. */ 1304: #define EASY_DIV_EXPR TRUNC_DIV_EXPR 1305: 1306: /* Define this as 1 if `char' should by default be signed; else as 0. */ 1307: #define DEFAULT_SIGNED_CHAR 1 1308: 1309: /* Don't cse the address of the function being compiled. */ 1310: #define NO_RECURSIVE_FUNCTION_CSE 1311: 1312: /* Max number of bytes we can move from memory to memory 1313: in one reasonably fast instruction. */ 1314: #define MOVE_MAX 4 1315: 1316: /* Define this if zero-extension is slow (more than one real instruction). */ 1317: #define SLOW_ZERO_EXTEND 1318: 1319: /* Nonzero if access to memory by bytes is slow and undesirable. */ 1320: #define SLOW_BYTE_ACCESS 0 1321: 1322: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1323: is done just by pretending it is already truncated. */ 1324: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1325: 1326: /* We assume that the store-condition-codes instructions store 0 for false 1327: and some other value for true. This is the value stored for true. */ 1328: 1329: #define STORE_FLAG_VALUE -1 1330: 1331: /* When a prototype says `char' or `short', really pass an `int'. */ 1332: #define PROMOTE_PROTOTYPES 1333: 1334: /* Specify the machine mode that pointers have. 1335: After generation of rtl, the compiler makes no further distinction 1336: between pointers and any other objects of this machine mode. */ 1337: #define Pmode SImode 1338: 1339: /* A function address in a call instruction 1340: is a byte address (for indexing purposes) 1341: so give the MEM rtx a byte's mode. */ 1342: #define FUNCTION_MODE QImode 1343: 1344: /* Compute the cost of computing a constant rtl expression RTX 1345: whose rtx-code is CODE. The body of this macro is a portion 1346: of a switch statement. If the code is computed here, 1347: return it with a return statement. Otherwise, break from the switch. */ 1348: 1349: #define CONST_COSTS(RTX,CODE,OUTER_CODE) \ 1350: case CONST_INT: \ 1351: /* Constant zero is super cheap due to clr instruction. */ \ 1352: if (RTX == const0_rtx) return 0; \ 1.1.1.4 ! root 1353: /* if ((OUTER_CODE) == SET) */ \ ! 1354: return const_int_cost(RTX); \ 1.1 root 1355: case CONST: \ 1356: case LABEL_REF: \ 1357: case SYMBOL_REF: \ 1358: return 3; \ 1359: case CONST_DOUBLE: \ 1360: return 5; 1361: 1362: /* Compute the cost of various arithmetic operations. 1363: These are vaguely right for a 68020. */ 1364: /* The costs for long multiply have been adjusted to 1365: work properly in synth_mult on the 68020, 1366: relative to an average of the time for add and the time for shift, 1367: taking away a little more because sometimes move insns are needed. */ 1.1.1.4 ! root 1368: /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */ 1.1 root 1369: #define MULL_COST (TARGET_68040 ? 5 : 13) 1.1.1.4 ! root 1370: #define MULW_COST (TARGET_68040 ? 3 : TARGET_68020 ? 8 : 5) ! 1371: #define DIVW_COST (TARGET_68020 ? 27 : 12) 1.1 root 1372: 1373: #define RTX_COSTS(X,CODE,OUTER_CODE) \ 1374: case PLUS: \ 1375: /* An lea costs about three times as much as a simple add. */ \ 1376: if (GET_MODE (X) == SImode \ 1377: && GET_CODE (XEXP (X, 0)) == REG \ 1378: && GET_CODE (XEXP (X, 1)) == MULT \ 1379: && GET_CODE (XEXP (XEXP (X, 1), 0)) == REG \ 1380: && GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT \ 1381: && (INTVAL (XEXP (XEXP (X, 1), 1)) == 2 \ 1382: || INTVAL (XEXP (XEXP (X, 1), 1)) == 4 \ 1383: || INTVAL (XEXP (XEXP (X, 1), 1)) == 8)) \ 1384: return COSTS_N_INSNS (3); /* lea an@(dx:l:i),am */ \ 1385: break; \ 1386: case ASHIFT: \ 1387: case ASHIFTRT: \ 1.1.1.4 ! root 1388: case LSHIFTRT: \ ! 1389: if (! TARGET_68020) \ ! 1390: { \ ! 1391: if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ ! 1392: { \ ! 1393: if (INTVAL (XEXP (X, 1)) < 16) \ ! 1394: return COSTS_N_INSNS (2) + INTVAL (XEXP (X, 1)) / 2; \ ! 1395: else \ ! 1396: /* We're using clrw + swap for these cases. */ \ ! 1397: return COSTS_N_INSNS (4) + (INTVAL (XEXP (X, 1)) - 16) / 2; \ ! 1398: } \ ! 1399: return COSTS_N_INSNS (10); /* worst case */ \ ! 1400: } \ 1.1 root 1401: /* A shift by a big integer takes an extra instruction. */ \ 1402: if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 1403: && (INTVAL (XEXP (X, 1)) == 16)) \ 1404: return COSTS_N_INSNS (2); /* clrw;swap */ \ 1405: if (GET_CODE (XEXP (X, 1)) == CONST_INT \ 1406: && !(INTVAL (XEXP (X, 1)) > 0 \ 1407: && INTVAL (XEXP (X, 1)) <= 8)) \ 1408: return COSTS_N_INSNS (3); /* lsr #i,dn */ \ 1409: break; \ 1410: case MULT: \ 1.1.1.4 ! root 1411: if ((GET_CODE (XEXP (X, 0)) == ZERO_EXTEND \ ! 1412: || GET_CODE (XEXP (X, 0)) == SIGN_EXTEND) \ ! 1413: && GET_MODE (X) == SImode) \ ! 1414: return COSTS_N_INSNS (MULW_COST); \ 1.1.1.2 root 1415: if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ 1.1 root 1416: return COSTS_N_INSNS (MULW_COST); \ 1417: else \ 1418: return COSTS_N_INSNS (MULL_COST); \ 1419: case DIV: \ 1420: case UDIV: \ 1421: case MOD: \ 1422: case UMOD: \ 1423: if (GET_MODE (X) == QImode || GET_MODE (X) == HImode) \ 1.1.1.4 ! root 1424: return COSTS_N_INSNS (DIVW_COST); /* div.w */ \ 1.1 root 1425: return COSTS_N_INSNS (43); /* div.l */ 1426: 1427: /* Tell final.c how to eliminate redundant test instructions. */ 1428: 1429: /* Here we define machine-dependent flags and fields in cc_status 1430: (see `conditions.h'). */ 1431: 1432: /* Set if the cc value is actually in the 68881, so a floating point 1433: conditional branch must be output. */ 1434: #define CC_IN_68881 04000 1435: 1436: /* Store in cc_status the expressions that the condition codes will 1437: describe after execution of an instruction whose pattern is EXP. 1438: Do not alter them if the instruction would not alter the cc's. */ 1439: 1440: /* On the 68000, all the insns to store in an address register fail to 1441: set the cc's. However, in some cases these instructions can make it 1442: possibly invalid to use the saved cc's. In those cases we clear out 1443: some or all of the saved cc's so they won't be used. */ 1444: 1445: #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) 1446: 1447: #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ 1448: { if (cc_prev_status.flags & CC_IN_68881) \ 1449: return FLOAT; \ 1450: if (cc_prev_status.flags & CC_NO_OVERFLOW) \ 1451: return NO_OV; \ 1452: return NORMAL; } 1453: 1454: /* Control the assembler format that we output. */ 1455: 1456: /* Output at beginning of assembler file. */ 1457: 1458: #define ASM_FILE_START(FILE) \ 1459: fprintf (FILE, "#NO_APP\n"); 1460: 1461: /* Output to assembler file text saying following lines 1462: may contain character constants, extra white space, comments, etc. */ 1463: 1464: #define ASM_APP_ON "#APP\n" 1465: 1466: /* Output to assembler file text saying following lines 1467: no longer contain unusual constructs. */ 1468: 1469: #define ASM_APP_OFF "#NO_APP\n" 1470: 1471: /* Output before read-only data. */ 1472: 1473: #define TEXT_SECTION_ASM_OP ".text" 1474: 1475: /* Output before writable data. */ 1476: 1477: #define DATA_SECTION_ASM_OP ".data" 1478: 1479: /* Here are four prefixes that are used by asm_fprintf to 1480: facilitate customization for alternate assembler syntaxes. 1481: Machines with no likelihood of an alternate syntax need not 1482: define these and need not use asm_fprintf. */ 1483: 1484: /* The prefix for register names. Note that REGISTER_NAMES 1485: is supposed to include this prefix. */ 1486: 1487: #define REGISTER_PREFIX "" 1488: 1489: /* The prefix for local labels. You should be able to define this as 1490: an empty string, or any arbitrary string (such as ".", ".L%", etc) 1491: without having to make any other changes to account for the specific 1492: definition. Note it is a string literal, not interpreted by printf 1493: and friends. */ 1494: 1495: #define LOCAL_LABEL_PREFIX "" 1496: 1497: /* The prefix to add to user-visible assembler symbols. */ 1498: 1499: #define USER_LABEL_PREFIX "_" 1500: 1501: /* The prefix for immediate operands. */ 1502: 1503: #define IMMEDIATE_PREFIX "#" 1504: 1505: /* How to refer to registers in assembler output. 1506: This sequence is indexed by compiler's hard-register-number (see above). */ 1507: 1508: #ifndef SUPPORT_SUN_FPA 1509: 1510: #define REGISTER_NAMES \ 1511: {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ 1512: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ 1513: "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7" } 1514: 1515: #else /* SUPPORTED_SUN_FPA */ 1516: 1517: #define REGISTER_NAMES \ 1518: {"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", \ 1519: "a0", "a1", "a2", "a3", "a4", "a5", "a6", "sp", \ 1520: "fp0", "fp1", "fp2", "fp3", "fp4", "fp5", "fp6", "fp7", \ 1521: "fpa0", "fpa1", "fpa2", "fpa3", "fpa4", "fpa5", "fpa6", "fpa7", \ 1522: "fpa8", "fpa9", "fpa10", "fpa11", "fpa12", "fpa13", "fpa14", "fpa15", \ 1523: "fpa16", "fpa17", "fpa18", "fpa19", "fpa20", "fpa21", "fpa22", "fpa23", \ 1524: "fpa24", "fpa25", "fpa26", "fpa27", "fpa28", "fpa29", "fpa30", "fpa31" } 1525: 1526: #endif /* defined SUPPORT_SUN_FPA */ 1527: 1528: /* How to renumber registers for dbx and gdb. 1529: On the Sun-3, the floating point registers have numbers 1530: 18 to 25, not 16 to 23 as they do in the compiler. */ 1531: 1532: #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) 1533: 1534: /* This is how to output the definition of a user-level label named NAME, 1535: such as the label on a static function or variable NAME. */ 1536: 1537: #define ASM_OUTPUT_LABEL(FILE,NAME) \ 1538: do { assemble_name (FILE, NAME); fputs (":\n", FILE); } while (0) 1539: 1540: /* This is how to output a command to make the user-level label named NAME 1541: defined for reference from other files. */ 1542: 1543: #define GLOBAL_ASM_OP ".globl" 1544: #define ASM_GLOBALIZE_LABEL(FILE,NAME) \ 1545: do { fprintf (FILE, "%s ", GLOBAL_ASM_OP); \ 1546: assemble_name (FILE, NAME); \ 1547: fputs ("\n", FILE);} while (0) 1548: 1549: /* This is how to output a reference to a user-level label named NAME. 1550: `assemble_name' uses this. */ 1551: 1552: #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 1553: asm_fprintf (FILE, "%0U%s", NAME) 1554: 1555: /* This is how to output an internal numbered label where 1556: PREFIX is the class of label and NUM is the number within the class. */ 1557: 1558: #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ 1559: asm_fprintf (FILE, "%0L%s%d:\n", PREFIX, NUM) 1560: 1561: /* This is how to store into the string LABEL 1562: the symbol_ref name of an internal numbered label where 1563: PREFIX is the class of label and NUM is the number within the class. 1564: This is suitable for output with `assemble_name'. */ 1565: 1566: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 1567: sprintf (LABEL, "*%s%s%d", LOCAL_LABEL_PREFIX, PREFIX, NUM) 1568: 1569: /* This is how to output a `long double' extended real constant. */ 1570: 1571: #define ASM_OUTPUT_LONG_DOUBLE(FILE,VALUE) \ 1572: do { long l[3]; \ 1573: REAL_VALUE_TO_TARGET_LONG_DOUBLE (VALUE, l); \ 1574: if (sizeof (int) == sizeof (long)) \ 1575: fprintf (FILE, "\t.long 0x%x,0x%x,0x%x\n", l[0], l[1], l[2]); \ 1576: else \ 1577: fprintf (FILE, "\t.long 0x%lx,0x%lx,0x%lx\n", l[0], l[1], l[2]); \ 1578: } while (0) 1579: 1580: /* This is how to output an assembler line defining a `double' constant. */ 1581: 1582: #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ 1583: do { char dstr[30]; \ 1584: REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ 1585: fprintf (FILE, "\t.double 0r%s\n", dstr); \ 1586: } while (0) 1587: 1588: /* This is how to output an assembler line defining a `float' constant. */ 1589: 1590: #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ 1591: do { long l; \ 1592: REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ 1593: if (sizeof (int) == sizeof (long)) \ 1594: fprintf (FILE, "\t.long 0x%x\n", l); \ 1595: else \ 1596: fprintf (FILE, "\t.long 0x%lx\n", l); \ 1597: } while (0) 1598: 1599: /* This is how to output an assembler line defining an `int' constant. */ 1600: 1601: #define ASM_OUTPUT_INT(FILE,VALUE) \ 1602: ( fprintf (FILE, "\t.long "), \ 1603: output_addr_const (FILE, (VALUE)), \ 1604: fprintf (FILE, "\n")) 1605: 1606: /* Likewise for `char' and `short' constants. */ 1607: 1608: #define ASM_OUTPUT_SHORT(FILE,VALUE) \ 1609: ( fprintf (FILE, "\t.word "), \ 1610: output_addr_const (FILE, (VALUE)), \ 1611: fprintf (FILE, "\n")) 1612: 1613: #define ASM_OUTPUT_CHAR(FILE,VALUE) \ 1614: ( fprintf (FILE, "\t.byte "), \ 1615: output_addr_const (FILE, (VALUE)), \ 1616: fprintf (FILE, "\n")) 1617: 1618: /* This is how to output an assembler line for a numeric constant byte. */ 1619: 1620: #define ASM_OUTPUT_BYTE(FILE,VALUE) \ 1621: fprintf (FILE, "\t.byte 0x%x\n", (VALUE)) 1622: 1623: /* This is how to output an insn to push a register on the stack. 1624: It need not be very fast code. */ 1625: 1626: #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 1627: asm_fprintf (FILE, "\tmovel %s,%Rsp@-\n", reg_names[REGNO]) 1628: 1629: /* This is how to output an insn to pop a register from the stack. 1630: It need not be very fast code. */ 1631: 1632: #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 1633: asm_fprintf (FILE, "\tmovel %Rsp@+,%s\n", reg_names[REGNO]) 1634: 1635: /* This is how to output an element of a case-vector that is absolute. 1636: (The 68000 does not use such vectors, 1637: but we must define this macro anyway.) */ 1638: 1639: #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1640: asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) 1641: 1642: /* This is how to output an element of a case-vector that is relative. */ 1643: 1644: #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ 1645: asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) 1646: 1647: /* This is how to output an assembler line 1648: that says to advance the location counter 1649: to a multiple of 2**LOG bytes. */ 1650: 1651: /* We don't have a way to align to more than a two-byte boundary, so do the 1652: best we can and don't complain. */ 1653: #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1654: if ((LOG) >= 1) \ 1655: fprintf (FILE, "\t.even\n"); 1656: 1657: #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 1658: fprintf (FILE, "\t.skip %u\n", (SIZE)) 1659: 1660: /* This says how to output an assembler line 1661: to define a global common symbol. */ 1662: 1663: #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 1664: ( fputs (".comm ", (FILE)), \ 1665: assemble_name ((FILE), (NAME)), \ 1666: fprintf ((FILE), ",%u\n", (ROUNDED))) 1667: 1668: /* This says how to output an assembler line 1669: to define a local common symbol. */ 1670: 1671: #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 1672: ( fputs (".lcomm ", (FILE)), \ 1673: assemble_name ((FILE), (NAME)), \ 1674: fprintf ((FILE), ",%u\n", (ROUNDED))) 1675: 1676: /* Store in OUTPUT a string (made with alloca) containing 1677: an assembler-name for a local static variable named NAME. 1678: LABELNO is an integer which is different for each call. */ 1679: 1680: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \ 1681: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \ 1682: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO))) 1683: 1684: /* Define the parentheses used to group arithmetic operations 1685: in assembler code. */ 1686: 1687: #define ASM_OPEN_PAREN "(" 1688: #define ASM_CLOSE_PAREN ")" 1689: 1690: /* Define results of standard character escape sequences. */ 1691: #define TARGET_BELL 007 1692: #define TARGET_BS 010 1693: #define TARGET_TAB 011 1694: #define TARGET_NEWLINE 012 1695: #define TARGET_VT 013 1696: #define TARGET_FF 014 1697: #define TARGET_CR 015 1698: 1699: /* Output a float value (represented as a C double) as an immediate operand. 1700: This macro is a 68k-specific macro. */ 1701: 1702: #define ASM_OUTPUT_FLOAT_OPERAND(CODE,FILE,VALUE) \ 1703: do { \ 1704: if (CODE == 'f') \ 1705: { \ 1706: char dstr[30]; \ 1707: REAL_VALUE_TO_DECIMAL (VALUE, "%.9g", dstr); \ 1708: asm_fprintf ((FILE), "%I0r%s", dstr); \ 1709: } \ 1710: else \ 1711: { \ 1712: long l; \ 1713: REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ 1714: if (sizeof (int) == sizeof (long)) \ 1715: asm_fprintf ((FILE), "%I0x%x", l); \ 1716: else \ 1717: asm_fprintf ((FILE), "%I0x%lx", l); \ 1718: } \ 1719: } while (0) 1720: 1721: /* Output a double value (represented as a C double) as an immediate operand. 1722: This macro is a 68k-specific macro. */ 1723: #define ASM_OUTPUT_DOUBLE_OPERAND(FILE,VALUE) \ 1724: do { char dstr[30]; \ 1725: REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ 1726: asm_fprintf (FILE, "%I0r%s", dstr); \ 1727: } while (0) 1728: 1729: /* Note, long double immediate operands are not actually 1730: generated by m68k.md. */ 1731: #define ASM_OUTPUT_LONG_DOUBLE_OPERAND(FILE,VALUE) \ 1732: do { char dstr[30]; \ 1733: REAL_VALUE_TO_DECIMAL (VALUE, "%.20g", dstr); \ 1734: asm_fprintf (FILE, "%I0r%s", dstr); \ 1735: } while (0) 1736: 1737: /* Print operand X (an rtx) in assembler syntax to file FILE. 1738: CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1739: For `%' followed by punctuation, CODE is the punctuation and X is null. 1740: 1741: On the 68000, we use several CODE characters: 1742: '.' for dot needed in Motorola-style opcode names. 1743: '-' for an operand pushing on the stack: 1744: sp@-, -(sp) or -(%sp) depending on the style of syntax. 1745: '+' for an operand pushing on the stack: 1746: sp@+, (sp)+ or (%sp)+ depending on the style of syntax. 1747: '@' for a reference to the top word on the stack: 1748: sp@, (sp) or (%sp) depending on the style of syntax. 1749: '#' for an immediate operand prefix (# in MIT and Motorola syntax 1750: but & in SGS syntax). 1751: '!' for the fpcr register (used in some float-to-fixed conversions). 1752: '$' for the letter `s' in an op code, but only on the 68040. 1753: '&' for the letter `d' in an op code, but only on the 68040. 1754: '/' for register prefix needed by longlong.h. 1755: 1756: 'b' for byte insn (no effect, on the Sun; this is for the ISI). 1757: 'd' to force memory addressing to be absolute, not relative. 1758: 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 1759: 'w' for FPA insn (print a CONST_DOUBLE as a SunFPA constant rather 1760: than directly). Second part of 'y' below. 1761: 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), 1762: or print pair of registers as rx:ry. 1763: 'y' for a FPA insn (print pair of registers as rx:ry). This also outputs 1764: CONST_DOUBLE's as SunFPA constant RAM registers if 1765: possible, so it should not be used except for the SunFPA. */ 1766: 1767: #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 1768: ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ 1769: || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ 1770: || (CODE) == '$' || (CODE) == '&' || (CODE) == '/') 1771: 1772: /* A C compound statement to output to stdio stream STREAM the 1773: assembler syntax for an instruction operand X. X is an RTL 1774: expression. 1775: 1776: CODE is a value that can be used to specify one of several ways 1777: of printing the operand. It is used when identical operands 1778: must be printed differently depending on the context. CODE 1779: comes from the `%' specification that was used to request 1780: printing of the operand. If the specification was just `%DIGIT' 1781: then CODE is 0; if the specification was `%LTR DIGIT' then CODE 1782: is the ASCII code for LTR. 1783: 1784: If X is a register, this macro should print the register's name. 1785: The names can be found in an array `reg_names' whose type is 1786: `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. 1787: 1788: When the machine description has a specification `%PUNCT' (a `%' 1789: followed by a punctuation character), this macro is called with 1790: a null pointer for X and the punctuation character for CODE. 1791: 1792: See m68k.c for the m68k specific codes. */ 1793: 1794: #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 1795: 1796: /* A C compound statement to output to stdio stream STREAM the 1797: assembler syntax for an instruction operand that is a memory 1798: reference whose address is ADDR. ADDR is an RTL expression. 1799: 1800: On some machines, the syntax for a symbolic address depends on 1801: the section that the address refers to. On these machines, 1802: define the macro `ENCODE_SECTION_INFO' to store the information 1803: into the `symbol_ref', and then check for it here. */ 1804: 1805: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 1806: 1807: 1.1.1.2 root 1808: /* Definitions for generating bytecode */ 1809: 1810: /* Just so it's known this target is supported by the bytecode generator. 1811: If this define isn't found anywhere in the target config files, then 1812: dummy stubs are supplied by bytecode.h, and any attempt to use 1813: -fbytecode will result in an error message. */ 1814: 1815: #define TARGET_SUPPORTS_BYTECODE 1816: 1817: /* Minimal segment alignment within sections is 8 units. */ 1818: #define MACHINE_SEG_ALIGN 3 1819: 1820: /* Integer alignment is two units. */ 1821: #define INT_ALIGN 2 1822: 1823: /* Pointer alignment is eight units. */ 1824: #define PTR_ALIGN 3 1825: 1826: /* Global symbols begin with `_' */ 1827: #define NAMES_HAVE_UNDERSCORES 1828: 1829: /* BC_xxx below are similar to their ASM_xxx counterparts above. */ 1830: #define BC_GLOBALIZE_LABEL(FP, NAME) bc_globalize_label(NAME) 1831: 1832: #define BC_OUTPUT_COMMON(FP, NAME, SIZE, ROUNDED) \ 1833: do { bc_emit_common(NAME, ROUNDED); bc_globalize_label(NAME); } while (0) 1834: 1835: #define BC_OUTPUT_LOCAL(FP, NAME, SIZE, ROUNDED) \ 1836: bc_emit_common(NAME, ROUNDED) 1837: 1838: #define BC_OUTPUT_ALIGN(FP, ALIGN) bc_align(ALIGN) 1839: 1840: #define BC_OUTPUT_LABEL(FP, NAME) bc_emit_labeldef(NAME) 1841: 1842: #define BC_OUTPUT_SKIP(FP, SIZE) bc_emit_skip(SIZE) 1843: 1844: #define BC_OUTPUT_LABELREF(FP, NAME) \ 1845: do { \ 1846: char *foo = (char *) xmalloc(strlen(NAME) + 2); \ 1847: strcpy(foo, "_"); \ 1848: strcat(foo, NAME); \ 1849: bc_emit_labelref (foo); \ 1850: free (foo); \ 1851: } while (0) 1852: 1853: #define BC_OUTPUT_FLOAT(FP, VAL) \ 1854: do { \ 1855: float F = VAL; \ 1856: bc_emit ((char *) &F, sizeof F); \ 1857: } while (0) 1858: 1859: #define BC_OUTPUT_DOUBLE(FP, VAL) \ 1860: do { \ 1861: double D = VAL; \ 1862: bc_emit ((char *) &D, sizeof D); \ 1863: } while (0) 1864: 1865: #define BC_OUTPUT_BYTE(FP, VAL) \ 1866: do { \ 1867: char C = VAL; \ 1868: bc_emit (&C, 1); \ 1869: } while (0) 1870: 1871: 1872: #define BC_OUTPUT_FILE ASM_OUTPUT_FILE 1873: #define BC_OUTPUT_ASCII ASM_OUTPUT_ASCII 1874: #define BC_OUTPUT_IDENT ASM_OUTPUT_IDENT 1875: 1876: /* Same as XSTR, but for bytecode */ 1877: #define BCXSTR(RTX) ((RTX)->bc_label) 1878: 1879: 1880: /* Flush bytecode buffer onto file */ 1881: #define BC_WRITE_FILE(FP) \ 1882: { \ 1883: fprintf (FP, ".text\n"); \ 1884: bc_seg_write (bc_text_seg, FP); \ 1885: fprintf(FP, "\n.data\n"); \ 1886: bc_seg_write (bc_data_seg, FP); \ 1887: bc_sym_write (FP); /* do .globl, .bss, etc. */ \ 1888: } 1889: 1890: /* Write one symbol */ 1891: #define BC_WRITE_SEGSYM(SEGSYM, FP) \ 1892: { \ 1893: prsym (FP, (SEGSYM)->sym->name); \ 1894: fprintf (FP, ":\n"); \ 1895: } 1896: 1897: 1898: /* Write one reloc entry */ 1899: #define BC_WRITE_RELOC_ENTRY(SEGRELOC, FP, OFFSET) \ 1900: { \ 1901: fprintf (FP, "\t.long "); \ 1902: prsym (FP, (SEGRELOC)->sym->name); \ 1903: fprintf (FP, " + %d\n", OFFSET); \ 1904: } 1905: 1906: /* Start new line of bytecodes */ 1907: #define BC_START_BYTECODE_LINE(FP) \ 1908: { \ 1909: fprintf (FP, "\t.byte"); \ 1910: } 1911: 1912: /* Write one bytecode */ 1913: #define BC_WRITE_BYTECODE(SEP, VAL, FP) \ 1914: { \ 1915: fprintf (FP, "%c0x%02X", (SEP), (VAL) & 0xff); \ 1916: } 1917: 1918: /* Write one bytecode RTL entry */ 1919: #define BC_WRITE_RTL(R, FP) \ 1920: { \ 1921: fprintf (FP, "%s+%d/0x%08X\n", (R)->label, (R)->offset, (R)->bc_label); \ 1922: } 1923: 1924: 1925: /* Emit function entry trampoline */ 1926: #define BC_EMIT_TRAMPOLINE(TRAMPSEG, CALLINFO) \ 1927: { \ 1928: short insn; \ 1929: \ 1930: /* Push a reference to the callinfo structure. */ \ 1931: insn = 0x4879; /* pea xxx.L */ \ 1932: seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \ 1933: seg_refsym (TRAMPSEG, CALLINFO, 0); \ 1934: \ 1935: /* Call __interp, pop arguments, and return. */ \ 1936: insn = 0x4eb9; /* jsr xxx.L */ \ 1937: seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \ 1938: seg_refsym (TRAMPSEG, "__callint", 0); \ 1939: insn = 0x588f; /* addql #4, sp */ \ 1940: seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \ 1941: insn = 0x4e75; /* rts */ \ 1942: seg_data (TRAMPSEG, (char *) &insn, sizeof insn); \ 1943: } 1944: 1945: 1946: 1947: #if 0 1948: #define VALIDATE_STACK() if (stack_depth < 0) abort (); 1949: #else 1950: #if 0 1951: #define VALIDATE_STACK() \ 1952: fprintf (stderr, " %%%d%%", stack_depth); 1953: #endif 1954: #endif 1955: 1.1 root 1956: /* Define functions defined in aux-output.c and used in templates. */ 1957: 1.1.1.4 ! root 1958: extern char *output_move_const_into_data_reg (); 1.1 root 1959: extern char *output_move_double (); 1960: extern char *output_move_const_single (); 1961: extern char *output_move_const_double (); 1962: extern char *output_btst (); 1.1.1.4 ! root 1963: extern char *output_scc_di (); 1.1 root 1964: 1965: /* 1966: Local variables: 1967: version-control: t 1968: End: 1969: */
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