--- gcc/config/m68k/m68k.md	2018/04/24 18:10:23	1.1.1.1
+++ gcc/config/m68k/m68k.md	2018/04/24 18:20:44	1.1.1.3
@@ -1,6 +1,5 @@
-;;- Machine description for GNU compiler
-;;- Motorola 68000 Version
-;;   Copyright (C) 1987, 1988, 1993 Free Software Foundation, Inc.
+;;- Machine description for GNU compiler, Motorola 68000 Version
+;;  Copyright (C) 1987, 1988, 1993, 1994 Free Software Foundation, Inc.
 
 ;; This file is part of GNU CC.
 
@@ -387,7 +386,11 @@
   "*
 {
   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+#ifdef SGS_CMP_ORDER
+    return \"cmpm%.l %0,%1\";
+#else
     return \"cmpm%.l %1,%0\";
+#endif
   if (REG_P (operands[1])
       || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
     { cc_status.flags |= CC_REVERSED;
@@ -406,13 +409,17 @@
 
 (define_insn "cmphi"
   [(set (cc0)
-	(compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m")
-		 (match_operand:HI 1 "general_operand" "d,rnm,m,n")))]
+	(compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
+		 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
   ""
   "*
 {
   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+#ifdef SGS_CMP_ORDER
+    return \"cmpm%.w %0,%1\";
+#else
     return \"cmpm%.w %1,%0\";
+#endif
   if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
       || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
     { cc_status.flags |= CC_REVERSED;
@@ -437,7 +444,11 @@
   "*
 {
   if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
+#ifdef SGS_CMP_ORDER
+    return \"cmpm%.b %0,%1\";
+#else
     return \"cmpm%.b %1,%0\";
+#endif
   if (REG_P (operands[1])
       || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
     { cc_status.flags |= CC_REVERSED;
@@ -587,7 +598,7 @@
 			    (const_int 1)
 			    (minus:SI (const_int 7)
 				      (and:SI
-				       (match_operand:SI 1 "general_operand" "d")
+				       (match_operand:SI 1 "register_operand" "d")
 				       (const_int 7)))))]
   ""
   "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
@@ -597,7 +608,7 @@
 			    (const_int 1)
 			    (minus:SI (const_int 31)
 				      (and:SI
-				       (match_operand:SI 1 "general_operand" "d")
+				       (match_operand:SI 1 "register_operand" "d")
 				       (const_int 31)))))]
   ""
   "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
@@ -607,9 +618,8 @@
 (define_insn ""
   [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md")
 			    (const_int 1)
-			    (match_operand:SI 1 "general_operand" "i")))]
-  "GET_CODE (operands[1]) == CONST_INT
-   && (unsigned) INTVAL (operands[1]) < 8"
+			    (match_operand:SI 1 "const_int_operand" "n")))]
+  "(unsigned) INTVAL (operands[1]) < 8"
   "*
 {
   operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1]));
@@ -619,8 +629,8 @@
 (define_insn ""
   [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do")
 			    (const_int 1)
-			    (match_operand:SI 1 "general_operand" "i")))]
-  "GET_CODE (operands[1]) == CONST_INT"
+			    (match_operand:SI 1 "const_int_operand" "n")))]
+  ""
   "*
 {
   if (GET_CODE (operands[0]) == MEM)
@@ -643,10 +653,8 @@
 ;; to reload the constant into a data register.
 (define_insn ""
   [(set (match_operand:SI 0 "push_operand" "=m")
-	(match_operand:SI 1 "general_operand" "J"))]
-  "GET_CODE (operands[1]) == CONST_INT
-   && INTVAL (operands[1]) >= -0x8000
-   && INTVAL (operands[1]) < 0x8000"
+	(match_operand:SI 1 "const_int_operand" "J"))]
+  "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
   "*
 {
   if (operands[1] == const0_rtx)
@@ -751,45 +759,18 @@
 	  return \"moveq %1,%0\";
 #endif
 	}
-#ifndef NO_ADDSUB_Q
-      else if (DATA_REG_P (operands[0])
-	       /* Do this with a moveq #N-8, dreg; addq #8,dreg */
-	       && INTVAL (operands[1]) < 136
-	       && INTVAL (operands[1]) >= 128)
-        {
-	  operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8);
-#if defined(MOTOROLA) && !defined(CRDS)
-          return \"moveq%.l %1,%0\;addq%.w %#8,%0\";
-#else
-	  return \"moveq %1,%0\;addq%.w %#8,%0\";
-#endif
-	}
-      else if (DATA_REG_P (operands[0])
-	       /* Do this with a moveq #N+8, dreg; subq #8,dreg */
-	       && INTVAL (operands[1]) < -128
-	       && INTVAL (operands[1]) >= -136)
-        {
-	  operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) + 8);
-#if defined(MOTOROLA) && !defined(CRDS)
-          return \"moveq%.l %1,%0;subq%.w %#8,%0\";
-#else
-	  return \"moveq %1,%0;subq%.w %#8,%0\";
-#endif
-	}
-#endif
       else if (DATA_REG_P (operands[0])
-	       /* If N is in the right range and is even, then use
-	          moveq #N/2, dreg; addl dreg,dreg */
-	       && INTVAL (operands[1]) > 127
-	       && INTVAL (operands[1]) <= 254
-	       && INTVAL (operands[1]) % 2 == 0)
+		/* if -256 < N < 256 but N is not in range for a moveq
+		   N^ff will be, so use moveq #N^ff, dreg; not.b dreg.	*/
+	       && INTVAL (operands[1]) < 256
+	       && INTVAL (operands[1]) >= -256)
         {
-	  operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) / 2);
+	  operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) ^ 0xff);
 #if defined(MOTOROLA) && !defined(CRDS)
-          return \"moveq%.l %1,%0\;add%.w %0,%0\";
+          return \"moveq%.l %1,%0\;not%.b %0\";
 #else
-	  return \"moveq %1,%0\;add%.w %0,%0\";
-#endif
+	  return \"moveq %1,%0\;not%.b %0\";
+#endif	 
 	}
       else if (ADDRESS_REG_P (operands[0])
 	       && INTVAL (operands[1]) < 0x8000
@@ -848,19 +829,15 @@
   /* Recognize the insn before a tablejump, one that refers
      to a table of offsets.  Such an insn will need to refer
      to a label on the insn.  So output one.  Use the label-number
-     of the table of offsets to generate this label.  */
+     of the table of offsets to generate this label.  This code,
+     and similar code below, assumes that there will be at most one
+     reference to each table.  */
   if (GET_CODE (operands[1]) == MEM
       && GET_CODE (XEXP (operands[1], 0)) == PLUS
-      && (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF
-	  || GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF)
-      && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS
-      && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) != PLUS)
-    {
-      rtx labelref;
-      if (GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF)
-	labelref = XEXP (XEXP (operands[1], 0), 0);
-      else
-	labelref = XEXP (XEXP (operands[1], 0), 1);
+      && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF
+      && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS)
+    {
+      rtx labelref = XEXP (XEXP (operands[1], 0), 1);
 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
 #ifdef SGS
       asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
@@ -916,7 +893,8 @@
      of several bytes a byte at a time.  */
   if (GET_CODE (operands[0]) == MEM
       && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
-      && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx)
+      && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx
+      && ! ADDRESS_REG_P (operands[1]))
     {
       xoperands[1] = operands[1];
       xoperands[2]
@@ -946,7 +924,7 @@
 	     and pop d0/1.  */
 	  if (! reg_mentioned_p (stack_pointer_rtx, operands[1]))
 	    {
-	      if (refers_to_regno_p (0, 1, operands[1], NULL_RTX))
+	      if (! refers_to_regno_p (0, 1, operands[1], NULL_RTX))
 		return \"move%.l %/d0,%-\;move%.b %1,%/d0\;move%.l %/d0,%0\;move%.l %+,%/d0\";
 	      else
 		return \"move%.l %/d1,%-\;move%.b %1,%/d1\;move%.l %/d1,%0\;move%.l %+,%/d1\";
@@ -996,7 +974,7 @@
 	     and pop d0/1.  */
 	  if (! reg_mentioned_p (stack_pointer_rtx, operands[0]))
 	    {
-	      if (refers_to_regno_p (0, 1, operands[0], NULL_RTX))
+	      if (! refers_to_regno_p (0, 1, operands[0], NULL_RTX))
 		return \"move%.l %/d0,%-\;move%.l %1,%/d0\;move%.b %/d0,%0\;move%.l %+,%/d0\";
 	      else
 		return \"move%.l %/d1,%-\;move%.l %1,%/d1\;move%.b %/d1,%0\;move%.l %+,%/d1\";
@@ -1109,14 +1087,14 @@
 }")
 
 (define_insn "movdf"
-  [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>,y,rm,x,!x,!rm")
-	(match_operand:DF 1 "general_operand" "rf,m,rofE<>,rmE,y,xH,rm,x"))]
+  [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
+	(match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
 ;  [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
 ;	(match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
   ""
   "*
 {
-  if (which_alternative == 6)
+  if (which_alternative == 7)
     return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
   if (FPA_REG_P (operands[0]))
     {
@@ -1217,7 +1195,7 @@
 ")
 
 (define_insn ""
-  [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,&rf,&rof<>")
+  [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
 	(match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
   "! TARGET_68881"
   "*
@@ -1260,7 +1238,7 @@
 ;; movdi can apply to fp regs in some cases
 (define_insn "movdi"
   ;; Let's see if it really still needs to handle fp regs, and, if so, why.
-  [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,y,rm,!*x,!rm")
+  [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
 	(match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
 ;  [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
 ;	(match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
@@ -1744,7 +1722,7 @@
 	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
    (clobber (match_scratch:SI 2 "=d"))
    (clobber (match_scratch:SI 3 "=d"))]
-  "TARGET_68040"
+  "TARGET_68881 && TARGET_68040"
   "*
 {
   CC_STATUS_INIT;
@@ -1756,7 +1734,7 @@
 	(fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
    (clobber (match_scratch:SI 2 "=d"))
    (clobber (match_scratch:SI 3 "=d"))]
-  "TARGET_68040"
+  "TARGET_68881 && TARGET_68040"
   "*
 {
   CC_STATUS_INIT;
@@ -1768,7 +1746,7 @@
 	(fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
    (clobber (match_scratch:SI 2 "=d"))
    (clobber (match_scratch:SI 3 "=d"))]
-  "TARGET_68040"
+  "TARGET_68881 && TARGET_68040"
   "*
 {
   CC_STATUS_INIT;
@@ -2276,65 +2254,11 @@
 ;; subtract instructions
 
 (define_insn "subsi3"
-  [(set (match_operand:SI 0 "general_operand" "=m,r,!a,?d")
-	(minus:SI (match_operand:SI 1 "general_operand" "0,0,a,mrIKs")
-		  (match_operand:SI 2 "general_operand" "dIKs,mrIKs,J,0")))]
+  [(set (match_operand:SI 0 "general_operand" "=m,r")
+	(minus:SI (match_operand:SI 1 "general_operand" "0,0")
+		  (match_operand:SI 2 "general_operand" "ds,mrs")))]
   ""
-  "*
-{
-  if (! operands_match_p (operands[0], operands[1]))
-    {
-      if (operands_match_p (operands[0], operands[2]))
-	{
-#ifndef NO_ADDSUB_Q
-	  if (GET_CODE (operands[1]) == CONST_INT)
-	    {
-	      if (INTVAL (operands[1]) > 0
-		  && INTVAL (operands[1]) <= 8)
-		return \"subq%.l %1,%0\;neg%.l %0\";
-	    }
-#endif
-	  return \"sub%.l %1,%0\;neg%.l %0\";
-	}
-      /* This case is matched by J, but negating -0x8000
-         in an lea would give an invalid displacement.
-	 So do this specially.  */
-      if (INTVAL (operands[2]) == -0x8000)
-	return \"move%.l %1,%0\;sub%.l %2,%0\";
-#ifdef SGS
-      return \"lea %n2(%1),%0\";
-#else
-#ifdef MOTOROLA
-      return \"lea (%n2,%1),%0\";
-#else /* not MOTOROLA (MIT syntax) */
-      return \"lea %1@(%n2),%0\";
-#endif /* not MOTOROLA */
-#endif /* not SGS */
-    }
-  if (GET_CODE (operands[2]) == CONST_INT)
-    {
-#ifndef NO_ADDSUB_Q
-      if (INTVAL (operands[2]) > 0
-	  && INTVAL (operands[2]) <= 8)
-	return \"subq%.l %2,%0\";
-      /* Using two subqw for 8 < N <= 16 being subtracted from an
-	 address register is faster on all but 68000 */
-      if (INTVAL (operands[2]) > 8
-	  && INTVAL (operands[2]) <= 16
-	  && ADDRESS_REG_P (operands[0])
-	  && TARGET_68020)
-	{
-	  operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8);
-	  return \"subq%.w %#8,%0\;subq%.w %2,%0\";
-	}
-#endif
-      if (ADDRESS_REG_P (operands[0])
-	  && INTVAL (operands[2]) >= -0x8000
-	  && INTVAL (operands[2]) < 0x8000)
-	return \"sub%.w %2,%0\";
-    }
-  return \"sub%.l %2,%0\";
-}")
+  "sub%.l %2,%0")
 
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=a")
@@ -2575,9 +2499,9 @@
 	  (mult:SI (match_operand:SI 1 "register_operand" "")
 		   (match_operand:SI 2 "nonimmediate_operand" "")))
      (set (subreg:SI (match_dup 0) 0)
-	  (truncate:SI (ashift:DI (mult:DI (sign_extend:DI (match_dup 1))
-					   (sign_extend:DI (match_dup 2)))
-				  (const_int 32))))])]
+	  (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
+					     (sign_extend:DI (match_dup 2)))
+				    (const_int 32))))])]
   "TARGET_68020"
   "")
 
@@ -2586,9 +2510,9 @@
 	(mult:SI (match_operand:SI 1 "register_operand" "%0")
 		 (match_operand:SI 2 "nonimmediate_operand" "dm")))
    (set (match_operand:SI 3 "register_operand" "=d")
-	(truncate:SI (ashift:DI (mult:DI (sign_extend:DI (match_dup 1))
-					 (sign_extend:DI (match_dup 2)))
-				(const_int 32))))]
+	(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
+					   (sign_extend:DI (match_dup 2)))
+				  (const_int 32))))]
   "TARGET_68020"
   "muls%.l %2,%3:%0")
 
@@ -2597,9 +2521,9 @@
 	(mult:SI (match_operand:SI 1 "register_operand" "%0")
 		 (match_operand:SI 2 "const_int_operand" "n")))
    (set (match_operand:SI 3 "register_operand" "=d")
-	(truncate:SI (ashift:DI (mult:DI (sign_extend:DI (match_dup 1))
-					 (match_dup 2))
-				(const_int 32))))]
+	(truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
+					   (match_dup 2))
+				  (const_int 32))))]
   "TARGET_68020
    /* This test is a noop on 32 bit machines,
       but important for a cross-compiler hosted on 64-bit machines.  */
@@ -2607,6 +2531,94 @@
    && INTVAL (operands[2]) >= -0x80000000"
   "muls%.l %2,%3:%0")
 
+(define_expand "umulsi3_highpart"
+  [(parallel
+    [(set (match_operand:SI 0 "register_operand" "")
+	  (truncate:SI
+	   (lshiftrt:DI
+	    (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
+		     (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
+	    (const_int 32))))
+     (clobber (match_dup 3))])]
+  "TARGET_68020"
+  "
+{
+  operands[3] = gen_reg_rtx (SImode);
+  if (CONSTANT_P (operands[2]))
+    {
+      /* We have to rearrange the operand order for the matching constraints.  */
+      emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
+					     operands[1], operands[2]));
+      DONE;
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(truncate:SI
+	 (lshiftrt:DI
+	  (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
+		   (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
+	  (const_int 32))))
+   (clobber (match_operand:SI 1 "register_operand" "=d"))]
+  "TARGET_68020"
+  "mulu%.l %3,%0:%1")
+
+(define_insn "const_umulsi3_highpart"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(truncate:SI
+	 (lshiftrt:DI
+	  (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
+		   (match_operand:DI 3 "immediate_operand" "i"))
+	  (const_int 32))))
+   (clobber (match_operand:SI 1 "register_operand" "=d"))]
+  "TARGET_68020"
+  "mulu%.l %3,%0:%1")
+
+(define_expand "smulsi3_highpart"
+  [(parallel
+    [(set (match_operand:SI 0 "register_operand" "")
+	  (truncate:SI
+	   (lshiftrt:DI
+	    (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
+		     (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
+	    (const_int 32))))
+     (clobber (match_dup 3))])]
+  "TARGET_68020"
+  "
+{
+  operands[3] = gen_reg_rtx (SImode);
+  if (CONSTANT_P (operands[2]))
+    {
+      /* We have to rearrange the operand order for the matching constraints.  */
+      emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
+					     operands[1], operands[2]));
+      DONE;
+    }
+}")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(truncate:SI
+	 (lshiftrt:DI
+	  (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
+		   (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
+	  (const_int 32))))
+   (clobber (match_operand:SI 1 "register_operand" "=d"))]
+  "TARGET_68020"
+  "muls%.l %3,%0:%1")
+
+(define_insn "const_smulsi3_highpart"
+  [(set (match_operand:SI 0 "register_operand" "=d")
+	(truncate:SI
+	 (lshiftrt:DI
+	  (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
+		   (match_operand:DI 3 "immediate_operand" "i"))
+	  (const_int 32))))
+   (clobber (match_operand:SI 1 "register_operand" "=d"))]
+  "TARGET_68020"
+  "muls%.l %3,%0:%1")
+
 (define_expand "muldf3"
   [(set (match_operand:DF 0 "general_operand" "")
 	(mult:DF (match_operand:DF 1 "general_operand" "")
@@ -2715,35 +2727,39 @@
 #endif
 }")
 
-(define_insn "divhisi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI
-	 (div:SI
-	  (match_operand:SI 1 "general_operand" "0")
-	  (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
-  ""
-  "*
-{
-#ifdef MOTOROLA
-  return \"divs%.w %2,%0\";
-#else
-  return \"divs %2,%0\";
-#endif
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI (div:SI (match_operand:SI 1 "general_operand" "0")
-			     (match_operand:SI 2 "const_int_operand" "n"))))]
-  ""
-  "*
-{
-#ifdef MOTOROLA
-  return \"divs%.w %2,%0\";
-#else
-  return \"divs %2,%0\";
-#endif
-}")
+;; These patterns don't work because the divs instruction is undefined if
+;; the quotient is more than 16 bits.  This valid C would be miscompiled:
+;; int n; short d; unsigned short q; ... q = (unsigned int) (n / d);
+;; Imagine what happens when n = 100000 and d = 1.
+;;(define_insn "divhisi3"
+;;  [(set (match_operand:HI 0 "general_operand" "=d")
+;;	(truncate:HI
+;;	 (div:SI
+;;	  (match_operand:SI 1 "general_operand" "0")
+;;	  (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
+;;  ""
+;;  "*
+;;{
+;;#ifdef MOTOROLA
+;;  return \"divs%.w %2,%0\";
+;;#else
+;;  return \"divs %2,%0\";
+;;#endif
+;;}")
+
+;;(define_insn ""
+;;  [(set (match_operand:HI 0 "general_operand" "=d")
+;;	(truncate:HI (div:SI (match_operand:SI 1 "general_operand" "0")
+;;			     (match_operand:SI 2 "const_int_operand" "n"))))]
+;;  ""
+;;  "*
+;;{
+;;#ifdef MOTOROLA
+;;  return \"divs%.w %2,%0\";
+;;#else
+;;  return \"divs %2,%0\";
+;;#endif
+;;}")
 
 (define_insn "udivhi3"
   [(set (match_operand:HI 0 "general_operand" "=d")
@@ -2759,35 +2775,36 @@
 #endif
 }")
 
-(define_insn "udivhisi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI
-	 (udiv:SI
-	  (match_operand:SI 1 "general_operand" "0")
-	  (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
-  ""
-  "*
-{
-#ifdef MOTOROLA
-  return \"divu%.w %2,%0\";
-#else
-  return \"divu %2,%0\";
-#endif
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI (udiv:SI (match_operand:SI 1 "general_operand" "0")
-			      (match_operand:SI 2 "const_int_operand" "n"))))]
-  ""
-  "*
-{
-#ifdef MOTOROLA
-  return \"divu%.w %2,%0\";
-#else
-  return \"divu %2,%0\";
-#endif
-}")
+;; See comment before divhisi3 why these are commented out.
+;;(define_insn "udivhisi3"
+;;  [(set (match_operand:HI 0 "general_operand" "=d")
+;;	(truncate:HI
+;;	 (udiv:SI
+;;	  (match_operand:SI 1 "general_operand" "0")
+;;	  (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
+;;  ""
+;;  "*
+;;{
+;;#ifdef MOTOROLA
+;;  return \"divu%.w %2,%0\";
+;;#else
+;;  return \"divu %2,%0\";
+;;#endif
+;;}")
+
+;;(define_insn ""
+;;  [(set (match_operand:HI 0 "general_operand" "=d")
+;;	(truncate:HI (udiv:SI (match_operand:SI 1 "general_operand" "0")
+;;			      (match_operand:SI 2 "const_int_operand" "n"))))]
+;;  ""
+;;  "*
+;;{
+;;#ifdef MOTOROLA
+;;  return \"divu%.w %2,%0\";
+;;#else
+;;  return \"divu %2,%0\";
+;;#endif
+;;}")
 
 (define_expand "divdf3"
   [(set (match_operand:DF 0 "general_operand" "")
@@ -2888,39 +2905,40 @@
 #endif
 }")
 
-(define_insn "modhisi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI
-	 (mod:SI
-	  (match_operand:SI 1 "general_operand" "0")
-	  (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
-  ""
-  "*
-{
-  /* The swap insn produces cc's that don't correspond to the result.  */
-  CC_STATUS_INIT;
-#ifdef MOTOROLA
-  return \"divs%.w %2,%0\;swap %0\";
-#else
-  return \"divs %2,%0\;swap %0\";
-#endif
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI (mod:SI (match_operand:SI 1 "general_operand" "0")
-			     (match_operand:SI 2 "const_int_operand" "n"))))]
-  ""
-  "*
-{
-  /* The swap insn produces cc's that don't correspond to the result.  */
-  CC_STATUS_INIT;
-#ifdef MOTOROLA
-  return \"divs%.w %2,%0\;swap %0\";
-#else
-  return \"divs %2,%0\;swap %0\";
-#endif
-}")
+;; See comment before divhisi3 why these are commented out.
+;;(define_insn "modhisi3"
+;;  [(set (match_operand:HI 0 "general_operand" "=d")
+;;	(truncate:HI
+;;	 (mod:SI
+;;	  (match_operand:SI 1 "general_operand" "0")
+;;	  (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
+;;  ""
+;;  "*
+;;{
+;;  /* The swap insn produces cc's that don't correspond to the result.  */
+;;  CC_STATUS_INIT;
+;;#ifdef MOTOROLA
+;;  return \"divs%.w %2,%0\;swap %0\";
+;;#else
+;;  return \"divs %2,%0\;swap %0\";
+;;#endif
+;;}")
+
+;;(define_insn ""
+;;  [(set (match_operand:HI 0 "general_operand" "=d")
+;;	(truncate:HI (mod:SI (match_operand:SI 1 "general_operand" "0")
+;;			     (match_operand:SI 2 "const_int_operand" "n"))))]
+;;  ""
+;;  "*
+;;{
+;;  /* The swap insn produces cc's that don't correspond to the result.  */
+;;  CC_STATUS_INIT;
+;;#ifdef MOTOROLA
+;;  return \"divs%.w %2,%0\;swap %0\";
+;;#else
+;;  return \"divs %2,%0\;swap %0\";
+;;#endif
+;;}")
 
 (define_insn "umodhi3"
   [(set (match_operand:HI 0 "general_operand" "=d")
@@ -2938,39 +2956,40 @@
 #endif
 }")
 
-(define_insn "umodhisi3"
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI
-	 (umod:SI
-	  (match_operand:SI 1 "general_operand" "0")
-	  (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
-  ""
-  "*
-{
-  /* The swap insn produces cc's that don't correspond to the result.  */
-  CC_STATUS_INIT;
-#ifdef MOTOROLA
-  return \"divu%.w %2,%0\;swap %0\";
-#else
-  return \"divu %2,%0\;swap %0\";
-#endif
-}")
-
-(define_insn ""
-  [(set (match_operand:HI 0 "general_operand" "=d")
-	(truncate:HI (umod:SI (match_operand:SI 1 "general_operand" "0")
-			      (match_operand:SI 2 "const_int_operand" "n"))))]
-  ""
-  "*
-{
-  /* The swap insn produces cc's that don't correspond to the result.  */
-  CC_STATUS_INIT;
-#ifdef MOTOROLA
-  return \"divu%.w %2,%0\;swap %0\";
-#else
-  return \"divu %2,%0\;swap %0\";
-#endif
-}")
+;; See comment before divhisi3 why these are commented out.
+;;(define_insn "umodhisi3"
+;;  [(set (match_operand:HI 0 "general_operand" "=d")
+;;	(truncate:HI
+;;	 (umod:SI
+;;	  (match_operand:SI 1 "general_operand" "0")
+;;	  (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))]
+;;  ""
+;;  "*
+;;{
+;;  /* The swap insn produces cc's that don't correspond to the result.  */
+;;  CC_STATUS_INIT;
+;;#ifdef MOTOROLA
+;;  return \"divu%.w %2,%0\;swap %0\";
+;;#else
+;;  return \"divu %2,%0\;swap %0\";
+;;#endif
+;;}")
+
+;;(define_insn ""
+;;  [(set (match_operand:HI 0 "general_operand" "=d")
+;;	(truncate:HI (umod:SI (match_operand:SI 1 "general_operand" "0")
+;;			      (match_operand:SI 2 "const_int_operand" "n"))))]
+;;  ""
+;;  "*
+;;{
+;;  /* The swap insn produces cc's that don't correspond to the result.  */
+;;  CC_STATUS_INIT;
+;;#ifdef MOTOROLA
+;;  return \"divu%.w %2,%0\;swap %0\";
+;;#else
+;;  return \"divu %2,%0\;swap %0\";
+;;#endif
+;;}")
 
 (define_insn "divmodsi4"
   [(set (match_operand:SI 0 "general_operand" "=d")
@@ -3041,7 +3060,8 @@
         }
       else
         {
-          operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));          operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
+	  operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8));
+	  operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8);
         }
       /* This does not set condition codes in a standard way.  */
       CC_STATUS_INIT;
@@ -3430,8 +3450,8 @@
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ashift:SI (match_operand:SI 1 "register_operand" "0")
-		   (match_operand:SI 2 "immediate_operand" "i")))]
-  "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)"
+		   (const_int 16)))]
+  ""
   "*
 {
   CC_STATUS_INIT;
@@ -3443,8 +3463,8 @@
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ashift:SI (match_operand:SI 1 "register_operand" "0")
-		   (match_operand:SI 2 "immediate_operand" "i")))]
-  "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT
+		   (match_operand:SI 2 "const_int_operand" "n")))]
+  "(! TARGET_68020
     && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
   "*
 {
@@ -3499,8 +3519,8 @@
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" 
+		     (const_int 16)))]
+  ""
   "swap %0\;ext%.l %0")
 
 ;; On the 68000, this makes faster code in a special case.
@@ -3508,8 +3528,8 @@
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT
+		     (match_operand:SI 2 "const_int_operand" "n")))]
+  "(! TARGET_68020
     && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
   "*
 {
@@ -3522,10 +3542,7 @@
 	(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
 		     (match_operand:SI 2 "general_operand" "dI")))]
   ""
-  "*
-{
-  return \"asr%.l %2,%0\";
-}")
+  "asr%.l %2,%0")
 
 (define_insn "ashrhi3"
   [(set (match_operand:HI 0 "register_operand" "=d")
@@ -3557,82 +3574,14 @@
 
 ;; logical shift instructions
 
-;; On all 68k models, this makes faster code in a special case.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(lshift:SI (match_operand:SI 1 "register_operand" "0")
-		   (match_operand:SI 2 "immediate_operand" "i")))]
-  "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)"
-  "*
-{
-  CC_STATUS_INIT;
-  return \"swap %0\;clr%.w %0\";
-}")
-
-;; On the 68000, this makes faster code in a special case.
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(lshift:SI (match_operand:SI 1 "register_operand" "0")
-		   (match_operand:SI 2 "immediate_operand" "i")))]
-  "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT
-    && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
-  "*
-{
-  CC_STATUS_INIT;
-
-  operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16);
-  return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
-}")
-
-(define_insn "lshlsi3"
-  [(set (match_operand:SI 0 "register_operand" "=d")
-	(lshift:SI (match_operand:SI 1 "register_operand" "0")
-		   (match_operand:SI 2 "general_operand" "dI")))]
-  ""
-  "*
-{
-  if (operands[2] == const1_rtx)
-    return \"add%.l %0,%0\";
-  return \"lsl%.l %2,%0\";
-}")
-
-(define_insn "lshlhi3"
-  [(set (match_operand:HI 0 "register_operand" "=d")
-	(lshift:HI (match_operand:HI 1 "register_operand" "0")
-		   (match_operand:HI 2 "general_operand" "dI")))]
-  ""
-  "lsl%.w %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
-	(lshift:HI (match_dup 0)
-		   (match_operand:HI 1 "general_operand" "dI")))]
-  ""
-  "lsl%.w %1,%0")
-
-(define_insn "lshlqi3"
-  [(set (match_operand:QI 0 "register_operand" "=d")
-	(lshift:QI (match_operand:QI 1 "register_operand" "0")
-		   (match_operand:QI 2 "general_operand" "dI")))]
-  ""
-  "lsl%.b %2,%0")
-
-(define_insn ""
-  [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
-	(lshift:QI (match_dup 0)
-		   (match_operand:QI 1 "general_operand" "dI")))]
-  ""
-  "lsl%.b %1,%0")
 
 ;; On all 68k models, this makes faster code in a special case.
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  "(GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)" 
+		     (const_int 16)))]
+  ""
   "*
 {
   CC_STATUS_INIT;
@@ -3644,8 +3593,8 @@
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=d")
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
-		     (match_operand:SI 2 "immediate_operand" "i")))]
-  "(! TARGET_68020 && GET_CODE (operands[2]) == CONST_INT
+		     (match_operand:SI 2 "const_int_operand" "n")))]
+  "(! TARGET_68020
     && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
   "*
 {
@@ -3659,10 +3608,7 @@
 	(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
 		     (match_operand:SI 2 "general_operand" "dI")))]
   ""
-  "*
-{
-  return \"lsr%.l %2,%0\";
-}")
+  "lsr%.l %2,%0")
 
 (define_insn "lshrhi3"
   [(set (match_operand:HI 0 "register_operand" "=d")
@@ -3779,13 +3725,10 @@
 ;
 (define_insn ""
   [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o")
-			 (match_operand:SI 1 "immediate_operand" "i")
-			 (match_operand:SI 2 "immediate_operand" "i"))
+			 (const_int 32)
+			 (match_operand:SI 2 "const_int_operand" "n"))
 	(match_operand:SI 3 "general_operand" "rmi"))]
   "TARGET_68020 && TARGET_BITFIELD
-   && GET_CODE (operands[1]) == CONST_INT
-   && (INTVAL (operands[1]) == 32)
-   && GET_CODE (operands[2]) == CONST_INT
    && (INTVAL (operands[2]) % 8) == 0
    && ! mode_dependent_address_p (XEXP (operands[0], 0))"
   "*
@@ -3798,13 +3741,11 @@
 
 (define_insn ""
   [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do")
-			 (match_operand:SI 1 "immediate_operand" "i")
-			 (match_operand:SI 2 "immediate_operand" "i"))
-	(match_operand:SI 3 "general_operand" "d"))]
+			 (match_operand:SI 1 "const_int_operand" "n")
+			 (match_operand:SI 2 "const_int_operand" "n"))
+	(match_operand:SI 3 "register_operand" "d"))]
   "TARGET_68020 && TARGET_BITFIELD
-   && GET_CODE (operands[1]) == CONST_INT
    && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
-   && GET_CODE (operands[2]) == CONST_INT
    && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
    && (GET_CODE (operands[0]) == REG
        || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
@@ -3838,12 +3779,9 @@
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=rm")
 	(zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o")
-			 (match_operand:SI 2 "immediate_operand" "i")
-			 (match_operand:SI 3 "immediate_operand" "i")))]
+			 (const_int 32)
+			 (match_operand:SI 3 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD
-   && GET_CODE (operands[2]) == CONST_INT
-   && (INTVAL (operands[2]) == 32)
-   && GET_CODE (operands[3]) == CONST_INT
    && (INTVAL (operands[3]) % 8) == 0
    && ! mode_dependent_address_p (XEXP (operands[1], 0))"
   "*
@@ -3857,12 +3795,10 @@
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=&d")
 	(zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
-			 (match_operand:SI 2 "immediate_operand" "i")
-			 (match_operand:SI 3 "immediate_operand" "i")))]
+			 (match_operand:SI 2 "const_int_operand" "n")
+			 (match_operand:SI 3 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD
-   && GET_CODE (operands[2]) == CONST_INT
    && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && GET_CODE (operands[3]) == CONST_INT
    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
    && (GET_CODE (operands[1]) == REG
        || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
@@ -3897,12 +3833,9 @@
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=rm")
 	(sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o")
-			 (match_operand:SI 2 "immediate_operand" "i")
-			 (match_operand:SI 3 "immediate_operand" "i")))]
+			 (const_int 32)
+			 (match_operand:SI 3 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD
-   && GET_CODE (operands[2]) == CONST_INT
-   && (INTVAL (operands[2]) == 32)
-   && GET_CODE (operands[3]) == CONST_INT
    && (INTVAL (operands[3]) % 8) == 0
    && ! mode_dependent_address_p (XEXP (operands[1], 0))"
   "*
@@ -3916,12 +3849,10 @@
 (define_insn ""
   [(set (match_operand:SI 0 "general_operand" "=d")
 	(sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do")
-			 (match_operand:SI 2 "immediate_operand" "i")
-			 (match_operand:SI 3 "immediate_operand" "i")))]
+			 (match_operand:SI 2 "const_int_operand" "n")
+			 (match_operand:SI 3 "const_int_operand" "n")))]
   "TARGET_68020 && TARGET_BITFIELD
-   && GET_CODE (operands[2]) == CONST_INT
    && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
-   && GET_CODE (operands[3]) == CONST_INT
    && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
    && (GET_CODE (operands[1]) == REG
        || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
@@ -3961,7 +3892,15 @@
   "TARGET_68020 && TARGET_BITFIELD"
   "*
 {
-  cc_status.flags |= CC_NOT_NEGATIVE;
+  if (GET_CODE (operands[2]) == CONST_INT)
+    {
+      if (INTVAL (operands[2]) != 32)
+	cc_status.flags |= CC_NOT_NEGATIVE;
+    }
+  else
+    {
+      CC_STATUS_INIT;
+    }
   return \"bfextu %1{%b3:%b2},%0\";
 }")
 
@@ -3970,9 +3909,8 @@
 			 (match_operand:SI 1 "general_operand" "di,di")
 			 (match_operand:SI 2 "general_operand" "di,di"))
         (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
-		(match_operand 3 "immediate_operand" "i,i")))]
+		(match_operand 3 "const_int_operand" "n,n")))]
   "TARGET_68020 && TARGET_BITFIELD
-   && GET_CODE (operands[3]) == CONST_INT
    && (INTVAL (operands[3]) == -1
        || (GET_CODE (operands[1]) == CONST_INT
            && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
@@ -4010,7 +3948,7 @@
   [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d")
 			 (match_operand:SI 1 "general_operand" "di,di")
 			 (match_operand:SI 2 "general_operand" "di,di"))
-	(match_operand:SI 3 "general_operand" "d,d"))]
+	(match_operand:SI 3 "register_operand" "d,d"))]
   "TARGET_68020 && TARGET_BITFIELD"
   "bfins %3,%0{%b2:%b1}")
 
@@ -4033,7 +3971,15 @@
   "TARGET_68020 && TARGET_BITFIELD"
   "*
 {
-  cc_status.flags |= CC_NOT_NEGATIVE;
+  if (GET_CODE (operands[2]) == CONST_INT)
+    {
+      if (INTVAL (operands[2]) != 32)
+	cc_status.flags |= CC_NOT_NEGATIVE;
+    }
+  else
+    {
+      CC_STATUS_INIT;
+    }
   return \"bfextu %1{%b3:%b2},%0\";
 }")
 
@@ -4065,7 +4011,7 @@
   [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d")
 			 (match_operand:SI 1 "general_operand" "di")
 			 (match_operand:SI 2 "general_operand" "di"))
-	(match_operand:SI 3 "general_operand" "d"))]
+	(match_operand:SI 3 "register_operand" "d"))]
   "TARGET_68020 && TARGET_BITFIELD"
   "*
 {
@@ -4086,10 +4032,9 @@
 (define_insn ""
   [(set (cc0)
 	(zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
-			 (match_operand:SI 1 "general_operand" "di")
+			 (match_operand:SI 1 "const_int_operand" "n")
 			 (match_operand:SI 2 "general_operand" "di")))]
-  "TARGET_68020 && TARGET_BITFIELD
-   && GET_CODE (operands[1]) == CONST_INT"
+  "TARGET_68020 && TARGET_BITFIELD"
   "*
 {
   if (operands[1] == const1_rtx
@@ -4115,10 +4060,9 @@
 (define_insn ""
   [(set (cc0)
 	(zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d")
-			 (match_operand:SI 1 "general_operand" "di")
+			 (match_operand:SI 1 "const_int_operand" "n")
 			 (match_operand:SI 2 "general_operand" "di")))]
-  "TARGET_68020 && TARGET_BITFIELD
-   && GET_CODE (operands[1]) == CONST_INT"
+  "TARGET_68020 && TARGET_BITFIELD"
   "*
 {
   if (operands[1] == const1_rtx
@@ -4548,7 +4492,8 @@
   "
 {
 #ifdef CASE_VECTOR_PC_RELATIVE
-    operands[0] = gen_rtx (PLUS, SImode, pc_rtx, operands[0]);
+    operands[0] = gen_rtx (PLUS, SImode, pc_rtx,
+			   gen_rtx (SIGN_EXTEND, SImode, operands[0]));
 #endif
 }")
 
@@ -4568,7 +4513,8 @@
 ;; Jump to variable address from dispatch table of relative addresses.
 (define_insn ""
   [(set (pc)
-	(plus:SI (pc) (match_operand:HI 0 "register_operand" "r")))
+	(plus:SI (pc)
+		 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
    (use (label_ref (match_operand 1 "" "")))]
   ""
   "*
@@ -4841,6 +4787,11 @@
   "! flag_pic"
   "*
 #ifdef MOTOROLA
+#ifdef MOTOROLA_BSR
+  if (GET_CODE (operands[0]) == MEM 
+      && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
+    return \"bsr %0\";
+#endif
   return \"jsr %0\";
 #else
   return \"jbsr %0\";
@@ -4858,8 +4809,12 @@
 #ifdef MOTOROLA
   if (GET_CODE (operands[0]) == MEM 
       && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
+#ifdef HPUX_ASM
+    return \"bsr.l %0\";
+#else
     return \"bsr %0@PLTPC\";
 #endif
+#endif
   return \"jsr %0\";
 ")
 
@@ -4892,6 +4847,11 @@
   "! flag_pic"
   "*
 #ifdef MOTOROLA
+#ifdef MOTOROLA_BSR
+  if (GET_CODE (operands[1]) == MEM 
+      && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
+    return \"bsr %1\";
+#endif
   return \"jsr %1\";
 #else
   return \"jbsr %1\";
@@ -4909,8 +4869,12 @@
 #ifdef MOTOROLA
   if (GET_CODE (operands[1]) == MEM 
       && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
+#ifdef HPUX_ASM
+    return \"bsr.l %1\";
+#else
     return \"bsr %1@PLTPC\";
 #endif
+#endif
   return \"jsr %1\";
 ")
 
@@ -4989,7 +4953,41 @@
   [(set (match_operand:SI 0 "general_operand" "=a")
 	(match_operand:QI 1 "address_operand" "p"))]
   ""
-  "lea %a1,%0")
+  "*
+{
+#ifndef SGS_NO_LI
+  /* Recognize an insn that refers to a table of offsets.  Such an insn will
+     need to refer to a label on the insn.  So output one.  Use the
+     label-number of the table of offsets to generate this label.  This code,
+     and similar code above, assumes that there will be at most one reference
+     to each table.  */
+  if (GET_CODE (operands[1]) == PLUS
+      && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
+      && GET_CODE (XEXP (operands[1], 0)) != PLUS)
+    {
+      rtx labelref = XEXP (operands[1], 1);
+#if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
+#ifdef SGS
+      asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
+		   CODE_LABEL_NUMBER (XEXP (labelref, 0)));
+#else /* not SGS */
+      asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
+	           CODE_LABEL_NUMBER (XEXP (labelref, 0)));
+#endif /* not SGS */
+#else /* SGS_SWITCH_TABLES or not MOTOROLA */
+      ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
+				 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
+#ifdef SGS_SWITCH_TABLES
+      /* Set flag saying we need to define the symbol
+	 LD%n (with value L%n-LI%n) at the end of the switch table.  */
+      switch_table_difference_label_flag = 1;
+#endif /* SGS_SWITCH_TABLES */
+#endif /* SGS_SWITCH_TABLES or not MOTOROLA */
+    }
+#endif /* SGS_NO_LI */
+
+  return \"lea %a1,%0\";
+}")
 
 ;; This is the first machine-dependent peephole optimization.
 ;; It is useful when a floating value is returned from a function call
@@ -5017,10 +5015,10 @@
 
 (define_peephole
   [(set (reg:SI 15) (plus:SI (reg:SI 15)
-			     (match_operand:SI 0 "immediate_operand" "n")))
+			     (match_operand:SI 0 "const_int_operand" "n")))
    (set (match_operand:SF 1 "push_operand" "=m")
 	(match_operand:SF 2 "general_operand" "rmfF"))]
-  "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) >= 4
+  "INTVAL (operands[0]) >= 4
    && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
   "*
 {
@@ -5054,10 +5052,10 @@
 
 (define_peephole
   [(set (reg:SI 15) (plus:SI (reg:SI 15)
-			     (match_operand:SI 0 "immediate_operand" "n")))
+			     (match_operand:SI 0 "const_int_operand" "n")))
    (set (match_operand:SI 1 "push_operand" "=m")
 	(match_operand:SI 2 "general_operand" "g"))]
-  "GET_CODE (operands[0]) == CONST_INT && INTVAL (operands[0]) >= 4
+  "INTVAL (operands[0]) >= 4
    && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
   "*
 {