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1.1.1.3 ! root 1: ;;- Machine description for GNU compiler, Motorola 68000 Version ! 2: ;; Copyright (C) 1987, 1988, 1993, 1994 Free Software Foundation, Inc. 1.1 root 3: 4: ;; This file is part of GNU CC. 5: 6: ;; GNU CC is free software; you can redistribute it and/or modify 7: ;; it under the terms of the GNU General Public License as published by 8: ;; the Free Software Foundation; either version 2, or (at your option) 9: ;; any later version. 10: 11: ;; GNU CC is distributed in the hope that it will be useful, 12: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14: ;; GNU General Public License for more details. 15: 16: ;; You should have received a copy of the GNU General Public License 17: ;; along with GNU CC; see the file COPYING. If not, write to 18: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 19: 20: 21: ;;- instruction definitions 22: 23: ;;- @@The original PO technology requires these to be ordered by speed, 24: ;;- @@ so that assigner will pick the fastest. 25: 26: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 27: 28: ;;- When naming insn's (operand 0 of define_insn) be careful about using 29: ;;- names from other targets machine descriptions. 30: 31: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code 32: ;;- updates for most instructions. 33: 34: ;;- Operand classes for the register allocator: 35: ;;- 'a' one of the address registers can be used. 36: ;;- 'd' one of the data registers can be used. 37: ;;- 'f' one of the m68881 registers can be used 38: ;;- 'r' either a data or an address register can be used. 39: ;;- 'x' if one of the Sun FPA registers 40: ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15). 41: 42: ;;- Immediate Floating point operator constraints 43: ;;- 'G' a floating point constant that is *NOT* one of the standard 44: ;; 68881 constant values (to force calling output_move_const_double 45: ;; to get it from rom if it is a 68881 constant). 46: ;;- 'H' one of the standard FPA constant values 47: ;; 48: ;; See the functions standard_XXX_constant_p in output-m68k.c for more 49: ;; info. 50: 51: ;;- Immediate integer operand constraints: 52: ;;- 'I' 1 .. 8 53: ;;- 'J' -32768 .. 32767 54: ;;- 'K' all integers EXCEPT -128 .. 127 55: ;;- 'L' -8 .. -1 56: 57: ;;- Assembler specs: 58: ;;- "%." size separator ("." or "") move%.l d0,d1 59: ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0 60: ;;- "%-" push operand "sp@-" move%.l d0,%- 61: ;;- "%+" pop operand "sp@+" move%.l d0,%+ 62: ;;- "%@" top of stack "sp@" move%.l d0,%@ 63: ;;- "%!" fpcr register 64: ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1 65: ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1 66: 67: ;;- Information about 68040 port. 68: 69: ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must 70: ;;- be emulated in software by the OS. It is faster to avoid these 71: ;;- instructions and issue a library call rather than trapping into 72: ;;- the kernel. The affected instructions are fintrz and fscale. The 73: ;;- TARGET_68040 flag turns the use of the opcodes off. 74: 75: ;;- The '040 also implements a set of new floating-point instructions 76: ;;- which specify the rounding precision in the opcode. This finally 77: ;;- permit the 68k series to be truly IEEE compliant, and solves all 78: ;;- issues of excess precision accumulating in the extended registers. 79: ;;- By default, GCC does not use these instructions, since such code will 80: ;;- not run on an '030. To use these instructions, use the -m68040-only 81: ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY, 82: ;;- you can make these instructions the default. 83: 84: ;;- These new instructions aren't directly in the md. They are brought 85: ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather 86: ;;- than "". 87: 88: 89: ;;- FPA port explanation: 90: 91: ;;- Usage of the Sun FPA and the 68881 together 92: 93: ;;- The current port of gcc to the sun fpa disallows use of the m68881 94: ;;- instructions completely if code is targeted for the fpa. This is 95: ;;- for the following reasons: 96: 97: ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you 98: ;;- can, the 68881 otherwise, and data registers only if you are 99: ;;- forced to it) is a bitch with the current constraint scheme, 100: ;;- especially since it would have to work for any combination of 101: ;;- -mfpa, -m68881. 102: 103: ;;- 2) There are no instructions to move between the two types of 104: ;;- registers; the stack must be used as an intermediary. 105: 106: ;;- It could indeed be done; I think the best way would be to have 107: ;;- separate patterns for TARGET_FPA (which implies a 68881), 108: ;;- TARGET_68881, and no floating point co-processor. Use 109: ;;- define_expands for all of the named instruction patterns, and 110: ;;- include code in the FPA instruction to deal with the 68881 with 111: ;;- preferences specifically set to favor the fpa. Some of this has 112: ;;- already been done: 113: ;;- 114: ;;- 1) Separation of most of the patterns out into a TARGET_FPA 115: ;;- case and a TARGET_68881 case (the exceptions are the patterns 116: ;;- which would need one define_expand and three define_insn's under 117: ;;- it (with a lot of duplicate code between them) to replace the 118: ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the 119: ;;- first two patterns in the md. 120: ;;- 121: ;;- Some would still have to be done: 122: ;;- 123: ;;- 1) Add code to the fpa patterns which correspond to 68881 124: ;;- patterns to deal with the 68881 case (including preferences!). 125: ;;- What you might actually do here is combine the fpa and 68881 code 126: ;;- back together into one pattern for those instructions where it's 127: ;;- absolutely necessary and save yourself some duplicate code. I'm 128: ;;- not completely sure as to whether you could get away with doing 129: ;;- this only for the mov* insns, or if you'd have to do it for all 130: ;;- named insns. 131: ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle 132: ;;- moving between fpa regs and 68881 regs. 133: 134: ;;- Since the fpa is more powerful than the 68881 and also has more 135: ;;- registers, and since I think the resultant md would be medium ugly 136: ;;- (lot's of duplicate code, ugly constraint strings), I elected not 137: ;;- to do this change. 138: 139: ;;- Another reason why someone *might* want to do the change is to 140: ;;- control which register classes are accessed in a slightly cleaner 141: ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in 142: ;;- the internals manual. 143: 144: ;;- Yet another reason why someone might want to do this change is to 145: ;;- allow use of some of the 68881 insns which have no equivalent on 146: ;;- the fpa. The sqrt instruction comes fairly quickly to mind. 147: 148: ;;- If this is ever done, don't forget to change sun3.h so that 149: ;;- it *will* define __HAVE_68881__ when the FPA is in use. 150: 151: ;;- Condition code hack 152: 153: ;;- When a floating point compare is done in the fpa, the resulting 154: ;;- condition codes are left in the fpastatus register. The values in 155: ;;- this register must be moved into the 68000 cc register before any 156: ;;- jump is executed. Once this has been done, regular jump 157: ;;- instructions are fine (ie. floating point jumps are not necessary. 158: ;;- They are only done if the cc is in the 68881). 159: 160: ;;- The instructions that move the fpastatus register to the 68000 161: ;;- register clobber a data register (the move cannot be done direct). 162: ;;- These instructions might be bundled either with the compare 163: ;;- instruction, or the branch instruction. If we were using both the 164: ;;- fpa and the 68881 together, we would wish to only mark the 165: ;;- register clobbered if we were doing the compare in the fpa, but I 166: ;;- think that that decision (whether to clobber the register or not) 167: ;;- must be done before register allocation (makes sense) and hence we 168: ;;- can't know if the floating point compare will be done in the fpa 169: ;;- or the fp. So whenever we are asked for code that uses the fpa, 170: ;;- we will mark a data register as clobbered. This is reasonable, as 171: ;;- almost all floating point compare operations done with fpa code 172: ;;- enabled will be done in the fpa. It's even more reasonable since 173: ;;- we decided to make the 68881 and the fpa mutually exclusive. 174: 175: ;;- We place to code to move the fpastatus register inside of a 176: ;;- define_expand so that we can do it conditionally based on whether 177: ;;- we are targeting an fpa or not. 178: 179: ;;- This still leaves us with the question of where we wish to put the 180: ;;- code to move the fpastatus reg. If we put it in the compare 181: ;;- instruction, we can restrict the clobbering of the register to 182: ;;- floating point compares, but we can't take advantage of floating 183: ;;- point subtracts & etc. that alter the fpastatus register. If we 184: ;;- put it in the branch instruction, all branches compiled with fpa 185: ;;- code enabled will clobber a data register, but we will be able to 186: ;;- take advantage of fpa subtracts. This balance favors putting the 187: ;;- code in with the compare instruction. 188: 189: ;;- Note that if some enterprising hacker should decide to switch 190: ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC. 191: 192: ;;- Usage of the top 16 fpa registers 193: 194: ;;- The only locations which we may transfer fpa registers 16-31 from 195: ;;- or to are the fpa registers 0-15. (68000 registers and memory 196: ;;- locations are impossible). This causes problems in gcc, which 197: ;;- assumes that mov?? instructions require no additional registers 198: ;;- (see section 11.7) and since floating point moves *must* be 199: ;;- supported into general registers (see section 12.3 under 200: ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere. 201: 202: ;;- My solution was to reserve fpa0 for moves into or out of these top 203: ;;- 16 registers and to disparage the choice to reload into or out of 204: ;;- these registers as much as I could. That alternative is always 205: ;;- last in the list, so it will not be used unless all else fails. I 206: ;;- will note that according to my current information, sun's compiler 207: ;;- doesn't use these top 16 registers at all. 208: 209: ;;- There is another possible way to do it. I *believe* that if you 210: ;;- make absolutely sure that the code will not be executed in the 211: ;;- reload pass, you can support the mov?? names with define_expands 212: ;;- which require new registers. This may be possible by the 213: ;;- appropriate juggling of constraints. I may come back to this later. 214: 215: ;;- Usage of constant RAM 216: 217: ;;- This has been handled correctly (I believe) but the way I've done 218: ;;- it could use a little explanation. The constant RAM can only be 219: ;;- accessed when the instruction is in "command register" mode. 220: ;;- "command register" mode means that no accessing of memory or the 221: ;;- 68000 registers is being done. This can be expressed easily in 222: ;;- constraints, so generally the mode of the instruction is 223: ;;- determined by a branch off of which_alternative. In outputting 224: ;;- instructions, a 'w' means to output an access to the constant ram 225: ;;- (if the arg is CONST_DOUBLE and is one of the available 226: ;;- constants), and 'x' means to output a register pair (if the arg is 227: ;;- a 68000 register) and a 'y' is the combination of the above two 228: ;;- processes. You use a 'y' in two operand DF instructions where you 229: ;;- *know* the other operand is an fpa register, you use an 'x' in DF 230: ;;- instructions where the arg might be a 68000 register and the 231: ;;- instruction is *not* in "command register" mode, and you use a 'w' 232: ;;- in two situations: 1) The instruction *is* in command register 233: ;;- mode (and hence won't be accessing 68000 registers), or 2) The 234: ;;- instruction is a two operand SF instruction where you know the 235: ;;- other operand is an fpa register. 236: 237: ;;- Optimization issues 238: 239: ;;- I actually think that I've included all of the fpa instructions 240: ;;- that should be included. Note that if someone is interested in 241: ;;- doing serious floating point work on the sun fpa, I would advise 242: ;;- the use of the "asm" instruction in gcc to allow you to use the 243: ;;- sin, cos, and exponential functions on the fpa board. 244: 245: ;;- END FPA Explanation Section. 246: 247: 248: ;;- Some of these insn's are composites of several m68000 op codes. 249: ;;- The assembler (or final @@??) insures that the appropriate one is 250: ;;- selected. 251: 252: (define_insn "" 253: [(set (match_operand:DF 0 "push_operand" "=m") 254: (match_operand:DF 1 "general_operand" "ro<>fyE"))] 255: "" 256: "* 257: { 258: if (FP_REG_P (operands[1])) 259: return \"fmove%.d %f1,%0\"; 260: if (FPA_REG_P (operands[1])) 261: return \"fpmove%.d %1, %x0\"; 262: return output_move_double (operands); 263: }") 264: 265: (define_insn "" 266: [(set (match_operand:DI 0 "push_operand" "=m") 267: (match_operand:DI 1 "general_operand" "ro<>Fy"))] 268: "" 269: "* 270: { 271: return output_move_double (operands); 272: }") 273: 274: ;; We don't want to allow a constant operand for test insns because 275: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will 276: ;; be folded while optimizing anyway. 277: (define_insn "tstsi" 278: [(set (cc0) 279: (match_operand:SI 0 "nonimmediate_operand" "rm"))] 280: "" 281: "* 282: { 283: #ifdef ISI_OV 284: /* ISI's assembler fails to handle tstl a0. */ 285: if (! ADDRESS_REG_P (operands[0])) 286: #else 287: if (TARGET_68020 || ! ADDRESS_REG_P (operands[0])) 288: #endif 289: return \"tst%.l %0\"; 290: /* If you think that the 68020 does not support tstl a0, 291: reread page B-167 of the 68020 manual more carefully. */ 292: /* On an address reg, cmpw may replace cmpl. */ 293: #ifdef SGS_CMP_ORDER 294: return \"cmp%.w %0,%#0\"; 295: #else 296: return \"cmp%.w %#0,%0\"; 297: #endif 298: }") 299: 300: ;; This can't use an address register, because comparisons 301: ;; with address registers as second operand always test the whole word. 302: (define_insn "tsthi" 303: [(set (cc0) 304: (match_operand:HI 0 "nonimmediate_operand" "dm"))] 305: "" 306: "tst%.w %0") 307: 308: (define_insn "tstqi" 309: [(set (cc0) 310: (match_operand:QI 0 "nonimmediate_operand" "dm"))] 311: "" 312: "tst%.b %0") 313: 314: (define_expand "tstsf" 315: [(set (cc0) 316: (match_operand:SF 0 "general_operand" ""))] 317: "TARGET_68881 || TARGET_FPA" 318: " 319: { 320: if (TARGET_FPA) 321: { 322: emit_insn (gen_tstsf_fpa (operands[0])); 323: DONE; 324: } 325: }") 326: 327: (define_insn "tstsf_fpa" 328: [(set (cc0) 329: (match_operand:SF 0 "general_operand" "xmdF")) 330: (clobber (match_scratch:SI 1 "=d"))] 331: "TARGET_FPA" 332: "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc") 333: 334: (define_insn "" 335: [(set (cc0) 336: (match_operand:SF 0 "general_operand" "fdm"))] 337: "TARGET_68881" 338: "* 339: { 340: cc_status.flags = CC_IN_68881; 341: if (FP_REG_P (operands[0])) 342: return \"ftst%.x %0\"; 343: return \"ftst%.s %0\"; 344: }") 345: 346: (define_expand "tstdf" 347: [(set (cc0) 348: (match_operand:DF 0 "general_operand" ""))] 349: "TARGET_68881 || TARGET_FPA" 350: " 351: { 352: if (TARGET_FPA) 353: { 354: emit_insn (gen_tstsf_fpa (operands[0])); 355: DONE; 356: } 357: }") 358: 359: (define_insn "tstdf_fpa" 360: [(set (cc0) 361: (match_operand:DF 0 "general_operand" "xrmF")) 362: (clobber (match_scratch:SI 1 "=d"))] 363: "TARGET_FPA" 364: "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc") 365: 366: (define_insn "" 367: [(set (cc0) 368: (match_operand:DF 0 "general_operand" "fm"))] 369: "TARGET_68881" 370: "* 371: { 372: cc_status.flags = CC_IN_68881; 373: if (FP_REG_P (operands[0])) 374: return \"ftst%.x %0\"; 375: return \"ftst%.d %0\"; 376: }") 377: 378: ;; compare instructions. 379: 380: ;; A composite of the cmp, cmpa, & cmpi m68000 op codes. 381: (define_insn "cmpsi" 382: [(set (cc0) 383: (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>") 384: (match_operand:SI 1 "general_operand" "mr,Ksr,>")))] 385: "" 386: "* 387: { 388: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 1.1.1.2 root 389: #ifdef SGS_CMP_ORDER 390: return \"cmpm%.l %0,%1\"; 391: #else 1.1 root 392: return \"cmpm%.l %1,%0\"; 1.1.1.2 root 393: #endif 1.1 root 394: if (REG_P (operands[1]) 395: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) 396: { cc_status.flags |= CC_REVERSED; 397: #ifdef SGS_CMP_ORDER 398: return \"cmp%.l %d1,%d0\"; 399: #else 400: return \"cmp%.l %d0,%d1\"; 401: #endif 402: } 403: #ifdef SGS_CMP_ORDER 404: return \"cmp%.l %d0,%d1\"; 405: #else 406: return \"cmp%.l %d1,%d0\"; 407: #endif 408: }") 409: 410: (define_insn "cmphi" 411: [(set (cc0) 1.1.1.2 root 412: (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>") 413: (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))] 1.1 root 414: "" 415: "* 416: { 417: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 1.1.1.2 root 418: #ifdef SGS_CMP_ORDER 419: return \"cmpm%.w %0,%1\"; 420: #else 1.1 root 421: return \"cmpm%.w %1,%0\"; 1.1.1.2 root 422: #endif 1.1 root 423: if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1])) 424: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) 425: { cc_status.flags |= CC_REVERSED; 426: #ifdef SGS_CMP_ORDER 427: return \"cmp%.w %d1,%d0\"; 428: #else 429: return \"cmp%.w %d0,%d1\"; 430: #endif 431: } 432: #ifdef SGS_CMP_ORDER 433: return \"cmp%.w %d0,%d1\"; 434: #else 435: return \"cmp%.w %d1,%d0\"; 436: #endif 437: }") 438: 439: (define_insn "cmpqi" 440: [(set (cc0) 441: (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>") 442: (match_operand:QI 1 "general_operand" "dm,nd,>")))] 443: "" 444: "* 445: { 446: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 1.1.1.2 root 447: #ifdef SGS_CMP_ORDER 448: return \"cmpm%.b %0,%1\"; 449: #else 1.1 root 450: return \"cmpm%.b %1,%0\"; 1.1.1.2 root 451: #endif 1.1 root 452: if (REG_P (operands[1]) 453: || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) 454: { cc_status.flags |= CC_REVERSED; 455: #ifdef SGS_CMP_ORDER 456: return \"cmp%.b %d1,%d0\"; 457: #else 458: return \"cmp%.b %d0,%d1\"; 459: #endif 460: } 461: #ifdef SGS_CMP_ORDER 462: return \"cmp%.b %d0,%d1\"; 463: #else 464: return \"cmp%.b %d1,%d0\"; 465: #endif 466: }") 467: 468: (define_expand "cmpdf" 469: [(set (cc0) 470: (compare (match_operand:DF 0 "general_operand" "") 471: (match_operand:DF 1 "general_operand" "")))] 472: "TARGET_68881 || TARGET_FPA" 473: " 474: { 475: if (TARGET_FPA) 476: { 477: emit_insn (gen_cmpdf_fpa (operands[0], operands[1])); 478: DONE; 479: } 480: }") 481: 482: (define_insn "cmpdf_fpa" 483: [(set (cc0) 484: (compare (match_operand:DF 0 "general_operand" "x,y") 485: (match_operand:DF 1 "general_operand" "xH,rmF"))) 486: (clobber (match_scratch:SI 2 "=d,d"))] 487: "TARGET_FPA" 488: "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc") 489: 490: (define_insn "" 491: [(set (cc0) 492: (compare (match_operand:DF 0 "general_operand" "f,mG") 493: (match_operand:DF 1 "general_operand" "fmG,f")))] 494: "TARGET_68881" 495: "* 496: { 497: cc_status.flags = CC_IN_68881; 498: #ifdef SGS_CMP_ORDER 499: if (REG_P (operands[0])) 500: { 501: if (REG_P (operands[1])) 502: return \"fcmp%.x %0,%1\"; 503: else 504: return \"fcmp%.d %0,%f1\"; 505: } 506: cc_status.flags |= CC_REVERSED; 507: return \"fcmp%.d %1,%f0\"; 508: #else 509: if (REG_P (operands[0])) 510: { 511: if (REG_P (operands[1])) 512: return \"fcmp%.x %1,%0\"; 513: else 514: return \"fcmp%.d %f1,%0\"; 515: } 516: cc_status.flags |= CC_REVERSED; 517: return \"fcmp%.d %f0,%1\"; 518: #endif 519: }") 520: 521: (define_expand "cmpsf" 522: [(set (cc0) 523: (compare (match_operand:SF 0 "general_operand" "") 524: (match_operand:SF 1 "general_operand" "")))] 525: "TARGET_68881 || TARGET_FPA" 526: " 527: { 528: if (TARGET_FPA) 529: { 530: emit_insn (gen_cmpsf_fpa (operands[0], operands[1])); 531: DONE; 532: } 533: }") 534: 535: (define_insn "cmpsf_fpa" 536: [(set (cc0) 537: (compare (match_operand:SF 0 "general_operand" "x,y") 538: (match_operand:SF 1 "general_operand" "xH,rmF"))) 539: (clobber (match_scratch:SI 2 "=d,d"))] 540: "TARGET_FPA" 541: "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc") 542: 543: (define_insn "" 544: [(set (cc0) 545: (compare (match_operand:SF 0 "general_operand" "f,mdG") 546: (match_operand:SF 1 "general_operand" "fmdG,f")))] 547: "TARGET_68881" 548: "* 549: { 550: cc_status.flags = CC_IN_68881; 551: #ifdef SGS_CMP_ORDER 552: if (FP_REG_P (operands[0])) 553: { 554: if (FP_REG_P (operands[1])) 555: return \"fcmp%.x %0,%1\"; 556: else 557: return \"fcmp%.s %0,%f1\"; 558: } 559: cc_status.flags |= CC_REVERSED; 560: return \"fcmp%.s %1,%f0\"; 561: #else 562: if (FP_REG_P (operands[0])) 563: { 564: if (FP_REG_P (operands[1])) 565: return \"fcmp%.x %1,%0\"; 566: else 567: return \"fcmp%.s %f1,%0\"; 568: } 569: cc_status.flags |= CC_REVERSED; 570: return \"fcmp%.s %f0,%1\"; 571: #endif 572: }") 573: 574: ;; Recognizers for btst instructions. 575: 576: (define_insn "" 577: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do") 578: (const_int 1) 579: (minus:SI (const_int 7) 580: (match_operand:SI 1 "general_operand" "di"))))] 581: "" 582: "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") 583: 584: (define_insn "" 585: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d") 586: (const_int 1) 587: (minus:SI (const_int 31) 588: (match_operand:SI 1 "general_operand" "di"))))] 589: "" 590: "* { return output_btst (operands, operands[1], operands[0], insn, 31); }") 591: 592: ;; The following two patterns are like the previous two 593: ;; except that they use the fact that bit-number operands 594: ;; are automatically masked to 3 or 5 bits. 595: 596: (define_insn "" 597: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "do") 598: (const_int 1) 599: (minus:SI (const_int 7) 600: (and:SI 1.1.1.3 ! root 601: (match_operand:SI 1 "register_operand" "d") 1.1 root 602: (const_int 7)))))] 603: "" 604: "* { return output_btst (operands, operands[1], operands[0], insn, 7); }") 605: 606: (define_insn "" 607: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "d") 608: (const_int 1) 609: (minus:SI (const_int 31) 610: (and:SI 1.1.1.3 ! root 611: (match_operand:SI 1 "register_operand" "d") 1.1 root 612: (const_int 31)))))] 613: "" 614: "* { return output_btst (operands, operands[1], operands[0], insn, 31); }") 615: 616: ;; Nonoffsettable mem refs are ok in this one pattern 617: ;; since we don't try to adjust them. 618: (define_insn "" 619: [(set (cc0) (zero_extract (match_operand:QI 0 "nonimmediate_operand" "md") 620: (const_int 1) 1.1.1.3 ! root 621: (match_operand:SI 1 "const_int_operand" "n")))] ! 622: "(unsigned) INTVAL (operands[1]) < 8" 1.1 root 623: "* 624: { 625: operands[1] = gen_rtx (CONST_INT, VOIDmode, 7 - INTVAL (operands[1])); 626: return output_btst (operands, operands[1], operands[0], insn, 7); 627: }") 628: 629: (define_insn "" 630: [(set (cc0) (zero_extract (match_operand:SI 0 "nonimmediate_operand" "do") 631: (const_int 1) 1.1.1.3 ! root 632: (match_operand:SI 1 "const_int_operand" "n")))] ! 633: "" 1.1 root 634: "* 635: { 636: if (GET_CODE (operands[0]) == MEM) 637: { 638: operands[0] = adj_offsettable_operand (operands[0], 639: INTVAL (operands[1]) / 8); 640: operands[1] = gen_rtx (CONST_INT, VOIDmode, 641: 7 - INTVAL (operands[1]) % 8); 642: return output_btst (operands, operands[1], operands[0], insn, 7); 643: } 644: operands[1] = gen_rtx (CONST_INT, VOIDmode, 645: 31 - INTVAL (operands[1])); 646: return output_btst (operands, operands[1], operands[0], insn, 31); 647: }") 648: 649: 650: ;; move instructions 651: 652: ;; A special case in which it is not desirable 653: ;; to reload the constant into a data register. 654: (define_insn "" 655: [(set (match_operand:SI 0 "push_operand" "=m") 1.1.1.3 ! root 656: (match_operand:SI 1 "const_int_operand" "J"))] ! 657: "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000" 1.1 root 658: "* 659: { 660: if (operands[1] == const0_rtx) 661: return \"clr%.l %0\"; 662: return \"pea %a1\"; 663: }") 664: 665: ;This is never used. 666: ;(define_insn "swapsi" 667: ; [(set (match_operand:SI 0 "general_operand" "+r") 668: ; (match_operand:SI 1 "general_operand" "+r")) 669: ; (set (match_dup 1) (match_dup 0))] 670: ; "" 671: ; "exg %1,%0") 672: 673: ;; Special case of fullword move when source is zero. 674: ;; The reason this is special is to avoid loading a zero 675: ;; into a data reg with moveq in order to store it elsewhere. 676: 677: (define_insn "" 678: [(set (match_operand:SI 0 "general_operand" "=g") 679: (const_int 0))] 680: ;; clr insns on 68000 read before writing. 681: ;; This isn't so on the 68010, but we have no alternative for it. 682: "(TARGET_68020 683: || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))" 684: "* 685: { 686: if (ADDRESS_REG_P (operands[0])) 687: return \"sub%.l %0,%0\"; 688: /* moveq is faster on the 68000. */ 689: if (DATA_REG_P (operands[0]) && !TARGET_68020) 690: #if defined(MOTOROLA) && !defined(CRDS) 691: return \"moveq%.l %#0,%0\"; 692: #else 693: return \"moveq %#0,%0\"; 694: #endif 695: return \"clr%.l %0\"; 696: }") 697: 698: ;; General case of fullword move. 699: ;; 700: ;; This is the main "hook" for PIC code. When generating 701: ;; PIC, movsi is responsible for determining when the source address 702: ;; needs PIC relocation and appropriately calling legitimize_pic_address 703: ;; to perform the actual relocation. 704: ;; 705: ;; In both the PIC and non-PIC cases the patterns generated will 706: ;; matched by the next define_insn. 707: (define_expand "movsi" 708: [(set (match_operand:SI 0 "general_operand" "") 709: (match_operand:SI 1 "general_operand" ""))] 710: "" 711: " 712: { 713: if (flag_pic && symbolic_operand (operands[1], SImode)) 714: { 715: /* The source is an address which requires PIC relocation. 716: Call legitimize_pic_address with the source, mode, and a relocation 717: register (a new pseudo, or the final destination if reload_in_progress 718: is set). Then fall through normally */ 719: extern rtx legitimize_pic_address(); 720: rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); 721: operands[1] = legitimize_pic_address (operands[1], SImode, temp); 722: } 723: }") 724: 725: ;; General case of fullword move. The register constraints 726: ;; force integer constants in range for a moveq to be reloaded 727: ;; if they are headed for memory. 728: (define_insn "" 729: ;; Notes: make sure no alternative allows g vs g. 730: ;; We don't allow f-regs since fixed point cannot go in them. 731: ;; We do allow y and x regs since fixed point is allowed in them. 732: [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m") 733: (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))] 734: "" 735: "* 736: { 737: if (which_alternative == 3) 738: return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\"; 739: if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0])) 740: return \"fpmove%.l %x1,%x0\"; 741: if (GET_CODE (operands[1]) == CONST_INT) 742: { 743: if (operands[1] == const0_rtx 744: && (DATA_REG_P (operands[0]) 745: || GET_CODE (operands[0]) == MEM) 746: /* clr insns on 68000 read before writing. 747: This isn't so on the 68010, but we have no alternative for it. */ 748: && (TARGET_68020 749: || !(GET_CODE (operands[0]) == MEM 750: && MEM_VOLATILE_P (operands[0])))) 751: return \"clr%.l %0\"; 752: else if (DATA_REG_P (operands[0]) 753: && INTVAL (operands[1]) < 128 754: && INTVAL (operands[1]) >= -128) 755: { 756: #if defined(MOTOROLA) && !defined(CRDS) 757: return \"moveq%.l %1,%0\"; 758: #else 759: return \"moveq %1,%0\"; 760: #endif 761: } 762: else if (DATA_REG_P (operands[0]) 1.1.1.3 ! root 763: /* if -256 < N < 256 but N is not in range for a moveq ! 764: N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ ! 765: && INTVAL (operands[1]) < 256 ! 766: && INTVAL (operands[1]) >= -256) 1.1 root 767: { 1.1.1.3 ! root 768: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) ^ 0xff); 1.1 root 769: #if defined(MOTOROLA) && !defined(CRDS) 1.1.1.3 ! root 770: return \"moveq%.l %1,%0\;not%.b %0\"; 1.1 root 771: #else 1.1.1.3 ! root 772: return \"moveq %1,%0\;not%.b %0\"; ! 773: #endif 1.1 root 774: } 775: else if (ADDRESS_REG_P (operands[0]) 776: && INTVAL (operands[1]) < 0x8000 777: && INTVAL (operands[1]) >= -0x8000) 778: return \"move%.w %1,%0\"; 779: else if (push_operand (operands[0], SImode) 780: && INTVAL (operands[1]) < 0x8000 781: && INTVAL (operands[1]) >= -0x8000) 782: return \"pea %a1\"; 783: } 784: else if ((GET_CODE (operands[1]) == SYMBOL_REF 785: || GET_CODE (operands[1]) == CONST) 786: && push_operand (operands[0], SImode)) 787: return \"pea %a1\"; 788: else if ((GET_CODE (operands[1]) == SYMBOL_REF 789: || GET_CODE (operands[1]) == CONST) 790: && ADDRESS_REG_P (operands[0])) 791: return \"lea %a1,%0\"; 792: return \"move%.l %1,%0\"; 793: }") 794: 795: (define_insn "movhi" 796: [(set (match_operand:HI 0 "general_operand" "=g") 797: (match_operand:HI 1 "general_operand" "g"))] 798: "" 799: "* 800: { 801: if (GET_CODE (operands[1]) == CONST_INT) 802: { 803: if (operands[1] == const0_rtx 804: && (DATA_REG_P (operands[0]) 805: || GET_CODE (operands[0]) == MEM) 806: /* clr insns on 68000 read before writing. 807: This isn't so on the 68010, but we have no alternative for it. */ 808: && (TARGET_68020 809: || !(GET_CODE (operands[0]) == MEM 810: && MEM_VOLATILE_P (operands[0])))) 811: return \"clr%.w %0\"; 812: else if (DATA_REG_P (operands[0]) 813: && INTVAL (operands[1]) < 128 814: && INTVAL (operands[1]) >= -128) 815: { 816: #if defined(MOTOROLA) && !defined(CRDS) 817: return \"moveq%.l %1,%0\"; 818: #else 819: return \"moveq %1,%0\"; 820: #endif 821: } 822: else if (INTVAL (operands[1]) < 0x8000 823: && INTVAL (operands[1]) >= -0x8000) 824: return \"move%.w %1,%0\"; 825: } 826: else if (CONSTANT_P (operands[1])) 827: return \"move%.l %1,%0\"; 828: #ifndef SGS_NO_LI 829: /* Recognize the insn before a tablejump, one that refers 830: to a table of offsets. Such an insn will need to refer 831: to a label on the insn. So output one. Use the label-number 1.1.1.3 ! root 832: of the table of offsets to generate this label. This code, ! 833: and similar code below, assumes that there will be at most one ! 834: reference to each table. */ 1.1 root 835: if (GET_CODE (operands[1]) == MEM 836: && GET_CODE (XEXP (operands[1], 0)) == PLUS 1.1.1.3 ! root 837: && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == LABEL_REF ! 838: && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) != PLUS) ! 839: { ! 840: rtx labelref = XEXP (XEXP (operands[1], 0), 1); 1.1 root 841: #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES) 842: #ifdef SGS 843: asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\", 844: CODE_LABEL_NUMBER (XEXP (labelref, 0))); 845: #else /* not SGS */ 846: asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\", 847: CODE_LABEL_NUMBER (XEXP (labelref, 0))); 848: #endif /* not SGS */ 849: #else /* SGS_SWITCH_TABLES or not MOTOROLA */ 850: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", 851: CODE_LABEL_NUMBER (XEXP (labelref, 0))); 852: #ifdef SGS_SWITCH_TABLES 853: /* Set flag saying we need to define the symbol 854: LD%n (with value L%n-LI%n) at the end of the switch table. */ 855: switch_table_difference_label_flag = 1; 856: #endif /* SGS_SWITCH_TABLES */ 857: #endif /* SGS_SWITCH_TABLES or not MOTOROLA */ 858: } 859: #endif /* SGS_NO_LI */ 860: return \"move%.w %1,%0\"; 861: }") 862: 863: (define_insn "movstricthi" 864: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) 865: (match_operand:HI 1 "general_operand" "rmn"))] 866: "" 867: "* 868: { 869: if (GET_CODE (operands[1]) == CONST_INT) 870: { 871: if (operands[1] == const0_rtx 872: && (DATA_REG_P (operands[0]) 873: || GET_CODE (operands[0]) == MEM) 874: /* clr insns on 68000 read before writing. 875: This isn't so on the 68010, but we have no alternative for it. */ 876: && (TARGET_68020 877: || !(GET_CODE (operands[0]) == MEM 878: && MEM_VOLATILE_P (operands[0])))) 879: return \"clr%.w %0\"; 880: } 881: return \"move%.w %1,%0\"; 882: }") 883: 884: (define_insn "movqi" 885: [(set (match_operand:QI 0 "general_operand" "=d,*a,m,m,?*a") 886: (match_operand:QI 1 "general_operand" "dmi*a,d*a,dmi,?*a,m"))] 887: "" 888: "* 889: { 890: rtx xoperands[4]; 891: 892: /* This is probably useless, since it loses for pushing a struct 893: of several bytes a byte at a time. */ 894: if (GET_CODE (operands[0]) == MEM 895: && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC 1.1.1.3 ! root 896: && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx ! 897: && ! ADDRESS_REG_P (operands[1])) 1.1 root 898: { 899: xoperands[1] = operands[1]; 900: xoperands[2] 901: = gen_rtx (MEM, QImode, 902: gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, const1_rtx)); 903: /* Just pushing a byte puts it in the high byte of the halfword. */ 904: /* We must put it in the low-order, high-numbered byte. */ 905: output_asm_insn (\"move%.b %1,%-\;move%.b %@,%2\", xoperands); 906: return \"\"; 907: } 908: 909: /* Moving a byte into an address register is not possible. */ 910: /* Use d0 as an intermediate, but don't clobber its contents. */ 911: if (ADDRESS_REG_P (operands[0]) && GET_CODE (operands[1]) == MEM) 912: { 913: /* ??? For 2.5, don't allow this choice and use secondary reloads 914: instead. 915: 916: See if the address register is used in the address. If it 917: is, we have to generate a more complex sequence than those below. */ 918: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1, 919: operands[1], NULL_RTX)) 920: { 921: /* See if the stack pointer is used in the address. If it isn't, 922: we can push d0 or d1 (the insn can't use both of them) on 923: the stack, perform our move into d0/d1, copy the byte from d0/1, 924: and pop d0/1. */ 925: if (! reg_mentioned_p (stack_pointer_rtx, operands[1])) 926: { 1.1.1.3 ! root 927: if (! refers_to_regno_p (0, 1, operands[1], NULL_RTX)) 1.1 root 928: return \"move%.l %/d0,%-\;move%.b %1,%/d0\;move%.l %/d0,%0\;move%.l %+,%/d0\"; 929: else 930: return \"move%.l %/d1,%-\;move%.b %1,%/d1\;move%.l %/d1,%0\;move%.l %+,%/d1\"; 931: } 932: else 933: { 934: /* Otherwise, we know that d0 cannot be used in the address 935: (since sp and one address register is). Assume that sp is 936: being used as a base register and replace the address 937: register that is our operand[0] with d0. */ 938: rtx reg_map[FIRST_PSEUDO_REGISTER]; 939: int i; 940: 941: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 942: reg_map[i] = 0; 943: 944: reg_map[REGNO (operands[0])] = gen_rtx (REG, Pmode, 0); 945: operands[1] = copy_rtx (operands[1]); 946: replace_regs (operands[1], reg_map, FIRST_PSEUDO_REGISTER, 0); 947: return \"exg %/d0,%0\;move%.b %1,%/d0\;exg %/d0,%0\"; 948: } 949: } 950: 951: /* If the address of operand 1 uses d0, choose d1 as intermediate. */ 952: if (refers_to_regno_p (0, 1, operands[1], NULL_RTX)) 953: return \"exg %/d1,%0\;move%.b %1,%/d1\;exg %/d1,%0\"; 954: /* Otherwise d0 is usable. 955: (An effective address on the 68k can't use two d-regs.) */ 956: else 957: return \"exg %/d0,%0\;move%.b %1,%/d0\;exg %/d0,%0\"; 958: } 959: 960: /* Likewise for moving from an address reg. */ 961: if (ADDRESS_REG_P (operands[1]) && GET_CODE (operands[0]) == MEM) 962: { 963: /* ??? For 2.5, don't allow this choice and use secondary reloads 964: instead. 965: 966: See if the address register is used in the address. If it 967: is, we have to generate a more complex sequence than those below. */ 968: if (refers_to_regno_p (REGNO (operands[1]), REGNO (operands[1]) + 1, 969: operands[0], NULL_RTX)) 970: { 971: /* See if the stack pointer is used in the address. If it isn't, 972: we can push d0 or d1 (the insn can't use both of them) on 973: the stack, copy the byte to d0/1, perform our move from d0/d1, 974: and pop d0/1. */ 975: if (! reg_mentioned_p (stack_pointer_rtx, operands[0])) 976: { 1.1.1.3 ! root 977: if (! refers_to_regno_p (0, 1, operands[0], NULL_RTX)) 1.1 root 978: return \"move%.l %/d0,%-\;move%.l %1,%/d0\;move%.b %/d0,%0\;move%.l %+,%/d0\"; 979: else 980: return \"move%.l %/d1,%-\;move%.l %1,%/d1\;move%.b %/d1,%0\;move%.l %+,%/d1\"; 981: } 982: else 983: { 984: /* Otherwise, we know that d0 cannot be used in the address 985: (since sp and one address register is). Assume that sp is 986: being used as a base register and replace the address 987: register that is our operand[1] with d0. */ 988: rtx reg_map[FIRST_PSEUDO_REGISTER]; 989: int i; 990: 991: for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 992: reg_map[i] = 0; 993: 994: reg_map[REGNO (operands[1])] = gen_rtx (REG, Pmode, 0); 995: operands[0] = copy_rtx (operands[0]); 996: replace_regs (operands[0], reg_map, FIRST_PSEUDO_REGISTER, 0); 997: return \"exg %/d0,%1\;move%.b %/d0,%0\;exg %/d0,%1\"; 998: } 999: } 1000: 1001: if (refers_to_regno_p (0, 1, operands[0], NULL_RTX)) 1002: return \"exg %/d1,%1\;move%.b %/d1,%0\;exg %/d1,%1\"; 1003: else 1004: return \"exg %/d0,%1\;move%.b %/d0,%0\;exg %/d0,%1\"; 1005: } 1006: 1007: /* clr and st insns on 68000 read before writing. 1008: This isn't so on the 68010, but we have no alternative for it. */ 1009: if (TARGET_68020 1010: || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))) 1011: { 1012: if (operands[1] == const0_rtx) 1013: return \"clr%.b %0\"; 1014: if (GET_CODE (operands[1]) == CONST_INT 1015: && INTVAL (operands[1]) == -1) 1016: { 1017: CC_STATUS_INIT; 1018: return \"st %0\"; 1019: } 1020: } 1021: if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) 1022: return \"move%.l %1,%0\"; 1023: if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) 1024: return \"move%.w %1,%0\"; 1025: return \"move%.b %1,%0\"; 1026: }") 1027: 1028: (define_insn "movstrictqi" 1029: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) 1030: (match_operand:QI 1 "general_operand" "dmn"))] 1031: "" 1032: "* 1033: { 1034: if (operands[1] == const0_rtx 1035: /* clr insns on 68000 read before writing. 1036: This isn't so on the 68010, but we have no alternative for it. */ 1037: && (TARGET_68020 1038: || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) 1039: return \"clr%.b %0\"; 1040: return \"move%.b %1,%0\"; 1041: }") 1042: 1043: (define_insn "movsf" 1044: [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm") 1045: (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))] 1046: ; [(set (match_operand:SF 0 "general_operand" "=rmf") 1047: ; (match_operand:SF 1 "general_operand" "rmfF"))] 1048: "" 1049: "* 1050: { 1051: if (which_alternative >= 4) 1052: return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\"; 1053: if (FPA_REG_P (operands[0])) 1054: { 1055: if (FPA_REG_P (operands[1])) 1056: return \"fpmove%.s %x1,%x0\"; 1057: else if (GET_CODE (operands[1]) == CONST_DOUBLE) 1058: return output_move_const_single (operands); 1059: else if (FP_REG_P (operands[1])) 1060: return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\"; 1061: return \"fpmove%.s %x1,%x0\"; 1062: } 1063: if (FPA_REG_P (operands[1])) 1064: { 1065: if (FP_REG_P (operands[0])) 1066: return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\"; 1067: else 1068: return \"fpmove%.s %x1,%x0\"; 1069: } 1070: if (FP_REG_P (operands[0])) 1071: { 1072: if (FP_REG_P (operands[1])) 1073: return \"f%$move%.x %1,%0\"; 1074: else if (ADDRESS_REG_P (operands[1])) 1075: return \"move%.l %1,%-\;f%$move%.s %+,%0\"; 1076: else if (GET_CODE (operands[1]) == CONST_DOUBLE) 1077: return output_move_const_single (operands); 1078: return \"f%$move%.s %f1,%0\"; 1079: } 1080: if (FP_REG_P (operands[1])) 1081: { 1082: if (ADDRESS_REG_P (operands[0])) 1083: return \"fmove%.s %1,%-\;move%.l %+,%0\"; 1084: return \"fmove%.s %f1,%0\"; 1085: } 1086: return \"move%.l %1,%0\"; 1087: }") 1088: 1089: (define_insn "movdf" 1.1.1.2 root 1090: [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm") 1091: (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))] 1.1 root 1092: ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>") 1093: ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))] 1094: "" 1095: "* 1096: { 1.1.1.2 root 1097: if (which_alternative == 7) 1.1 root 1098: return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\"; 1099: if (FPA_REG_P (operands[0])) 1100: { 1101: if (GET_CODE (operands[1]) == CONST_DOUBLE) 1102: return output_move_const_double (operands); 1103: if (FP_REG_P (operands[1])) 1104: return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\"; 1105: return \"fpmove%.d %x1,%x0\"; 1106: } 1107: else if (FPA_REG_P (operands[1])) 1108: { 1109: if (FP_REG_P(operands[0])) 1110: return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\"; 1111: else 1112: return \"fpmove%.d %x1,%x0\"; 1113: } 1114: if (FP_REG_P (operands[0])) 1115: { 1116: if (FP_REG_P (operands[1])) 1117: return \"f%&move%.x %1,%0\"; 1118: if (REG_P (operands[1])) 1119: { 1120: rtx xoperands[2]; 1121: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 1122: output_asm_insn (\"move%.l %1,%-\", xoperands); 1123: output_asm_insn (\"move%.l %1,%-\", operands); 1124: return \"f%&move%.d %+,%0\"; 1125: } 1126: if (GET_CODE (operands[1]) == CONST_DOUBLE) 1127: return output_move_const_double (operands); 1128: return \"f%&move%.d %f1,%0\"; 1129: } 1130: else if (FP_REG_P (operands[1])) 1131: { 1132: if (REG_P (operands[0])) 1133: { 1134: output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); 1135: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 1136: return \"move%.l %+,%0\"; 1137: } 1138: else 1139: return \"fmove%.d %f1,%0\"; 1140: } 1141: return output_move_double (operands); 1142: } 1143: ") 1144: 1145: (define_expand "movxf" 1146: [(set (match_operand:XF 0 "nonimmediate_operand" "") 1147: (match_operand:XF 1 "general_operand" ""))] 1148: "" 1149: " 1150: { 1151: if (CONSTANT_P (operands[1])) 1152: { 1153: operands[1] = force_const_mem (XFmode, operands[1]); 1154: if (! memory_address_p (XFmode, XEXP (operands[1], 0)) 1155: && ! reload_in_progress) 1156: operands[1] = change_address (operands[1], XFmode, 1157: XEXP (operands[1], 0)); 1158: } 1159: }") 1160: 1161: (define_insn "" 1162: [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f") 1163: (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))] 1164: "TARGET_68881" 1165: "* 1166: { 1167: if (FP_REG_P (operands[0])) 1168: { 1169: if (FP_REG_P (operands[1])) 1170: return \"fmove%.x %1,%0\"; 1171: if (REG_P (operands[1])) 1172: { 1173: rtx xoperands[2]; 1174: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); 1175: output_asm_insn (\"move%.l %1,%-\", xoperands); 1176: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 1177: output_asm_insn (\"move%.l %1,%-\", xoperands); 1178: output_asm_insn (\"move%.l %1,%-\", operands); 1179: return \"fmove%.x %+,%0\"; 1180: } 1181: if (GET_CODE (operands[1]) == CONST_DOUBLE) 1182: return \"fmove%.x %1,%0\"; 1183: return \"fmove%.x %f1,%0\"; 1184: } 1185: if (REG_P (operands[0])) 1186: { 1187: output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands); 1188: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 1189: output_asm_insn (\"move%.l %+,%0\", operands); 1190: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 1191: return \"move%.l %+,%0\"; 1192: } 1193: return \"fmove%.x %f1,%0\"; 1194: } 1195: ") 1196: 1197: (define_insn "" 1.1.1.2 root 1198: [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>") 1.1 root 1199: (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))] 1200: "! TARGET_68881" 1201: "* 1202: { 1203: if (FP_REG_P (operands[0])) 1204: { 1205: if (FP_REG_P (operands[1])) 1206: return \"fmove%.x %1,%0\"; 1207: if (REG_P (operands[1])) 1208: { 1209: rtx xoperands[2]; 1210: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 2); 1211: output_asm_insn (\"move%.l %1,%-\", xoperands); 1212: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 1213: output_asm_insn (\"move%.l %1,%-\", xoperands); 1214: output_asm_insn (\"move%.l %1,%-\", operands); 1215: return \"fmove%.x %+,%0\"; 1216: } 1217: if (GET_CODE (operands[1]) == CONST_DOUBLE) 1218: return \"fmove%.x %1,%0\"; 1219: return \"fmove%.x %f1,%0\"; 1220: } 1221: if (FP_REG_P (operands[1])) 1222: { 1223: if (REG_P (operands[0])) 1224: { 1225: output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands); 1226: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 1227: output_asm_insn (\"move%.l %+,%0\", operands); 1228: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 1229: return \"move%.l %+,%0\"; 1230: } 1231: else 1232: return \"fmove%.x %f1,%0\"; 1233: } 1234: return output_move_double (operands); 1235: } 1236: ") 1237: 1238: ;; movdi can apply to fp regs in some cases 1239: (define_insn "movdi" 1240: ;; Let's see if it really still needs to handle fp regs, and, if so, why. 1.1.1.2 root 1241: [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm") 1.1 root 1242: (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))] 1243: ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm") 1244: ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))] 1245: ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f") 1246: ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))] 1247: "" 1248: "* 1249: { 1250: if (which_alternative == 8) 1251: return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\"; 1252: if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1])) 1253: return \"fpmove%.d %x1,%x0\"; 1254: if (FP_REG_P (operands[0])) 1255: { 1256: if (FP_REG_P (operands[1])) 1257: return \"fmove%.x %1,%0\"; 1258: if (REG_P (operands[1])) 1259: { 1260: rtx xoperands[2]; 1261: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 1262: output_asm_insn (\"move%.l %1,%-\", xoperands); 1263: output_asm_insn (\"move%.l %1,%-\", operands); 1264: return \"fmove%.d %+,%0\"; 1265: } 1266: if (GET_CODE (operands[1]) == CONST_DOUBLE) 1267: return output_move_const_double (operands); 1268: return \"fmove%.d %f1,%0\"; 1269: } 1270: else if (FP_REG_P (operands[1])) 1271: { 1272: if (REG_P (operands[0])) 1273: { 1274: output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); 1275: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 1276: return \"move%.l %+,%0\"; 1277: } 1278: else 1279: return \"fmove%.d %f1,%0\"; 1280: } 1281: return output_move_double (operands); 1282: } 1283: ") 1284: 1285: ;; Thus goes after the move instructions 1286: ;; because the move instructions are better (require no spilling) 1287: ;; when they can apply. It goes before the add/sub insns 1288: ;; so we will prefer it to them. 1289: 1290: (define_insn "pushasi" 1291: [(set (match_operand:SI 0 "push_operand" "=m") 1292: (match_operand:SI 1 "address_operand" "p"))] 1293: "" 1294: "pea %a1") 1295: 1296: ;; truncation instructions 1297: (define_insn "truncsiqi2" 1298: [(set (match_operand:QI 0 "general_operand" "=dm,d") 1299: (truncate:QI 1300: (match_operand:SI 1 "general_operand" "doJ,i")))] 1301: "" 1302: "* 1303: { 1304: if (GET_CODE (operands[0]) == REG) 1305: { 1306: /* Must clear condition codes, since the move.l bases them on 1307: the entire 32 bits, not just the desired 8 bits. */ 1308: CC_STATUS_INIT; 1309: return \"move%.l %1,%0\"; 1310: } 1311: if (GET_CODE (operands[1]) == MEM) 1312: operands[1] = adj_offsettable_operand (operands[1], 3); 1313: return \"move%.b %1,%0\"; 1314: }") 1315: 1316: (define_insn "trunchiqi2" 1317: [(set (match_operand:QI 0 "general_operand" "=dm,d") 1318: (truncate:QI 1319: (match_operand:HI 1 "general_operand" "doJ,i")))] 1320: "" 1321: "* 1322: { 1323: if (GET_CODE (operands[0]) == REG 1324: && (GET_CODE (operands[1]) == MEM 1325: || GET_CODE (operands[1]) == CONST_INT)) 1326: { 1327: /* Must clear condition codes, since the move.w bases them on 1328: the entire 16 bits, not just the desired 8 bits. */ 1329: CC_STATUS_INIT; 1330: return \"move%.w %1,%0\"; 1331: } 1332: if (GET_CODE (operands[0]) == REG) 1333: { 1334: /* Must clear condition codes, since the move.l bases them on 1335: the entire 32 bits, not just the desired 8 bits. */ 1336: CC_STATUS_INIT; 1337: return \"move%.l %1,%0\"; 1338: } 1339: if (GET_CODE (operands[1]) == MEM) 1340: operands[1] = adj_offsettable_operand (operands[1], 1); 1341: return \"move%.b %1,%0\"; 1342: }") 1343: 1344: (define_insn "truncsihi2" 1345: [(set (match_operand:HI 0 "general_operand" "=dm,d") 1346: (truncate:HI 1347: (match_operand:SI 1 "general_operand" "roJ,i")))] 1348: "" 1349: "* 1350: { 1351: if (GET_CODE (operands[0]) == REG) 1352: { 1353: /* Must clear condition codes, since the move.l bases them on 1354: the entire 32 bits, not just the desired 8 bits. */ 1355: CC_STATUS_INIT; 1356: return \"move%.l %1,%0\"; 1357: } 1358: if (GET_CODE (operands[1]) == MEM) 1359: operands[1] = adj_offsettable_operand (operands[1], 2); 1360: return \"move%.w %1,%0\"; 1361: }") 1362: 1363: ;; zero extension instructions 1364: 1365: (define_expand "zero_extendhisi2" 1366: [(set (match_operand:SI 0 "register_operand" "") 1367: (const_int 0)) 1368: (set (strict_low_part (match_dup 2)) 1369: (match_operand:HI 1 "general_operand" ""))] 1370: "" 1371: " 1372: { 1373: operands[1] = make_safe_from (operands[1], operands[0]); 1374: if (GET_CODE (operands[0]) == SUBREG) 1375: operands[2] = gen_rtx (SUBREG, HImode, SUBREG_REG (operands[0]), 1376: SUBREG_WORD (operands[0])); 1377: else 1378: operands[2] = gen_rtx (SUBREG, HImode, operands[0], 0); 1379: }") 1380: 1381: (define_expand "zero_extendqihi2" 1382: [(set (match_operand:HI 0 "register_operand" "") 1383: (const_int 0)) 1384: (set (strict_low_part (match_dup 2)) 1385: (match_operand:QI 1 "general_operand" ""))] 1386: "" 1387: " 1388: { 1389: operands[1] = make_safe_from (operands[1], operands[0]); 1390: if (GET_CODE (operands[0]) == SUBREG) 1391: operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]), 1392: SUBREG_WORD (operands[0])); 1393: else 1394: operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0); 1395: }") 1396: 1397: (define_expand "zero_extendqisi2" 1398: [(set (match_operand:SI 0 "register_operand" "") 1399: (const_int 0)) 1400: (set (strict_low_part (match_dup 2)) 1401: (match_operand:QI 1 "general_operand" ""))] 1402: "" 1403: " 1404: { 1405: operands[1] = make_safe_from (operands[1], operands[0]); 1406: if (GET_CODE (operands[0]) == SUBREG) 1407: operands[2] = gen_rtx (SUBREG, QImode, SUBREG_REG (operands[0]), 1408: SUBREG_WORD (operands[0])); 1409: else 1410: operands[2] = gen_rtx (SUBREG, QImode, operands[0], 0); 1411: }") 1412: 1413: ;; Patterns to recognize zero-extend insns produced by the combiner. 1414: ;; We don't allow both operands in memory, because of aliasing problems. 1415: ;; Explicitly disallow two memory operands via the condition since reloading 1416: ;; of this case will result in worse code than the uncombined patterns. 1417: 1418: (define_insn "" 1419: [(set (match_operand:SI 0 "general_operand" "=do<>,d<") 1420: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))] 1421: "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" 1422: "* 1423: { 1424: if (DATA_REG_P (operands[0])) 1425: { 1426: if (GET_CODE (operands[1]) == REG 1427: && REGNO (operands[0]) == REGNO (operands[1])) 1428: return \"and%.l %#0xFFFF,%0\"; 1429: if (reg_mentioned_p (operands[0], operands[1])) 1430: return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\"; 1431: return \"clr%.l %0\;move%.w %1,%0\"; 1432: } 1433: else if (GET_CODE (operands[0]) == MEM 1434: && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 1435: return \"move%.w %1,%0\;clr%.w %0\"; 1436: else if (GET_CODE (operands[0]) == MEM 1437: && GET_CODE (XEXP (operands[0], 0)) == POST_INC) 1438: return \"clr%.w %0\;move%.w %1,%0\"; 1439: else 1440: { 1441: output_asm_insn (\"clr%.w %0\", operands); 1442: operands[0] = adj_offsettable_operand (operands[0], 2); 1443: return \"move%.w %1,%0\"; 1444: } 1445: }") 1446: 1447: (define_insn "" 1448: [(set (match_operand:HI 0 "general_operand" "=do<>,d") 1449: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 1450: "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" 1451: "* 1452: { 1453: if (DATA_REG_P (operands[0])) 1454: { 1455: if (GET_CODE (operands[1]) == REG 1456: && REGNO (operands[0]) == REGNO (operands[1])) 1457: return \"and%.w %#0xFF,%0\"; 1458: if (reg_mentioned_p (operands[0], operands[1])) 1459: return \"move%.b %1,%0\;and%.w %#0xFF,%0\"; 1460: return \"clr%.w %0\;move%.b %1,%0\"; 1461: } 1462: else if (GET_CODE (operands[0]) == MEM 1463: && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 1464: { 1465: if (REGNO (XEXP (XEXP (operands[0], 0), 0)) 1466: == STACK_POINTER_REGNUM) 1467: { 1468: output_asm_insn (\"clr%.w %-\", operands); 1469: operands[0] = gen_rtx (MEM, GET_MODE (operands[0]), 1470: plus_constant (stack_pointer_rtx, 1)); 1471: return \"move%.b %1,%0\"; 1472: } 1473: else 1474: return \"move%.b %1,%0\;clr%.b %0\"; 1475: } 1476: else if (GET_CODE (operands[0]) == MEM 1477: && GET_CODE (XEXP (operands[0], 0)) == POST_INC) 1478: return \"clr%.b %0\;move%.b %1,%0\"; 1479: else 1480: { 1481: output_asm_insn (\"clr%.b %0\", operands); 1482: operands[0] = adj_offsettable_operand (operands[0], 1); 1483: return \"move%.b %1,%0\"; 1484: } 1485: }") 1486: 1487: (define_insn "" 1488: [(set (match_operand:SI 0 "general_operand" "=do<>,d") 1489: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))] 1490: "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" 1491: "* 1492: { 1493: if (DATA_REG_P (operands[0])) 1494: { 1495: if (GET_CODE (operands[1]) == REG 1496: && REGNO (operands[0]) == REGNO (operands[1])) 1497: return \"and%.l %#0xFF,%0\"; 1498: if (reg_mentioned_p (operands[0], operands[1])) 1499: return \"move%.b %1,%0\;and%.l %#0xFF,%0\"; 1500: return \"clr%.l %0\;move%.b %1,%0\"; 1501: } 1502: else if (GET_CODE (operands[0]) == MEM 1503: && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 1504: { 1505: operands[0] = XEXP (XEXP (operands[0], 0), 0); 1506: #ifdef MOTOROLA 1507: #ifdef SGS 1508: return \"clr%.l -(%0)\;move%.b %1,3(%0)\"; 1509: #else 1510: return \"clr%.l -(%0)\;move%.b %1,(3,%0)\"; 1511: #endif 1512: #else 1513: return \"clrl %0@-\;moveb %1,%0@(3)\"; 1514: #endif 1515: } 1516: else if (GET_CODE (operands[0]) == MEM 1517: && GET_CODE (XEXP (operands[0], 0)) == POST_INC) 1518: { 1519: operands[0] = XEXP (XEXP (operands[0], 0), 0); 1520: #ifdef MOTOROLA 1521: #ifdef SGS 1522: return \"clr%.l (%0)+\;move%.b %1,-1(%0)\"; 1523: #else 1524: return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\"; 1525: #endif 1526: #else 1527: return \"clrl %0@+\;moveb %1,%0@(-1)\"; 1528: #endif 1529: } 1530: else 1531: { 1532: output_asm_insn (\"clr%.l %0\", operands); 1533: operands[0] = adj_offsettable_operand (operands[0], 3); 1534: return \"move%.b %1,%0\"; 1535: } 1536: }") 1537: 1538: ;; sign extension instructions 1539: 1540: (define_insn "extendhisi2" 1541: [(set (match_operand:SI 0 "general_operand" "=*d,a") 1542: (sign_extend:SI 1543: (match_operand:HI 1 "nonimmediate_operand" "0,rm")))] 1544: "" 1545: "* 1546: { 1547: if (ADDRESS_REG_P (operands[0])) 1548: return \"move%.w %1,%0\"; 1549: return \"ext%.l %0\"; 1550: }") 1551: 1552: (define_insn "extendqihi2" 1553: [(set (match_operand:HI 0 "general_operand" "=d") 1554: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))] 1555: "" 1556: "ext%.w %0") 1557: 1558: (define_insn "extendqisi2" 1559: [(set (match_operand:SI 0 "general_operand" "=d") 1560: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))] 1561: "TARGET_68020" 1562: "extb%.l %0") 1563: 1564: ;; Conversions between float and double. 1565: 1566: (define_expand "extendsfdf2" 1567: [(set (match_operand:DF 0 "general_operand" "") 1568: (float_extend:DF 1569: (match_operand:SF 1 "general_operand" "")))] 1570: "TARGET_68881 || TARGET_FPA" 1571: "") 1572: 1573: (define_insn "" 1574: [(set (match_operand:DF 0 "general_operand" "=x,y") 1575: (float_extend:DF 1576: (match_operand:SF 1 "general_operand" "xH,rmF")))] 1577: "TARGET_FPA" 1578: "fpstod %w1,%0") 1579: 1580: (define_insn "" 1581: [(set (match_operand:DF 0 "general_operand" "=*fdm,f") 1582: (float_extend:DF 1583: (match_operand:SF 1 "general_operand" "f,dmF")))] 1584: "TARGET_68881" 1585: "* 1586: { 1587: if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) 1588: { 1589: if (REGNO (operands[0]) == REGNO (operands[1])) 1590: { 1591: /* Extending float to double in an fp-reg is a no-op. 1592: NOTICE_UPDATE_CC has already assumed that the 1593: cc will be set. So cancel what it did. */ 1594: cc_status = cc_prev_status; 1595: return \"\"; 1596: } 1597: return \"f%&move%.x %1,%0\"; 1598: } 1599: if (FP_REG_P (operands[0])) 1600: return \"f%&move%.s %f1,%0\"; 1601: if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1])) 1602: { 1603: output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); 1604: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 1605: return \"move%.l %+,%0\"; 1606: } 1607: return \"fmove%.d %f1,%0\"; 1608: }") 1609: 1610: ;; This cannot output into an f-reg because there is no way to be 1611: ;; sure of truncating in that case. 1612: ;; But on the Sun FPA, we can be sure. 1613: (define_expand "truncdfsf2" 1614: [(set (match_operand:SF 0 "general_operand" "") 1615: (float_truncate:SF 1616: (match_operand:DF 1 "general_operand" "")))] 1617: "TARGET_68881 || TARGET_FPA" 1618: "") 1619: 1620: (define_insn "" 1621: [(set (match_operand:SF 0 "general_operand" "=x,y") 1622: (float_truncate:SF 1623: (match_operand:DF 1 "general_operand" "xH,rmF")))] 1624: "TARGET_FPA" 1625: "fpdtos %y1,%0") 1626: 1627: ;; On the '040 we can truncate in a register accurately and easily. 1628: (define_insn "" 1629: [(set (match_operand:SF 0 "general_operand" "=f") 1630: (float_truncate:SF 1631: (match_operand:DF 1 "general_operand" "fmG")))] 1632: "TARGET_68040_ONLY" 1633: "* 1634: { 1635: if (FP_REG_P (operands[1])) 1636: return \"f%$move%.x %1,%0\"; 1637: return \"f%$move%.d %f1,%0\"; 1638: }") 1639: 1640: (define_insn "" 1641: [(set (match_operand:SF 0 "general_operand" "=dm") 1642: (float_truncate:SF 1643: (match_operand:DF 1 "general_operand" "f")))] 1644: "TARGET_68881" 1645: "fmove%.s %f1,%0") 1646: 1647: ;; Conversion between fixed point and floating point. 1648: ;; Note that among the fix-to-float insns 1649: ;; the ones that start with SImode come first. 1650: ;; That is so that an operand that is a CONST_INT 1651: ;; (and therefore lacks a specific machine mode). 1652: ;; will be recognized as SImode (which is always valid) 1653: ;; rather than as QImode or HImode. 1654: 1655: (define_expand "floatsisf2" 1656: [(set (match_operand:SF 0 "general_operand" "") 1657: (float:SF (match_operand:SI 1 "general_operand" "")))] 1658: "TARGET_68881 || TARGET_FPA" 1659: "") 1660: 1661: (define_insn "" 1662: [(set (match_operand:SF 0 "general_operand" "=y,x") 1663: (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))] 1664: "TARGET_FPA" 1665: "fpltos %1,%0") 1666: 1667: (define_insn "" 1668: [(set (match_operand:SF 0 "general_operand" "=f") 1669: (float:SF (match_operand:SI 1 "general_operand" "dmi")))] 1670: "TARGET_68881" 1671: "f%$move%.l %1,%0") 1672: 1673: (define_expand "floatsidf2" 1674: [(set (match_operand:DF 0 "general_operand" "") 1675: (float:DF (match_operand:SI 1 "general_operand" "")))] 1676: "TARGET_68881 || TARGET_FPA" 1677: "") 1678: 1679: (define_insn "" 1680: [(set (match_operand:DF 0 "general_operand" "=y,x") 1681: (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))] 1682: "TARGET_FPA" 1683: "fpltod %1,%0") 1684: 1685: (define_insn "" 1686: [(set (match_operand:DF 0 "general_operand" "=f") 1687: (float:DF (match_operand:SI 1 "general_operand" "dmi")))] 1688: "TARGET_68881" 1689: "f%&move%.l %1,%0") 1690: 1691: (define_insn "floathisf2" 1692: [(set (match_operand:SF 0 "general_operand" "=f") 1693: (float:SF (match_operand:HI 1 "general_operand" "dmn")))] 1694: "TARGET_68881" 1695: "f%$move%.w %1,%0") 1696: 1697: (define_insn "floathidf2" 1698: [(set (match_operand:DF 0 "general_operand" "=f") 1699: (float:DF (match_operand:HI 1 "general_operand" "dmn")))] 1700: "TARGET_68881" 1701: "fmove%.w %1,%0") 1702: 1703: (define_insn "floatqisf2" 1704: [(set (match_operand:SF 0 "general_operand" "=f") 1705: (float:SF (match_operand:QI 1 "general_operand" "dmn")))] 1706: "TARGET_68881" 1707: "fmove%.b %1,%0") 1708: 1709: (define_insn "floatqidf2" 1710: [(set (match_operand:DF 0 "general_operand" "=f") 1711: (float:DF (match_operand:QI 1 "general_operand" "dmn")))] 1712: "TARGET_68881" 1713: "f%&move%.b %1,%0") 1714: 1715: ;; New routines to convert floating-point values to integers 1716: ;; to be used on the '040. These should be faster than trapping 1717: ;; into the kernel to emulate fintrz. They should also be faster 1718: ;; than calling the subroutines fixsfsi or fixdfsi. 1719: 1720: (define_insn "fix_truncdfsi2" 1721: [(set (match_operand:SI 0 "general_operand" "=dm") 1722: (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) 1723: (clobber (match_scratch:SI 2 "=d")) 1724: (clobber (match_scratch:SI 3 "=d"))] 1.1.1.2 root 1725: "TARGET_68881 && TARGET_68040" 1.1 root 1726: "* 1727: { 1728: CC_STATUS_INIT; 1729: return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\"; 1730: }") 1731: 1732: (define_insn "fix_truncdfhi2" 1733: [(set (match_operand:HI 0 "general_operand" "=dm") 1734: (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f")))) 1735: (clobber (match_scratch:SI 2 "=d")) 1736: (clobber (match_scratch:SI 3 "=d"))] 1.1.1.2 root 1737: "TARGET_68881 && TARGET_68040" 1.1 root 1738: "* 1739: { 1740: CC_STATUS_INIT; 1741: return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\"; 1742: }") 1743: 1744: (define_insn "fix_truncdfqi2" 1745: [(set (match_operand:QI 0 "general_operand" "=dm") 1746: (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f")))) 1747: (clobber (match_scratch:SI 2 "=d")) 1748: (clobber (match_scratch:SI 3 "=d"))] 1.1.1.2 root 1749: "TARGET_68881 && TARGET_68040" 1.1 root 1750: "* 1751: { 1752: CC_STATUS_INIT; 1753: return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\"; 1754: }") 1755: 1756: ;; Convert a float to a float whose value is an integer. 1757: ;; This is the first stage of converting it to an integer type. 1758: 1759: (define_insn "ftruncdf2" 1760: [(set (match_operand:DF 0 "general_operand" "=f") 1761: (fix:DF (match_operand:DF 1 "general_operand" "fFm")))] 1762: "TARGET_68881 && !TARGET_68040" 1763: "* 1764: { 1765: if (FP_REG_P (operands[1])) 1766: return \"fintrz%.x %f1,%0\"; 1767: return \"fintrz%.d %f1,%0\"; 1768: }") 1769: 1770: (define_insn "ftruncsf2" 1771: [(set (match_operand:SF 0 "general_operand" "=f") 1772: (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))] 1773: "TARGET_68881 && !TARGET_68040" 1774: "* 1775: { 1776: if (FP_REG_P (operands[1])) 1777: return \"fintrz%.x %f1,%0\"; 1778: return \"fintrz%.s %f1,%0\"; 1779: }") 1780: 1781: ;; Convert a float whose value is an integer 1782: ;; to an actual integer. Second stage of converting float to integer type. 1783: (define_insn "fixsfqi2" 1784: [(set (match_operand:QI 0 "general_operand" "=dm") 1785: (fix:QI (match_operand:SF 1 "general_operand" "f")))] 1786: "TARGET_68881" 1787: "fmove%.b %1,%0") 1788: 1789: (define_insn "fixsfhi2" 1790: [(set (match_operand:HI 0 "general_operand" "=dm") 1791: (fix:HI (match_operand:SF 1 "general_operand" "f")))] 1792: "TARGET_68881" 1793: "fmove%.w %1,%0") 1794: 1795: (define_insn "fixsfsi2" 1796: [(set (match_operand:SI 0 "general_operand" "=dm") 1797: (fix:SI (match_operand:SF 1 "general_operand" "f")))] 1798: "TARGET_68881" 1799: "fmove%.l %1,%0") 1800: 1801: (define_insn "fixdfqi2" 1802: [(set (match_operand:QI 0 "general_operand" "=dm") 1803: (fix:QI (match_operand:DF 1 "general_operand" "f")))] 1804: "TARGET_68881" 1805: "fmove%.b %1,%0") 1806: 1807: (define_insn "fixdfhi2" 1808: [(set (match_operand:HI 0 "general_operand" "=dm") 1809: (fix:HI (match_operand:DF 1 "general_operand" "f")))] 1810: "TARGET_68881" 1811: "fmove%.w %1,%0") 1812: 1813: (define_insn "fixdfsi2" 1814: [(set (match_operand:SI 0 "general_operand" "=dm") 1815: (fix:SI (match_operand:DF 1 "general_operand" "f")))] 1816: "TARGET_68881" 1817: "fmove%.l %1,%0") 1818: 1819: ;; Convert a float to an integer. 1820: ;; On the Sun FPA, this is done in one step. 1821: 1822: (define_insn "" 1823: [(set (match_operand:SI 0 "general_operand" "=x,y") 1824: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))] 1825: "TARGET_FPA" 1826: "fpstol %w1,%0") 1827: 1828: (define_insn "" 1829: [(set (match_operand:SI 0 "general_operand" "=x,y") 1830: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))] 1831: "TARGET_FPA" 1832: "fpdtol %y1,%0") 1833: 1834: ;; add instructions 1835: 1836: ;; Note that the middle two alternatives are near-duplicates 1837: ;; in order to handle insns generated by reload. 1838: ;; This is needed since they are not themselves reloaded, 1839: ;; so commutativity won't apply to them. 1840: (define_insn "addsi3" 1841: [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r") 1842: (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0") 1843: (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))] 1844: "" 1845: "* 1846: { 1847: if (! operands_match_p (operands[0], operands[1])) 1848: { 1849: if (!ADDRESS_REG_P (operands[1])) 1850: { 1851: rtx tmp = operands[1]; 1852: 1853: operands[1] = operands[2]; 1854: operands[2] = tmp; 1855: } 1856: 1857: /* These insns can result from reloads to access 1858: stack slots over 64k from the frame pointer. */ 1859: if (GET_CODE (operands[2]) == CONST_INT 1860: && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000) 1861: return \"move%.l %2,%0\;add%.l %1,%0\"; 1862: #ifdef SGS 1863: if (GET_CODE (operands[2]) == REG) 1864: return \"lea 0(%1,%2.l),%0\"; 1865: else 1866: return \"lea %c2(%1),%0\"; 1867: #else /* not SGS */ 1868: #ifdef MOTOROLA 1869: if (GET_CODE (operands[2]) == REG) 1870: return \"lea (%1,%2.l),%0\"; 1871: else 1872: return \"lea (%c2,%1),%0\"; 1873: #else /* not MOTOROLA (MIT syntax) */ 1874: if (GET_CODE (operands[2]) == REG) 1875: return \"lea %1@(0,%2:l),%0\"; 1876: else 1877: return \"lea %1@(%c2),%0\"; 1878: #endif /* not MOTOROLA */ 1879: #endif /* not SGS */ 1880: } 1881: if (GET_CODE (operands[2]) == CONST_INT) 1882: { 1883: #ifndef NO_ADDSUB_Q 1884: if (INTVAL (operands[2]) > 0 1885: && INTVAL (operands[2]) <= 8) 1886: return (ADDRESS_REG_P (operands[0]) 1887: ? \"addq%.w %2,%0\" 1888: : \"addq%.l %2,%0\"); 1889: if (INTVAL (operands[2]) < 0 1890: && INTVAL (operands[2]) >= -8) 1891: { 1892: operands[2] = gen_rtx (CONST_INT, VOIDmode, 1893: - INTVAL (operands[2])); 1894: return (ADDRESS_REG_P (operands[0]) 1895: ? \"subq%.w %2,%0\" 1896: : \"subq%.l %2,%0\"); 1897: } 1898: /* On everything except the 68000 it is faster to use two 1899: addqw instructions to add a small integer (8 < N <= 16) 1900: to an address register. Likewise for subqw.*/ 1901: if (INTVAL (operands[2]) > 8 1902: && INTVAL (operands[2]) <= 16 1903: && ADDRESS_REG_P (operands[0]) 1904: && TARGET_68020) 1905: { 1906: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); 1907: return \"addq%.w %#8,%0\;addq%.w %2,%0\"; 1908: } 1909: if (INTVAL (operands[2]) < -8 1910: && INTVAL (operands[2]) >= -16 1911: && ADDRESS_REG_P (operands[0]) 1912: && TARGET_68020) 1913: { 1914: operands[2] = gen_rtx (CONST_INT, VOIDmode, 1915: - INTVAL (operands[2]) - 8); 1916: return \"subq%.w %#8,%0\;subq%.w %2,%0\"; 1917: } 1918: #endif 1919: if (ADDRESS_REG_P (operands[0]) 1920: && INTVAL (operands[2]) >= -0x8000 1921: && INTVAL (operands[2]) < 0x8000) 1922: return \"add%.w %2,%0\"; 1923: } 1924: return \"add%.l %2,%0\"; 1925: }") 1926: 1927: (define_insn "" 1928: [(set (match_operand:SI 0 "general_operand" "=a") 1929: (plus:SI (match_operand:SI 1 "general_operand" "0") 1930: (sign_extend:SI 1931: (match_operand:HI 2 "nonimmediate_operand" "rm"))))] 1932: "" 1933: "add%.w %2,%0") 1934: 1935: (define_insn "addhi3" 1936: [(set (match_operand:HI 0 "general_operand" "=m,r") 1937: (plus:HI (match_operand:HI 1 "general_operand" "%0,0") 1938: (match_operand:HI 2 "general_operand" "dn,rmn")))] 1939: "" 1940: "* 1941: { 1942: #ifndef NO_ADDSUB_Q 1943: if (GET_CODE (operands[2]) == CONST_INT) 1944: { 1945: /* If the constant would be a negative number when interpreted as 1946: HImode, make it negative. This is usually, but not always, done 1947: elsewhere in the compiler. First check for constants out of range, 1948: which could confuse us. */ 1949: 1950: if (INTVAL (operands[2]) >= 32768) 1951: operands[2] = gen_rtx (CONST_INT, VOIDmode, 1952: INTVAL (operands[2]) - 65536); 1953: 1954: if (INTVAL (operands[2]) > 0 1955: && INTVAL (operands[2]) <= 8) 1956: return \"addq%.w %2,%0\"; 1957: if (INTVAL (operands[2]) < 0 1958: && INTVAL (operands[2]) >= -8) 1959: { 1960: operands[2] = gen_rtx (CONST_INT, VOIDmode, 1961: - INTVAL (operands[2])); 1962: return \"subq%.w %2,%0\"; 1963: } 1964: /* On everything except the 68000 it is faster to use two 1965: addqw instructions to add a small integer (8 < N <= 16) 1966: to an address register. Likewise for subqw. */ 1967: if (INTVAL (operands[2]) > 8 1968: && INTVAL (operands[2]) <= 16 1969: && ADDRESS_REG_P (operands[0]) 1970: && TARGET_68020) 1971: { 1972: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 8); 1973: return \"addq%.w %#8,%0\;addq%.w %2,%0\"; 1974: } 1975: if (INTVAL (operands[2]) < -8 1976: && INTVAL (operands[2]) >= -16 1977: && ADDRESS_REG_P (operands[0]) 1978: && TARGET_68020) 1979: { 1980: operands[2] = gen_rtx (CONST_INT, VOIDmode, 1981: - INTVAL (operands[2]) - 8); 1982: return \"subq%.w %#8,%0\;subq%.w %2,%0\"; 1983: } 1984: } 1985: #endif 1986: return \"add%.w %2,%0\"; 1987: }") 1988: 1989: ;; These insns must use MATCH_DUP instead of the more expected 1990: ;; use of a matching constraint because the "output" here is also 1991: ;; an input, so you can't use the matching constraint. That also means 1992: ;; that you can't use the "%", so you need patterns with the matched 1993: ;; operand in both positions. 1994: 1995: (define_insn "" 1996: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 1997: (plus:HI (match_dup 0) 1998: (match_operand:HI 1 "general_operand" "dn,rmn")))] 1999: "" 2000: "* 2001: { 2002: #ifndef NO_ADDSUB_Q 2003: if (GET_CODE (operands[1]) == CONST_INT) 2004: { 2005: /* If the constant would be a negative number when interpreted as 2006: HImode, make it negative. This is usually, but not always, done 2007: elsewhere in the compiler. First check for constants out of range, 2008: which could confuse us. */ 2009: 2010: if (INTVAL (operands[1]) >= 32768) 2011: operands[1] = gen_rtx (CONST_INT, VOIDmode, 2012: INTVAL (operands[1]) - 65536); 2013: 2014: if (INTVAL (operands[1]) > 0 2015: && INTVAL (operands[1]) <= 8) 2016: return \"addq%.w %1,%0\"; 2017: if (INTVAL (operands[1]) < 0 2018: && INTVAL (operands[1]) >= -8) 2019: { 2020: operands[1] = gen_rtx (CONST_INT, VOIDmode, 2021: - INTVAL (operands[1])); 2022: return \"subq%.w %1,%0\"; 2023: } 2024: /* On everything except the 68000 it is faster to use two 2025: addqw instructions to add a small integer (8 < N <= 16) 2026: to an address register. Likewise for subqw. */ 2027: if (INTVAL (operands[1]) > 8 2028: && INTVAL (operands[1]) <= 16 2029: && ADDRESS_REG_P (operands[0]) 2030: && TARGET_68020) 2031: { 2032: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); 2033: return \"addq%.w %#8,%0\;addq%.w %1,%0\"; 2034: } 2035: if (INTVAL (operands[1]) < -8 2036: && INTVAL (operands[1]) >= -16 2037: && ADDRESS_REG_P (operands[0]) 2038: && TARGET_68020) 2039: { 2040: operands[1] = gen_rtx (CONST_INT, VOIDmode, 2041: - INTVAL (operands[1]) - 8); 2042: return \"subq%.w %#8,%0\;subq%.w %1,%0\"; 2043: } 2044: } 2045: #endif 2046: return \"add%.w %1,%0\"; 2047: }") 2048: 2049: (define_insn "" 2050: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 2051: (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn") 2052: (match_dup 0)))] 2053: "" 2054: "* 2055: { 2056: #ifndef NO_ADDSUB_Q 2057: if (GET_CODE (operands[1]) == CONST_INT) 2058: { 2059: /* If the constant would be a negative number when interpreted as 2060: HImode, make it negative. This is usually, but not always, done 2061: elsewhere in the compiler. First check for constants out of range, 2062: which could confuse us. */ 2063: 2064: if (INTVAL (operands[1]) >= 32768) 2065: operands[1] = gen_rtx (CONST_INT, VOIDmode, 2066: INTVAL (operands[1]) - 65536); 2067: 2068: if (INTVAL (operands[1]) > 0 2069: && INTVAL (operands[1]) <= 8) 2070: return \"addq%.w %1,%0\"; 2071: if (INTVAL (operands[1]) < 0 2072: && INTVAL (operands[1]) >= -8) 2073: { 2074: operands[1] = gen_rtx (CONST_INT, VOIDmode, 2075: - INTVAL (operands[1])); 2076: return \"subq%.w %1,%0\"; 2077: } 2078: /* On everything except the 68000 it is faster to use two 2079: addqw instructions to add a small integer (8 < N <= 16) 2080: to an address register. Likewise for subqw. */ 2081: if (INTVAL (operands[1]) > 8 2082: && INTVAL (operands[1]) <= 16 2083: && ADDRESS_REG_P (operands[0]) 2084: && TARGET_68020) 2085: { 2086: operands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) - 8); 2087: return \"addq%.w %#8,%0\;addq%.w %1,%0\"; 2088: } 2089: if (INTVAL (operands[1]) < -8 2090: && INTVAL (operands[1]) >= -16 2091: && ADDRESS_REG_P (operands[0]) 2092: && TARGET_68020) 2093: { 2094: operands[1] = gen_rtx (CONST_INT, VOIDmode, 2095: - INTVAL (operands[1]) - 8); 2096: return \"subq%.w %#8,%0\;subq%.w %1,%0\"; 2097: } 2098: } 2099: #endif 2100: return \"add%.w %1,%0\"; 2101: }") 2102: 2103: (define_insn "addqi3" 2104: [(set (match_operand:QI 0 "general_operand" "=m,d") 2105: (plus:QI (match_operand:QI 1 "general_operand" "%0,0") 2106: (match_operand:QI 2 "general_operand" "dn,dmn")))] 2107: "" 2108: "* 2109: { 2110: #ifndef NO_ADDSUB_Q 2111: if (GET_CODE (operands[2]) == CONST_INT) 2112: { 2113: if (INTVAL (operands[2]) >= 128) 2114: operands[2] = gen_rtx (CONST_INT, VOIDmode, 2115: INTVAL (operands[2]) - 256); 2116: 2117: if (INTVAL (operands[2]) > 0 2118: && INTVAL (operands[2]) <= 8) 2119: return \"addq%.b %2,%0\"; 2120: if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8) 2121: { 2122: operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2])); 2123: return \"subq%.b %2,%0\"; 2124: } 2125: } 2126: #endif 2127: return \"add%.b %2,%0\"; 2128: }") 2129: 2130: (define_insn "" 2131: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 2132: (plus:QI (match_dup 0) 2133: (match_operand:QI 1 "general_operand" "dn,dmn")))] 2134: "" 2135: "* 2136: { 2137: #ifndef NO_ADDSUB_Q 2138: if (GET_CODE (operands[1]) == CONST_INT) 2139: { 2140: if (INTVAL (operands[1]) >= 128) 2141: operands[1] = gen_rtx (CONST_INT, VOIDmode, 2142: INTVAL (operands[1]) - 256); 2143: 2144: if (INTVAL (operands[1]) > 0 2145: && INTVAL (operands[1]) <= 8) 2146: return \"addq%.b %1,%0\"; 2147: if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) 2148: { 2149: operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); 2150: return \"subq%.b %1,%0\"; 2151: } 2152: } 2153: #endif 2154: return \"add%.b %1,%0\"; 2155: }") 2156: 2157: (define_insn "" 2158: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 2159: (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn") 2160: (match_dup 0)))] 2161: "" 2162: "* 2163: { 2164: #ifndef NO_ADDSUB_Q 2165: if (GET_CODE (operands[1]) == CONST_INT) 2166: { 2167: if (INTVAL (operands[1]) >= 128) 2168: operands[1] = gen_rtx (CONST_INT, VOIDmode, 2169: INTVAL (operands[1]) - 256); 2170: 2171: if (INTVAL (operands[1]) > 0 2172: && INTVAL (operands[1]) <= 8) 2173: return \"addq%.b %1,%0\"; 2174: if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) 2175: { 2176: operands[1] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[1])); 2177: return \"subq%.b %1,%0\"; 2178: } 2179: } 2180: #endif 2181: return \"add%.b %1,%0\"; 2182: }") 2183: 2184: (define_expand "adddf3" 2185: [(set (match_operand:DF 0 "general_operand" "") 2186: (plus:DF (match_operand:DF 1 "general_operand" "") 2187: (match_operand:DF 2 "general_operand" "")))] 2188: "TARGET_68881 || TARGET_FPA" 2189: "") 2190: 2191: (define_insn "" 2192: [(set (match_operand:DF 0 "general_operand" "=x,y") 2193: (plus:DF (match_operand:DF 1 "general_operand" "%xH,y") 2194: (match_operand:DF 2 "general_operand" "xH,dmF")))] 2195: "TARGET_FPA" 2196: "* 2197: { 2198: if (rtx_equal_p (operands[0], operands[1])) 2199: return \"fpadd%.d %y2,%0\"; 2200: if (rtx_equal_p (operands[0], operands[2])) 2201: return \"fpadd%.d %y1,%0\"; 2202: if (which_alternative == 0) 2203: return \"fpadd3%.d %w2,%w1,%0\"; 2204: return \"fpadd3%.d %x2,%x1,%0\"; 2205: }") 2206: 2207: (define_insn "" 2208: [(set (match_operand:DF 0 "general_operand" "=f") 2209: (plus:DF (match_operand:DF 1 "general_operand" "%0") 2210: (match_operand:DF 2 "general_operand" "fmG")))] 2211: "TARGET_68881" 2212: "* 2213: { 2214: if (REG_P (operands[2])) 2215: return \"f%&add%.x %2,%0\"; 2216: return \"f%&add%.d %f2,%0\"; 2217: }") 2218: 2219: (define_expand "addsf3" 2220: [(set (match_operand:SF 0 "general_operand" "") 2221: (plus:SF (match_operand:SF 1 "general_operand" "") 2222: (match_operand:SF 2 "general_operand" "")))] 2223: "TARGET_68881 || TARGET_FPA" 2224: "") 2225: 2226: (define_insn "" 2227: [(set (match_operand:SF 0 "general_operand" "=x,y") 2228: (plus:SF (match_operand:SF 1 "general_operand" "%xH,y") 2229: (match_operand:SF 2 "general_operand" "xH,rmF")))] 2230: "TARGET_FPA" 2231: "* 2232: { 2233: if (rtx_equal_p (operands[0], operands[1])) 2234: return \"fpadd%.s %w2,%0\"; 2235: if (rtx_equal_p (operands[0], operands[2])) 2236: return \"fpadd%.s %w1,%0\"; 2237: if (which_alternative == 0) 2238: return \"fpadd3%.s %w2,%w1,%0\"; 2239: return \"fpadd3%.s %2,%1,%0\"; 2240: }") 2241: 2242: (define_insn "" 2243: [(set (match_operand:SF 0 "general_operand" "=f") 2244: (plus:SF (match_operand:SF 1 "general_operand" "%0") 2245: (match_operand:SF 2 "general_operand" "fdmF")))] 2246: "TARGET_68881" 2247: "* 2248: { 2249: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) 2250: return \"f%$add%.x %2,%0\"; 2251: return \"f%$add%.s %f2,%0\"; 2252: }") 2253: 2254: ;; subtract instructions 2255: 2256: (define_insn "subsi3" 1.1.1.3 ! root 2257: [(set (match_operand:SI 0 "general_operand" "=m,r") ! 2258: (minus:SI (match_operand:SI 1 "general_operand" "0,0") ! 2259: (match_operand:SI 2 "general_operand" "ds,mrs")))] 1.1 root 2260: "" 1.1.1.3 ! root 2261: "sub%.l %2,%0") 1.1 root 2262: 2263: (define_insn "" 2264: [(set (match_operand:SI 0 "general_operand" "=a") 2265: (minus:SI (match_operand:SI 1 "general_operand" "0") 2266: (sign_extend:SI 2267: (match_operand:HI 2 "nonimmediate_operand" "rm"))))] 2268: "" 2269: "sub%.w %2,%0") 2270: 2271: (define_insn "subhi3" 2272: [(set (match_operand:HI 0 "general_operand" "=m,r") 2273: (minus:HI (match_operand:HI 1 "general_operand" "0,0") 2274: (match_operand:HI 2 "general_operand" "dn,rmn")))] 2275: "" 2276: "sub%.w %2,%0") 2277: 2278: (define_insn "" 2279: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 2280: (minus:HI (match_dup 0) 2281: (match_operand:HI 1 "general_operand" "dn,rmn")))] 2282: "" 2283: "sub%.w %1,%0") 2284: 2285: (define_insn "subqi3" 2286: [(set (match_operand:QI 0 "general_operand" "=m,d") 2287: (minus:QI (match_operand:QI 1 "general_operand" "0,0") 2288: (match_operand:QI 2 "general_operand" "dn,dmn")))] 2289: "" 2290: "sub%.b %2,%0") 2291: 2292: (define_insn "" 2293: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 2294: (minus:QI (match_dup 0) 2295: (match_operand:QI 1 "general_operand" "dn,dmn")))] 2296: "" 2297: "sub%.b %1,%0") 2298: 2299: (define_expand "subdf3" 2300: [(set (match_operand:DF 0 "general_operand" "") 2301: (minus:DF (match_operand:DF 1 "general_operand" "") 2302: (match_operand:DF 2 "general_operand" "")))] 2303: "TARGET_68881 || TARGET_FPA" 2304: "") 2305: 2306: (define_insn "" 2307: [(set (match_operand:DF 0 "general_operand" "=x,y,y") 2308: (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF") 2309: (match_operand:DF 2 "general_operand" "xH,dmF,0")))] 2310: "TARGET_FPA" 2311: "* 2312: { 2313: if (rtx_equal_p (operands[0], operands[2])) 2314: return \"fprsub%.d %y1,%0\"; 2315: if (rtx_equal_p (operands[0], operands[1])) 2316: return \"fpsub%.d %y2,%0\"; 2317: if (which_alternative == 0) 2318: return \"fpsub3%.d %w2,%w1,%0\"; 2319: return \"fpsub3%.d %x2,%x1,%0\"; 2320: }") 2321: 2322: (define_insn "" 2323: [(set (match_operand:DF 0 "general_operand" "=f") 2324: (minus:DF (match_operand:DF 1 "general_operand" "0") 2325: (match_operand:DF 2 "general_operand" "fmG")))] 2326: "TARGET_68881" 2327: "* 2328: { 2329: if (REG_P (operands[2])) 2330: return \"f%&sub%.x %2,%0\"; 2331: return \"f%&sub%.d %f2,%0\"; 2332: }") 2333: 2334: (define_expand "subsf3" 2335: [(set (match_operand:SF 0 "general_operand" "") 2336: (minus:SF (match_operand:SF 1 "general_operand" "") 2337: (match_operand:SF 2 "general_operand" "")))] 2338: "TARGET_68881 || TARGET_FPA" 2339: "") 2340: 2341: (define_insn "" 2342: [(set (match_operand:SF 0 "general_operand" "=x,y,y") 2343: (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF") 2344: (match_operand:SF 2 "general_operand" "xH,rmF,0")))] 2345: "TARGET_FPA" 2346: "* 2347: { 2348: if (rtx_equal_p (operands[0], operands[2])) 2349: return \"fprsub%.s %w1,%0\"; 2350: if (rtx_equal_p (operands[0], operands[1])) 2351: return \"fpsub%.s %w2,%0\"; 2352: if (which_alternative == 0) 2353: return \"fpsub3%.s %w2,%w1,%0\"; 2354: return \"fpsub3%.s %2,%1,%0\"; 2355: }") 2356: 2357: (define_insn "" 2358: [(set (match_operand:SF 0 "general_operand" "=f") 2359: (minus:SF (match_operand:SF 1 "general_operand" "0") 2360: (match_operand:SF 2 "general_operand" "fdmF")))] 2361: "TARGET_68881" 2362: "* 2363: { 2364: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) 2365: return \"f%$sub%.x %2,%0\"; 2366: return \"f%$sub%.s %f2,%0\"; 2367: }") 2368: 2369: ;; multiply instructions 2370: 2371: (define_insn "mulhi3" 2372: [(set (match_operand:HI 0 "general_operand" "=d") 2373: (mult:HI (match_operand:HI 1 "general_operand" "%0") 2374: (match_operand:HI 2 "general_operand" "dmn")))] 2375: "" 2376: "* 2377: { 2378: #if defined(MOTOROLA) && !defined(CRDS) 2379: return \"muls%.w %2,%0\"; 2380: #else 2381: return \"muls %2,%0\"; 2382: #endif 2383: }") 2384: 2385: (define_insn "mulhisi3" 2386: [(set (match_operand:SI 0 "general_operand" "=d") 2387: (mult:SI (sign_extend:SI 2388: (match_operand:HI 1 "nonimmediate_operand" "%0")) 2389: (sign_extend:SI 2390: (match_operand:HI 2 "nonimmediate_operand" "dm"))))] 2391: "" 2392: "* 2393: { 2394: #if defined(MOTOROLA) && !defined(CRDS) 2395: return \"muls%.w %2,%0\"; 2396: #else 2397: return \"muls %2,%0\"; 2398: #endif 2399: }") 2400: 2401: (define_insn "" 2402: [(set (match_operand:SI 0 "general_operand" "=d") 2403: (mult:SI (sign_extend:SI 2404: (match_operand:HI 1 "nonimmediate_operand" "%0")) 2405: (match_operand:SI 2 "const_int_operand" "n")))] 2406: "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff" 2407: "* 2408: { 2409: #if defined(MOTOROLA) && !defined(CRDS) 2410: return \"muls%.w %2,%0\"; 2411: #else 2412: return \"muls %2,%0\"; 2413: #endif 2414: }") 2415: 2416: (define_insn "mulsi3" 2417: [(set (match_operand:SI 0 "general_operand" "=d") 2418: (mult:SI (match_operand:SI 1 "general_operand" "%0") 2419: (match_operand:SI 2 "general_operand" "dmsK")))] 2420: "TARGET_68020" 2421: "muls%.l %2,%0") 2422: 2423: (define_insn "umulhisi3" 2424: [(set (match_operand:SI 0 "general_operand" "=d") 2425: (mult:SI (zero_extend:SI 2426: (match_operand:HI 1 "nonimmediate_operand" "%0")) 2427: (zero_extend:SI 2428: (match_operand:HI 2 "nonimmediate_operand" "dm"))))] 2429: "" 2430: "* 2431: { 2432: #if defined(MOTOROLA) && !defined(CRDS) 2433: return \"mulu%.w %2,%0\"; 2434: #else 2435: return \"mulu %2,%0\"; 2436: #endif 2437: }") 2438: 2439: (define_insn "" 2440: [(set (match_operand:SI 0 "general_operand" "=d") 2441: (mult:SI (zero_extend:SI 2442: (match_operand:HI 1 "nonimmediate_operand" "%0")) 2443: (match_operand:SI 2 "const_int_operand" "n")))] 2444: "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff" 2445: "* 2446: { 2447: #if defined(MOTOROLA) && !defined(CRDS) 2448: return \"mulu%.w %2,%0\"; 2449: #else 2450: return \"mulu %2,%0\"; 2451: #endif 2452: }") 2453: 2454: ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the 2455: ;; proper matching constraint. This is because the matching is between 2456: ;; the high-numbered word of the DImode operand[0] and operand[1]. 2457: (define_expand "umulsidi3" 2458: [(parallel 2459: [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1) 2460: (mult:SI (match_operand:SI 1 "register_operand" "") 2461: (match_operand:SI 2 "nonimmediate_operand" ""))) 2462: (set (subreg:SI (match_dup 0) 0) 2463: (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) 2464: (zero_extend:DI (match_dup 2))) 2465: (const_int 32))))])] 2466: "TARGET_68020" 2467: "") 2468: 2469: (define_insn "" 2470: [(set (match_operand:SI 0 "register_operand" "=d") 2471: (mult:SI (match_operand:SI 1 "register_operand" "%0") 2472: (match_operand:SI 2 "nonimmediate_operand" "dm"))) 2473: (set (match_operand:SI 3 "register_operand" "=d") 2474: (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) 2475: (zero_extend:DI (match_dup 2))) 2476: (const_int 32))))] 2477: "TARGET_68020" 2478: "mulu%.l %2,%3:%0") 2479: 2480: ; Match immediate case. For 2.4 only match things < 2^31. 2481: ; It's tricky with larger values in these patterns since we need to match 2482: ; values between the two parallel multiplies, between a CONST_DOUBLE and 2483: ; a CONST_INT. 2484: (define_insn "" 2485: [(set (match_operand:SI 0 "register_operand" "=d") 2486: (mult:SI (match_operand:SI 1 "register_operand" "%0") 2487: (match_operand:SI 2 "const_int_operand" "n"))) 2488: (set (match_operand:SI 3 "register_operand" "=d") 2489: (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) 2490: (match_dup 2)) 2491: (const_int 32))))] 2492: "TARGET_68020 2493: && (unsigned) INTVAL (operands[2]) <= 0x7fffffff" 2494: "mulu%.l %2,%3:%0") 2495: 2496: (define_expand "mulsidi3" 2497: [(parallel 2498: [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1) 2499: (mult:SI (match_operand:SI 1 "register_operand" "") 2500: (match_operand:SI 2 "nonimmediate_operand" ""))) 2501: (set (subreg:SI (match_dup 0) 0) 1.1.1.2 root 2502: (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) 2503: (sign_extend:DI (match_dup 2))) 2504: (const_int 32))))])] 1.1 root 2505: "TARGET_68020" 2506: "") 2507: 2508: (define_insn "" 2509: [(set (match_operand:SI 0 "register_operand" "=d") 2510: (mult:SI (match_operand:SI 1 "register_operand" "%0") 2511: (match_operand:SI 2 "nonimmediate_operand" "dm"))) 2512: (set (match_operand:SI 3 "register_operand" "=d") 1.1.1.2 root 2513: (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) 2514: (sign_extend:DI (match_dup 2))) 2515: (const_int 32))))] 1.1 root 2516: "TARGET_68020" 2517: "muls%.l %2,%3:%0") 2518: 2519: (define_insn "" 2520: [(set (match_operand:SI 0 "register_operand" "=d") 2521: (mult:SI (match_operand:SI 1 "register_operand" "%0") 2522: (match_operand:SI 2 "const_int_operand" "n"))) 2523: (set (match_operand:SI 3 "register_operand" "=d") 1.1.1.2 root 2524: (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) 2525: (match_dup 2)) 2526: (const_int 32))))] 1.1 root 2527: "TARGET_68020 2528: /* This test is a noop on 32 bit machines, 2529: but important for a cross-compiler hosted on 64-bit machines. */ 2530: && INTVAL (operands[2]) <= 0x7fffffff 2531: && INTVAL (operands[2]) >= -0x80000000" 2532: "muls%.l %2,%3:%0") 2533: 1.1.1.3 ! root 2534: (define_expand "umulsi3_highpart" ! 2535: [(parallel ! 2536: [(set (match_operand:SI 0 "register_operand" "") ! 2537: (truncate:SI ! 2538: (lshiftrt:DI ! 2539: (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) ! 2540: (zero_extend:DI (match_operand:SI 2 "general_operand" ""))) ! 2541: (const_int 32)))) ! 2542: (clobber (match_dup 3))])] ! 2543: "TARGET_68020" ! 2544: " ! 2545: { ! 2546: operands[3] = gen_reg_rtx (SImode); ! 2547: if (CONSTANT_P (operands[2])) ! 2548: { ! 2549: /* We have to rearrange the operand order for the matching constraints. */ ! 2550: emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3], ! 2551: operands[1], operands[2])); ! 2552: DONE; ! 2553: } ! 2554: }") ! 2555: ! 2556: (define_insn "" ! 2557: [(set (match_operand:SI 0 "register_operand" "=d") ! 2558: (truncate:SI ! 2559: (lshiftrt:DI ! 2560: (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1")) ! 2561: (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) ! 2562: (const_int 32)))) ! 2563: (clobber (match_operand:SI 1 "register_operand" "=d"))] ! 2564: "TARGET_68020" ! 2565: "mulu%.l %3,%0:%1") ! 2566: ! 2567: (define_insn "const_umulsi3_highpart" ! 2568: [(set (match_operand:SI 0 "register_operand" "=d") ! 2569: (truncate:SI ! 2570: (lshiftrt:DI ! 2571: (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1")) ! 2572: (match_operand:DI 3 "immediate_operand" "i")) ! 2573: (const_int 32)))) ! 2574: (clobber (match_operand:SI 1 "register_operand" "=d"))] ! 2575: "TARGET_68020" ! 2576: "mulu%.l %3,%0:%1") ! 2577: ! 2578: (define_expand "smulsi3_highpart" ! 2579: [(parallel ! 2580: [(set (match_operand:SI 0 "register_operand" "") ! 2581: (truncate:SI ! 2582: (lshiftrt:DI ! 2583: (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) ! 2584: (sign_extend:DI (match_operand:SI 2 "general_operand" ""))) ! 2585: (const_int 32)))) ! 2586: (clobber (match_dup 3))])] ! 2587: "TARGET_68020" ! 2588: " ! 2589: { ! 2590: operands[3] = gen_reg_rtx (SImode); ! 2591: if (CONSTANT_P (operands[2])) ! 2592: { ! 2593: /* We have to rearrange the operand order for the matching constraints. */ ! 2594: emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3], ! 2595: operands[1], operands[2])); ! 2596: DONE; ! 2597: } ! 2598: }") ! 2599: ! 2600: (define_insn "" ! 2601: [(set (match_operand:SI 0 "register_operand" "=d") ! 2602: (truncate:SI ! 2603: (lshiftrt:DI ! 2604: (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1")) ! 2605: (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) ! 2606: (const_int 32)))) ! 2607: (clobber (match_operand:SI 1 "register_operand" "=d"))] ! 2608: "TARGET_68020" ! 2609: "muls%.l %3,%0:%1") ! 2610: ! 2611: (define_insn "const_smulsi3_highpart" ! 2612: [(set (match_operand:SI 0 "register_operand" "=d") ! 2613: (truncate:SI ! 2614: (lshiftrt:DI ! 2615: (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1")) ! 2616: (match_operand:DI 3 "immediate_operand" "i")) ! 2617: (const_int 32)))) ! 2618: (clobber (match_operand:SI 1 "register_operand" "=d"))] ! 2619: "TARGET_68020" ! 2620: "muls%.l %3,%0:%1") ! 2621: 1.1 root 2622: (define_expand "muldf3" 2623: [(set (match_operand:DF 0 "general_operand" "") 2624: (mult:DF (match_operand:DF 1 "general_operand" "") 2625: (match_operand:DF 2 "general_operand" "")))] 2626: "TARGET_68881 || TARGET_FPA" 2627: "") 2628: 2629: (define_insn "" 2630: [(set (match_operand:DF 0 "general_operand" "=x,y") 2631: (mult:DF (match_operand:DF 1 "general_operand" "%xH,y") 2632: (match_operand:DF 2 "general_operand" "xH,rmF")))] 2633: "TARGET_FPA" 2634: "* 2635: { 2636: if (rtx_equal_p (operands[1], operands[2])) 2637: return \"fpsqr%.d %y1,%0\"; 2638: if (rtx_equal_p (operands[0], operands[1])) 2639: return \"fpmul%.d %y2,%0\"; 2640: if (rtx_equal_p (operands[0], operands[2])) 2641: return \"fpmul%.d %y1,%0\"; 2642: if (which_alternative == 0) 2643: return \"fpmul3%.d %w2,%w1,%0\"; 2644: return \"fpmul3%.d %x2,%x1,%0\"; 2645: }") 2646: 2647: (define_insn "" 2648: [(set (match_operand:DF 0 "general_operand" "=f") 2649: (mult:DF (match_operand:DF 1 "general_operand" "%0") 2650: (match_operand:DF 2 "general_operand" "fmG")))] 2651: "TARGET_68881" 2652: "* 2653: { 2654: if (GET_CODE (operands[2]) == CONST_DOUBLE 2655: && floating_exact_log2 (operands[2]) && !TARGET_68040) 2656: { 2657: int i = floating_exact_log2 (operands[2]); 2658: operands[2] = gen_rtx (CONST_INT, VOIDmode, i); 2659: return \"fscale%.l %2,%0\"; 2660: } 2661: if (REG_P (operands[2])) 2662: return \"f%&mul%.x %2,%0\"; 2663: return \"f%&mul%.d %f2,%0\"; 2664: }") 2665: 2666: (define_expand "mulsf3" 2667: [(set (match_operand:SF 0 "general_operand" "") 2668: (mult:SF (match_operand:SF 1 "general_operand" "") 2669: (match_operand:SF 2 "general_operand" "")))] 2670: "TARGET_68881 || TARGET_FPA" 2671: "") 2672: 2673: (define_insn "" 2674: [(set (match_operand:SF 0 "general_operand" "=x,y") 2675: (mult:SF (match_operand:SF 1 "general_operand" "%xH,y") 2676: (match_operand:SF 2 "general_operand" "xH,rmF")))] 2677: "TARGET_FPA" 2678: "* 2679: { 2680: if (rtx_equal_p (operands[1], operands[2])) 2681: return \"fpsqr%.s %w1,%0\"; 2682: if (rtx_equal_p (operands[0], operands[1])) 2683: return \"fpmul%.s %w2,%0\"; 2684: if (rtx_equal_p (operands[0], operands[2])) 2685: return \"fpmul%.s %w1,%0\"; 2686: if (which_alternative == 0) 2687: return \"fpmul3%.s %w2,%w1,%0\"; 2688: return \"fpmul3%.s %2,%1,%0\"; 2689: }") 2690: 2691: (define_insn "" 2692: [(set (match_operand:SF 0 "general_operand" "=f") 2693: (mult:SF (match_operand:SF 1 "general_operand" "%0") 2694: (match_operand:SF 2 "general_operand" "fdmF")))] 2695: "TARGET_68881" 2696: "* 2697: { 2698: #ifdef FSGLMUL_USE_S 2699: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) 2700: return (TARGET_68040_ONLY 2701: ? \"fsmul%.s %2,%0\" 2702: : \"fsglmul%.s %2,%0\"); 2703: #else 2704: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) 2705: return (TARGET_68040_ONLY 2706: ? \"fsmul%.x %2,%0\" 2707: : \"fsglmul%.x %2,%0\"); 2708: #endif 2709: return (TARGET_68040_ONLY 2710: ? \"fsmul%.s %f2,%0\" 2711: : \"fsglmul%.s %f2,%0\"); 2712: }") 2713: 2714: ;; divide instructions 2715: 2716: (define_insn "divhi3" 2717: [(set (match_operand:HI 0 "general_operand" "=d") 2718: (div:HI (match_operand:HI 1 "general_operand" "0") 2719: (match_operand:HI 2 "general_operand" "dmn")))] 2720: "" 2721: "* 2722: { 2723: #ifdef MOTOROLA 2724: return \"ext%.l %0\;divs%.w %2,%0\"; 2725: #else 2726: return \"extl %0\;divs %2,%0\"; 2727: #endif 2728: }") 2729: 1.1.1.2 root 2730: ;; These patterns don't work because the divs instruction is undefined if 2731: ;; the quotient is more than 16 bits. This valid C would be miscompiled: 2732: ;; int n; short d; unsigned short q; ... q = (unsigned int) (n / d); 2733: ;; Imagine what happens when n = 100000 and d = 1. 2734: ;;(define_insn "divhisi3" 2735: ;; [(set (match_operand:HI 0 "general_operand" "=d") 2736: ;; (truncate:HI 2737: ;; (div:SI 2738: ;; (match_operand:SI 1 "general_operand" "0") 2739: ;; (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] 2740: ;; "" 2741: ;; "* 2742: ;;{ 2743: ;;#ifdef MOTOROLA 2744: ;; return \"divs%.w %2,%0\"; 2745: ;;#else 2746: ;; return \"divs %2,%0\"; 2747: ;;#endif 2748: ;;}") 2749: 2750: ;;(define_insn "" 2751: ;; [(set (match_operand:HI 0 "general_operand" "=d") 2752: ;; (truncate:HI (div:SI (match_operand:SI 1 "general_operand" "0") 2753: ;; (match_operand:SI 2 "const_int_operand" "n"))))] 2754: ;; "" 2755: ;; "* 2756: ;;{ 2757: ;;#ifdef MOTOROLA 2758: ;; return \"divs%.w %2,%0\"; 2759: ;;#else 2760: ;; return \"divs %2,%0\"; 2761: ;;#endif 2762: ;;}") 1.1 root 2763: 2764: (define_insn "udivhi3" 2765: [(set (match_operand:HI 0 "general_operand" "=d") 2766: (udiv:HI (match_operand:HI 1 "general_operand" "0") 2767: (match_operand:HI 2 "general_operand" "dmn")))] 2768: "" 2769: "* 2770: { 2771: #ifdef MOTOROLA 2772: return \"and%.l %#0xFFFF,%0\;divu%.w %2,%0\"; 2773: #else 2774: return \"andl %#0xFFFF,%0\;divu %2,%0\"; 2775: #endif 2776: }") 2777: 1.1.1.2 root 2778: ;; See comment before divhisi3 why these are commented out. 2779: ;;(define_insn "udivhisi3" 2780: ;; [(set (match_operand:HI 0 "general_operand" "=d") 2781: ;; (truncate:HI 2782: ;; (udiv:SI 2783: ;; (match_operand:SI 1 "general_operand" "0") 2784: ;; (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] 2785: ;; "" 2786: ;; "* 2787: ;;{ 2788: ;;#ifdef MOTOROLA 2789: ;; return \"divu%.w %2,%0\"; 2790: ;;#else 2791: ;; return \"divu %2,%0\"; 2792: ;;#endif 2793: ;;}") 2794: 2795: ;;(define_insn "" 2796: ;; [(set (match_operand:HI 0 "general_operand" "=d") 2797: ;; (truncate:HI (udiv:SI (match_operand:SI 1 "general_operand" "0") 2798: ;; (match_operand:SI 2 "const_int_operand" "n"))))] 2799: ;; "" 2800: ;; "* 2801: ;;{ 2802: ;;#ifdef MOTOROLA 2803: ;; return \"divu%.w %2,%0\"; 2804: ;;#else 2805: ;; return \"divu %2,%0\"; 2806: ;;#endif 2807: ;;}") 1.1 root 2808: 2809: (define_expand "divdf3" 2810: [(set (match_operand:DF 0 "general_operand" "") 2811: (div:DF (match_operand:DF 1 "general_operand" "") 2812: (match_operand:DF 2 "general_operand" "")))] 2813: "TARGET_68881 || TARGET_FPA" 2814: "") 2815: 2816: (define_insn "" 2817: [(set (match_operand:DF 0 "general_operand" "=x,y,y") 2818: (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF") 2819: (match_operand:DF 2 "general_operand" "xH,rmF,0")))] 2820: "TARGET_FPA" 2821: "* 2822: { 2823: if (rtx_equal_p (operands[0], operands[2])) 2824: return \"fprdiv%.d %y1,%0\"; 2825: if (rtx_equal_p (operands[0], operands[1])) 2826: return \"fpdiv%.d %y2,%0\"; 2827: if (which_alternative == 0) 2828: return \"fpdiv3%.d %w2,%w1,%0\"; 2829: return \"fpdiv3%.d %x2,%x1,%x0\"; 2830: }") 2831: 2832: (define_insn "" 2833: [(set (match_operand:DF 0 "general_operand" "=f") 2834: (div:DF (match_operand:DF 1 "general_operand" "0") 2835: (match_operand:DF 2 "general_operand" "fmG")))] 2836: "TARGET_68881" 2837: "* 2838: { 2839: if (REG_P (operands[2])) 2840: return \"f%&div%.x %2,%0\"; 2841: return \"f%&div%.d %f2,%0\"; 2842: }") 2843: 2844: (define_expand "divsf3" 2845: [(set (match_operand:SF 0 "general_operand" "") 2846: (div:SF (match_operand:SF 1 "general_operand" "") 2847: (match_operand:SF 2 "general_operand" "")))] 2848: "TARGET_68881 || TARGET_FPA" 2849: "") 2850: 2851: (define_insn "" 2852: [(set (match_operand:SF 0 "general_operand" "=x,y,y") 2853: (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF") 2854: (match_operand:SF 2 "general_operand" "xH,rmF,0")))] 2855: "TARGET_FPA" 2856: "* 2857: { 2858: if (rtx_equal_p (operands[0], operands[1])) 2859: return \"fpdiv%.s %w2,%0\"; 2860: if (rtx_equal_p (operands[0], operands[2])) 2861: return \"fprdiv%.s %w1,%0\"; 2862: if (which_alternative == 0) 2863: return \"fpdiv3%.s %w2,%w1,%0\"; 2864: return \"fpdiv3%.s %2,%1,%0\"; 2865: }") 2866: 2867: (define_insn "" 2868: [(set (match_operand:SF 0 "general_operand" "=f") 2869: (div:SF (match_operand:SF 1 "general_operand" "0") 2870: (match_operand:SF 2 "general_operand" "fdmF")))] 2871: "TARGET_68881" 2872: "* 2873: { 2874: #ifdef FSGLDIV_USE_S 2875: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) 2876: return (TARGET_68040_ONLY 2877: ? \"fsdiv%.s %2,%0\" 2878: : \"fsgldiv%.s %2,%0\"); 2879: #else 2880: if (REG_P (operands[2]) && ! DATA_REG_P (operands[2])) 2881: return (TARGET_68040_ONLY 2882: ? \"fsdiv%.x %2,%0\" 2883: : \"fsgldiv%.x %2,%0\"); 2884: #endif 2885: return (TARGET_68040_ONLY 2886: ? \"fsdiv%.s %f2,%0\" 2887: : \"fsgldiv%.s %f2,%0\"); 2888: }") 2889: 2890: ;; Remainder instructions. 2891: 2892: (define_insn "modhi3" 2893: [(set (match_operand:HI 0 "general_operand" "=d") 2894: (mod:HI (match_operand:HI 1 "general_operand" "0") 2895: (match_operand:HI 2 "general_operand" "dmn")))] 2896: "" 2897: "* 2898: { 2899: /* The swap insn produces cc's that don't correspond to the result. */ 2900: CC_STATUS_INIT; 2901: #ifdef MOTOROLA 2902: return \"ext%.l %0\;divs%.w %2,%0\;swap %0\"; 2903: #else 2904: return \"extl %0\;divs %2,%0\;swap %0\"; 2905: #endif 2906: }") 2907: 1.1.1.2 root 2908: ;; See comment before divhisi3 why these are commented out. 2909: ;;(define_insn "modhisi3" 2910: ;; [(set (match_operand:HI 0 "general_operand" "=d") 2911: ;; (truncate:HI 2912: ;; (mod:SI 2913: ;; (match_operand:SI 1 "general_operand" "0") 2914: ;; (sign_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] 2915: ;; "" 2916: ;; "* 2917: ;;{ 2918: ;; /* The swap insn produces cc's that don't correspond to the result. */ 2919: ;; CC_STATUS_INIT; 2920: ;;#ifdef MOTOROLA 2921: ;; return \"divs%.w %2,%0\;swap %0\"; 2922: ;;#else 2923: ;; return \"divs %2,%0\;swap %0\"; 2924: ;;#endif 2925: ;;}") 2926: 2927: ;;(define_insn "" 2928: ;; [(set (match_operand:HI 0 "general_operand" "=d") 2929: ;; (truncate:HI (mod:SI (match_operand:SI 1 "general_operand" "0") 2930: ;; (match_operand:SI 2 "const_int_operand" "n"))))] 2931: ;; "" 2932: ;; "* 2933: ;;{ 2934: ;; /* The swap insn produces cc's that don't correspond to the result. */ 2935: ;; CC_STATUS_INIT; 2936: ;;#ifdef MOTOROLA 2937: ;; return \"divs%.w %2,%0\;swap %0\"; 2938: ;;#else 2939: ;; return \"divs %2,%0\;swap %0\"; 2940: ;;#endif 2941: ;;}") 1.1 root 2942: 2943: (define_insn "umodhi3" 2944: [(set (match_operand:HI 0 "general_operand" "=d") 2945: (umod:HI (match_operand:HI 1 "general_operand" "0") 2946: (match_operand:HI 2 "general_operand" "dmn")))] 2947: "" 2948: "* 2949: { 2950: /* The swap insn produces cc's that don't correspond to the result. */ 2951: CC_STATUS_INIT; 2952: #ifdef MOTOROLA 2953: return \"and%.l %#0xFFFF,%0\;divu%.w %2,%0\;swap %0\"; 2954: #else 2955: return \"andl %#0xFFFF,%0\;divu %2,%0\;swap %0\"; 2956: #endif 2957: }") 2958: 1.1.1.2 root 2959: ;; See comment before divhisi3 why these are commented out. 2960: ;;(define_insn "umodhisi3" 2961: ;; [(set (match_operand:HI 0 "general_operand" "=d") 2962: ;; (truncate:HI 2963: ;; (umod:SI 2964: ;; (match_operand:SI 1 "general_operand" "0") 2965: ;; (zero_extend:SI (match_operand:HI 2 "nonimmediate_operand" "dm")))))] 2966: ;; "" 2967: ;; "* 2968: ;;{ 2969: ;; /* The swap insn produces cc's that don't correspond to the result. */ 2970: ;; CC_STATUS_INIT; 2971: ;;#ifdef MOTOROLA 2972: ;; return \"divu%.w %2,%0\;swap %0\"; 2973: ;;#else 2974: ;; return \"divu %2,%0\;swap %0\"; 2975: ;;#endif 2976: ;;}") 2977: 2978: ;;(define_insn "" 2979: ;; [(set (match_operand:HI 0 "general_operand" "=d") 2980: ;; (truncate:HI (umod:SI (match_operand:SI 1 "general_operand" "0") 2981: ;; (match_operand:SI 2 "const_int_operand" "n"))))] 2982: ;; "" 2983: ;; "* 2984: ;;{ 2985: ;; /* The swap insn produces cc's that don't correspond to the result. */ 2986: ;; CC_STATUS_INIT; 2987: ;;#ifdef MOTOROLA 2988: ;; return \"divu%.w %2,%0\;swap %0\"; 2989: ;;#else 2990: ;; return \"divu %2,%0\;swap %0\"; 2991: ;;#endif 2992: ;;}") 1.1 root 2993: 2994: (define_insn "divmodsi4" 2995: [(set (match_operand:SI 0 "general_operand" "=d") 2996: (div:SI (match_operand:SI 1 "general_operand" "0") 2997: (match_operand:SI 2 "general_operand" "dmsK"))) 2998: (set (match_operand:SI 3 "general_operand" "=d") 2999: (mod:SI (match_dup 1) (match_dup 2)))] 3000: "TARGET_68020" 3001: "* 3002: { 3003: if (find_reg_note (insn, REG_UNUSED, operands[3])) 3004: return \"divs%.l %2,%0\"; 3005: else 3006: return \"divsl%.l %2,%3:%0\"; 3007: }") 3008: 3009: (define_insn "udivmodsi4" 3010: [(set (match_operand:SI 0 "general_operand" "=d") 3011: (udiv:SI (match_operand:SI 1 "general_operand" "0") 3012: (match_operand:SI 2 "general_operand" "dmsK"))) 3013: (set (match_operand:SI 3 "general_operand" "=d") 3014: (umod:SI (match_dup 1) (match_dup 2)))] 3015: "TARGET_68020" 3016: "* 3017: { 3018: if (find_reg_note (insn, REG_UNUSED, operands[3])) 3019: return \"divu%.l %2,%0\"; 3020: else 3021: return \"divul%.l %2,%3:%0\"; 3022: }") 3023: 3024: ;; logical-and instructions 3025: 3026: ;; Prevent AND from being made with sp. This doesn't exist in the machine 3027: ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we 3028: ;; can't allocate pseudos into it. 3029: (define_insn "andsi3" 3030: [(set (match_operand:SI 0 "not_sp_operand" "=m,d") 3031: (and:SI (match_operand:SI 1 "general_operand" "%0,0") 3032: (match_operand:SI 2 "general_operand" "dKs,dmKs")))] 3033: "" 3034: "* 3035: { 3036: int logval; 3037: if (GET_CODE (operands[2]) == CONST_INT 3038: && (INTVAL (operands[2]) | 0xffff) == 0xffffffff 3039: && (DATA_REG_P (operands[0]) 3040: || offsettable_memref_p (operands[0]))) 3041: { 3042: if (GET_CODE (operands[0]) != REG) 3043: operands[0] = adj_offsettable_operand (operands[0], 2); 3044: operands[2] = gen_rtx (CONST_INT, VOIDmode, 3045: INTVAL (operands[2]) & 0xffff); 3046: /* Do not delete a following tstl %0 insn; that would be incorrect. */ 3047: CC_STATUS_INIT; 3048: if (operands[2] == const0_rtx) 3049: return \"clr%.w %0\"; 3050: return \"and%.w %2,%0\"; 3051: } 3052: if (GET_CODE (operands[2]) == CONST_INT 3053: && (logval = exact_log2 (~ INTVAL (operands[2]))) >= 0 3054: && (DATA_REG_P (operands[0]) 3055: || offsettable_memref_p (operands[0]))) 3056: { 3057: if (DATA_REG_P (operands[0])) 3058: { 3059: operands[1] = gen_rtx (CONST_INT, VOIDmode, logval); 3060: } 3061: else 3062: { 1.1.1.3 ! root 3063: operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8)); ! 3064: operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8); 1.1 root 3065: } 3066: /* This does not set condition codes in a standard way. */ 3067: CC_STATUS_INIT; 3068: return \"bclr %1,%0\"; 3069: } 3070: return \"and%.l %2,%0\"; 3071: }") 3072: 3073: (define_insn "andhi3" 3074: [(set (match_operand:HI 0 "general_operand" "=m,d") 3075: (and:HI (match_operand:HI 1 "general_operand" "%0,0") 3076: (match_operand:HI 2 "general_operand" "dn,dmn")))] 3077: "" 3078: "and%.w %2,%0") 3079: 3080: (define_insn "" 3081: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 3082: (and:HI (match_dup 0) 3083: (match_operand:HI 1 "general_operand" "dn,dmn")))] 3084: "" 3085: "and%.w %1,%0") 3086: 3087: (define_insn "" 3088: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 3089: (and:HI (match_operand:HI 1 "general_operand" "dn,dmn") 3090: (match_dup 0)))] 3091: "" 3092: "and%.w %1,%0") 3093: 3094: (define_insn "andqi3" 3095: [(set (match_operand:QI 0 "general_operand" "=m,d") 3096: (and:QI (match_operand:QI 1 "general_operand" "%0,0") 3097: (match_operand:QI 2 "general_operand" "dn,dmn")))] 3098: "" 3099: "and%.b %2,%0") 3100: 3101: (define_insn "" 3102: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 3103: (and:QI (match_dup 0) 3104: (match_operand:QI 1 "general_operand" "dn,dmn")))] 3105: "" 3106: "and%.b %1,%0") 3107: 3108: (define_insn "" 3109: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 3110: (and:QI (match_operand:QI 1 "general_operand" "dn,dmn") 3111: (match_dup 0)))] 3112: "" 3113: "and%.b %1,%0") 3114: 3115: ;; inclusive-or instructions 3116: 3117: (define_insn "iorsi3" 3118: [(set (match_operand:SI 0 "general_operand" "=m,d") 3119: (ior:SI (match_operand:SI 1 "general_operand" "%0,0") 3120: (match_operand:SI 2 "general_operand" "dKs,dmKs")))] 3121: "" 3122: "* 3123: { 3124: register int logval; 3125: if (GET_CODE (operands[2]) == CONST_INT 3126: && INTVAL (operands[2]) >> 16 == 0 3127: && (DATA_REG_P (operands[0]) 3128: || offsettable_memref_p (operands[0]))) 3129: { 3130: if (GET_CODE (operands[0]) != REG) 3131: operands[0] = adj_offsettable_operand (operands[0], 2); 3132: /* Do not delete a following tstl %0 insn; that would be incorrect. */ 3133: CC_STATUS_INIT; 3134: return \"or%.w %2,%0\"; 3135: } 3136: if (GET_CODE (operands[2]) == CONST_INT 3137: && (logval = exact_log2 (INTVAL (operands[2]))) >= 0 3138: && (DATA_REG_P (operands[0]) 3139: || offsettable_memref_p (operands[0]))) 3140: { 3141: if (DATA_REG_P (operands[0])) 3142: { 3143: operands[1] = gen_rtx (CONST_INT, VOIDmode, logval); 3144: } 3145: else 3146: { 3147: operands[0] = adj_offsettable_operand (operands[0], 3 - (logval / 8)); 3148: operands[1] = gen_rtx (CONST_INT, VOIDmode, logval % 8); 3149: } 3150: CC_STATUS_INIT; 3151: return \"bset %1,%0\"; 3152: } 3153: return \"or%.l %2,%0\"; 3154: }") 3155: 3156: (define_insn "iorhi3" 3157: [(set (match_operand:HI 0 "general_operand" "=m,d") 3158: (ior:HI (match_operand:HI 1 "general_operand" "%0,0") 3159: (match_operand:HI 2 "general_operand" "dn,dmn")))] 3160: "" 3161: "or%.w %2,%0") 3162: 3163: (define_insn "" 3164: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 3165: (ior:HI (match_dup 0) 3166: (match_operand:HI 1 "general_operand" "dn,dmn")))] 3167: "" 3168: "or%.w %1,%0") 3169: 3170: (define_insn "" 3171: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d")) 3172: (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn") 3173: (match_dup 0)))] 3174: "" 3175: "or%.w %1,%0") 3176: 3177: (define_insn "iorqi3" 3178: [(set (match_operand:QI 0 "general_operand" "=m,d") 3179: (ior:QI (match_operand:QI 1 "general_operand" "%0,0") 3180: (match_operand:QI 2 "general_operand" "dn,dmn")))] 3181: "" 3182: "or%.b %2,%0") 3183: 3184: (define_insn "" 3185: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 3186: (ior:QI (match_dup 0) 3187: (match_operand:QI 1 "general_operand" "dn,dmn")))] 3188: "" 3189: "or%.b %1,%0") 3190: 3191: (define_insn "" 3192: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d")) 3193: (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn") 3194: (match_dup 0)))] 3195: "" 3196: "or%.b %1,%0") 3197: 3198: ;; xor instructions 3199: 3200: (define_insn "xorsi3" 3201: [(set (match_operand:SI 0 "general_operand" "=do,m") 3202: (xor:SI (match_operand:SI 1 "general_operand" "%0,0") 3203: (match_operand:SI 2 "general_operand" "di,dKs")))] 3204: "" 3205: "* 3206: { 3207: if (GET_CODE (operands[2]) == CONST_INT 3208: && INTVAL (operands[2]) >> 16 == 0 3209: && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0]))) 3210: { 3211: if (! DATA_REG_P (operands[0])) 3212: operands[0] = adj_offsettable_operand (operands[0], 2); 3213: /* Do not delete a following tstl %0 insn; that would be incorrect. */ 3214: CC_STATUS_INIT; 3215: return \"eor%.w %2,%0\"; 3216: } 3217: return \"eor%.l %2,%0\"; 3218: }") 3219: 3220: (define_insn "xorhi3" 3221: [(set (match_operand:HI 0 "general_operand" "=dm") 3222: (xor:HI (match_operand:HI 1 "general_operand" "%0") 3223: (match_operand:HI 2 "general_operand" "dn")))] 3224: "" 3225: "eor%.w %2,%0") 3226: 3227: (define_insn "" 3228: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) 3229: (xor:HI (match_dup 0) 3230: (match_operand:HI 1 "general_operand" "dn")))] 3231: "" 3232: "eor%.w %1,%0") 3233: 3234: 3235: (define_insn "" 3236: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) 3237: (xor:HI (match_operand:HI 1 "general_operand" "dn") 3238: (match_dup 0)))] 3239: "" 3240: "eor%.w %1,%0") 3241: 3242: (define_insn "xorqi3" 3243: [(set (match_operand:QI 0 "general_operand" "=dm") 3244: (xor:QI (match_operand:QI 1 "general_operand" "%0") 3245: (match_operand:QI 2 "general_operand" "dn")))] 3246: "" 3247: "eor%.b %2,%0") 3248: 3249: (define_insn "" 3250: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) 3251: (xor:QI (match_dup 0) 3252: (match_operand:QI 1 "general_operand" "dn")))] 3253: "" 3254: "eor%.b %1,%0") 3255: 3256: (define_insn "" 3257: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) 3258: (xor:QI (match_operand:QI 1 "general_operand" "dn") 3259: (match_dup 0)))] 3260: "" 3261: "eor%.b %1,%0") 3262: 3263: ;; negation instructions 3264: 3265: (define_insn "negsi2" 3266: [(set (match_operand:SI 0 "general_operand" "=dm") 3267: (neg:SI (match_operand:SI 1 "general_operand" "0")))] 3268: "" 3269: "neg%.l %0") 3270: 3271: (define_insn "neghi2" 3272: [(set (match_operand:HI 0 "general_operand" "=dm") 3273: (neg:HI (match_operand:HI 1 "general_operand" "0")))] 3274: "" 3275: "neg%.w %0") 3276: 3277: (define_insn "" 3278: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) 3279: (neg:HI (match_dup 0)))] 3280: "" 3281: "neg%.w %0") 3282: 3283: (define_insn "negqi2" 3284: [(set (match_operand:QI 0 "general_operand" "=dm") 3285: (neg:QI (match_operand:QI 1 "general_operand" "0")))] 3286: "" 3287: "neg%.b %0") 3288: 3289: (define_insn "" 3290: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) 3291: (neg:QI (match_dup 0)))] 3292: "" 3293: "neg%.b %0") 3294: 3295: (define_expand "negsf2" 3296: [(set (match_operand:SF 0 "general_operand" "") 3297: (neg:SF (match_operand:SF 1 "general_operand" "")))] 3298: "TARGET_68881 || TARGET_FPA" 3299: "") 3300: 3301: (define_insn "" 3302: [(set (match_operand:SF 0 "general_operand" "=x,y") 3303: (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))] 3304: "TARGET_FPA" 3305: "fpneg%.s %w1,%0") 3306: 3307: (define_insn "" 3308: [(set (match_operand:SF 0 "general_operand" "=f,d") 3309: (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))] 3310: "TARGET_68881" 3311: "* 3312: { 3313: if (DATA_REG_P (operands[0])) 3314: { 3315: operands[1] = gen_rtx (CONST_INT, VOIDmode, 31); 3316: return \"bchg %1,%0\"; 3317: } 3318: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) 3319: return \"f%$neg%.x %1,%0\"; 3320: return \"f%$neg%.s %f1,%0\"; 3321: }") 3322: 3323: (define_expand "negdf2" 3324: [(set (match_operand:DF 0 "general_operand" "") 3325: (neg:DF (match_operand:DF 1 "general_operand" "")))] 3326: "TARGET_68881 || TARGET_FPA" 3327: "") 3328: 3329: (define_insn "" 3330: [(set (match_operand:DF 0 "general_operand" "=x,y") 3331: (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))] 3332: "TARGET_FPA" 3333: "fpneg%.d %y1, %0") 3334: 3335: (define_insn "" 3336: [(set (match_operand:DF 0 "general_operand" "=f,d") 3337: (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))] 3338: "TARGET_68881" 3339: "* 3340: { 3341: if (DATA_REG_P (operands[0])) 3342: { 3343: operands[1] = gen_rtx (CONST_INT, VOIDmode, 31); 3344: return \"bchg %1,%0\"; 3345: } 3346: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) 3347: return \"f%&neg%.x %1,%0\"; 3348: return \"f%&neg%.d %f1,%0\"; 3349: }") 3350: 3351: ;; Sqrt instruction for the 68881 3352: 3353: (define_insn "sqrtdf2" 3354: [(set (match_operand:DF 0 "general_operand" "=f") 3355: (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))] 3356: "TARGET_68881" 3357: "* 3358: { 3359: if (FP_REG_P (operands[1])) 3360: return \"fsqrt%.x %1,%0\"; 3361: else 3362: return \"fsqrt%.d %1,%0\"; 3363: }") 3364: 3365: ;; Absolute value instructions 3366: 3367: (define_expand "abssf2" 3368: [(set (match_operand:SF 0 "general_operand" "") 3369: (abs:SF (match_operand:SF 1 "general_operand" "")))] 3370: "TARGET_68881 || TARGET_FPA" 3371: "") 3372: 3373: (define_insn "" 3374: [(set (match_operand:SF 0 "general_operand" "=x,y") 3375: (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))] 3376: "TARGET_FPA" 3377: "fpabs%.s %y1,%0") 3378: 3379: (define_insn "" 3380: [(set (match_operand:SF 0 "general_operand" "=f") 3381: (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))] 3382: "TARGET_68881" 3383: "* 3384: { 3385: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) 3386: return \"f%$abs%.x %1,%0\"; 3387: return \"f%$abs%.s %f1,%0\"; 3388: }") 3389: 3390: (define_expand "absdf2" 3391: [(set (match_operand:DF 0 "general_operand" "") 3392: (abs:DF (match_operand:DF 1 "general_operand" "")))] 3393: "TARGET_68881 || TARGET_FPA" 3394: "") 3395: 3396: (define_insn "" 3397: [(set (match_operand:DF 0 "general_operand" "=x,y") 3398: (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))] 3399: "TARGET_FPA" 3400: "fpabs%.d %y1,%0") 3401: 3402: (define_insn "" 3403: [(set (match_operand:DF 0 "general_operand" "=f") 3404: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))] 3405: "TARGET_68881" 3406: "* 3407: { 3408: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) 3409: return \"f%&abs%.x %1,%0\"; 3410: return \"f%&abs%.d %f1,%0\"; 3411: }") 3412: 3413: ;; one complement instructions 3414: 3415: (define_insn "one_cmplsi2" 3416: [(set (match_operand:SI 0 "general_operand" "=dm") 3417: (not:SI (match_operand:SI 1 "general_operand" "0")))] 3418: "" 3419: "not%.l %0") 3420: 3421: (define_insn "one_cmplhi2" 3422: [(set (match_operand:HI 0 "general_operand" "=dm") 3423: (not:HI (match_operand:HI 1 "general_operand" "0")))] 3424: "" 3425: "not%.w %0") 3426: 3427: (define_insn "" 3428: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm")) 3429: (not:HI (match_dup 0)))] 3430: "" 3431: "not%.w %0") 3432: 3433: (define_insn "one_cmplqi2" 3434: [(set (match_operand:QI 0 "general_operand" "=dm") 3435: (not:QI (match_operand:QI 1 "general_operand" "0")))] 3436: "" 3437: "not%.b %0") 3438: 3439: (define_insn "" 3440: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm")) 3441: (not:QI (match_dup 0)))] 3442: "" 3443: "not%.b %0") 3444: 3445: ;; arithmetic shift instructions 3446: ;; We don't need the shift memory by 1 bit instruction 3447: 3448: ;; On all 68k models, this makes faster code in a special case. 3449: 3450: (define_insn "" 3451: [(set (match_operand:SI 0 "register_operand" "=d") 3452: (ashift:SI (match_operand:SI 1 "register_operand" "0") 1.1.1.3 ! root 3453: (const_int 16)))] ! 3454: "" 1.1 root 3455: "* 3456: { 3457: CC_STATUS_INIT; 3458: return \"swap %0\;clr%.w %0\"; 3459: }") 3460: 3461: ;; On the 68000, this makes faster code in a special case. 3462: 3463: (define_insn "" 3464: [(set (match_operand:SI 0 "register_operand" "=d") 3465: (ashift:SI (match_operand:SI 1 "register_operand" "0") 1.1.1.3 ! root 3466: (match_operand:SI 2 "const_int_operand" "n")))] ! 3467: "(! TARGET_68020 1.1 root 3468: && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" 3469: "* 3470: { 3471: CC_STATUS_INIT; 3472: 3473: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); 3474: return \"asl%.w %2,%0\;swap %0\;clr%.w %0\"; 3475: }") 3476: 3477: (define_insn "ashlsi3" 3478: [(set (match_operand:SI 0 "register_operand" "=d") 3479: (ashift:SI (match_operand:SI 1 "register_operand" "0") 3480: (match_operand:SI 2 "general_operand" "dI")))] 3481: "" 3482: "* 3483: { 3484: if (operands[2] == const1_rtx) 3485: return \"add%.l %0,%0\"; 3486: return \"asl%.l %2,%0\"; 3487: }") 3488: 3489: (define_insn "ashlhi3" 3490: [(set (match_operand:HI 0 "register_operand" "=d") 3491: (ashift:HI (match_operand:HI 1 "register_operand" "0") 3492: (match_operand:HI 2 "general_operand" "dI")))] 3493: "" 3494: "asl%.w %2,%0") 3495: 3496: (define_insn "" 3497: [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 3498: (ashift:HI (match_dup 0) 3499: (match_operand:HI 1 "general_operand" "dI")))] 3500: "" 3501: "asl%.w %1,%0") 3502: 3503: (define_insn "ashlqi3" 3504: [(set (match_operand:QI 0 "register_operand" "=d") 3505: (ashift:QI (match_operand:QI 1 "register_operand" "0") 3506: (match_operand:QI 2 "general_operand" "dI")))] 3507: "" 3508: "asl%.b %2,%0") 3509: 3510: (define_insn "" 3511: [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 3512: (ashift:QI (match_dup 0) 3513: (match_operand:QI 1 "general_operand" "dI")))] 3514: "" 3515: "asl%.b %1,%0") 3516: 3517: ;; On all 68k models, this makes faster code in a special case. 3518: 3519: (define_insn "" 3520: [(set (match_operand:SI 0 "register_operand" "=d") 3521: (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 1.1.1.3 ! root 3522: (const_int 16)))] ! 3523: "" 1.1 root 3524: "swap %0\;ext%.l %0") 3525: 3526: ;; On the 68000, this makes faster code in a special case. 3527: 3528: (define_insn "" 3529: [(set (match_operand:SI 0 "register_operand" "=d") 3530: (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 1.1.1.3 ! root 3531: (match_operand:SI 2 "const_int_operand" "n")))] ! 3532: "(! TARGET_68020 1.1 root 3533: && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" 3534: "* 3535: { 3536: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); 3537: return \"swap %0\;asr%.w %2,%0\;ext%.l %0\"; 3538: }") 3539: 3540: (define_insn "ashrsi3" 3541: [(set (match_operand:SI 0 "register_operand" "=d") 3542: (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 3543: (match_operand:SI 2 "general_operand" "dI")))] 3544: "" 1.1.1.3 ! root 3545: "asr%.l %2,%0") 1.1 root 3546: 3547: (define_insn "ashrhi3" 3548: [(set (match_operand:HI 0 "register_operand" "=d") 3549: (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") 3550: (match_operand:HI 2 "general_operand" "dI")))] 3551: "" 3552: "asr%.w %2,%0") 3553: 3554: (define_insn "" 3555: [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 3556: (ashiftrt:HI (match_dup 0) 3557: (match_operand:HI 1 "general_operand" "dI")))] 3558: "" 3559: "asr%.w %1,%0") 3560: 3561: (define_insn "ashrqi3" 3562: [(set (match_operand:QI 0 "register_operand" "=d") 3563: (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") 3564: (match_operand:QI 2 "general_operand" "dI")))] 3565: "" 3566: "asr%.b %2,%0") 3567: 3568: (define_insn "" 3569: [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 3570: (ashiftrt:QI (match_dup 0) 3571: (match_operand:QI 1 "general_operand" "dI")))] 3572: "" 3573: "asr%.b %1,%0") 3574: 3575: ;; logical shift instructions 3576: 3577: 3578: ;; On all 68k models, this makes faster code in a special case. 3579: 3580: (define_insn "" 3581: [(set (match_operand:SI 0 "register_operand" "=d") 3582: (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 1.1.1.3 ! root 3583: (const_int 16)))] ! 3584: "" 1.1 root 3585: "* 3586: { 3587: CC_STATUS_INIT; 3588: return \"clr%.w %0\;swap %0\"; 3589: }") 3590: 3591: ;; On the 68000, this makes faster code in a special case. 3592: 3593: (define_insn "" 3594: [(set (match_operand:SI 0 "register_operand" "=d") 3595: (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 1.1.1.3 ! root 3596: (match_operand:SI 2 "const_int_operand" "n")))] ! 3597: "(! TARGET_68020 1.1 root 3598: && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)" 3599: "* 3600: { 3601: /* I think lsr%.w sets the CC properly. */ 3602: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) - 16); 3603: return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\"; 3604: }") 3605: 3606: (define_insn "lshrsi3" 3607: [(set (match_operand:SI 0 "register_operand" "=d") 3608: (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 3609: (match_operand:SI 2 "general_operand" "dI")))] 3610: "" 1.1.1.3 ! root 3611: "lsr%.l %2,%0") 1.1 root 3612: 3613: (define_insn "lshrhi3" 3614: [(set (match_operand:HI 0 "register_operand" "=d") 3615: (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") 3616: (match_operand:HI 2 "general_operand" "dI")))] 3617: "" 3618: "lsr%.w %2,%0") 3619: 3620: (define_insn "" 3621: [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 3622: (lshiftrt:HI (match_dup 0) 3623: (match_operand:HI 1 "general_operand" "dI")))] 3624: "" 3625: "lsr%.w %1,%0") 3626: 3627: (define_insn "lshrqi3" 3628: [(set (match_operand:QI 0 "register_operand" "=d") 3629: (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") 3630: (match_operand:QI 2 "general_operand" "dI")))] 3631: "" 3632: "lsr%.b %2,%0") 3633: 3634: (define_insn "" 3635: [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 3636: (lshiftrt:QI (match_dup 0) 3637: (match_operand:QI 1 "general_operand" "dI")))] 3638: "" 3639: "lsr%.b %1,%0") 3640: 3641: ;; rotate instructions 3642: 3643: (define_insn "rotlsi3" 3644: [(set (match_operand:SI 0 "register_operand" "=d") 3645: (rotate:SI (match_operand:SI 1 "register_operand" "0") 3646: (match_operand:SI 2 "general_operand" "dI")))] 3647: "" 3648: "rol%.l %2,%0") 3649: 3650: (define_insn "rotlhi3" 3651: [(set (match_operand:HI 0 "register_operand" "=d") 3652: (rotate:HI (match_operand:HI 1 "register_operand" "0") 3653: (match_operand:HI 2 "general_operand" "dI")))] 3654: "" 3655: "rol%.w %2,%0") 3656: 3657: 3658: (define_insn "" 3659: [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 3660: (rotate:HI (match_dup 0) 3661: (match_operand:HI 1 "general_operand" "dI")))] 3662: "" 3663: "rol%.w %1,%0") 3664: 3665: (define_insn "rotlqi3" 3666: [(set (match_operand:QI 0 "register_operand" "=d") 3667: (rotate:QI (match_operand:QI 1 "register_operand" "0") 3668: (match_operand:QI 2 "general_operand" "dI")))] 3669: "" 3670: "rol%.b %2,%0") 3671: 3672: (define_insn "" 3673: [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 3674: (rotate:QI (match_dup 0) 3675: (match_operand:QI 1 "general_operand" "dI")))] 3676: "" 3677: "rol%.b %1,%0") 3678: 3679: (define_insn "rotrsi3" 3680: [(set (match_operand:SI 0 "register_operand" "=d") 3681: (rotatert:SI (match_operand:SI 1 "register_operand" "0") 3682: (match_operand:SI 2 "general_operand" "dI")))] 3683: "" 3684: "ror%.l %2,%0") 3685: 3686: (define_insn "rotrhi3" 3687: [(set (match_operand:HI 0 "register_operand" "=d") 3688: (rotatert:HI (match_operand:HI 1 "register_operand" "0") 3689: (match_operand:HI 2 "general_operand" "dI")))] 3690: "" 3691: "ror%.w %2,%0") 3692: 3693: (define_insn "" 3694: [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 3695: (rotatert:HI (match_dup 0) 3696: (match_operand:HI 1 "general_operand" "dI")))] 3697: "" 3698: "ror%.w %1,%0") 3699: 3700: (define_insn "rotrqi3" 3701: [(set (match_operand:QI 0 "register_operand" "=d") 3702: (rotatert:QI (match_operand:QI 1 "register_operand" "0") 3703: (match_operand:QI 2 "general_operand" "dI")))] 3704: "" 3705: "ror%.b %2,%0") 3706: 3707: (define_insn "" 3708: [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 3709: (rotatert:QI (match_dup 0) 3710: (match_operand:QI 1 "general_operand" "dI")))] 3711: "" 3712: "ror%.b %1,%0") 3713: 3714: ;; Special cases of bit-field insns which we should 3715: ;; recognize in preference to the general case. 3716: ;; These handle aligned 8-bit and 16-bit fields, 3717: ;; which can usually be done with move instructions. 3718: 3719: ; 3720: ; Special case for 32-bit field in memory. This only occurs when 32-bit 3721: ; alignment of structure members is specified. 3722: ; 3723: ; The move is allowed to be odd byte aligned, because that's still faster 3724: ; than an odd byte aligned bit field instruction. 3725: ; 3726: (define_insn "" 3727: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o") 1.1.1.3 ! root 3728: (const_int 32) ! 3729: (match_operand:SI 2 "const_int_operand" "n")) 1.1 root 3730: (match_operand:SI 3 "general_operand" "rmi"))] 3731: "TARGET_68020 && TARGET_BITFIELD 3732: && (INTVAL (operands[2]) % 8) == 0 3733: && ! mode_dependent_address_p (XEXP (operands[0], 0))" 3734: "* 3735: { 3736: operands[0] 3737: = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); 3738: 3739: return \"move%.l %3,%0\"; 3740: }") 3741: 3742: (define_insn "" 3743: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+do") 1.1.1.3 ! root 3744: (match_operand:SI 1 "const_int_operand" "n") ! 3745: (match_operand:SI 2 "const_int_operand" "n")) ! 3746: (match_operand:SI 3 "register_operand" "d"))] 1.1 root 3747: "TARGET_68020 && TARGET_BITFIELD 3748: && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) 3749: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 3750: && (GET_CODE (operands[0]) == REG 3751: || ! mode_dependent_address_p (XEXP (operands[0], 0)))" 3752: "* 3753: { 3754: if (REG_P (operands[0])) 3755: { 3756: if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32) 3757: return \"bfins %3,%0{%b2:%b1}\"; 3758: } 3759: else 3760: operands[0] 3761: = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8); 3762: 3763: if (GET_CODE (operands[3]) == MEM) 3764: operands[3] = adj_offsettable_operand (operands[3], 3765: (32 - INTVAL (operands[1])) / 8); 3766: if (INTVAL (operands[1]) == 8) 3767: return \"move%.b %3,%0\"; 3768: return \"move%.w %3,%0\"; 3769: }") 3770: 3771: 3772: ; 3773: ; Special case for 32-bit field in memory. This only occurs when 32-bit 3774: ; alignment of structure members is specified. 3775: ; 3776: ; The move is allowed to be odd byte aligned, because that's still faster 3777: ; than an odd byte aligned bit field instruction. 3778: ; 3779: (define_insn "" 3780: [(set (match_operand:SI 0 "general_operand" "=rm") 3781: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o") 1.1.1.3 ! root 3782: (const_int 32) ! 3783: (match_operand:SI 3 "const_int_operand" "n")))] 1.1 root 3784: "TARGET_68020 && TARGET_BITFIELD 3785: && (INTVAL (operands[3]) % 8) == 0 3786: && ! mode_dependent_address_p (XEXP (operands[1], 0))" 3787: "* 3788: { 3789: operands[1] 3790: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); 3791: 3792: return \"move%.l %1,%0\"; 3793: }") 3794: 3795: (define_insn "" 3796: [(set (match_operand:SI 0 "general_operand" "=&d") 3797: (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do") 1.1.1.3 ! root 3798: (match_operand:SI 2 "const_int_operand" "n") ! 3799: (match_operand:SI 3 "const_int_operand" "n")))] 1.1 root 3800: "TARGET_68020 && TARGET_BITFIELD 3801: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 3802: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 3803: && (GET_CODE (operands[1]) == REG 3804: || ! mode_dependent_address_p (XEXP (operands[1], 0)))" 3805: "* 3806: { 3807: cc_status.flags |= CC_NOT_NEGATIVE; 3808: if (REG_P (operands[1])) 3809: { 3810: if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) 3811: return \"bfextu %1{%b3:%b2},%0\"; 3812: } 3813: else 3814: operands[1] 3815: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); 3816: 3817: output_asm_insn (\"clr%.l %0\", operands); 3818: if (GET_CODE (operands[0]) == MEM) 3819: operands[0] = adj_offsettable_operand (operands[0], 3820: (32 - INTVAL (operands[1])) / 8); 3821: if (INTVAL (operands[2]) == 8) 3822: return \"move%.b %1,%0\"; 3823: return \"move%.w %1,%0\"; 3824: }") 3825: 3826: ; 3827: ; Special case for 32-bit field in memory. This only occurs when 32-bit 3828: ; alignment of structure members is specified. 3829: ; 3830: ; The move is allowed to be odd byte aligned, because that's still faster 3831: ; than an odd byte aligned bit field instruction. 3832: ; 3833: (define_insn "" 3834: [(set (match_operand:SI 0 "general_operand" "=rm") 3835: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o") 1.1.1.3 ! root 3836: (const_int 32) ! 3837: (match_operand:SI 3 "const_int_operand" "n")))] 1.1 root 3838: "TARGET_68020 && TARGET_BITFIELD 3839: && (INTVAL (operands[3]) % 8) == 0 3840: && ! mode_dependent_address_p (XEXP (operands[1], 0))" 3841: "* 3842: { 3843: operands[1] 3844: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); 3845: 3846: return \"move%.l %1,%0\"; 3847: }") 3848: 3849: (define_insn "" 3850: [(set (match_operand:SI 0 "general_operand" "=d") 3851: (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "do") 1.1.1.3 ! root 3852: (match_operand:SI 2 "const_int_operand" "n") ! 3853: (match_operand:SI 3 "const_int_operand" "n")))] 1.1 root 3854: "TARGET_68020 && TARGET_BITFIELD 3855: && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 3856: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 3857: && (GET_CODE (operands[1]) == REG 3858: || ! mode_dependent_address_p (XEXP (operands[1], 0)))" 3859: "* 3860: { 3861: if (REG_P (operands[1])) 3862: { 3863: if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) 3864: return \"bfexts %1{%b3:%b2},%0\"; 3865: } 3866: else 3867: operands[1] 3868: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8); 3869: 3870: if (INTVAL (operands[2]) == 8) 3871: return \"move%.b %1,%0\;extb%.l %0\"; 3872: return \"move%.w %1,%0\;ext%.l %0\"; 3873: }") 3874: 3875: ;; Bit field instructions, general cases. 3876: ;; "o,d" constraint causes a nonoffsettable memref to match the "o" 3877: ;; so that its address is reloaded. 3878: 3879: (define_insn "extv" 3880: [(set (match_operand:SI 0 "general_operand" "=d,d") 3881: (sign_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d") 3882: (match_operand:SI 2 "general_operand" "di,di") 3883: (match_operand:SI 3 "general_operand" "di,di")))] 3884: "TARGET_68020 && TARGET_BITFIELD" 3885: "bfexts %1{%b3:%b2},%0") 3886: 3887: (define_insn "extzv" 3888: [(set (match_operand:SI 0 "general_operand" "=d,d") 3889: (zero_extract:SI (match_operand:QI 1 "nonimmediate_operand" "o,d") 3890: (match_operand:SI 2 "general_operand" "di,di") 3891: (match_operand:SI 3 "general_operand" "di,di")))] 3892: "TARGET_68020 && TARGET_BITFIELD" 3893: "* 3894: { 1.1.1.2 root 3895: if (GET_CODE (operands[2]) == CONST_INT) 3896: { 3897: if (INTVAL (operands[2]) != 32) 3898: cc_status.flags |= CC_NOT_NEGATIVE; 3899: } 3900: else 3901: { 3902: CC_STATUS_INIT; 3903: } 1.1 root 3904: return \"bfextu %1{%b3:%b2},%0\"; 3905: }") 3906: 3907: (define_insn "" 3908: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") 3909: (match_operand:SI 1 "general_operand" "di,di") 3910: (match_operand:SI 2 "general_operand" "di,di")) 3911: (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2)) 1.1.1.3 ! root 3912: (match_operand 3 "const_int_operand" "n,n")))] 1.1 root 3913: "TARGET_68020 && TARGET_BITFIELD 3914: && (INTVAL (operands[3]) == -1 3915: || (GET_CODE (operands[1]) == CONST_INT 3916: && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))" 3917: "* 3918: { 3919: CC_STATUS_INIT; 3920: return \"bfchg %0{%b2:%b1}\"; 3921: }") 3922: 3923: (define_insn "" 3924: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") 3925: (match_operand:SI 1 "general_operand" "di,di") 3926: (match_operand:SI 2 "general_operand" "di,di")) 3927: (const_int 0))] 3928: "TARGET_68020 && TARGET_BITFIELD" 3929: "* 3930: { 3931: CC_STATUS_INIT; 3932: return \"bfclr %0{%b2:%b1}\"; 3933: }") 3934: 3935: (define_insn "" 3936: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") 3937: (match_operand:SI 1 "general_operand" "di,di") 3938: (match_operand:SI 2 "general_operand" "di,di")) 3939: (const_int -1))] 3940: "TARGET_68020 && TARGET_BITFIELD" 3941: "* 3942: { 3943: CC_STATUS_INIT; 3944: return \"bfset %0{%b2:%b1}\"; 3945: }") 3946: 3947: (define_insn "insv" 3948: [(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+o,d") 3949: (match_operand:SI 1 "general_operand" "di,di") 3950: (match_operand:SI 2 "general_operand" "di,di")) 1.1.1.3 ! root 3951: (match_operand:SI 3 "register_operand" "d,d"))] 1.1 root 3952: "TARGET_68020 && TARGET_BITFIELD" 3953: "bfins %3,%0{%b2:%b1}") 3954: 3955: ;; Now recognize bit field insns that operate on registers 3956: ;; (or at least were intended to do so). 3957: 3958: (define_insn "" 3959: [(set (match_operand:SI 0 "general_operand" "=d") 3960: (sign_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d") 3961: (match_operand:SI 2 "general_operand" "di") 3962: (match_operand:SI 3 "general_operand" "di")))] 3963: "TARGET_68020 && TARGET_BITFIELD" 3964: "bfexts %1{%b3:%b2},%0") 3965: 3966: (define_insn "" 3967: [(set (match_operand:SI 0 "general_operand" "=d") 3968: (zero_extract:SI (match_operand:SI 1 "nonimmediate_operand" "d") 3969: (match_operand:SI 2 "general_operand" "di") 3970: (match_operand:SI 3 "general_operand" "di")))] 3971: "TARGET_68020 && TARGET_BITFIELD" 3972: "* 3973: { 1.1.1.2 root 3974: if (GET_CODE (operands[2]) == CONST_INT) 3975: { 3976: if (INTVAL (operands[2]) != 32) 3977: cc_status.flags |= CC_NOT_NEGATIVE; 3978: } 3979: else 3980: { 3981: CC_STATUS_INIT; 3982: } 1.1 root 3983: return \"bfextu %1{%b3:%b2},%0\"; 3984: }") 3985: 3986: (define_insn "" 3987: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") 3988: (match_operand:SI 1 "general_operand" "di") 3989: (match_operand:SI 2 "general_operand" "di")) 3990: (const_int 0))] 3991: "TARGET_68020 && TARGET_BITFIELD" 3992: "* 3993: { 3994: CC_STATUS_INIT; 3995: return \"bfclr %0{%b2:%b1}\"; 3996: }") 3997: 3998: (define_insn "" 3999: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") 4000: (match_operand:SI 1 "general_operand" "di") 4001: (match_operand:SI 2 "general_operand" "di")) 4002: (const_int -1))] 4003: "TARGET_68020 && TARGET_BITFIELD" 4004: "* 4005: { 4006: CC_STATUS_INIT; 4007: return \"bfset %0{%b2:%b1}\"; 4008: }") 4009: 4010: (define_insn "" 4011: [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+d") 4012: (match_operand:SI 1 "general_operand" "di") 4013: (match_operand:SI 2 "general_operand" "di")) 1.1.1.3 ! root 4014: (match_operand:SI 3 "register_operand" "d"))] 1.1 root 4015: "TARGET_68020 && TARGET_BITFIELD" 4016: "* 4017: { 4018: #if 0 4019: /* These special cases are now recognized by a specific pattern. */ 4020: if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT 4021: && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16) 4022: return \"move%.w %3,%0\"; 4023: if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT 4024: && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8) 4025: return \"move%.b %3,%0\"; 4026: #endif 4027: return \"bfins %3,%0{%b2:%b1}\"; 4028: }") 4029: 4030: ;; Special patterns for optimizing bit-field instructions. 4031: 4032: (define_insn "" 4033: [(set (cc0) 4034: (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") 1.1.1.3 ! root 4035: (match_operand:SI 1 "const_int_operand" "n") 1.1 root 4036: (match_operand:SI 2 "general_operand" "di")))] 1.1.1.3 ! root 4037: "TARGET_68020 && TARGET_BITFIELD" 1.1 root 4038: "* 4039: { 4040: if (operands[1] == const1_rtx 4041: && GET_CODE (operands[2]) == CONST_INT) 4042: { 4043: int width = GET_CODE (operands[0]) == REG ? 31 : 7; 4044: return output_btst (operands, 4045: gen_rtx (CONST_INT, VOIDmode, 4046: width - INTVAL (operands[2])), 4047: operands[0], 4048: insn, 1000); 4049: /* Pass 1000 as SIGNPOS argument so that btst will 4050: not think we are testing the sign bit for an `and' 4051: and assume that nonzero implies a negative result. */ 4052: } 4053: if (INTVAL (operands[1]) != 32) 4054: cc_status.flags = CC_NOT_NEGATIVE; 4055: return \"bftst %0{%b2:%b1}\"; 4056: }") 4057: 4058: 4059: ;;; now handle the register cases 4060: (define_insn "" 4061: [(set (cc0) 4062: (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "d") 1.1.1.3 ! root 4063: (match_operand:SI 1 "const_int_operand" "n") 1.1 root 4064: (match_operand:SI 2 "general_operand" "di")))] 1.1.1.3 ! root 4065: "TARGET_68020 && TARGET_BITFIELD" 1.1 root 4066: "* 4067: { 4068: if (operands[1] == const1_rtx 4069: && GET_CODE (operands[2]) == CONST_INT) 4070: { 4071: int width = GET_CODE (operands[0]) == REG ? 31 : 7; 4072: return output_btst (operands, 4073: gen_rtx (CONST_INT, VOIDmode, 4074: width - INTVAL (operands[2])), 4075: operands[0], 4076: insn, 1000); 4077: /* Pass 1000 as SIGNPOS argument so that btst will 4078: not think we are testing the sign bit for an `and' 4079: and assume that nonzero implies a negative result. */ 4080: } 4081: if (INTVAL (operands[1]) != 32) 4082: cc_status.flags = CC_NOT_NEGATIVE; 4083: return \"bftst %0{%b2:%b1}\"; 4084: }") 4085: 4086: (define_insn "seq" 4087: [(set (match_operand:QI 0 "general_operand" "=d") 4088: (eq:QI (cc0) (const_int 0)))] 4089: "" 4090: "* 4091: cc_status = cc_prev_status; 4092: OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\"); 4093: ") 4094: 4095: (define_insn "sne" 4096: [(set (match_operand:QI 0 "general_operand" "=d") 4097: (ne:QI (cc0) (const_int 0)))] 4098: "" 4099: "* 4100: cc_status = cc_prev_status; 4101: OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\"); 4102: ") 4103: 4104: (define_insn "sgt" 4105: [(set (match_operand:QI 0 "general_operand" "=d") 4106: (gt:QI (cc0) (const_int 0)))] 4107: "" 4108: "* 4109: cc_status = cc_prev_status; 4110: OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0); 4111: ") 4112: 4113: (define_insn "sgtu" 4114: [(set (match_operand:QI 0 "general_operand" "=d") 4115: (gtu:QI (cc0) (const_int 0)))] 4116: "" 4117: "* cc_status = cc_prev_status; 4118: return \"shi %0\"; ") 4119: 4120: (define_insn "slt" 4121: [(set (match_operand:QI 0 "general_operand" "=d") 4122: (lt:QI (cc0) (const_int 0)))] 4123: "" 4124: "* cc_status = cc_prev_status; 4125: OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ") 4126: 4127: (define_insn "sltu" 4128: [(set (match_operand:QI 0 "general_operand" "=d") 4129: (ltu:QI (cc0) (const_int 0)))] 4130: "" 4131: "* cc_status = cc_prev_status; 4132: return \"scs %0\"; ") 4133: 4134: (define_insn "sge" 4135: [(set (match_operand:QI 0 "general_operand" "=d") 4136: (ge:QI (cc0) (const_int 0)))] 4137: "" 4138: "* cc_status = cc_prev_status; 4139: OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ") 4140: 4141: (define_insn "sgeu" 4142: [(set (match_operand:QI 0 "general_operand" "=d") 4143: (geu:QI (cc0) (const_int 0)))] 4144: "" 4145: "* cc_status = cc_prev_status; 4146: return \"scc %0\"; ") 4147: 4148: (define_insn "sle" 4149: [(set (match_operand:QI 0 "general_operand" "=d") 4150: (le:QI (cc0) (const_int 0)))] 4151: "" 4152: "* 4153: cc_status = cc_prev_status; 4154: OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0); 4155: ") 4156: 4157: (define_insn "sleu" 4158: [(set (match_operand:QI 0 "general_operand" "=d") 4159: (leu:QI (cc0) (const_int 0)))] 4160: "" 4161: "* cc_status = cc_prev_status; 4162: return \"sls %0\"; ") 4163: 4164: ;; Basic conditional jump instructions. 4165: 4166: (define_insn "beq" 4167: [(set (pc) 4168: (if_then_else (eq (cc0) 4169: (const_int 0)) 4170: (label_ref (match_operand 0 "" "")) 4171: (pc)))] 4172: "" 4173: "* 4174: { 4175: #ifdef MOTOROLA 4176: OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\"); 4177: #else 4178: OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\"); 4179: #endif 4180: }") 4181: 4182: (define_insn "bne" 4183: [(set (pc) 4184: (if_then_else (ne (cc0) 4185: (const_int 0)) 4186: (label_ref (match_operand 0 "" "")) 4187: (pc)))] 4188: "" 4189: "* 4190: { 4191: #ifdef MOTOROLA 4192: OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\"); 4193: #else 4194: OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\"); 4195: #endif 4196: }") 4197: 4198: (define_insn "bgt" 4199: [(set (pc) 4200: (if_then_else (gt (cc0) 4201: (const_int 0)) 4202: (label_ref (match_operand 0 "" "")) 4203: (pc)))] 4204: "" 4205: "* 4206: #ifdef MOTOROLA 4207: OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0); 4208: #else 4209: OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0); 4210: #endif 4211: ") 4212: 4213: (define_insn "bgtu" 4214: [(set (pc) 4215: (if_then_else (gtu (cc0) 4216: (const_int 0)) 4217: (label_ref (match_operand 0 "" "")) 4218: (pc)))] 4219: "" 4220: "* 4221: #ifdef MOTOROLA 4222: return \"jbhi %l0\"; 4223: #else 4224: return \"jhi %l0\"; 4225: #endif 4226: ") 4227: 4228: (define_insn "blt" 4229: [(set (pc) 4230: (if_then_else (lt (cc0) 4231: (const_int 0)) 4232: (label_ref (match_operand 0 "" "")) 4233: (pc)))] 4234: "" 4235: "* 4236: #ifdef MOTOROLA 4237: OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\"); 4238: #else 4239: OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\"); 4240: #endif 4241: ") 4242: 4243: (define_insn "bltu" 4244: [(set (pc) 4245: (if_then_else (ltu (cc0) 4246: (const_int 0)) 4247: (label_ref (match_operand 0 "" "")) 4248: (pc)))] 4249: "" 4250: "* 4251: #ifdef MOTOROLA 4252: return \"jbcs %l0\"; 4253: #else 4254: return \"jcs %l0\"; 4255: #endif 4256: ") 4257: 4258: (define_insn "bge" 4259: [(set (pc) 4260: (if_then_else (ge (cc0) 4261: (const_int 0)) 4262: (label_ref (match_operand 0 "" "")) 4263: (pc)))] 4264: "" 4265: "* 4266: #ifdef MOTOROLA 4267: OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\"); 4268: #else 4269: OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\"); 4270: #endif 4271: ") 4272: 4273: (define_insn "bgeu" 4274: [(set (pc) 4275: (if_then_else (geu (cc0) 4276: (const_int 0)) 4277: (label_ref (match_operand 0 "" "")) 4278: (pc)))] 4279: "" 4280: "* 4281: #ifdef MOTOROLA 4282: return \"jbcc %l0\"; 4283: #else 4284: return \"jcc %l0\"; 4285: #endif 4286: ") 4287: 4288: (define_insn "ble" 4289: [(set (pc) 4290: (if_then_else (le (cc0) 4291: (const_int 0)) 4292: (label_ref (match_operand 0 "" "")) 4293: (pc)))] 4294: "" 4295: "* 4296: #ifdef MOTOROLA 4297: OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0); 4298: #else 4299: OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0); 4300: #endif 4301: ") 4302: 4303: (define_insn "bleu" 4304: [(set (pc) 4305: (if_then_else (leu (cc0) 4306: (const_int 0)) 4307: (label_ref (match_operand 0 "" "")) 4308: (pc)))] 4309: "" 4310: "* 4311: #ifdef MOTOROLA 4312: return \"jbls %l0\"; 4313: #else 4314: return \"jls %l0\"; 4315: #endif 4316: ") 4317: 4318: ;; Negated conditional jump instructions. 4319: 4320: (define_insn "" 4321: [(set (pc) 4322: (if_then_else (eq (cc0) 4323: (const_int 0)) 4324: (pc) 4325: (label_ref (match_operand 0 "" ""))))] 4326: "" 4327: "* 4328: { 4329: #ifdef MOTOROLA 4330: OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\"); 4331: #else 4332: OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\"); 4333: #endif 4334: }") 4335: 4336: (define_insn "" 4337: [(set (pc) 4338: (if_then_else (ne (cc0) 4339: (const_int 0)) 4340: (pc) 4341: (label_ref (match_operand 0 "" ""))))] 4342: "" 4343: "* 4344: { 4345: #ifdef MOTOROLA 4346: OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\"); 4347: #else 4348: OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\"); 4349: #endif 4350: }") 4351: 4352: (define_insn "" 4353: [(set (pc) 4354: (if_then_else (gt (cc0) 4355: (const_int 0)) 4356: (pc) 4357: (label_ref (match_operand 0 "" ""))))] 4358: "" 4359: "* 4360: #ifdef MOTOROLA 4361: OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0); 4362: #else 4363: OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0); 4364: #endif 4365: ") 4366: 4367: (define_insn "" 4368: [(set (pc) 4369: (if_then_else (gtu (cc0) 4370: (const_int 0)) 4371: (pc) 4372: (label_ref (match_operand 0 "" ""))))] 4373: "" 4374: "* 4375: #ifdef MOTOROLA 4376: return \"jbls %l0\"; 4377: #else 4378: return \"jls %l0\"; 4379: #endif 4380: ") 4381: 4382: (define_insn "" 4383: [(set (pc) 4384: (if_then_else (lt (cc0) 4385: (const_int 0)) 4386: (pc) 4387: (label_ref (match_operand 0 "" ""))))] 4388: "" 4389: "* 4390: #ifdef MOTOROLA 4391: OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\"); 4392: #else 4393: OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\"); 4394: #endif 4395: ") 4396: 4397: (define_insn "" 4398: [(set (pc) 4399: (if_then_else (ltu (cc0) 4400: (const_int 0)) 4401: (pc) 4402: (label_ref (match_operand 0 "" ""))))] 4403: "" 4404: "* 4405: #ifdef MOTOROLA 4406: return \"jbcc %l0\"; 4407: #else 4408: return \"jcc %l0\"; 4409: #endif 4410: ") 4411: 4412: (define_insn "" 4413: [(set (pc) 4414: (if_then_else (ge (cc0) 4415: (const_int 0)) 4416: (pc) 4417: (label_ref (match_operand 0 "" ""))))] 4418: "" 4419: "* 4420: #ifdef MOTOROLA 4421: OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\"); 4422: #else 4423: OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\"); 4424: #endif 4425: ") 4426: 4427: (define_insn "" 4428: [(set (pc) 4429: (if_then_else (geu (cc0) 4430: (const_int 0)) 4431: (pc) 4432: (label_ref (match_operand 0 "" ""))))] 4433: "" 4434: "* 4435: #ifdef MOTOROLA 4436: return \"jbcs %l0\"; 4437: #else 4438: return \"jcs %l0\"; 4439: #endif 4440: ") 4441: 4442: (define_insn "" 4443: [(set (pc) 4444: (if_then_else (le (cc0) 4445: (const_int 0)) 4446: (pc) 4447: (label_ref (match_operand 0 "" ""))))] 4448: "" 4449: "* 4450: #ifdef MOTOROLA 4451: OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0); 4452: #else 4453: OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0); 4454: #endif 4455: ") 4456: 4457: (define_insn "" 4458: [(set (pc) 4459: (if_then_else (leu (cc0) 4460: (const_int 0)) 4461: (pc) 4462: (label_ref (match_operand 0 "" ""))))] 4463: "" 4464: "* 4465: #ifdef MOTOROLA 4466: return \"jbhi %l0\"; 4467: #else 4468: return \"jhi %l0\"; 4469: #endif 4470: ") 4471: 4472: ;; Unconditional and other jump instructions 4473: (define_insn "jump" 4474: [(set (pc) 4475: (label_ref (match_operand 0 "" "")))] 4476: "" 4477: "* 4478: #ifdef MOTOROLA 4479: return \"jbra %l0\"; 4480: #else 4481: return \"jra %l0\"; 4482: #endif 4483: ") 4484: 4485: ;; We support two different ways of handling dispatch tables. 4486: ;; The NeXT uses absolute tables, and other machines use relative. 4487: ;; This define_expand can generate either kind. 4488: (define_expand "tablejump" 4489: [(parallel [(set (pc) (match_operand 0 "" "")) 4490: (use (label_ref (match_operand 1 "" "")))])] 4491: "" 4492: " 4493: { 4494: #ifdef CASE_VECTOR_PC_RELATIVE 1.1.1.3 ! root 4495: operands[0] = gen_rtx (PLUS, SImode, pc_rtx, ! 4496: gen_rtx (SIGN_EXTEND, SImode, operands[0])); 1.1 root 4497: #endif 4498: }") 4499: 4500: ;; Jump to variable address from dispatch table of absolute addresses. 4501: (define_insn "" 4502: [(set (pc) (match_operand:SI 0 "register_operand" "a")) 4503: (use (label_ref (match_operand 1 "" "")))] 4504: "" 4505: "* 4506: #ifdef MOTOROLA 4507: return \"jmp (%0)\"; 4508: #else 4509: return \"jmp %0@\"; 4510: #endif 4511: ") 4512: 4513: ;; Jump to variable address from dispatch table of relative addresses. 4514: (define_insn "" 4515: [(set (pc) 1.1.1.3 ! root 4516: (plus:SI (pc) ! 4517: (sign_extend:SI (match_operand:HI 0 "register_operand" "r")))) 1.1 root 4518: (use (label_ref (match_operand 1 "" "")))] 4519: "" 4520: "* 4521: #ifdef ASM_RETURN_CASE_JUMP 4522: ASM_RETURN_CASE_JUMP; 4523: #else 4524: #ifdef SGS 4525: #ifdef ASM_OUTPUT_CASE_LABEL 4526: return \"jmp 6(%%pc,%0.w)\"; 4527: #else 4528: #ifdef CRDS 4529: return \"jmp 2(pc,%0.w)\"; 4530: #else 4531: return \"jmp 2(%%pc,%0.w)\"; 4532: #endif /* end !CRDS */ 4533: #endif 4534: #else /* not SGS */ 4535: #ifdef MOTOROLA 4536: return \"jmp (2,pc,%0.w)\"; 4537: #else 4538: return \"jmp pc@(2,%0:w)\"; 4539: #endif 4540: #endif 4541: #endif 4542: ") 4543: 4544: ;; Decrement-and-branch insns. 4545: (define_insn "" 4546: [(set (pc) 4547: (if_then_else 4548: (ne (match_operand:HI 0 "general_operand" "+g") 4549: (const_int 0)) 4550: (label_ref (match_operand 1 "" "")) 4551: (pc))) 4552: (set (match_dup 0) 4553: (plus:HI (match_dup 0) 4554: (const_int -1)))] 4555: "" 4556: "* 4557: { 4558: CC_STATUS_INIT; 4559: if (DATA_REG_P (operands[0])) 4560: return \"dbra %0,%l1\"; 4561: if (GET_CODE (operands[0]) == MEM) 4562: { 4563: #ifdef MOTOROLA 4564: #ifdef NO_ADDSUB_Q 4565: return \"sub%.w %#1,%0\;jbcc %l1\"; 4566: #else 4567: return \"subq%.w %#1,%0\;jbcc %l1\"; 4568: #endif 4569: #else /* not MOTOROLA */ 4570: return \"subqw %#1,%0\;jcc %l1\"; 4571: #endif 4572: } 4573: #ifdef MOTOROLA 4574: #ifdef SGS_CMP_ORDER 4575: #ifdef NO_ADDSUB_Q 4576: return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\"; 4577: #else 4578: return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\"; 4579: #endif 4580: #else /* not SGS_CMP_ORDER */ 4581: return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\"; 4582: #endif 4583: #else /* not MOTOROLA */ 4584: return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\"; 4585: #endif 4586: }") 4587: 4588: (define_insn "" 4589: [(set (pc) 4590: (if_then_else 4591: (ne (match_operand:SI 0 "general_operand" "+g") 4592: (const_int 0)) 4593: (label_ref (match_operand 1 "" "")) 4594: (pc))) 4595: (set (match_dup 0) 4596: (plus:SI (match_dup 0) 4597: (const_int -1)))] 4598: "" 4599: "* 4600: { 4601: CC_STATUS_INIT; 4602: #ifdef MOTOROLA 4603: #ifdef NO_ADDSUB_Q 4604: if (DATA_REG_P (operands[0])) 4605: return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\"; 4606: if (GET_CODE (operands[0]) == MEM) 4607: return \"sub%.l %#1,%0\;jbcc %l1\"; 4608: #else 4609: if (DATA_REG_P (operands[0])) 4610: return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\"; 4611: if (GET_CODE (operands[0]) == MEM) 4612: return \"subq%.l %#1,%0\;jbcc %l1\"; 4613: #endif /* NO_ADDSUB_Q */ 4614: #ifdef SGS_CMP_ORDER 4615: #ifdef NO_ADDSUB_Q 4616: return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; 4617: #else 4618: return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; 4619: #endif 4620: #else /* not SGS_CMP_ORDER */ 4621: return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\"; 4622: #endif /* not SGS_CMP_ORDER */ 4623: #else /* not MOTOROLA */ 4624: if (DATA_REG_P (operands[0])) 4625: return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\"; 4626: if (GET_CODE (operands[0]) == MEM) 4627: return \"subql %#1,%0\;jcc %l1\"; 4628: return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\"; 4629: #endif /* not MOTOROLA */ 4630: }") 4631: 4632: ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce. 4633: 4634: (define_insn "" 4635: [(set (pc) 4636: (if_then_else 4637: (ge (plus:HI (match_operand:HI 0 "general_operand" "+g") 4638: (const_int -1)) 4639: (const_int 0)) 4640: (label_ref (match_operand 1 "" "")) 4641: (pc))) 4642: (set (match_dup 0) 4643: (plus:HI (match_dup 0) 4644: (const_int -1)))] 4645: "find_reg_note (insn, REG_NONNEG, 0)" 4646: "* 4647: { 4648: CC_STATUS_INIT; 4649: #ifdef MOTOROLA 4650: #ifdef NO_ADDSUB_Q 4651: if (DATA_REG_P (operands[0])) 4652: return \"dbra %0,%l1\"; 4653: if (GET_CODE (operands[0]) == MEM) 4654: return \"sub%.w %#1,%0\;jbcc %l1\"; 4655: #else 4656: if (DATA_REG_P (operands[0])) 4657: return \"dbra %0,%l1\"; 4658: if (GET_CODE (operands[0]) == MEM) 4659: return \"subq%.w %#1,%0\;jbcc %l1\"; 4660: #endif 4661: #ifdef SGS_CMP_ORDER 4662: #ifdef NO_ADDSUB_Q 4663: return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\"; 4664: #else 4665: return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\"; 4666: #endif 4667: #else /* not SGS_CMP_ORDER */ 4668: return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\"; 4669: #endif /* not SGS_CMP_ORDER */ 4670: #else /* not MOTOROLA */ 4671: if (DATA_REG_P (operands[0])) 4672: return \"dbra %0,%l1\"; 4673: if (GET_CODE (operands[0]) == MEM) 4674: return \"subqw %#1,%0\;jcc %l1\"; 4675: return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\"; 4676: #endif /* not MOTOROLA */ 4677: }") 4678: 4679: (define_insn "decrement_and_branch_until_zero" 4680: [(set (pc) 4681: (if_then_else 4682: (ge (plus:SI (match_operand:SI 0 "general_operand" "+g") 4683: (const_int -1)) 4684: (const_int 0)) 4685: (label_ref (match_operand 1 "" "")) 4686: (pc))) 4687: (set (match_dup 0) 4688: (plus:SI (match_dup 0) 4689: (const_int -1)))] 4690: "find_reg_note (insn, REG_NONNEG, 0)" 4691: "* 4692: { 4693: CC_STATUS_INIT; 4694: #ifdef MOTOROLA 4695: #ifdef NO_ADDSUB_Q 4696: if (DATA_REG_P (operands[0])) 4697: return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\"; 4698: if (GET_CODE (operands[0]) == MEM) 4699: return \"sub%.l %#1,%0\;jbcc %l1\"; 4700: #else 4701: if (DATA_REG_P (operands[0])) 4702: return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\"; 4703: if (GET_CODE (operands[0]) == MEM) 4704: return \"subq%.l %#1,%0\;jbcc %l1\"; 4705: #endif 4706: #ifdef SGS_CMP_ORDER 4707: #ifdef NO_ADDSUB_Q 4708: return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; 4709: #else 4710: return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\"; 4711: #endif 4712: #else /* not SGS_CMP_ORDER */ 4713: return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\"; 4714: #endif /* not SGS_CMP_ORDER */ 4715: #else /* not MOTOROLA */ 4716: if (DATA_REG_P (operands[0])) 4717: return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\"; 4718: if (GET_CODE (operands[0]) == MEM) 4719: return \"subql %#1,%0\;jcc %l1\"; 4720: return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\"; 4721: #endif /* not MOTOROLA */ 4722: }") 4723: 4724: 4725: ;; PIC calls are handled by loading the address of the function into a 4726: ;; register (via movsi), then emitting a register indirect call using 4727: ;; the "jsr" function call syntax. 4728: ;; 4729: ;; It is important to note that the "jsr" syntax is always used for 4730: ;; PIC calls, even on machines in which GCC normally uses the "jbsr" 4731: ;; syntax for non-PIC calls. This keeps at least 1 assembler (Sun) 4732: ;; from emitting incorrect code for a PIC call. 4733: ;; 4734: ;; We have different patterns for PIC calls and non-PIC calls. The 4735: ;; different patterns are only used to choose the right syntax 4736: ;; ("jsr" vs "jbsr"). 4737: ;; 4738: ;; On svr4 m68k, PIC stuff is done differently. To be able to support 4739: ;; dynamic linker LAZY BINDING, all the procedure calls need to go 4740: ;; through the PLT (Procedure Linkage Table) section in PIC mode. The 4741: ;; svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it 4742: ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC', 4743: ;; that tells the linker editor to create an entry for `FUNC' in PLT 4744: ;; section at link time. However, all global objects reference are still 4745: ;; done by using `OBJ@GOT'. So, the goal here is to output the function 4746: ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'. 4747: ;; We need to have a way to differentiate these two different operands. 4748: ;; 4749: ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate 4750: ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs 4751: ;; to be changed to recognize function calls symbol_ref operand as a legal 4752: ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will 4753: ;; avoid the compiler to load this symbol_ref operand into a register. 4754: ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly 4755: ;; since the value is a PC relative offset, not a real address. 4756: ;; 4757: ;; All global objects are treated in the similar way as in SUN3. The only 4758: ;; difference is: on m68k svr4, the reference of such global object needs 4759: ;; to end with a suffix "@GOT" so the assembler and linker know to create 4760: ;; an entry for it in GOT (Global Offset Table) section. This is done in 4761: ;; m68k.c. 4762: 4763: ;; Call subroutine with no return value. 4764: (define_expand "call" 4765: [(call (match_operand:QI 0 "memory_operand" "") 4766: (match_operand:SI 1 "general_operand" ""))] 4767: ;; Operand 1 not really used on the m68000. 4768: 4769: "" 4770: " 4771: { 4772: if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) 4773: #ifdef MOTOROLA 4774: SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1; 4775: #else 4776: operands[0] = gen_rtx (MEM, GET_MODE (operands[0]), 4777: force_reg (Pmode, XEXP (operands[0], 0))); 4778: #endif 4779: }") 4780: 4781: ;; This is a normal call sequence. 4782: (define_insn "" 4783: [(call (match_operand:QI 0 "memory_operand" "o") 4784: (match_operand:SI 1 "general_operand" "g"))] 4785: ;; Operand 1 not really used on the m68000. 4786: 4787: "! flag_pic" 4788: "* 4789: #ifdef MOTOROLA 1.1.1.3 ! root 4790: #ifdef MOTOROLA_BSR ! 4791: if (GET_CODE (operands[0]) == MEM ! 4792: && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) ! 4793: return \"bsr %0\"; ! 4794: #endif 1.1 root 4795: return \"jsr %0\"; 4796: #else 4797: return \"jbsr %0\"; 4798: #endif 4799: ") 4800: 4801: ;; This is a PIC call sequence. 4802: (define_insn "" 4803: [(call (match_operand:QI 0 "memory_operand" "o") 4804: (match_operand:SI 1 "general_operand" "g"))] 4805: ;; Operand 1 not really used on the m68000. 4806: 4807: "flag_pic" 4808: "* 4809: #ifdef MOTOROLA 4810: if (GET_CODE (operands[0]) == MEM 4811: && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) 1.1.1.3 ! root 4812: #ifdef HPUX_ASM ! 4813: return \"bsr.l %0\"; ! 4814: #else 1.1 root 4815: return \"bsr %0@PLTPC\"; 4816: #endif 1.1.1.2 root 4817: #endif 1.1.1.3 ! root 4818: return \"jsr %0\"; 1.1 root 4819: ") 4820: 4821: ;; Call subroutine, returning value in operand 0 4822: ;; (which must be a hard register). 4823: ;; See comments before "call" regarding PIC calls. 4824: (define_expand "call_value" 4825: [(set (match_operand 0 "" "") 4826: (call (match_operand:QI 1 "memory_operand" "") 4827: (match_operand:SI 2 "general_operand" "")))] 4828: ;; Operand 2 not really used on the m68000. 4829: "" 4830: " 4831: { 4832: if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) 4833: #ifdef MOTOROLA 4834: SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1; 4835: #else 4836: operands[1] = gen_rtx (MEM, GET_MODE (operands[1]), 4837: force_reg (Pmode, XEXP (operands[1], 0))); 4838: #endif 4839: }") 4840: 4841: ;; This is a normal call_value 4842: (define_insn "" 4843: [(set (match_operand 0 "" "=rf") 4844: (call (match_operand:QI 1 "memory_operand" "o") 4845: (match_operand:SI 2 "general_operand" "g")))] 4846: ;; Operand 2 not really used on the m68000. 4847: "! flag_pic" 4848: "* 4849: #ifdef MOTOROLA 1.1.1.3 ! root 4850: #ifdef MOTOROLA_BSR ! 4851: if (GET_CODE (operands[1]) == MEM ! 4852: && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) ! 4853: return \"bsr %1\"; ! 4854: #endif 1.1 root 4855: return \"jsr %1\"; 4856: #else 4857: return \"jbsr %1\"; 4858: #endif 4859: ") 4860: 4861: ;; This is a PIC call_value 4862: (define_insn "" 4863: [(set (match_operand 0 "" "=rf") 4864: (call (match_operand:QI 1 "memory_operand" "o") 4865: (match_operand:SI 2 "general_operand" "g")))] 4866: ;; Operand 2 not really used on the m68000. 4867: "flag_pic" 4868: "* 4869: #ifdef MOTOROLA 4870: if (GET_CODE (operands[1]) == MEM 4871: && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) 1.1.1.3 ! root 4872: #ifdef HPUX_ASM ! 4873: return \"bsr.l %1\"; ! 4874: #else 1.1 root 4875: return \"bsr %1@PLTPC\"; 4876: #endif 1.1.1.2 root 4877: #endif 1.1.1.3 ! root 4878: return \"jsr %1\"; 1.1 root 4879: ") 4880: 4881: ;; Call subroutine returning any type. 4882: 4883: (define_expand "untyped_call" 4884: [(parallel [(call (match_operand 0 "" "") 4885: (const_int 0)) 4886: (match_operand 1 "" "") 4887: (match_operand 2 "" "")])] 4888: "NEEDS_UNTYPED_CALL" 4889: " 4890: { 4891: int i; 4892: 4893: emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 4894: 4895: for (i = 0; i < XVECLEN (operands[2], 0); i++) 4896: { 4897: rtx set = XVECEXP (operands[2], 0, i); 4898: emit_move_insn (SET_DEST (set), SET_SRC (set)); 4899: } 4900: 4901: /* The optimizer does not know that the call sets the function value 4902: registers we stored in the result block. We avoid problems by 4903: claiming that all hard registers are used and clobbered at this 4904: point. */ 4905: emit_insn (gen_blockage ()); 4906: 4907: DONE; 4908: }") 4909: 4910: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 4911: ;; all of memory. This blocks insns from being moved across this point. 4912: 4913: (define_insn "blockage" 4914: [(unspec_volatile [(const_int 0)] 0)] 4915: "" 4916: "") 4917: 4918: (define_insn "nop" 4919: [(const_int 0)] 4920: "" 4921: "nop") 4922: 4923: (define_insn "probe" 4924: [(reg:SI 15)] 4925: "NEED_PROBE" 4926: "* 4927: { 4928: operands[0] = gen_rtx (PLUS, SImode, stack_pointer_rtx, 4929: gen_rtx (CONST_INT, VOIDmode, NEED_PROBE)); 4930: return \"tstl %a0\"; 4931: }") 4932: 4933: ;; Used for frameless functions which save no regs and allocate no locals. 4934: (define_insn "return" 4935: [(return)] 4936: "USE_RETURN_INSN" 4937: "* 4938: { 4939: if (current_function_pops_args == 0) 4940: return \"rts\"; 4941: operands[0] = gen_rtx (CONST_INT, VOIDmode, current_function_pops_args); 4942: return \"rtd %0\"; 4943: }") 4944: 4945: (define_insn "indirect_jump" 4946: [(set (pc) (match_operand:SI 0 "address_operand" "p"))] 4947: "" 4948: "jmp %a0") 4949: 4950: ;; This should not be used unless the add/sub insns can't be. 4951: 4952: (define_insn "" 4953: [(set (match_operand:SI 0 "general_operand" "=a") 4954: (match_operand:QI 1 "address_operand" "p"))] 4955: "" 1.1.1.3 ! root 4956: "* ! 4957: { ! 4958: #ifndef SGS_NO_LI ! 4959: /* Recognize an insn that refers to a table of offsets. Such an insn will ! 4960: need to refer to a label on the insn. So output one. Use the ! 4961: label-number of the table of offsets to generate this label. This code, ! 4962: and similar code above, assumes that there will be at most one reference ! 4963: to each table. */ ! 4964: if (GET_CODE (operands[1]) == PLUS ! 4965: && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF ! 4966: && GET_CODE (XEXP (operands[1], 0)) != PLUS) ! 4967: { ! 4968: rtx labelref = XEXP (operands[1], 1); ! 4969: #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES) ! 4970: #ifdef SGS ! 4971: asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\", ! 4972: CODE_LABEL_NUMBER (XEXP (labelref, 0))); ! 4973: #else /* not SGS */ ! 4974: asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\", ! 4975: CODE_LABEL_NUMBER (XEXP (labelref, 0))); ! 4976: #endif /* not SGS */ ! 4977: #else /* SGS_SWITCH_TABLES or not MOTOROLA */ ! 4978: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", ! 4979: CODE_LABEL_NUMBER (XEXP (labelref, 0))); ! 4980: #ifdef SGS_SWITCH_TABLES ! 4981: /* Set flag saying we need to define the symbol ! 4982: LD%n (with value L%n-LI%n) at the end of the switch table. */ ! 4983: switch_table_difference_label_flag = 1; ! 4984: #endif /* SGS_SWITCH_TABLES */ ! 4985: #endif /* SGS_SWITCH_TABLES or not MOTOROLA */ ! 4986: } ! 4987: #endif /* SGS_NO_LI */ ! 4988: ! 4989: return \"lea %a1,%0\"; ! 4990: }") 1.1 root 4991: 4992: ;; This is the first machine-dependent peephole optimization. 4993: ;; It is useful when a floating value is returned from a function call 4994: ;; and then is moved into an FP register. 4995: ;; But it is mainly intended to test the support for these optimizations. 4996: 4997: (define_peephole 4998: [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4))) 4999: (set (match_operand:DF 0 "register_operand" "=f") 5000: (match_operand:DF 1 "register_operand" "ad"))] 5001: "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])" 5002: "* 5003: { 5004: rtx xoperands[2]; 5005: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 5006: output_asm_insn (\"move%.l %1,%@\", xoperands); 5007: output_asm_insn (\"move%.l %1,%-\", operands); 5008: return \"fmove%.d %+,%0\"; 5009: } 5010: ") 5011: 5012: ;; Optimize a stack-adjust followed by a push of an argument. 5013: ;; This is said to happen frequently with -msoft-float 5014: ;; when there are consecutive library calls. 5015: 5016: (define_peephole 5017: [(set (reg:SI 15) (plus:SI (reg:SI 15) 1.1.1.3 ! root 5018: (match_operand:SI 0 "const_int_operand" "n"))) 1.1 root 5019: (set (match_operand:SF 1 "push_operand" "=m") 5020: (match_operand:SF 2 "general_operand" "rmfF"))] 1.1.1.3 ! root 5021: "INTVAL (operands[0]) >= 4 1.1 root 5022: && ! reg_mentioned_p (stack_pointer_rtx, operands[2])" 5023: "* 5024: { 5025: if (INTVAL (operands[0]) > 4) 5026: { 5027: rtx xoperands[2]; 5028: xoperands[0] = stack_pointer_rtx; 5029: xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4); 5030: #ifndef NO_ADDSUB_Q 5031: if (INTVAL (xoperands[1]) <= 8) 5032: output_asm_insn (\"addq%.w %1,%0\", xoperands); 5033: else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020) 5034: { 5035: xoperands[1] = gen_rtx (CONST_INT, VOIDmode, 5036: INTVAL (xoperands[1]) - 8); 5037: output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands); 5038: } 5039: else 5040: #endif 5041: if (INTVAL (xoperands[1]) <= 0x7FFF) 5042: output_asm_insn (\"add%.w %1,%0\", xoperands); 5043: else 5044: output_asm_insn (\"add%.l %1,%0\", xoperands); 5045: } 5046: if (FP_REG_P (operands[2])) 5047: return \"fmove%.s %2,%@\"; 5048: return \"move%.l %2,%@\"; 5049: }") 5050: 5051: ;; Speed up stack adjust followed by a fullword fixedpoint push. 5052: 5053: (define_peephole 5054: [(set (reg:SI 15) (plus:SI (reg:SI 15) 1.1.1.3 ! root 5055: (match_operand:SI 0 "const_int_operand" "n"))) 1.1 root 5056: (set (match_operand:SI 1 "push_operand" "=m") 5057: (match_operand:SI 2 "general_operand" "g"))] 1.1.1.3 ! root 5058: "INTVAL (operands[0]) >= 4 1.1 root 5059: && ! reg_mentioned_p (stack_pointer_rtx, operands[2])" 5060: "* 5061: { 5062: if (INTVAL (operands[0]) > 4) 5063: { 5064: rtx xoperands[2]; 5065: xoperands[0] = stack_pointer_rtx; 5066: xoperands[1] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[0]) - 4); 5067: #ifndef NO_ADDSUB_Q 5068: if (INTVAL (xoperands[1]) <= 8) 5069: output_asm_insn (\"addq%.w %1,%0\", xoperands); 5070: else if (INTVAL (xoperands[1]) <= 16 && TARGET_68020) 5071: { 5072: xoperands[1] = gen_rtx (CONST_INT, VOIDmode, 5073: INTVAL (xoperands[1]) - 8); 5074: output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands); 5075: } 5076: else 5077: #endif 5078: if (INTVAL (xoperands[1]) <= 0x7FFF) 5079: output_asm_insn (\"add%.w %1,%0\", xoperands); 5080: else 5081: output_asm_insn (\"add%.l %1,%0\", xoperands); 5082: } 5083: if (operands[2] == const0_rtx) 5084: return \"clr%.l %@\"; 5085: return \"move%.l %2,%@\"; 5086: }") 5087: 5088: ;; Speed up pushing a single byte but leaving four bytes of space. 5089: 5090: (define_peephole 5091: [(set (mem:QI (pre_dec:SI (reg:SI 15))) 5092: (match_operand:QI 1 "general_operand" "dami")) 5093: (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))] 5094: "! reg_mentioned_p (stack_pointer_rtx, operands[1])" 5095: "* 5096: { 5097: rtx xoperands[4]; 5098: 5099: if (GET_CODE (operands[1]) == REG) 5100: return \"move%.l %1,%-\"; 5101: 5102: xoperands[1] = operands[1]; 5103: xoperands[2] 5104: = gen_rtx (MEM, QImode, 5105: gen_rtx (PLUS, VOIDmode, stack_pointer_rtx, 5106: gen_rtx (CONST_INT, VOIDmode, 3))); 5107: xoperands[3] = stack_pointer_rtx; 5108: output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands); 5109: return \"\"; 5110: }") 5111: 5112: (define_peephole 5113: [(set (match_operand:SI 0 "register_operand" "=d") 5114: (const_int 0)) 5115: (set (strict_low_part (subreg:HI (match_dup 0) 0)) 5116: (match_operand:HI 1 "general_operand" "rmn"))] 5117: "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])" 5118: "* 5119: { 5120: if (GET_CODE (operands[1]) == CONST_INT) 5121: { 5122: if (operands[1] == const0_rtx 5123: && (DATA_REG_P (operands[0]) 5124: || GET_CODE (operands[0]) == MEM) 5125: /* clr insns on 68000 read before writing. 5126: This isn't so on the 68010, but we have no alternative for it. */ 5127: && (TARGET_68020 5128: || !(GET_CODE (operands[0]) == MEM 5129: && MEM_VOLATILE_P (operands[0])))) 5130: return \"clr%.w %0\"; 5131: } 5132: return \"move%.w %1,%0\"; 5133: }") 5134: 5135: ;; dbCC peepholes 5136: ;; 5137: ;; Turns 5138: ;; loop: 5139: ;; [ ... ] 5140: ;; jCC label ; abnormal loop termination 5141: ;; dbra dN, loop ; normal loop termination 5142: ;; 5143: ;; Into 5144: ;; loop: 5145: ;; [ ... ] 5146: ;; dbCC dN, loop 5147: ;; jCC label 5148: ;; 5149: ;; Which moves the jCC condition outside the inner loop for free. 5150: ;; 5151: (define_peephole 5152: [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" 5153: [(cc0) (const_int 0)]) 5154: (label_ref (match_operand 2 "" "")) 5155: (pc))) 5156: (parallel 5157: [(set (pc) 5158: (if_then_else 5159: (ge (plus:HI (match_operand:HI 0 "register_operand" "+d") 5160: (const_int -1)) 5161: (const_int 0)) 5162: (label_ref (match_operand 1 "" "")) 5163: (pc))) 5164: (set (match_dup 0) 5165: (plus:HI (match_dup 0) 5166: (const_int -1)))])] 5167: "DATA_REG_P (operands[0])" 5168: "* 5169: { 5170: CC_STATUS_INIT; 5171: output_dbcc_and_branch (operands); 5172: return \"\"; 5173: }") 5174: 5175: (define_peephole 5176: [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" 5177: [(cc0) (const_int 0)]) 5178: (label_ref (match_operand 2 "" "")) 5179: (pc))) 5180: (parallel 5181: [(set (pc) 5182: (if_then_else 5183: (ge (plus:SI (match_operand:SI 0 "register_operand" "+d") 5184: (const_int -1)) 5185: (const_int 0)) 5186: (label_ref (match_operand 1 "" "")) 5187: (pc))) 5188: (set (match_dup 0) 5189: (plus:SI (match_dup 0) 5190: (const_int -1)))])] 5191: "DATA_REG_P (operands[0])" 5192: "* 5193: { 5194: CC_STATUS_INIT; 5195: output_dbcc_and_branch (operands); 5196: return \"\"; 5197: }") 5198: 5199: 5200: ;; FPA multiply and add. 5201: (define_insn "" 5202: [(set (match_operand:DF 0 "register_operand" "=x,y,y") 5203: (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y") 5204: (match_operand:DF 2 "general_operand" "xH,y,y")) 5205: (match_operand:DF 3 "general_operand" "xH,y,dmF")))] 5206: "TARGET_FPA" 5207: "@ 5208: fpma%.d %1,%w2,%w3,%0 5209: fpma%.d %x1,%x2,%x3,%0 5210: fpma%.d %x1,%x2,%x3,%0") 5211: 5212: (define_insn "" 5213: [(set (match_operand:SF 0 "register_operand" "=x,y,y") 5214: (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y") 5215: (match_operand:SF 2 "general_operand" "xH,y,ydmF")) 5216: (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))] 5217: "TARGET_FPA" 5218: "@ 5219: fpma%.s %1,%w2,%w3,%0 5220: fpma%.s %1,%2,%3,%0 5221: fpma%.s %1,%2,%3,%0") 5222: 5223: ;; FPA Multiply and subtract 5224: (define_insn "" 5225: [(set (match_operand:DF 0 "register_operand" "=x,y,y") 5226: (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y") 5227: (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y") 5228: (match_operand:DF 3 "general_operand" "x,y,rmF"))))] 5229: "TARGET_FPA" 5230: "@ 5231: fpms%.d %3,%w2,%w1,%0 5232: fpms%.d %x3,%2,%x1,%0 5233: fpms%.d %x3,%2,%x1,%0") 5234: 5235: (define_insn "" 5236: [(set (match_operand:SF 0 "register_operand" "=x,y,y") 5237: (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF") 5238: (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y") 5239: (match_operand:SF 3 "general_operand" "x,y,yrmF"))))] 5240: "TARGET_FPA" 5241: "@ 5242: fpms%.s %3,%w2,%w1,%0 5243: fpms%.s %3,%2,%1,%0 5244: fpms%.s %3,%2,%1,%0") 5245: 5246: (define_insn "" 5247: [(set (match_operand:DF 0 "register_operand" "=x,y,y") 5248: (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y") 5249: (match_operand:DF 2 "general_operand" "x,y,rmF")) 5250: (match_operand:DF 3 "general_operand" "xH,rmF,y")))] 5251: "TARGET_FPA" 5252: "@ 5253: fpmr%.d %2,%w1,%w3,%0 5254: fpmr%.d %x2,%1,%x3,%0 5255: fpmr%.d %x2,%1,%x3,%0") 5256: 5257: (define_insn "" 5258: [(set (match_operand:SF 0 "register_operand" "=x,y,y") 5259: (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y") 5260: (match_operand:SF 2 "general_operand" "x,y,yrmF")) 5261: (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))] 5262: "TARGET_FPA" 5263: "@ 5264: fpmr%.s %2,%w1,%w3,%0 5265: fpmr%.s %x2,%1,%x3,%0 5266: fpmr%.s %x2,%1,%x3,%0") 5267: 5268: ;; FPA Add and multiply 5269: (define_insn "" 5270: [(set (match_operand:DF 0 "register_operand" "=x,y,y") 5271: (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y") 5272: (match_operand:DF 2 "general_operand" "x,y,rmF")) 5273: (match_operand:DF 3 "general_operand" "xH,rmF,y")))] 5274: "TARGET_FPA" 5275: "@ 5276: fpam%.d %2,%w1,%w3,%0 5277: fpam%.d %x2,%1,%x3,%0 5278: fpam%.d %x2,%1,%x3,%0") 5279: 5280: (define_insn "" 5281: [(set (match_operand:SF 0 "register_operand" "=x,y,y") 5282: (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y") 5283: (match_operand:SF 2 "general_operand" "x,y,yrmF")) 5284: (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))] 5285: "TARGET_FPA" 5286: "@ 5287: fpam%.s %2,%w1,%w3,%0 5288: fpam%.s %x2,%1,%x3,%0 5289: fpam%.s %x2,%1,%x3,%0") 5290: 5291: ;;FPA Subtract and multiply 5292: (define_insn "" 5293: [(set (match_operand:DF 0 "register_operand" "=x,y,y") 5294: (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y") 5295: (match_operand:DF 2 "general_operand" "x,y,rmF")) 5296: (match_operand:DF 3 "general_operand" "xH,rmF,y")))] 5297: "TARGET_FPA" 5298: "@ 5299: fpsm%.d %2,%w1,%w3,%0 5300: fpsm%.d %x2,%1,%x3,%0 5301: fpsm%.d %x2,%1,%x3,%0") 5302: 5303: (define_insn "" 5304: [(set (match_operand:DF 0 "register_operand" "=x,y,y") 5305: (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y") 5306: (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y") 5307: (match_operand:DF 3 "general_operand" "x,y,rmF"))))] 5308: "TARGET_FPA" 5309: "@ 5310: fpsm%.d %3,%w2,%w1,%0 5311: fpsm%.d %x3,%2,%x1,%0 5312: fpsm%.d %x3,%2,%x1,%0") 5313: 5314: (define_insn "" 5315: [(set (match_operand:SF 0 "register_operand" "=x,y,y") 5316: (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y") 5317: (match_operand:SF 2 "general_operand" "x,y,yrmF")) 5318: (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))] 5319: "TARGET_FPA" 5320: "@ 5321: fpsm%.s %2,%w1,%w3,%0 5322: fpsm%.s %x2,%1,%x3,%0 5323: fpsm%.s %x2,%1,%x3,%0") 5324: 5325: (define_insn "" 5326: [(set (match_operand:SF 0 "register_operand" "=x,y,y") 5327: (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF") 5328: (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y") 5329: (match_operand:SF 3 "general_operand" "x,y,yrmF"))))] 5330: "TARGET_FPA" 5331: "@ 5332: fpsm%.s %3,%w2,%w1,%0 5333: fpsm%.s %x3,%2,%x1,%0 5334: fpsm%.s %x3,%2,%x1,%0") 5335: 5336: (define_insn "tstxf" 5337: [(set (cc0) 5338: (match_operand:XF 0 "nonimmediate_operand" "fm"))] 5339: "TARGET_68881" 5340: "* 5341: { 5342: cc_status.flags = CC_IN_68881; 5343: return \"ftst%.x %0\"; 5344: }") 5345: 5346: 5347: (define_expand "cmpxf" 5348: [(set (cc0) 5349: (compare (match_operand:XF 0 "general_operand" "f,mG") 5350: (match_operand:XF 1 "general_operand" "fmG,f")))] 5351: "TARGET_68881" 5352: " 5353: { 5354: if (CONSTANT_P (operands[0])) 5355: operands[0] = force_const_mem (XFmode, operands[0]); 5356: if (CONSTANT_P (operands[1])) 5357: operands[1] = force_const_mem (XFmode, operands[1]); 5358: }") 5359: 5360: (define_insn "" 5361: [(set (cc0) 5362: (compare (match_operand:XF 0 "nonimmediate_operand" "f,mG") 5363: (match_operand:XF 1 "nonimmediate_operand" "fmG,f")))] 5364: "TARGET_68881" 5365: "* 5366: { 5367: cc_status.flags = CC_IN_68881; 5368: #ifdef SGS_CMP_ORDER 5369: if (REG_P (operands[0])) 5370: { 5371: if (REG_P (operands[1])) 5372: return \"fcmp%.x %0,%1\"; 5373: else 5374: return \"fcmp%.x %0,%f1\"; 5375: } 5376: cc_status.flags |= CC_REVERSED; 5377: return \"fcmp%.x %1,%f0\"; 5378: #else 5379: if (REG_P (operands[0])) 5380: { 5381: if (REG_P (operands[1])) 5382: return \"fcmp%.x %1,%0\"; 5383: else 5384: return \"fcmp%.x %f1,%0\"; 5385: } 5386: cc_status.flags |= CC_REVERSED; 5387: return \"fcmp%.x %f0,%1\"; 5388: #endif 5389: }") 5390: 5391: (define_insn "extendsfxf2" 5392: [(set (match_operand:XF 0 "general_operand" "=fm,f") 5393: (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))] 5394: "TARGET_68881" 5395: "* 5396: { 5397: if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) 5398: { 5399: if (REGNO (operands[0]) == REGNO (operands[1])) 5400: { 5401: /* Extending float to double in an fp-reg is a no-op. 5402: NOTICE_UPDATE_CC has already assumed that the 5403: cc will be set. So cancel what it did. */ 5404: cc_status = cc_prev_status; 5405: return \"\"; 5406: } 5407: return \"f%$move%.x %1,%0\"; 5408: } 5409: if (FP_REG_P (operands[0])) 5410: return \"f%$move%.s %f1,%0\"; 5411: return \"fmove%.x %f1,%0\"; 5412: }") 5413: 5414: 5415: (define_insn "extenddfxf2" 5416: [(set (match_operand:XF 0 "general_operand" "=fm,f") 5417: (float_extend:XF 5418: (match_operand:DF 1 "general_operand" "f,m")))] 5419: "TARGET_68881" 5420: "* 5421: { 5422: if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) 5423: { 5424: if (REGNO (operands[0]) == REGNO (operands[1])) 5425: { 5426: /* Extending float to double in an fp-reg is a no-op. 5427: NOTICE_UPDATE_CC has already assumed that the 5428: cc will be set. So cancel what it did. */ 5429: cc_status = cc_prev_status; 5430: return \"\"; 5431: } 5432: return \"fmove%.x %1,%0\"; 5433: } 5434: if (FP_REG_P (operands[0])) 5435: return \"f%&move%.d %f1,%0\"; 5436: return \"fmove%.x %f1,%0\"; 5437: }") 5438: 5439: (define_insn "truncxfdf2" 5440: [(set (match_operand:DF 0 "general_operand" "=m,!r") 5441: (float_truncate:DF 5442: (match_operand:XF 1 "general_operand" "f,f")))] 5443: "TARGET_68881" 5444: "* 5445: { 5446: if (REG_P (operands[0])) 5447: { 5448: output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands); 5449: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 5450: return \"move%.l %+,%0\"; 5451: } 5452: return \"fmove%.d %f1,%0\"; 5453: }") 5454: 5455: (define_insn "truncxfsf2" 5456: [(set (match_operand:SF 0 "general_operand" "=dm") 5457: (float_truncate:SF 5458: (match_operand:XF 1 "general_operand" "f")))] 5459: "TARGET_68881" 5460: "fmove%.s %f1,%0") 5461: 5462: (define_insn "floatsixf2" 5463: [(set (match_operand:XF 0 "general_operand" "=f") 5464: (float:XF (match_operand:SI 1 "general_operand" "dmi")))] 5465: "TARGET_68881" 5466: "fmove%.l %1,%0") 5467: 5468: (define_insn "floathixf2" 5469: [(set (match_operand:XF 0 "general_operand" "=f") 5470: (float:XF (match_operand:HI 1 "general_operand" "dmn")))] 5471: "TARGET_68881" 5472: "fmove%.w %1,%0") 5473: 5474: (define_insn "floatqixf2" 5475: [(set (match_operand:XF 0 "general_operand" "=f") 5476: (float:XF (match_operand:QI 1 "general_operand" "dmn")))] 5477: "TARGET_68881" 5478: "fmove%.b %1,%0") 5479: 5480: (define_insn "ftruncxf2" 5481: [(set (match_operand:XF 0 "general_operand" "=f") 5482: (fix:XF (match_operand:XF 1 "general_operand" "fFm")))] 5483: "TARGET_68881" 5484: "* 5485: { 5486: if (FP_REG_P (operands[1])) 5487: return \"fintrz%.x %f1,%0\"; 5488: return \"fintrz%.x %f1,%0\"; 5489: }") 5490: 5491: (define_insn "fixxfqi2" 5492: [(set (match_operand:QI 0 "general_operand" "=dm") 5493: (fix:QI (match_operand:XF 1 "general_operand" "f")))] 5494: "TARGET_68881" 5495: "fmove%.b %1,%0") 5496: 5497: (define_insn "fixxfhi2" 5498: [(set (match_operand:HI 0 "general_operand" "=dm") 5499: (fix:HI (match_operand:XF 1 "general_operand" "f")))] 5500: "TARGET_68881" 5501: "fmove%.w %1,%0") 5502: 5503: (define_insn "fixxfsi2" 5504: [(set (match_operand:SI 0 "general_operand" "=dm") 5505: (fix:SI (match_operand:XF 1 "general_operand" "f")))] 5506: "TARGET_68881" 5507: "fmove%.l %1,%0") 5508: 5509: (define_expand "addxf3" 5510: [(set (match_operand:XF 0 "general_operand" "") 5511: (plus:XF (match_operand:XF 1 "general_operand" "") 5512: (match_operand:XF 2 "general_operand" "")))] 5513: "TARGET_68881" 5514: " 5515: { 5516: if (CONSTANT_P (operands[1])) 5517: operands[1] = force_const_mem (XFmode, operands[1]); 5518: if (CONSTANT_P (operands[2])) 5519: operands[2] = force_const_mem (XFmode, operands[2]); 5520: }") 5521: 5522: (define_insn "" 5523: [(set (match_operand:XF 0 "general_operand" "=f") 5524: (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0") 5525: (match_operand:XF 2 "nonimmediate_operand" "fmG")))] 5526: "TARGET_68881" 5527: "* 5528: { 5529: if (REG_P (operands[2])) 5530: return \"fadd%.x %2,%0\"; 5531: return \"fadd%.x %f2,%0\"; 5532: }") 5533: 5534: (define_expand "subxf3" 5535: [(set (match_operand:XF 0 "general_operand" "") 5536: (minus:XF (match_operand:XF 1 "general_operand" "") 5537: (match_operand:XF 2 "general_operand" "")))] 5538: "TARGET_68881" 5539: " 5540: { 5541: if (CONSTANT_P (operands[1])) 5542: operands[1] = force_const_mem (XFmode, operands[1]); 5543: if (CONSTANT_P (operands[2])) 5544: operands[2] = force_const_mem (XFmode, operands[2]); 5545: }") 5546: 5547: (define_insn "" 5548: [(set (match_operand:XF 0 "general_operand" "=f") 5549: (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0") 5550: (match_operand:XF 2 "nonimmediate_operand" "fmG")))] 5551: "TARGET_68881" 5552: "* 5553: { 5554: if (REG_P (operands[2])) 5555: return \"fsub%.x %2,%0\"; 5556: return \"fsub%.x %f2,%0\"; 5557: }") 5558: 5559: (define_expand "mulxf3" 5560: [(set (match_operand:XF 0 "general_operand" "") 5561: (mult:XF (match_operand:XF 1 "general_operand" "") 5562: (match_operand:XF 2 "general_operand" "")))] 5563: "TARGET_68881" 5564: " 5565: { 5566: if (CONSTANT_P (operands[1])) 5567: operands[1] = force_const_mem (XFmode, operands[1]); 5568: if (CONSTANT_P (operands[2])) 5569: operands[2] = force_const_mem (XFmode, operands[2]); 5570: }") 5571: 5572: (define_insn "" 5573: [(set (match_operand:XF 0 "general_operand" "=f") 5574: (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0") 5575: (match_operand:XF 2 "nonimmediate_operand" "fmG")))] 5576: "TARGET_68881" 5577: "* 5578: { 5579: if (REG_P (operands[2])) 5580: return \"fmul%.x %2,%0\"; 5581: return \"fmul%.x %f2,%0\"; 5582: }") 5583: 5584: (define_expand "divxf3" 5585: [(set (match_operand:XF 0 "general_operand" "") 5586: (div:XF (match_operand:XF 1 "general_operand" "") 5587: (match_operand:XF 2 "general_operand" "")))] 5588: "TARGET_68881" 5589: " 5590: { 5591: if (CONSTANT_P (operands[1])) 5592: operands[1] = force_const_mem (XFmode, operands[1]); 5593: if (CONSTANT_P (operands[2])) 5594: operands[2] = force_const_mem (XFmode, operands[2]); 5595: }") 5596: 5597: (define_insn "" 5598: [(set (match_operand:XF 0 "general_operand" "=f") 5599: (div:XF (match_operand:XF 1 "nonimmediate_operand" "0") 5600: (match_operand:XF 2 "nonimmediate_operand" "fmG")))] 5601: "TARGET_68881" 5602: "* 5603: { 5604: if (REG_P (operands[2])) 5605: return \"fdiv%.x %2,%0\"; 5606: return \"fdiv%.x %f2,%0\"; 5607: }") 5608: 5609: (define_insn "negxf2" 5610: [(set (match_operand:XF 0 "general_operand" "=f") 5611: (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fmF")))] 5612: "TARGET_68881" 5613: "* 5614: { 5615: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) 5616: return \"fneg%.x %1,%0\"; 5617: return \"fneg%.x %f1,%0\"; 5618: }") 5619: 5620: (define_insn "absxf2" 5621: [(set (match_operand:XF 0 "general_operand" "=f") 5622: (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fmF")))] 5623: "TARGET_68881" 5624: "* 5625: { 5626: if (REG_P (operands[1]) && ! DATA_REG_P (operands[1])) 5627: return \"fabs%.x %1,%0\"; 5628: return \"fabs%.x %f1,%0\"; 5629: }") 5630: 5631: (define_insn "sqrtxf2" 5632: [(set (match_operand:XF 0 "general_operand" "=f") 5633: (sqrt:XF (match_operand:DF 1 "nonimmediate_operand" "fm")))] 5634: "TARGET_68881" 5635: "* 5636: { 5637: return \"fsqrt%.x %1,%0\"; 5638: }")
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