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1.1 root 1: ;;- Machine description for the Motorola 88000 for GNU C compiler
2: ;; Copyright (C) 1988 Free Software Foundation, Inc.
3: ;; Contributed by Michael Tiemann ([email protected])
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 1, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21:
22: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
23:
24: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
25: ;;- updates for most instructions.
26:
27: ;;- Operand classes for the register allocator:
28:
29: ;; Compare instructions.
30: ;; This pattern is used for generating an "insn"
31: ;; which does just a compare and sets a (fictitious) condition code.
32:
33: ;; The actual the m88000 insns are compare-and-conditional-jump.
34: ;; The define_peephole's below recognize the combinations of
35: ;; compares and jumps, and output each pair as a single assembler insn.
36:
37: ;; This controls RTL generation and register allocation.
38: (define_insn "cmpsi"
39: [(set (cc0)
40: (compare (match_operand:SI 0 "arith_operand" "rI")
41: (match_operand:SI 1 "arith_operand" "rI")))]
42: ""
43: "*
44: {
45: if (GET_CODE (operands[0]) == CONST_INT)
46: {
47: cc_status.flags |= CC_REVERSED;
48: return \"cmp r25,%1,%0\";
49: }
50: return \"cmp r25,%0,%1\";
51: }")
52:
53: (define_insn "cmpdf"
54: [(set (cc0)
55: (compare (match_operand:DF 0 "nonmemory_operand" "rG")
56: (match_operand:DF 1 "nonmemory_operand" "rG")))]
57: ""
58: "*
59: {
60: if (GET_CODE (operands[0]) == CONST_DOUBLE)
61: {
62: cc_status.flags |= CC_REVERSED | CC_IN_FCCR;
63: return \"fcmp.sdd r25,%1,%0\";
64: }
65: cc_status.flags |= CC_IN_FCCR;
66: return \"fcmp.sdd r25,%0,%1\";
67: }")
68:
69: (define_insn "cmpsf"
70: [(set (cc0)
71: (compare (match_operand:SF 0 "nonmemory_operand" "rG")
72: (match_operand:SF 1 "nonmemory_operand" "rG")))]
73: ""
74: "*
75: {
76: if (GET_CODE (operands[0]) == CONST_DOUBLE)
77: {
78: cc_status.flags |= CC_REVERSED | CC_IN_FCCR;
79: return \"fcmp.sss r25,%1,%0\";
80: }
81: cc_status.flags |= CC_IN_FCCR;
82: return \"fcmp.sss r25,%0,%1\";
83: }")
84: ;; We have to have this because cse can optimize the previous pattern
85: ;; into this one.
86:
87: (define_insn "tstsi"
88: [(set (cc0)
89: (match_operand:SI 0 "register_operand" "r"))]
90: ""
91: "cmp r25,%0,0")
92:
93: (define_insn "tstdf"
94: [(set (cc0)
95: (match_operand:DF 0 "register_operand" "r"))]
96: ""
97: "*
98: {
99: cc_status.flags |= CC_IN_FCCR;
100: return \"fcmp.sds r25,%0,r0\";
101: }")
102:
103: (define_insn "tstsf"
104: [(set (cc0)
105: (match_operand:SF 0 "register_operand" "r"))]
106: ""
107: "*
108: {
109: cc_status.flags |= CC_IN_FCCR;
110: return \"fcmp.sss r25,%0,r0\";
111: }")
112:
113: ;; These control RTL generation for conditional jump insns
114: ;; and match them for register allocation.
115:
116: (define_insn "beq"
117: [(set (pc)
118: (if_then_else (eq (cc0)
119: (const_int 0))
120: (label_ref (match_operand 0 "" ""))
121: (pc)))]
122: ""
123: "bb1 eq,r25,%l0")
124:
125: (define_peephole
126: [(set (cc0)
127: (match_operand:SI 0 "register_operand" "r"))
128: (set (pc)
129: (if_then_else (eq (cc0)
130: (const_int 0))
131: (label_ref (match_operand 1 "" ""))
132: (pc)))]
133: ""
134: "*
135: {
136: CC_STATUS_INIT;
137: return \"bcnd eq0,%0,%l1\";
138: }")
139:
140: (define_insn "bne"
141: [(set (pc)
142: (if_then_else (ne (cc0)
143: (const_int 0))
144: (label_ref (match_operand 0 "" ""))
145: (pc)))]
146: ""
147: "bb1 ne,r25,%l0")
148:
149: (define_peephole
150: [(set (cc0)
151: (match_operand:SI 0 "register_operand" "r"))
152: (set (pc)
153: (if_then_else (ne (cc0)
154: (const_int 0))
155: (label_ref (match_operand 1 "" ""))
156: (pc)))]
157: ""
158: "*
159: {
160: CC_STATUS_INIT;
161: return \"bcnd ne0,%0,%l1\";
162: }")
163:
164: (define_insn "bgt"
165: [(set (pc)
166: (if_then_else (gt (cc0)
167: (const_int 0))
168: (label_ref (match_operand 0 "" ""))
169: (pc)))]
170: ""
171: "bb1 gt,r25,%l0")
172:
173: (define_insn "bgtu"
174: [(set (pc)
175: (if_then_else (gtu (cc0)
176: (const_int 0))
177: (label_ref (match_operand 0 "" ""))
178: (pc)))]
179: ""
180: "bb1 hi,r25,%l0")
181:
182: (define_insn "blt"
183: [(set (pc)
184: (if_then_else (lt (cc0)
185: (const_int 0))
186: (label_ref (match_operand 0 "" ""))
187: (pc)))]
188: ""
189: "bb1 lt,r25,%l0")
190:
191: (define_insn "bltu"
192: [(set (pc)
193: (if_then_else (ltu (cc0)
194: (const_int 0))
195: (label_ref (match_operand 0 "" ""))
196: (pc)))]
197: ""
198: "bb1 lo,r25,%l0")
199:
200: (define_insn "bge"
201: [(set (pc)
202: (if_then_else (ge (cc0)
203: (const_int 0))
204: (label_ref (match_operand 0 "" ""))
205: (pc)))]
206: ""
207: "bb1 ge,r25,%l0")
208:
209: (define_insn "bgeu"
210: [(set (pc)
211: (if_then_else (geu (cc0)
212: (const_int 0))
213: (label_ref (match_operand 0 "" ""))
214: (pc)))]
215: ""
216: "bb1 hs,r25,%l0")
217:
218: (define_insn "ble"
219: [(set (pc)
220: (if_then_else (le (cc0)
221: (const_int 0))
222: (label_ref (match_operand 0 "" ""))
223: (pc)))]
224: ""
225: "bb1 le,r25,%l0")
226:
227: (define_insn "bleu"
228: [(set (pc)
229: (if_then_else (leu (cc0)
230: (const_int 0))
231: (label_ref (match_operand 0 "" ""))
232: (pc)))]
233: ""
234: "bb1 ls,r25,%l0")
235:
236: ;; These match inverted jump insns for register allocation.
237:
238: (define_insn ""
239: [(set (pc)
240: (if_then_else (eq (cc0)
241: (const_int 0))
242: (pc)
243: (label_ref (match_operand 0 "" ""))))]
244: ""
245: "bb0 eq,r25,%l0")
246:
247: (define_peephole
248: [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
249: (set (pc)
250: (if_then_else (eq (cc0)
251: (const_int 0))
252: (pc)
253: (label_ref (match_operand 1 "" ""))))]
254: ""
255: "*
256: {
257: CC_STATUS_INIT;
258: return \"bcnd ne0,%0,%l1\";
259: }")
260:
261: (define_insn ""
262: [(set (pc)
263: (if_then_else (ne (cc0)
264: (const_int 0))
265: (pc)
266: (label_ref (match_operand 0 "" ""))))]
267: ""
268: "bb0 ne,r25,%l0")
269:
270: (define_peephole
271: [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
272: (set (pc)
273: (if_then_else (ne (cc0)
274: (const_int 0))
275: (pc)
276: (label_ref (match_operand 1 "" ""))))]
277: ""
278: "*
279: {
280: CC_STATUS_INIT;
281: return \"bcnd eq0,%0,%l1\";
282: }")
283:
284: (define_insn ""
285: [(set (pc)
286: (if_then_else (gt (cc0)
287: (const_int 0))
288: (pc)
289: (label_ref (match_operand 0 "" ""))))]
290: ""
291: "bb0 gt,r25,%l0")
292:
293: (define_insn ""
294: [(set (pc)
295: (if_then_else (gtu (cc0)
296: (const_int 0))
297: (pc)
298: (label_ref (match_operand 0 "" ""))))]
299: ""
300: "bb0 hi,r25,%l0")
301:
302: (define_insn ""
303: [(set (pc)
304: (if_then_else (lt (cc0)
305: (const_int 0))
306: (pc)
307: (label_ref (match_operand 0 "" ""))))]
308: ""
309: "bb0 lt,r25,%l0")
310:
311: (define_insn ""
312: [(set (pc)
313: (if_then_else (ltu (cc0)
314: (const_int 0))
315: (pc)
316: (label_ref (match_operand 0 "" ""))))]
317: ""
318: "bb0 lo,r25,%l0")
319:
320: (define_insn ""
321: [(set (pc)
322: (if_then_else (ge (cc0)
323: (const_int 0))
324: (pc)
325: (label_ref (match_operand 0 "" ""))))]
326: ""
327: "bb0 ge,r25,%l0")
328:
329: (define_insn ""
330: [(set (pc)
331: (if_then_else (geu (cc0)
332: (const_int 0))
333: (pc)
334: (label_ref (match_operand 0 "" ""))))]
335: ""
336: "bb0 hs,r25,%l0")
337:
338: (define_insn ""
339: [(set (pc)
340: (if_then_else (le (cc0)
341: (const_int 0))
342: (pc)
343: (label_ref (match_operand 0 "" ""))))]
344: ""
345: "bb0 le,r25,%l0")
346:
347: (define_insn ""
348: [(set (pc)
349: (if_then_else (leu (cc0)
350: (const_int 0))
351: (pc)
352: (label_ref (match_operand 0 "" ""))))]
353: ""
354: "bb0 ls,r25,%l0")
355:
356: ;; Move instructions
357:
358: (define_insn "swapsi"
359: [(set (match_operand:SI 0 "general_operand" "g")
360: (match_operand:SI 1 "general_operand" "g"))
361: (set (match_dup 1) (match_dup 0))]
362: ""
363: "*
364: {
365: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
366: {
367: CC_STATUS_INIT;
368: return \"ld r25,%0\;xmem r25,%1\;st r25,%0\";
369: }
370: if (! REG_P (operands[1]))
371: return \"xmem %0,%1\";
372: if (REG_P (operands[0]))
373: {
374: if (REGNO (operands[0]) == REGNO (operands[1]))
375: return \"\";
376: return \"xor %0,%0,%1\;xor %1,%1,%0\;xor %0,%0,%1\";
377: }
378: return \"xmem %1,%0\";
379: }")
380:
381: (define_peephole
382: [(set (match_operand:SI 0 "register_operand" "=r")
383: (match_operand:SI 1 "memory_operand" "m"))
384: (set (match_operand:SI 2 "register_operand" "=r")
385: (match_operand:SI 3 "memory_operand" "m"))
386: (set (match_dup 1) (match_dup 2))
387: (set (match_dup 3) (match_dup 0))]
388: ""
389: "*
390: {
391: CC_STATUS_INIT;
392: return \"ld r25,%1\;xmem r25,%3\;st r25,%1\";
393: }")
394:
395: (define_insn "swapqi"
396: [(set (match_operand:QI 0 "general_operand" "g")
397: (match_operand:QI 1 "general_operand" "g"))
398: (set (match_dup 1) (match_dup 0))]
399: ""
400: "*
401: {
402: if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
403: {
404: CC_STATUS_INIT;
405: return \"ld.bu r25,%0\;xmem.bu r25,%1\;st.bu r25,%0\";
406: }
407: if (! REG_P (operands[1]))
408: return \"xmem.bu %0,%1\";
409: if (REG_P (operands[0]))
410: {
411: if (REGNO (operands[0]) == REGNO (operands[1]))
412: return \"\";
413: return \"xor %0,%0,%1\;xor %1,%1,%0\;xor %0,%0,%1\";
414: }
415: return \"xmem.bu %1,%0\";
416: }")
417:
418: (define_peephole
419: [(set (match_operand:QI 0 "register_operand" "=r")
420: (match_operand:QI 1 "memory_operand" "m"))
421: (set (match_operand:QI 2 "register_operand" "=r")
422: (match_operand:QI 3 "memory_operand" "m"))
423: (set (match_dup 1) (match_dup 2))
424: (set (match_dup 3) (match_dup 0))]
425: ""
426: "*
427: {
428: CC_STATUS_INIT;
429: return \"ld.bu r25,%1\;xmem.bu r25,%3\;st.bu r25,%1\";
430: }")
431:
432: (define_insn ""
433: [(set (match_operand:SI 0 "general_operand" "g")
434: (const_int 0))]
435: ""
436: "*
437: {
438: if (REG_P (operands[0]))
439: return \"or %0,r0,0\";
440: return \"st r0,%0\";
441: }")
442:
443: (define_insn "movsi"
444: [(set (match_operand:SI 0 "general_operand" "=g,r")
445: (match_operand:SI 1 "general_operand" "r,mi"))]
446: ""
447: "*
448: {
449: if (REG_P (operands[0]))
450: {
451: if (GET_CODE (operands[1]) == MEM)
452: return \"ld %0,%1\";
453: if (GET_CODE (operands[1]) == CONST_INT)
454: return output_store_const_int (SImode, operands);
455: if (GET_CODE (operands[1]) == LABEL_REF
456: || GET_CODE (operands[1]) == SYMBOL_REF)
457: return \"lda %0,r0,%1\";
458: return \"or %0,r0,%1\";
459: }
460: return \"st %1,%0\";
461: }")
462:
463: ;; Simulate pre inc. Post inc/dec is automatically optimized
464: ;; by sheer luck. ?? In which phase should this really be done??
465: (define_insn ""
466: [(set (match_operand:SI 0 "register_operand" "r")
467: (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
468: (match_operand:SI 2 "arith_operand" "rI"))))
469: (set (match_dup 1)
470: (plus:SI (match_dup 1)
471: (match_dup 2)))]
472: ""
473: "ld %0,%1,%2\\t;; pipelined!\;addu %1,%1,%2\\t;; /")
474:
475: (define_insn ""
476: [(set (mem:SI (plus:SI (match_operand:SI 0 "register_operand" "r")
477: (match_operand:SI 1 "arith_operand" "rI")))
478: (match_operand:SI 2 "register_operand" "r"))
479: (set (match_dup 0)
480: (plus:SI (match_dup 0)
481: (match_dup 1)))]
482: ""
483: "st %2,%0,%1\\t;; pipelined!\;addu %0,%0,%1\\t;; /")
484:
485: (define_insn ""
486: [(set (match_operand:HI 0 "general_operand" "g")
487: (const_int 0))]
488: ""
489: "*
490: {
491: if (REG_P (operands[0]))
492: return \"or %0,r0,0\";
493: return \"st.h r0,%0\";
494: }")
495:
496: (define_insn "movhi"
497: [(set (match_operand:HI 0 "general_operand" "=g,r")
498: (match_operand:HI 1 "general_operand" "r,mn"))]
499: ""
500: "*
501: {
502: if (REG_P (operands[0]))
503: {
504: if (GET_CODE (operands[1]) == MEM)
505: return \"ld.h %0,%1\";
506: if (GET_CODE (operands[1]) == CONST_INT)
507: return output_store_const_int (HImode, operands);
508: return \"or %0,r0,%1\";
509: }
510: return \"st.h %1,%0\";
511: }")
512:
513: (define_insn ""
514: [(set (match_operand:SI 0 "register_operand" "r")
515: (sign_extend:SI
516: (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
517: (match_operand:SI 2 "arith_operand" "rI")))))
518: (set (match_dup 1)
519: (plus:SI (match_dup 1)
520: (match_dup 2)))]
521: ""
522: "ld.h %0,%1,%2\\t;; pipelined!\;addu %1,%1,%2\\t;; /")
523:
524: (define_insn ""
525: [(set (match_operand:SI 0 "register_operand" "r")
526: (zero_extend:SI
527: (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "r")
528: (match_operand:SI 2 "arith_operand" "rI")))))
529: (set (match_dup 1)
530: (plus:SI (match_dup 1)
531: (match_dup 2)))]
532: ""
533: "ld.hu %0,%1,%2\\t;; pipelined!\;addu %1,%1,%2\\t;; /")
534:
535: (define_insn ""
536: [(set (mem:HI (plus:SI (match_operand:SI 0 "register_operand" "r")
537: (match_operand:SI 1 "arith_operand" "rI")))
538: (match_operand:SI 2 "register_operand" "r"))
539: (set (match_dup 0)
540: (plus:SI (match_dup 0)
541: (match_dup 1)))]
542: ""
543: "st.h %2,%0,%1\\t;; pipelined!\;addu %0,%0,%1\\t;; /")
544:
545: (define_insn ""
546: [(set (match_operand:QI 0 "general_operand" "g")
547: (const_int 0))]
548: ""
549: "*
550: {
551: if (REG_P (operands[0]))
552: return \"or %0,r0,0\";
553: return \"st.b r0,%0\";
554: }")
555:
556: (define_insn "movqi"
557: [(set (match_operand:QI 0 "general_operand" "=g,r")
558: (match_operand:QI 1 "general_operand" "r,mn"))]
559: ""
560: "*
561: {
562: if (REG_P (operands[0]))
563: {
564: if (GET_CODE (operands[1]) == MEM)
565: return \"ld.b %0,%1\";
566: if (GET_CODE (operands[1]) == CONST_INT)
567: return output_store_const_int (QImode, operands);
568: return \"or %0,r0,%1\";
569: }
570: return \"st.b %1,%0\";
571: }")
572:
573: (define_insn ""
574: [(set (match_operand:SI 0 "register_operand" "r")
575: (sign_extend:SI
576: (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
577: (match_operand:SI 2 "arith_operand" "rI")))))
578: (set (match_dup 1)
579: (plus:SI (match_dup 1)
580: (match_dup 2)))]
581: ""
582: "ld.b %0,%1,%2\\t;; pipelined!\;addu %1,%1,%2\\t;; /")
583:
584: (define_insn ""
585: [(set (match_operand:SI 0 "register_operand" "r")
586: (zero_extend:SI
587: (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "r")
588: (match_operand:SI 2 "arith_operand" "rI")))))
589: (set (match_dup 1)
590: (plus:SI (match_dup 1)
591: (match_dup 2)))]
592: ""
593: "ld.bu %0,%1,%2\\t;; pipelined!\;addu %1,%1,%2\\t;; /")
594:
595: (define_insn ""
596: [(set (mem:QI (plus:SI (match_operand:SI 0 "register_operand" "r")
597: (match_operand:SI 1 "arith_operand" "rI")))
598: (match_operand:SI 2 "register_operand" "r"))
599: (set (match_dup 0)
600: (plus:SI (match_dup 0)
601: (match_dup 1)))]
602: ""
603: "st.b %2,%0,%1\\t;; pipelined!\;addu %0,%0,%1\\t;; /")
604:
605: ;; The definition of this insn does not really explain what it does,
606: ;; but it should suffice
607: ;; that anything generated as this insn will be recognized as one
608: ;; and that it won't successfully combine with anything.
609: (define_insn "movstrsi"
610: [(set (match_operand:BLK 0 "general_operand" "=g")
611: (match_operand:BLK 1 "general_operand" "g"))
612: (use (match_operand:SI 2 "arith32_operand" "rn"))
613: (clobber (reg:SI 10))
614: (clobber (reg:SI 11))
615: (clobber (reg:SI 12))]
616: ""
617: "* output_block_move (operands);")
618:
619: ;; This pattern forces (set (reg:DF ...) (const_double ...))
620: ;; to be reloaded by putting the constant into memory.
621: ;; It must come before the more general movdf pattern.
622: (define_insn ""
623: [(set (match_operand:DF 0 "general_operand" "=r,o")
624: (match_operand:DF 1 "" "mG,G"))]
625: "GET_CODE (operands[1]) == CONST_DOUBLE"
626: "*
627: {
628: if (operands[1] == dconst0_rtx && GET_CODE (operands[0]) == REG)
629: {
630: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
631: return \"add %0,r0,0\;add %1,r0,0\";
632: }
633: if (operands[1] == dconst0_rtx && GET_CODE (operands[0]) == MEM)
634: {
635: operands[1] = adj_offsettable_operand (operands[0], 4);
636: return \"st r0,%0\;st r0,%1\";
637: }
638: return output_move_double (operands);
639: }
640: ")
641:
642: (define_insn "movdf"
643: [(set (match_operand:DF 0 "general_operand" "=r,m")
644: (match_operand:DF 1 "general_operand" "rm,r"))]
645: ""
646: "* return output_move_double (operands);")
647:
648: (define_insn "movdi"
649: [(set (match_operand:DI 0 "general_operand" "=r,m")
650: (match_operand:DI 1 "general_operand" "rm,r"))]
651: ""
652: "* return output_move_double (operands);")
653:
654: (define_insn "movsf"
655: [(set (match_operand:SF 0 "general_operand" "=g,r")
656: (match_operand:SF 1 "general_operand" "r,mF"))]
657: ""
658: "*
659: {
660: if (REG_P (operands[0]))
661: {
662: if (GET_CODE (operands[1]) == MEM)
663: return \"ld %0,%1\";
664: if (GET_CODE (operands[1]) == CONST_DOUBLE)
665: return output_store_const_float (SFmode, operands);
666: return \"or %0,r0,%1\";
667: }
668: return \"st %1,%0\";
669: }")
670:
671: ;;- load effective address
672: (define_insn ""
673: [(set (match_operand:SI 0 "register_operand" "=r")
674: (match_operand:QI 1 "address_operand" "p"))]
675: ""
676: "lda.b %0,%a1")
677:
678: (define_insn ""
679: [(set (match_operand:SI 0 "register_operand" "=r")
680: (match_operand:HI 1 "address_operand" "p"))]
681: ""
682: "lda.w %0,%a1")
683:
684: (define_insn ""
685: [(set (match_operand:SI 0 "register_operand" "=r")
686: (match_operand:SI 1 "address_operand" "p"))]
687: ""
688: "lda %0,%a1")
689:
690: (define_insn ""
691: [(set (match_operand:SI 0 "register_operand" "=r")
692: (match_operand:DI 1 "address_operand" "p"))]
693: ""
694: "lda.d %0,%a1")
695:
696: (define_insn ""
697: [(set (match_operand:SI 0 "register_operand" "=r")
698: (match_operand:SF 1 "address_operand" "p"))]
699: ""
700: "lda %0,%a1")
701:
702: (define_insn ""
703: [(set (match_operand:SI 0 "register_operand" "=r")
704: (match_operand:DF 1 "address_operand" "p"))]
705: ""
706: "lda.d %0,%a1")
707:
708: ;;- truncation instructions
709: (define_insn "truncsiqi2"
710: [(set (match_operand:QI 0 "general_operand" "=g")
711: (truncate:QI
712: (match_operand:SI 1 "register_operand" "r")))]
713: ""
714: "*
715: {
716: if (GET_CODE (operands[0]) == MEM)
717: return \"st.b %1,%0\";
718: return \"or %0,r0,%1\";
719: }")
720:
721: (define_insn "trunchiqi2"
722: [(set (match_operand:QI 0 "general_operand" "=g")
723: (truncate:QI
724: (match_operand:HI 1 "register_operand" "r")))]
725: ""
726: "*
727: {
728: if (GET_CODE (operands[0]) == MEM)
729: return \"st.b %1,%0\";
730: return \"or %0,r0,%1\";
731: }")
732:
733: (define_insn "truncsihi2"
734: [(set (match_operand:HI 0 "general_operand" "=g")
735: (truncate:HI
736: (match_operand:SI 1 "register_operand" "r")))]
737: ""
738: "*
739: {
740: if (GET_CODE (operands[0]) == MEM)
741: return \"st.h %1,%0\";
742: return \"or %0,r0,%1\";
743: }")
744:
745: ;;- zero extension instructions
746:
747: ;; Note that the one starting from HImode comes before those for QImode
748: ;; so that a constant operand will match HImode, not QImode.
749:
750: (define_insn "zero_extendhisi2"
751: [(set (match_operand:SI 0 "register_operand" "=r")
752: (zero_extend:SI
753: (match_operand:HI 1 "general_operand" "g")))]
754: ""
755: "*
756: {
757: if (REG_P (operands[1]))
758: return \"mask %0,%1,0xffff\";
759: if (GET_CODE (operands[1]) == CONST_INT)
760: return output_store_const_int (SImode, operands);
761: return \"ld.hu %0,%1\";
762: }")
763:
764: (define_insn "zero_extendqihi2"
765: [(set (match_operand:HI 0 "register_operand" "=r")
766: (zero_extend:HI
767: (match_operand:QI 1 "general_operand" "g")))]
768: ""
769: "*
770: {
771: if (REG_P (operands[1]))
772: return \"mask %0,%1,0xff\";
773: if (GET_CODE (operands[1]) == CONST_INT)
774: return output_store_const_int (SImode, operands);
775: return \"ld.bu %0,%1\";
776: }")
777:
778: (define_insn "zero_extendqisi2"
779: [(set (match_operand:SI 0 "register_operand" "=r")
780: (zero_extend:SI
781: (match_operand:QI 1 "general_operand" "g")))]
782: ""
783: "*
784: {
785: if (REG_P (operands[1]))
786: return \"mask %0,%1,0xff\";
787: if (GET_CODE (operands[1]) == CONST_INT)
788: return output_store_const_int (SImode, operands);
789: return \"ld.bu %0,%1\";
790: }")
791:
792: ;;- sign extension instructions
793: ;; Note that the one starting from HImode comes before those for QImode
794: ;; so that a constant operand will match HImode, not QImode.
795:
796: (define_insn "extendhisi2"
797: [(set (match_operand:SI 0 "register_operand" "=r")
798: (sign_extend:SI
799: (match_operand:HI 1 "general_operand" "g")))]
800: ""
801: "*
802: {
803: if (REG_P (operands[1]))
804: return \"ext %0,%1,16<0>\";
805: if (GET_CODE (operands[1]) == CONST_INT)
806: return output_store_const_int (SImode, operands);
807: return \"ld.h %0,%1\";
808: }")
809:
810: (define_insn "extendqihi2"
811: [(set (match_operand:HI 0 "register_operand" "=r")
812: (sign_extend:HI
813: (match_operand:QI 1 "general_operand" "g")))]
814: ""
815: "*
816: {
817: if (REG_P (operands[1]))
818: return \"ext %0,%1,8<0>\";
819: if (GET_CODE (operands[1]) == CONST_INT)
820: return output_store_const_int (SImode, operands);
821: return \"ld.b %0,%1\";
822: }")
823:
824: (define_insn "extendqisi2"
825: [(set (match_operand:SI 0 "register_operand" "=r")
826: (sign_extend:SI
827: (match_operand:QI 1 "general_operand" "g")))]
828: ""
829: "*
830: {
831: if (REG_P (operands[1]))
832: return \"ext %0,%1,8<0>\";
833: if (GET_CODE (operands[1]) == CONST_INT)
834: return output_store_const_int (SImode, operands);
835: return \"ld.b %0,%1\";
836: }")
837:
838: ;; Conversions between float and double.
839:
840: (define_insn "extendsfdf2"
841: [(set (match_operand:DF 0 "general_operand" "=r")
842: (float_extend:DF
843: (match_operand:SF 1 "general_operand" "r")))]
844: ""
845: "fadd.dss %0,r0,%1")
846:
847: (define_insn "truncdfsf2"
848: [(set (match_operand:SF 0 "general_operand" "=r")
849: (float_truncate:SF
850: (match_operand:DF 1 "general_operand" "r")))]
851: ""
852: "fadd.ssd %0,r0,%1")
853: ;; Conversions between floating point and integer
854:
855: (define_insn "floatsidf2"
856: [(set (match_operand:DF 0 "general_operand" "=r")
857: (float:DF (match_operand:SI 1 "general_operand" "r")))]
858: ""
859: "flt.ds %0,%1")
860:
861: (define_insn "floatsisf2"
862: [(set (match_operand:SF 0 "general_operand" "=r")
863: (float:SF (match_operand:SI 1 "general_operand" "r")))]
864: ""
865: "flt.ss %0,%1")
866:
867: (define_insn "fixdfsi2"
868: [(set (match_operand:SI 0 "general_operand" "=r")
869: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "r"))))]
870: ""
871: "int.sd %0,%1")
872:
873: (define_insn "fixsfsi2"
874: [(set (match_operand:SI 0 "general_operand" "=r")
875: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "r"))))]
876: ""
877: "int.ss %0,%1")
878:
879: ;;- arithmetic instructions
880: ;;- add instructions
881: (define_insn "addsi3"
882: [(set (match_operand:SI 0 "register_operand" "=r")
883: (plus:SI (match_operand:SI 1 "arith32_operand" "%r")
884: (match_operand:SI 2 "arith32_operand" "rn")))]
885: ""
886: "*
887: {
888: unsigned int i;
889:
890: if (REG_P (operands[2]))
891: return \"addu %0,%1,%2\";
892: i = INTVAL (operands[2]);
893: if (INT_FITS_16_BITS (i))
894: return \"addu %0,%1,%2\";
895: if (INT_FITS_16_BITS (-i))
896: {
897: operands[2] = gen_rtx (CONST_INT, VOIDmode, -i);
898: return \"subu %0,%1,%2\";
899: }
900: return \"or.u %0,r0,hi16(%2)\;or %0,%0,lo16(%2)\;addu %0,%1,%0\";
901: }")
902:
903: (define_insn "adddf3"
904: [(set (match_operand:DF 0 "register_operand" "=r")
905: (plus:DF (match_operand:DF 1 "register_operand" "%r")
906: (match_operand:DF 2 "register_operand" "r")))]
907: ""
908: "fadd.ddd %0,%1,%2")
909:
910: ;; a bunch more can go in here!
911:
912: (define_insn "addsf3"
913: [(set (match_operand:SF 0 "register_operand" "=r")
914: (plus:SF (match_operand:SF 1 "register_operand" "%r")
915: (match_operand:SF 2 "register_operand" "r")))]
916: ""
917: "fadd.sss %0,%1,%2")
918:
919: ;;- subtract instructions
920: (define_insn "subsi3"
921: [(set (match_operand:SI 0 "register_operand" "=r")
922: (minus:SI (match_operand:SI 1 "register_operand" "r")
923: (match_operand:SI 2 "arith32_operand" "rn")))]
924: ""
925: "*
926: {
927: unsigned int i;
928:
929: if (REG_P (operands[2]))
930: return \"subu %0,%1,%2\";
931: i = INTVAL (operands[2]);
932: if (INT_FITS_16_BITS (i))
933: return \"subu %0,%1,%2\";
934: if (INT_FITS_16_BITS (-i))
935: {
936: operands[2] = gen_rtx (CONST_INT, VOIDmode, -i);
937: return \"addu %0,%1,%2\";
938: }
939: return \"or.u %0,r0,hi16(%2)\;or %0,%0,lo16(%2)\;subu %0,%1,%0\";
940: }")
941:
942: (define_insn "subdf3"
943: [(set (match_operand:DF 0 "register_operand" "=r")
944: (minus:DF (match_operand:DF 1 "register_operand" "%r")
945: (match_operand:DF 2 "register_operand" "r")))]
946: ""
947: "fsub.ddd %0,%1,%2")
948:
949: (define_insn "subsf3"
950: [(set (match_operand:SF 0 "register_operand" "=r")
951: (minus:SF (match_operand:SF 1 "register_operand" "%r")
952: (match_operand:SF 2 "register_operand" "r")))]
953: ""
954: "fsub.sss %0,%1,%2")
955:
956: ;;- multiply instructions
957: (define_insn "mulsi3"
958: [(set (match_operand:SI 0 "register_operand" "=r")
959: (mult:SI (match_operand:SI 1 "register_operand" "%r")
960: (match_operand:SI 2 "arith32_operand" "rn")))]
961: ""
962: "*
963: {
964: unsigned int i;
965:
966: if (REG_P (operands[2]))
967: return \"mul %0,%1,%2\";
968: i = INTVAL (operands[2]);
969: if (INT_FITS_16_BITS (i))
970: return \"mul %0,%1,%2\";
971: return \"or.u %0,r0,hi16(%2)\;or %0,%0,lo16(%2)\;mul %0,%1,%0\";
972: }")
973:
974: (define_insn "umulsi3"
975: [(set (match_operand:SI 0 "register_operand" "=r")
976: (umult:SI (match_operand:SI 1 "register_operand" "%r")
977: (match_operand:SI 2 "arith_operand" "rI")))]
978: ""
979: "mul %0,%1,%2")
980:
981: (define_insn "muldf3"
982: [(set (match_operand:DF 0 "register_operand" "=r")
983: (mult:DF (match_operand:DF 1 "register_operand" "%r")
984: (match_operand:DF 2 "register_operand" "r")))]
985: ""
986: "fmul.ddd %0,%1,%2")
987:
988: (define_insn "mulsf3"
989: [(set (match_operand:SF 0 "register_operand" "=r")
990: (mult:SF (match_operand:SF 1 "register_operand" "%r")
991: (match_operand:SF 2 "register_operand" "r")))]
992: ""
993: "fmul.sss %0,%1,%2")
994:
995: ;;- divide instructions
996: (define_insn "divsi3"
997: [(set (match_operand:SI 0 "register_operand" "=r")
998: (div:SI (match_operand:SI 1 "register_operand" "r")
999: (match_operand:SI 2 "arith32_operand" "rn")))]
1000: ""
1001: "*
1002: {
1003: unsigned int i;
1004:
1005: if (REG_P (operands[2]))
1006: return \"div %0,%1,%2\";
1007: i = INTVAL (operands[2]);
1008: if (INT_FITS_16_BITS (i))
1009: return \"div %0,%1,%2\";
1010: return \"or.u %0,r0,hi16(%2)\;or %0,%0,lo16(%2)\;div %0,%1,%0\";
1011: }")
1012:
1013:
1014: (define_insn "udivsi3"
1015: [(set (match_operand:SI 0 "register_operand" "=r")
1016: (udiv:SI (match_operand:SI 1 "register_operand" "r")
1017: (match_operand:SI 2 "arith_operand" "rI")))]
1018: ""
1019: "div %0,%1,%2")
1020:
1021: (define_insn "divdf3"
1022: [(set (match_operand:DF 0 "register_operand" "=r")
1023: (div:DF (match_operand:DF 1 "register_operand" "r")
1024: (match_operand:DF 2 "register_operand" "r")))]
1025: ""
1026: "fdiv.ddd %0,%1,%2")
1027:
1028: (define_insn "divsf3"
1029: [(set (match_operand:SF 0 "register_operand" "=r")
1030: (div:SF (match_operand:SF 1 "register_operand" "r")
1031: (match_operand:SF 2 "register_operand" "r")))]
1032: ""
1033: "fdiv.sss %0,%1,%2")
1034:
1035: ;; Remainder instructions.
1036:
1037: (define_insn "modsi3"
1038: [(set (match_operand:SI 0 "register_operand" "=r")
1039: (mod:SI (match_operand:SI 1 "register_operand" "r")
1040: (match_operand:SI 2 "arith32_operand" "rn")))]
1041: ""
1042: "*
1043: {
1044: unsigned int i;
1045:
1046: if (REG_P (operands[2]))
1047: return \"div %0,%1,%2\;mul %0,%0,%2\;sub %0,%1,%0\";
1048: i = INTVAL (operands[2]);
1049: if (INT_FITS_16_BITS (i))
1050: return \"div %0,%1,%2\;mul %0,%0,%2\;sub %0,%1,%0\";
1051: if (INT_FITS_16_BITS (-i))
1052: fatal (\"implement negative case for mod\");
1053: fatal (\"implement 32 bit case for mod\");
1054: }")
1055:
1056: (define_insn "umodsi3"
1057: [(set (match_operand:SI 0 "register_operand" "=r")
1058: (umod:SI (match_operand:SI 1 "register_operand" "r")
1059: (match_operand:SI 2 "arith_operand" "rI")))]
1060: ""
1061: "*
1062: {
1063: unsigned int i;
1064:
1065: if (REG_P (operands[2]))
1066: return \"div %0,%1,%2\;mul %0,%0,%2\;sub %0,%1,%0\";
1067: i = INTVAL (operands[2]);
1068: if (INT_FITS_16_BITS (i))
1069: return \"div %0,%1,%2\;mul %0,%0,%2\;sub %0,%1,%0\";
1070: if (INT_FITS_16_BITS (-i))
1071: fatal (\"implement negative case for umod\");
1072: fatal (\"implement 32 bit case for umod\");
1073: }")
1074:
1075: (define_insn "divmodsi4"
1076: [(set (match_operand:SI 0 "register_operand" "=r")
1077: (div:SI (match_operand:SI 1 "register_operand" "r")
1078: (match_operand:SI 2 "arith_operand" "rI")))
1079: (set (match_operand:SI 3 "register_operand" "=r")
1080: (mod:SI (match_dup 1) (match_dup 2)))]
1081: ""
1082: "div %0,%1,%2\;mul %3,%0,%2\;sub %3,%1,%3")
1083:
1084: (define_insn "udivmodsi4"
1085: [(set (match_operand:SI 0 "register_operand" "=r")
1086: (udiv:SI (match_operand:SI 1 "register_operand" "r")
1087: (match_operand:SI 2 "arith_operand" "rI")))
1088: (set (match_operand:SI 3 "register_operand" "=r")
1089: (umod:SI (match_dup 1) (match_dup 2)))]
1090: ""
1091: "div %0,%1,%2\;mul %3,%0,%2\;sub %3,%1,%3")
1092:
1093: ;;- and instructions (with complement also)
1094: (define_insn "andsi3"
1095: [(set (match_operand:SI 0 "register_operand" "=r")
1096: (and:SI (match_operand:SI 1 "register_operand" "%r")
1097: (match_operand:SI 2 "arith32_operand" "rn")))]
1098: ""
1099: "*
1100: {
1101: unsigned int i;
1102:
1103: if (REG_P (operands[2]))
1104: return \"and %0,%1,%2\";
1105: i = INTVAL (operands[2]);
1106: if (INT_FITS_16_BITS (i))
1107: return \"mask %0,%1,%2\";
1108: if (INT_FITS_16_BITS (-i))
1109: {
1110: operands[2] = gen_rtx (CONST_INT, VOIDmode, i & 0xffff);
1111: return \"and %0,%1,%2\";
1112: }
1113: return \"and.u %0,%1,hi16(%2)\;and %0,%1,lo16(%2)\";
1114: }")
1115:
1116: (define_insn "andcbsi3"
1117: [(set (match_operand:SI 0 "register_operand" "=r")
1118: (and:SI (match_operand:SI 1 "register_operand" "%r")
1119: (not:SI (match_operand:SI 2 "register_operand" "r"))))]
1120: ""
1121: "and.c %0,%1,%2")
1122:
1123: ;;- Bit set (inclusive or) instructions (with complement also)
1124: (define_insn "iorsi3"
1125: [(set (match_operand:SI 0 "register_operand" "=r")
1126: (ior:SI (match_operand:SI 1 "register_operand" "%r")
1127: (match_operand:SI 2 "arith32_operand" "rn")))]
1128: ""
1129: "*
1130: {
1131: unsigned int i;
1132:
1133: if (REG_P (operands[2]))
1134: return \"or %0,%1,%2\";
1135: i = INTVAL (operands[2]);
1136: if (INT_FITS_16_BITS (i))
1137: return \"or %0,%1,%2\";
1138: return \"or.u %0,%1,hi16(%2)\;or %0,%1,lo16(%2)\";
1139: }")
1140:
1141: (define_insn "iorcbsi3"
1142: [(set (match_operand:SI 0 "register_operand" "=r")
1143: (ior:SI (match_operand:SI 1 "register_operand" "%r")
1144: (not:SI (match_operand:SI 2 "register_operand" "r"))))]
1145: ""
1146: "or.c %0,%1,%2")
1147:
1148: ;;- xor instructions (with complement also)
1149: (define_insn "xorsi3"
1150: [(set (match_operand:SI 0 "register_operand" "=r")
1151: (xor:SI (match_operand:SI 1 "register_operand" "%r")
1152: (match_operand:SI 2 "arith32_operand" "rn")))]
1153: ""
1154: "*
1155: {
1156: unsigned int i;
1157:
1158: if (REG_P (operands[2]))
1159: return \"xor %0,%1,%2\";
1160: i = INTVAL (operands[2]);
1161: if (INT_FITS_16_BITS (i))
1162: return \"xor %0,%1,%2\";
1163: if ((i & 0xffff) == 0)
1164: return \"xor.u %0,%1,hi16(%2)\";
1165: return \"xor.u %0,%1,hi16(%2)\;xor %0,%1,lo16(%2)\";
1166: }")
1167:
1168: (define_insn "xorcbsi3"
1169: [(set (match_operand:SI 0 "register_operand" "=r")
1170: (xor:SI (match_operand:SI 1 "register_operand" "%r")
1171: (not:SI (match_operand:SI 2 "register_operand" "r"))))]
1172: ""
1173: "xor.c %0,%1,%2")
1174:
1175: ;;- one complement instructions
1176: (define_insn "one_cmplsi2"
1177: [(set (match_operand:SI 0 "register_operand" "=r")
1178: (not:SI (match_operand:SI 1 "register_operand" "r")))]
1179: ""
1180: "xor.c %0,%1,r0")
1181:
1182: ;; Optimized special case of shifting.
1183: ;; Must precede the general case.
1184:
1185: (define_insn ""
1186: [(set (match_operand:SI 0 "register_operand" "=r")
1187: (ashiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1188: (const_int 24)))]
1189: ""
1190: "ld.b %0,%1")
1191:
1192: (define_insn ""
1193: [(set (match_operand:SI 0 "register_operand" "=r")
1194: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1195: (const_int 24)))]
1196: ""
1197: "ld.bu %0,%1")
1198:
1199: ;;- arithmetic shift instructions
1200: (define_insn "ashlsi3"
1201: [(set (match_operand:SI 0 "register_operand" "=r")
1202: (ashift:SI (match_operand:SI 1 "register_operand" "r")
1203: (match_operand:SI 2 "arith_operand" "rI")))]
1204: ""
1205: "*
1206: {
1207: if (GET_CODE (operands[2]) == CONST_INT)
1208: return \"mak %0,%1,0<%2>\";
1209: return \"mask %0,%2,0x1f\;mak %0,%1,%0\";
1210: }")
1211:
1212: (define_insn "ashrsi3"
1213: [(set (match_operand:SI 0 "register_operand" "=r")
1214: (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
1215: (match_operand:SI 2 "arith_operand" "rI")))]
1216: ""
1217: "*
1218: {
1219: if (GET_CODE (operands[2]) == CONST_INT)
1220: return \"ext %0,%1,0<%2>\";
1221: return \"mask %0,%2,0x1f\;ext %0,%1,%0\";
1222: }")
1223:
1224: ;;- logical shift instructions
1225: (define_insn "lshrsi3"
1226: [(set (match_operand:SI 0 "register_operand" "=r")
1227: (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
1228: (match_operand:SI 2 "arith_operand" "rI")))]
1229: ""
1230: "*
1231: {
1232: if (GET_CODE (operands[2]) == CONST_INT)
1233: return \"extu %0,%1,0<%2>\";
1234: return \"mask %0,%2,0x1f\;extu %0,%1,%0\";
1235: }")
1236:
1237: ;;- rotate instructions
1238:
1239: (define_insn "rotlsi3"
1240: [(set (match_operand:SI 0 "register_operand" "=r")
1241: (rotate:SI (match_operand:SI 1 "register_operand" "r")
1242: (match_operand:SI 2 "arith_operand" "rI")))]
1243: ""
1244: "*
1245: {
1246: if (GET_CODE (operands[2]) == CONST_INT)
1247: {
1248: operands[2] = gen_rtx (CONST_INT, SImode, 32 - INTVAL (operands[2]));
1249: return \"rot %0,%1,%2\";
1250: }
1251: return \"or %0,r0,32\;sub %0,%2,%0\;rot %0,%1,%0\";
1252: }")
1253:
1254: (define_insn "rotrsi3"
1255: [(set (match_operand:SI 0 "register_operand" "=r")
1256: (rotatert:SI (match_operand:SI 1 "register_operand" "r")
1257: (match_operand:SI 2 "arith_operand" "rI")))]
1258: ""
1259: "rot %0,%1,%2")
1260:
1261: ;; Special cases of bit-field insns which we should
1262: ;; recognize in preference to the general case.
1263: ;; These handle aligned 8-bit and 16-bit fields,
1264: ;; which can usually be done with move instructions.
1265:
1266: (define_insn ""
1267: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+ro")
1268: (match_operand:SI 1 "int5_operand" "K")
1269: (match_operand:SI 2 "int5_operand" "K"))
1270: (match_operand:SI 3 "register_operand" "r"))]
1271: "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
1272: && INTVAL (operands[2]) % INTVAL (operands[1]) == 0"
1273: "*
1274: {
1275: if (REG_P (operands[0]))
1276: {
1277: if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
1278: return \"mak %0,%3,%1<%2>\";
1279: }
1280: else
1281: operands[0]
1282: = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
1283:
1284: if (GET_CODE (operands[3]) == MEM)
1285: operands[3] = adj_offsettable_operand (operands[3],
1286: (32 - INTVAL (operands[1])) / 8);
1287: if (INTVAL (operands[1]) == 8)
1288: return \"st.b %3,%0\";
1289: return \"st.w %3,%0\";
1290: }")
1291:
1292: (define_insn ""
1293: [(set (match_operand:SI 0 "register_operand" "=&r")
1294: (zero_extract:SI (match_operand:SI 1 "general_operand" "ro")
1295: (match_operand:SI 2 "int5_operand" "K")
1296: (match_operand:SI 3 "int5_operand" "K")))]
1297: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1298: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
1299: "*
1300: {
1301: if (REG_P (operands[1]))
1302: {
1303: if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
1304: return \"extu %0,%1,%2<%3>\";
1305: }
1306: else
1307: operands[1]
1308: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
1309:
1310: if (GET_CODE (operands[0]) == MEM)
1311: operands[0] = adj_offsettable_operand (operands[0],
1312: (32 - INTVAL (operands[1])) / 8);
1313: if (INTVAL (operands[2]) == 8)
1314: return \"ld.bu %0,%1\";
1315: return \"ld.hu %0,%1\";
1316: }")
1317:
1318: (define_insn ""
1319: [(set (match_operand:SI 0 "register_operand" "=r")
1320: (sign_extract:SI (match_operand:SI 1 "general_operand" "ro")
1321: (match_operand:SI 2 "int5_operand" "K")
1322: (match_operand:SI 3 "int5_operand" "K")))]
1323: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1324: && INTVAL (operands[3]) % INTVAL (operands[2]) == 0"
1325: "*
1326: {
1327: if (REG_P (operands[1]))
1328: {
1329: if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
1330: return \"extu %0,%1,%2<%3>\";
1331: }
1332: else
1333: operands[1]
1334: = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
1335:
1336: if (INTVAL (operands[2]) == 8)
1337: return \"ld.b %0,%1\";
1338: return \"ld.h %0,%1\";
1339: }")
1340:
1341: ;; Bit field instructions.
1342:
1343: (define_insn "extv"
1344: [(set (match_operand:SI 0 "register_operand" "=r,r")
1345: (sign_extract:SI (match_operand:QI 1 "register_operand" "r,r")
1346: (match_operand:SI 2 "arith_operand" "K,rK")
1347: (match_operand:SI 3 "arith_operand" "K,&r")))]
1348: ""
1349: "*
1350: {
1351: if (GET_CODE (operands[3]) == CONST_INT)
1352: return \"ext %0,%1,%2<%3>\";
1353: if (GET_CODE (operands[2]) == CONST_INT)
1354: {
1355: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1356: (INTVAL (operands[2]) & 0x1f) << 5);
1357: return \"mask %3,%3,0x1f\;or %3,%3,%2\;ext %0,%1,%3\";
1358: }
1359: return \"mak %0,%2,5<5>\;mask %3,%3,0x1f\;or %3,%3,%0\;ext %0,%1,%3\";
1360: }")
1361:
1362: (define_insn ""
1363: [(set (match_operand:SI 0 "register_operand" "=r,r")
1364: (sign_extract:SI (match_operand:SI 1 "register_operand" "r,r")
1365: (match_operand:SI 2 "arith_operand" "K,rK")
1366: (match_operand:SI 3 "arith_operand" "K,&r")))]
1367: ""
1368: "*
1369: {
1370: if (GET_CODE (operands[3]) == CONST_INT)
1371: return \"ext %0,%1,%2<%3>\";
1372: if (GET_CODE (operands[2]) == CONST_INT)
1373: {
1374: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1375: (INTVAL (operands[2]) & 0x1f) << 5);
1376: return \"mask %3,%3,0x1f\;or %3,%3,%2\;ext %0,%1,%3\";
1377: }
1378: return \"mak %0,%2,5<5>\;mask %3,%3,0x1f\;or %3,%3,%0\;ext %0,%1,%3\";
1379: }")
1380:
1381: (define_insn "extzv"
1382: [(set (match_operand:SI 0 "register_operand" "=r,r")
1383: (zero_extract:SI (match_operand:QI 1 "register_operand" "r,r")
1384: (match_operand:SI 2 "arith_operand" "K,Kr")
1385: (match_operand:SI 3 "arith_operand" "K,&r")))]
1386: ""
1387: "*
1388: {
1389: if (GET_CODE (operands[3]) == CONST_INT)
1390: return \"extu %0,%1,%2<%3>\";
1391: if (GET_CODE (operands[2]) == CONST_INT)
1392: {
1393: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1394: (INTVAL (operands[2]) & 0x1f) << 5);
1395: return \"mask %3,%3,0x1f\;or %3,%3,%2\;extu %0,%1,%3\";
1396: }
1397: return \"mak %0,%2,5<5>\;mask %3,%3,0x1f\;or %3,%3,%0\;ext %0,%1,%3\";
1398: }")
1399:
1400: (define_insn ""
1401: [(set (match_operand:SI 0 "register_operand" "=r,r")
1402: (zero_extract:SI (match_operand:SI 1 "register_operand" "r,r")
1403: (match_operand:SI 2 "arith_operand" "K,Kr")
1404: (match_operand:SI 3 "arith_operand" "K,&r")))]
1405: ""
1406: "*
1407: {
1408: if (GET_CODE (operands[3]) == CONST_INT)
1409: return \"extu %0,%1,%2<%3>\";
1410: if (GET_CODE (operands[2]) == CONST_INT)
1411: {
1412: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1413: (INTVAL (operands[2]) & 0x1f) << 5);
1414: return \"mask %3,%3,0x1f\;or %3,%3,%2\;extu %0,%1,%3\";
1415: }
1416: return \"mak %0,%2,5<5>\;mask %3,%3,0x1f\;or %3,%3,%0\;ext %0,%1,%3\";
1417: }")
1418:
1419: (define_insn ""
1420: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r,r")
1421: (match_operand:SI 1 "arith_operand" "K,K,&r")
1422: (match_operand:SI 2 "arith_operand" "K,&r,&"))
1423: (const_int 0))]
1424: ""
1425: "*
1426: {
1427: if (GET_CODE (operands[2]) == CONST_INT)
1428: return \"clr %0,%0,%1<%2>\";
1429: if (GET_CODE (operands[1]) == CONST_INT)
1430: {
1431: operands[1] = gen_rtx (CONST_INT, VOIDmode,
1432: (INTVAL (operands[1]) & 0x1f) << 5);
1433: return \"mask %2,%2,0x1f\;or %2,%2,%1\;clr %0,%0,%2\";
1434: }
1435: return \"mak %1,%1,5<5>\;mask %2,%2,0x1f\;or %2,%2,%1\;clr %0,%0,%2\";
1436: }")
1437:
1438: (define_insn ""
1439: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r,r")
1440: (match_operand:SI 1 "arith_operand" "K,K,&r")
1441: (match_operand:SI 2 "arith_operand" "K,&r,&r"))
1442: (const_int -1))]
1443: ""
1444: "*
1445: {
1446: if (GET_CODE (operands[2]) == CONST_INT)
1447: return \"set %0,%0,%1<%2>\";
1448: if (GET_CODE (operands[1]) == CONST_INT)
1449: {
1450: operands[1] = gen_rtx (CONST_INT, VOIDmode,
1451: (INTVAL (operands[1]) & 0x1f) << 5);
1452: return \"mask %2,%2,0x1f\;or %2,%2,%1\;set %0,%0,%2\";
1453: }
1454: return \"mak %1,%1,5<5>\;mask %2,%2,0x1f\;or %2,%2,%1\;set %0,%0,%2\";
1455: }")
1456:
1457: (define_insn "insv"
1458: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r,r")
1459: (match_operand:SI 1 "arith_operand" "K,K,&r")
1460: (match_operand:SI 2 "arith_operand" "K,&r,&r"))
1461: (match_operand:SI 3 "register_operand" "&r,&r,r"))]
1462: ""
1463: "*
1464: {
1465: if (GET_CODE (operands[2]) == CONST_INT)
1466: return \"mak %3,%3,%1<%2>\;clr %0,%0,%1<%2>\;or %0,%0,%3\";
1467: if (GET_CODE (operands[1]) == CONST_INT)
1468: {
1469: operands[1] = gen_rtx (CONST_INT, VOIDmode,
1470: (INTVAL (operands[1]) & 0x1f) << 5);
1471: return \"mask %2,%2,0x1f\;or %2,%2,%1\;mak %3,%3,%2\;clr %0,%0,%2\;or %0,%0,%3\";
1472: }
1473: return \"mak %1,%1,5<5>\;mask %2,%2,0x1f\;or %2,%2,%1\;mak %1,%3,%2\;clr %0,%0,%2\;or %0,%0,%1\";
1474: }")
1475:
1476: ;; negate insns
1477: (define_insn "negsi2"
1478: [(set (match_operand:SI 0 "register_operand" "=r")
1479: (neg:SI (match_operand:SI 1 "arith_operand" "rI")))]
1480: ""
1481: "sub %0,r0,%1")
1482:
1483: (define_insn "negdf2"
1484: [(set (match_operand:DF 0 "register_operand" "=r")
1485: (neg:DF (match_operand:DF 1 "register_operand" "r")))]
1486: ""
1487: "fsub.dsd %0,r0,%1")
1488:
1489: (define_insn "negsf2"
1490: [(set (match_operand:SF 0 "register_operand" "=r")
1491: (neg:SF (match_operand:SF 1 "register_operand" "r")))]
1492: ""
1493: "fsub.sss %0,r0,%1")
1494:
1495: ;; Store condition code values into registers
1496: (define_insn "seq"
1497: [(set (match_operand:SI 0 "general_operand" "=g")
1498: (eq (cc0) (const_int 0)))]
1499: ""
1500: "*
1501: {
1502: CC_STATUS_INIT;
1503: if (REG_P (operands[0]))
1504: return \"extu %0,r25,1<eq>\";
1505: return \"extu r25,r25,1<eq>\;st r25,%0\";
1506: }")
1507:
1508: (define_peephole
1509: [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
1510: (set (match_operand:SI 1 "general_operand" "=g")
1511: (eq (cc0) (const_int 0)))]
1512: ""
1513: "*
1514: {
1515: CC_STATUS_INIT;
1516: if (REG_P (operands[1]))
1517: return \"cmp r25,%0,0\;extu %1,r25,1<eq>\";
1518: return \"cmp r25,%0,0\;extu r25,r25,1<eq>\;st r25,%1\";
1519: }")
1520:
1521: (define_peephole
1522: [(set (cc0)
1523: (compare
1524: (match_operand:SI 0 "arith_operand" "r")
1525: (match_operand:SI 1 "arith_operand" "rI")))
1526: (set (match_operand:SI 2 "general_operand" "=g")
1527: (eq (cc0) (const_int 0)))]
1528: ""
1529: "*
1530: {
1531: CC_STATUS_INIT;
1532: if (REG_P (operands[2]))
1533: return \"cmp r25,%0,%1\;extu %2,r25,1<eq>\";
1534: return \"cmp r25,%0,%1\;extu r25,r25,1<eq>\;st r25,%2\";
1535: }")
1536:
1537: (define_insn "sne"
1538: [(set (match_operand:SI 0 "general_operand" "=g")
1539: (ne (cc0) (const_int 0)))]
1540: ""
1541: "*
1542: {
1543: CC_STATUS_INIT;
1544: if (REG_P (operands[0]))
1545: return \"extu %0,r25,1<ne>\";
1546: return \"extu r25,r25,1<ne>\;st r25,%0\";
1547: }")
1548:
1549: (define_peephole
1550: [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
1551: (set (match_operand:SI 1 "general_operand" "=g")
1552: (ne (cc0) (const_int 0)))]
1553: ""
1554: "*
1555: {
1556: CC_STATUS_INIT;
1557: if (REG_P (operands[1]))
1558: return \"cmp r25,%0,0\;extu %1,r25,1<ne>\";
1559: return \"cmp r25,%0,0\;extu r25,r25,1<ne>\;st r25,%1\";
1560: }")
1561:
1562: (define_peephole
1563: [(set (cc0)
1564: (compare
1565: (match_operand:SI 0 "arith_operand" "r")
1566: (match_operand:SI 1 "arith_operand" "rI")))
1567: (set (match_operand:SI 2 "general_operand" "=g")
1568: (ne (cc0) (const_int 0)))]
1569: ""
1570: "*
1571: {
1572: CC_STATUS_INIT;
1573: if (REG_P (operands[2]))
1574: return \"cmp r25,%0,%1\;extu %2,r25,1<ne>\";
1575: return \"cmp r25,%0,%1\;extu r25,r25,1<ne>\;st r25,%2\";
1576: }")
1577:
1578: (define_insn "sgt"
1579: [(set (match_operand:SI 0 "general_operand" "=g")
1580: (gt (cc0) (const_int 0)))]
1581: ""
1582: "*
1583: {
1584: CC_STATUS_INIT;
1585: if (REG_P (operands[0]))
1586: return \"extu %0,r25,1<gt>\";
1587: return \"extu r25,r25,1<gt>\;st r25,%0\";
1588: }")
1589:
1590: (define_peephole
1591: [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
1592: (set (match_operand:SI 1 "general_operand" "=g")
1593: (gt (cc0) (const_int 0)))]
1594: ""
1595: "*
1596: {
1597: CC_STATUS_INIT;
1598: if (REG_P (operands[1]))
1599: return \"cmp r25,%0,0\;extu %1,r25,1<gt>\";
1600: return \"cmp r25,%0,0\;extu r25,r25,1<gt>\;st r25,%1\";
1601: }")
1602:
1603: (define_peephole
1604: [(set (cc0)
1605: (compare
1606: (match_operand:SI 0 "arith_operand" "r")
1607: (match_operand:SI 1 "arith_operand" "rI")))
1608: (set (match_operand:SI 2 "general_operand" "=g")
1609: (gt (cc0) (const_int 0)))]
1610: ""
1611: "*
1612: {
1613: CC_STATUS_INIT;
1614: if (REG_P (operands[2]))
1615: return \"cmp r25,%0,%1\;extu %2,r25,1<gt>\";
1616: return \"cmp r25,%0,%1\;extu r25,r25,1<gt>\;st r25,%2\";
1617: }")
1618:
1619: (define_insn "sgtu"
1620: [(set (match_operand:SI 0 "general_operand" "=g")
1621: (gtu (cc0) (const_int 0)))]
1622: ""
1623: "*
1624: {
1625: CC_STATUS_INIT;
1626: if (REG_P (operands[0]))
1627: return \"extu %0,r25,1<hi>\";
1628: return \"extu r25,r25,1<hi>\;st r25,%0\";
1629: }")
1630:
1631: (define_peephole
1632: [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
1633: (set (match_operand:SI 1 "general_operand" "=g")
1634: (gtu (cc0) (const_int 0)))]
1635: ""
1636: "*
1637: {
1638: CC_STATUS_INIT;
1639: if (REG_P (operands[1]))
1640: return \"cmp r25,%0,0\;extu %1,r25,1<hi>\";
1641: return \"cmp r25,%0,0\;extu r25,r25,1<hi>\;st r25,%1\";
1642: }")
1643:
1644: (define_peephole
1645: [(set (cc0)
1646: (compare
1647: (match_operand:SI 0 "arith_operand" "r")
1648: (match_operand:SI 1 "arith_operand" "rI")))
1649: (set (match_operand:SI 2 "general_operand" "=g")
1650: (gtu (cc0) (const_int 0)))]
1651: ""
1652: "*
1653: {
1654: CC_STATUS_INIT;
1655: if (REG_P (operands[2]))
1656: return \"cmp r25,%0,%1\;extu %2,r25,1<hi>\";
1657: return \"cmp r25,%0,%1\;extu r25,r25,1<hi>\;st r25,%2\";
1658: }")
1659:
1660: (define_insn "slt"
1661: [(set (match_operand:SI 0 "general_operand" "=g")
1662: (lt (cc0) (const_int 0)))]
1663: ""
1664: "*
1665: {
1666: CC_STATUS_INIT;
1667: if (REG_P (operands[0]))
1668: return \"extu %0,r25,1<lt>\";
1669: return \"extu r25,r25,1<lt>\;st r25,%0\";
1670: }")
1671:
1672: (define_peephole
1673: [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
1674: (set (match_operand:SI 1 "general_operand" "=g")
1675: (lt (cc0) (const_int 0)))]
1676: ""
1677: "*
1678: {
1679: CC_STATUS_INIT;
1680: if (REG_P (operands[1]))
1681: return \"cmp r25,%0,0\;extu %1,r25,1<lt>\";
1682: return \"cmp r25,%0,0\;extu r25,r25,1<lt>\;st r25,%1\";
1683: }")
1684:
1685: (define_peephole
1686: [(set (cc0)
1687: (compare
1688: (match_operand:SI 0 "arith_operand" "r")
1689: (match_operand:SI 1 "arith_operand" "rI")))
1690: (set (match_operand:SI 2 "general_operand" "=g")
1691: (lt (cc0) (const_int 0)))]
1692: ""
1693: "*
1694: {
1695: CC_STATUS_INIT;
1696: if (REG_P (operands[2]))
1697: return \"cmp r25,%0,%1\;extu %2,r25,1<lt>\";
1698: return \"cmp r25,%0,%1\;extu r25,r25,1<lt>\;st r25,%2\";
1699: }")
1700:
1701: (define_insn "sltu"
1702: [(set (match_operand:SI 0 "general_operand" "=g")
1703: (ltu (cc0) (const_int 0)))]
1704: ""
1705: "*
1706: {
1707: CC_STATUS_INIT;
1708: if (REG_P (operands[0]))
1709: return \"extu %0,r25,1<lo>\";
1710: return \"extu r25,r25,1<lo>\;st r25,%0\";
1711: }")
1712:
1713: (define_peephole
1714: [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
1715: (set (match_operand:SI 1 "general_operand" "=g")
1716: (ltu (cc0) (const_int 0)))]
1717: ""
1718: "*
1719: {
1720: CC_STATUS_INIT;
1721: if (REG_P (operands[1]))
1722: return \"cmp r25,%0,0\;extu %1,r25,1<lo>\";
1723: return \"cmp r25,%0,0\;extu r25,r25,1<lo>\;st r25,%1\";
1724: }")
1725:
1726: (define_peephole
1727: [(set (cc0)
1728: (compare
1729: (match_operand:SI 0 "arith_operand" "r")
1730: (match_operand:SI 1 "arith_operand" "rI")))
1731: (set (match_operand:SI 2 "general_operand" "=g")
1732: (ltu (cc0) (const_int 0)))]
1733: ""
1734: "*
1735: {
1736: CC_STATUS_INIT;
1737: if (REG_P (operands[2]))
1738: return \"cmp r25,%0,%1\;extu %2,r25,1<lo>\";
1739: return \"cmp r25,%0,%1\;extu r25,r25,1<lo>\;st r25,%2\";
1740: }")
1741:
1742: (define_insn "sge"
1743: [(set (match_operand:SI 0 "general_operand" "=g")
1744: (ge (cc0) (const_int 0)))]
1745: ""
1746: "*
1747: {
1748: CC_STATUS_INIT;
1749: if (REG_P (operands[0]))
1750: return \"extu %0,r25,1<ge>\";
1751: return \"extu r25,r25,1<ge>\;st r25,%0\";
1752: }")
1753:
1754: (define_peephole
1755: [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
1756: (set (match_operand:SI 1 "general_operand" "=g")
1757: (ge (cc0) (const_int 0)))]
1758: ""
1759: "*
1760: {
1761: CC_STATUS_INIT;
1762: if (REG_P (operands[1]))
1763: return \"cmp r25,%0,0\;extu %1,r25,1<ge>\";
1764: return \"cmp r25,%0,0\;extu r25,r25,1<ge>\;st r25,%1\";
1765: }")
1766:
1767: (define_peephole
1768: [(set (cc0)
1769: (compare
1770: (match_operand:SI 0 "arith_operand" "r")
1771: (match_operand:SI 1 "arith_operand" "rI")))
1772: (set (match_operand:SI 2 "general_operand" "=g")
1773: (ge (cc0) (const_int 0)))]
1774: ""
1775: "*
1776: {
1777: CC_STATUS_INIT;
1778: if (REG_P (operands[2]))
1779: return \"cmp r25,%0,%1\;extu %2,r25,1<ge>\";
1780: return \"cmp r25,%0,%1\;extu r25,r25,1<ge>\;st r25,%2\";
1781: }")
1782:
1783: (define_insn "sgeu"
1784: [(set (match_operand:SI 0 "general_operand" "=g")
1785: (geu (cc0) (const_int 0)))]
1786: ""
1787: "*
1788: {
1789: CC_STATUS_INIT;
1790: if (REG_P (operands[0]))
1791: return \"extu %0,r25,1<hs>\";
1792: return \"extu r25,r25,1<hs>\;st r25,%0\";
1793: }")
1794:
1795: (define_peephole
1796: [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
1797: (set (match_operand:SI 1 "general_operand" "=g")
1798: (geu (cc0) (const_int 0)))]
1799: ""
1800: "*
1801: {
1802: CC_STATUS_INIT;
1803: if (REG_P (operands[1]))
1804: return \"cmp r25,%0,0\;extu %1,r25,1<hs>\";
1805: return \"cmp r25,%0,0\;extu r25,r25,1<hs>\;st r25,%1\";
1806: }")
1807:
1808: (define_peephole
1809: [(set (cc0)
1810: (compare
1811: (match_operand:SI 0 "arith_operand" "r")
1812: (match_operand:SI 1 "arith_operand" "rI")))
1813: (set (match_operand:SI 2 "general_operand" "=g")
1814: (geu (cc0) (const_int 0)))]
1815: ""
1816: "*
1817: {
1818: CC_STATUS_INIT;
1819: if (REG_P (operands[2]))
1820: return \"cmp r25,%0,%1\;extu %2,r25,1<hs>\";
1821: return \"cmp r25,%0,%1\;extu r25,r25,1<hs>\;st r25,%2\";
1822: }")
1823:
1824: (define_insn "sle"
1825: [(set (match_operand:SI 0 "general_operand" "=g")
1826: (le (cc0) (const_int 0)))]
1827: ""
1828: "*
1829: {
1830: CC_STATUS_INIT;
1831: if (REG_P (operands[0]))
1832: return \"extu %0,r25,1<le>\";
1833: return \"extu r25,r25,1<le>\;st r25,%0\";
1834: }")
1835:
1836: (define_peephole
1837: [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
1838: (set (match_operand:SI 1 "general_operand" "=g")
1839: (le (cc0) (const_int 0)))]
1840: ""
1841: "*
1842: {
1843: CC_STATUS_INIT;
1844: if (REG_P (operands[1]))
1845: return \"cmp r25,%0,0\;extu %1,r25,1<le>\";
1846: return \"cmp r25,%0,0\;extu r25,r25,1<le>\;st r25,%1\";
1847: }")
1848:
1849: (define_peephole
1850: [(set (cc0)
1851: (compare
1852: (match_operand:SI 0 "arith_operand" "r")
1853: (match_operand:SI 1 "arith_operand" "rI")))
1854: (set (match_operand:SI 2 "general_operand" "=g")
1855: (le (cc0) (const_int 0)))]
1856: ""
1857: "*
1858: {
1859: CC_STATUS_INIT;
1860: if (REG_P (operands[2]))
1861: return \"cmp r25,%0,%1\;extu %2,r25,1<le>\";
1862: return \"cmp r25,%0,%1\;extu r25,r25,1<le>\;st r25,%2\";
1863: }")
1864:
1865: (define_insn "sleu"
1866: [(set (match_operand:SI 0 "general_operand" "=g")
1867: (leu (cc0) (const_int 0)))]
1868: ""
1869: "*
1870: {
1871: CC_STATUS_INIT;
1872: if (REG_P (operands[0]))
1873: return \"extu %0,r25,1<ls>\";
1874: return \"extu r25,r25,1<ls>\;st r25,%0\";
1875: }")
1876:
1877: (define_peephole
1878: [(set (cc0) (match_operand:SI 0 "register_operand" "r"))
1879: (set (match_operand:SI 1 "general_operand" "=g")
1880: (leu (cc0) (const_int 0)))]
1881: ""
1882: "*
1883: {
1884: CC_STATUS_INIT;
1885: if (REG_P (operands[1]))
1886: return \"cmp r25,%0,0\;extu %1,r25,1<ls>\";
1887: return \"cmp r25,%0,0\;extu r25,r25,1<ls>\;st r25,%1\";
1888: }")
1889:
1890: (define_peephole
1891: [(set (cc0)
1892: (compare
1893: (match_operand:SI 0 "arith_operand" "r")
1894: (match_operand:SI 1 "arith_operand" "rI")))
1895: (set (match_operand:SI 2 "general_operand" "=g")
1896: (leu (cc0) (const_int 0)))]
1897: ""
1898: "*
1899: {
1900: CC_STATUS_INIT;
1901: if (REG_P (operands[2]))
1902: return \"cmp r25,%0,%1\;extu %2,r25,1<ls>\";
1903: return \"cmp r25,%0,%1\;extu r25,r25,1<ls>\;st r25,%2\";
1904: }")
1905:
1906:
1907: ;; Unconditional and other jump instructions
1908: (define_insn "jump"
1909: [(set (pc)
1910: (label_ref (match_operand 0 "" "")))]
1911: ""
1912: "br %l0")
1913:
1914: (define_insn ""
1915: [(set (pc)
1916: (label_ref (match_operand 0 "" "")))
1917: (clobber (const_int 1))]
1918: ""
1919: "br.n %l0")
1920:
1921: (define_insn "tablejump"
1922: [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1923: (use (label_ref (match_operand 1 "" "")))]
1924: ""
1925: "jmp %0")
1926:
1927: ;;- jump to subroutine
1928: (define_insn "call"
1929: [(call (match_operand:SI 0 "memory_operand" "m")
1930: (match_operand:SI 1 "general_operand" "g"))
1931: (use (reg:SI 1))]
1932: ;;- Don't use operand 1 for most machines.
1933: ""
1934: "*
1935: {
1936: operands[0] = XEXP (operands[0], 0);
1937: if (REG_P (operands[0]))
1938: return \"jsr %0\";
1939: return \"bsr %0\";
1940: }")
1941:
1942: (define_insn ""
1943: [(call (match_operand:SI 0 "memory_operand" "m")
1944: (match_operand:SI 1 "general_operand" "g"))
1945: (clobber (const_int 1))
1946: (use (reg:SI 1))]
1947: ;;- Don't use operand 1 for most machines.
1948: ""
1949: "*
1950: {
1951: operands[0] = XEXP (operands[0], 0);
1952: if (REG_P (operands[0]))
1953: return \"jsr.n %0\";
1954: return \"bsr.n %0\";
1955: }")
1956:
1957: ;;- jump to subroutine
1958: (define_insn "call_value"
1959: [(set (match_operand 0 "" "=r")
1960: (call (match_operand:SI 1 "memory_operand" "m")
1961: (match_operand:SI 2 "general_operand" "g")))
1962: (use (reg:SI 1))]
1963: ;;- Don't use operand 2 for most machines.
1964: ""
1965: "*
1966: {
1967: operands[1] = XEXP (operands[1], 0);
1968: if (REG_P (operands[1]))
1969: return \"jsr %1\";
1970: return \"bsr %1\";
1971: }")
1972:
1973: (define_insn ""
1974: [(set (match_operand 0 "" "=r")
1975: (call (match_operand:SI 1 "memory_operand" "m")
1976: (match_operand:SI 2 "general_operand" "g")))
1977: (use (reg:SI 1))
1978: (clobber (const_int 2))]
1979: ;;- Don't use operand 2 for most machines.
1980: ""
1981: "*
1982: {
1983: operands[1] = XEXP (operands[1], 0);
1984: if (REG_P (operands[1]))
1985: return \"jsr.n %1\";
1986: return \"bsr.n %1\";
1987: }")
1988:
1989: ;; A memory ref with constant address is not normally valid.
1990: ;; But it is valid in a call insns. This pattern allows the
1991: ;; loading of the address to combine with the call.
1992: (define_insn ""
1993: [(call (mem:SI (match_operand:SI 0 "" "i"))
1994: (match_operand:SI 1 "general_operand" "g"))
1995: (use (reg:SI 1))]
1996: ;;- Don't use operand 1 for most machines.
1997: "GET_CODE (operands[0]) == SYMBOL_REF"
1998: "bsr %0")
1999:
2000: (define_insn ""
2001: [(call (mem:SI (match_operand:SI 0 "" "i"))
2002: (match_operand:SI 1 "general_operand" "g"))
2003: (clobber (const_int 1))
2004: (use (reg:SI 1))]
2005: ;;- Don't use operand 1 for most machines.
2006: "GET_CODE (operands[0]) == SYMBOL_REF"
2007: "bsr.n %0")
2008:
2009: (define_insn "nop"
2010: [(const_int 0)]
2011: ""
2012: "nop")
2013:
2014: ;; Recognize jbs and jbc instructions.
2015:
2016: (define_insn ""
2017: [(set (pc)
2018: (if_then_else
2019: (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
2020: (const_int 1)
2021: (match_operand:SI 1 "int5_operand" "K"))
2022: (const_int 0))
2023: (label_ref (match_operand 2 "" ""))
2024: (pc)))]
2025: ""
2026: "bb1 %1,%0,%l2")
2027:
2028: (define_insn ""
2029: [(set (pc)
2030: (if_then_else
2031: (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
2032: (const_int 1)
2033: (match_operand:SI 1 "int5_operand" "K"))
2034: (const_int 0))
2035: (label_ref (match_operand 2 "" ""))
2036: (pc)))]
2037: ""
2038: "bb0 %1,%0,%l2")
2039:
2040: (define_insn ""
2041: [(set (pc)
2042: (if_then_else
2043: (ne (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
2044: (const_int 1)
2045: (match_operand:SI 1 "int5_operand" "K"))
2046: (const_int 0))
2047: (pc)
2048: (label_ref (match_operand 2 "" ""))))]
2049: ""
2050: "bb0 %1,%0,%l2")
2051:
2052: (define_insn ""
2053: [(set (pc)
2054: (if_then_else
2055: (eq (sign_extract:SI (match_operand:SI 0 "register_operand" "r")
2056: (const_int 1)
2057: (match_operand:SI 1 "int5_operand" "K"))
2058: (const_int 0))
2059: (pc)
2060: (label_ref (match_operand 2 "" ""))))]
2061: ""
2062: "bb1 %1,%0,%l2")
2063:
2064: (define_insn ""
2065: [(set (pc)
2066: (if_then_else
2067: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
2068: (const_int 1)
2069: (match_operand:SI 1 "int5_operand" "K"))
2070: (const_int 0))
2071: (label_ref (match_operand 2 "" ""))
2072: (pc)))]
2073: ""
2074: "bb1 %1,%0,%l2")
2075:
2076: (define_insn ""
2077: [(set (pc)
2078: (if_then_else
2079: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
2080: (const_int 1)
2081: (match_operand:SI 1 "int5_operand" "K"))
2082: (const_int 0))
2083: (label_ref (match_operand 2 "" ""))
2084: (pc)))]
2085: ""
2086: "bb0 %1,%0,%l2")
2087:
2088: (define_insn ""
2089: [(set (pc)
2090: (if_then_else
2091: (eq (and:SI (match_operand:SI 0 "register_operand" "r")
2092: (match_operand:SI 1 "int5_operand" "K"))
2093: (const_int 0))
2094: (pc)
2095: (label_ref (match_operand 2 "" ""))))]
2096: "exact_log2 (INTVAL (operands[1])) >= 0"
2097: "*
2098: {
2099: operands[1]
2100: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
2101: return \"bb1 %1,%0,%l2\";
2102: }")
2103:
2104: (define_insn ""
2105: [(set (pc)
2106: (if_then_else
2107: (eq (and:SI (match_operand:SI 0 "register_operand" "r")
2108: (match_operand:SI 1 "int5_operand" "K"))
2109: (const_int 0))
2110: (label_ref (match_operand 2 "" ""))
2111: (pc)))]
2112: "exact_log2 (INTVAL (operands[1])) >= 0"
2113: "*
2114: {
2115: operands[1]
2116: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
2117: return \"bb0 %1,%0,%l2\";
2118: }")
2119:
2120: (define_insn ""
2121: [(set (pc)
2122: (if_then_else
2123: (ne (and:SI (match_operand:SI 0 "register_operand" "r")
2124: (match_operand:SI 1 "int5_operand" "K"))
2125: (const_int 0))
2126: (pc)
2127: (label_ref (match_operand 2 "" ""))))]
2128: "exact_log2 (INTVAL (operands[1])) >= 0"
2129: "*
2130: {
2131: operands[1]
2132: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
2133: return \"bb0 %1,%0,%l2\";
2134: }")
2135:
2136: (define_insn ""
2137: [(set (pc)
2138: (if_then_else
2139: (ne (and:SI (match_operand:SI 0 "register_operand" "r")
2140: (match_operand:SI 1 "int5_operand" "K"))
2141: (const_int 0))
2142: (label_ref (match_operand 2 "" ""))
2143: (pc)))]
2144: "exact_log2 (INTVAL (operands[1])) >= 0"
2145: "*
2146: {
2147: operands[1]
2148: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
2149: return \"bb1 %1,%0,%l2\";
2150: }")
2151:
2152: (define_insn ""
2153: [(set (pc)
2154: (if_then_else
2155: (ne (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
2156: (const_int 1)
2157: (match_operand:SI 1 "int5_operand" "K"))
2158: (const_int 0))
2159: (pc)
2160: (label_ref (match_operand 2 "" ""))))]
2161: ""
2162: "bb0 %1,%0,%l2")
2163:
2164: (define_insn ""
2165: [(set (pc)
2166: (if_then_else
2167: (eq (sign_extract:SI (match_operand:SI 0 "general_operand" "r")
2168: (const_int 1)
2169: (match_operand:SI 1 "int5_operand" "K"))
2170: (const_int 0))
2171: (pc)
2172: (label_ref (match_operand 2 "" ""))))]
2173: ""
2174: "bb1 %1,%0,%l2")
2175:
2176: (define_insn ""
2177: [(set (pc)
2178: (if_then_else
2179: (ne (and:SI (match_operand:SI 0 "register_operand" "r")
2180: (const_int 1))
2181: (const_int 0))
2182: (label_ref (match_operand 1 "" ""))
2183: (pc)))]
2184: ""
2185: "bb1 0,%0,%l1")
2186:
2187: (define_insn ""
2188: [(set (pc)
2189: (if_then_else
2190: (eq (and:SI (match_operand:SI 0 "register_operand" "r")
2191: (const_int 1))
2192: (const_int 0))
2193: (label_ref (match_operand 1 "" ""))
2194: (pc)))]
2195: ""
2196: "bb0 0,%0,%l1")
2197:
2198: (define_insn ""
2199: [(set (pc)
2200: (if_then_else
2201: (ne (and:SI (match_operand:SI 0 "register_operand" "r")
2202: (const_int 1))
2203: (const_int 0))
2204: (pc)
2205: (label_ref (match_operand 1 "" ""))))]
2206: ""
2207: "bb0 0,%0,%l1")
2208:
2209: (define_insn ""
2210: [(set (pc)
2211: (if_then_else
2212: (eq (and:SI (match_operand:SI 0 "register_operand" "r")
2213: (const_int 1))
2214: (const_int 0))
2215: (pc)
2216: (label_ref (match_operand 1 "" ""))))]
2217: ""
2218: "bb1 0,%0,%l1")
2219:
2220: ;; These four entries allow a jlbc or jlbs,to be made
2221: ;; by combination with a bic.
2222: (define_insn ""
2223: [(set (pc)
2224: (if_then_else
2225: (ne (and:SI (match_operand:SI 0 "register_operand" "r")
2226: (not:SI (const_int -2)))
2227: (const_int 0))
2228: (label_ref (match_operand 1 "" ""))
2229: (pc)))]
2230: ""
2231: "bb1 0,%0,%l1")
2232:
2233: (define_insn ""
2234: [(set (pc)
2235: (if_then_else
2236: (eq (and:SI (match_operand:SI 0 "register_operand" "r")
2237: (not:SI (const_int -2)))
2238: (const_int 0))
2239: (label_ref (match_operand 1 "" ""))
2240: (pc)))]
2241: ""
2242: "bb0 0,%0,%l1")
2243:
2244: (define_insn ""
2245: [(set (pc)
2246: (if_then_else
2247: (ne (and:SI (match_operand:SI 0 "register_operand" "r")
2248: (not:SI (const_int -2)))
2249: (const_int 0))
2250: (pc)
2251: (label_ref (match_operand 1 "" ""))))]
2252: ""
2253: "bb0 0,%0,%l1")
2254:
2255: (define_insn ""
2256: [(set (pc)
2257: (if_then_else
2258: (eq (and:SI (match_operand:SI 0 "register_operand" "r")
2259: (not:SI (const_int -2)))
2260: (const_int 0))
2261: (pc)
2262: (label_ref (match_operand 1 "" ""))))]
2263: ""
2264: "bb1 0,%0,%l1")
2265: ;;- Local variables:
2266: ;;- mode:emacs-lisp
2267: ;;- comment-start: ";;- "
2268: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2269: ;;- eval: (modify-syntax-entry ?[ "(]")
2270: ;;- eval: (modify-syntax-entry ?] ")[")
2271: ;;- eval: (modify-syntax-entry ?{ "(}")
2272: ;;- eval: (modify-syntax-entry ?} "){")
2273: ;;- End:
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