--- gcc/config/m88k/m88k.md 2018/04/24 18:13:56 1.1.1.2 +++ gcc/config/m88k/m88k.md 2018/04/24 18:27:41 1.1.1.4 @@ -1,8 +1,8 @@ ;;- Machine description for the Motorola 88000 for GNU C compiler -;; Copyright (C) 1988, 1989, 1990, 1991, 1993 Free Software Foundation, Inc. +;; Copyright (C) 1988, 92, 93, 94, 1995 Free Software Foundation, Inc. ;; Contributed by Michael Tiemann (tiemann@mcc.com) ;; Additional changes by Michael Meissner (meissner@osf.org) -;; Version 2 port by Tom Wood (Tom_Wood@NeXT.com) +;; Version 2 port by Tom Wood (twood@pets.sps.mot.com) ;; This file is part of GNU CC. @@ -18,20 +18,22 @@ ;; You should have received a copy of the GNU General Public License ;; along with GNU CC; see the file COPYING. If not, write to -;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. +;; the Free Software Foundation, 59 Temple Place - Suite 330, +;; Boston, MA 02111-1307, USA. ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. -;; SCCS rev field. This is a NOP, just to get the SCCS id into the +;; RCS rev field. This is a NOP, just to get the RCS id into the ;; program image. -(define_expand "m88k_sccs_id" +(define_expand "m88k_rcs_id" [(match_operand:SI 0 "" "")] "" - "{ static char sccs_id[] = \"@(#)m88k.md 2.3.3.2 12/16/92 08:26:12\"; + "{ static char rcs_id[] = \"$What: <@(#) m88k.md,v 1.1.1.2.2.2> $\"; FAIL; }") -;; Attribute specifications +;; Attribute describing the processor. This attribute must match exactly +;; with the processor_type enumeration in m88k.h. ; Target CPU. (define_attr "cpu" "m88100,m88110,m88000" @@ -324,8 +326,7 @@ ;; (tege@sics.se). They've changed since then, so don't complain to him ;; if they don't work right. -;; Regarding shifts, gen_lshlsi3 generates ASHIFT. LSHIFT opcodes are -;; not produced and should not normally occur. Also, the gen functions +;; Regarding shifts, gen_lshlsi3 generates ASHIFT. The gen functions ;; produce the necessary insns to support TARGET_*_LARGE_SHIFT, so nothing ;; special needs to be done here. @@ -1837,12 +1838,35 @@ "" "or %0,%1,%#lo16(%g2)") +;; For PIC, symbol_refs are put inside unspec so that the optimizer won't +;; confuse them with real addresses. +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=r") + (lo_sum:SI (match_operand:SI 1 "register_operand" "r") + (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))] + "" + "or %0,%1,%#lo16(%g2)" + ;; Need to set length for this arith insn because operand2 + ;; is not an "arith_operand". + [(set_attr "length" "1")]) + (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") (high:SI (match_operand 1 "" "")))] "" "or.u %0,%#r0,%#hi16(%g1)") +;; For PIC, symbol_refs are put inside unspec so that the optimizer won't +;; confuse them with real addresses. +(define_insn "" + [(set (match_operand:SI 0 "register_operand" "=r") + (high:SI (unspec:SI [(match_operand 1 "" "")] 0)))] + "" + "or.u %0,%#r0,%#hi16(%g1)" + ;; Need to set length for this arith insn because operand2 + ;; is not an arith_operand. + [(set_attr "length" "1")]) + ;; HImode move instructions (define_expand "movhi" @@ -1970,6 +1994,20 @@ DONE; }") +(define_split + [(set (match_operand:DF 0 "register_operand" "=r") + (match_operand:DF 1 "register_operand" "r"))] + "reload_completed + && GET_CODE (operands[0]) == REG && !XRF_REGNO_P (REGNO (operands[0])) + && GET_CODE (operands[1]) == REG && !XRF_REGNO_P (REGNO (operands[1]))" + [(set (match_dup 2) (match_dup 3)) + (set (match_dup 4) (match_dup 5))] + " +{ operands[2] = operand_subword (operands[0], 0, 0, DFmode); + operands[3] = operand_subword (operands[1], 0, 0, DFmode); + operands[4] = operand_subword (operands[0], 1, 0, DFmode); + operands[5] = operand_subword (operands[1], 1, 0, DFmode); }") + ;; @@ This pattern is incomplete and doesn't appear necessary. ;; ;; This pattern forces (set (reg:DF ...) (const_double ...)) @@ -2679,7 +2717,7 @@ ;;- multiply instructions ;; -;; There is an unfounded silicon eratta for E.1 requiring that an +;; There is an unfounded silicon errata for E.1 requiring that an ;; immediate constant value in div/divu/mul instructions be less than ;; 0x800. This is no longer provided for. @@ -2691,13 +2729,14 @@ "mul %0,%1,%2" [(set_attr "type" "imul")]) -(define_insn "umulsidi3" - [(set (match_operand:DI 0 "register_operand" "=r") - (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) - (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] - "TARGET_88110" - "mulu.d %0,%1,%2" - [(set_attr "type" "imul")]) +;; Loses for acvs/P60504.c (mod case) on 88110 +;; (define_insn "umulsidi3" +;; [(set (match_operand:DI 0 "register_operand" "=r") +;; (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r")) +;; (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))] +;; "TARGET_88110" +;; "mulu.d %0,%1,%2" +;; [(set_attr "type" "imul")]) ;; patterns for mixed mode floating point ;; Do not define patterns that utilize mixed mode arithmetic that result @@ -2773,9 +2812,9 @@ ;; for divide-by-zero or take your chances. If the div instruction is ;; used, the O/S must complete the operation if the operands are ;; negative. The O/S will signal an overflow condition if the most -;; negative number (-214783648) is divided by negative 1. +;; negative number (-2147483648) is divided by negative 1. ;; -;; There is an unfounded silicon eratta for E.1 requiring that an +;; There is an unfounded silicon errata for E.1 requiring that an ;; immediate constant value in div/divu/mul instructions be less than ;; 0x800. This is no longer provided for. @@ -3526,28 +3565,7 @@ [(set_attr "type" "bit")]) ;;- logical shift instructions. Logical shift left becomes arithmetic -;; shift left. LSHIFT is not normally produced, but is supported. - -(define_expand "lshlsi3" - [(set (match_operand:SI 0 "register_operand" "") - (lshift:SI (match_operand:SI 1 "register_operand" "") - (match_operand:SI 2 "arith32_operand" "")))] - "" - " -{ - emit_insn (gen_ashlsi3 (operands[0], operands[1], operands[2])); - DONE; -}") - -(define_insn "" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (lshift:SI (match_operand:SI 1 "register_operand" "r,r") - (match_operand:SI 2 "arith5_operand" "r,K")))] - "" - "@ - mak %0,%1,%2 - mak %0,%1,0<%2>" - [(set_attr "type" "bit")]) +;; shift left. (define_expand "lshrsi3" [(set (match_operand:SI 0 "register_operand" "") @@ -3836,7 +3854,7 @@ emit_jump_insn (gen_casesi_enter (label, index_diff, operands[3])); else /* Load the table entry and jump to it. */ - emit_jump_insn (gen_casesi_jump (gen_reg_rtx (SImode), base, index_diff)); + emit_jump_insn (gen_casesi_jump (gen_reg_rtx (SImode), base, index_diff, operands[3])); /* Claim that flow drops into the table so it will be adjacent by not emitting a barrier. */ @@ -3848,10 +3866,18 @@ (mem:SI (plus:SI (match_operand:SI 1 "" "") (mult:SI (match_operand:SI 2 "" "") (const_int 4))))) - (set (pc) (match_dup 0))] + (parallel [(set (pc) (match_dup 0)) + (use (label_ref (match_operand 3 "" "")))])] "" "") +(define_insn "" + [(set (pc) (match_operand:SI 0 "register_operand" "r")) + (use (label_ref (match_operand 1 "" "")))] + "" + "jmp%. %0" + [(set_attr "type" "jump")]) + ;; The bsr.n instruction is directed to the END of the table. See ;; ASM_OUTPUT_CASE_END.