--- gcc/config/m88k/m88k.md	2018/04/24 18:10:23	1.1.1.1
+++ gcc/config/m88k/m88k.md	2018/04/24 18:27:41	1.1.1.4
@@ -1,8 +1,8 @@
 ;;- Machine description for the Motorola 88000 for GNU C compiler
-;;  Copyright (C) 1988, 1989, 1990, 1991 Free Software Foundation, Inc.
+;;  Copyright (C) 1988, 92, 93, 94, 1995 Free Software Foundation, Inc.
 ;;  Contributed by Michael Tiemann (tiemann@mcc.com)
 ;;  Additional changes by Michael Meissner (meissner@osf.org)
-;;  Version 2 port by Tom Wood (Tom_Wood@NeXT.com)
+;;  Version 2 port by Tom Wood (twood@pets.sps.mot.com)
 
 ;; This file is part of GNU CC.
 
@@ -18,20 +18,22 @@
 
 ;; You should have received a copy of the GNU General Public License
 ;; along with GNU CC; see the file COPYING.  If not, write to
-;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
+;; the Free Software Foundation, 59 Temple Place - Suite 330,
+;; Boston, MA 02111-1307, USA.
 
 
 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
 
-;; SCCS rev field.  This is a NOP, just to get the SCCS id into the
+;; RCS rev field.  This is a NOP, just to get the RCS id into the
 ;; program image.
-(define_expand "m88k_sccs_id"
+(define_expand "m88k_rcs_id"
   [(match_operand:SI 0 "" "")]
   ""
-  "{ static char sccs_id[] = \"@(#)m88k.md	2.3.3.2 12/16/92 08:26:12\";
+  "{ static char rcs_id[] = \"$What: <@(#) m88k.md,v	1.1.1.2.2.2> $\";
      FAIL; }")
 
-;; Attribute specifications
+;; Attribute describing the processor.  This attribute must match exactly
+;; with the processor_type enumeration in m88k.h.
 
 ; Target CPU.
 (define_attr "cpu" "m88100,m88110,m88000"
@@ -324,8 +326,7 @@
 ;; (tege@sics.se).  They've changed since then, so don't complain to him
 ;; if they don't work right.
 
-;; Regarding shifts, gen_lshlsi3 generates ASHIFT.  LSHIFT opcodes are
-;; not produced and should not normally occur.  Also, the gen functions
+;; Regarding shifts, gen_lshlsi3 generates ASHIFT.  The gen functions
 ;; produce the necessary insns to support TARGET_*_LARGE_SHIFT, so nothing
 ;; special needs to be done here.
 
@@ -397,6 +398,7 @@
 ;; We define all logical operations on CCmode values to preserve the pairwise
 ;; relationship of the compare bits.  This allows a future branch prediction
 ;; pass the degree of freedom needed to change and/bb0-le into or/bb1-gt.
+;; THIS IS CURRENTLY FALSE! 
 ;;
 ;; Opportunities arise when conditional expressions using && and || are made
 ;; unconditional.  When these are used to branch, the sequence is
@@ -419,21 +421,21 @@
 (define_split
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(ior:SI (neg:SI 
-		 (match_operator 1 "relop"
-				 [(match_operand:CC 2 "register_operand" "%r")
+		 (match_operator 1 "even_relop"
+				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
 				  (const_int 0)]))
 		(neg:SI
 		 (match_operator 3 "relop"
-				 [(match_operand:CC 4 "register_operand" "r")
+				 [(match_operand 4 "partial_ccmode_register_operand" "r")
 				  (const_int 0)]))))
    (clobber (match_operand:SI 5 "register_operand" "=r"))]
   ""
   [(set (match_dup 5)
-	(ior:CC (match_dup 4)
+	(ior:CCEVEN (match_dup 4)
 		(match_dup 2)))
    (set (match_dup 0)
 	(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
-  "operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
+  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
    if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
      ; /* The conditions match.  */
    else if (GET_CODE (operands[1])
@@ -456,43 +458,140 @@
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (match_operator 1 "relop"
-				[(match_operand:CC 2 "register_operand" "%r")
+	(ior:SI (neg:SI 
+		 (match_operator 1 "odd_relop"
+				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
+				  (const_int 0)]))
+		(neg:SI
+		 (match_operator 3 "odd_relop"
+				 [(match_operand 4 "partial_ccmode_register_operand" "r")
+				  (const_int 0)]))))
+   (clobber (match_operand:SI 5 "register_operand" "=r"))]
+  ""
+  [(set (match_dup 5)
+	(and:CCEVEN (match_dup 4)
+		(match_dup 2)))
+   (set (match_dup 0)
+	(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
+  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
+   if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
+     ; /* The conditions match.  */
+   else
+     {
+       /* Make the condition pairs line up by rotating the compare word.  */
+       int cv1 = condition_value (operands[1]);
+       int cv2 = condition_value (operands[3]);
+
+       operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
+			      gen_rtx (CONST_INT, VOIDmode,
+				       (cv2 - cv1) & 0x1f));
+     }")
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ior:SI (neg:SI 
+		 (match_operator 1 "odd_relop"
+				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
+				  (const_int 0)]))
+		(neg:SI
+		 (match_operator 3 "even_relop"
+				 [(match_operand 4 "partial_ccmode_register_operand" "r")
+				  (const_int 0)]))))
+   (clobber (match_operand:SI 5 "register_operand" "=r"))]
+  ""
+  [(set (match_dup 5)
+	(ior:CCEVEN (not:CC (match_dup 2))
+		(match_dup 4)))
+   (set (match_dup 0)
+	(neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))]
+  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
+  if (GET_CODE (operands[1])
+	    == reverse_condition (GET_CODE (operands[3])))
+     ; 
+   else
+     {
+       /* Make the condition pairs line up by rotating the compare word.  */
+       int cv1 = condition_value (operands[1]);
+       int cv2 = condition_value (operands[3]);
+
+       operands[2] = gen_rtx (ROTATE, CCmode, operands[2],
+			      gen_rtx (CONST_INT, VOIDmode,
+				       ((cv1 & ~1) - (cv2 & ~1)) & 0x1f));
+     }")
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ior:SI (match_operator 1 "even_relop"
+				[(match_operand 2 "partial_ccmode_register_operand" "%r")
 				 (const_int 0)])
 		(match_operator 3 "relop"
-				[(match_operand:CC 4 "register_operand" "r")
+				[(match_operand 4 "partial_ccmode_register_operand" "r")
 				 (const_int 0)])))
    (clobber (match_operand:SI 5 "register_operand" "=r"))]
   "GET_CODE (operands[1]) == GET_CODE (operands[3])
    || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
   [(set (match_dup 5)
-	(ior:CC (match_dup 4)
+	(ior:CCEVEN (match_dup 4)
 		(match_dup 2)))
    (set (match_dup 0)
 	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
-  "operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
+  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
    /* Reverse the condition by  complimenting the compare word.  */
    if (GET_CODE (operands[1]) != GET_CODE (operands[3]))
       operands[4] = gen_rtx (NOT, CCmode, operands[4]);")
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "=r")
+	(ior:SI (match_operator 1 "odd_relop"
+				[(match_operand 2 "partial_ccmode_register_operand" "%r")
+				 (const_int 0)])
+		(match_operator 3 "odd_relop"
+				[(match_operand 4 "partial_ccmode_register_operand" "r")
+				 (const_int 0)])))
+   (clobber (match_operand:SI 5 "register_operand" "=r"))]
+  "GET_CODE (operands[1]) == GET_CODE (operands[3])"
+  [(set (match_dup 5)
+	(and:CCEVEN (match_dup 4)
+		(match_dup 2)))
+   (set (match_dup 0)
+	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
+  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(ior:SI (match_operator 1 "odd_relop"
+				[(match_operand 2 "partial_ccmode_register_operand" "%r")
+				 (const_int 0)])
+		(match_operator 3 "even_relop"
+				[(match_operand 4 "partial_ccmode_register_operand" "r")
+				 (const_int 0)])))
+   (clobber (match_operand:SI 5 "register_operand" "=r"))]
+  "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
+  [(set (match_dup 5)
+	(ior:CCEVEN (not:CC (match_dup 4))
+		(match_dup 2)))
+   (set (match_dup 0)
+	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
+  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "=r")
 	(and:SI (neg:SI 
-		 (match_operator 1 "relop"
-				 [(match_operand:CC 2 "register_operand" "%r")
+		 (match_operator 1 "even_relop"
+				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
 				  (const_int 0)]))
 		(neg:SI
 		 (match_operator 3 "relop"
-				 [(match_operand:CC 4 "register_operand" "r")
+				 [(match_operand 4 "partial_ccmode_register_operand" "r")
 				  (const_int 0)]))))
    (clobber (match_operand:SI 5 "register_operand" "=r"))]
   ""
   [(set (match_dup 5)
-	(and:CC (match_dup 4)
+	(and:CCEVEN (match_dup 4)
 		(match_dup 2)))
    (set (match_dup 0)
 	(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
-  "operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
+  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
    if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
      ; /* The conditions match.  */
    else if (GET_CODE (operands[1])
@@ -504,7 +603,6 @@
        /* Make the condition pairs line up by rotating the compare word.  */
        int cv1 = condition_value (operands[1]);
        int cv2 = condition_value (operands[3]);
-
        operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
 			      gen_rtx (CONST_INT, VOIDmode,
 				       ((cv2 & ~1) - (cv1 & ~1)) & 0x1f));
@@ -515,53 +613,148 @@
 
 (define_split
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(and:SI (match_operator 1 "relop"
-				[(match_operand:CC 2 "register_operand" "%r")
+	(and:SI (neg:SI 
+		 (match_operator 1 "odd_relop"
+				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
+				  (const_int 0)]))
+		(neg:SI
+		 (match_operator 3 "odd_relop"
+				 [(match_operand 4 "partial_ccmode_register_operand" "r")
+				  (const_int 0)]))))
+   (clobber (match_operand:SI 5 "register_operand" "=r"))]
+  ""
+  [(set (match_dup 5)
+	(ior:CCEVEN (match_dup 4)
+		(match_dup 2)))
+   (set (match_dup 0)
+	(neg:SI (match_op_dup 1 [(match_dup 5) (const_int 0)])))]
+  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
+   if (GET_CODE (operands[1]) == GET_CODE (operands[3]))
+     ; /* The conditions match.  */
+   else
+     {
+       /* Make the condition pairs line up by rotating the compare word.  */
+       int cv1 = condition_value (operands[1]);
+       int cv2 = condition_value (operands[3]);
+       operands[4] = gen_rtx (ROTATE, CCmode, operands[4],
+			      gen_rtx (CONST_INT, VOIDmode,
+				       (cv2 - cv1) & 0x1f));
+     }")
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(and:SI (neg:SI 
+		 (match_operator 1 "odd_relop"
+				 [(match_operand 2 "partial_ccmode_register_operand" "%r")
+				  (const_int 0)]))
+		(neg:SI
+		 (match_operator 3 "even_relop"
+				 [(match_operand 4 "partial_ccmode_register_operand" "r")
+				  (const_int 0)]))))
+   (clobber (match_operand:SI 5 "register_operand" "=r"))]
+  ""
+  [(set (match_dup 5)
+	(and:CCEVEN (not:CC (match_dup 2))
+		(match_dup 4)))
+   (set (match_dup 0)
+	(neg:SI (match_op_dup 3 [(match_dup 5) (const_int 0)])))]
+  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
+   if (GET_CODE (operands[1])
+	    == reverse_condition (GET_CODE (operands[3])))
+	;
+   else
+     {
+       /* Make the condition pairs line up by rotating the compare word.  */
+       int cv1 = condition_value (operands[1]);
+       int cv2 = condition_value (operands[3]);
+       operands[2] = gen_rtx (ROTATE, CCmode, operands[2],
+			      gen_rtx (CONST_INT, VOIDmode,
+				       ((cv1 & ~1) - (cv2 & ~1)) & 0x1f));
+     }")
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(and:SI (match_operator 1 "even_relop"
+				[(match_operand 2 "partial_ccmode_register_operand" "%r")
 				 (const_int 0)])
 		(match_operator 3 "relop"
-				[(match_operand:CC 4 "register_operand" "r")
+				[(match_operand 4 "partial_ccmode_register_operand" "r")
 				 (const_int 0)])))
    (clobber (match_operand:SI 5 "register_operand" "=r"))]
   "GET_CODE (operands[1]) == GET_CODE (operands[3])
    || GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
   [(set (match_dup 5)
-	(and:CC (match_dup 4)
+	(and:CCEVEN (match_dup 4)
 		(match_dup 2)))
    (set (match_dup 0)
 	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
-  "operands[5] = gen_rtx (SUBREG, CCmode, operands[5], 0);
+  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);
    /* Reverse the condition by  complimenting the compare word.  */
    if (GET_CODE (operands[1]) != GET_CODE (operands[3]))
       operands[4] = gen_rtx (NOT, CCmode, operands[4]);")
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(and:SI (match_operator 1 "odd_relop"
+				[(match_operand 2 "partial_ccmode_register_operand" "%r")
+				 (const_int 0)])
+		(match_operator 3 "odd_relop"
+				[(match_operand 4 "partial_ccmode_register_operand" "r")
+				 (const_int 0)])))
+   (clobber (match_operand:SI 5 "register_operand" "=r"))]
+  "GET_CODE (operands[1]) == GET_CODE (operands[3])"
+  [(set (match_dup 5)
+	(ior:CCEVEN (match_dup 4)
+		(match_dup 2)))
+   (set (match_dup 0)
+	(match_op_dup 1 [(match_dup 5) (const_int 0)]))]
+  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(and:SI (match_operator 1 "odd_relop"
+				[(match_operand 2 "partial_ccmode_register_operand" "%r")
+				 (const_int 0)])
+		(match_operator 3 "even_relop"
+				[(match_operand 4 "partial_ccmode_register_operand" "r")
+				 (const_int 0)])))
+   (clobber (match_operand:SI 5 "register_operand" "=r"))]
+  "GET_CODE (operands[1]) == reverse_condition (GET_CODE (operands[3]))"
+  [(set (match_dup 5)
+	(and:CCEVEN (not:CC (match_dup 2))
+		(match_dup 4)))
+   (set (match_dup 0)
+	(match_op_dup 3 [(match_dup 5) (const_int 0)]))]
+  "operands[5] = gen_rtx(SUBREG, CCEVENmode, operands[5], 0);")
+
 
 ;; Logical operations on compare words.
 
 (define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(and:CC (not:CC (match_operand:CC 1 "register_operand" "r"))
-		(match_operand:CC 2 "register_operand" "r")))]
+  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+	(and:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r"))
+		(match_operand 2 "partial_ccmode_register_operand" "r")))]
   ""
   "and.c %0,%2,%1")
 
-
 (define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(and:CC (match_operand:CC 1 "register_operand" "%r")
-		(match_operand:CC 2 "register_operand" "r")))]
+  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+	(and:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r")
+		(match_operand 2 "partial_ccmode_register_operand" "r")))]
   ""
   "and %0,%1,%2")
 
 (define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(ior:CC (not:CC (match_operand:CC 1 "register_operand" "r"))
-		(match_operand:CC 2 "register_operand" "r")))]
+  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+	(ior:CCEVEN (not:CC (match_operand 1 "partial_ccmode_register_operand" "r"))
+		(match_operand 2 "partial_ccmode_register_operand" "r")))]
   ""
   "or.c %0,%2,%1")
 
 (define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(ior:CC (match_operand:CC 1 "register_operand" "%r")
-		(match_operand:CC 2 "register_operand" "r")))]
+  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+	(ior:CCEVEN (match_operand 1 "partial_ccmode_register_operand" "%r")
+		(match_operand 2 "partial_ccmode_register_operand" "r")))]
   ""
   "or %0,%1,%2")
 
@@ -573,95 +766,104 @@
   "rot %0,%1,%2"
   [(set_attr "type" "bit")])
 
+(define_insn ""
+  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+	(rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
+		   (match_operand:CC 2 "int5_operand" "")))]
+  ""
+  "rot %0,%1,%2"
+  [(set_attr "type" "bit")])
+
 ;; rotate/and[.c] and rotate/ior[.c]
 
 (define_split
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(ior:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+	(ior:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
 			   (match_operand:CC 2 "int5_operand" ""))
-		(match_operand:CC 3 "register_operand" "r")))
-   (clobber (match_operand:CC 4 "register_operand" "=r"))]
+		(match_operand 3 "partial_ccmode_register_operand" "r")))
+   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
   ""
   [(set (match_dup 4)
 	(rotate:CC (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
-	(ior:CC (match_dup 4) (match_dup 3)))]
+	(ior:CCEVEN (match_dup 4) (match_dup 3)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(ior:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+	(ior:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
 			   (match_operand:CC 2 "int5_operand" ""))
-		(match_operand:CC 3 "register_operand" "r")))
-   (clobber (match_scratch:CC 4 "=r"))]
+		(match_operand 3 "partial_ccmode_register_operand" "r")))
+   (clobber (match_scratch:CCEVEN 4 "=r"))]
   ""
   "#")
 
 (define_split
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(ior:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+	(ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
 				   (match_operand:CC 2 "int5_operand" "")))
-		(match_operand:CC 3 "register_operand" "r")))
-   (clobber (match_operand:CC 4 "register_operand" "=r"))]
+		(match_operand 3 "partial_ccmode_register_operand" "r")))
+   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
   ""
   [(set (match_dup 4)
 	(rotate:CC (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
-	(ior:CC (not:CC (match_dup 4)) (match_dup 3)))]
+	(ior:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(ior:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+	(ior:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
 				   (match_operand:CC 2 "int5_operand" "")))
-		(match_operand:CC 3 "register_operand" "r")))
-   (clobber (match_scratch:CC 4 "=r"))]
+		(match_operand 3 "partial_ccmode_register_operand" "r")))
+   (clobber (match_scratch:CCEVEN 4 "=r"))]
   ""
   "#")
 
 (define_split
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(and:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+	(and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
 			   (match_operand:CC 2 "int5_operand" ""))
-		(match_operand:CC 3 "register_operand" "r")))
-   (clobber (match_operand:CC 4 "register_operand" "=r"))]
+		(match_operand 3 "partial_ccmode_register_operand" "r")))
+   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
   ""
   [(set (match_dup 4)
 	(rotate:CC (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
-	(and:CC (match_dup 4) (match_dup 3)))]
+	(and:CCEVEN (match_dup 4) (match_dup 3)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(and:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+	(and:CCEVEN (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
 			   (match_operand:CC 2 "int5_operand" ""))
-		(match_operand:CC 3 "register_operand" "r")))
-   (clobber (match_scratch:CC 4 "=r"))]
+		(match_operand 3 "partial_ccmode_register_operand" "r")))
+   (clobber (match_scratch:CCEVEN 4 "=r"))]
   ""
   "#")
 
 (define_split
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(and:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+	(and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
 				   (match_operand:CC 2 "int5_operand" "")))
-		(match_operand:CC 3 "register_operand" "r")))
-   (clobber (match_operand:CC 4 "register_operand" "=r"))]
+		(match_operand 3 "partial_ccmode_register_operand" "r")))
+   (clobber (match_operand:CCEVEN 4 "register_operand" "=r"))]
   ""
   [(set (match_dup 4)
 	(rotate:CC (match_dup 1) (match_dup 2)))
    (set (match_dup 0)
-	(and:CC (not:CC (match_dup 4)) (match_dup 3)))]
+	(and:CCEVEN (not:CC (match_dup 4)) (match_dup 3)))]
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 0 "register_operand" "=r")
-	(and:CC (not:CC (rotate:CC (match_operand:CC 1 "register_operand" "r")
+  [(set (match_operand:CCEVEN 0 "register_operand" "=r")
+	(and:CCEVEN (not:CC (rotate:CC (match_operand 1 "partial_ccmode_register_operand" "r")
 				   (match_operand:CC 2 "int5_operand" "")))
-		(match_operand:CC 3 "register_operand" "r")))
-   (clobber (match_scratch:CC 4 "=r"))]
+		(match_operand 3 "partial_ccmode_register_operand" "r")))
+   (clobber (match_scratch:CCEVEN 4 "=r"))]
   ""
   "#")
+
 
 ;; Recognize bcnd instructions for integer values.  This is distinguished
 ;; from a conditional branch instruction (below) with SImode instead of
@@ -1179,6 +1381,44 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
+	(match_operator:SI 1 "even_relop"
+			   [(match_operand:CCEVEN 2 "register_operand" "r")
+			    (const_int 0)]))]
+  ""
+  "ext %0,%2,1<%C1>"
+  [(set_attr "type" "bit")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(not:SI (match_operator:SI 1 "odd_relop"
+			   [(match_operand:CCEVEN 2 "register_operand" "r")
+			    (const_int 0)])))]
+  ""
+  "ext %0,%2,1<%!%C1>"
+  [(set_attr "type" "bit")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(match_operator:SI 1 "odd_relop"
+			   [(match_operand:CCEVEN 2 "register_operand" "r")
+			    (const_int 0)]))
+   (clobber (match_operand:SI 3 "register_operand" "=r"))]
+  ""
+  [(set (match_dup 3) (not:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])))
+   (set (match_dup 0) (not:SI (match_dup 3)))]
+  "")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(match_operator:SI 1 "odd_relop"
+			   [(match_operand:CCEVEN 2 "register_operand" "r")
+			    (const_int 0)]))
+   (clobber (match_scratch:SI 3 "=r"))]
+  ""
+  "#")
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
 	(neg:SI
 	 (match_operator:SI 1 "relop"
 			    [(match_operand:CC 2 "register_operand" "r")
@@ -1186,6 +1426,51 @@
   ""
   "extu %0,%2,1<%C1>"
   [(set_attr "type" "bit")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(neg:SI
+	 (match_operator:SI 1 "even_relop"
+			    [(match_operand:CCEVEN 2 "register_operand" "r")
+			     (const_int 0)])))]
+  ""
+  "extu %0,%2,1<%C1>"
+  [(set_attr "type" "bit")])
+
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(neg:SI
+	 (not:SI (match_operator:SI 1 "odd_relop"
+			    [(match_operand:CCEVEN 2 "register_operand" "r")
+			     (const_int 0)]))))]
+  ""
+  "extu %0,%2,1<%!%C1>"
+  [(set_attr "type" "bit")])
+
+(define_split
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(neg:SI (match_operator:SI 1 "odd_relop"
+			   [(match_operand:CCEVEN 2 "register_operand" "r")
+			    (const_int 0)])))
+   (clobber (match_operand:SI 3 "register_operand" "=r"))]
+  ""
+  [(set (match_dup 3) (neg:SI (not:SI (match_op_dup 1 [(match_dup 2)
+                                                       (const_int 0)]))))
+   (set (match_dup 0) (xor:SI (match_dup 3) (const_int 1)))]
+  "")
+
+(define_insn
+ ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(neg:SI (match_operator:SI 1 "odd_relop"
+			   [(match_operand:CCEVEN 2 "register_operand" "r")
+			    (const_int 0)])))
+   (clobber (match_scratch:SI 3 "=r"))]
+  ""
+  "#")
+
+
+
 
 ;; Conditional branch insns.  The compare insns set a register
 ;; rather than cc0 and record that register for use here.  See above
@@ -1360,8 +1645,38 @@
 }"
   [(set_attr "type" "branch")])
 
+;;
+;; Here branch prediction is sacrificed. To get it back, you need 
+;;  - CCODD (CC mode where the ODD bits are valid)
+;;  - several define_split that can apply De Morgan's Law.
+;;  - transformations between CCEVEN and CCODD modes. 
+;;  
+
+(define_insn ""
+  [(set (pc) (if_then_else
+	      (match_operator 0 "even_relop"
+			      [(match_operand:CCEVEN 1 "register_operand" "r")
+			       (const_int 0)])
+	      (match_operand 2 "pc_or_label_ref" "")
+	      (match_operand 3 "pc_or_label_ref" "")))]
+  ""
+  "bb%L2%. %C0,%1,%P2%P3"
+  [(set_attr "type" "branch")])
+
+(define_insn ""
+  [(set (pc) (if_then_else
+	      (match_operator 0 "odd_relop"
+			      [(match_operand:CCEVEN 1 "register_operand" "r")
+			       (const_int 0)])
+	      (match_operand 2 "pc_or_label_ref" "")
+	      (match_operand 3 "pc_or_label_ref" "")))]
+  ""
+  "bb%L3%. %!%C0,%1,%P2%P3"
+  [(set_attr "type" "branch")])
+
 ;; Branch conditional on scc values.  These arise from manipulations on
 ;; compare words above.
+;; Are these really used ? 
 
 (define_insn ""
   [(set (pc)
@@ -1379,6 +1694,32 @@
 (define_insn ""
   [(set (pc)
 	(if_then_else
+	 (ne (match_operator 0 "even_relop"
+			     [(match_operand:CCEVEN 1 "register_operand" "r")
+			      (const_int 0)])
+	     (const_int 0))
+	 (match_operand 2 "pc_or_label_ref" "")
+	 (match_operand 3 "pc_or_label_ref" "")))]
+  ""
+  "bb%L2 %C0,%1,%P2%P3"
+  [(set_attr "type" "branch")])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else
+	 (ne (match_operator 0 "odd_relop"
+			     [(match_operand:CCEVEN 1 "register_operand" "r")
+			      (const_int 0)])
+	     (const_int 0))
+	 (match_operand 2 "pc_or_label_ref" "")
+	 (match_operand 3 "pc_or_label_ref" "")))]
+  ""
+  "bb%L3 %!%C0,%1,%P2%P3"
+  [(set_attr "type" "branch")])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else
 	 (eq (match_operator 0 "relop"
 			     [(match_operand:CC 1 "register_operand" "r")
 			      (const_int 0)])
@@ -1388,6 +1729,32 @@
   ""
   "bb%L3 %C0,%1,%P2%P3"
   [(set_attr "type" "branch")])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else
+	 (eq (match_operator 0 "even_relop"
+			     [(match_operand:CCEVEN 1 "register_operand" "r")
+			      (const_int 0)])
+	     (const_int 0))
+	 (match_operand 2 "pc_or_label_ref" "")
+	 (match_operand 3 "pc_or_label_ref" "")))]
+  ""
+  "bb%L3 %C0,%1,%P2%P3"
+  [(set_attr "type" "branch")])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else
+	 (eq (match_operator 0 "odd_relop"
+			     [(match_operand:CCEVEN 1 "register_operand" "r")
+			      (const_int 0)])
+	     (const_int 0))
+	 (match_operand 2 "pc_or_label_ref" "")
+	 (match_operand 3 "pc_or_label_ref" "")))]
+  ""
+  "bb%L2 %!%C0,%1,%P2%P3"
+  [(set_attr "type" "branch")])
 
 (define_insn "locate1"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1471,12 +1838,35 @@
   ""
   "or %0,%1,%#lo16(%g2)")
 
+;; For PIC, symbol_refs are put inside unspec so that the optimizer won't
+;; confuse them with real addresses.
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
+		   (unspec:SI [(match_operand:SI 2 "immediate_operand" "in")] 0)))]
+  ""
+  "or %0,%1,%#lo16(%g2)"
+  ;; Need to set length for this arith insn because operand2
+  ;; is not an "arith_operand".
+  [(set_attr "length" "1")])
+
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(high:SI (match_operand 1 "" "")))]
   ""
   "or.u %0,%#r0,%#hi16(%g1)")
 
+;; For PIC, symbol_refs are put inside unspec so that the optimizer won't
+;; confuse them with real addresses.
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "=r")
+	(high:SI (unspec:SI [(match_operand 1 "" "")] 0)))]
+  ""
+  "or.u %0,%#r0,%#hi16(%g1)"
+  ;; Need to set length for this arith insn because operand2
+  ;; is not an arith_operand.
+  [(set_attr "length" "1")])
+
 ;; HImode move instructions
 
 (define_expand "movhi"
@@ -1604,6 +1994,20 @@
     DONE;
 }")
 
+(define_split
+  [(set (match_operand:DF 0 "register_operand" "=r")
+	(match_operand:DF 1 "register_operand" "r"))]
+  "reload_completed
+   && GET_CODE (operands[0]) == REG && !XRF_REGNO_P (REGNO (operands[0]))
+   && GET_CODE (operands[1]) == REG && !XRF_REGNO_P (REGNO (operands[1]))"
+  [(set (match_dup 2) (match_dup 3))
+   (set (match_dup 4) (match_dup 5))]
+  "
+{ operands[2] = operand_subword (operands[0], 0, 0, DFmode);
+  operands[3] = operand_subword (operands[1], 0, 0, DFmode);
+  operands[4] = operand_subword (operands[0], 1, 0, DFmode);
+  operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
+
 ;; @@ This pattern is incomplete and doesn't appear necessary.
 ;;
 ;; This pattern forces (set (reg:DF ...) (const_double ...))
@@ -2313,7 +2717,7 @@
 
 ;;- multiply instructions
 ;;
-;; There is an unfounded silicon eratta for E.1 requiring that an
+;; There is an unfounded silicon errata for E.1 requiring that an
 ;; immediate constant value in div/divu/mul instructions be less than
 ;; 0x800.  This is no longer provided for.
 
@@ -2325,13 +2729,14 @@
   "mul %0,%1,%2"
   [(set_attr "type" "imul")])
 
-(define_insn "umulsidi3"
-  [(set (match_operand:DI 0 "register_operand" "=r")
-        (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
-                 (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
-  "TARGET_88110"
-  "mulu.d %0,%1,%2"
-  [(set_attr "type" "imul")])
+;; Loses for acvs/P60504.c (mod case) on 88110
+;; (define_insn "umulsidi3"
+;;   [(set (match_operand:DI 0 "register_operand" "=r")
+;;         (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "%r"))
+;;                  (zero_extend:DI (match_operand:SI 2 "register_operand" "r"))))]
+;;   "TARGET_88110"
+;;   "mulu.d %0,%1,%2"
+;;   [(set_attr "type" "imul")])
 
 ;; patterns for mixed mode floating point
 ;; Do not define patterns that utilize mixed mode arithmetic that result
@@ -2407,9 +2812,9 @@
 ;; for divide-by-zero or take your chances.  If the div instruction is
 ;; used, the O/S must complete the operation if the operands are
 ;; negative.  The O/S will signal an overflow condition if the most
-;; negative number (-214783648) is divided by negative 1.
+;; negative number (-2147483648) is divided by negative 1.
 ;;
-;; There is an unfounded silicon eratta for E.1 requiring that an
+;; There is an unfounded silicon errata for E.1 requiring that an
 ;; immediate constant value in div/divu/mul instructions be less than
 ;; 0x800.  This is no longer provided for.
 
@@ -3160,28 +3565,7 @@
   [(set_attr "type" "bit")])
 
 ;;- logical shift instructions.  Logical shift left becomes arithmetic
-;; shift left.  LSHIFT is not normally produced, but is supported.
-
-(define_expand "lshlsi3"
-  [(set (match_operand:SI 0 "register_operand" "")
-	(lshift:SI (match_operand:SI 1 "register_operand" "")
-		   (match_operand:SI 2 "arith32_operand" "")))]
-  ""
-  "
-{
-  emit_insn (gen_ashlsi3 (operands[0], operands[1], operands[2]));
-  DONE;
-}")
-
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=r,r")
-	(lshift:SI (match_operand:SI 1 "register_operand" "r,r")
-		   (match_operand:SI 2 "arith5_operand" "r,K")))]
-  ""
-  "@
-   mak %0,%1,%2
-   mak %0,%1,0<%2>"
-  [(set_attr "type" "bit")])
+;; shift left.  
 
 (define_expand "lshrsi3"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -3470,7 +3854,7 @@
     emit_jump_insn (gen_casesi_enter (label, index_diff, operands[3]));
   else
     /* Load the table entry and jump to it.  */
-    emit_jump_insn (gen_casesi_jump (gen_reg_rtx (SImode), base, index_diff));
+    emit_jump_insn (gen_casesi_jump (gen_reg_rtx (SImode), base, index_diff, operands[3]));
 
   /* Claim that flow drops into the table so it will be adjacent by not
      emitting a barrier.  */
@@ -3482,10 +3866,18 @@
 	(mem:SI (plus:SI (match_operand:SI 1 "" "")
 			 (mult:SI (match_operand:SI 2 "" "")
 				  (const_int 4)))))
-   (set (pc) (match_dup 0))]
+   (parallel [(set (pc) (match_dup 0))
+              (use (label_ref (match_operand 3 "" "")))])]
   ""
   "")
 
+(define_insn ""
+  [(set (pc) (match_operand:SI 0 "register_operand" "r"))
+   (use (label_ref (match_operand 1 "" "")))]
+  ""
+  "jmp%. %0"
+  [(set_attr "type" "jump")])
+
 ;; The bsr.n instruction is directed to the END of the table.  See
 ;; ASM_OUTPUT_CASE_END.