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1.1 root 1: /* Definitions of target machine for GNU compiler. MIPS version.
2: Contributed by A. Lichnewsky, [email protected]
3: Changed by Michael Meissner, [email protected]
4: Copyright (C) 1989, 1990, 1991, 1992 Free Software Foundation, Inc.
5:
6: This file is part of GNU CC.
7:
8: GNU CC is free software; you can redistribute it and/or modify
9: it under the terms of the GNU General Public License as published by
10: the Free Software Foundation; either version 2, or (at your option)
11: any later version.
12:
13: GNU CC is distributed in the hope that it will be useful,
14: but WITHOUT ANY WARRANTY; without even the implied warranty of
15: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: GNU General Public License for more details.
17:
18: You should have received a copy of the GNU General Public License
19: along with GNU CC; see the file COPYING. If not, write to
20: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
21:
22:
23: /* Make Saber happier on obstack.[ch]. */
24: #if defined(__mips__) || defined(mips)
25: #define __PTR_TO_INT(P) ((int)(P))
26: #define __INT_TO_PTR(P) ((char *)(P))
27: #endif
28:
29: /* Standard GCC variables that we reference. */
30:
31: extern int target_flags;
32: extern int optimize;
33: extern int may_call_alloca;
34: extern int current_function_calls_alloca;
35: extern int frame_pointer_needed;
36: extern int flag_omit_frame_pointer;
37:
38: /* MIPS external variables defined in mips.c. */
39:
40: /* comparison type */
41: enum cmp_type {
42: CMP_SI, /* compare integers */
43: CMP_SF, /* compare single precision floats */
44: CMP_DF, /* compare double precision floats */
45: CMP_MAX /* max comparison type */
46: };
47:
48: /* types of delay slot */
49: enum delay_type {
50: DELAY_NONE, /* no delay slot */
51: DELAY_LOAD, /* load from memory delay */
52: DELAY_HILO /* move from/to hi/lo registers */
53: };
54:
55: /* Which processor to schedule for. Since there is no difference between
56: a R2000 and R3000 in terms of the scheduler, we collapse them into
57: just an R3000. */
58:
59: enum processor_type {
60: PROCESSOR_DEFAULT,
61: PROCESSOR_R3000,
62: PROCESSOR_R6000,
63: PROCESSOR_R4000
64: };
65:
66: extern char mips_reg_names[][8]; /* register names (a0 vs. $4). */
67: extern char mips_print_operand_punct[]; /* print_operand punctuation chars */
68: extern char *current_function_name; /* current function being compiled */
69: extern char *current_function_file; /* filename current function is in */
70: extern int num_source_filenames; /* current .file # */
71: extern int inside_function; /* != 0 if inside of a function */
72: extern int ignore_line_number; /* != 0 if we are to ignore next .loc */
73: extern int file_in_function_warning; /* warning given about .file in func */
74: extern int sdb_label_count; /* block start/end next label # */
75: extern int mips_section_threshold; /* # bytes of data/sdata cutoff */
76: extern int g_switch_value; /* value of the -G xx switch */
77: extern int g_switch_set; /* whether -G xx was passed. */
78: extern int sym_lineno; /* sgi next label # for each stmt */
79: extern int set_noreorder; /* # of nested .set noreorder's */
80: extern int set_nomacro; /* # of nested .set nomacro's */
81: extern int set_noat; /* # of nested .set noat's */
82: extern int set_volatile; /* # of nested .set volatile's */
83: extern int mips_branch_likely; /* emit 'l' after br (branch likely) */
84: extern int mips_dbx_regno[]; /* Map register # to debug register # */
85: extern char mips_rtx_classify[]; /* classify an RTX code */
86: extern struct rtx_def *branch_cmp[2]; /* operands for compare */
87: extern enum cmp_type branch_type; /* what type of branch to use */
88: extern enum processor_type mips_cpu; /* which cpu are we scheduling for */
89: extern int mips_isa; /* architectural level */
90: extern char *mips_cpu_string; /* for -mcpu=<xxx> */
91: extern char *mips_isa_string; /* for -mips{1,2,3} */
92: extern int dslots_load_total; /* total # load related delay slots */
93: extern int dslots_load_filled; /* # filled load delay slots */
94: extern int dslots_jump_total; /* total # jump related delay slots */
95: extern int dslots_jump_filled; /* # filled jump delay slots */
96: extern int dslots_number_nops; /* # of nops needed by previous insn */
97: extern int num_refs[3]; /* # 1/2/3 word references */
98: extern struct rtx_def *mips_load_reg; /* register to check for load delay */
99: extern struct rtx_def *mips_load_reg2; /* 2nd reg to check for load delay */
100: extern struct rtx_def *mips_load_reg3; /* 3rd reg to check for load delay */
101: extern struct rtx_def *mips_load_reg4; /* 4th reg to check for load delay */
102:
103: /* Functions within mips.c that we reference. */
104:
105: extern void abort_with_insn ();
106: extern int arith32_operand ();
107: extern int arith_operand ();
108: extern int call_memory_operand ();
109: extern int cmp_op ();
110: extern int cmp2_op ();
111: extern unsigned long compute_frame_size ();
112: extern void expand_block_move ();
113: extern int equality_op ();
114: extern int fcmp_op ();
115: extern struct rtx_def * function_arg ();
116: extern void function_arg_advance ();
117: extern int function_arg_partial_nregs ();
118: extern void function_epilogue ();
119: extern void function_prologue ();
120: extern void gen_conditional_branch ();
121: extern void init_cumulative_args ();
122: extern int large_int ();
123: extern int md_register_operand ();
124: extern int mips_address_cost ();
125: extern void mips_asm_file_end ();
126: extern void mips_asm_file_start ();
127: extern int mips_const_double_ok ();
128: extern void mips_count_memory_refs ();
129: extern int mips_debugger_offset ();
130: extern int mips_epilogue_delay_slots ();
131: extern char *mips_fill_delay_slot ();
132: extern char *mips_move_1word ();
133: extern char *mips_move_2words ();
134: extern int mips_output_external ();
135: extern void mips_output_filename ();
136: extern void mips_output_lineno ();
137: extern void override_options ();
138: extern void print_operand_address ();
139: extern void print_operand ();
140: extern void print_options ();
141: extern int reg_or_0_operand ();
142: extern int simple_memory_operand ();
143: extern int small_int ();
144: extern void trace();
145: extern int uns_arith_operand ();
146: extern int uns_cmp_op ();
147:
148: /* Functions in varasm.c that we reference. */
149: extern void data_section ();
150: extern void rdata_section ();
151: extern void readonly_data_section ();
152: extern void sdata_section ();
153: extern void text_section ();
154:
155: /* Stubs for half-pic support if not OSF/1 reference platform. */
156:
157: #ifndef HALF_PIC_P
158: #define HALF_PIC_P() 0
159: #define HALF_PIC_ENCODE(DECL)
160: #define HALF_PIC_INIT() error ("half-pic init called on systems that don't support it.")
161: #define HALF_PIC_ADDRESS_P(X) 0
162: #endif
163:
164:
165: /* Switch Recognition by gcc.c. Add -G xx support */
166:
167: #ifdef SWITCH_TAKES_ARG
168: #undef SWITCH_TAKES_ARG
169: #endif
170:
171: #define SWITCH_TAKES_ARG(CHAR) \
172: ((CHAR) == 'D' || (CHAR) == 'U' || (CHAR) == 'o' \
173: || (CHAR) == 'e' || (CHAR) == 'T' || (CHAR) == 'u' \
174: || (CHAR) == 'I' || (CHAR) == 'm' \
175: || (CHAR) == 'L' || (CHAR) == 'A' || (CHAR) == 'G')
176:
177: /* Sometimes certain combinations of command options do not make sense
178: on a particular target machine. You can define a macro
179: `OVERRIDE_OPTIONS' to take account of this. This macro, if
180: defined, is executed once just after all the command options have
181: been parsed.
182:
183: On the MIPS, it is used to handle -G. We also use it to set up all
184: of the tables referenced in the other macros. */
185:
186: #define OVERRIDE_OPTIONS override_options ()
187:
188: /* Zero or more C statements that may conditionally modify two
189: variables `fixed_regs' and `call_used_regs' (both of type `char
190: []') after they have been initialized from the two preceding
191: macros.
192:
193: This is necessary in case the fixed or call-clobbered registers
194: depend on target flags.
195:
196: You need not define this macro if it has no work to do.
197:
198: If the usage of an entire class of registers depends on the target
199: flags, you may indicate this to GCC by using this macro to modify
200: `fixed_regs' and `call_used_regs' to 1 for each of the registers in
201: the classes which should not be used by GCC. Also define the macro
202: `REG_CLASS_FROM_LETTER' to return `NO_REGS' if it is called with a
203: letter for a class that shouldn't be used.
204:
205: (However, if this class is not included in `GENERAL_REGS' and all
206: of the insn patterns whose constraints permit this class are
207: controlled by target switches, then GCC will automatically avoid
208: using these registers when the target switches are opposed to
209: them.) */
210:
211: #define CONDITIONAL_REGISTER_USAGE \
212: do \
213: { \
214: if (!TARGET_HARD_FLOAT) \
215: { \
216: int regno; \
217: \
218: for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) \
219: fixed_regs[regno] = call_used_regs[regno] = 1; \
220: } \
221: } \
222: while (0)
223:
224:
225: /* Some machines may desire to change what optimizations are
226: performed for various optimization levels. This macro, if
227: defined, is executed once just after the optimization level is
228: determined and before the remainder of the command options have
229: been parsed. Values set in this macro are used as the default
230: values for the other command line options.
231:
232: LEVEL is the optimization level specified; 2 if -O2 is
233: specified, 1 if -O is specified, and 0 if neither is specified. */
234:
235: #define OPTIMIZATION_OPTIONS(LEVEL) \
236: { \
237: if (LEVEL) \
238: { \
239: flag_omit_frame_pointer = TRUE; \
240: flag_delayed_branch = TRUE; \
241: flag_thread_jumps = TRUE; \
242: flag_schedule_insns_after_reload = TRUE; \
243: } \
244: \
245: if (LEVEL >= 2) \
246: { \
247: flag_strength_reduce = TRUE; \
248: flag_cse_follow_jumps = TRUE; \
249: flag_expensive_optimizations = TRUE; \
250: flag_rerun_cse_after_loop = TRUE; \
251: flag_schedule_insns = TRUE; \
252: flag_caller_saves = TRUE; \
253: } \
254: \
255: if (LEVEL >= 3) \
256: { \
257: flag_inline_functions = TRUE; \
258: } \
259: }
260:
261:
262:
263: /* Complain about missing specs and predefines that should be defined in each
264: of the target tm files to override the defaults. This is mostly a place-
265: holder until I can get each of the files updated [mm]. */
266:
267: #if defined(OSF_OS) \
268: || defined(DECSTATION) \
269: || defined(SGI_TARGET) \
270: || defined(MIPS_NEWS) \
271: || defined(MIPS_SYSV) \
272: || defined(MIPS_BSD43)
273:
274: #ifndef CPP_PREDEFINES
275: #error "Define CPP_PREDEFINES in the appropriate tm.h file"
276: #endif
277:
278: #ifndef CPP_SPEC
279: #error "Define CPP_SPEC in the appropriate tm.h file"
280: #endif
281:
282: #ifndef LINK_SPEC
283: #error "Define LINK_SPEC in the appropriate tm.h file"
284: #endif
285:
286: #ifndef LIB_SPEC
287: #error "Define LIB_SPEC in the appropriate tm.h file"
288: #endif
289:
290: #ifndef STARTFILE_SPEC
291: #error "Define STARTFILE_SPEC in the appropriate tm.h file"
292: #endif
293:
294: #ifndef MACHINE_TYPE
295: #error "Define MACHINE_TYPE in the appropriate tm.h file"
296: #endif
297: #endif
298:
299:
300: /* Names to predefine in the preprocessor for this target machine. */
301:
302: #ifndef CPP_PREDEFINES
303: #define CPP_PREDEFINES "-Dmips -Dunix -Dhost_mips -DMIPSEB -DR3000"
304: #endif
305:
306: /* Extra switches sometimes passed to the assembler. */
307:
308: #ifndef ASM_SPEC
309: #define ASM_SPEC "\
310: %{!mgas: \
311: %{!mrnames: -nocpp} \
312: %{pipe: %e-pipe is not supported.} \
313: %{EB} %{!EB:-EB} \
314: %{EL: %e-EL not supported} \
315: %{O:-O2} %{O1:-O2} %{O2:-O2} %{O3:-O3} \
316: %{g} %{g0} %{g1} %{g2} %{g3} %{v} %{K}} \
317: %{G*}"
318:
319: #endif /* ASM_SPEC */
320:
321: /* Specify to run a post-processor, mips-tfile after the assembler
322: has run to stuff the mips debug information into the object file.
323: This is needed because the $#!%^ MIPS assembler provides no way
324: of specifing such information in the assembly file. */
325:
326: #ifndef ASM_FINAL_SPEC
327: #define ASM_FINAL_SPEC "\
328: %{!mgas: %{!mno-mips-tfile: \
329: \n mips-tfile %{v*: -v} \
330: %{K: -I %b.o~} \
331: %{!K: %{save-temps: -I %b.o~}} \
332: %{c:%W{o*}%{!o*:-o %b.o}}%{!c:-o %b.o} \
333: %{.s:%i} %{!.s:%g.s}}}"
334: #endif
335:
336: /* Redefinition of libraries used. Mips doesn't support normal
337: UNIX style profiling via calling _mcount. It does offer
338: profiling that samples the PC, so do what we can... */
339:
340: #ifndef LIB_SPEC
341: #define LIB_SPEC "%{pg:-lprof1} %{p:-lprof1} -lc"
342: #endif
343:
344: /* Extra switches sometimes passed to the linker. */
345:
346: #ifndef LINK_SPEC
347: #define LINK_SPEC "\
348: %{G*} \
349: %{!mgas: \
350: %{pipe: %e-pipe is not supported.} \
351: %{EB} %{!EB:-EB} \
352: %{EL: %e-EL not supported} \
353: %{bestGnum}}"
354: #endif /* LINK_SPEC defined */
355:
356: /* Specs for the compiler proper */
357:
358: #ifndef CC1_SPEC
359: #define CC1_SPEC "\
360: %{O*: %{!mno-gpOPT:%{!mno-gpopt: -mgpopt}}} \
361: %{gline:%{!g:%{!g0:%{!g1:%{!g2: -g1}}}}} \
362: %{G*} \
363: %{pic-none: -mno-half-pic} \
364: %{pic-lib: -mhalf-pic} \
365: %{pic-extern: -mhalf-pic} \
366: %{pic-calls: -mhalf-pic} \
367: %{save-temps: }"
368: #endif
369:
370: #ifndef CC1PLUS_SPEC
371: #define CC1PLUS_SPEC "%{!fgnu-binutils: -fno-gnu-binutils}"
372: #endif
373:
374: /* Preprocessor specs */
375:
376: #ifndef CPP_SPEC
377: #define CPP_SPEC "\
378: %{!ansi:-DSYSTYPE_BSD} -D__SYSTYPE_BSD__ \
379: %{.cc: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
380: %{.cxx: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
381: %{.C: -D__LANGUAGE_C_PLUS_PLUS -D_LANGUAGE_C_PLUS_PLUS} \
382: %{.m: -D__LANGUAGE_OBJECTIVE_C -D_LANGUAGE_OBJECTIVE_C} \
383: %{.S: -D__LANGUAGE_ASSEMBLY -D_LANGUAGE_ASSEMBLY %{!ansi:-DLANGUAGE_ASSEMBLY}} \
384: %{!.S: -D__LANGUAGE_C -D_LANGUAGE_C %{!ansi:-DLANGUAGE_C}}"
385: #endif
386:
387: /* If defined, this macro is an additional prefix to try after
388: `STANDARD_EXEC_PREFIX'. */
389:
390: #ifndef MD_EXEC_PREFIX
391: #define MD_EXEC_PREFIX "/usr/lib/cmplrs/cc"
392: #endif
393:
394:
395: /* Print subsidiary information on the compiler version in use. */
396:
397: #define MIPS_VERSION "[AL 1.1, MM 12]"
398:
399: #ifndef MACHINE_TYPE
400: #define MACHINE_TYPE "BSD Mips"
401: #endif
402:
403: #ifndef TARGET_VERSION_INTERNAL
404: #define TARGET_VERSION_INTERNAL(STREAM) \
405: fprintf (STREAM, " %s %s", MIPS_VERSION, MACHINE_TYPE)
406: #endif
407:
408: #ifndef TARGET_VERSION
409: #define TARGET_VERSION TARGET_VERSION_INTERNAL (stderr)
410: #endif
411:
412:
413: #define SDB_DEBUGGING_INFO /* generate info for mips-tfile */
414: #define DBX_DEBUGGING_INFO /* generate stabs (OSF/rose) */
415: #define MIPS_DEBUGGING_INFO /* MIPS specific debugging info */
416:
417: #ifndef PREFERRED_DEBUGGING_TYPE /* assume SDB_DEBUGGING_INFO */
418: #define PREFERRED_DEBUGGING_TYPE SDB_DEBUG
419: #endif
420:
421: /* If we are passing smuggling stabs through the MIPS ECOFF object
422: format, put a comment in front of the .stab<x> operation so
423: that the MIPS assembler does not choke. The mips-tfile program
424: will correctly put the stab into the object file. */
425:
426: #define ASM_STABS_OP ((TARGET_GAS) ? ".stabs" : " #.stabs")
427: #define ASM_STABN_OP ((TARGET_GAS) ? ".stabn" : " #.stabn")
428: #define ASM_STABD_OP ((TARGET_GAS) ? ".stabd" : " #.stabd")
429:
430: /* Forward references to tags are allowed. */
431: #define SDB_ALLOW_FORWARD_REFERENCES
432:
433: /* Unknown tags are also allowed. */
434: #define SDB_ALLOW_UNKNOWN_REFERENCES
435:
436: /* On Sun 4, this limit is 2048. We use 1500 to be safe,
437: since the length can run past this up to a continuation point. */
438: #define DBX_CONTIN_LENGTH 1500
439:
440:
441: /* How to renumber registers for dbx and gdb. */
442: #define DBX_REGISTER_NUMBER(REGNO) mips_dbx_regno[ (REGNO) ]
443:
444:
445: /* Overrides for the COFF debug format. */
446: #define PUT_SDB_SCL(a) \
447: do { \
448: extern FILE *asm_out_text_file; \
449: fprintf (asm_out_text_file, "\t.scl\t%d;", (a)); \
450: } while (0)
451:
452: #define PUT_SDB_INT_VAL(a) \
453: do { \
454: extern FILE *asm_out_text_file; \
455: fprintf (asm_out_text_file, "\t.val\t%d;", (a)); \
456: } while (0)
457:
458: #define PUT_SDB_VAL(a) \
459: do { \
460: extern FILE *asm_out_text_file; \
461: fputs ("\t.val\t", asm_out_text_file); \
462: output_addr_const (asm_out_text_file, (a)); \
463: fputc (';', asm_out_text_file); \
464: } while (0)
465:
466: #define PUT_SDB_DEF(a) \
467: do { \
468: extern FILE *asm_out_text_file; \
469: fprintf (asm_out_text_file, "\t#.def\t"); \
470: ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
471: fputc (';', asm_out_text_file); \
472: } while (0)
473:
474: #define PUT_SDB_PLAIN_DEF(a) \
475: do { \
476: extern FILE *asm_out_text_file; \
477: fprintf (asm_out_text_file, "\t#.def\t.%s;", (a)); \
478: } while (0)
479:
480: #define PUT_SDB_ENDEF \
481: do { \
482: extern FILE *asm_out_text_file; \
483: fprintf (asm_out_text_file, "\t.endef\n"); \
484: } while (0)
485:
486: #define PUT_SDB_TYPE(a) \
487: do { \
488: extern FILE *asm_out_text_file; \
489: fprintf (asm_out_text_file, "\t.type\t0x%x;", (a)); \
490: } while (0)
491:
492: #define PUT_SDB_SIZE(a) \
493: do { \
494: extern FILE *asm_out_text_file; \
495: fprintf (asm_out_text_file, "\t.size\t%d;", (a)); \
496: } while (0)
497:
498: #define PUT_SDB_DIM(a) \
499: do { \
500: extern FILE *asm_out_text_file; \
501: fprintf (asm_out_text_file, "\t.dim\t%d;", (a)); \
502: } while (0)
503:
504: #ifndef PUT_SDB_START_DIM
505: #define PUT_SDB_START_DIM \
506: do { \
507: extern FILE *asm_out_text_file; \
508: fprintf (asm_out_text_file, "\t.dim\t"); \
509: } while (0)
510: #endif
511:
512: #ifndef PUT_SDB_NEXT_DIM
513: #define PUT_SDB_NEXT_DIM(a) \
514: do { \
515: extern FILE *asm_out_text_file; \
516: fprintf (asm_out_text_file, "%d,", a); \
517: } while (0)
518: #endif
519:
520: #ifndef PUT_SDB_LAST_DIM
521: #define PUT_SDB_LAST_DIM(a) \
522: do { \
523: extern FILE *asm_out_text_file; \
524: fprintf (asm_out_text_file, "%d;", a); \
525: } while (0)
526: #endif
527:
528: #define PUT_SDB_TAG(a) \
529: do { \
530: extern FILE *asm_out_text_file; \
531: fprintf (asm_out_text_file, "\t.tag\t"); \
532: ASM_OUTPUT_LABELREF (asm_out_text_file, a); \
533: fputc (';', asm_out_text_file); \
534: } while (0)
535:
536: /* For block start and end, we create labels, so that
537: later we can figure out where the correct offset is.
538: The normal .ent/.end serve well enough for functions,
539: so those are just commented out. */
540:
541: #define PUT_SDB_BLOCK_START(LINE) \
542: do { \
543: extern FILE *asm_out_text_file; \
544: fprintf (asm_out_text_file, \
545: "$Lb%d:\n\t#.begin\t$Lb%d\t%d\n", \
546: sdb_label_count, \
547: sdb_label_count, \
548: (LINE)); \
549: sdb_label_count++; \
550: } while (0)
551:
552: #define PUT_SDB_BLOCK_END(LINE) \
553: do { \
554: extern FILE *asm_out_text_file; \
555: fprintf (asm_out_text_file, \
556: "$Le%d:\n\t#.bend\t$Le%d\t%d\n", \
557: sdb_label_count, \
558: sdb_label_count, \
559: (LINE)); \
560: sdb_label_count++; \
561: } while (0)
562:
563: #define PUT_SDB_FUNCTION_START(LINE)
564:
565: #define PUT_SDB_FUNCTION_END(LINE)
566:
567: #define PUT_SDB_EPILOGUE_END(NAME)
568:
569: #define SDB_GENERATE_FAKE(BUFFER, NUMBER) \
570: sprintf ((BUFFER), ".%dfake", (NUMBER));
571:
572: /* Correct the offset of automatic variables and arguments
573: if the frame pointer has been eliminated. */
574:
575: #define DEBUGGER_AUTO_OFFSET(X) mips_debugger_offset (X, 0)
576: #define DEBUGGER_ARG_OFFSET(OFFSET, X) mips_debugger_offset (X, OFFSET)
577:
578:
579: /* Tell collect that the object format is ECOFF */
580: #ifndef OBJECT_FORMAT_ROSE
581: #define OBJECT_FORMAT_COFF /* Object file looks like COFF */
582: #define EXTENDED_COFF /* ECOFF, not normal coff */
583: #endif
584:
585:
586: /* Run-time compilation parameters selecting different hardware subsets. */
587:
588: /* Macros used in the machine description to test the flags. */
589:
590: /* Bits for real switches */
591: #define MASK_INT64 0x00000001 /* ints are 64 bits */
592: #define MASK_LONG64 0x00000002 /* longs are 64 bits */
593: #define MASK_LLONG128 0x00000004 /* long longs are 128 bits */
594: #define MASK_GPOPT 0x00000008 /* Optimize for global pointer */
595: #define MASK_GAS 0x00000010 /* Gas used instead of MIPS as */
596: #define MASK_NAME_REGS 0x00000020 /* Use MIPS s/w reg name convention */
597: #define MASK_STATS 0x00000040 /* print statistics to stderr */
598: #define MASK_MEMCPY 0x00000080 /* call memcpy instead of inline code*/
599: #define MASK_SOFT_FLOAT 0x00000100 /* software floating point */
600: #define MASK_FLOAT64 0x00000200 /* fp registers are 64 bits */
601: #define MASK_ABICALLS 0x00000400 /* emit .abicalls/.cprestore/.cpload */
602: #define MASK_HALF_PIC 0x00000800 /* Emit OSF-style pic refs to externs*/
603: #define MASK_UNUSED1 0x00001000
604: #define MASK_UNUSED2 0x00002000
605: #define MASK_UNUSED3 0x00004000
606: #define MASK_UNUSED4 0x00008000
607: #define MASK_UNUSED5 0x00010000
608: #define MASK_UNUSED6 0x00020000
609: #define MASK_UNUSED7 0x00040000
610: #define MASK_UNUSED8 0x00080000
611:
612: /* Dummy switches used only in spec's*/
613: #define MASK_MIPS_TFILE 0x00000000 /* flag for mips-tfile usage */
614:
615: /* switches not used yet */
616: #define MASK_WC8 0x00000000 /* wchar's are 8 bits, not 32 */
617: #define MASK_WC16 0x00000000 /* wchar's are 16 bits, not 32 */
618: #define MASK_WC32 0x00000000 /* dummy for consistancy */
619:
620: /* Debug switches, not documented */
621: #define MASK_DEBUG 0x40000000 /* Eliminate version # in .s file */
622: #define MASK_DEBUG_A 0x20000000 /* don't allow <label>($reg) addrs */
623: #define MASK_DEBUG_B 0x10000000 /* GO_IF_LEGITIMATE_ADDRESS debug */
624: #define MASK_DEBUG_C 0x08000000 /* suppress normal divmod patterns */
625: #define MASK_DEBUG_D 0x04000000 /* make multiply cost 2 */
626: #define MASK_DEBUG_E 0x02000000 /* function_arg debug */
627: #define MASK_DEBUG_F 0x01000000 /* don't try to suppress load nop's */
628: #define MASK_DEBUG_G 0x00800000 /* don't support 64 bit arithmetic */
629: #define MASK_DEBUG_H 0x00400000 /* allow ints in FP registers */
630: #define MASK_DEBUG_I 0x00200000 /* unused */
631: #define MASK_DEBUG_J 0x00100000 /* unused */
632:
633: /* r4000 64 bit sizes */
634: #define TARGET_INT64 (target_flags & MASK_INT64)
635: #define TARGET_LONG64 (target_flags & MASK_LONG64)
636: #define TARGET_LLONG128 (target_flags & MASK_LLONG128)
637: #define TARGET_FLOAT64 (target_flags & MASK_FLOAT64)
638:
639: /* Mips vs. GNU assembler */
640: #define TARGET_GAS (target_flags & MASK_GAS)
641: #define TARGET_UNIX_ASM (!TARGET_GAS)
642: #define TARGET_MIPS_AS TARGET_UNIX_ASM
643:
644: /* Debug Mode */
645: #define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
646: #define TARGET_DEBUG_A_MODE (target_flags & MASK_DEBUG_A)
647: #define TARGET_DEBUG_B_MODE (target_flags & MASK_DEBUG_B)
648: #define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
649: #define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
650: #define TARGET_DEBUG_E_MODE (target_flags & MASK_DEBUG_E)
651: #define TARGET_DEBUG_F_MODE (target_flags & MASK_DEBUG_F)
652: #define TARGET_DEBUG_G_MODE (target_flags & MASK_DEBUG_G)
653: #define TARGET_DEBUG_H_MODE (target_flags & MASK_DEBUG_H)
654: #define TARGET_DEBUG_I_MODE (target_flags & MASK_DEBUG_I)
655: #define TARGET_DEBUG_J_MODE (target_flags & MASK_DEBUG_J)
656:
657: /* Reg. Naming in .s ($21 vs. $a0) */
658: #define TARGET_NAME_REGS (target_flags & MASK_NAME_REGS)
659:
660: /* Optimize for Sdata/Sbss */
661: #define TARGET_GP_OPT (target_flags & MASK_GPOPT)
662:
663: /* print program statistics */
664: #define TARGET_STATS (target_flags & MASK_STATS)
665:
666: /* call memcpy instead of inline code */
667: #define TARGET_MEMCPY (target_flags & MASK_MEMCPY)
668:
669: /* .abicalls, etc from Pyramid V.4 */
670: #define TARGET_ABICALLS (target_flags & MASK_ABICALLS)
671:
672: /* OSF pic references to externs */
673: #define TARGET_HALF_PIC (target_flags & MASK_HALF_PIC)
674:
675: /* wchar size */
676: #define TARGET_WC8 (target_flags & MASK_WC8)
677: #define TARGET_WC16 (target_flags & MASK_WC16)
678: #define TARGET_WC32 ((target_flags & (MASK_WC8 | MASK_WC16)) == 0)
679:
680: /* software floating point */
681: #define TARGET_SOFT_FLOAT (target_flags & MASK_SOFT_FLOAT)
682: #define TARGET_HARD_FLOAT (! TARGET_SOFT_FLOAT)
683:
684: /* Macro to define tables used to set the flags.
685: This is a list in braces of pairs in braces,
686: each pair being { "NAME", VALUE }
687: where VALUE is the bits to set or minus the bits to clear.
688: An empty string NAME is used to identify the default VALUE. */
689:
690: #define TARGET_SWITCHES \
691: { \
692: {"int64", MASK_INT64 | MASK_LONG64}, \
693: {"long64", MASK_LONG64}, \
694: {"longlong128", MASK_INT64 | MASK_LONG64 | MASK_LLONG128}, \
695: {"mips-as", -MASK_GAS}, \
696: {"gas", MASK_GAS}, \
697: {"rnames", MASK_NAME_REGS}, \
698: {"no-rnames", -MASK_NAME_REGS}, \
699: {"gpOPT", MASK_GPOPT}, \
700: {"gpopt", MASK_GPOPT}, \
701: {"no-gpOPT", -MASK_GPOPT}, \
702: {"no-gpopt", -MASK_GPOPT}, \
703: {"stats", MASK_STATS}, \
704: {"no-stats", -MASK_STATS}, \
705: {"memcpy", MASK_MEMCPY}, \
706: {"no-memcpy", -MASK_MEMCPY}, \
707: {"wc8", MASK_WC8}, \
708: {"wc16", MASK_WC16}, \
709: {"wc32", MASK_WC32}, \
710: {"mips-tfile", MASK_MIPS_TFILE}, \
711: {"no-mips-tfile", -MASK_MIPS_TFILE}, \
712: {"soft-float", MASK_SOFT_FLOAT}, \
713: {"hard-float", -MASK_SOFT_FLOAT}, \
714: {"fp64", MASK_FLOAT64}, \
715: {"fp32", -MASK_FLOAT64}, \
716: {"abicalls", MASK_ABICALLS}, \
717: {"no-abicalls", -MASK_ABICALLS}, \
718: {"half-pic", MASK_HALF_PIC}, \
719: {"no-half-pic", -MASK_HALF_PIC}, \
720: {"debug", MASK_DEBUG}, \
721: {"debuga", MASK_DEBUG_A}, \
722: {"debugb", MASK_DEBUG_B}, \
723: {"debugc", MASK_DEBUG_C}, \
724: {"debugd", MASK_DEBUG_D}, \
725: {"debuge", MASK_DEBUG_E}, \
726: {"debugf", MASK_DEBUG_F}, \
727: {"debugg", MASK_DEBUG_G}, \
728: {"debugh", MASK_DEBUG_H}, \
729: {"debugi", MASK_DEBUG_I}, \
730: {"debugj", MASK_DEBUG_J}, \
731: {"", TARGET_DEFAULT} \
732: }
733:
734: /* Default target_flags if no switches are specified */
735:
736: #ifndef TARGET_DEFAULT
737: #define TARGET_DEFAULT 0
738: #endif
739:
740: /* This macro is similar to `TARGET_SWITCHES' but defines names of
741: command options that have values. Its definition is an
742: initializer with a subgrouping for each command option.
743:
744: Each subgrouping contains a string constant, that defines the
745: fixed part of the option name, and the address of a variable.
746: The variable, type `char *', is set to the variable part of the
747: given option if the fixed part matches. The actual option name
748: is made by appending `-m' to the specified name.
749:
750: Here is an example which defines `-mshort-data-NUMBER'. If the
751: given option is `-mshort-data-512', the variable `m88k_short_data'
752: will be set to the string `"512"'.
753:
754: extern char *m88k_short_data;
755: #define TARGET_OPTIONS { { "short-data-", &m88k_short_data } } */
756:
757: #define TARGET_OPTIONS \
758: { \
759: { "cpu=", &mips_cpu_string }, \
760: { "ips", &mips_isa_string } \
761: }
762:
763: /* Macros to decide whether certain features are available or not,
764: depending on the instruction set architecture level. */
765:
766: #define BRANCH_LIKELY_P() (mips_isa >= 2)
767: #define HAVE_64BIT_P() (mips_isa >= 3)
768: #define HAVE_SQRT_P() (mips_isa >= 2)
769:
770:
771: /* Target machine storage layout */
772:
773: /* Define this if most significant bit is lowest numbered
774: in instructions that operate on numbered bit-fields.
775: */
776: /* #define BITS_BIG_ENDIAN */
777:
778: /* Define this if most significant byte of a word is the lowest numbered. */
779: #ifndef BYTES_BIG_ENDIAN
780: #ifndef DECSTATION
781: #define BYTES_BIG_ENDIAN 1
782: #else
783: #define BYTES_BIG_ENDIAN 0
784: #endif
785: #endif
786:
787: /* Define this if most significant word of a multiword number is the lowest. */
788: #ifndef WORDS_BIG_ENDIAN
789: #ifndef DECSTATION
790: #define WORDS_BIG_ENDIAN 1
791: #else
792: #define WORDS_BIG_ENDIAN 0
793: #endif
794: #endif
795:
796: /* Define macros to easily access the most and least significant words
797: without a lot of #ifdef's. */
798:
799: #if WORDS_BIG_ENDIAN
800: #define MOST_SIGNIFICANT_WORD 0
801: #define LEAST_SIGNIFICANT_WORD 1
802:
803: #else
804: #define MOST_SIGNIFICANT_WORD 1
805: #define LEAST_SIGNIFICANT_WORD 0
806: #endif
807:
808: /* Number of bits in an addressible storage unit */
809: #define BITS_PER_UNIT 8
810:
811: /* Width in bits of a "word", which is the contents of a machine register.
812: Note that this is not necessarily the width of data type `int';
813: if using 16-bit ints on a 68000, this would still be 32.
814: But on a machine with 16-bit registers, this would be 16. */
815: #define BITS_PER_WORD 32
816:
817: /* Width of a word, in units (bytes). */
818: #define UNITS_PER_WORD 4
819:
820: /* A C expression for the size in bits of the type `int' on the
821: target machine. If you don't define this, the default is one
822: word. */
823: #define INT_TYPE_SIZE 32
824:
825: /* A C expression for the size in bits of the type `short' on the
826: target machine. If you don't define this, the default is half a
827: word. (If this would be less than one storage unit, it is
828: rounded up to one unit.) */
829: #define SHORT_TYPE_SIZE 16
830:
831: /* A C expression for the size in bits of the type `long' on the
832: target machine. If you don't define this, the default is one
833: word. */
834: #define LONG_TYPE_SIZE 32
835:
836: /* A C expression for the size in bits of the type `long long' on the
837: target machine. If you don't define this, the default is two
838: words. */
839: #define LONG_LONG_TYPE_SIZE 64
840:
841: /* A C expression for the size in bits of the type `char' on the
842: target machine. If you don't define this, the default is one
843: quarter of a word. (If this would be less than one storage unit,
844: it is rounded up to one unit.) */
845: #define CHAR_TYPE_SIZE BITS_PER_UNIT
846:
847: /* A C expression for the size in bits of the type `float' on the
848: target machine. If you don't define this, the default is one
849: word. */
850: #define FLOAT_TYPE_SIZE 32
851:
852: /* A C expression for the size in bits of the type `double' on the
853: target machine. If you don't define this, the default is two
854: words. */
855: #define DOUBLE_TYPE_SIZE 64
856:
857: /* A C expression for the size in bits of the type `long double' on
858: the target machine. If you don't define this, the default is two
859: words. */
860: #define LONG_DOUBLE_TYPE_SIZE 64
861:
862: /* Width in bits of a pointer.
863: See also the macro `Pmode' defined below. */
864: #define POINTER_SIZE 32
865:
866: /* Allocation boundary (in *bits*) for storing pointers in memory. */
867: #define POINTER_BOUNDARY 32
868:
869: /* Allocation boundary (in *bits*) for storing arguments in argument list. */
870: #define PARM_BOUNDARY 32
871:
872: /* Allocation boundary (in *bits*) for the code of a function. */
873: #define FUNCTION_BOUNDARY 32
874:
875: /* Alignment of field after `int : 0' in a structure. */
876: #define EMPTY_FIELD_BOUNDARY 32
877:
878: /* Every structure's size must be a multiple of this. */
879: /* 8 is observed right on a DECstation and on riscos 4.02. */
880: #define STRUCTURE_SIZE_BOUNDARY 8
881:
882: /* There is no point aligning anything to a rounder boundary than this. */
883: #define BIGGEST_ALIGNMENT 64
884:
885: /* Biggest alignment any structure field can require in bits. */
886: #define BIGGEST_FIELD_ALIGNMENT 64
887:
888: /* Define this if move instructions will actually fail to work
889: when given unaligned data. */
890: #define STRICT_ALIGNMENT
891:
892: /* Define this if you wish to imitate the way many other C compilers
893: handle alignment of bitfields and the structures that contain
894: them.
895:
896: The behavior is that the type written for a bitfield (`int',
897: `short', or other integer type) imposes an alignment for the
898: entire structure, as if the structure really did contain an
899: ordinary field of that type. In addition, the bitfield is placed
900: within the structure so that it would fit within such a field,
901: not crossing a boundary for it.
902:
903: Thus, on most machines, a bitfield whose type is written as `int'
904: would not cross a four-byte boundary, and would force four-byte
905: alignment for the whole structure. (The alignment used may not
906: be four bytes; it is controlled by the other alignment
907: parameters.)
908:
909: If the macro is defined, its definition should be a C expression;
910: a nonzero value for the expression enables this behavior. */
911:
912: #define PCC_BITFIELD_TYPE_MATTERS 1
913:
914: /* If defined, a C expression to compute the alignment given to a
915: constant that is being placed in memory. CONSTANT is the constant
916: and ALIGN is the alignment that the object would ordinarily have.
917: The value of this macro is used instead of that alignment to align
918: the object.
919:
920: If this macro is not defined, then ALIGN is used.
921:
922: The typical use of this macro is to increase alignment for string
923: constants to be word aligned so that `strcpy' calls that copy
924: constants can be done inline. */
925:
926: #define CONSTANT_ALIGNMENT(EXP, ALIGN) \
927: ((TREE_CODE (EXP) == STRING_CST || TREE_CODE (EXP) == CONSTRUCTOR) \
928: && (ALIGN) < BITS_PER_WORD \
929: ? BITS_PER_WORD \
930: : (ALIGN))
931:
932: /* If defined, a C expression to compute the alignment for a static
933: variable. TYPE is the data type, and ALIGN is the alignment that
934: the object would ordinarily have. The value of this macro is used
935: instead of that alignment to align the object.
936:
937: If this macro is not defined, then ALIGN is used.
938:
939: One use of this macro is to increase alignment of medium-size
940: data to make it all fit in fewer cache lines. Another is to
941: cause character arrays to be word-aligned so that `strcpy' calls
942: that copy constants to character arrays can be done inline. */
943:
944: #undef DATA_ALIGNMENT
945: #define DATA_ALIGNMENT(TYPE, ALIGN) \
946: ((((ALIGN) < BITS_PER_WORD) \
947: && (TREE_CODE (TYPE) == ARRAY_TYPE \
948: || TREE_CODE (TYPE) == UNION_TYPE \
949: || TREE_CODE (TYPE) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN))
950:
951: /* Define this macro if an argument declared as `char' or `short' in a
952: prototype should actually be passed as an `int'. In addition to
953: avoiding errors in certain cases of mismatch, it also makes for
954: better code on certain machines. */
955:
956: #define PROMOTE_PROTOTYPES
957:
958: /* Define this macro if an instruction to load a value narrower
959: than a word from memory into a register also zero-extends the
960: value to the whole register. */
961:
962: #define BYTE_LOADS_ZERO_EXTEND
963:
964:
965: /* Standard register usage. */
966:
967: /* Number of actual hardware registers.
968: The hardware registers are assigned numbers for the compiler
969: from 0 to just below FIRST_PSEUDO_REGISTER.
970: All registers that the compiler knows about must be given numbers,
971: even those that are not normally considered general registers.
972:
973: On the Mips, we have 32 integer registers, 32 floating point registers
974: and the special registers hi, lo, and fp status. */
975:
976: #define FIRST_PSEUDO_REGISTER 67
977:
978: /* 1 for registers that have pervasive standard uses
979: and are not available for the register allocator.
980:
981: On the MIPS, see conventions, page D-2 */
982:
983: #define FIXED_REGISTERS \
984: { \
985: 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
986: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, \
987: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
988: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
989: 1, 1, 1 \
990: }
991:
992:
993: /* 1 for registers not available across function calls.
994: These must include the FIXED_REGISTERS and also any
995: registers that can be used without being saved.
996: The latter must include the registers where values are returned
997: and the register where structure-value addresses are passed.
998: Aside from that, you can include as many other registers as you like. */
999:
1000: #define CALL_USED_REGISTERS \
1001: { \
1002: 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1003: 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1, \
1004: 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
1005: 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
1006: 1, 1, 1 \
1007: }
1008:
1009:
1010: /* Internal macros to classify a register number as to whether it's a
1011: general purpose register, a floating point register, a
1012: multiply/divide register, or a status register.
1013:
1014: The macro FP_CALL_REG_P also allows registers $4 and $6 as floating
1015: point registers to pass floating point as per MIPS spec. */
1016:
1017: #define GP_REG_FIRST 0
1018: #define GP_REG_LAST 31
1019: #define GP_REG_NUM (GP_REG_LAST - GP_REG_FIRST + 1)
1020: #define GP_DBX_FIRST 0
1021:
1022: #define FP_REG_FIRST 32
1023: #define FP_REG_LAST 63
1024: #define FP_REG_NUM (FP_REG_LAST - FP_REG_FIRST + 1)
1025: #define FP_DBX_FIRST ((write_symbols == DBX_DEBUG) ? 38 : 32)
1026:
1027: #define MD_REG_FIRST 64
1028: #define MD_REG_LAST 65
1029: #define MD_REG_NUM (MD_REG_LAST - MD_REG_FIRST + 1)
1030:
1031: #define ST_REG_FIRST 66
1032: #define ST_REG_LAST 66
1033: #define ST_REG_NUM (ST_REG_LAST - ST_REG_FIRST + 1)
1034:
1035: #define AT_REGNUM (GP_REG_FIRST + 1)
1036: #define HI_REGNUM (MD_REG_FIRST + 0)
1037: #define LO_REGNUM (MD_REG_FIRST + 1)
1038: #define FPSW_REGNUM ST_REG_FIRST
1039:
1040: #define GP_REG_P(REGNO) ((unsigned) ((REGNO) - GP_REG_FIRST) < GP_REG_NUM)
1041: #define FP_REG_P(REGNO) ((unsigned) ((REGNO) - FP_REG_FIRST) < FP_REG_NUM)
1042: #define MD_REG_P(REGNO) ((unsigned) ((REGNO) - MD_REG_FIRST) < MD_REG_NUM)
1043: #define ST_REG_P(REGNO) ((REGNO) == ST_REG_FIRST)
1044:
1045: #define FP_CALL_REG_P(REGNO) \
1046: (FP_REG_P (REGNO) \
1047: || (REGNO) == (4 + GP_REG_FIRST) \
1048: || (REGNO) == (6 + GP_REG_FIRST))
1049:
1050: /* Return number of consecutive hard regs needed starting at reg REGNO
1051: to hold something of mode MODE.
1052: This is ordinarily the length in words of a value of mode MODE
1053: but can be less for certain modes in special long registers.
1054:
1055: On the MIPS, all general registers are one word long. Except on
1056: the R4000 with the FR bit set, the floating point uses register
1057: pairs, with the second register not being allocatable. */
1058:
1059: #define HARD_REGNO_NREGS(REGNO, MODE) \
1060: (! FP_REG_P (REGNO) \
1061: ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \
1062: : (((GET_MODE_SIZE (MODE) + (2*UNITS_PER_WORD) - 1) / (2*UNITS_PER_WORD)) \
1063: << (TARGET_FLOAT64 == 0)))
1064:
1065: /* Value is 1 if hard register REGNO can hold a value of machine-mode
1066: MODE. Require that DImode and DFmode be in even registers. For
1067: DImode, this makes some of the insns easier to write, since you
1068: don't have to worry about a DImode value in registers 3 & 4,
1069: producing a result in 4 & 5.
1070:
1071: To make the code simpler HARD_REGNO_MODE_OK now just references an
1072: array built in override_options. Because machmodes.h is not yet
1073: included before this file is processed, the MODE bound can't be
1074: expressed here. */
1075:
1076: extern char mips_hard_regno_mode_ok[][FIRST_PSEUDO_REGISTER];
1077:
1078: #define HARD_REGNO_MODE_OK(REGNO, MODE) \
1079: mips_hard_regno_mode_ok[ (int)(MODE) ][ (REGNO) ]
1080:
1081: /* Value is 1 if it is a good idea to tie two pseudo registers
1082: when one has mode MODE1 and one has mode MODE2.
1083: If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,
1084: for any hard reg, then this must be 0 for correct output. */
1085: #define MODES_TIEABLE_P(MODE1, MODE2) \
1086: ((GET_MODE_CLASS (MODE1) == MODE_FLOAT || \
1087: GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \
1088: == (GET_MODE_CLASS (MODE2) == MODE_FLOAT || \
1089: GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))
1090:
1091: /* MIPS pc is not overloaded on a register. */
1092: /* #define PC_REGNUM xx */
1093:
1094: /* Register to use for pushing function arguments. */
1095: #define STACK_POINTER_REGNUM 29
1096:
1097: /* Offset from the stack pointer to the first available location. */
1098: #define STACK_POINTER_OFFSET 0
1099:
1100: /* Base register for access to local variables of the function. */
1101: #define FRAME_POINTER_REGNUM 30
1102:
1103: /* Value should be nonzero if functions must have frame pointers.
1104: Zero means the frame pointer need not be set up (and parms
1105: may be accessed via the stack pointer) in functions that seem suitable.
1106: This is computed in `reload', in reload1.c. */
1107: #define FRAME_POINTER_REQUIRED (current_function_calls_alloca)
1108:
1109: /* Base register for access to arguments of the function. */
1110: #define ARG_POINTER_REGNUM FRAME_POINTER_REGNUM
1111:
1112: /* Register in which static-chain is passed to a function. */
1113: #define STATIC_CHAIN_REGNUM 2
1114:
1115: /* Register in which address to store a structure value
1116: is passed to a function. */
1117: #define STRUCT_VALUE_REGNUM 4
1118:
1119: /* Mips registers used in prologue/epilogue code when the stack frame
1120: is larger than 32K bytes. These registers must come from the
1121: scratch register set, and not used for passing and returning
1122: arguments and any other information used in the calling sequence
1123: (such as pic). */
1124: #define MIPS_TEMP1_REGNUM 8
1125: #define MIPS_TEMP2_REGNUM 9
1126:
1127: /* Define this macro if it is as good or better to call a constant
1128: function address than to call an address kept in a register. */
1129: #define NO_FUNCTION_CSE 1
1130:
1131: /* Define this macro if it is as good or better for a function to
1132: call itself with an explicit address than to call an address
1133: kept in a register. */
1134: #define NO_RECURSIVE_FUNCTION_CSE 1
1135:
1136: /* The register number of the register used to address a table of
1137: static data addresses in memory. In some cases this register is
1138: defined by a processor's "application binary interface" (ABI).
1139: When this macro is defined, RTL is generated for this register
1140: once, as with the stack pointer and frame pointer registers. If
1141: this macro is not defined, it is up to the machine-dependent
1142: files to allocate such a register (if necessary). */
1143: #define PIC_OFFSET_TABLE_REGNUM 28
1144:
1145:
1146: /* Define the classes of registers for register constraints in the
1147: machine description. Also define ranges of constants.
1148:
1149: One of the classes must always be named ALL_REGS and include all hard regs.
1150: If there is more than one class, another class must be named NO_REGS
1151: and contain no registers.
1152:
1153: The name GENERAL_REGS must be the name of a class (or an alias for
1154: another name such as ALL_REGS). This is the class of registers
1155: that is allowed by "g" or "r" in a register constraint.
1156: Also, registers outside this class are allocated only when
1157: instructions express preferences for them.
1158:
1159: The classes must be numbered in nondecreasing order; that is,
1160: a larger-numbered class must never be contained completely
1161: in a smaller-numbered class.
1162:
1163: For any two classes, it is very desirable that there be another
1164: class that represents their union. */
1165:
1166: enum reg_class
1167: {
1168: NO_REGS, /* no registers in set */
1169: GR_REGS, /* integer registers */
1170: FP_REGS, /* floating point registers */
1171: HI_REG, /* hi register */
1172: LO_REG, /* lo register */
1173: MD_REGS, /* multiply/divide registers (hi/lo) */
1174: ST_REGS, /* status registers (fp status) */
1175: ALL_REGS, /* all registers */
1176: LIM_REG_CLASSES /* max value + 1 */
1177: };
1178:
1179: #define N_REG_CLASSES (int) LIM_REG_CLASSES
1180:
1181: #define GENERAL_REGS GR_REGS
1182:
1183: /* An initializer containing the names of the register classes as C
1184: string constants. These names are used in writing some of the
1185: debugging dumps. */
1186:
1187: #define REG_CLASS_NAMES \
1188: { \
1189: "NO_REGS", \
1190: "GR_REGS", \
1191: "FP_REGS", \
1192: "HI_REG", \
1193: "LO_REG", \
1194: "MD_REGS", \
1195: "ST_REGS", \
1196: "ALL_REGS" \
1197: }
1198:
1199: /* An initializer containing the contents of the register classes,
1200: as integers which are bit masks. The Nth integer specifies the
1201: contents of class N. The way the integer MASK is interpreted is
1202: that register R is in the class if `MASK & (1 << R)' is 1.
1203:
1204: When the machine has more than 32 registers, an integer does not
1205: suffice. Then the integers are replaced by sub-initializers,
1206: braced groupings containing several integers. Each
1207: sub-initializer must be suitable as an initializer for the type
1208: `HARD_REG_SET' which is defined in `hard-reg-set.h'. */
1209:
1210: #define REG_CLASS_CONTENTS \
1211: { \
1212: { 0x00000000, 0x00000000, 0x00000000 }, /* no registers */ \
1213: { 0xffffffff, 0x00000000, 0x00000000 }, /* integer registers */ \
1214: { 0x00000000, 0xffffffff, 0x00000000 }, /* floating registers*/ \
1215: { 0x00000000, 0x00000000, 0x00000001 }, /* lo register */ \
1216: { 0x00000000, 0x00000000, 0x00000002 }, /* hi register */ \
1217: { 0x00000000, 0x00000000, 0x00000003 }, /* mul/div registers */ \
1218: { 0x00000000, 0x00000000, 0x00000004 }, /* status registers */ \
1219: { 0xffffffff, 0xffffffff, 0x00000007 } /* all registers */ \
1220: }
1221:
1222:
1223: /* A C expression whose value is a register class containing hard
1224: register REGNO. In general there is more that one such class;
1225: choose a class which is "minimal", meaning that no smaller class
1226: also contains the register. */
1227:
1228: extern enum reg_class mips_regno_to_class[];
1229:
1230: #define REGNO_REG_CLASS(REGNO) mips_regno_to_class[ (REGNO) ]
1231:
1232: /* A macro whose definition is the name of the class to which a
1233: valid base register must belong. A base register is one used in
1234: an address which is the register value plus a displacement. */
1235:
1236: #define BASE_REG_CLASS GR_REGS
1237:
1238: /* A macro whose definition is the name of the class to which a
1239: valid index register must belong. An index register is one used
1240: in an address where its value is either multiplied by a scale
1241: factor or added to another register (as well as added to a
1242: displacement). */
1243:
1244: #define INDEX_REG_CLASS GR_REGS
1245:
1246:
1247: /* REGISTER AND CONSTANT CLASSES */
1248:
1249: /* Get reg_class from a letter such as appears in the machine
1250: description.
1251:
1252: DEFINED REGISTER CLASSES:
1253:
1254: 'd' General (aka integer) registers
1255: 'f' Floating point registers
1256: 'h' Hi register
1257: 'l' Lo register
1258: 's' Status registers
1259: 'x' Multiply/divide registers */
1260:
1261: extern enum reg_class mips_char_to_class[];
1262:
1263: #define REG_CLASS_FROM_LETTER(C) mips_char_to_class[ (C) ]
1264:
1265: /* The letters I, J, K, L, M, N, O, and P in a register constraint
1266: string can be used to stand for particular ranges of immediate
1267: operands. This macro defines what the ranges are. C is the
1268: letter, and VALUE is a constant value. Return 1 if VALUE is
1269: in the range specified by C. */
1270:
1271: /* For MIPS:
1272:
1273: `I' is used for the range of constants an arithmetic insn can
1274: actually contain (16 bits signed integers).
1275:
1276: `J' is used for the range which is just zero (ie, $r0).
1277:
1278: `K' is used for the range of constants a logical insn can actually
1279: contain (16 bit zero-extended integers).
1280:
1281: `L' is used for the range of constants that be loaded with lui
1282: (ie, the bottom 16 bits are zero).
1283:
1284: `M' is used for the range of constants that take two words to load
1285: (ie, not matched by `I', `K', and `L').
1286:
1287: `N' is used for negative 16 bit constants.
1288:
1289: `O' is an exact power of 2 (not yet used in the md file).
1290:
1291: `P' is used for positive 16 bit constants. */
1292:
1293: #define SMALL_INT(X) ((unsigned) (INTVAL (X) + 0x8000) < 0x10000)
1294: #define SMALL_INT_UNSIGNED(X) ((unsigned) (INTVAL (X)) < 0x10000)
1295:
1296: #define CONST_OK_FOR_LETTER_P(VALUE, C) \
1297: ((C) == 'I' ? ((unsigned) ((VALUE) + 0x8000) < 0x10000) \
1298: : (C) == 'J' ? ((VALUE) == 0) \
1299: : (C) == 'K' ? ((unsigned) (VALUE) < 0x10000) \
1300: : (C) == 'L' ? (((VALUE) & 0xffff0000) == (VALUE)) \
1301: : (C) == 'M' ? ((((VALUE) & 0xffff0000) != 0) \
1302: && (((VALUE) & 0xffff0000) != 0xffff0000) \
1303: && ((VALUE) & 0x0000ffff) != 0) \
1304: : (C) == 'N' ? (((VALUE) & 0xffff0000) == 0xffff0000) \
1305: : (C) == 'O' ? (exact_log2 (VALUE) >= 0) \
1306: : (C) == 'P' ? ((VALUE) != 0 && (((VALUE) & 0xffff0000) == 0)) \
1307: : 0)
1308:
1309: /* Similar, but for floating constants, and defining letters G and H.
1310: Here VALUE is the CONST_DOUBLE rtx itself. */
1311:
1312: /* For Mips
1313:
1314: 'G' : Floating point 0 */
1315:
1316: #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \
1317: ((C) == 'G' \
1318: && CONST_DOUBLE_HIGH (VALUE) == 0 \
1319: && CONST_DOUBLE_LOW (VALUE) == 0)
1320:
1321: /* Letters in the range `Q' through `U' may be defined in a
1322: machine-dependent fashion to stand for arbitrary operand types.
1323: The machine description macro `EXTRA_CONSTRAINT' is passed the
1324: operand as its first argument and the constraint letter as its
1325: second operand.
1326:
1327: `Q' is for memory refereces using take more than 1 instruction.
1328: `R' is for memory refereces which take 1 word for the instruction.
1329: `S' is for references to extern items which are PIC for OSF/rose. */
1330:
1331: #define EXTRA_CONSTRAINT(OP,CODE) \
1332: ((GET_CODE (OP) != MEM) ? FALSE \
1333: : ((CODE) == 'Q') ? !simple_memory_operand (OP, GET_MODE (OP)) \
1334: : ((CODE) == 'R') ? simple_memory_operand (OP, GET_MODE (OP)) \
1335: : ((CODE) == 'S') ? (HALF_PIC_P () && CONSTANT_P (OP) \
1336: && HALF_PIC_ADDRESS_P (OP)) \
1337: : FALSE)
1338:
1339: /* Given an rtx X being reloaded into a reg required to be
1340: in class CLASS, return the class of reg to actually use.
1341: In general this is just CLASS; but on some machines
1342: in some cases it is preferable to use a more restrictive class. */
1343:
1344: #define PREFERRED_RELOAD_CLASS(X,CLASS) \
1345: ((GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT \
1346: || GET_MODE_CLASS (GET_MODE (X)) == MODE_COMPLEX_FLOAT) \
1347: ? (TARGET_SOFT_FLOAT ? GR_REGS : FP_REGS) \
1348: : ((GET_MODE (X) == VOIDmode) \
1349: ? GR_REGS \
1350: : CLASS))
1351:
1352: /* Return the maximum number of consecutive registers
1353: needed to represent mode MODE in a register of class CLASS. */
1354:
1355: #define CLASS_MAX_NREGS(CLASS, MODE) \
1356: ((((MODE) == DFmode) || ((MODE) == SFmode)) ? 2 \
1357: : ((MODE) == VOIDmode)? ((CLASS) == FP_REGS ? 2 : 1) \
1358: : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
1359:
1360: /* If defined, this is a C expression whose value should be
1361: nonzero if the insn INSN has the effect of mysteriously
1362: clobbering the contents of hard register number REGNO. By
1363: "mysterious" we mean that the insn's RTL expression doesn't
1364: describe such an effect.
1365:
1366: If this macro is not defined, it means that no insn clobbers
1367: registers mysteriously. This is the usual situation; all else
1368: being equal, it is best for the RTL expression to show all the
1369: activity. */
1370:
1371: /* #define INSN_CLOBBERS_REGNO_P(INSN, REGNO) */
1372:
1373:
1374: /* Stack layout; function entry, exit and calling. */
1375:
1376: /* Define this if pushing a word on the stack
1377: makes the stack pointer a smaller address. */
1378: #define STACK_GROWS_DOWNWARD
1379:
1380: /* Define this if the nominal address of the stack frame
1381: is at the high-address end of the local variables;
1382: that is, each additional local variable allocated
1383: goes at a more negative offset in the frame. */
1384: #define FRAME_GROWS_DOWNWARD
1385:
1386: /* Offset within stack frame to start allocating local variables at.
1387: If FRAME_GROWS_DOWNWARD, this is the offset to the END of the
1388: first local allocated. Otherwise, it is the offset to the BEGINNING
1389: of the first local allocated. */
1390: #define STARTING_FRAME_OFFSET (-8)
1391:
1392: /* Structure to be filled in by compute_frame_size with register
1393: save masks, and offsets for the current function. */
1394:
1395: struct mips_frame_info
1396: {
1397: unsigned long total_size; /* # bytes that the entire frame takes up */
1398: unsigned long var_size; /* # bytes that variables take up */
1399: unsigned long args_size; /* # bytes that outgoing arguments take up */
1400: unsigned long extra_size; /* # bytes of extra gunk */
1401: unsigned int gp_reg_size; /* # bytes needed to store gp regs */
1402: unsigned int fp_reg_size; /* # bytes needed to store fp regs */
1403: unsigned long mask; /* mask of saved gp registers */
1404: unsigned long fmask; /* mask of saved fp registers */
1405: long gp_save_offset; /* offset from vfp to store gp registers */
1406: long fp_save_offset; /* offset from vfp to store fp registers */
1407: unsigned long gp_sp_offset; /* offset from new sp to store gp registers */
1408: unsigned long fp_sp_offset; /* offset from new sp to store fp registers */
1409: int initialized; /* != 0 if frame size already calculated */
1410: };
1411:
1412: extern struct mips_frame_info current_frame_info;
1413:
1414: /* Store in the variable DEPTH the initial difference between the
1415: frame pointer reg contents and the stack pointer reg contents,
1416: as of the start of the function body. This depends on the layout
1417: of the fixed parts of the stack frame and on how registers are saved. */
1418:
1419: #define INITIAL_FRAME_POINTER_OFFSET(VAR) \
1420: ((VAR) = compute_frame_size (get_frame_size ()))
1421:
1422: /* If we generate an insn to push BYTES bytes,
1423: this says how many the stack pointer really advances by.
1424: On the vax, sp@- in a byte insn really pushes a word. */
1425:
1426: /* #define PUSH_ROUNDING(BYTES) 0 */
1427:
1428: /* If defined, the maximum amount of space required for outgoing
1429: arguments will be computed and placed into the variable
1430: `current_function_outgoing_args_size'. No space will be pushed
1431: onto the stack for each call; instead, the function prologue
1432: should increase the stack frame size by this amount.
1433:
1434: It is not proper to define both `PUSH_ROUNDING' and
1435: `ACCUMULATE_OUTGOING_ARGS'. */
1436: #define ACCUMULATE_OUTGOING_ARGS
1437:
1438: /* Offset of first parameter from the argument pointer register value. */
1439: #define FIRST_PARM_OFFSET(FNDECL) 0
1440:
1441: /* Offset from top-of-stack address to location to store the
1442: function parameter if it can't go in a register.
1443: Addresses for following parameters are computed relative to this one.
1444:
1445: It also has the effect of counting register arguments in the total
1446: argument size. */
1447: #define FIRST_PARM_CALLER_OFFSET(FNDECL) 0
1448:
1449: /* When a parameter is passed in a register, stack space is still
1450: allocated for it. For the MIPS, stack space must be allocated, cf
1451: Asm Lang Prog Guide page 7-8.
1452:
1453: BEWARE that some space is also allocated for non existing arguments
1454: in register. In case an argument list is of form GF used registers
1455: are a0 (a2,a3), but we should push over a1... */
1456:
1457: #define REG_PARM_STACK_SPACE(FNDECL) (4*4)
1458:
1459: /* Define this if it is the responsibility of the caller to
1460: allocate the area reserved for arguments passed in registers.
1461: If `ACCUMULATE_OUTGOING_ARGS' is also defined, the only effect
1462: of this macro is to determine whether the space is included in
1463: `current_function_outgoing_args_size'. */
1464: #define OUTGOING_REG_PARM_STACK_SPACE
1465:
1466: /* Align stack frames on 64 bits (Double Word ). */
1467: #define STACK_BOUNDARY 64
1468:
1469: /* Make sure 16 bytes are always allocated on the stack. */
1470:
1471: #ifndef STACK_ARGS_ADJUST
1472: #define STACK_ARGS_ADJUST(SIZE) \
1473: { \
1474: if (SIZE.constant < 16) \
1475: SIZE.constant = 16; \
1476: }
1477: #endif
1478:
1479:
1480: /* A C expression that should indicate the number of bytes of its
1481: own arguments that a function function pops on returning, or 0
1482: if the function pops no arguments and the caller must therefore
1483: pop them all after the function returns.
1484:
1485: FUNTYPE is a C variable whose value is a tree node that
1486: describes the function in question. Normally it is a node of
1487: type `FUNCTION_TYPE' that describes the data type of the function.
1488: From this it is possible to obtain the data types of the value
1489: and arguments (if known).
1490:
1491: When a call to a library function is being considered, FUNTYPE
1492: will contain an identifier node for the library function. Thus,
1493: if you need to distinguish among various library functions, you
1494: can do so by their names. Note that "library function" in this
1495: context means a function used to perform arithmetic, whose name
1496: is known specially in the compiler and was not mentioned in the
1497: C code being compiled.
1498:
1499: STACK-SIZE is the number of bytes of arguments passed on the
1500: stack. If a variable number of bytes is passed, it is zero, and
1501: argument popping will always be the responsibility of the
1502: calling function. */
1503:
1504: #define RETURN_POPS_ARGS(FUNTYPE, SIZE) 0
1505:
1506:
1507: /* Symbolic macros for the registers used to return integer and floating
1508: point values. */
1509:
1510: #define GP_RETURN (GP_REG_FIRST + 2)
1511: #define FP_RETURN ((TARGET_SOFT_FLOAT) ? GP_RETURN : (FP_REG_FIRST + 0))
1512:
1513: /* Symbolic macros for the first/last argument registers. */
1514:
1515: #define GP_ARG_FIRST (GP_REG_FIRST + 4)
1516: #define GP_ARG_LAST (GP_REG_FIRST + 7)
1517: #define FP_ARG_FIRST (FP_REG_FIRST + 12)
1518: #define FP_ARG_LAST (FP_REG_FIRST + 15)
1519:
1520: #define MAX_ARGS_IN_REGISTERS 4
1521:
1522: /* Define how to find the value returned by a library function
1523: assuming the value has mode MODE. */
1524:
1525: #define LIBCALL_VALUE(MODE) \
1526: gen_rtx (REG, MODE, \
1527: (GET_MODE_CLASS (MODE) == MODE_FLOAT) \
1528: ? FP_RETURN \
1529: : GP_RETURN)
1530:
1531: /* Define how to find the value returned by a function.
1532: VALTYPE is the data type of the value (as a tree).
1533: If the precise function being called is known, FUNC is its FUNCTION_DECL;
1534: otherwise, FUNC is 0. */
1535:
1536: #define FUNCTION_VALUE(VALTYPE, FUNC) LIBCALL_VALUE (TYPE_MODE (VALTYPE))
1537:
1538:
1539: /* 1 if N is a possible register number for a function value.
1540: On the MIPS, R2 R3 and F0 F2 are the only register thus used.
1541: Currently, R2 and F0 are only implemented here (C has no complex type) */
1542:
1543: #define FUNCTION_VALUE_REGNO_P(N) ((N) == GP_RETURN || (N) == FP_RETURN)
1544:
1545: /* 1 if N is a possible register number for function argument passing. */
1546:
1547: #define FUNCTION_ARG_REGNO_P(N) (((N) >= GP_ARG_FIRST && (N) <= GP_ARG_LAST) \
1548: || ((N) >= FP_ARG_FIRST && (N) <= FP_ARG_LAST \
1549: && (0 == (N) % 2)))
1550:
1551: /* A C expression which can inhibit the returning of certain function
1552: values in registers, based on the type of value. A nonzero value says
1553: to return the function value in memory, just as large structures are
1554: always returned. Here TYPE will be a C expression of type
1555: `tree', representing the data type of the value.
1556:
1557: Note that values of mode `BLKmode' are returned in memory
1558: regardless of this macro. Also, the option `-fpcc-struct-return'
1559: takes effect regardless of this macro. On most systems, it is
1560: possible to leave the macro undefined; this causes a default
1561: definition to be used, whose value is the constant 0.
1562:
1563: GCC normally converts 1 byte structures into chars, 2 byte
1564: structs into shorts, and 4 byte structs into ints, and returns
1565: them this way. Defining the following macro overrides this,
1566: to give us MIPS cc compatibility. */
1567:
1568: #define RETURN_IN_MEMORY(TYPE) \
1569: ((TREE_CODE (TYPE) == RECORD_TYPE) || (TREE_CODE (TYPE) == UNION_TYPE))
1570:
1571:
1572: /* A code distinguishing the floating point format of the target
1573: machine. There are three defined values: IEEE_FLOAT_FORMAT,
1574: VAX_FLOAT_FORMAT, and UNKNOWN_FLOAT_FORMAT. */
1575:
1576: #define TARGET_FLOAT_FORMAT IEEE_FLOAT_FORMAT
1577:
1578:
1579: /* Define a data type for recording info about an argument list
1580: during the scan of that argument list. This data type should
1581: hold all necessary information about the function itself
1582: and about the args processed so far, enough to enable macros
1583: such as FUNCTION_ARG to determine where the next arg should go.
1584: */
1585:
1586: typedef struct mips_args {
1587: int gp_reg_found;
1588: int arg_number;
1589: int arg_words;
1590: } CUMULATIVE_ARGS;
1591:
1592: /* Initialize a variable CUM of type CUMULATIVE_ARGS
1593: for a call to a function whose data type is FNTYPE.
1594: For a library call, FNTYPE is 0.
1595:
1596: */
1597:
1598: #define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \
1599: init_cumulative_args (&CUM, FNTYPE, LIBNAME) \
1600:
1601: /* Update the data in CUM to advance over an argument
1602: of mode MODE and data type TYPE.
1603: (TYPE is null for libcalls where that information may not be available.) */
1604:
1605: #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \
1606: function_arg_advance (&CUM, MODE, TYPE, NAMED)
1607:
1608: /* Determine where to put an argument to a function.
1609: Value is zero to push the argument on the stack,
1610: or a hard register in which to store the argument.
1611:
1612: MODE is the argument's machine mode.
1613: TYPE is the data type of the argument (as a tree).
1614: This is null for libcalls where that information may
1615: not be available.
1616: CUM is a variable of type CUMULATIVE_ARGS which gives info about
1617: the preceding args and about the function being called.
1618: NAMED is nonzero if this argument is a named parameter
1619: (otherwise it is an extra parameter matching an ellipsis). */
1620:
1621: #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \
1622: function_arg( &CUM, MODE, TYPE, NAMED)
1623:
1624: /* For an arg passed partly in registers and partly in memory,
1625: this is the number of registers used.
1626: For args passed entirely in registers or entirely in memory, zero. */
1627:
1628: #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \
1629: function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED)
1630:
1631: /* If defined, a C expression that gives the alignment boundary, in
1632: bits, of an argument with the specified mode and type. If it is
1633: not defined, `PARM_BOUNDARY' is used for all arguments. */
1634:
1635: #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \
1636: (((TYPE) != 0) \
1637: ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \
1638: ? PARM_BOUNDARY \
1639: : TYPE_ALIGN(TYPE)) \
1640: : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \
1641: ? PARM_BOUNDARY \
1642: : GET_MODE_ALIGNMENT(MODE)))
1643:
1644:
1645: /* This macro generates the assembly code for function entry.
1646: FILE is a stdio stream to output the code to.
1647: SIZE is an int: how many units of temporary storage to allocate.
1648: Refer to the array `regs_ever_live' to determine which registers
1649: to save; `regs_ever_live[I]' is nonzero if register number I
1650: is ever used in the function. This macro is responsible for
1651: knowing which registers should not be saved even if used. */
1652:
1653: #define FUNCTION_PROLOGUE(FILE, SIZE) function_prologue(FILE, SIZE)
1654:
1655: /* This macro generates the assembly code for function exit,
1656: on machines that need it. If FUNCTION_EPILOGUE is not defined
1657: then individual return instructions are generated for each
1658: return statement. Args are same as for FUNCTION_PROLOGUE. */
1659:
1660: #define FUNCTION_EPILOGUE(FILE, SIZE) function_epilogue(FILE, SIZE)
1661:
1662: /* Define the number of delay slots needed for the function epilogue.
1663:
1664: On the mips, we need a slot if either no stack has been allocated,
1665: or the only register saved is the return register. */
1666:
1667: #define DELAY_SLOTS_FOR_EPILOGUE mips_epilogue_delay_slots ()
1668:
1669: /* Define whether INSN can be placed in delay slot N for the epilogue.
1670: No references to the stack must be made, since on the MIPS, the
1671: delay slot is done after the stack has been cleaned up. */
1672:
1673: #define ELIGIBLE_FOR_EPILOGUE_DELAY(INSN,N) \
1674: (get_attr_dslot (INSN) == DSLOT_NO \
1675: && get_attr_length (INSN) == 1 \
1676: && ! reg_mentioned_p (stack_pointer_rtx, PATTERN (INSN)) \
1677: && ! reg_mentioned_p (frame_pointer_rtx, PATTERN (INSN)))
1678:
1679: /* Tell prologue and epilogue if register REGNO should be saved / restored. */
1680:
1681: #define MUST_SAVE_REGISTER(regno) \
1682: ((regs_ever_live[regno] && !call_used_regs[regno]) \
1683: || (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) \
1684: || (regno == 31 && regs_ever_live[31]))
1685:
1686: /* ALIGN FRAMES on double word boundaries */
1687:
1688: #define MIPS_STACK_ALIGN(LOC) (((LOC)+7) & 0xfffffff8)
1689:
1690:
1691: /* Output assembler code to FILE to increment profiler label # LABELNO
1692: for profiling a function entry. */
1693:
1694: #define FUNCTION_PROFILER(FILE, LABELNO) \
1695: { \
1696: fprintf (FILE, "\t.set\tnoreorder\n"); \
1697: fprintf (FILE, "\t.set\tnoat\n"); \
1698: fprintf (FILE, "\tmove\t%s,%s\t\t# save current return address\n", \
1699: reg_names[GP_REG_FIRST + 1], reg_names[GP_REG_FIRST + 31]); \
1700: fprintf (FILE, "\tjal\t_mcount\n"); \
1701: fprintf (FILE, "\tsubu\t%s,%s,8\t\t# _mcount pops 2 words from stack\n", \
1702: reg_names[STACK_POINTER_REGNUM], \
1703: reg_names[STACK_POINTER_REGNUM]); \
1704: fprintf (FILE, "\t.set\treorder\n"); \
1705: fprintf (FILE, "\t.set\tat\n"); \
1706: }
1707:
1708: /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function,
1709: the stack pointer does not matter. The value is tested only in
1710: functions that have frame pointers.
1711: No definition is equivalent to always zero. */
1712:
1713: #define EXIT_IGNORE_STACK 1
1714:
1715:
1716: /* A C statement to output, on the stream FILE, assembler code for a
1717: block of data that contains the constant parts of a trampoline.
1718: This code should not include a label--the label is taken care of
1719: automatically. */
1720:
1721: #define TRAMPOLINE_TEMPLATE(STREAM) \
1722: { \
1723: fprintf (STREAM, "\t.word\t0x03e00821\t\t# move $1,$31\n"); \
1724: fprintf (STREAM, "\t.word\t0x04110001\t\t# bgezal $0,.+8\n"); \
1725: fprintf (STREAM, "\t.word\t0x00000000\t\t# nop\n"); \
1726: fprintf (STREAM, "\t.word\t0x8fe30010\t\t# lw $3,16($31)\n"); \
1727: fprintf (STREAM, "\t.word\t0x8fe20014\t\t# lw $2,20($31)\n"); \
1728: fprintf (STREAM, "\t.word\t0x00600008\t\t# jr $3\n"); \
1729: fprintf (STREAM, "\t.word\t0x0020f821\t\t# move $31,$1\n"); \
1730: fprintf (STREAM, "\t.word\t0x00000000\t\t# <function address>\n"); \
1731: fprintf (STREAM, "\t.word\t0x00000000\t\t# <static chain value>\n"); \
1732: }
1733:
1734: /* A C expression for the size in bytes of the trampoline, as an
1735: integer. */
1736:
1737: #define TRAMPOLINE_SIZE (9*4)
1738:
1739: /* Alignment required for trampolines, in bits.
1740:
1741: If you don't define this macro, the value of `BIGGEST_ALIGNMENT'
1742: is used for aligning trampolines. */
1743:
1744: /* #define TRAMPOLINE_ALIGNMENT 32 */
1745:
1746: /* A C statement to initialize the variable parts of a trampoline.
1747: ADDR is an RTX for the address of the trampoline; FNADDR is an
1748: RTX for the address of the nested function; STATIC_CHAIN is an
1749: RTX for the static chain value that should be passed to the
1750: function when it is called. */
1751:
1752: #define INITIALIZE_TRAMPOLINE(ADDR, FUNC, CHAIN) \
1753: { \
1754: rtx addr = ADDR; \
1755: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 28)), FUNC); \
1756: emit_move_insn (gen_rtx (MEM, SImode, plus_constant (addr, 32)), CHAIN); \
1757: \
1758: /* Attempt to make stack executable */ \
1759: emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "__enable_execute_stack"), \
1760: 0, VOIDmode, 1, addr, Pmode); \
1761: }
1762:
1763:
1764: /* Attempt to turn on access permissions for the stack. */
1765:
1766: #define TRANSFER_FROM_TRAMPOLINE \
1767: \
1768: void \
1769: __enable_execute_stack (addr) \
1770: char *addr; \
1771: { \
1772: int size = getpagesize (); \
1773: int mask = ~(size-1); \
1774: char *page = (char *) (((int) addr) & mask); \
1775: char *end = (char *) ((((int) (addr + TRAMPOLINE_SIZE)) & mask) + size); \
1776: \
1777: /* 7 is PROT_READ | PROT_WRITE | PROT_EXEC */ \
1778: if (mprotect (page, end - page, 7) < 0) \
1779: perror ("mprotect of trampoline code"); \
1780: \
1781: /* \
1782: if (cacheflush (addr, TRAMPOLINE_SIZE, 1) < 0) \
1783: perror ("cacheflush of trampoline code"); \
1784: */ \
1785: }
1786:
1787:
1788: /* Addressing modes, and classification of registers for them. */
1789:
1790: /* #define HAVE_POST_INCREMENT */
1791: /* #define HAVE_POST_DECREMENT */
1792:
1793: /* #define HAVE_PRE_DECREMENT */
1794: /* #define HAVE_PRE_INCREMENT */
1795:
1796: /* These assume that REGNO is a hard or pseudo reg number.
1797: They give nonzero only if REGNO is a hard reg of the suitable class
1798: or a pseudo reg currently allocated to a suitable hard reg.
1799: These definitions are NOT overridden anywhere. */
1800:
1801: #define GP_REG_OR_PSEUDO_STRICT_P(regno) \
1802: GP_REG_P((regno < FIRST_PSEUDO_REGISTER) ? regno : reg_renumber[regno])
1803:
1804: #define GP_REG_OR_PSEUDO_NONSTRICT_P(regno) \
1805: (((regno) >= FIRST_PSEUDO_REGISTER) || (GP_REG_P (regno)))
1806:
1807: #define REGNO_OK_FOR_INDEX_P(regno) GP_REG_OR_PSEUDO_STRICT_P (regno)
1808: #define REGNO_OK_FOR_BASE_P(regno) GP_REG_OR_PSEUDO_STRICT_P (regno)
1809:
1810: /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx
1811: and check its validity for a certain class.
1812: We have two alternate definitions for each of them.
1813: The usual definition accepts all pseudo regs; the other rejects them all.
1814: The symbol REG_OK_STRICT causes the latter definition to be used.
1815:
1816: Most source files want to accept pseudo regs in the hope that
1817: they will get allocated to the class that the insn wants them to be in.
1818: Some source files that are used after register allocation
1819: need to be strict. */
1820:
1821: #ifndef REG_OK_STRICT
1822:
1823: #define REG_OK_STRICT_P 0
1824: #define REG_OK_FOR_INDEX_P(X) GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X))
1825: #define REG_OK_FOR_BASE_P(X) GP_REG_OR_PSEUDO_NONSTRICT_P (REGNO (X))
1826:
1827: #else
1828:
1829: #define REG_OK_STRICT_P 1
1830: #define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
1831: #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
1832:
1833: #endif
1834:
1835:
1836: /* Maximum number of registers that can appear in a valid memory address. */
1837:
1838: #define MAX_REGS_PER_ADDRESS 1
1839:
1840: /* A C compound statement with a conditional `goto LABEL;' executed
1841: if X (an RTX) is a legitimate memory address on the target
1842: machine for a memory operand of mode MODE.
1843:
1844: It usually pays to define several simpler macros to serve as
1845: subroutines for this one. Otherwise it may be too complicated
1846: to understand.
1847:
1848: This macro must exist in two variants: a strict variant and a
1849: non-strict one. The strict variant is used in the reload pass.
1850: It must be defined so that any pseudo-register that has not been
1851: allocated a hard register is considered a memory reference. In
1852: contexts where some kind of register is required, a
1853: pseudo-register with no hard register must be rejected.
1854:
1855: The non-strict variant is used in other passes. It must be
1856: defined to accept all pseudo-registers in every context where
1857: some kind of register is required.
1858:
1859: Compiler source files that want to use the strict variant of
1860: this macro define the macro `REG_OK_STRICT'. You should use an
1861: `#ifdef REG_OK_STRICT' conditional to define the strict variant
1862: in that case and the non-strict variant otherwise.
1863:
1864: Typically among the subroutines used to define
1865: `GO_IF_LEGITIMATE_ADDRESS' are subroutines to check for
1866: acceptable registers for various purposes (one for base
1867: registers, one for index registers, and so on). Then only these
1868: subroutine macros need have two variants; the higher levels of
1869: macros may be the same whether strict or not.
1870:
1871: Normally, constant addresses which are the sum of a `symbol_ref'
1872: and an integer are stored inside a `const' RTX to mark them as
1873: constant. Therefore, there is no need to recognize such sums
1874: specifically as legitimate addresses. Normally you would simply
1875: recognize any `const' as legitimate.
1876:
1877: Usually `PRINT_OPERAND_ADDRESS' is not prepared to handle
1878: constant sums that are not marked with `const'. It assumes
1879: that a naked `plus' indicates indexing. If so, then you *must*
1880: reject such naked constant sums as illegitimate addresses, so
1881: that none of them will be given to `PRINT_OPERAND_ADDRESS'.
1882:
1883: On some machines, whether a symbolic address is legitimate
1884: depends on the section that the address refers to. On these
1885: machines, define the macro `ENCODE_SECTION_INFO' to store the
1886: information into the `symbol_ref', and then check for it here.
1887: When you see a `const', you will have to look inside it to find
1888: the `symbol_ref' in order to determine the section. */
1889:
1890: #if 1
1891: #define GO_PRINTF(x) trace(x)
1892: #define GO_PRINTF2(x,y) trace(x,y)
1893: #define GO_DEBUG_RTX(x) debug_rtx(x)
1894:
1895: #else
1896: #define GO_PRINTF(x)
1897: #define GO_PRINTF2(x,y)
1898: #define GO_DEBUG_RTX(x)
1899: #endif
1900:
1901: #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \
1902: { \
1903: register rtx xinsn = (X); \
1904: \
1905: if (TARGET_DEBUG_B_MODE) \
1906: { \
1907: GO_PRINTF2 ("\n========== GO_IF_LEGITIMATE_ADDRESS, %sstrict\n", \
1908: (REG_OK_STRICT_P) ? "" : "not "); \
1909: GO_DEBUG_RTX (xinsn); \
1910: } \
1911: \
1912: if (GET_CODE (xinsn) == REG && REG_OK_FOR_BASE_P (xinsn)) \
1913: goto ADDR; \
1914: \
1915: if (CONSTANT_ADDRESS_P (xinsn)) \
1916: goto ADDR; \
1917: \
1918: if (GET_CODE (xinsn) == PLUS) \
1919: { \
1920: register rtx xplus0 = XEXP (xinsn, 0); \
1921: register rtx xplus1 = XEXP (xinsn, 1); \
1922: register enum rtx_code code0 = GET_CODE (xplus0); \
1923: register enum rtx_code code1 = GET_CODE (xplus1); \
1924: \
1925: if (code0 != REG && code1 == REG) \
1926: { \
1927: xplus0 = XEXP (xinsn, 1); \
1928: xplus1 = XEXP (xinsn, 0); \
1929: code0 = GET_CODE (xplus0); \
1930: code1 = GET_CODE (xplus1); \
1931: } \
1932: \
1933: if (code0 == REG && REG_OK_FOR_BASE_P (xplus0)) \
1934: { \
1935: if (code1 == CONST_INT) \
1936: { \
1937: register unsigned adj_offset = INTVAL (xplus1) + 0x8000; \
1938: \
1939: if ((adj_offset <= 0xffff) \
1940: && (adj_offset + GET_MODE_SIZE (MODE) - 1 <= 0xffff)) \
1941: goto ADDR; \
1942: } \
1943: \
1944: /* For some code sequences, you actually get better code by \
1945: pretending that the MIPS supports an address mode of a \
1946: constant address + a register, even though the real \
1947: machine doesn't support it. This is because the \
1948: assembler can use $r1 to load just the high 16 bits, add \
1949: in the register, and fold the low 16 bits into the memory \
1950: reference, wheras the compiler generates a 4 instruction \
1951: sequence. On the other hand, CSE is not as effective. \
1952: It would be a win to generate the lui directly, but the \
1953: MIPS assembler does not have syntax to generate the \
1954: appropriate relocation. */ \
1955: \
1956: else if (!TARGET_DEBUG_A_MODE \
1957: && code0 == REG \
1958: && CONSTANT_ADDRESS_P (xplus1)) \
1959: goto ADDR; \
1960: } \
1961: } \
1962: \
1963: if (TARGET_DEBUG_B_MODE) \
1964: GO_PRINTF ("Not a legitimate address\n"); \
1965: }
1966:
1967:
1968: /* A C expression that is 1 if the RTX X is a constant which is a
1969: valid address. On most machines, this can be defined as
1970: `CONSTANT_P (X)', but a few machines are more restrictive in
1971: which constant addresses are supported.
1972:
1973: `CONSTANT_P' accepts integer-values expressions whose values are
1974: not explicitly known, such as `symbol_ref', `label_ref', and
1975: `high' expressions and `const' arithmetic expressions, in
1976: addition to `const_int' and `const_double' expressions. */
1977:
1978: #define CONSTANT_ADDRESS_P(X) \
1979: (CONSTANT_P (X) && (!HALF_PIC_P () || HALF_PIC_ADDRESS_P (X)))
1980:
1981:
1982: /* Nonzero if the constant value X is a legitimate general operand.
1983: It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE.
1984:
1985: At present, GAS doesn't understand li.[sd], so don't allow it
1986: to be generated at present. Also, the MIPS assembler does not
1987: grok li.d Infinity. */
1988:
1989: #define LEGITIMATE_CONSTANT_P(X) \
1990: (GET_CODE (X) != CONST_DOUBLE || mips_const_double_ok (X, GET_MODE (X)))
1991:
1992:
1993: /* A C compound statement that attempts to replace X with a valid
1994: memory address for an operand of mode MODE. WIN will be a C
1995: statement label elsewhere in the code; the macro definition may
1996: use
1997:
1998: GO_IF_LEGITIMATE_ADDRESS (MODE, X, WIN);
1999:
2000: to avoid further processing if the address has become legitimate.
2001:
2002: X will always be the result of a call to `break_out_memory_refs',
2003: and OLDX will be the operand that was given to that function to
2004: produce X.
2005:
2006: The code generated by this macro should not alter the
2007: substructure of X. If it transforms X into a more legitimate
2008: form, it should assign X (which will always be a C variable) a
2009: new value.
2010:
2011: It is not necessary for this macro to come up with a legitimate
2012: address. The compiler has standard ways of doing so in all
2013: cases. In fact, it is safe for this macro to do nothing. But
2014: often a machine-dependent strategy can generate better code. */
2015:
2016: #define LEGITIMIZE_ADDRESS(X,OLDX,MODE,WIN) {}
2017:
2018:
2019: /* A C statement or compound statement with a conditional `goto
2020: LABEL;' executed if memory address X (an RTX) can have different
2021: meanings depending on the machine mode of the memory reference it
2022: is used for.
2023:
2024: Autoincrement and autodecrement addresses typically have
2025: mode-dependent effects because the amount of the increment or
2026: decrement is the size of the operand being addressed. Some
2027: machines have other mode-dependent addresses. Many RISC machines
2028: have no mode-dependent addresses.
2029:
2030: You may assume that ADDR is a valid address for the machine. */
2031:
2032: #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) {}
2033:
2034:
2035: /* Define this macro if references to a symbol must be treated
2036: differently depending on something about the variable or
2037: function named by the symbol (such as what section it is in).
2038:
2039: The macro definition, if any, is executed immediately after the
2040: rtl for DECL has been created and stored in `DECL_RTL (DECL)'.
2041: The value of the rtl will be a `mem' whose address is a
2042: `symbol_ref'.
2043:
2044: The usual thing for this macro to do is to a flag in the
2045: `symbol_ref' (such as `SYMBOL_REF_FLAG') or to store a modified
2046: name string in the `symbol_ref' (if one bit is not enough
2047: information).
2048:
2049: The best way to modify the name string is by adding text to the
2050: beginning, with suitable punctuation to prevent any ambiguity.
2051: Allocate the new name in `saveable_obstack'. You will have to
2052: modify `ASM_OUTPUT_LABELREF' to remove and decode the added text
2053: and output the name accordingly.
2054:
2055: You can also check the information stored in the `symbol_ref' in
2056: the definition of `GO_IF_LEGITIMATE_ADDRESS' or
2057: `PRINT_OPERAND_ADDRESS'. */
2058:
2059: #define ENCODE_SECTION_INFO(DECL) \
2060: do \
2061: { \
2062: if (optimize && mips_section_threshold > 0 && TARGET_GP_OPT \
2063: && TREE_CODE (DECL) == VAR_DECL) \
2064: { \
2065: int size = int_size_in_bytes (TREE_TYPE (DECL)); \
2066: \
2067: if (size > 0 && size <= mips_section_threshold) \
2068: SYMBOL_REF_FLAG (XEXP (DECL_RTL (DECL), 0)) = 1; \
2069: } \
2070: \
2071: else if (HALF_PIC_P ()) \
2072: HALF_PIC_ENCODE (DECL); \
2073: } \
2074: while (0)
2075:
2076:
2077: /* Specify the machine mode that this machine uses
2078: for the index in the tablejump instruction. */
2079: #define CASE_VECTOR_MODE SImode
2080:
2081: /* Define this if the tablejump instruction expects the table
2082: to contain offsets from the address of the table.
2083: Do not define this if the table should contain absolute addresses. */
2084: /* #define CASE_VECTOR_PC_RELATIVE */
2085:
2086: /* Specify the tree operation to be used to convert reals to integers. */
2087: #define IMPLICIT_FIX_EXPR FIX_ROUND_EXPR
2088:
2089: /* This is the kind of divide that is easiest to do in the general case. */
2090: #define EASY_DIV_EXPR TRUNC_DIV_EXPR
2091:
2092: /* Define this as 1 if `char' should by default be signed; else as 0. */
2093: #define DEFAULT_SIGNED_CHAR 1
2094:
2095: /* Max number of bytes we can move from memory to memory
2096: in one reasonably fast instruction. */
2097: #define MOVE_MAX 4
2098:
2099: /* Define this macro as a C expression which is nonzero if
2100: accessing less than a word of memory (i.e. a `char' or a
2101: `short') is no faster than accessing a word of memory, i.e., if
2102: such access require more than one instruction or if there is no
2103: difference in cost between byte and (aligned) word loads.
2104:
2105: On RISC machines, it tends to generate better code to define
2106: this as 1, since it avoids making a QI or HI mode register. */
2107: #define SLOW_BYTE_ACCESS 1
2108:
2109: /* We assume that the store-condition-codes instructions store 0 for false
2110: and some other value for true. This is the value stored for true. */
2111:
2112: #define STORE_FLAG_VALUE 1
2113:
2114: /* Define this if zero-extension is slow (more than one real instruction). */
2115: #define SLOW_ZERO_EXTEND
2116:
2117: /* Define if shifts truncate the shift count
2118: which implies one can omit a sign-extension or zero-extension
2119: of a shift count.
2120:
2121: Only 5 bits are used in SLLV and SRLV */
2122:
2123: #define SHIFT_COUNT_TRUNCATED
2124:
2125: /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits
2126: is done just by pretending it is already truncated. */
2127: #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1
2128:
2129: /* By default, allow $ to be part of an identifier. */
2130: #define DOLLARS_IN_IDENTIFIERS 1
2131:
2132: /* Specify the machine mode that pointers have.
2133: After generation of rtl, the compiler makes no further distinction
2134: between pointers and any other objects of this machine mode. */
2135: #define Pmode SImode
2136:
2137: /* A function address in a call instruction
2138: is a word address (for indexing purposes)
2139: so give the MEM rtx a words's mode. */
2140:
2141: #define FUNCTION_MODE SImode
2142:
2143: /* Define TARGET_MEM_FUNCTIONS if we want to use calls to memcpy and
2144: memset, instead of the BSD functions bcopy and bzero. */
2145:
2146: #if defined(MIPS_SYSV) || defined(OSF_OS)
2147: #define TARGET_MEM_FUNCTIONS
2148: #endif
2149:
2150:
2151: /* A part of a C `switch' statement that describes the relative
2152: costs of constant RTL expressions. It must contain `case'
2153: labels for expression codes `const_int', `const', `symbol_ref',
2154: `label_ref' and `const_double'. Each case must ultimately reach
2155: a `return' statement to return the relative cost of the use of
2156: that kind of constant value in an expression. The cost may
2157: depend on the precise value of the constant, which is available
2158: for examination in X.
2159:
2160: CODE is the expression code--redundant, since it can be obtained
2161: with `GET_CODE (X)'. */
2162:
2163: #define CONST_COSTS(X,CODE) \
2164: case CONST_INT: \
2165: /* Always return 0, since we don't have different sized \
2166: instructions, hence different costs according to Richard \
2167: Kenner */ \
2168: return COSTS_N_INSNS (0); \
2169: \
2170: case LABEL_REF: \
2171: return COSTS_N_INSNS (2); \
2172: \
2173: case CONST: \
2174: { \
2175: extern rtx eliminate_constant_term (); \
2176: int offset = 0; \
2177: rtx symref = eliminate_constant_term (X, &offset); \
2178: \
2179: if (GET_CODE (symref) == LABEL_REF) \
2180: return COSTS_N_INSNS (2); \
2181: \
2182: if (GET_CODE (symref) != SYMBOL_REF) \
2183: return COSTS_N_INSNS (4); \
2184: \
2185: /* let's be paranoid.... */ \
2186: if (offset < -32768 || offset > 32767) \
2187: return COSTS_N_INSNS (2); \
2188: \
2189: return COSTS_N_INSNS (SYMBOL_REF_FLAG (symref) ? 1 : 2); \
2190: } \
2191: \
2192: case SYMBOL_REF: \
2193: return COSTS_N_INSNS (SYMBOL_REF_FLAG (X) ? 1 : 2); \
2194: \
2195: case CONST_DOUBLE: \
2196: return COSTS_N_INSNS ((CONST_DOUBLE_HIGH (X) == 0 \
2197: && CONST_DOUBLE_LOW (X)) ? 2 : 4);
2198:
2199:
2200: /* Like `CONST_COSTS' but applies to nonconstant RTL expressions.
2201: This can be used, for example, to indicate how costly a multiply
2202: instruction is. In writing this macro, you can use the construct
2203: `COSTS_N_INSNS (N)' to specify a cost equal to N fast instructions.
2204:
2205: This macro is optional; do not define it if the default cost
2206: assumptions are adequate for the target machine.
2207:
2208: If -mdebugd is used, change the multiply cost to 2, so multiply by
2209: a constant isn't converted to a series of shifts. This helps
2210: strength reduction, and also makes it easier to identify what the
2211: compiler is doing. */
2212:
2213: #define RTX_COSTS(X,CODE) \
2214: case MEM: \
2215: { \
2216: int num_words = (GET_MODE_SIZE (GET_MODE (X)) > UNITS_PER_WORD) ? 2 : 1; \
2217: if (simple_memory_operand (X, GET_MODE (X))) \
2218: return COSTS_N_INSNS (num_words); \
2219: \
2220: return COSTS_N_INSNS (2*num_words); \
2221: } \
2222: \
2223: case FFS: \
2224: return COSTS_N_INSNS (6); \
2225: \
2226: case NOT: \
2227: return COSTS_N_INSNS ((GET_MODE (X) == DImode) ? 2 : 1); \
2228: \
2229: case AND: \
2230: case IOR: \
2231: case XOR: \
2232: if (GET_MODE (X) == DImode) \
2233: return COSTS_N_INSNS (2); \
2234: \
2235: if (GET_CODE (XEXP (X, 1)) == CONST_INT) \
2236: { \
2237: rtx number = XEXP (X, 1); \
2238: if (SMALL_INT_UNSIGNED (number)) \
2239: return COSTS_N_INSNS (1); \
2240: \
2241: else if (SMALL_INT (number)) \
2242: return COSTS_N_INSNS (2); \
2243: \
2244: return COSTS_N_INSNS (3); \
2245: } \
2246: \
2247: return COSTS_N_INSNS (1); \
2248: \
2249: case ASHIFT: \
2250: case ASHIFTRT: \
2251: case LSHIFT: \
2252: case LSHIFTRT: \
2253: if (GET_MODE (X) == DImode) \
2254: return COSTS_N_INSNS ((GET_CODE (XEXP (X, 1)) == CONST_INT) ? 12 : 4); \
2255: \
2256: return COSTS_N_INSNS (1); \
2257: \
2258: case ABS: \
2259: { \
2260: enum machine_mode xmode = GET_MODE (X); \
2261: if (xmode == SFmode || xmode == DFmode) \
2262: return COSTS_N_INSNS (1); \
2263: \
2264: return COSTS_N_INSNS (4); \
2265: } \
2266: \
2267: case PLUS: \
2268: case MINUS: \
2269: { \
2270: enum machine_mode xmode = GET_MODE (X); \
2271: if (xmode == SFmode || xmode == DFmode) \
2272: return COSTS_N_INSNS (2); \
2273: \
2274: if (xmode == DImode) \
2275: return COSTS_N_INSNS (4); \
2276: \
2277: return COSTS_N_INSNS (1); \
2278: } \
2279: \
2280: case NEG: \
2281: return COSTS_N_INSNS ((GET_MODE (X) == DImode) ? 4 : 1); \
2282: \
2283: case MULT: \
2284: { \
2285: enum machine_mode xmode = GET_MODE (X); \
2286: if (xmode == SFmode) \
2287: return COSTS_N_INSNS (4); \
2288: \
2289: if (xmode == DFmode) \
2290: return COSTS_N_INSNS (5); \
2291: \
2292: return COSTS_N_INSNS ((TARGET_DEBUG_D_MODE) ? 2 : 12); \
2293: } \
2294: \
2295: case DIV: \
2296: case MOD: \
2297: { \
2298: enum machine_mode xmode = GET_MODE (X); \
2299: if (xmode == SFmode) \
2300: return COSTS_N_INSNS (12); \
2301: \
2302: if (xmode == DFmode) \
2303: return COSTS_N_INSNS (19); \
2304: } \
2305: /* fall through */ \
2306: \
2307: case UDIV: \
2308: case UMOD: \
2309: return COSTS_N_INSNS (35);
2310:
2311: /* An expression giving the cost of an addressing mode that
2312: contains ADDRESS. If not defined, the cost is computed from the
2313: form of the ADDRESS expression and the `CONST_COSTS' values.
2314:
2315: For most CISC machines, the default cost is a good approximation
2316: of the true cost of the addressing mode. However, on RISC
2317: machines, all instructions normally have the same length and
2318: execution time. Hence all addresses will have equal costs.
2319:
2320: In cases where more than one form of an address is known, the
2321: form with the lowest cost will be used. If multiple forms have
2322: the same, lowest, cost, the one that is the most complex will be
2323: used.
2324:
2325: For example, suppose an address that is equal to the sum of a
2326: register and a constant is used twice in the same basic block.
2327: When this macro is not defined, the address will be computed in
2328: a register and memory references will be indirect through that
2329: register. On machines where the cost of the addressing mode
2330: containing the sum is no higher than that of a simple indirect
2331: reference, this will produce an additional instruction and
2332: possibly require an additional register. Proper specification
2333: of this macro eliminates this overhead for such machines.
2334:
2335: Similar use of this macro is made in strength reduction of loops.
2336:
2337: ADDRESS need not be valid as an address. In such a case, the
2338: cost is not relevant and can be any value; invalid addresses
2339: need not be assigned a different cost.
2340:
2341: On machines where an address involving more than one register is
2342: as cheap as an address computation involving only one register,
2343: defining `ADDRESS_COST' to reflect this can cause two registers
2344: to be live over a region of code where only one would have been
2345: if `ADDRESS_COST' were not defined in that manner. This effect
2346: should be considered in the definition of this macro.
2347: Equivalent costs should probably only be given to addresses with
2348: different numbers of registers on machines with lots of registers.
2349:
2350: This macro will normally either not be defined or be defined as
2351: a constant. */
2352:
2353: #define ADDRESS_COST(ADDR) (REG_P (ADDR) ? 1 : mips_address_cost (ADDR))
2354:
2355: /* A C expression for the cost of moving data from a register in
2356: class FROM to one in class TO. The classes are expressed using
2357: the enumeration values such as `GENERAL_REGS'. A value of 2 is
2358: the default; other values are interpreted relative to that.
2359:
2360: It is not required that the cost always equal 2 when FROM is the
2361: same as TO; on some machines it is expensive to move between
2362: registers if they are not general registers.
2363:
2364: If reload sees an insn consisting of a single `set' between two
2365: hard registers, and if `REGISTER_MOVE_COST' applied to their
2366: classes returns a value of 2, reload does not check to ensure
2367: that the constraints of the insn are met. Setting a cost of
2368: other than 2 will allow reload to verify that the constraints are
2369: met. You should do this if the `movM' pattern's constraints do
2370: not allow such copying. */
2371:
2372: #define REGISTER_MOVE_COST(FROM, TO) 4 /* force reload to use constraints */
2373:
2374: /* A C expression for the cost of a branch instruction. A value of
2375: 1 is the default; other values are interpreted relative to that. */
2376:
2377: #define BRANCH_COST \
2378: ((mips_cpu == PROCESSOR_R4000 || mips_cpu == PROCESSOR_R6000) ? 2 : 1)
2379:
2380:
2381: /* Used in by the peephole code. */
2382: #define classify_op(op,mode) (mips_rtx_classify[ (int)GET_CODE (op) ])
2383: #define additive_op(op,mode) ((classify_op (op,mode) & CLASS_ADD_OP) != 0)
2384: #define divmod_op(op,mode) ((classify_op (op,mode) & CLASS_DIVMOD_OP) != 0)
2385: #define unsigned_op(op,mode) ((classify_op (op,mode) & CLASS_UNSIGNED_OP) != 0)
2386:
2387: #define CLASS_ADD_OP 0x01 /* operator is PLUS/MINUS */
2388: #define CLASS_DIVMOD_OP 0x02 /* operator is {,U}{DIV,MOD} */
2389: #define CLASS_UNSIGNED_OP 0x04 /* operator is U{DIV,MOD} */
2390: #define CLASS_CMP_OP 0x08 /* operator is comparison */
2391: #define CLASS_EQUALITY_OP 0x10 /* operator is == or != */
2392: #define CLASS_FCMP_OP 0x08 /* operator is fp. compare */
2393:
2394: #define CLASS_UNS_CMP_OP (CLASS_UNSIGNED_OP | CLASS_CMP_OP)
2395:
2396:
2397: /* Optionally define this if you have added predicates to
2398: `MACHINE.c'. This macro is called within an initializer of an
2399: array of structures. The first field in the structure is the
2400: name of a predicate and the second field is an arrary of rtl
2401: codes. For each predicate, list all rtl codes that can be in
2402: expressions matched by the predicate. The list should have a
2403: trailing comma. Here is an example of two entries in the list
2404: for a typical RISC machine:
2405:
2406: #define PREDICATE_CODES \
2407: {"gen_reg_rtx_operand", {SUBREG, REG}}, \
2408: {"reg_or_short_cint_operand", {SUBREG, REG, CONST_INT}},
2409:
2410: Defining this macro does not affect the generated code (however,
2411: incorrect definitions that omit an rtl code that may be matched
2412: by the predicate can cause the compiler to malfunction).
2413: Instead, it allows the table built by `genrecog' to be more
2414: compact and efficient, thus speeding up the compiler. The most
2415: important predicates to include in the list specified by this
2416: macro are thoses used in the most insn patterns. */
2417:
2418: #define PREDICATE_CODES \
2419: {"uns_arith_operand", { REG, CONST_INT, SUBREG }}, \
2420: {"arith_operand", { REG, CONST_INT, SUBREG }}, \
2421: {"arith32_operand", { REG, CONST_INT, SUBREG }}, \
2422: {"reg_or_0_operand", { REG, CONST_INT, SUBREG }}, \
2423: {"small_int", { CONST_INT }}, \
2424: {"large_int", { CONST_INT }}, \
2425: {"md_register_operand", { REG }}, \
2426: {"mips_const_double_ok", { CONST_DOUBLE }}, \
2427: {"simple_memory_operand", { MEM, SUBREG }}, \
2428: {"call_memory_operand", { MEM, SUBREG }}, \
2429: {"equality_op", { EQ, NE }}, \
2430: {"cmp_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
2431: LTU, LEU }}, \
2432: {"cmp2_op", { EQ, NE, GT, GE, GTU, GEU, LT, LE, \
2433: LTU, LEU }}, \
2434: {"fcmp_op", { EQ, NE, GT, GE, LT, LE }}, \
2435: {"uns_cmp_op", { GTU, GEU, LTU, LEU }},
2436:
2437:
2438: /* If defined, a C statement to be executed just prior to the
2439: output of assembler code for INSN, to modify the extracted
2440: operands so they will be output differently.
2441:
2442: Here the argument OPVEC is the vector containing the operands
2443: extracted from INSN, and NOPERANDS is the number of elements of
2444: the vector which contain meaningful data for this insn. The
2445: contents of this vector are what will be used to convert the
2446: insn template into assembler code, so you can change the
2447: assembler output by changing the contents of the vector.
2448:
2449: We use it to check if the current insn needs a nop in front of it
2450: because of load delays, and also to update the delay slot
2451: statistics. */
2452:
2453: #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \
2454: do \
2455: { \
2456: if (dslots_number_nops > 0 && mips_load_reg != (rtx)0) \
2457: { \
2458: enum machine_mode mode = GET_MODE (mips_load_reg); \
2459: rtx pattern = PATTERN (INSN); \
2460: \
2461: if (reg_mentioned_p (mips_load_reg, pattern) \
2462: || (mips_load_reg2 != (rtx)0 \
2463: && reg_mentioned_p (mips_load_reg2, pattern)) \
2464: || (mips_load_reg3 != (rtx)0 \
2465: && reg_mentioned_p (mips_load_reg3, pattern)) \
2466: || (mips_load_reg4 != (rtx)0 \
2467: && reg_mentioned_p (mips_load_reg4, pattern)) \
2468: || get_attr_length (INSN) == 0) \
2469: { \
2470: fputs ((set_noreorder) ? "\tnop\n" : "\t#nop\n", asm_out_file); \
2471: } \
2472: else \
2473: dslots_load_filled++; \
2474: \
2475: while (--dslots_number_nops > 0) \
2476: fputs ((set_noreorder) ? "\tnop\n" : "\t#nop\n", asm_out_file); \
2477: \
2478: mips_load_reg = (rtx)0; \
2479: mips_load_reg2 = (rtx)0; \
2480: mips_load_reg3 = (rtx)0; \
2481: mips_load_reg4 = (rtx)0; \
2482: \
2483: if (set_noreorder && --set_noreorder == 0) \
2484: fputs ("\t.set\treorder\n", asm_out_file); \
2485: } \
2486: \
2487: if (TARGET_STATS) \
2488: { \
2489: enum rtx_code code = GET_CODE (INSN); \
2490: if (code == JUMP_INSN || code == CALL_INSN) \
2491: dslots_jump_total++; \
2492: } \
2493: } \
2494: while (0)
2495:
2496:
2497: /* Tell final.c how to eliminate redundant test instructions.
2498: Here we define machine-dependent flags and fields in cc_status
2499: (see `conditions.h'). */
2500:
2501: /* A C compound statement to set the components of `cc_status'
2502: appropriately for an insn INSN whose body is EXP. It is this
2503: macro's responsibility to recognize insns that set the condition
2504: code as a byproduct of other activity as well as those that
2505: explicitly set `(cc0)'.
2506:
2507: This macro is not used on machines that do not use `cc0'. */
2508:
2509: #define NOTICE_UPDATE_CC(EXP, INSN) \
2510: do \
2511: { \
2512: enum attr_type type = get_attr_type (INSN); \
2513: if (type == TYPE_ICMP || type == TYPE_FCMP) \
2514: CC_STATUS_INIT; \
2515: } \
2516: while (0)
2517:
2518: /* A list of names to be used for additional modes for condition
2519: code values in registers (*note Jump Patterns::.). These names
2520: are added to `enum machine_mode' and all have class `MODE_CC'.
2521: By convention, they should start with `CC' and end with `mode'.
2522:
2523: You should only define this macro if your machine does not use
2524: `cc0' and only if additional modes are required.
2525:
2526: On the MIPS, we use CC_FPmode for all floating point, CC_EQmode for
2527: integer equality/inequality comparisons, CC_0mode for comparisons
2528: against 0, and CCmode for other integer comparisons. */
2529:
2530: #define EXTRA_CC_MODES CC_EQmode, CC_FPmode, CC_0mode
2531:
2532: /* A list of C strings giving the names for the modes listed in
2533: `EXTRA_CC_MODES'. For example, the Sparc defines this macro and
2534: `EXTRA_CC_MODES' as
2535:
2536: #define EXTRA_CC_MODES CC_NOOVmode, CCFPmode
2537: #define EXTRA_CC_NAMES "CC_NOOV", "CCFP"
2538:
2539: This macro is not required if `EXTRA_CC_MODES' is not defined. */
2540:
2541: #define EXTRA_CC_NAMES "CC_EQ", "CC_FP", "CC_0"
2542:
2543: /* Returns a mode from class `MODE_CC' to be used when comparison
2544: operation code OP is applied to rtx X. For example, on the
2545: Sparc, `SELECT_CC_MODE' is defined as (see *note Jump
2546: Patterns::. for a description of the reason for this definition)
2547:
2548: #define SELECT_CC_MODE(OP,X) \
2549: (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CCFPmode \
2550: : (GET_CODE (X) == PLUS || GET_CODE (X) == MINUS \
2551: || GET_CODE (X) == NEG) \
2552: ? CC_NOOVmode : CCmode)
2553:
2554: This macro is not required if `EXTRA_CC_MODES' is not defined. */
2555:
2556: #define SELECT_CC_MODE (OP, X) \
2557: (GET_MODE_CLASS (GET_MODE (X)) == MODE_FLOAT ? CC_FPmode : \
2558: (OP == EQ || OP == NE) ? CC_EQmode : CCmode)
2559:
2560:
2561: /* Control the assembler format that we output. */
2562:
2563: /* Output at beginning of assembler file.
2564: If we are optimizing to use the global pointer, create a temporary
2565: file to hold all of the text stuff, and write it out to the end.
2566: This is needed because the MIPS assembler is evidently one pass,
2567: and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
2568: declaration when the code is processed, it generates a two
2569: instruction sequence. */
2570:
2571: #define ASM_FILE_START(STREAM) mips_asm_file_start (STREAM)
2572:
2573: /* Output to assembler file text saying following lines
2574: may contain character constants, extra white space, comments, etc. */
2575:
2576: #define ASM_APP_ON " #APP\n"
2577:
2578: /* Output to assembler file text saying following lines
2579: no longer contain unusual constructs. */
2580:
2581: #define ASM_APP_OFF " #NO_APP\n"
2582:
2583: /* How to refer to registers in assembler output.
2584: This sequence is indexed by compiler's hard-register-number (see above).
2585:
2586: In order to support the two different conventions for register names,
2587: we use the name of a table set up in mips.c, which is overwritten
2588: if -mrnames is used. */
2589:
2590: #define REGISTER_NAMES \
2591: { \
2592: &mips_reg_names[ 0][0], \
2593: &mips_reg_names[ 1][0], \
2594: &mips_reg_names[ 2][0], \
2595: &mips_reg_names[ 3][0], \
2596: &mips_reg_names[ 4][0], \
2597: &mips_reg_names[ 5][0], \
2598: &mips_reg_names[ 6][0], \
2599: &mips_reg_names[ 7][0], \
2600: &mips_reg_names[ 8][0], \
2601: &mips_reg_names[ 9][0], \
2602: &mips_reg_names[10][0], \
2603: &mips_reg_names[11][0], \
2604: &mips_reg_names[12][0], \
2605: &mips_reg_names[13][0], \
2606: &mips_reg_names[14][0], \
2607: &mips_reg_names[15][0], \
2608: &mips_reg_names[16][0], \
2609: &mips_reg_names[17][0], \
2610: &mips_reg_names[18][0], \
2611: &mips_reg_names[19][0], \
2612: &mips_reg_names[20][0], \
2613: &mips_reg_names[21][0], \
2614: &mips_reg_names[22][0], \
2615: &mips_reg_names[23][0], \
2616: &mips_reg_names[24][0], \
2617: &mips_reg_names[25][0], \
2618: &mips_reg_names[26][0], \
2619: &mips_reg_names[27][0], \
2620: &mips_reg_names[28][0], \
2621: &mips_reg_names[29][0], \
2622: &mips_reg_names[30][0], \
2623: &mips_reg_names[31][0], \
2624: &mips_reg_names[32][0], \
2625: &mips_reg_names[33][0], \
2626: &mips_reg_names[34][0], \
2627: &mips_reg_names[35][0], \
2628: &mips_reg_names[36][0], \
2629: &mips_reg_names[37][0], \
2630: &mips_reg_names[38][0], \
2631: &mips_reg_names[39][0], \
2632: &mips_reg_names[40][0], \
2633: &mips_reg_names[41][0], \
2634: &mips_reg_names[42][0], \
2635: &mips_reg_names[43][0], \
2636: &mips_reg_names[44][0], \
2637: &mips_reg_names[45][0], \
2638: &mips_reg_names[46][0], \
2639: &mips_reg_names[47][0], \
2640: &mips_reg_names[48][0], \
2641: &mips_reg_names[49][0], \
2642: &mips_reg_names[50][0], \
2643: &mips_reg_names[51][0], \
2644: &mips_reg_names[52][0], \
2645: &mips_reg_names[53][0], \
2646: &mips_reg_names[54][0], \
2647: &mips_reg_names[55][0], \
2648: &mips_reg_names[56][0], \
2649: &mips_reg_names[57][0], \
2650: &mips_reg_names[58][0], \
2651: &mips_reg_names[59][0], \
2652: &mips_reg_names[60][0], \
2653: &mips_reg_names[61][0], \
2654: &mips_reg_names[62][0], \
2655: &mips_reg_names[63][0], \
2656: &mips_reg_names[64][0], \
2657: &mips_reg_names[65][0], \
2658: &mips_reg_names[66][0], \
2659: }
2660:
2661: /* If defined, a C initializer for an array of structures
2662: containing a name and a register number. This macro defines
2663: additional names for hard registers, thus allowing the `asm'
2664: option in declarations to refer to registers using alternate
2665: names.
2666:
2667: We define both names for the integer registers here. */
2668:
2669: #define ADDITIONAL_REGISTER_NAMES \
2670: { \
2671: { "$0", 0 + GP_REG_FIRST }, \
2672: { "$1", 1 + GP_REG_FIRST }, \
2673: { "$2", 2 + GP_REG_FIRST }, \
2674: { "$3", 3 + GP_REG_FIRST }, \
2675: { "$4", 4 + GP_REG_FIRST }, \
2676: { "$5", 5 + GP_REG_FIRST }, \
2677: { "$6", 6 + GP_REG_FIRST }, \
2678: { "$7", 7 + GP_REG_FIRST }, \
2679: { "$8", 8 + GP_REG_FIRST }, \
2680: { "$9", 9 + GP_REG_FIRST }, \
2681: { "$10", 10 + GP_REG_FIRST }, \
2682: { "$11", 11 + GP_REG_FIRST }, \
2683: { "$12", 12 + GP_REG_FIRST }, \
2684: { "$13", 13 + GP_REG_FIRST }, \
2685: { "$14", 14 + GP_REG_FIRST }, \
2686: { "$15", 15 + GP_REG_FIRST }, \
2687: { "$16", 16 + GP_REG_FIRST }, \
2688: { "$17", 17 + GP_REG_FIRST }, \
2689: { "$18", 18 + GP_REG_FIRST }, \
2690: { "$19", 19 + GP_REG_FIRST }, \
2691: { "$20", 20 + GP_REG_FIRST }, \
2692: { "$21", 21 + GP_REG_FIRST }, \
2693: { "$22", 22 + GP_REG_FIRST }, \
2694: { "$23", 23 + GP_REG_FIRST }, \
2695: { "$24", 24 + GP_REG_FIRST }, \
2696: { "$25", 25 + GP_REG_FIRST }, \
2697: { "$26", 26 + GP_REG_FIRST }, \
2698: { "$27", 27 + GP_REG_FIRST }, \
2699: { "$28", 28 + GP_REG_FIRST }, \
2700: { "$29", 29 + GP_REG_FIRST }, \
2701: { "$30", 30 + GP_REG_FIRST }, \
2702: { "$31", 31 + GP_REG_FIRST }, \
2703: { "$sp", 29 + GP_REG_FIRST }, \
2704: { "$fp", 30 + GP_REG_FIRST }, \
2705: { "at", 1 + GP_REG_FIRST }, \
2706: { "v0", 2 + GP_REG_FIRST }, \
2707: { "v1", 3 + GP_REG_FIRST }, \
2708: { "a0", 4 + GP_REG_FIRST }, \
2709: { "a1", 5 + GP_REG_FIRST }, \
2710: { "a2", 6 + GP_REG_FIRST }, \
2711: { "a3", 7 + GP_REG_FIRST }, \
2712: { "t0", 8 + GP_REG_FIRST }, \
2713: { "t1", 9 + GP_REG_FIRST }, \
2714: { "t2", 10 + GP_REG_FIRST }, \
2715: { "t3", 11 + GP_REG_FIRST }, \
2716: { "t4", 12 + GP_REG_FIRST }, \
2717: { "t5", 13 + GP_REG_FIRST }, \
2718: { "t6", 14 + GP_REG_FIRST }, \
2719: { "t7", 15 + GP_REG_FIRST }, \
2720: { "s0", 16 + GP_REG_FIRST }, \
2721: { "s1", 17 + GP_REG_FIRST }, \
2722: { "s2", 18 + GP_REG_FIRST }, \
2723: { "s3", 19 + GP_REG_FIRST }, \
2724: { "s4", 20 + GP_REG_FIRST }, \
2725: { "s5", 21 + GP_REG_FIRST }, \
2726: { "s6", 22 + GP_REG_FIRST }, \
2727: { "s7", 23 + GP_REG_FIRST }, \
2728: { "t8", 24 + GP_REG_FIRST }, \
2729: { "t9", 25 + GP_REG_FIRST }, \
2730: { "k0", 26 + GP_REG_FIRST }, \
2731: { "k1", 27 + GP_REG_FIRST }, \
2732: { "gp", 28 + GP_REG_FIRST }, \
2733: { "sp", 29 + GP_REG_FIRST }, \
2734: { "fp", 30 + GP_REG_FIRST }, \
2735: { "ra", 31 + GP_REG_FIRST }, \
2736: }
2737:
2738: /* Define results of standard character escape sequences. */
2739: #define TARGET_BELL 007
2740: #define TARGET_BS 010
2741: #define TARGET_TAB 011
2742: #define TARGET_NEWLINE 012
2743: #define TARGET_VT 013
2744: #define TARGET_FF 014
2745: #define TARGET_CR 015
2746:
2747: /* A C compound statement to output to stdio stream STREAM the
2748: assembler syntax for an instruction operand X. X is an RTL
2749: expression.
2750:
2751: CODE is a value that can be used to specify one of several ways
2752: of printing the operand. It is used when identical operands
2753: must be printed differently depending on the context. CODE
2754: comes from the `%' specification that was used to request
2755: printing of the operand. If the specification was just `%DIGIT'
2756: then CODE is 0; if the specification was `%LTR DIGIT' then CODE
2757: is the ASCII code for LTR.
2758:
2759: If X is a register, this macro should print the register's name.
2760: The names can be found in an array `reg_names' whose type is
2761: `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
2762:
2763: When the machine description has a specification `%PUNCT' (a `%'
2764: followed by a punctuation character), this macro is called with
2765: a null pointer for X and the punctuation character for CODE.
2766:
2767: See mips.c for the MIPS specific codes. */
2768:
2769: #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE)
2770:
2771: /* A C expression which evaluates to true if CODE is a valid
2772: punctuation character for use in the `PRINT_OPERAND' macro. If
2773: `PRINT_OPERAND_PUNCT_VALID_P' is not defined, it means that no
2774: punctuation characters (except for the standard one, `%') are
2775: used in this way. */
2776:
2777: #define PRINT_OPERAND_PUNCT_VALID_P(CODE) mips_print_operand_punct[CODE]
2778:
2779: /* A C compound statement to output to stdio stream STREAM the
2780: assembler syntax for an instruction operand that is a memory
2781: reference whose address is ADDR. ADDR is an RTL expression.
2782:
2783: On some machines, the syntax for a symbolic address depends on
2784: the section that the address refers to. On these machines,
2785: define the macro `ENCODE_SECTION_INFO' to store the information
2786: into the `symbol_ref', and then check for it here. */
2787:
2788: #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR)
2789:
2790:
2791: /* A C statement, to be executed after all slot-filler instructions
2792: have been output. If necessary, call `dbr_sequence_length' to
2793: determine the number of slots filled in a sequence (zero if not
2794: currently outputting a sequence), to decide how many no-ops to
2795: output, or whatever.
2796:
2797: Don't define this macro if it has nothing to do, but it is
2798: helpful in reading assembly output if the extent of the delay
2799: sequence is made explicit (e.g. with white space).
2800:
2801: Note that output routines for instructions with delay slots must
2802: be prepared to deal with not being output as part of a sequence
2803: (i.e. when the scheduling pass is not run, or when no slot
2804: fillers could be found.) The variable `final_sequence' is null
2805: when not processing a sequence, otherwise it contains the
2806: `sequence' rtx being output. */
2807:
2808: #define DBR_OUTPUT_SEQEND(STREAM) \
2809: do \
2810: { \
2811: if (set_nomacro > 0 && --set_nomacro == 0) \
2812: fputs ("\t.set\tmacro\n", STREAM); \
2813: \
2814: if (set_noreorder > 0 && --set_noreorder == 0) \
2815: fputs ("\t.set\treorder\n", STREAM); \
2816: \
2817: dslots_jump_filled++; \
2818: fputs ("\n", STREAM); \
2819: } \
2820: while (0)
2821:
2822:
2823: /* How to tell the debugger about changes of source files. Note, the
2824: mips ECOFF format cannot deal with changes of files inside of
2825: functions, which means the output of parser generators like bison
2826: is generally not debuggable without using the -l switch. Lose,
2827: lose, lose. Silicon graphics seems to want all .file's hardwired
2828: to 1. */
2829:
2830: #ifndef SET_FILE_NUMBER
2831: #define SET_FILE_NUMBER() ++num_source_filenames
2832: #endif
2833:
2834: #define ASM_OUTPUT_SOURCE_FILENAME(STREAM, NAME) \
2835: mips_output_filename (STREAM, NAME)
2836:
2837: /* This is how to output a note the debugger telling it the line number
2838: to which the following sequence of instructions corresponds.
2839: Silicon graphics puts a label after each .loc. */
2840:
2841: #ifndef LABEL_AFTER_LOC
2842: #define LABEL_AFTER_LOC(STREAM)
2843: #endif
2844:
2845: #define ASM_OUTPUT_SOURCE_LINE(STREAM, LINE) \
2846: mips_output_lineno (STREAM, LINE)
2847:
2848: /* The MIPS implementation uses some labels for it's own purposed. The
2849: following lists what labels are created, and are all formed by the
2850: pattern $L[a-z].*. The machine independent portion of GCC creates
2851: labels matching: $L[A-Z][0-9]+ and $L[0-9]+.
2852:
2853: LM[0-9]+ Sillicon graphics/ECOFF stabs label before each stmt.
2854: $Lb[0-9]+ Begin blocks for MIPS debug support
2855: $Lc[0-9]+ Label for use in s<xx> operation.
2856: $Le[0-9]+ End blocks for MIPS debug support
2857: $Lp\..+ Half-pic labels.
2858: $Ls[0-9]+ FP-SP difference if -fomit-frame-pointer */
2859:
2860: /* This is how to output the definition of a user-level label named NAME,
2861: such as the label on a static function or variable NAME.
2862:
2863: If we are optimizing the gp, remember that this label has been put
2864: out, so we know not to emit an .extern for it in mips_asm_file_end.
2865: We use one of the common bits in the IDENTIFIER tree node for this,
2866: since those bits seem to be unused, and we don't have any method
2867: of getting the decl nodes from the name. */
2868:
2869: #ifndef COLLECT
2870: #define ASM_OUTPUT_LABEL(STREAM,NAME) \
2871: do { \
2872: assemble_name (STREAM, NAME); \
2873: fputs (":\n", STREAM); \
2874: \
2875: if (TARGET_GP_OPT && mips_section_threshold != 0) \
2876: { \
2877: tree name_tree = get_identifier (NAME); \
2878: TREE_ADDRESSABLE (name_tree) = 1; \
2879: } \
2880: } while (0)
2881:
2882: #else
2883: #define ASM_OUTPUT_LABEL(STREAM,NAME) \
2884: do { \
2885: fprintf (STREAM, "%s:\n", NAME); \
2886: } while (0)
2887: #endif
2888:
2889: /* This is how to output a command to make the user-level label named NAME
2890: defined for reference from other files. */
2891:
2892: #ifndef COLLECT
2893: #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
2894: do { \
2895: fputs ("\t.globl\t", STREAM); \
2896: assemble_name (STREAM, NAME); \
2897: fputs ("\n", STREAM); \
2898: } while (0)
2899:
2900: #else
2901: #define ASM_GLOBALIZE_LABEL(STREAM,NAME) \
2902: do { \
2903: fprintf (STREAM, "\t.globl\t%s\n", NAME); \
2904: } while (0)
2905: #endif
2906:
2907: /* This says how to output an assembler line
2908: to define a global common symbol. */
2909:
2910: #define ASM_OUTPUT_COMMON(STREAM, NAME, SIZE, ROUNDED) \
2911: do { \
2912: fputs ("\n\t.comm\t", (STREAM)); \
2913: assemble_name ((STREAM), (NAME)); \
2914: fprintf ((STREAM), ",%u\n", (ROUNDED)); \
2915: \
2916: if (TARGET_GP_OPT && mips_section_threshold != 0) \
2917: { \
2918: tree name_tree = get_identifier (NAME); \
2919: TREE_ADDRESSABLE (name_tree) = 1; \
2920: } \
2921: } while (0)
2922:
2923: /* This says how to output an assembler line
2924: to define a local common symbol. */
2925:
2926: #define ASM_OUTPUT_LOCAL(STREAM, NAME, SIZE, ROUNDED) \
2927: do { \
2928: fputs ("\n\t.lcomm\t", (STREAM)); \
2929: assemble_name ((STREAM), (NAME)); \
2930: fprintf ((STREAM), ",%u\n", (ROUNDED)); \
2931: \
2932: if (TARGET_GP_OPT && mips_section_threshold != 0) \
2933: { \
2934: tree name_tree = get_identifier (NAME); \
2935: TREE_ADDRESSABLE (name_tree) = 1; \
2936: } \
2937: } while (0)
2938:
2939:
2940: /* This says how to output an external. It would be possible not to
2941: output anything and let undefined symbol become external. However
2942: the assembler uses length information on externals to allocate in
2943: data/sdata bss/sbss, thereby saving exec time. */
2944:
2945: #define ASM_OUTPUT_EXTERNAL(STREAM,DECL,NAME) \
2946: mips_output_external(STREAM,DECL,NAME)
2947:
2948: /* This says what to print at the end of the assembly file */
2949: #define ASM_FILE_END(STREAM) mips_asm_file_end(STREAM)
2950:
2951:
2952: /* This is how to declare a function name. The actual work of
2953: emitting the label is moved to function_prologue, so that we can
2954: get the line number correctly emitted before the .ent directive,
2955: and after any .file directives.
2956:
2957: Also, switch files if we are optimizing the global pointer. */
2958:
2959: #define ASM_DECLARE_FUNCTION_NAME(STREAM,NAME,DECL) \
2960: { \
2961: extern FILE *asm_out_text_file; \
2962: if (TARGET_GP_OPT) \
2963: STREAM = asm_out_text_file; \
2964: \
2965: current_function_name = NAME; \
2966: }
2967:
2968: /* This is how to output a reference to a user-level label named NAME.
2969: `assemble_name' uses this. */
2970:
2971: #define ASM_OUTPUT_LABELREF(STREAM,NAME) fprintf (STREAM, "%s", NAME)
2972:
2973: /* This is how to output an internal numbered label where
2974: PREFIX is the class of label and NUM is the number within the class. */
2975:
2976: #define ASM_OUTPUT_INTERNAL_LABEL(STREAM,PREFIX,NUM) \
2977: fprintf (STREAM, "$%s%d:\n", PREFIX, NUM)
2978:
2979: /* This is how to store into the string LABEL
2980: the symbol_ref name of an internal numbered label where
2981: PREFIX is the class of label and NUM is the number within the class.
2982: This is suitable for output with `assemble_name'. */
2983:
2984: #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \
2985: sprintf (LABEL, "*$%s%d", PREFIX, NUM)
2986:
2987: /* This is how to output an assembler line defining a `double' constant. */
2988:
2989: #define ASM_OUTPUT_DOUBLE(STREAM,VALUE) \
2990: { \
2991: union { double d; long l[2]; } u2; \
2992: u2.d = VALUE; \
2993: fprintf (STREAM, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n", \
2994: u2.l[0], u2.d, u2.l[1]); \
2995: }
2996:
2997: /* This is how to output an assembler line defining a `float' constant. */
2998:
2999: #define ASM_OUTPUT_FLOAT(STREAM,VALUE) \
3000: { \
3001: union { float f; long l; } u2; \
3002: u2.f = VALUE; \
3003: fprintf (STREAM, "\t.word\t0x%08lx\t\t# %.12g\n", u2.l, u2.f); \
3004: }
3005:
3006: /* This is how to output an assembler line defining an `int' constant. */
3007:
3008: #ifndef COLLECT
3009: #define ASM_OUTPUT_INT(STREAM,VALUE) \
3010: do { \
3011: fprintf (STREAM, "\t.word\t"); \
3012: output_addr_const (STREAM, (VALUE)); \
3013: fprintf (STREAM, "\n"); \
3014: } while (0)
3015:
3016: #else
3017: #define ASM_OUTPUT_INT(STREAM,VALUE) \
3018: fprintf (STREAM, "\t.word\t%d\n", VALUE)
3019: #endif
3020:
3021: /* Likewise for `char' and `short' constants. */
3022:
3023: #define ASM_OUTPUT_SHORT(STREAM,VALUE) \
3024: { \
3025: fprintf (STREAM, "\t.half\t"); \
3026: output_addr_const (STREAM, (VALUE)); \
3027: fprintf (STREAM, "\n"); \
3028: }
3029:
3030: #define ASM_OUTPUT_CHAR(STREAM,VALUE) \
3031: { \
3032: fprintf (STREAM, "\t.byte\t"); \
3033: output_addr_const (STREAM, (VALUE)); \
3034: fprintf (STREAM, "\n"); \
3035: }
3036:
3037: /* This is how to output an assembler line defining an `int' constant,
3038: which is not in tree format (for collect.c). */
3039:
3040: #define ASM_OUTPUT_INT_CONST(STREAM,VALUE) \
3041: fprintf(STREAM, "\t.word\t%d\n", VALUE)
3042:
3043: /* This is how to output an assembler line defining an external/static
3044: address which is not in tree format (for collect.c). */
3045:
3046: #define ASM_OUTPUT_PTR_INT_SUM(STREAM, NAME, VALUE) \
3047: do { \
3048: fprintf (STREAM, "\t.word\t"); \
3049: ASM_OUTPUT_LABELREF (STREAM, NAME); \
3050: fprintf (STREAM, "+%d\n", VALUE); \
3051: } while (0)
3052:
3053: #define ASM_OUTPUT_LABELREF_AS_INT(STREAM, NAME) \
3054: do { \
3055: fprintf (STREAM, "\t.word\t"); \
3056: ASM_OUTPUT_LABELREF (STREAM, NAME); \
3057: fprintf (STREAM, "\n"); \
3058: } while (0)
3059:
3060: /* This is how to output an assembler line for a numeric constant byte. */
3061:
3062: #define ASM_OUTPUT_BYTE(STREAM,VALUE) \
3063: fprintf (STREAM, "\t.byte\t0x%x\n", (VALUE))
3064:
3065: /* This is how to output an element of a case-vector that is absolute. */
3066:
3067: #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) \
3068: fprintf (STREAM, "\t.word\t$L%d\n", VALUE)
3069:
3070: /* This is how to output an element of a case-vector that is relative.
3071: (We do not use such vectors,
3072: but we must define this macro anyway.) */
3073:
3074: #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, VALUE, REL) \
3075: fprintf (STREAM, "\t.word\t$L%d-$L%d\n", VALUE, REL)
3076:
3077: /* This is how to emit the initial label for switch statements. We
3078: need to put the switch labels somewhere else from the text section,
3079: because the MIPS assembler gets real confused about line numbers if
3080: .word's appear in the text section. */
3081:
3082: #define ASM_OUTPUT_CASE_LABEL(STREAM, PREFIX, NUM, JUMPTABLE) \
3083: { \
3084: rdata_section (); \
3085: ASM_OUTPUT_ALIGN (STREAM, 2); \
3086: ASM_OUTPUT_INTERNAL_LABEL (STREAM, PREFIX, NUM); \
3087: }
3088:
3089: /* This is how to output an assembler line
3090: that says to advance the location counter
3091: to a multiple of 2**LOG bytes. */
3092:
3093: #define ASM_OUTPUT_ALIGN(STREAM,LOG) \
3094: { \
3095: int mask = (1 << (LOG)) - 1; \
3096: fprintf (STREAM, "\t.align\t%d\n", (LOG)); \
3097: }
3098:
3099: /* This is how to output an assembler line to to advance the location
3100: counter by SIZE bytes. */
3101:
3102: #define ASM_OUTPUT_SKIP(STREAM,SIZE) \
3103: fprintf (STREAM, "\t.space\t%u\n", (SIZE))
3104:
3105:
3106: /* This is how to output a string. */
3107: #define ASM_OUTPUT_ASCII(STREAM, STRING, LEN) \
3108: do { \
3109: register int i, c, len = (LEN), cur_pos = 17; \
3110: register unsigned char *string = (unsigned char *)(STRING); \
3111: fprintf ((STREAM), "\t.ascii\t\""); \
3112: for (i = 0; i < len; i++) \
3113: { \
3114: register int c = string[i]; \
3115: \
3116: switch (c) \
3117: { \
3118: case '\"': \
3119: case '\\': \
3120: putc ('\\', (STREAM)); \
3121: putc (c, (STREAM)); \
3122: cur_pos += 2; \
3123: break; \
3124: \
3125: case TARGET_NEWLINE: \
3126: fputs ("\\n", (STREAM)); \
3127: if (i+1 < len \
3128: && (((c = string[i+1]) >= '\040' && c <= '~') \
3129: || c == TARGET_TAB)) \
3130: cur_pos = 32767; /* break right here */ \
3131: else \
3132: cur_pos += 2; \
3133: break; \
3134: \
3135: case TARGET_TAB: \
3136: fputs ("\\t", (STREAM)); \
3137: cur_pos += 2; \
3138: break; \
3139: \
3140: case TARGET_FF: \
3141: fputs ("\\f", (STREAM)); \
3142: cur_pos += 2; \
3143: break; \
3144: \
3145: case TARGET_BS: \
3146: fputs ("\\b", (STREAM)); \
3147: cur_pos += 2; \
3148: break; \
3149: \
3150: case TARGET_CR: \
3151: fputs ("\\r", (STREAM)); \
3152: cur_pos += 2; \
3153: break; \
3154: \
3155: default: \
3156: if (c >= ' ' && c < 0177) \
3157: { \
3158: putc (c, (STREAM)); \
3159: cur_pos++; \
3160: } \
3161: else \
3162: { \
3163: fprintf ((STREAM), "\\%03o", c); \
3164: cur_pos += 4; \
3165: } \
3166: } \
3167: \
3168: if (cur_pos > 72 && i+1 < len) \
3169: { \
3170: cur_pos = 17; \
3171: fprintf ((STREAM), "\"\n\t.ascii\t\""); \
3172: } \
3173: } \
3174: fprintf ((STREAM), "\"\n"); \
3175: } while (0)
3176:
3177: /* Handle certain cpp directives used in header files on sysV. */
3178: #define SCCS_DIRECTIVE
3179:
3180: /* Output #ident as a in the read-only data section. */
3181: #define ASM_OUTPUT_IDENT(FILE, STRING) \
3182: { \
3183: char *p = STRING; \
3184: int size = strlen (p) + 1; \
3185: rdata_section (); \
3186: assemble_string (p, size); \
3187: }
3188:
3189:
3190: /* Output before read-only data. */
3191:
3192: #define TEXT_SECTION_ASM_OP "\t.text"
3193:
3194: /* Output before writable data. */
3195:
3196: #define DATA_SECTION_ASM_OP "\t.data"
3197:
3198: /* Output before writable short data. */
3199:
3200: #define SDATA_SECTION_ASM_OP "\t.sdata"
3201:
3202: /* Output before read-only data. */
3203:
3204: #define RDATA_SECTION_ASM_OP "\t.rdata"
3205: #define READONLY_DATA_SECTION rdata_section
3206:
3207: /* What other sections we support other than the normal .data/.text. */
3208:
3209: #define EXTRA_SECTIONS in_sdata, in_rdata, in_last_p1
3210:
3211: /* Define the additional functions to select our additional sections. */
3212:
3213: /* on the MIPS it is not a good idea to put constants in the text
3214: section, since this defeats the sdata/data mechanism. This is
3215: especially true when -O is used. In this case an effort is made to
3216: address with faster (gp) register relative addressing, which can
3217: only get at sdata and sbss items (there is no stext !!) However,
3218: if the constant is too large for sdata, and it's readonly, it
3219: will go into the .rdata section. */
3220:
3221: #define EXTRA_SECTION_FUNCTIONS \
3222: void \
3223: sdata_section () \
3224: { \
3225: if (in_section != in_sdata) \
3226: { \
3227: fprintf (asm_out_file, "%s\n", SDATA_SECTION_ASM_OP); \
3228: in_section = in_sdata; \
3229: } \
3230: } \
3231: \
3232: void \
3233: rdata_section () \
3234: { \
3235: if (in_section != in_rdata) \
3236: { \
3237: fprintf (asm_out_file, "%s\n", RDATA_SECTION_ASM_OP); \
3238: in_section = in_rdata; \
3239: } \
3240: }
3241:
3242: /* Given a decl node or constant node, choose the section to output it in
3243: and select that section. */
3244:
3245: #define SELECT_SECTION_MODE(MODE,RTX) \
3246: { \
3247: extern int mips_section_threshold; \
3248: if ((GET_MODE_SIZE(MODE) / BITS_PER_UNIT) <= mips_section_threshold \
3249: && mips_section_threshold > 0) \
3250: sdata_section (); \
3251: else \
3252: rdata_section (); \
3253: } \
3254:
3255: #define SELECT_SECTION(DECL,RELOC) \
3256: { \
3257: extern int mips_section_threshold; \
3258: if (int_size_in_bytes (TREE_TYPE (DECL)) <= mips_section_threshold \
3259: && mips_section_threshold > 0) \
3260: sdata_section (); \
3261: else if (TREE_CODE (DECL) == STRING_CST) \
3262: { \
3263: if (flag_writable_strings) \
3264: data_section (); \
3265: else \
3266: rdata_section (); \
3267: } \
3268: else if (TREE_CODE (DECL) != VAR_DECL) \
3269: rdata_section (); \
3270: else if (!TREE_READONLY (DECL)) \
3271: data_section (); \
3272: else \
3273: rdata_section (); \
3274: }
3275:
3276:
3277: /* Store in OUTPUT a string (made with alloca) containing
3278: an assembler-name for a local static variable named NAME.
3279: LABELNO is an integer which is different for each call. */
3280:
3281: #define ASM_FORMAT_PRIVATE_NAME(OUTPUT, NAME, LABELNO) \
3282: ( (OUTPUT) = (char *) alloca (strlen ((NAME)) + 10), \
3283: sprintf ((OUTPUT), "%s.%d", (NAME), (LABELNO)))
3284:
3285: #define ASM_OUTPUT_REG_PUSH(STREAM,REGNO) \
3286: do \
3287: { \
3288: fprintf (STREAM, "\tsubu\t%s,%s,8\n\tsw\t%s,0(%s)\n", \
3289: reg_names[STACK_POINTER_REGNUM], \
3290: reg_names[STACK_POINTER_REGNUM], \
3291: reg_names[REGNO], \
3292: reg_names[STACK_POINTER_REGNUM]); \
3293: } \
3294: while (0)
3295:
3296: #define ASM_OUTPUT_REG_POP(STREAM,REGNO) \
3297: do \
3298: { \
3299: if (! set_noreorder) \
3300: fprintf (STREAM, "\t.set\tnoreorder\n"); \
3301: \
3302: dslots_load_total++; \
3303: dslots_load_filled++; \
3304: fprintf (STREAM, "\tlw\t%s,0(%s)\n\taddu\t%s,%s,8\n", \
3305: reg_names[REGNO], \
3306: reg_names[STACK_POINTER_REGNUM], \
3307: reg_names[STACK_POINTER_REGNUM], \
3308: reg_names[STACK_POINTER_REGNUM]); \
3309: \
3310: if (! set_noreorder) \
3311: fprintf (STREAM, "\t.set\treorder\n"); \
3312: } \
3313: while (0)
3314:
3315: /* Define the parentheses used to group arithmetic operations
3316: in assembler code. */
3317:
3318: #define ASM_OPEN_PAREN "("
3319: #define ASM_CLOSE_PAREN ")"
3320:
3321: /* How to start an assembler comment. */
3322: #ifndef ASM_COMMENT_START
3323: #define ASM_COMMENT_START "\t\t# "
3324: #endif
3325:
3326:
3327:
3328: /* Macros for mips-tfile.c to encapsulate stabs in ECOFF, and for
3329: and mips-tdump.c to print them out.
3330:
3331: These must match the corresponding definitions in gdb/mipsread.c.
3332: Unfortunately, gcc and gdb do not currently share any directories. */
3333:
3334: #define CODE_MASK 0x8F300
3335: #define MIPS_IS_STAB(sym) (((sym)->index & 0xFFF00) == CODE_MASK)
3336: #define MIPS_MARK_STAB(code) ((code)+CODE_MASK)
3337: #define MIPS_UNMARK_STAB(code) ((code)-CODE_MASK)
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.