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1.1 ! root 1: ;; Mips.md Naive version of Machine Description for MIPS ! 2: ;; Contributed by A. Lichnewsky, [email protected] ! 3: ;; Copyright (C) 1989 Free Software Foundation, Inc. ! 4: ! 5: ;; This file is part of GNU CC. ! 6: ! 7: ;; GNU CC is free software; you can redistribute it and/or modify ! 8: ;; it under the terms of the GNU General Public License as published by ! 9: ;; the Free Software Foundation; either version 1, or (at your option) ! 10: ;; any later version. ! 11: ! 12: ;; GNU CC is distributed in the hope that it will be useful, ! 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 15: ;; GNU General Public License for more details. ! 16: ! 17: ;; You should have received a copy of the GNU General Public License ! 18: ;; along with GNU CC; see the file COPYING. If not, write to ! 19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 20: ! 21: ;; ! 22: ;;------------------------------------------------------------------------ ! 23: ;; ! 24: ! 25: ;; ! 26: ;; .................... ! 27: ;; ! 28: ;; Peephole Optimizations for ! 29: ;; ! 30: ;; ARITHMETIC ! 31: ;; ! 32: ;; .................... ! 33: ;; ! 34: ;;- The following peepholes are ! 35: ;;- motivated by the fact that ! 36: ;;- stack movement result in some ! 37: ;;- cases in embarrassing sequences ! 38: ;;- of addiu SP,SP,int ! 39: ;;- addiu SP,SP,other_int ! 40: ! 41: ;;- -------------------- ! 42: ;;- REMARK: this would be done better ! 43: ;;- by analysis of dependencies in ! 44: ;;- basic blocks, prior to REG ALLOC, ! 45: ;;- and simplification of trees: ! 46: ;;- (+ (+ REG const) const) ! 47: ;;- -> (+ REG newconst) ! 48: ;;- -------------------- ! 49: (define_peephole ! 50: [(set (match_operand:SI 0 "general_operand" "=r") ! 51: (plus:SI (match_operand:SI 1 "general_operand" "r") ! 52: (match_operand:SI 2 "general_operand" "IJ"))) ! 53: (set (match_operand:SI 3 "general_operand" "=r") ! 54: (plus:SI (match_dup 0) ! 55: (match_operand:SI 4 "general_operand" "IJ")))] ! 56: " /* DATA FLOW SEMANTICS*/ ! 57: (((REGNO (operands[0])) == (REGNO (operands[3]))) ! 58: || ! 59: dead_or_set_p (insn, operands[0])) ! 60: && ! 61: ( /* CONSTRAINTS */ ! 62: (GET_CODE (operands[2]) == CONST_INT) ! 63: && ((CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I')) ! 64: ||(CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) ! 65: && (GET_CODE (operands[4]) == CONST_INT) ! 66: && ((CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'I')) ! 67: ||(CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'J')))) ! 68: " ! 69: "* ! 70: { ! 71: rtx ops[3]; ! 72: int i; ! 73: i = INTVAL (operands[2]) + INTVAL (operands[4]); ! 74: if (i == 0) ! 75: { ! 76: if ((REGNO (operands[3])) == (REGNO (operands[1]))) ! 77: { ! 78: if ((REGNO (operands[0])) == (REGNO (operands[3]))) ! 79: return \"\\t\\t# NULL %0 <- %1 + %2; %3 <- %0 + %4\"; ! 80: else ! 81: return \"\\t\\t# NULL %0 <- %1 + %2; %3 <- %0 + %4 and dead %0\"; ! 82: } ! 83: else ! 84: return \"add%:\\t%3,%1,$0\\t# %0 <- %1 + %2; %3 <- %0 + %4 and dead %0\"; ! 85: } ! 86: else ! 87: { ! 88: ops[0] = operands[3]; ! 89: ops[1] = operands[1]; ! 90: ops[2] = gen_rtx (CONST_INT, VOIDmode, i); ! 91: output_asm_insn (\"addi%:\\t%0,%1,%2\\t# simplification of:\", ops); ! 92: return \"\\t\\t\\t# %0 <- %1 + %2; %3 <- %0 + %4 and dead %0\"; ! 93: } ! 94: }") ! 95: ! 96: ! 97: ! 98: ! 99: (define_peephole ! 100: [(set (match_operand:SI 0 "general_operand" "=r") ! 101: (plus:SI (match_operand:SI 1 "general_operand" "r") ! 102: (match_operand:SI 2 "general_operand" "IJ"))) ! 103: (set (match_operand:SI 3 "general_operand" "=r") ! 104: (minus:SI (match_dup 0) ! 105: (match_operand:SI 4 "general_operand" "IJ")))] ! 106: "(((REGNO (operands[0])) == (REGNO (operands[3]))) ! 107: || ! 108: dead_or_set_p (insn, operands[0])) ! 109: && ! 110: ( /* CONSTRAINTS */ ! 111: (GET_CODE (operands[2]) == CONST_INT) ! 112: && ((CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I')) ! 113: ||(CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) ! 114: && (GET_CODE (operands[4]) == CONST_INT) ! 115: && ((CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'I')) ! 116: ||(CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'J')))) ! 117: " ! 118: "* ! 119: { ! 120: rtx ops[3]; ! 121: int i; ! 122: i = INTVAL (operands[2]) - INTVAL (operands[4]); ! 123: if (i == 0) ! 124: { ! 125: if ((REGNO (operands[3])) == (REGNO (operands[1]))) ! 126: { ! 127: if ((REGNO (operands[0])) == (REGNO (operands[3]))) ! 128: return \"\\t\\t# NULL %0 <- %1 + %2; %3 <- %0 - %4\"; ! 129: else ! 130: return \"\\t\\t# NULL %0 <- %1 + %2; %3 <- %0 - %4 and dead %0\"; ! 131: } ! 132: else ! 133: return \"add%:\\t%3,%1,$0\\t# %0 <- %1 + %2; %3 <- %0 - %4 and dead %0\"; ! 134: } ! 135: else ! 136: { ! 137: ops[0] = operands[3]; ! 138: ops[1] = operands[1]; ! 139: ops[2] = gen_rtx (CONST_INT, VOIDmode, i); ! 140: output_asm_insn (\"addi%:\\t%0,%1,%2\\t# simplification of:\", ops); ! 141: return \"\\t\\t\\t# %0 <- %1 + %2; %3 <- %0 - %4 and dead %0\"; ! 142: } ! 143: }") ! 144: ! 145: ! 146: (define_peephole ! 147: [(set (match_operand:SI 0 "general_operand" "=r") ! 148: (minus:SI (match_operand:SI 1 "general_operand" "r") ! 149: (match_operand:SI 2 "general_operand" "IJ"))) ! 150: (set (match_operand:SI 3 "general_operand" "=r") ! 151: (plus:SI (match_dup 0) ! 152: (match_operand:SI 4 "general_operand" "IJ")))] ! 153: "(((REGNO (operands[0])) == (REGNO (operands[3]))) ! 154: || ! 155: dead_or_set_p (insn, operands[0])) ! 156: && ! 157: ( /* CONSTRAINTS */ ! 158: (GET_CODE (operands[2]) == CONST_INT) ! 159: && ((CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I')) ! 160: ||(CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))) ! 161: && (GET_CODE (operands[4]) == CONST_INT) ! 162: && ((CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'I')) ! 163: ||(CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'J')))) ! 164: " ! 165: "* ! 166: { ! 167: rtx ops[3]; ! 168: int i; ! 169: i = (- INTVAL (operands[2])) + INTVAL (operands[4]); ! 170: if (i == 0) ! 171: { ! 172: if ((REGNO (operands[3])) == (REGNO (operands[1]))) ! 173: { ! 174: if ((REGNO (operands[0])) == (REGNO (operands[3]))) ! 175: return \"\\t\\t# NULL %0 <- %1 - %2; %3 <- %0 + %4\"; ! 176: else ! 177: return \"\\t\\t# NULL %0 <- %1 - %2; %3 <- %0 + %4 and dead %0\"; ! 178: } ! 179: else ! 180: return \"add%:\\t%3,%1,$0\\t# %0 <- %1 - %2; %3 <- %0 + %4 and dead %0\"; ! 181: } ! 182: else ! 183: { ! 184: ops[0] = operands[3]; ! 185: ops[1] = operands[1]; ! 186: ops[2] = gen_rtx (CONST_INT, VOIDmode, i); ! 187: output_asm_insn (\"addi%:\\t%0,%1,%2\\t# simplification of:\", ops); ! 188: return \"\\t\\t\\t# %0 <- %1 - %2; %3 <- %0 + %4 and dead %0\"; ! 189: } ! 190: }") ! 191: ! 192: ! 193: ! 194: ! 195: (define_peephole ! 196: [(set (match_operand:SI 0 "general_operand" "=r") ! 197: (minus:SI (match_operand:SI 1 "general_operand" "r") ! 198: (match_operand:SI 2 "general_operand" "IJ"))) ! 199: (set (match_operand:SI 3 "general_operand" "=r") ! 200: (minus:SI (match_dup 0) ! 201: (match_operand:SI 4 "general_operand" "IJ")))] ! 202: "((REGNO (operands[0]) == REGNO (operands[3]) ! 203: || dead_or_set_p (insn, operands[0])) ! 204: && ! 205: (GET_CODE (operands[2]) == CONST_INT ! 206: && (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I') ! 207: || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) ! 208: && GET_CODE (operands[4]) == CONST_INT ! 209: && (CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'I') ! 210: || CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'J'))))" ! 211: "* ! 212: { ! 213: rtx ops[3]; ! 214: int i = - (INTVAL (operands[2]) + INTVAL (operands[4])); ! 215: ! 216: if (i == 0) ! 217: { ! 218: if (REGNO (operands[3]) == REGNO (operands[1])) ! 219: { ! 220: if (REGNO (operands[0]) == REGNO (operands[3])) ! 221: return \"\\t\\t# NULL %0 <- %1 - %2; %3 <- %0 - %4\"; ! 222: else ! 223: return \"\\t\\t# NULL %0 <- %1 - %2; %3 <- %0 - %4 and dead %0\"; ! 224: } ! 225: else ! 226: return \"add%:\\t%3,%1,$0\\t# %0 <- %1 - %2; %3 <- %0 - %4 and dead %0\"; ! 227: } ! 228: else ! 229: { ! 230: ops[0] = operands[3]; ! 231: ops[1] = operands[1]; ! 232: ops[2] = gen_rtx (CONST_INT, VOIDmode, i); ! 233: output_asm_insn (\"addi%:\\t%0,%1,%2\\t# simplification of:\", ops); ! 234: return \"\\t\\t\\t# %0 <- %1 - %2; %3 <- %0 - %4 and dead %0\"; ! 235: } ! 236: }") ! 237: ! 238: ! 239: ;; ! 240: ;; .................... ! 241: ;; ! 242: ;; ARITHMETIC ! 243: ;; ! 244: ;; .................... ! 245: ;; ! 246: ! 247: (define_insn "adddf3" ! 248: [(set (match_operand:DF 0 "general_operand" "=f") ! 249: (plus:DF (match_operand:DF 1 "general_operand" "%f") ! 250: (match_operand:DF 2 "general_operand" "f")))] ! 251: "" ! 252: "add.d\\t%0,%1,%2") ! 253: ! 254: (define_insn "addsf3" ! 255: [(set (match_operand:SF 0 "general_operand" "=f") ! 256: (plus:SF (match_operand:SF 1 "general_operand" "%f") ! 257: (match_operand:SF 2 "general_operand" "f")))] ! 258: "" ! 259: "add.s\\t%0,%1,%2") ! 260: ! 261: (define_insn "addsi3" ! 262: [(set (match_operand:SI 0 "register_operand" "=r") ! 263: (plus:SI (match_operand:SI 1 "register_operand" "%r") ! 264: (match_operand:SI 2 "general_operand" "rIJ")))] ! 265: "" ! 266: "* ! 267: { ! 268: if (GET_CODE (operands[2]) == CONST_INT) ! 269: { ! 270: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I')) ! 271: return \"addi%:\\t%0,%1,%x2\\t#addsi3\\t%1,%d2 -> %0\"; ! 272: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) ! 273: return \"add%:\\t%0,%1,$0\\t#addsi3\\t%1,%2 -> %0\"; ! 274: else abort_with_insn (insn, \"Constant does not fit descriptor\"); ! 275: } ! 276: else ! 277: return \"add%:\\t%0,%1,%2\\t#addsi3\\t%1,%2 -> %0\"; ! 278: }") ! 279: ! 280: (define_insn "addhi3" ! 281: [(set (match_operand:HI 0 "general_operand" "=r") ! 282: (plus:HI (match_operand:HI 1 "general_operand" "%r") ! 283: (match_operand:HI 2 "general_operand" "rIJ")))] ! 284: "" ! 285: "* ! 286: { ! 287: if (GET_CODE (operands[2]) == CONST_INT) ! 288: { ! 289: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I')) ! 290: return \"addi%:\\t%0,%1,%x2\\t#addhi3\\t%1,%d2 -> %0\"; ! 291: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) ! 292: return \"add%:\\t%0,%1,$0\\t#addhi3\\t%1,%2 -> %0\"; ! 293: else abort_with_insn (insn, \"Constant does not fit descriptor\"); ! 294: } ! 295: else ! 296: return \"add%:\\t%0,%1,%2\\t#addhi3 %1,%2 -> %0\"; ! 297: ! 298: }") ! 299: ! 300: (define_insn "addqi3" ! 301: [(set (match_operand:QI 0 "general_operand" "=r") ! 302: (plus:QI (match_operand:QI 1 "general_operand" "%r") ! 303: (match_operand:QI 2 "general_operand" "rIJ")))] ! 304: "" ! 305: "* ! 306: { ! 307: if (GET_CODE (operands[2]) == CONST_INT) ! 308: { ! 309: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I')) ! 310: return \"addi%:\\t%0,%1,%x2\\t#addqi3\\t%1,%d2 -> %0\"; ! 311: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) ! 312: return \"add%:\\t%0,%1,$0\\t#addqi3\\t%1,%2 -> %0\"; ! 313: else abort_with_insn (insn, \"Constant does not fit descriptor\"); ! 314: } ! 315: else ! 316: return \"add%:\\t%0,%1,%2\\t#addqi3 %1,%2 -> %0\"; ! 317: }") ! 318: ! 319: ;;- All kinds of subtract instructions. ! 320: ! 321: (define_insn "subdf3" ! 322: [(set (match_operand:DF 0 "general_operand" "=f") ! 323: (minus:DF (match_operand:DF 1 "general_operand" "f") ! 324: (match_operand:DF 2 "general_operand" "f")))] ! 325: "" ! 326: "sub.d\\t%0,%1,%2") ! 327: ! 328: (define_insn "subsf3" ! 329: [(set (match_operand:SF 0 "general_operand" "=f") ! 330: (minus:SF (match_operand:SF 1 "general_operand" "f") ! 331: (match_operand:SF 2 "general_operand" "f")))] ! 332: "" ! 333: "sub.s\\t%0,%1,%2") ! 334: ! 335: (define_insn "subsi3" ! 336: [(set (match_operand:SI 0 "general_operand" "=r") ! 337: (minus:SI (match_operand:SI 1 "general_operand" "r") ! 338: (match_operand:SI 2 "general_operand" "rIJ")))] ! 339: "" ! 340: "* ! 341: { ! 342: if (GET_CODE (operands[2]) == CONST_INT) ! 343: { ! 344: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I')) ! 345: { ! 346: rtx ops[4]; ! 347: ops[0] = operands[0]; ! 348: ops[1] = operands[1]; ! 349: ops[3] = operands[2]; ! 350: ops[2] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[2])); ! 351: output_asm_insn (\"addi%:\\t%0,%1,%x2\\t#subsi3\\t%1,%d3 -> %0\", ! 352: ops); ! 353: return \"\"; ! 354: } ! 355: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) ! 356: return \"sub%:\\t%0,%1,$0\\t#subsi3\\t%1,%2 -> %0\"; ! 357: else abort_with_insn (insn, \"Constant does not fit descriptor\"); ! 358: } ! 359: else ! 360: return \"sub%:\\t%0,%1,%2\\t#subsi3 %1,%2 -> %0\"; ! 361: }") ! 362: ! 363: (define_insn "subhi3" ! 364: [(set (match_operand:HI 0 "general_operand" "=r") ! 365: (minus:HI (match_operand:HI 1 "general_operand" "r") ! 366: (match_operand:HI 2 "general_operand" "r")))] ! 367: "" ! 368: "* ! 369: { ! 370: if (GET_CODE (operands[2]) == CONST_INT) ! 371: { ! 372: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I')) ! 373: { ! 374: rtx ops[4]; ! 375: ops[0] = operands[0]; ! 376: ops[1] = operands[1]; ! 377: ops[3] = operands[2]; ! 378: ops[2] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[2])); ! 379: output_asm_insn (\"addi%:\\t%0,%1,%x2\\t#subhi3\\t%1,%d3 -> %0\" ! 380: , ops); ! 381: return \"\"; ! 382: } ! 383: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) ! 384: return \"sub%:\\t%0,%1,$0\\t#subhi3\\t%1,%2 -> %0\"; ! 385: else abort_with_insn (insn, \"Constant does not fit descriptor\"); ! 386: } ! 387: else ! 388: return \"sub%:\\t%0,%1,%2\\t#subhi3 %1,%2 -> %0\"; ! 389: }") ! 390: ! 391: (define_insn "subqi3" ! 392: [(set (match_operand:QI 0 "general_operand" "=r") ! 393: (minus:QI (match_operand:QI 1 "general_operand" "r") ! 394: (match_operand:QI 2 "general_operand" "r")))] ! 395: "" ! 396: "* ! 397: { ! 398: if (GET_CODE (operands[2]) == CONST_INT) ! 399: { ! 400: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I')) ! 401: { ! 402: rtx ops[4]; ! 403: ops[0] = operands[0]; ! 404: ops[1] = operands[1]; ! 405: ops[3] = operands[2]; ! 406: ops[2] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[2])); ! 407: output_asm_insn (\"addi%:\\t%0,%1,%x2\\t#subqi3\\t%1,%d3 -> %0\" ! 408: , ops); ! 409: return \"\"; ! 410: } ! 411: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) ! 412: return \"sub%:\\t%0,%1,$0\\t#subqi3\\t%1,%2 -> %0\"; ! 413: else abort_with_insn (insn, \"Constant does not fit descriptor\"); ! 414: } ! 415: else ! 416: return \"sub%:\\t%0,%1,%2\\t#subqi3 %1,%2 -> %0\"; ! 417: }") ! 418: ! 419: ;;- Multiply instructions. ! 420: ! 421: (define_insn "muldf3" ! 422: [(set (match_operand:DF 0 "general_operand" "=f") ! 423: (mult:DF (match_operand:DF 1 "general_operand" "%f") ! 424: (match_operand:DF 2 "general_operand" "f")))] ! 425: "" ! 426: "mul.d\\t%0,%1,%2") ! 427: ! 428: (define_insn "mulsf3" ! 429: [(set (match_operand:SF 0 "general_operand" "=f") ! 430: (mult:SF (match_operand:SF 1 "general_operand" "%f") ! 431: (match_operand:SF 2 "general_operand" "f")))] ! 432: "" ! 433: "mul.s\\t%0,%1,%2") ! 434: ! 435: (define_insn "mulsi3" ! 436: [(set (match_operand:SI 0 "general_operand" "=r") ! 437: (mult:SI (match_operand:SI 1 "general_operand" "%r") ! 438: (match_operand:SI 2 "general_operand" "r")))] ! 439: "" ! 440: "mul\\t%0,%1,%2\\t#mulsi3 %1,%2 -> %0") ! 441: ! 442: (define_insn "mulhi3" ! 443: [(set (match_operand:HI 0 "general_operand" "=r") ! 444: (mult:HI (match_operand:HI 1 "general_operand" "%r") ! 445: (match_operand:HI 2 "general_operand" "r")))] ! 446: "" ! 447: "mul\\t%0,%1,%2\\t#mulhi3 %1,%2 -> %0") ! 448: ! 449: (define_insn "mulqi3" ! 450: [(set (match_operand:QI 0 "general_operand" "=r") ! 451: (mult:QI (match_operand:QI 1 "general_operand" "%r") ! 452: (match_operand:QI 2 "general_operand" "r")))] ! 453: "" ! 454: "mul\\t%0,%1,%2\\t#mulhi3 %1,%2 -> %0") ! 455: ! 456: ;;- Divide instructions. ! 457: ! 458: (define_insn "divdf3" ! 459: [(set (match_operand:DF 0 "general_operand" "=f") ! 460: (div:DF (match_operand:DF 1 "general_operand" "f") ! 461: (match_operand:DF 2 "general_operand" "f")))] ! 462: "" ! 463: "div.d\\t%0,\\t%1,%2") ! 464: ! 465: (define_insn "divsf3" ! 466: [(set (match_operand:SF 0 "general_operand" "=f") ! 467: (div:SF (match_operand:SF 1 "general_operand" "f") ! 468: (match_operand:SF 2 "general_operand" "f")))] ! 469: "" ! 470: "div.s\\t%0,%1,%2") ! 471: ! 472: (define_insn "divsi3" ! 473: [(set (match_operand:SI 0 "general_operand" "=r") ! 474: (div:SI (match_operand:SI 1 "general_operand" "r") ! 475: (match_operand:SI 2 "general_operand" "r")))] ! 476: "" ! 477: "div\\t%0,%1,%2\\t#divsi3 %1,%2 -> %0") ! 478: ! 479: (define_insn "divhi3" ! 480: [(set (match_operand:HI 0 "general_operand" "=r") ! 481: (div:HI (match_operand:HI 1 "general_operand" "r") ! 482: (match_operand:HI 2 "general_operand" "r")))] ! 483: "" ! 484: "div\\t%0,%1,%2\\t#divhi3 %1,%2 -> %0") ! 485: ! 486: (define_insn "divqi3" ! 487: [(set (match_operand:QI 0 "general_operand" "=r") ! 488: (div:QI (match_operand:QI 1 "general_operand" "r") ! 489: (match_operand:QI 2 "general_operand" "r")))] ! 490: "" ! 491: "div\\t%0,%1,%2\\t#divqi3 %1,%2 -> %0") ! 492: ! 493: ;; ! 494: ;; .................... ! 495: ;; ! 496: ;; LOGICAL ! 497: ;; ! 498: ;; .................... ! 499: ;; ! 500: ! 501: (define_insn "anddi3" ! 502: [(set (match_operand:DI 0 "general_operand" "=r") ! 503: (and:DI (match_operand:DI 1 "general_operand" "%r") ! 504: (match_operand:DI 2 "general_operand" "r")))] ! 505: "" ! 506: "* ! 507: { ! 508: rtx xops[3]; ! 509: if ((REGNO (operands[0]) != (REGNO (operands[1]) +1)) ! 510: && ! 511: (REGNO (operands[0]) != (REGNO (operands[2]) +1))) ! 512: { ! 513: /* TAKE CARE OF OVERLAPS */ ! 514: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])); ! 515: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 516: xops[2] = gen_rtx (REG, SImode, REGNO (operands[2])); ! 517: output_asm_insn (\"and\\t%0,%1,%2\\t#anddi %1,%2 -> %0\", xops); ! 518: xops[0] = gen_rtx (REG, SImode, REGNO (xops[0])+1); ! 519: xops[1] = gen_rtx (REG, SImode, REGNO (xops[1])+1); ! 520: xops[2] = gen_rtx (REG, SImode, REGNO (xops[2])+1); ! 521: output_asm_insn (\"and\\t%0,%1,%2\\t#anddi %1,%2 -> %0\", xops); ! 522: } ! 523: else ! 524: abort (); ! 525: return \"\"; ! 526: }") ! 527: ! 528: (define_insn "andsi3" ! 529: [(set (match_operand:SI 0 "general_operand" "=r,&r") ! 530: (and:SI (match_operand:SI 1 "general_operand" "%r,r") ! 531: (match_operand:SI 2 "general_operand" "rJ,I")))] ! 532: "" ! 533: "* ! 534: { ! 535: rtx xops[3]; ! 536: if (GET_CODE (operands[2]) == CONST_INT) ! 537: { ! 538: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I')) ! 539: if (INTVAL (operands[2]) >= 0) ! 540: { ! 541: return \"andi\\t%0,%1,%x2\\t#andsi3\\t%1,%d2 -> %0\"; ! 542: } ! 543: else ! 544: { ! 545: xops[0] = operands[0]; ! 546: xops[1] = operands[1];; ! 547: xops[2] = gen_rtx (CONST_INT, VOIDmode, ! 548: (INTVAL (operands[2]))>>16); ! 549: output_asm_insn (\"lui\\t%0,%x2\\t#load higher part (andsi3)\", ! 550: xops); ! 551: xops[2] = gen_rtx (CONST_INT, VOIDmode, ! 552: 0xffff & (INTVAL (operands[2]))); ! 553: output_asm_insn (\"addi%:\\t%0,$0,%x2\\t#load lower part (andsi3)\", ! 554: xops); ! 555: output_asm_insn (\"and\\t%0,%0,%1\\t#andsi3\", xops); ! 556: return \"\"; ! 557: } ! 558: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) ! 559: return \"and\\t%0,%1,$0\\t#andsi3\\t%1,%2 -> %0\"; ! 560: else return \"ERROR op2 not zero \\t#andsi3\\t%1,%2 -> %0\"; ! 561: } ! 562: else ! 563: return \"and\\t%0,%1,%2\\t#andsi3\\t%1,%2 -> %0\"; ! 564: }") ! 565: ! 566: (define_insn "andhi3" ! 567: [(set (match_operand:HI 0 "general_operand" "=r") ! 568: (and:HI (match_operand:HI 1 "general_operand" "%r") ! 569: (match_operand:HI 2 "general_operand" "r")))] ! 570: "" ! 571: "and\\t%0,%1,%2\\t#andhi3 %1,%2 -> %0") ! 572: ! 573: (define_insn "andqi3" ! 574: [(set (match_operand:QI 0 "general_operand" "=r") ! 575: (and:QI (match_operand:QI 1 "general_operand" "%r") ! 576: (match_operand:QI 2 "general_operand" "r")))] ! 577: "" ! 578: "and\\t%0,%1,%2\\t#andqi3 %1,%2 -> %0") ! 579: ! 580: (define_insn "iordi3" ! 581: [(set (match_operand:DI 0 "general_operand" "=r") ! 582: (ior:DI (match_operand:DI 1 "general_operand" "%r") ! 583: (match_operand:DI 2 "general_operand" "r")))] ! 584: "" ! 585: "* ! 586: { ! 587: rtx xops[3]; ! 588: if ((REGNO (operands[0]) != (REGNO (operands[1]) +1)) ! 589: && ! 590: (REGNO (operands[0]) != (REGNO (operands[2]) +1))) ! 591: { ! 592: /* TAKE CARE OF OVERLAPS */ ! 593: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])); ! 594: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 595: xops[2] = gen_rtx (REG, SImode, REGNO (operands[2])); ! 596: output_asm_insn (\"or\\t%0,%1,%2\\t#iordi3 %1,%2 -> %0\", xops); ! 597: xops[0] = gen_rtx (REG, SImode, REGNO (xops[0])+1); ! 598: xops[1] = gen_rtx (REG, SImode, REGNO (xops[1])+1); ! 599: xops[2] = gen_rtx (REG, SImode, REGNO (xops[2])+1); ! 600: output_asm_insn (\"or\\t%0,%1,%2\\t#iordi3 %1,%2 -> %0\", xops); ! 601: } ! 602: else ! 603: abort (); ! 604: return \"\"; ! 605: }") ! 606: ! 607: (define_insn "iorsi3" ! 608: [(set (match_operand:SI 0 "general_operand" "=r") ! 609: (ior:SI (match_operand:SI 1 "general_operand" "%r") ! 610: (match_operand:SI 2 "general_operand" "rIJ")))] ! 611: "" ! 612: "* ! 613: { ! 614: if (GET_CODE (operands[2]) == CONST_INT) ! 615: { ! 616: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I')) ! 617: { ! 618: return \"ori\\t%0,%1,%x2\\t#iorsi3\\t%1,%d2 -> %0\"; ! 619: } ! 620: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) ! 621: return \"or\\t%0,%1,$0\\t#iorsi3\\t%1,%2 -> %0\"; ! 622: else return \"ERROR op2 not zero \\t#iorsi3\\t%1,%2 -> %0\"; ! 623: } ! 624: else ! 625: return \"or\\t%0,%1,%2\\t#iorsi3\\t%1,%2 -> %0\"; ! 626: }") ! 627: ! 628: (define_insn "iorhi3" ! 629: [(set (match_operand:HI 0 "general_operand" "=r") ! 630: (ior:HI (match_operand:HI 1 "general_operand" "%r") ! 631: (match_operand:HI 2 "general_operand" "r")))] ! 632: "" ! 633: "or\\t%0,%1,%2\\t#iorhi3 %1,%2 -> %0") ! 634: ! 635: (define_insn "iorqi3" ! 636: [(set (match_operand:QI 0 "general_operand" "=r") ! 637: (ior:QI (match_operand:QI 1 "general_operand" "%r") ! 638: (match_operand:QI 2 "general_operand" "r")))] ! 639: "" ! 640: "or\\t%0,%1,%2\\t#iorqi3 %1,%2 -> %0") ! 641: ! 642: (define_insn "xordi3" ! 643: [(set (match_operand:DI 0 "general_operand" "=r") ! 644: (xor:DI (match_operand:DI 1 "general_operand" "r") ! 645: (match_operand:DI 2 "general_operand" "r")))] ! 646: "" ! 647: "* ! 648: { ! 649: rtx xops[3]; ! 650: if ((REGNO (operands[0]) != (REGNO (operands[1]) +1)) ! 651: && ! 652: (REGNO (operands[0]) != (REGNO (operands[2]) +1))) ! 653: { ! 654: /* TAKE CARE OF OVERLAPS */ ! 655: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])); ! 656: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 657: xops[2] = gen_rtx (REG, SImode, REGNO (operands[2])); ! 658: output_asm_insn (\"xor\\t%0,%1,%2\\t#xordi3 %1,%2 -> %0\", xops); ! 659: xops[0] = gen_rtx (REG, SImode, REGNO (xops[0])+1); ! 660: xops[1] = gen_rtx (REG, SImode, REGNO (xops[1])+1); ! 661: xops[2] = gen_rtx (REG, SImode, REGNO (xops[2])+1); ! 662: output_asm_insn (\"xor\\t%0,%1,%2\\t#xordi3 %1,%2 -> %0\", xops); ! 663: } ! 664: else ! 665: abort (); ! 666: return \"\"; ! 667: }") ! 668: ! 669: (define_insn "xorsi3" ! 670: [(set (match_operand:SI 0 "general_operand" "=r") ! 671: (xor:SI (match_operand:SI 1 "general_operand" "%r") ! 672: (match_operand:SI 2 "general_operand" "rIJ")))] ! 673: "" ! 674: "* ! 675: { ! 676: if (GET_CODE (operands[2]) == CONST_INT) ! 677: { ! 678: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I')) ! 679: { ! 680: return \"xori\\t%0,%1,%x2\\t#xorsi3\\t%1,%d2 -> %0\"; ! 681: } ! 682: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')) ! 683: return \"xor\\t%0,%1,$0\\t#xorsi3\\t%1,%2 -> %0\"; ! 684: else return \"ERROR op2 not zero \\t#xorsi3\\t%1,%2 -> %0\"; ! 685: } ! 686: else ! 687: return \"xor\\t%0,%1,%2\\t#xorsi3\\t%1,%2 -> %0\"; ! 688: }") ! 689: ! 690: (define_insn "xorhi3" ! 691: [(set (match_operand:HI 0 "general_operand" "=r") ! 692: (xor:HI (match_operand:HI 1 "general_operand" "%r") ! 693: (match_operand:HI 2 "general_operand" "r")))] ! 694: "" ! 695: "xor\\t%0,%1,%2\\t#xorhi3 %1,%2 -> %0") ! 696: ! 697: (define_insn "xorqi3" ! 698: [(set (match_operand:QI 0 "general_operand" "=r") ! 699: (xor:QI (match_operand:QI 1 "general_operand" "%r") ! 700: (match_operand:QI 2 "general_operand" "r")))] ! 701: "" ! 702: "xor\\t%0,%1,%2\\t#xorqi3 %1,%2 -> %0") ! 703: ! 704: ;; ! 705: ;; .................... ! 706: ;; ! 707: ;; TRUNCATION ! 708: ;; ! 709: ;; .................... ! 710: ! 711: ;; Extension and truncation insns. ! 712: ;; Those for integer source operand ! 713: ;; are ordered widest source type first. ! 714: ! 715: ! 716: (define_insn "truncsiqi2" ! 717: [(set (match_operand:QI 0 "general_operand" "=r") ! 718: (truncate:QI (match_operand:SI 1 "general_operand" "r")))] ! 719: "" ! 720: "andi\\t%0,%1,0xff\\t#truncsiqi2\\t %1 -> %0") ! 721: ! 722: (define_insn "truncsihi2" ! 723: [(set (match_operand:HI 0 "general_operand" "=r") ! 724: (truncate:HI (match_operand:SI 1 "general_operand" "r")))] ! 725: "" ! 726: "* ! 727: output_asm_insn (\"sll\\t%0,%1,0x10\\t#truncsihi2\\t %1 -> %0\", ! 728: operands); ! 729: return \"sra\\t%0,%0,0x10\\t#truncsihi2\\t %1 -> %0\"; ! 730: ") ! 731: ! 732: (define_insn "trunchiqi2" ! 733: [(set (match_operand:QI 0 "general_operand" "=r") ! 734: (truncate:QI (match_operand:HI 1 "general_operand" "r")))] ! 735: "" ! 736: "andi\\t%0,%1,0xff\\t#trunchiqi2\\t %1 -> %0") ! 737: ! 738: (define_insn "truncdfsf2" ! 739: [(set (match_operand:SF 0 "general_operand" "=f") ! 740: (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))] ! 741: "" ! 742: "cvt.s.d\\t%0,%1\\t#truncdfsf2\\t %1 -> %0") ! 743: ! 744: ;; ! 745: ;; .................... ! 746: ;; ! 747: ;; ZERO EXTENSION ! 748: ;; ! 749: ;; .................... ! 750: ! 751: ;; Extension insns. ! 752: ;; Those for integer source operand ! 753: ;; are ordered widest source type first. ! 754: ! 755: ! 756: ! 757: (define_insn "zero_extendhisi2" ! 758: [(set (match_operand:SI 0 "general_operand" "=r,r") ! 759: (zero_extend:SI (match_operand:HI 1 "general_operand" "r,m")))] ! 760: "" ! 761: "* ! 762: { ! 763: if (which_alternative == 0) ! 764: { ! 765: output_asm_insn (\"sll\\t%0,%1,0x10\\t#zero_extendhisi2\\t %1 -> %0\", ! 766: operands); ! 767: return \"srl\\t%0,%0,0x10\\t#zero_extendhisi2\\t %1 -> %0\"; ! 768: } ! 769: else ! 770: return \"lhu\\t%0,%1\\t#zero extendhisi2 %1 -> %0\"; ! 771: }") ! 772: ! 773: (define_insn "zero_extendqihi2" ! 774: [(set (match_operand:HI 0 "general_operand" "=r") ! 775: (zero_extend:HI (match_operand:QI 1 "general_operand" "r")))] ! 776: "" ! 777: "* ! 778: output_asm_insn (\"sll\\t%0,%1,0x18\\t#zero_extendqihi2\\t %1 -> %0\", ! 779: operands); ! 780: return \"srl\\t%0,%0,0x18\\t#zero_extendqihi2\\t %1 -> %0\"; ! 781: ") ! 782: ! 783: ! 784: (define_insn "zero_extendqisi2" ! 785: [(set (match_operand:SI 0 "general_operand" "=r,r") ! 786: (zero_extend:SI (match_operand:QI 1 "general_operand" "r,m")))] ! 787: "" ! 788: "* ! 789: { ! 790: if (which_alternative == 0) ! 791: { ! 792: return \"andi\\t%0,%1,0xff\\t#zero_extendqisi2\\t %1 -> %0\"; ! 793: } ! 794: else ! 795: return \"lbu\\t%0,%1\\t#zero extendqisi2 %1 -> %0\"; ! 796: }") ! 797: ! 798: ! 799: ;; ! 800: ;; .................... ! 801: ;; ! 802: ;; SIGN EXTENSION ! 803: ;; ! 804: ;; .................... ! 805: ! 806: ;; Extension insns. ! 807: ;; Those for integer source operand ! 808: ;; are ordered widest source type first. ! 809: ! 810: ! 811: ! 812: (define_insn "extendhisi2" ! 813: [(set (match_operand:SI 0 "general_operand" "=r,r") ! 814: (sign_extend:SI (match_operand:HI 1 "general_operand" "r,m")))] ! 815: "" ! 816: "* ! 817: { ! 818: if (which_alternative == 0) ! 819: { ! 820: output_asm_insn (\"sll\\t%0,%1,0x10\\t#sign extendhisi2\\t %1 -> %0\", ! 821: operands); ! 822: return \"sra\\t%0,%0,0x10\\t#sign extendhisi2\\t %1 -> %0\"; ! 823: } ! 824: else ! 825: return \"lh\\t%0,%1\\t#sign extendhisi2 %1 -> %0\"; ! 826: }") ! 827: ! 828: (define_insn "extendqihi2" ! 829: [(set (match_operand:HI 0 "general_operand" "=r") ! 830: (sign_extend:HI (match_operand:QI 1 "general_operand" "r")))] ! 831: "" ! 832: "* ! 833: output_asm_insn (\"sll\\t%0,%1,0x18\\t#sign extendqihi2\\t %1 -> %0\", ! 834: operands); ! 835: return \"sra\\t%0,%0,0x18\\t#sign extendqihi2\\t %1 -> %0\"; ! 836: ") ! 837: ! 838: ! 839: (define_insn "extendqisi2" ! 840: [(set (match_operand:SI 0 "general_operand" "=r,r") ! 841: (sign_extend:SI (match_operand:QI 1 "general_operand" "r,m")))] ! 842: "" ! 843: "* ! 844: { ! 845: if (which_alternative == 0) ! 846: { ! 847: output_asm_insn (\"sll\\t%0,%1,0x18\\t#sign extendqisi2\\t %1 -> %0\", ! 848: operands); ! 849: return \"sra\\t%0,%0,0x18\\t#sign extendqisi2\\t %1 -> %0\"; ! 850: } ! 851: else ! 852: return \"lb\\t%0,%1\\t#sign extendqisi2 %1 -> %0\"; ! 853: }") ! 854: ! 855: ! 856: (define_insn "extendsfdf2" ! 857: [(set (match_operand:DF 0 "general_operand" "=f") ! 858: (float_extend:DF (match_operand:SF 1 "general_operand" "f")))] ! 859: "" ! 860: "cvt.d.s\\t%0,%1\\t#extendsfdf2\\t %1 -> %0") ! 861: ! 862: ! 863: ;; ! 864: ;; .................... ! 865: ;; ! 866: ;; CONVERSIONS ! 867: ;; ! 868: ;; .................... ! 869: ! 870: ! 871: (define_insn "fix_truncdfsi2" ! 872: [(set (match_operand:SI 0 "general_operand" "=r") ! 873: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "f")))) ! 874: (clobber (reg:DF 44))] ! 875: "" ! 876: "trunc.w.d\\t$f12,%1,%0\\t#fix_truncdfsi2\\t%1 -> %0\;mfc1\\t%0,$f12\\t#fix_truncdfsi2\\t%1 -> %0") ! 877: ! 878: ! 879: (define_insn "fix_truncsfsi2" ! 880: [(set (match_operand:SI 0 "general_operand" "=r") ! 881: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "f")))) ! 882: (clobber (reg:DF 44))] ! 883: "" ! 884: "trunc.w.s\\t$f12,%1,%0\\t#fix_truncsfsi2\\t%1 -> %0\;mfc1\\t%0,$f12\\t#fix_truncsfsi2\\t%1 -> %0") ! 885: ! 886: (define_insn "floatsidf2" ! 887: [(set (match_operand:DF 0 "general_operand" "=f") ! 888: (float:DF (match_operand:SI 1 "general_operand" "r")))] ! 889: "" ! 890: "mtc1\\t%1,%0\\t#floatsidf2\\t%1 -> %0\;cvt.d.w\\t%0,%0\\t#floatsidf2\\t%1 -> %0") ! 891: ! 892: ! 893: (define_insn "floatsisf2" ! 894: [(set (match_operand:SF 0 "general_operand" "=f") ! 895: (float:SF (match_operand:SI 1 "general_operand" "r")))] ! 896: "" ! 897: "mtc1\\t%1,%0\\t#floatsisf2\\t%1 -> %0\;cvt.s.w\\t%0,%0\\t#floatsisf2\\t%1 -> %0") ! 898: ! 899: ;;- Wild things used when ! 900: ;;- unions make double and int ! 901: ;;- overlap. ! 902: ;;- ! 903: ;;- This must be supported ! 904: ;;- since corresponding code ! 905: ;;- gets generated ! 906: ! 907: (define_insn "" ! 908: [(set (subreg:DF (match_operand:DI 0 "register_operand" "=ry") 0) ! 909: (match_operand:DF 1 "register_operand" "rf")) ! 910: (clobber (match_operand 2 "register_operand" "rf"))] ! 911: "" ! 912: "* ! 913: { ! 914: rtx xops[2]; ! 915: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])); ! 916: #ifndef DECSTATION ! 917: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])+1); ! 918: #else ! 919: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])); ! 920: #endif ! 921: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> (subreg:DF %0 0) \\t likely Union\" ! 922: , xops); ! 923: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])+1); ! 924: #ifndef DECSTATION ! 925: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])); ! 926: #else ! 927: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])+1); ! 928: #endif ! 929: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> (subreg:DF %0 0) \" ! 930: , xops); ! 931: return (\"\"); ! 932: }") ! 933: ! 934: ! 935: ! 936: (define_insn "" ! 937: [(set (subreg:DF (match_operand:DI 0 "register_operand" "=ry") 0) ! 938: (match_operand:DF 1 "register_operand" "rf"))] ! 939: "" ! 940: "* ! 941: { ! 942: rtx xops[2]; ! 943: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])); ! 944: #ifndef DECSTATION ! 945: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])+1); ! 946: #else ! 947: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])); ! 948: #endif ! 949: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> (subreg:DF %0 0) \\t likely Union\" ! 950: , xops); ! 951: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])+1); ! 952: #ifndef DECSTATION ! 953: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])); ! 954: #else ! 955: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])+1); ! 956: #endif ! 957: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> (subreg:DF %0 0) \" ! 958: ,xops); ! 959: return (\"\"); ! 960: }") ! 961: ! 962: ! 963: ! 964: (define_insn "" ! 965: [(set (match_operand:DF 0 "register_operand" "=rf") ! 966: (subreg:DF (match_operand:DI 1 "register_operand" "ry") 0)) ! 967: (clobber (match_operand 2 "register_operand" "rf"))] ! 968: "" ! 969: "* ! 970: { ! 971: rtx xops[2]; ! 972: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0])); ! 973: #ifndef DECSTATION ! 974: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1); ! 975: #else ! 976: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 977: #endif ! 978: output_asm_insn (\"mtc1\\t%1,%0\\t# (subreg:DF %1) -> %0 \\t\" ! 979: , xops); ! 980: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0])+1); ! 981: #ifndef DECSTATION ! 982: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 983: #else ! 984: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1); ! 985: #endif ! 986: output_asm_insn (\"mtc1\\t%1,%0\\t# (subreg:DF %1) -> %0 \\t\" ! 987: , xops); ! 988: return (\"\"); ! 989: }") ! 990: ! 991: ! 992: ! 993: (define_insn "" ! 994: [(set (match_operand:DF 0 "register_operand" "=rf") ! 995: (subreg:DF (match_operand:DI 1 "register_operand" "ry") 0))] ! 996: "" ! 997: "* ! 998: { ! 999: rtx xops[2]; ! 1000: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0])); ! 1001: #ifndef DECSTATION ! 1002: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1); ! 1003: #else ! 1004: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 1005: #endif ! 1006: output_asm_insn (\"mtc1\\t%1,%0\\t# (subreg:DF %1) -> %0 \\t\" ! 1007: , xops); ! 1008: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0])+1); ! 1009: #ifndef DECSTATION ! 1010: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 1011: #else ! 1012: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1); ! 1013: #endif ! 1014: output_asm_insn (\"mtc1\\t%1,%0\\t# (subreg:DF %1) -> %0 \\t\" ! 1015: , xops); ! 1016: ! 1017: return (\"\"); ! 1018: }") ! 1019: ! 1020: ;; ! 1021: ;; .................... ! 1022: ;; ! 1023: ;; MOVES ! 1024: ;; ! 1025: ;; and ! 1026: ;; ! 1027: ;; LOADS AND STORES ! 1028: ;; ! 1029: ;; .................... ! 1030: ! 1031: (define_insn "movdi" ! 1032: [(set (match_operand:DI 0 "general_operand" "=r,*r,*m") ! 1033: (match_operand:DI 1 "general_operand" "r,*miF,*r"))] ! 1034: "" ! 1035: "* ! 1036: { ! 1037: extern rtx change_address (); ! 1038: extern rtx plus_constant (); ! 1039: ! 1040: if (which_alternative == 0) ! 1041: { ! 1042: rtx xops[2]; ! 1043: if (REGNO (operands[0]) != (REGNO (operands[1]) +1)) ! 1044: { ! 1045: /* TAKE CARE OF OVERLAPS */ ! 1046: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])); ! 1047: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 1048: output_asm_insn (\"add%:\\t%0,$0,%1\\t#movdi %1 -> %0\", xops); ! 1049: xops[0] = gen_rtx (REG, SImode, REGNO (xops[0])+1); ! 1050: xops[1] = gen_rtx (REG, SImode, REGNO (xops[1])+1); ! 1051: output_asm_insn (\"add%:\\t%0,$0,%1\\t#movdi %1 -> %0\", xops); ! 1052: } ! 1053: else ! 1054: { ! 1055: /* TAKE CARE OF OVERLAPS */ ! 1056: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])+1); ! 1057: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1); ! 1058: output_asm_insn (\"add%:\\t%0,$0,%1\\t#movdi %1 -> %0\", xops); ! 1059: xops[0] = gen_rtx (REG, SImode, REGNO (xops[0])-1); ! 1060: xops[1] = gen_rtx (REG, SImode, REGNO (xops[1])-1); ! 1061: output_asm_insn (\"add%:\\t%0,$0,%1\\t#movdi %1 -> %0\", xops); ! 1062: } ! 1063: return \"\"; ! 1064: } ! 1065: else if (which_alternative == 1) ! 1066: { ! 1067: /* No overlap here */ ! 1068: rtx xops[2]; ! 1069: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])); ! 1070: if (GET_CODE (operands[1]) == MEM) ! 1071: { ! 1072: xops[1] = gen_rtx (MEM, SImode, XEXP (operands[1], 0)); ! 1073: output_asm_insn (\"lw\\t%0,%1\\t#movdi %1 (mem) -> %0\", xops); ! 1074: } ! 1075: else if (CONSTANT_P (operands[1])) ! 1076: { ! 1077: #ifdef WORDS_BIG_ENDIAN ! 1078: xops[1] = const0_rtx; ! 1079: #else ! 1080: xops[1] = operands[1]; ! 1081: #endif ! 1082: output_load_immediate (xops); ! 1083: } ! 1084: else if (GET_CODE (operands[1]) == CONST_DOUBLE) ! 1085: { ! 1086: xops[1] = gen_rtx (CONST_INT, VOIDmode, ! 1087: CONST_DOUBLE_LOW (operands[1])); ! 1088: output_load_immediate (xops); ! 1089: } ! 1090: else ! 1091: abort (); ! 1092: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])+1); ! 1093: if (offsettable_memref_p (operands[1])) ! 1094: { ! 1095: xops[1] = adj_offsettable_operand (gen_rtx (MEM, SImode, ! 1096: XEXP (operands[1], 0)), ! 1097: 4); ! 1098: output_asm_insn (\"lw\\t%0,%1\\t#movdi %1(mem) -> %0\", xops); ! 1099: } ! 1100: else if (GET_CODE (operands[1]) == MEM) ! 1101: { ! 1102: abort (); ! 1103: output_asm_insn (\"lw\\t%0,%1\\t#movdi %1(mem) -> %0\", xops); ! 1104: } ! 1105: else if (CONSTANT_P (operands[1])) ! 1106: { ! 1107: #ifdef WORDS_BIG_ENDIAN ! 1108: xops[1] = operands[1]; ! 1109: #else ! 1110: xops[1] = const0_rtx; ! 1111: #endif ! 1112: output_load_immediate (xops); ! 1113: } ! 1114: else if (GET_CODE (operands[1]) == CONST_DOUBLE) ! 1115: { ! 1116: xops[1] = gen_rtx (CONST_INT, VOIDmode, ! 1117: CONST_DOUBLE_HIGH (operands[1])); ! 1118: output_load_immediate (xops); ! 1119: } ! 1120: else abort (); ! 1121: return \"\"; ! 1122: } ! 1123: else ! 1124: { ! 1125: /* No overlap here */ ! 1126: rtx xops[2]; ! 1127: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 1128: if (GET_CODE (operands[0]) == MEM) ! 1129: xops[0] = gen_rtx (MEM, SImode, XEXP (operands[0], 0)); ! 1130: else abort (); ! 1131: output_asm_insn (\"sw\\t%1,%0\\t#movdi %1 -> %0(mem)\", xops); ! 1132: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1); ! 1133: if (offsettable_memref_p (operands[0])) ! 1134: { ! 1135: xops[0] = adj_offsettable_operand (gen_rtx (MEM, SImode, ! 1136: XEXP (operands[0], 0)), ! 1137: 4); ! 1138: output_asm_insn (\"sw\\t%1,%0\\t#movdi %1 -> %0 (mem)\", xops); ! 1139: } ! 1140: else if (GET_CODE (operands[0]) == MEM) ! 1141: { ! 1142: abort (); ! 1143: output_asm_insn (\"sw\\t%1,%0\\t#movdi %1(mem) -> %0\", xops); ! 1144: } ! 1145: else abort (); ! 1146: return \"\"; ! 1147: } ! 1148: }") ! 1149: ! 1150: (define_insn "movsi" ! 1151: [(set (match_operand:SI 0 "general_operand" "=r,r,m,r,r,m,*r") ! 1152: (match_operand:SI 1 "general_operand" "r,m,r,i,J,J,*p"))] ! 1153: "" ! 1154: "* ! 1155: { ! 1156: if (which_alternative >= 4) ! 1157: { ! 1158: if (which_alternative == 4) ! 1159: return \"add%:\\t%0,$0,$0\\t#movsi\\t%1 == 0 -> %0\"; ! 1160: else if (which_alternative == 5) ! 1161: return \"sw\\t$0,%0\\t#movsi\\t%1 == 0 -> %0\"; ! 1162: else if (which_alternative == 6) ! 1163: { ! 1164: rtx xops[4]; ! 1165: register rtx addr; ! 1166: xops[0] = operands[0]; ! 1167: addr = operands[1]; ! 1168: if ((GET_CODE (addr) == PLUS) ! 1169: && (GET_CODE (XEXP (addr, 0)) == REG)) ! 1170: { ! 1171: xops[1] = XEXP (addr, 0); ! 1172: xops[2] = XEXP (addr, 1); ! 1173: xops[3] = addr; ! 1174: output_asm_insn (\"addiu\\t%0,%1,%2\\t#movsi (*p)\\t%a3 -> %0\", xops); ! 1175: return \"\"; ! 1176: } ! 1177: else abort (); ! 1178: } ! 1179: } ! 1180: else if ((GET_CODE (operands[0]) == REG) && (GET_CODE (operands[1]) == REG)) ! 1181: return \"add%:\\t%0,$0,%1\\t#movsi\\t%1 -> %0 \"; ! 1182: else if (GET_CODE (operands[0]) == REG ! 1183: && ! 1184: GET_CODE (operands[1]) == CONST_INT) ! 1185: { ! 1186: output_load_immediate (operands); ! 1187: return \"\"; ! 1188: } ! 1189: else if (GET_CODE (operands[0]) == REG) ! 1190: { ! 1191: if (GET_CODE (operands[1]) == SYMBOL_REF ! 1192: || GET_CODE (operands[1]) == LABEL_REF) ! 1193: return \"la\\t%0,%a1\\t#movsi %a1 -> %0\"; ! 1194: else if (GET_CODE (operands[1]) == CONST) ! 1195: return \"la\\t%0,%a1\\t#movsi %a1(AExp) -> %0\"; ! 1196: else ! 1197: return \"lw\\t%0,%1\\t#movsi %1 -> %0\"; ! 1198: } ! 1199: else ! 1200: return \"sw\\t%1,%0\\t#movsi %1 -> %0\"; ! 1201: }") ! 1202: ! 1203: (define_insn "" ! 1204: [(set (match_operand:SI 0 "register_operand" "=*r") ! 1205: (match_operand:SI 1 "address_operand" "*p"))] ! 1206: "FIXED_FRAME_PTR_REL_P (operands[1])" ! 1207: "* ! 1208: { ! 1209: rtx xops[4]; ! 1210: register rtx addr; ! 1211: xops[0] = operands[0]; ! 1212: addr = operands[1]; ! 1213: if (GET_CODE (addr) == PLUS ! 1214: && GET_CODE (XEXP (addr, 0)) == REG) ! 1215: { ! 1216: xops[1] = XEXP (addr, 0); ! 1217: xops[2] = XEXP (addr, 1); ! 1218: xops[3] = addr; ! 1219: output_asm_insn (\"addiu\\t%0,%1,%2\\t#movsi (*p)\\t%a3 -> %0\", xops); ! 1220: return \"\"; ! 1221: } ! 1222: else ! 1223: abort (); ! 1224: }") ! 1225: ! 1226: (define_insn "movhi" ! 1227: [(set (match_operand:HI 0 "general_operand" "=r,r,m,r,r,m") ! 1228: (match_operand:HI 1 "general_operand" "r,m,r,i,J,J"))] ! 1229: "" ! 1230: "* ! 1231: { ! 1232: if (which_alternative == 4) ! 1233: return \"add%:\\t%0,$0,$0\\t#movhi\\t%1 == 0 -> %0\"; ! 1234: else if (which_alternative == 5) ! 1235: return \"sh\\t$0,%0\\t#movhi\\t%1 == 0 -> %0\"; ! 1236: else if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG) ! 1237: return \"add%:\\t%0,$0,%1\\t#move.h %1 -> %0 \"; ! 1238: else if (GET_CODE (operands[0]) == REG ! 1239: && GET_CODE (operands[1]) == CONST_INT) ! 1240: return \"addi%:\\t%0,$0,%x1\\t# movhi %1 -> %0\"; ! 1241: else if (GET_CODE (operands[0]) == REG) ! 1242: return \"lh\\t%0,%1\\t#movhi %1 -> %0\"; ! 1243: else ! 1244: return \"sh\\t%1,%0\\t#movhi %1 -> %0\"; ! 1245: }") ! 1246: ! 1247: (define_insn "movqi" ! 1248: [(set (match_operand:QI 0 "general_operand" "=r,r,m,r,r,m") ! 1249: (match_operand:QI 1 "general_operand" "r,m,r,i,J,J"))] ! 1250: "" ! 1251: "* ! 1252: { ! 1253: if (which_alternative == 4) ! 1254: return \"add%:\\t%0,$0,$0\\t#movqi\\t%1 == 0 -> %0\"; ! 1255: else if (which_alternative == 5) ! 1256: return \"sb\\t$0,%0\\t#movqi\\t%1 == 0 -> %0\"; ! 1257: else if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG) ! 1258: return \"add%:\\t%0,$0,%1\\t#move.b %1 -> %0 \"; ! 1259: ! 1260: if ((GET_CODE (operands[0]) == REG ) ! 1261: && ! 1262: (GET_CODE (operands[1]) == CONST_INT)) ! 1263: return \"addi%:\\t%0,$0,%x1\\t# movqi %1 -> %0\"; ! 1264: ! 1265: /* Should say that I am not padding high order ! 1266: ** bits correctly ! 1267: */ ! 1268: else if (GET_CODE (operands[0]) == REG) ! 1269: return \"lb\\t%0,%1\\t#movqi %1 -> %0\"; ! 1270: else ! 1271: return \"sb\\t%1,%0\\t#movqi %1 -> %0\"; ! 1272: }") ! 1273: ! 1274: (define_insn "movsf" ! 1275: [(set (match_operand:SF 0 "general_operand" "=f,f,m,f") ! 1276: (match_operand:SF 1 "general_operand" "f,m,f,F")) ! 1277: (clobber (reg:SI 24))] ! 1278: "" ! 1279: "* ! 1280: { ! 1281: if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG) ! 1282: return \"mov.s %0,%1\\t#movsf %1 -> %0 \"; ! 1283: ! 1284: if (GET_CODE (operands[0]) == REG ! 1285: && GET_CODE (operands[1]) == CONST_DOUBLE) ! 1286: { ! 1287: rtx xops[3]; ! 1288: xops[0] = operands[0]; ! 1289: xops[1] = gen_rtx (CONST_INT, VOIDmode, ! 1290: (XINT (operands[1], 0))>>16); ! 1291: xops[2] = gen_rtx (CONST_INT, VOIDmode, ! 1292: XINT (operands[1], 0)); ! 1293: output_asm_insn (\"lui\\t$24,%x1\\t#move high part of %2\", xops); ! 1294: xops[1] = gen_rtx (CONST_INT, VOIDmode, ! 1295: (XINT (operands[1], 0)) & 0xff); ! 1296: output_asm_insn (\"ori\\t$24,%x1\\t#move low part of %2\", xops); ! 1297: output_asm_insn (\"mtc1\\t$24,%0\", xops); ! 1298: ! 1299: xops[0] = gen_rtx (REG, SFmode, REGNO (xops[0])+1); ! 1300: xops[1] = gen_rtx (CONST_INT, VOIDmode, ! 1301: (XINT (operands[1], 1))>>16); ! 1302: xops[2] = gen_rtx (CONST_INT, VOIDmode, ! 1303: XINT (operands[1], 1)); ! 1304: output_asm_insn (\"lui\\t$24,%x1\\t#move high part of %2\", xops); ! 1305: xops[1] = gen_rtx (CONST_INT, VOIDmode, ! 1306: (XINT (operands[1], 1)) & 0xff); ! 1307: output_asm_insn (\"ori\\t$24,%x1\\t#move low part of %2\", xops); ! 1308: ! 1309: output_asm_insn (\"mtc1\\t$24,%0\", xops); ! 1310: return \"cvt.s.d\\t %0,%0 \"; ! 1311: } ! 1312: /* Should say that I am not padding high order ! 1313: ** bits correctly ! 1314: */ ! 1315: else if (GET_CODE (operands[0]) == REG) ! 1316: return \"l.s\\t %0,%1\\t#movsf %1 -> %0\"; ! 1317: else ! 1318: return \"s.s\\t %1,%0\\t#movsf %1 -> %0\"; ! 1319: }") ! 1320: ! 1321: ;; --- ! 1322: ! 1323: (define_insn "movdf" ! 1324: [(set (match_operand:DF 0 "general_operand" "=f,f,m,f,*f,*y") ! 1325: (match_operand:DF 1 "general_operand" "f,m,f,F,*y,*f")) ! 1326: (clobber (reg:SI 24))] ! 1327: "" ! 1328: "* ! 1329: { ! 1330: if (which_alternative > 3) ! 1331: { ! 1332: rtx xops[2]; ! 1333: ! 1334: if (REGNO (operands[1]) == 6) ! 1335: { ! 1336: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0])); ! 1337: #ifndef DECSTATION ! 1338: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1); ! 1339: #else ! 1340: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 1341: #endif ! 1342: output_asm_insn (\"mtc1\\t%1,%0\\t# %1 -> %0 \\tcalling sequence trick\" ! 1343: , xops); ! 1344: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0])+1); ! 1345: #ifndef DECSTATION ! 1346: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 1347: #else ! 1348: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1); ! 1349: #endif ! 1350: output_asm_insn (\"mtc1\\t%1,%0\\t# %1 -> %0 \\tcalling sequence trick\" ! 1351: , xops); ! 1352: return (\"\"); ! 1353: } ! 1354: else if (REGNO (operands[0]) == 6) ! 1355: { ! 1356: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])); ! 1357: #ifndef DECSTATION ! 1358: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])+1); ! 1359: #else ! 1360: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 1361: #endif ! 1362: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> %0 \\tcalling sequence trick\" ! 1363: , xops); ! 1364: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])+1); ! 1365: #ifndef DECSTATION ! 1366: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])); ! 1367: #else ! 1368: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1); ! 1369: #endif ! 1370: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> %0 \\tcalling sequence trick\" ! 1371: , xops); ! 1372: return (\"\"); ! 1373: } ! 1374: else ! 1375: abort_with_insn (insn, ! 1376: \"Matched *y constraint and register number wrong\"); ! 1377: } ! 1378: else ! 1379: { ! 1380: if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG) ! 1381: return \"mov.d\\t%0,%1\\t#movdf %1 -> %0 \"; ! 1382: ! 1383: if (GET_CODE (operands[0]) == REG ! 1384: && GET_CODE (operands[1]) == CONST_DOUBLE) ! 1385: { ! 1386: rtx xops[3]; ! 1387: xops[0] = operands[0]; ! 1388: xops[1] = gen_rtx (CONST_INT, VOIDmode, ! 1389: (XINT (operands[1], 0))>>16); ! 1390: xops[2] = gen_rtx (CONST_INT, VOIDmode, ! 1391: XINT (operands[1], 0)); ! 1392: output_asm_insn (\"lui\\t$24,%x1\\t#move high part of %2\", xops); ! 1393: xops[1] = gen_rtx (CONST_INT, VOIDmode, ! 1394: (XINT (operands[1], 0)) & 0xff); ! 1395: output_asm_insn (\"ori\\t$24,%x1\\t#move low part of %2\", xops); ! 1396: output_asm_insn (\"mtc1\\t%0,$24\", xops); ! 1397: ! 1398: xops[0] = gen_rtx (REG, SFmode, REGNO (xops[0])+1); ! 1399: xops[1] = gen_rtx (CONST_INT, VOIDmode, ! 1400: (XINT (operands[1], 1))>>16); ! 1401: xops[2] = gen_rtx (CONST_INT, VOIDmode, ! 1402: XINT (operands[1], 1)); ! 1403: output_asm_insn (\"lui\\t$24,%x1\\t#move high part of %2\", xops); ! 1404: xops[1] = gen_rtx (CONST_INT, VOIDmode, ! 1405: (XINT (operands[1], 1)) & 0xff); ! 1406: output_asm_insn (\"ori\\t$24,%x1\\t#move low part of %2\", xops); ! 1407: ! 1408: output_asm_insn (\"mtc1\\t%0,$24\", xops); ! 1409: return \"# \"; ! 1410: ! 1411: } ! 1412: else if (GET_CODE (operands[0]) == REG) ! 1413: return \"l.d\\t %0,%1\\t#movdf %1 -> %0\"; ! 1414: else ! 1415: return \"s.d\\t %1,%0\\t#movdf %1 -> %0\"; ! 1416: } ! 1417: }") ! 1418: ! 1419: (define_insn "" ! 1420: [(set (match_operand:SF 0 "general_operand" "=f,f,m") ! 1421: (match_operand:SF 1 "general_operand" "f,m,f"))] ! 1422: "" ! 1423: "* ! 1424: { ! 1425: if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG) ! 1426: return \"mov.s %0,%1\\t#movsf %1 -> %0 \"; ! 1427: ! 1428: if (GET_CODE (operands[0]) == REG) ! 1429: return \"l.s\\t %0,%1\\t#movsf %1 -> %0\"; ! 1430: else ! 1431: return \"s.s\\t %1,%0\\t#movsf %1 -> %0\"; ! 1432: }") ! 1433: ! 1434: ;; --- ! 1435: ! 1436: (define_insn "" ! 1437: [(set (match_operand:DF 0 "general_operand" "=f,f,m,*f,*y") ! 1438: (match_operand:DF 1 "general_operand" "f,m,f,*y,*f"))] ! 1439: "" ! 1440: "* ! 1441: { ! 1442: if (which_alternative > 2) ! 1443: { ! 1444: rtx xops[2]; ! 1445: if (REGNO (operands[1]) == 6) ! 1446: { ! 1447: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0])); ! 1448: #ifndef DECSTATION ! 1449: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1); ! 1450: #else ! 1451: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 1452: #endif ! 1453: output_asm_insn (\"mtc1\\t%1,%0\\t# %1 -> %0 \\tcalling sequence trick\" ! 1454: , xops); ! 1455: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0])+1); ! 1456: #ifndef DECSTATION ! 1457: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 1458: #else ! 1459: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1); ! 1460: #endif ! 1461: output_asm_insn (\"mtc1\\t%1,%0\\t# %1 -> %0 \\tcalling sequence trick\" ! 1462: , xops); ! 1463: return (\"\"); ! 1464: } ! 1465: else if (REGNO (operands[0]) == 6) ! 1466: { ! 1467: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])); ! 1468: #ifndef DECSTATION ! 1469: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])+1); ! 1470: #else ! 1471: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])); ! 1472: #endif ! 1473: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> %0 \\tcalling sequence trick\" ! 1474: , xops); ! 1475: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])+1); ! 1476: #ifndef DECSTATION ! 1477: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])); ! 1478: #else ! 1479: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1); ! 1480: #endif ! 1481: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> %0 \\tcalling sequence trick\" ! 1482: , xops); ! 1483: return (\"\"); ! 1484: } ! 1485: else ! 1486: abort_with_insn (insn, ! 1487: \"Matched *y constraint and register number wrong\"); ! 1488: } ! 1489: else ! 1490: { ! 1491: if ((GET_CODE (operands[0]) == REG) && (GET_CODE (operands[1]) == REG)) ! 1492: return \"mov.d\\t%0,%1\\t#movdf %1 -> %0 \"; ! 1493: ! 1494: if (GET_CODE (operands[0]) == REG) ! 1495: return \"l.d\\t %0,%1\\t#movdf %1 -> %0\"; ! 1496: else ! 1497: return \"s.d\\t %1,%0\\t#movdf %1 -> %0\"; ! 1498: } ! 1499: }") ! 1500: ! 1501: (define_insn "" ! 1502: [(set (match_operand:SI 0 "general_operand" "=r") ! 1503: (match_operand:QI 1 "general_operand" "r"))] ! 1504: "" ! 1505: "andi\\t%0,%1,0xff\\t#Wild zero_extendqisi2\\t %1 -> %0") ! 1506: ! 1507: ! 1508: ! 1509: ! 1510: ;; ! 1511: ;; .................... ! 1512: ;; ! 1513: ;; OTHER ARITHMETIC AND SHIFT ! 1514: ;; ! 1515: ;; .................... ! 1516: ! 1517: (define_insn "ashlqi3" ! 1518: [(set (match_operand:QI 0 "general_operand" "=r") ! 1519: (ashift:QI (match_operand:QI 1 "general_operand" "r") ! 1520: (match_operand:SI 2 "arith32_operand" "ri")))] ! 1521: "" ! 1522: "* ! 1523: { ! 1524: if (GET_CODE (operands[2]) == CONST_INT) ! 1525: { ! 1526: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f); ! 1527: output_asm_insn (\"sll\\t%0,%1,%2\\t#ashlqi3\\t (%1<<%2) -> %0\", operands); ! 1528: } ! 1529: else ! 1530: output_asm_insn (\"sll\\t%0,%1,%2\\t#ashlqi3\\t (%1<<%2) -> %0 (asm syntax)\", ! 1531: operands); ! 1532: return \"andi\\t%0,%0,0xff\\t#ashlqi3\"; ! 1533: }") ! 1534: ! 1535: ! 1536: ! 1537: (define_insn "ashlhi3" ! 1538: [(set (match_operand:HI 0 "general_operand" "=r") ! 1539: (ashift:HI (match_operand:HI 1 "general_operand" "r") ! 1540: (match_operand:SI 2 "arith32_operand" "ri")))] ! 1541: "" ! 1542: "* ! 1543: { ! 1544: if (GET_CODE (operands[2]) == CONST_INT) ! 1545: { ! 1546: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f); ! 1547: output_asm_insn (\"sll\\t%0,%1,%2\\t#ashlhi3\\t (%1<<%2) -> %0\", ! 1548: operands); ! 1549: } ! 1550: else ! 1551: output_asm_insn (\"sll\\t%0,%1,%2\\t#ashlhi3\\t (%1<<%2) -> %0 (asm syntax)\", ! 1552: operands); ! 1553: return \"sll\\t%0,%0,0x10\;sra\\t%0,%0,0x10\\t#ashlhi3\"; ! 1554: }") ! 1555: ! 1556: ! 1557: ! 1558: (define_insn "ashlsi3" ! 1559: [(set (match_operand:SI 0 "general_operand" "=r") ! 1560: (ashift:SI (match_operand:SI 1 "general_operand" "r") ! 1561: (match_operand:SI 2 "arith32_operand" "ri")))] ! 1562: "" ! 1563: "* ! 1564: { ! 1565: if (GET_CODE (operands[2]) == CONST_INT) ! 1566: { ! 1567: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f); ! 1568: return \"sll\\t%0,%1,%2\\t#ashlsi3\\t (%1<<%2) -> %0\"; ! 1569: } ! 1570: return \"sll\\t%0,%1,%2\\t#ashlsi3\\t (%1<<%2) -> %0 (asm syntax)\"; ! 1571: }") ! 1572: ! 1573: ! 1574: ! 1575: (define_insn "ashrsi3" ! 1576: [(set (match_operand:SI 0 "general_operand" "=r") ! 1577: (ashiftrt:SI (match_operand:SI 1 "general_operand" "r") ! 1578: (match_operand:SI 2 "arith32_operand" "ri")))] ! 1579: "" ! 1580: "* ! 1581: { ! 1582: if (GET_CODE (operands[2]) == CONST_INT) ! 1583: { ! 1584: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f); ! 1585: return \"sra\\t%0,%1,%2\\t#ashrsi3\\t (%1>>%2) -> %0\"; ! 1586: } ! 1587: return \"sra\\t%0,%1,%2\\t#ashrsi3\\t (%1>>%2) -> %0 (asm syntax for srav)\"; ! 1588: }") ! 1589: ! 1590: ! 1591: ! 1592: (define_insn "lshrsi3" ! 1593: [(set (match_operand:SI 0 "general_operand" "=r") ! 1594: (lshiftrt:SI (match_operand:SI 1 "general_operand" "r") ! 1595: (match_operand:SI 2 "arith32_operand" "rn")))] ! 1596: "" ! 1597: "* ! 1598: { ! 1599: if (GET_CODE (operands[2]) == CONST_INT) ! 1600: { ! 1601: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f); ! 1602: return \"srl\\t%0,%1,%2\\t#lshrsi3\\t (%1>>%2) -> %0\"; ! 1603: } ! 1604: return \"srl\\t%0,%1,%2\\t#lshrsi3\\t (%1>>%2) -> %0 (asm syntax)\"; ! 1605: }") ! 1606: ! 1607: ! 1608: ! 1609: ! 1610: (define_insn "negsi2" ! 1611: [(set (match_operand:SI 0 "general_operand" "=r") ! 1612: (neg:SI (match_operand:SI 1 "arith_operand" "r")))] ! 1613: "" ! 1614: "sub%:\\t%0,$0,%1\\t#negsi2") ! 1615: ! 1616: ! 1617: (define_insn "negdf2" ! 1618: [(set (match_operand:DF 0 "general_operand" "=f") ! 1619: (neg:DF (match_operand:DF 1 "general_operand" "f")))] ! 1620: "" ! 1621: "neg.d\\t%0,%1\\t#negdf2") ! 1622: ! 1623: ! 1624: ! 1625: (define_insn "negsf2" ! 1626: ! 1627: [(set (match_operand:SF 0 "general_operand" "=f") ! 1628: (neg:SF (match_operand:SF 1 "general_operand" "f")))] ! 1629: "" ! 1630: "neg.s\\t%0,%1\\t#negsf2") ! 1631: ! 1632: ! 1633: (define_insn "one_cmplsi2" ! 1634: [(set (match_operand:SI 0 "general_operand" "=r") ! 1635: (not:SI (match_operand:SI 1 "arith_operand" "r")))] ! 1636: "" ! 1637: "nor\\t%0,$0,%1\\t#one_cmplsi2") ! 1638: ! 1639: ! 1640: ! 1641: (define_insn "one_cmplhi2" ! 1642: [(set (match_operand:HI 0 "general_operand" "=r") ! 1643: (not:HI (match_operand:HI 1 "arith_operand" "r")))] ! 1644: "" ! 1645: "nor\\t%0,$0,%1\\t#one_cmplhi2") ! 1646: ! 1647: ! 1648: ! 1649: (define_insn "one_cmplqi2" ! 1650: [(set (match_operand:QI 0 "general_operand" "=r") ! 1651: (not:QI (match_operand:QI 1 "arith_operand" "r")))] ! 1652: "" ! 1653: "nor\\t%0,$0,%1\\t#one_cmplqi2") ! 1654: ! 1655: ;; ! 1656: ;; .................... ! 1657: ;; ! 1658: ;; BRANCHES ! 1659: ;; ! 1660: ;; .................... ! 1661: ! 1662: ! 1663: ;;- MERGED CMPSI + BEQ ! 1664: (define_peephole ! 1665: [(set (cc0) ! 1666: (compare (match_operand:SI 0 "general_operand" "r") ! 1667: (match_operand:SI 1 "general_operand" "r"))) ! 1668: (set (pc) ! 1669: (if_then_else (eq (cc0) ! 1670: (const_int 0)) ! 1671: (label_ref (match_operand 2 "" "")) ! 1672: (pc)))] ! 1673: "" ! 1674: "beq \\t%0,%1,%l2\\t#beq MIPS primitive insn") ! 1675: ! 1676: ;;- MERGED CMPSI + INV BEQ ! 1677: (define_peephole ! 1678: [(set (cc0) ! 1679: (compare (match_operand:SI 0 "general_operand" "r") ! 1680: (match_operand:SI 1 "general_operand" "r"))) ! 1681: (set (pc) ! 1682: (if_then_else (ne (cc0) ! 1683: (const_int 0)) ! 1684: (pc) ! 1685: (label_ref (match_operand 2 "" ""))))] ! 1686: "" ! 1687: "beq \\t%0,%1,%l2\\t#beq inverted primitive insn") ! 1688: ;;- MERGED CMPSI + BNE ! 1689: (define_peephole ! 1690: [(set (cc0) ! 1691: (compare (match_operand:SI 0 "general_operand" "r") ! 1692: (match_operand:SI 1 "general_operand" "r"))) ! 1693: (set (pc) ! 1694: (if_then_else (ne (cc0) ! 1695: (const_int 0)) ! 1696: (label_ref (match_operand 2 "" "")) ! 1697: (pc)))] ! 1698: "" ! 1699: "bne \\t%0,%1,%l2\\t#bne MIPS primitive insn") ! 1700: ! 1701: ;;- MERGED CMPSI + INV BNE ! 1702: (define_peephole ! 1703: [(set (cc0) ! 1704: (compare (match_operand:SI 0 "general_operand" "r") ! 1705: (match_operand:SI 1 "general_operand" "r"))) ! 1706: (set (pc) ! 1707: (if_then_else (eq (cc0) ! 1708: (const_int 0)) ! 1709: (pc) ! 1710: (label_ref (match_operand 2 "" ""))))] ! 1711: "" ! 1712: "bne \\t%0,%1,%l2\\t#bne inverted primitive insn") ! 1713: ! 1714: ;;- MERGED CMPSI + BGT ! 1715: (define_peephole ! 1716: [(set (cc0) ! 1717: (compare (match_operand:SI 0 "general_operand" "r") ! 1718: (match_operand:SI 1 "general_operand" "r"))) ! 1719: (set (pc) ! 1720: (if_then_else (gt (cc0) ! 1721: (const_int 0)) ! 1722: (label_ref (match_operand 2 "" "")) ! 1723: (pc)))] ! 1724: "" ! 1725: "bgt \\t%0,%1,%l2\\t#bgt MIPS composite insn") ! 1726: ! 1727: ;;- MERGED CMPSI + INV BGT ! 1728: (define_peephole ! 1729: [(set (cc0) ! 1730: (compare (match_operand:SI 0 "general_operand" "r") ! 1731: (match_operand:SI 1 "general_operand" "r"))) ! 1732: (set (pc) ! 1733: (if_then_else (le (cc0) ! 1734: (const_int 0)) ! 1735: (pc) ! 1736: (label_ref (match_operand 2 "" ""))))] ! 1737: "" ! 1738: "bgt \\t%0,%1,%l2\\t#bgt inverted composite insn") ! 1739: ;;- MERGED CMPSI + BLT ! 1740: (define_peephole ! 1741: [(set (cc0) ! 1742: (compare (match_operand:SI 0 "general_operand" "r") ! 1743: (match_operand:SI 1 "general_operand" "r"))) ! 1744: (set (pc) ! 1745: (if_then_else (lt (cc0) ! 1746: (const_int 0)) ! 1747: (label_ref (match_operand 2 "" "")) ! 1748: (pc)))] ! 1749: "" ! 1750: "blt \\t%0,%1,%l2\\t#blt MIPS composite insn") ! 1751: ! 1752: ;;- MERGED CMPSI + INV BLT ! 1753: (define_peephole ! 1754: [(set (cc0) ! 1755: (compare (match_operand:SI 0 "general_operand" "r") ! 1756: (match_operand:SI 1 "general_operand" "r"))) ! 1757: (set (pc) ! 1758: (if_then_else (ge (cc0) ! 1759: (const_int 0)) ! 1760: (pc) ! 1761: (label_ref (match_operand 2 "" ""))))] ! 1762: "" ! 1763: "blt \\t%0,%1,%l2\\t#blt inverted composite insn") ! 1764: ;;- MERGED CMPSI + BGE ! 1765: (define_peephole ! 1766: [(set (cc0) ! 1767: (compare (match_operand:SI 0 "general_operand" "r") ! 1768: (match_operand:SI 1 "general_operand" "r"))) ! 1769: (set (pc) ! 1770: (if_then_else (ge (cc0) ! 1771: (const_int 0)) ! 1772: (label_ref (match_operand 2 "" "")) ! 1773: (pc)))] ! 1774: "" ! 1775: "bge \\t%0,%1,%l2\\t#bge composite insn") ! 1776: ! 1777: ;;- MERGED CMPSI + INV BGE ! 1778: (define_peephole ! 1779: [(set (cc0) ! 1780: (compare (match_operand:SI 0 "general_operand" "r") ! 1781: (match_operand:SI 1 "general_operand" "r"))) ! 1782: (set (pc) ! 1783: (if_then_else (lt (cc0) ! 1784: (const_int 0)) ! 1785: (pc) ! 1786: (label_ref (match_operand 2 "" ""))))] ! 1787: "" ! 1788: "bge \\t%0,%1,%l2\\t#bge inverted composite insn") ! 1789: ;;- MERGED CMPSI + BLE ! 1790: (define_peephole ! 1791: [(set (cc0) ! 1792: (compare (match_operand:SI 0 "general_operand" "r") ! 1793: (match_operand:SI 1 "general_operand" "r"))) ! 1794: (set (pc) ! 1795: (if_then_else (le (cc0) ! 1796: (const_int 0)) ! 1797: (label_ref (match_operand 2 "" "")) ! 1798: (pc)))] ! 1799: "" ! 1800: "ble \\t%0,%1,%l2\\t#ble composite insn") ! 1801: ! 1802: ;;- MERGED CMPSI + INV BLE ! 1803: (define_peephole ! 1804: [(set (cc0) ! 1805: (compare (match_operand:SI 0 "general_operand" "r") ! 1806: (match_operand:SI 1 "general_operand" "r"))) ! 1807: (set (pc) ! 1808: (if_then_else (gt (cc0) ! 1809: (const_int 0)) ! 1810: (pc) ! 1811: (label_ref (match_operand 2 "" ""))))] ! 1812: "" ! 1813: "ble \\t%0,%1,%l2\\t#ble inverted composite insn") ! 1814: ! 1815: ! 1816: ;;- MERGED CMPSI + BGT ! 1817: (define_peephole ! 1818: [(set (cc0) ! 1819: (compare (match_operand:SI 0 "general_operand" "r") ! 1820: (match_operand:SI 1 "general_operand" "r"))) ! 1821: (set (pc) ! 1822: (if_then_else (gtu (cc0) ! 1823: (const_int 0)) ! 1824: (label_ref (match_operand 2 "" "")) ! 1825: (pc)))] ! 1826: "" ! 1827: "bgtu \\t%0,%1,%l2\\t#bgtu MIPS composite insn") ! 1828: ! 1829: ;;- MERGED CMPSI + INV BGT ! 1830: (define_peephole ! 1831: [(set (cc0) ! 1832: (compare (match_operand:SI 0 "general_operand" "r") ! 1833: (match_operand:SI 1 "general_operand" "r"))) ! 1834: (set (pc) ! 1835: (if_then_else (leu (cc0) ! 1836: (const_int 0)) ! 1837: (pc) ! 1838: (label_ref (match_operand 2 "" ""))))] ! 1839: "" ! 1840: "bgtu \\t%0,%1,%l2\\t#bgtu inverted composite insn") ! 1841: ;;- MERGED CMPSI + INV BLTU ! 1842: (define_peephole ! 1843: [(set (cc0) ! 1844: (compare (match_operand:SI 0 "general_operand" "r") ! 1845: (match_operand:SI 1 "general_operand" "r"))) ! 1846: (set (pc) ! 1847: (if_then_else (geu (cc0) ! 1848: (const_int 0)) ! 1849: (pc) ! 1850: (label_ref (match_operand 2 "" ""))))] ! 1851: "" ! 1852: "bltu \\t%0,%1,%l2\\t#blt inverted composite insn") ! 1853: ;;- MERGED CMPSI + BGEU ! 1854: (define_peephole ! 1855: [(set (cc0) ! 1856: (compare (match_operand:SI 0 "general_operand" "r") ! 1857: (match_operand:SI 1 "general_operand" "r"))) ! 1858: (set (pc) ! 1859: (if_then_else (geu (cc0) ! 1860: (const_int 0)) ! 1861: (label_ref (match_operand 2 "" "")) ! 1862: (pc)))] ! 1863: "" ! 1864: "bgeu \\t%0,%1,%l2\\t#bgeu composite insn") ! 1865: ! 1866: ;;- MERGED CMPSI + INV BGEU ! 1867: (define_peephole ! 1868: [(set (cc0) ! 1869: (compare (match_operand:SI 0 "general_operand" "r") ! 1870: (match_operand:SI 1 "general_operand" "r"))) ! 1871: (set (pc) ! 1872: (if_then_else (ltu (cc0) ! 1873: (const_int 0)) ! 1874: (pc) ! 1875: (label_ref (match_operand 2 "" ""))))] ! 1876: "" ! 1877: "bgeu \\t%0,%1,%l2\\t#bgeu inverted composite insn") ! 1878: ;;- MERGED CMPSI + BLE ! 1879: (define_peephole ! 1880: [(set (cc0) ! 1881: (compare (match_operand:SI 0 "general_operand" "r") ! 1882: (match_operand:SI 1 "general_operand" "r"))) ! 1883: (set (pc) ! 1884: (if_then_else (leu (cc0) ! 1885: (const_int 0)) ! 1886: (label_ref (match_operand 2 "" "")) ! 1887: (pc)))] ! 1888: "" ! 1889: "bleu \\t%0,%1,%l2\\t#bleu composite insn") ! 1890: ! 1891: ;;- MERGED CMPSI + INV BLE ! 1892: (define_peephole ! 1893: [(set (cc0) ! 1894: (compare (match_operand:SI 0 "general_operand" "r") ! 1895: (match_operand:SI 1 "general_operand" "r"))) ! 1896: (set (pc) ! 1897: (if_then_else (gtu (cc0) ! 1898: (const_int 0)) ! 1899: (pc) ! 1900: (label_ref (match_operand 2 "" ""))))] ! 1901: "" ! 1902: "bleu \\t%0,%1,%l2\\t#bleu inverted composite insn") ! 1903: ;;- MERGED CMPSI + BLTU ! 1904: (define_peephole ! 1905: [(set (cc0) ! 1906: (compare (match_operand:SI 0 "general_operand" "r") ! 1907: (match_operand:SI 1 "general_operand" "r"))) ! 1908: (set (pc) ! 1909: (if_then_else (ltu (cc0) ! 1910: (const_int 0)) ! 1911: (label_ref (match_operand 2 "" "")) ! 1912: (pc)))] ! 1913: "" ! 1914: "bltu \\t%0,%1,%l2\\t#bltu MIPS composite insn") ! 1915: ! 1916: ;;- MERGED CMPSI + INV BLTU ! 1917: (define_peephole ! 1918: [(set (cc0) ! 1919: (compare (match_operand:SI 0 "general_operand" "r") ! 1920: (match_operand:SI 1 "general_operand" "r"))) ! 1921: (set (pc) ! 1922: (if_then_else (geu (cc0) ! 1923: (const_int 0)) ! 1924: (pc) ! 1925: (label_ref (match_operand 2 "" ""))))] ! 1926: "" ! 1927: "bltu \\t%0,%1,%l2\\t#bltu inverted composite insn") ! 1928: ! 1929: ;;- FLOATING POINT CASES ! 1930: ;;- -------------------- ! 1931: ! 1932: ;;- MERGED CMPSF + BEQ ! 1933: (define_peephole ! 1934: [(set (cc0) ! 1935: (compare (match_operand:SF 0 "general_operand" "f") ! 1936: (match_operand:SF 1 "general_operand" "f"))) ! 1937: (set (pc) ! 1938: (if_then_else (eq (cc0) ! 1939: (const_int 0)) ! 1940: (label_ref (match_operand 2 "" "")) ! 1941: (pc)))] ! 1942: "" ! 1943: "c.eq.s\\t%0,%1\\t# Merged CMPSF + BEQ \;bc1t\\t%l2\\t# Merged CMPSF + BEQ ") ! 1944: ! 1945: ;;- MERGED CMPSF + INV BEQ ! 1946: ! 1947: (define_peephole ! 1948: [(set (cc0) ! 1949: (compare (match_operand:SF 0 "general_operand" "f") ! 1950: (match_operand:SF 1 "general_operand" "f"))) ! 1951: (set (pc) ! 1952: (if_then_else (ne (cc0) ! 1953: (const_int 0)) ! 1954: (pc) ! 1955: (label_ref (match_operand 2 "" ""))))] ! 1956: "" ! 1957: "c.eq.s\\t%0,%1\\t# Merged CMPSF + BEQ \;bc1t\\t%l2\\t# Merged CMPSF + BEQ ") ! 1958: ! 1959: ;;- MERGED CMPSF + BNE ! 1960: ! 1961: (define_peephole ! 1962: [(set (cc0) ! 1963: (compare (match_operand:SF 0 "general_operand" "f") ! 1964: (match_operand:SF 1 "general_operand" "f"))) ! 1965: (set (pc) ! 1966: (if_then_else (ne (cc0) ! 1967: (const_int 0)) ! 1968: (label_ref (match_operand 2 "" "")) ! 1969: (pc)))] ! 1970: "" ! 1971: "c.eq.s\\t%0,%1\\t# Merged CMPSF + BNE \;bc1f\\t%l2\\t# Merged CMPSF + BNE ") ! 1972: ! 1973: ;;- MERGED CMPSF + INV BNE ! 1974: (define_peephole ! 1975: [(set (cc0) ! 1976: (compare (match_operand:SF 0 "general_operand" "f") ! 1977: (match_operand:SF 1 "general_operand" "f"))) ! 1978: (set (pc) ! 1979: (if_then_else (eq (cc0) ! 1980: (const_int 0)) ! 1981: (pc) ! 1982: (label_ref (match_operand 2 "" ""))))] ! 1983: "" ! 1984: "c.eq.s\\t%0,%1\\t# Merged CMPSF + I.BNE \;bc1f\\t%l2\\t# Merged CMPSF +I.BNE ") ! 1985: ! 1986: ;;- MERGED CMPSF + BGT ! 1987: (define_peephole ! 1988: [(set (cc0) ! 1989: (compare (match_operand:SF 0 "general_operand" "f") ! 1990: (match_operand:SF 1 "general_operand" "f"))) ! 1991: (set (pc) ! 1992: (if_then_else (gt (cc0) ! 1993: (const_int 0)) ! 1994: (label_ref (match_operand 2 "" "")) ! 1995: (pc)))] ! 1996: "" ! 1997: "c.le.s\\t%0,%1\\t# Merged CMPSF + BGT \;bc1f\\t%l2\\t# Merged CMPSF + BGT ") ! 1998: ! 1999: ;;- MERGED CMPSF + INV BGT ! 2000: (define_peephole ! 2001: [(set (cc0) ! 2002: (compare (match_operand:SF 0 "general_operand" "f") ! 2003: (match_operand:SF 1 "general_operand" "f"))) ! 2004: (set (pc) ! 2005: (if_then_else (le (cc0) ! 2006: (const_int 0)) ! 2007: (pc) ! 2008: (label_ref (match_operand 2 "" ""))))] ! 2009: "" ! 2010: "c.le.s\\t%0,%1\\t# Merged CMPSF + I.BGT \;bc1f\\t%l2\\t# Merged CMPSF +I. BGT ") ! 2011: ! 2012: ;;- MERGED CMPSF + BLT ! 2013: (define_peephole ! 2014: [(set (cc0) ! 2015: (compare (match_operand:SF 0 "general_operand" "f") ! 2016: (match_operand:SF 1 "general_operand" "f"))) ! 2017: (set (pc) ! 2018: (if_then_else (lt (cc0) ! 2019: (const_int 0)) ! 2020: (label_ref (match_operand 2 "" "")) ! 2021: (pc)))] ! 2022: "" ! 2023: "c.lt.s\\t%0,%1\\t# Merged CMPSF + BLT \;bc1t\\t%l2\\t# Merged CMPSF + BLT ") ! 2024: ! 2025: ;;- MERGED CMPSF + INV BLT ! 2026: (define_peephole ! 2027: [(set (cc0) ! 2028: (compare (match_operand:SF 0 "general_operand" "f") ! 2029: (match_operand:SF 1 "general_operand" "f"))) ! 2030: (set (pc) ! 2031: (if_then_else (ge (cc0) ! 2032: (const_int 0)) ! 2033: (pc) ! 2034: (label_ref (match_operand 2 "" ""))))] ! 2035: "" ! 2036: "c.lt.s\\t%0,%1\\t# Merged CMPSF + I.BLT \;bc1t\\t%l2\\t# Merged CMPSF + I.BLT ") ! 2037: ! 2038: ;;- MERGED CMPSF + BGE ! 2039: (define_peephole ! 2040: [(set (cc0) ! 2041: (compare (match_operand:SF 0 "general_operand" "f") ! 2042: (match_operand:SF 1 "general_operand" "f"))) ! 2043: (set (pc) ! 2044: (if_then_else (ge (cc0) ! 2045: (const_int 0)) ! 2046: (label_ref (match_operand 2 "" "")) ! 2047: (pc)))] ! 2048: "" ! 2049: "c.lt.s\\t%0,%1\\t# Merged CMPSF + BGE \;bc1f\\t%l2\\t# Merged CMPSF + BGE") ! 2050: ! 2051: ;;- MERGED CMPSF + INV BGE ! 2052: (define_peephole ! 2053: [(set (cc0) ! 2054: (compare (match_operand:SF 0 "general_operand" "f") ! 2055: (match_operand:SF 1 "general_operand" "f"))) ! 2056: (set (pc) ! 2057: (if_then_else (lt (cc0) ! 2058: (const_int 0)) ! 2059: (pc) ! 2060: (label_ref (match_operand 2 "" ""))))] ! 2061: "" ! 2062: "c.lt.s\\t%0,%1\\t# Merged CMPSF +INV BGE \;bc1f\\t%l2\\t# Merged CMPSF +INV BGE ") ! 2063: ;;- MERGED CMPSF + BLE ! 2064: (define_peephole ! 2065: [(set (cc0) ! 2066: (compare (match_operand:SF 0 "general_operand" "f") ! 2067: (match_operand:SF 1 "general_operand" "f"))) ! 2068: (set (pc) ! 2069: (if_then_else (le (cc0) ! 2070: (const_int 0)) ! 2071: (label_ref (match_operand 2 "" "")) ! 2072: (pc)))] ! 2073: "" ! 2074: "c.le.s\\t%0,%1\\t# Merged CMPSF + BLE \;bc1t\\t%l2\\t# Merged CMPSF + BLE ") ! 2075: ! 2076: ;;- MERGED CMPSF + INV BLE ! 2077: (define_peephole ! 2078: [(set (cc0) ! 2079: (compare (match_operand:SF 0 "general_operand" "f") ! 2080: (match_operand:SF 1 "general_operand" "f"))) ! 2081: (set (pc) ! 2082: (if_then_else (gt (cc0) ! 2083: (const_int 0)) ! 2084: (pc) ! 2085: (label_ref (match_operand 2 "" ""))))] ! 2086: "" ! 2087: "c.le.s\\t%0,%1\\t# Merged CMPSF + INV BLE \;bc1t\\t%l2\\t# Merged CMPSF +I. BLE") ! 2088: ! 2089: ;;- DOUBLE FLOATING POINT CASES ! 2090: ;;- -------------------- ! 2091: ! 2092: ;;- MERGED CMPDF + BEQ ! 2093: ! 2094: (define_peephole ! 2095: [(set (cc0) ! 2096: (compare (match_operand:DF 0 "general_operand" "f") ! 2097: (match_operand:DF 1 "general_operand" "f"))) ! 2098: (set (pc) ! 2099: (if_then_else (eq (cc0) ! 2100: (const_int 0)) ! 2101: (label_ref (match_operand 2 "" "")) ! 2102: (pc)))] ! 2103: "" ! 2104: "c.eq.d\\t%0,%1\\t# Merged CMPDF + BEQ \;bc1t\\t%l2\\t# Merged CMPDF + BEQ ") ! 2105: ! 2106: ;;- MERGED CMPDF + INV BEQ ! 2107: ! 2108: (define_peephole ! 2109: [(set (cc0) ! 2110: (compare (match_operand:DF 0 "general_operand" "f") ! 2111: (match_operand:DF 1 "general_operand" "f"))) ! 2112: (set (pc) ! 2113: (if_then_else (ne (cc0) ! 2114: (const_int 0)) ! 2115: (pc) ! 2116: (label_ref (match_operand 2 "" ""))))] ! 2117: "" ! 2118: "c.eq.d\\t%0,%1\\t# Merged CMPDF + I.BEQ \;bc1t\\t%l2\\t# Merged CMPDF +I. BEQ ") ! 2119: ! 2120: ;;- MERGED CMPDF + BNE ! 2121: ! 2122: (define_peephole ! 2123: [(set (cc0) ! 2124: (compare (match_operand:DF 0 "general_operand" "f") ! 2125: (match_operand:DF 1 "general_operand" "f"))) ! 2126: (set (pc) ! 2127: (if_then_else (ne (cc0) ! 2128: (const_int 0)) ! 2129: (label_ref (match_operand 2 "" "")) ! 2130: (pc)))] ! 2131: "" ! 2132: "c.eq.d\\t%0,%1\\t# Merged CMPDF + BNE \;bc1f\\t%l2\\t# Merged CMPDF + BNE ") ! 2133: ! 2134: ;;- MERGED CMPDF + INV BNE ! 2135: (define_peephole ! 2136: [(set (cc0) ! 2137: (compare (match_operand:DF 0 "general_operand" "f") ! 2138: (match_operand:DF 1 "general_operand" "f"))) ! 2139: (set (pc) ! 2140: (if_then_else (eq (cc0) ! 2141: (const_int 0)) ! 2142: (pc) ! 2143: (label_ref (match_operand 2 "" ""))))] ! 2144: "" ! 2145: "c.eq.d\\t%0,%1\\t# Merged CMPDF +I. BNE \;bc1f\\t%l2\\t# Merged CMPDF +I BNE") ! 2146: ! 2147: ;;- MERGED CMPDF + BGT ! 2148: (define_peephole ! 2149: [(set (cc0) ! 2150: (compare (match_operand:DF 0 "general_operand" "f") ! 2151: (match_operand:DF 1 "general_operand" "f"))) ! 2152: (set (pc) ! 2153: (if_then_else (gt (cc0) ! 2154: (const_int 0)) ! 2155: (label_ref (match_operand 2 "" "")) ! 2156: (pc)))] ! 2157: "" ! 2158: "c.le.d\\t%0,%1\\t# Merged CMPDF + BGT \;bc1f\\t%l2\\t# Merged CMPDF + BGT ") ! 2159: ! 2160: ;;- MERGED CMPDF + INV BGT ! 2161: (define_peephole ! 2162: [(set (cc0) ! 2163: (compare (match_operand:DF 0 "general_operand" "f") ! 2164: (match_operand:DF 1 "general_operand" "f"))) ! 2165: (set (pc) ! 2166: (if_then_else (le (cc0) ! 2167: (const_int 0)) ! 2168: (pc) ! 2169: (label_ref (match_operand 2 "" ""))))] ! 2170: "" ! 2171: "c.le.d\\t%0,%1\\t# Merged CMPDF + I. BGT \;bc1f\\t%l2\\t# Merged CMPDF + I. BGT ") ! 2172: ! 2173: ;;- MERGED CMPDF + BLT ! 2174: (define_peephole ! 2175: [(set (cc0) ! 2176: (compare (match_operand:DF 0 "general_operand" "f") ! 2177: (match_operand:DF 1 "general_operand" "f"))) ! 2178: (set (pc) ! 2179: (if_then_else (lt (cc0) ! 2180: (const_int 0)) ! 2181: (label_ref (match_operand 2 "" "")) ! 2182: (pc)))] ! 2183: "" ! 2184: "c.lt.d\\t%0,%1\\t# Merged CMPDF + BLT \;bc1t\\t%l2\\t# Merged CMPDF + BLT ") ! 2185: ! 2186: ;;- MERGED CMPDF + INV BLT ! 2187: (define_peephole ! 2188: [(set (cc0) ! 2189: (compare (match_operand:DF 0 "general_operand" "f") ! 2190: (match_operand:DF 1 "general_operand" "f"))) ! 2191: (set (pc) ! 2192: (if_then_else (ge (cc0) ! 2193: (const_int 0)) ! 2194: (pc) ! 2195: (label_ref (match_operand 2 "" ""))))] ! 2196: "" ! 2197: "c.lt.d\\t%0,%1\\t# Merged CMPDF + I.BLT \;bc1t\\t%l2\\t# Merged CMPDF + I.BLT") ! 2198: ! 2199: ;;- MERGED CMPDF + BGE ! 2200: (define_peephole ! 2201: [(set (cc0) ! 2202: (compare (match_operand:DF 0 "general_operand" "f") ! 2203: (match_operand:DF 1 "general_operand" "f"))) ! 2204: (set (pc) ! 2205: (if_then_else (ge (cc0) ! 2206: (const_int 0)) ! 2207: (label_ref (match_operand 2 "" "")) ! 2208: (pc)))] ! 2209: "" ! 2210: "c.lt.d\\t%0,%1\\t# Merged CMPDF + BGE \;bc1f\\t%l2\\t# Merged CMPDF + BGE") ! 2211: ! 2212: ;;- MERGED CMPDF + INV BGE ! 2213: (define_peephole ! 2214: [(set (cc0) ! 2215: (compare (match_operand:DF 0 "general_operand" "f") ! 2216: (match_operand:DF 1 "general_operand" "f"))) ! 2217: (set (pc) ! 2218: (if_then_else (lt (cc0) ! 2219: (const_int 0)) ! 2220: (pc) ! 2221: (label_ref (match_operand 2 "" ""))))] ! 2222: "" ! 2223: "c.lt.d\\t%0,%1\\t# Merged CMPDF +I. BGE \;bc1f\\t%l2\\t# Merged CMPDF +I. BGE") ! 2224: ;;- MERGED CMPDF + BLE ! 2225: (define_peephole ! 2226: [(set (cc0) ! 2227: (compare (match_operand:DF 0 "general_operand" "f") ! 2228: (match_operand:DF 1 "general_operand" "f"))) ! 2229: (set (pc) ! 2230: (if_then_else (le (cc0) ! 2231: (const_int 0)) ! 2232: (label_ref (match_operand 2 "" "")) ! 2233: (pc)))] ! 2234: "" ! 2235: "c.le.d\\t%0,%1\\t# Merged CMPDF + BLE \;bc1t\\t%l2\\t# Merged CMPDF + BLE ") ! 2236: ! 2237: ;;- MERGED CMPDF + INV BLE ! 2238: (define_peephole ! 2239: [(set (cc0) ! 2240: (compare (match_operand:DF 0 "general_operand" "f") ! 2241: (match_operand:DF 1 "general_operand" "f"))) ! 2242: (set (pc) ! 2243: (if_then_else (gt (cc0) ! 2244: (const_int 0)) ! 2245: (pc) ! 2246: (label_ref (match_operand 2 "" ""))))] ! 2247: "" ! 2248: "c.le.d\\t%0,%1\\t# Merged CMPDF +I. BLE \;bc1t\\t%l2\\t# Merged CMPDF + I.BLE ") ! 2249: ! 2250: ! 2251: ! 2252: ! 2253: ;; ! 2254: ;; .................... ! 2255: ;; ! 2256: ;; COMPARISONS ! 2257: ;; ! 2258: ;; .................... ! 2259: ! 2260: ;;- Order is significant here ! 2261: ;;- because there are untyped ! 2262: ;;- comparisons generated by ! 2263: ;;- the optimizer ! 2264: ;;- (set (cc0) ! 2265: ;;- (compare (const_int 2) ! 2266: ;;- (const_int 1))) ! 2267: ! 2268: (define_insn "cmpsi" ! 2269: [(set (cc0) ! 2270: (compare (match_operand:SI 0 "register_operand" "r") ! 2271: (match_operand:SI 1 "register_operand" "r")))] ! 2272: "" ! 2273: "* ! 2274: compare_collect (SImode, operands[0], operands[1]); ! 2275: return \" #\\tcmpsi\\t%0,%1\"; ! 2276: ") ! 2277: ! 2278: ;; These patterns are hopelessly invalid, because ! 2279: ;; comparing subword values properly requires extending them. ! 2280: ! 2281: ;; (define_insn "cmphi" ! 2282: ;; [(set (cc0) ! 2283: ;; (compare (match_operand:HI 0 "general_operand" "r") ! 2284: ;; (match_operand:HI 1 "general_operand" "r")))] ! 2285: ;; "" ! 2286: ;; "* ! 2287: ;; compare_collect (HImode, operands[0], operands[1]); ! 2288: ;; return \" #\\tcmphi\\t%0,%1\"; ! 2289: ;; ") ! 2290: ;; ! 2291: ;; (define_insn "cmpqi" ! 2292: ;; [(set (cc0) ! 2293: ;; (compare (match_operand:QI 0 "general_operand" "r") ! 2294: ;; (match_operand:QI 1 "general_operand" "r")))] ! 2295: ;; "" ! 2296: ;; "* ! 2297: ;; compare_collect (QImode, operands[0], operands[1]); ! 2298: ;; return \" #\\tcmpqi\\t%0,%1\"; ! 2299: ;; ") ! 2300: ! 2301: (define_insn "cmpdf" ! 2302: [(set (cc0) ! 2303: (compare (match_operand:DF 0 "register_operand" "f") ! 2304: (match_operand:DF 1 "register_operand" "f")))] ! 2305: "" ! 2306: "* ! 2307: compare_collect (DFmode, operands[0], operands[1]); ! 2308: return \" #\\tcmpdf\\t%0,%1\" ; ! 2309: ") ! 2310: ! 2311: (define_insn "cmpsf" ! 2312: [(set (cc0) ! 2313: (compare (match_operand:SF 0 "register_operand" "f") ! 2314: (match_operand:SF 1 "register_operand" "f")))] ! 2315: "" ! 2316: "* ! 2317: compare_collect (SFmode, operands[0], operands[1]); ! 2318: return \" #\\tcmpsf\\t%0,%1\" ; ! 2319: ") ! 2320: ! 2321: (define_insn "" ! 2322: [(set (cc0) ! 2323: (match_operand:QI 0 "general_operand" "r"))] ! 2324: "" ! 2325: "* ! 2326: compare_collect (QImode, operands[0], gen_rtx (REG, QImode, 0)); ! 2327: return \" #\\t (set (cc0)\\t%0)\"; ! 2328: ") ! 2329: ! 2330: (define_insn "" ! 2331: [(set (cc0) ! 2332: (match_operand:HI 0 "general_operand" "r"))] ! 2333: "" ! 2334: "* ! 2335: compare_collect (HImode, operands[0], gen_rtx (REG, HImode, 0)); ! 2336: return \" #\\t (set (cc0)\\t%0)\"; ! 2337: ") ! 2338: ! 2339: (define_insn "" ! 2340: [(set (cc0) ! 2341: (match_operand:SI 0 "general_operand" "r"))] ! 2342: "" ! 2343: "* ! 2344: compare_collect (SImode, operands[0], gen_rtx (REG, SImode, 0)); ! 2345: return \" #\\t (set (cc0)\\t%0)\"; ! 2346: ") ! 2347: ! 2348: ;; ! 2349: ;; .................... ! 2350: ;; ! 2351: ;; BRANCHES ! 2352: ;; ! 2353: ;; .................... ! 2354: ! 2355: (define_insn "jump" ! 2356: [(set (pc) ! 2357: (label_ref (match_operand 0 "" "")))] ! 2358: "" ! 2359: "* ! 2360: { ! 2361: if (GET_CODE (operands[0]) == REG) ! 2362: return \"j\\t%%0\\t#jump %l0 (jr not asm syntax)\"; ! 2363: else ! 2364: return \"j\\t%l0\\t#jump %l0\"; ! 2365: }") ! 2366: ! 2367: ! 2368: (define_insn "beq" ! 2369: [(set (pc) ! 2370: (if_then_else (eq (cc0) ! 2371: (const_int 0)) ! 2372: (label_ref (match_operand 0 "" "")) ! 2373: (pc)))] ! 2374: "" ! 2375: "* ! 2376: { ! 2377: rtx br_ops[3]; ! 2378: enum machine_mode mode; ! 2379: compare_restore (br_ops, &mode, insn); ! 2380: br_ops[2] = operands[0]; ! 2381: if (mode == DFmode) ! 2382: { ! 2383: output_asm_insn (\"c.eq.d\\t%0,%1\\t#beq\", br_ops); ! 2384: output_asm_insn (\"bc1t\\t%2\\t#beq\", br_ops); ! 2385: } ! 2386: else if (mode == SFmode) ! 2387: { ! 2388: output_asm_insn (\"c.eq.s\\t%0,%1\\t#beq\", br_ops); ! 2389: output_asm_insn (\"bc1t\\t%2\\t#beq\", br_ops); ! 2390: } ! 2391: else ! 2392: { ! 2393: output_asm_insn (\"beq\\t%0,%1,%2\\t#beq\", br_ops); ! 2394: } ! 2395: return \"\"; ! 2396: } ! 2397: ") ! 2398: ! 2399: (define_insn "bne" ! 2400: [(set (pc) ! 2401: (if_then_else (ne (cc0) ! 2402: (const_int 0)) ! 2403: (label_ref (match_operand 0 "" "")) ! 2404: (pc)))] ! 2405: "" ! 2406: "* ! 2407: { ! 2408: rtx br_ops[3]; ! 2409: enum machine_mode mode; ! 2410: compare_restore (br_ops, &mode, insn); ! 2411: br_ops[2] = operands[0]; ! 2412: if (mode == DFmode) ! 2413: { ! 2414: output_asm_insn (\"c.eq.d\\t%0,%1\\t#bne\", br_ops); ! 2415: output_asm_insn (\"bc1f\\t%2\\t#bne\", br_ops); ! 2416: } ! 2417: else if (mode == SFmode) ! 2418: { ! 2419: output_asm_insn (\"c.eq.s\\t%0,%1\\t#bne\", br_ops); ! 2420: output_asm_insn (\"bc1f\\t%2\\t#bne\", br_ops); ! 2421: } ! 2422: else ! 2423: { ! 2424: output_asm_insn (\"bne\\t%0,%1,%2\\t#bne\", br_ops); ! 2425: } ! 2426: return \"\"; ! 2427: } ! 2428: ! 2429: ") ! 2430: ! 2431: (define_insn "bgt" ! 2432: [(set (pc) ! 2433: (if_then_else (gt (cc0) ! 2434: (const_int 0)) ! 2435: (label_ref (match_operand 0 "" "")) ! 2436: (pc)))] ! 2437: "" ! 2438: "* ! 2439: { ! 2440: rtx br_ops[3]; ! 2441: enum machine_mode mode; ! 2442: compare_restore (br_ops, &mode, insn); ! 2443: br_ops[2] = operands[0]; ! 2444: if (mode == DFmode) ! 2445: { ! 2446: output_asm_insn (\"c.le.d\\t%0,%1\\t#bgt branch %0 > %1\", br_ops); ! 2447: output_asm_insn (\"bc1f\\t%2\\t#bgt\", br_ops); ! 2448: } ! 2449: else if (mode == SFmode) ! 2450: { ! 2451: output_asm_insn (\"c.le.s\\t%0,%1\\t#bgt branch %0 > %1\", br_ops); ! 2452: output_asm_insn (\"bc1f\\t%2\\t#bgt\", br_ops); ! 2453: } ! 2454: else ! 2455: { ! 2456: output_asm_insn (\"bgt\\t%0,%1,%2\\t#bgt\", br_ops); ! 2457: } ! 2458: return \"\"; ! 2459: } ! 2460: ! 2461: ") ! 2462: ! 2463: (define_insn "blt" ! 2464: [(set (pc) ! 2465: (if_then_else (lt (cc0) ! 2466: (const_int 0)) ! 2467: (label_ref (match_operand 0 "" "")) ! 2468: (pc)))] ! 2469: "" ! 2470: "* ! 2471: { ! 2472: rtx br_ops[3]; ! 2473: enum machine_mode mode; ! 2474: compare_restore (br_ops, &mode, insn); ! 2475: br_ops[2] = operands[0]; ! 2476: if (mode == DFmode) ! 2477: { ! 2478: output_asm_insn (\"c.lt.d\\t%0,%1\\t#blt\", br_ops); ! 2479: output_asm_insn (\"bc1t\\t%2\\t#blt\", br_ops); ! 2480: } ! 2481: else if (mode == SFmode) ! 2482: { ! 2483: output_asm_insn (\"c.lt.s\\t%0,%1\\t#blt\", br_ops); ! 2484: output_asm_insn (\"bc1t\\t%2\\t#blt\", br_ops); ! 2485: } ! 2486: else ! 2487: { ! 2488: output_asm_insn (\"blt\\t%0,%1,%2\\t#blt\", br_ops); ! 2489: } ! 2490: return \" #\\tblt \\t%l0\\t#blt\"; ! 2491: } ! 2492: ") ! 2493: ! 2494: (define_insn "bgtu" ! 2495: [(set (pc) ! 2496: (if_then_else (gtu (cc0) ! 2497: (const_int 0)) ! 2498: (label_ref (match_operand 0 "" "")) ! 2499: (pc)))] ! 2500: "" ! 2501: "* ! 2502: { ! 2503: rtx br_ops[3]; ! 2504: enum machine_mode mode; ! 2505: compare_restore (br_ops, &mode, insn); ! 2506: br_ops[2] = operands[0]; ! 2507: if (mode == DFmode) ! 2508: { ! 2509: output_asm_insn (\"c.le.d\\t%0,%1\\t#bgtu\", br_ops); ! 2510: output_asm_insn (\"bc1f\\t%2\\t#bgtu\", br_ops); ! 2511: } ! 2512: else if (mode == SFmode) ! 2513: { ! 2514: output_asm_insn (\"c.le.s\\t%0,%1\\t#bgtu\", br_ops); ! 2515: output_asm_insn (\"bc1f\\t%2\\t#bgtu\", br_ops); ! 2516: } ! 2517: else ! 2518: { ! 2519: output_asm_insn (\"bgtu\\t%0,%1,%2\\t#bgtu\", br_ops); ! 2520: } ! 2521: return \" #\\tbgtu \\t%l0\\t#bgtu\"; ! 2522: } ! 2523: ! 2524: ") ! 2525: ! 2526: (define_insn "bltu" ! 2527: [(set (pc) ! 2528: (if_then_else (ltu (cc0) ! 2529: (const_int 0)) ! 2530: (label_ref (match_operand 0 "" "")) ! 2531: (pc)))] ! 2532: "" ! 2533: "* ! 2534: { ! 2535: rtx br_ops[3]; ! 2536: enum machine_mode mode; ! 2537: compare_restore (br_ops, &mode, insn); ! 2538: br_ops[2] = operands[0]; ! 2539: if (mode == DFmode) ! 2540: { ! 2541: output_asm_insn (\"c.lt.d\\t%0,%1\\t#bltu\", br_ops); ! 2542: output_asm_insn (\"bc1t\\t%2\\t#bltu\", br_ops); ! 2543: } ! 2544: else if (mode == SFmode) ! 2545: { ! 2546: output_asm_insn (\"c.lt.s\\t%0,%1\\t#bltu\", br_ops); ! 2547: output_asm_insn (\"bc1t\\t%2\\t#bltu\", br_ops); ! 2548: } ! 2549: else ! 2550: { ! 2551: output_asm_insn (\"bltu\\t%0,%1,%2\\t#bltu\", br_ops); ! 2552: } ! 2553: return \"\"; ! 2554: } ! 2555: ") ! 2556: ! 2557: (define_insn "bge" ! 2558: [(set (pc) ! 2559: (if_then_else (ge (cc0) ! 2560: (const_int 0)) ! 2561: (label_ref (match_operand 0 "" "")) ! 2562: (pc)))] ! 2563: "" ! 2564: "* ! 2565: { ! 2566: rtx br_ops[3]; ! 2567: enum machine_mode mode; ! 2568: compare_restore (br_ops, &mode, insn); ! 2569: br_ops[2] = operands[0]; ! 2570: if (mode == DFmode) ! 2571: { ! 2572: output_asm_insn (\"c.lt.d\\t%0,%1\\t#bge\", br_ops); ! 2573: output_asm_insn (\"bc1f\\t%2\\t#bge\", br_ops); ! 2574: } ! 2575: else if (mode == SFmode) ! 2576: { ! 2577: output_asm_insn (\"c.lt.s\\t%0,%1\\t#bge\", br_ops); ! 2578: output_asm_insn (\"bc1f\\t%2\\t#bge\", br_ops); ! 2579: } ! 2580: else ! 2581: { ! 2582: output_asm_insn (\"bge\\t%0,%1,%2\\t#bge\", br_ops); ! 2583: } ! 2584: return \"\"; ! 2585: } ! 2586: ") ! 2587: ! 2588: (define_insn "bgeu" ! 2589: [(set (pc) ! 2590: (if_then_else (geu (cc0) ! 2591: (const_int 0)) ! 2592: (label_ref (match_operand 0 "" "")) ! 2593: (pc)))] ! 2594: "" ! 2595: "* ! 2596: { ! 2597: rtx br_ops[3]; ! 2598: enum machine_mode mode; ! 2599: compare_restore (br_ops, &mode, insn); ! 2600: br_ops[2] = operands[0]; ! 2601: if (mode == DFmode) ! 2602: { ! 2603: output_asm_insn (\"c.lt.d\\t%0,%1\\t#bgeu\", br_ops); ! 2604: output_asm_insn (\"bc1f\\t%2\\t#bgeu\", br_ops); ! 2605: } ! 2606: else if (mode == SFmode) ! 2607: { ! 2608: output_asm_insn (\"c.lt.s\\t%0,%1\\t#bgeu\", br_ops); ! 2609: output_asm_insn (\"bc1f\\t%2\\t#bgeu\", br_ops); ! 2610: } ! 2611: else ! 2612: { ! 2613: output_asm_insn (\"bgeu\\t%0,%1,%2\\t#bgeu\", br_ops); ! 2614: } ! 2615: return \"\"; ! 2616: } ! 2617: ") ! 2618: ! 2619: (define_insn "ble" ! 2620: [(set (pc) ! 2621: (if_then_else (le (cc0) ! 2622: (const_int 0)) ! 2623: (label_ref (match_operand 0 "" "")) ! 2624: (pc)))] ! 2625: "" ! 2626: "* ! 2627: { ! 2628: rtx br_ops[3]; ! 2629: enum machine_mode mode; ! 2630: compare_restore (br_ops, &mode, insn); ! 2631: br_ops[2] = operands[0]; ! 2632: if (mode == DFmode) ! 2633: { ! 2634: output_asm_insn (\"c.le.d\\t%0,%1\\t#ble\", br_ops); ! 2635: output_asm_insn (\"bc1t\\t%2\\t#ble\", br_ops); ! 2636: } ! 2637: else if (mode == SFmode) ! 2638: { ! 2639: output_asm_insn (\"c.le.s\\t%0,%1\\t#ble\", br_ops); ! 2640: output_asm_insn (\"bc1t\\t%2\\t#ble\", br_ops); ! 2641: } ! 2642: else ! 2643: { ! 2644: output_asm_insn (\"ble\\t%0,%1,%2\\t#ble\", br_ops); ! 2645: } ! 2646: return \"\"; ! 2647: } ! 2648: ") ! 2649: ! 2650: (define_insn "bleu" ! 2651: [(set (pc) ! 2652: (if_then_else (leu (cc0) ! 2653: (const_int 0)) ! 2654: (label_ref (match_operand 0 "" "")) ! 2655: (pc)))] ! 2656: "" ! 2657: "* ! 2658: { ! 2659: rtx br_ops[3]; ! 2660: enum machine_mode mode; ! 2661: compare_restore (br_ops, &mode, insn); ! 2662: br_ops[2] = operands[0]; ! 2663: if (mode == DFmode) ! 2664: { ! 2665: output_asm_insn (\"c.le.d\\t%0,%1\\t#ble\", br_ops); ! 2666: output_asm_insn (\"bc1t\\t%2\\t#ble\", br_ops); ! 2667: } ! 2668: else if (mode == SFmode) ! 2669: { ! 2670: output_asm_insn (\"c.le.s\\t%0,%1\\t#ble\", br_ops); ! 2671: output_asm_insn (\"bc1t\\t%2\\t#ble\", br_ops); ! 2672: } ! 2673: else ! 2674: { ! 2675: output_asm_insn (\"bleu\\t%0,%1,%2\\t#bleu\", br_ops); ! 2676: } ! 2677: return \" #\\tbleu \\t%l0\\t#bleu\"; ! 2678: } ! 2679: ") ! 2680: ! 2681: (define_insn "" ! 2682: [(set (pc) ! 2683: (if_then_else (ne (cc0) ! 2684: (const_int 0)) ! 2685: (pc) ! 2686: (label_ref (match_operand 0 "" ""))))] ! 2687: "" ! 2688: "* ! 2689: { ! 2690: rtx br_ops[3]; ! 2691: enum machine_mode mode; ! 2692: compare_restore (br_ops, &mode, insn); ! 2693: br_ops[2] = operands[0]; ! 2694: if (mode == DFmode) ! 2695: { ! 2696: output_asm_insn (\"c.eq.d\\t%0,%1\\t#beq\", br_ops); ! 2697: output_asm_insn (\"bc1t\\t%2\\t#beq\", br_ops); ! 2698: } ! 2699: else if (mode == SFmode) ! 2700: { ! 2701: output_asm_insn (\"c.eq.s\\t%0,%1\\t#beq\", br_ops); ! 2702: output_asm_insn (\"bc1t\\t%2\\t#beq\", br_ops); ! 2703: } ! 2704: else ! 2705: { ! 2706: output_asm_insn (\"beq\\t%0,%1,%2\\t#beq Inv.\", br_ops); ! 2707: } ! 2708: return \"\"; ! 2709: } ! 2710: ") ! 2711: ! 2712: (define_insn "" ! 2713: [(set (pc) ! 2714: (if_then_else (eq (cc0) ! 2715: (const_int 0)) ! 2716: (pc) ! 2717: (label_ref (match_operand 0 "" ""))))] ! 2718: "" ! 2719: "* ! 2720: { ! 2721: rtx br_ops[3]; ! 2722: enum machine_mode mode; ! 2723: compare_restore (br_ops, &mode, insn); ! 2724: br_ops[2] = operands[0]; ! 2725: if (mode == DFmode) ! 2726: { ! 2727: output_asm_insn (\"c.eq.d\\t%0,%1\\t#bne\", br_ops); ! 2728: output_asm_insn (\"bc1f\\t%2\\t#bne\", br_ops); ! 2729: } ! 2730: else if (mode == SFmode) ! 2731: { ! 2732: output_asm_insn (\"c.eq.s\\t%0,%1\\t#bne\", br_ops); ! 2733: output_asm_insn (\"bc1f\\t%2\\t#beq\", br_ops); ! 2734: } ! 2735: else ! 2736: { ! 2737: output_asm_insn (\"bne\\t%0,%1,%2\\t#bne Inv.\", br_ops); ! 2738: } ! 2739: return \"\"; ! 2740: } ! 2741: ! 2742: ") ! 2743: ! 2744: (define_insn "" ! 2745: [(set (pc) ! 2746: (if_then_else (le (cc0) ! 2747: (const_int 0)) ! 2748: (pc) ! 2749: (label_ref (match_operand 0 "" ""))))] ! 2750: "" ! 2751: "* ! 2752: { ! 2753: rtx br_ops[3]; ! 2754: enum machine_mode mode; ! 2755: compare_restore (br_ops, &mode, insn); ! 2756: br_ops[2] = operands[0]; ! 2757: if (mode == DFmode) ! 2758: { ! 2759: output_asm_insn (\"c.le.d\\t%0,%1\\t#bgt\", br_ops); ! 2760: output_asm_insn (\"bc1f\\t%2\\t#beq\", br_ops); ! 2761: } ! 2762: else if (mode == SFmode) ! 2763: { ! 2764: output_asm_insn (\"c.le.s\\t%0,%1\\t#bgt\", br_ops); ! 2765: output_asm_insn (\"bc1f\\t%2\\t#beq\", br_ops); ! 2766: } ! 2767: else ! 2768: { ! 2769: output_asm_insn (\"bgt\\t%0,%1,%2\\t#bgt Inv.\", br_ops); ! 2770: } ! 2771: return \"\"; ! 2772: } ! 2773: ") ! 2774: ! 2775: (define_insn "" ! 2776: [(set (pc) ! 2777: (if_then_else (leu (cc0) ! 2778: (const_int 0)) ! 2779: (pc) ! 2780: (label_ref (match_operand 0 "" ""))))] ! 2781: "" ! 2782: "* ! 2783: { ! 2784: rtx br_ops[3]; ! 2785: enum machine_mode mode; ! 2786: compare_restore (br_ops, &mode, insn); ! 2787: br_ops[2] = operands[0]; ! 2788: if (mode == DFmode) ! 2789: { ! 2790: output_asm_insn (\"c.le.d\\t%0,%1\\t#bgt\", br_ops); ! 2791: output_asm_insn (\"bc1f\\t%2\\t#beq\", br_ops); ! 2792: } ! 2793: else if (mode == SFmode) ! 2794: { ! 2795: output_asm_insn (\"c.le.s\\t%0,%1\\t#bgt\", br_ops); ! 2796: output_asm_insn (\"bc1f\\t%2\\t#beq\", br_ops); ! 2797: } ! 2798: else ! 2799: { ! 2800: output_asm_insn (\"bgtu\\t%0,%1,%2\\t#bgtu Inv.\", br_ops); ! 2801: } ! 2802: return \" #\\tbgtu \\t%l0\\t#bgtu\"; ! 2803: } ! 2804: ") ! 2805: ! 2806: (define_insn "" ! 2807: [(set (pc) ! 2808: (if_then_else (ge (cc0) ! 2809: (const_int 0)) ! 2810: (pc) ! 2811: (label_ref (match_operand 0 "" ""))))] ! 2812: "" ! 2813: "* ! 2814: { ! 2815: rtx br_ops[3]; ! 2816: enum machine_mode mode; ! 2817: compare_restore (br_ops, &mode, insn); ! 2818: br_ops[2] = operands[0]; ! 2819: if (mode == DFmode) ! 2820: { ! 2821: output_asm_insn (\"c.lt.d\\t%0,%1\\t#blt\", br_ops); ! 2822: output_asm_insn (\"bc1t\\t%2\\t#beq\", br_ops); ! 2823: } ! 2824: else if (mode == SFmode) ! 2825: { ! 2826: output_asm_insn (\"c.lt.s\\t%0,%1\\t#blt\", br_ops); ! 2827: output_asm_insn (\"bc1t\\t%2\\t#beq\", br_ops); ! 2828: } ! 2829: else ! 2830: { ! 2831: output_asm_insn (\"blt\\t%0,%1,%2\\t#blt Inv.\", br_ops); ! 2832: } ! 2833: return \"\"; ! 2834: } ! 2835: ") ! 2836: ! 2837: (define_insn "" ! 2838: [(set (pc) ! 2839: (if_then_else (geu (cc0) ! 2840: (const_int 0)) ! 2841: (pc) ! 2842: (label_ref (match_operand 0 "" ""))))] ! 2843: "" ! 2844: "* ! 2845: { ! 2846: rtx br_ops[3]; ! 2847: enum machine_mode mode; ! 2848: compare_restore (br_ops, &mode, insn); ! 2849: br_ops[2] = operands[0]; ! 2850: if (mode == DFmode) ! 2851: { ! 2852: output_asm_insn (\"c.lt.d\\t%0,%1\\t#bltu\", br_ops); ! 2853: output_asm_insn (\"bc1t\\t%2\\t#bltu\", br_ops); ! 2854: } ! 2855: else if (mode == SFmode) ! 2856: { ! 2857: output_asm_insn (\"c.lt.s\\t%0,%1\\t#bltu\", br_ops); ! 2858: output_asm_insn (\"bc1t\\t%2\\t#bltu\", br_ops); ! 2859: } ! 2860: else ! 2861: { ! 2862: output_asm_insn (\"bltu\\t%0,%1,%2\\t#bltu Inv.\", br_ops); ! 2863: } ! 2864: return \" #\\tbltu \\t%l0\\t#bltu\"; ! 2865: } ! 2866: ") ! 2867: ! 2868: (define_insn "" ! 2869: [(set (pc) ! 2870: (if_then_else (lt (cc0) ! 2871: (const_int 0)) ! 2872: (pc) ! 2873: (label_ref (match_operand 0 "" ""))))] ! 2874: "" ! 2875: "* ! 2876: { ! 2877: rtx br_ops[3]; ! 2878: enum machine_mode mode; ! 2879: compare_restore (br_ops, &mode, insn); ! 2880: br_ops[2] = operands[0]; ! 2881: if (mode == DFmode) ! 2882: { ! 2883: output_asm_insn (\"c.lt.d\\t%0,%1\\t#bge\", br_ops); ! 2884: output_asm_insn (\"bc1f\\t%2\\t#bge (DF) Inv.\", br_ops); ! 2885: } ! 2886: else if (mode == SFmode) ! 2887: { ! 2888: output_asm_insn (\"c.lt.s\\t%0,%1\\t#bge\", br_ops); ! 2889: output_asm_insn (\"bc1f\\t%2\\t#bge (SF) Inv.\", br_ops); ! 2890: } ! 2891: else ! 2892: { ! 2893: output_asm_insn (\"bge\\t%0,%1,%2\\t#bge Inv.\", br_ops); ! 2894: } ! 2895: return \"\"; ! 2896: } ! 2897: ") ! 2898: ! 2899: (define_insn "" ! 2900: [(set (pc) ! 2901: (if_then_else (ltu (cc0) ! 2902: (const_int 0)) ! 2903: (pc) ! 2904: (label_ref (match_operand 0 "" ""))))] ! 2905: "" ! 2906: "* ! 2907: { ! 2908: rtx br_ops[3]; ! 2909: enum machine_mode mode; ! 2910: compare_restore (br_ops, &mode, insn); ! 2911: br_ops[2] = operands[0]; ! 2912: if (mode == DFmode) ! 2913: { ! 2914: output_asm_insn (\"c.lt.d\\t%0,%1\\t#bge\", br_ops); ! 2915: output_asm_insn (\"bc1f\\t%2\\t#bgeu (DF) Inv.\", br_ops); ! 2916: } ! 2917: else if (mode == SFmode) ! 2918: { ! 2919: output_asm_insn (\"c.lt.s\\t%0,%1\\t#bge\", br_ops); ! 2920: output_asm_insn (\"bc1f\\t%2\\t#bgeu (SF )Inv.\", br_ops); ! 2921: } ! 2922: else ! 2923: { ! 2924: output_asm_insn (\"bgeu\\t%0,%1,%2\\t#bgeu Inv.\", br_ops); ! 2925: } ! 2926: return \" #\\tbgeu \\t%l0\\t#bgeu\"; ! 2927: } ! 2928: ") ! 2929: ! 2930: (define_insn "" ! 2931: [(set (pc) ! 2932: (if_then_else (gt (cc0) ! 2933: (const_int 0)) ! 2934: (pc) ! 2935: (label_ref (match_operand 0 "" ""))))] ! 2936: "" ! 2937: "* ! 2938: { ! 2939: rtx br_ops[3]; ! 2940: enum machine_mode mode; ! 2941: compare_restore (br_ops, &mode, insn); ! 2942: br_ops[2] = operands[0]; ! 2943: if (mode == DFmode) ! 2944: { ! 2945: output_asm_insn (\"c.le.d\\t%0,%1\\t#ble\", br_ops); ! 2946: output_asm_insn (\"bc1t\\t%2\\t#ble\", br_ops); ! 2947: } ! 2948: else if (mode == SFmode) ! 2949: { ! 2950: output_asm_insn (\"c.le.s\\t%0,%1\\t#ble\", br_ops); ! 2951: output_asm_insn (\"bc1t\\t%2\\t#ble\", br_ops); ! 2952: } ! 2953: else ! 2954: { ! 2955: output_asm_insn (\"ble\\t%0,%1,%2\\t#ble Inv.\", br_ops); ! 2956: } ! 2957: return \"\"; ! 2958: } ! 2959: ") ! 2960: ! 2961: (define_insn "" ! 2962: [(set (pc) ! 2963: (if_then_else (gtu (cc0) ! 2964: (const_int 0)) ! 2965: (pc) ! 2966: (label_ref (match_operand 0 "" ""))))] ! 2967: "" ! 2968: "* ! 2969: { ! 2970: rtx br_ops[3]; ! 2971: enum machine_mode mode; ! 2972: compare_restore (br_ops, &mode, insn); ! 2973: br_ops[2] = operands[0]; ! 2974: if (mode == DFmode) ! 2975: { ! 2976: output_asm_insn (\"c.le.d\\t%0,%1\\t#bleu\", br_ops); ! 2977: output_asm_insn (\"bc1t\\t%2\\t#bleu\", br_ops); ! 2978: } ! 2979: else if (mode == SFmode) ! 2980: { ! 2981: output_asm_insn (\"c.le.s\\t%0,%1\\t#bleu\", br_ops); ! 2982: output_asm_insn (\"bc1t\\t%2\\t#bleu\", br_ops); ! 2983: } ! 2984: else ! 2985: { ! 2986: output_asm_insn (\"bleu\\t%0,%1,%2\\t#bleu Inv.\", br_ops); ! 2987: } ! 2988: return \"\"; ! 2989: } ! 2990: ") ! 2991: ! 2992: (define_insn "tablejump" ! 2993: [(set (pc) ! 2994: (match_operand:SI 0 "general_operand" "r")) ! 2995: (use (label_ref (match_operand 1 "" "")))] ! 2996: "" ! 2997: "j\\t%0\\t# tablejump, label %l1\\t (jr not asm syntax)") ! 2998: ! 2999: ;; ! 3000: ;; .................... ! 3001: ;; ! 3002: ;; LINKAGE ! 3003: ;; ! 3004: ;; .................... ! 3005: ! 3006: (define_insn "call" ! 3007: [(call (match_operand 0 "general_operand" "g") ! 3008: (match_operand 1 "general_operand" "g")) ! 3009: (clobber (reg:SI 31))] ! 3010: "" ! 3011: "* ! 3012: { ! 3013: if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF) ! 3014: return \"jal\\t%0\\t# call with %1 arguments\"; ! 3015: else ! 3016: { ! 3017: operands[0] = XEXP (operands[0], 0); ! 3018: return \"jal\\t$31,%0\\t# call with %1 arguments (reg)\"; ! 3019: } ! 3020: }" ) ! 3021: ! 3022: ! 3023: (define_expand "call_value" ! 3024: [(set (match_operand 0 "" "=rf") ! 3025: (call (match_operand:SI 1 "memory_operand" "m") ! 3026: (match_operand 2 "" "i"))) ! 3027: (clobber (reg:SI 31))] ! 3028: ;; operand 3 is next_arg_register ! 3029: "" ! 3030: " ! 3031: { ! 3032: rtx fn_rtx, nregs_rtx; ! 3033: rtvec vec; ! 3034: ! 3035: fn_rtx = operands[1]; ! 3036: ! 3037: nregs_rtx = const0_rtx; ! 3038: ! 3039: ! 3040: vec = gen_rtvec (2, ! 3041: gen_rtx (SET, VOIDmode, operands[0], ! 3042: gen_rtx (CALL, VOIDmode, fn_rtx, nregs_rtx)), ! 3043: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31))); ! 3044: ! 3045: emit_call_insn (gen_rtx (PARALLEL, VOIDmode, vec)); ! 3046: DONE; ! 3047: }") ! 3048: ! 3049: ! 3050: (define_insn "" ! 3051: [(set (match_operand 0 "general_operand" "=g,f") ! 3052: (call (match_operand 1 "general_operand" "g,g") ! 3053: (match_operand 2 "general_operand" "g,g"))) ! 3054: (clobber (match_operand 3 "general_operand" "g,g"))] ! 3055: "" ! 3056: "* ! 3057: { ! 3058: if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF) ! 3059: return \"jal\\t%1\\t# call %1 regle 2-call (VOIDmode)\"; ! 3060: else ! 3061: { ! 3062: operands[1] = XEXP (operands[1], 0); ! 3063: return \"jal\\t$31,%1\\t# call %1 regle 2-call (VOIDmode, reg)\"; ! 3064: } ! 3065: }") ! 3066: ! 3067: (define_insn "nop" ! 3068: [(const_int 0)] ! 3069: "" ! 3070: "nop") ! 3071: ! 3072: (define_expand "probe" ! 3073: [(set (reg:SI 29) (minus:SI (reg:SI 29) (const_int 4))) ! 3074: (set (mem:SI (reg:SI 29)) (const_int 0)) ! 3075: (set (reg:SI 29) (plus:SI (reg:SI 29) (const_int 4)))] ! 3076: "" ! 3077: "") ! 3078: ! 3079: ;; ! 3080: ;;- Local variables: ! 3081: ;;- mode:emacs-lisp ! 3082: ;;- comment-start: ";;- " ! 3083: ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) ! 3084: ;;- eval: (modify-syntax-entry ?[ "(]") ! 3085: ;;- eval: (modify-syntax-entry ?] ")[") ! 3086: ;;- eval: (modify-syntax-entry ?{ "(}") ! 3087: ;;- eval: (modify-syntax-entry ?} "){") ! 3088: ;;- End:
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