![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to mips.md CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GCC 1.x] / gcc / config|
Return to mips.md CVS log | Up to [GCC 1.x] / gcc / config |
1.1 root 1: ;; Mips.md Naive version of Machine Description for MIPS
2: ;; Contributed by A. Lichnewsky, [email protected]
3: ;; Copyright (C) 1989 Free Software Foundation, Inc.
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 1, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21: ;;
22: ;;------------------------------------------------------------------------
23: ;;
24:
25: ;;
26: ;; ....................
27: ;;
28: ;; Peephole Optimizations for
29: ;;
30: ;; ARITHMETIC
31: ;;
32: ;; ....................
33: ;;
34: ;;- The following peepholes are
35: ;;- motivated by the fact that
36: ;;- stack movement result in some
37: ;;- cases in embarrassing sequences
38: ;;- of addiu SP,SP,int
39: ;;- addiu SP,SP,other_int
40:
41: ;;- --------------------
42: ;;- REMARK: this would be done better
43: ;;- by analysis of dependencies in
44: ;;- basic blocks, prior to REG ALLOC,
45: ;;- and simplification of trees:
46: ;;- (+ (+ REG const) const)
47: ;;- -> (+ REG newconst)
48: ;;- --------------------
49: (define_peephole
50: [(set (match_operand:SI 0 "general_operand" "=r")
51: (plus:SI (match_operand:SI 1 "general_operand" "r")
52: (match_operand:SI 2 "general_operand" "IJ")))
53: (set (match_operand:SI 3 "general_operand" "=r")
54: (plus:SI (match_dup 0)
55: (match_operand:SI 4 "general_operand" "IJ")))]
56: " /* DATA FLOW SEMANTICS*/
57: (((REGNO (operands[0])) == (REGNO (operands[3])))
58: ||
59: dead_or_set_p (insn, operands[0]))
60: &&
61: ( /* CONSTRAINTS */
62: (GET_CODE (operands[2]) == CONST_INT)
63: && ((CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I'))
64: ||(CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
65: && (GET_CODE (operands[4]) == CONST_INT)
66: && ((CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'I'))
67: ||(CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'J'))))
68: "
69: "*
70: {
71: rtx ops[3];
72: int i;
73: i = INTVAL (operands[2]) + INTVAL (operands[4]);
74: if (i == 0)
75: {
76: if ((REGNO (operands[3])) == (REGNO (operands[1])))
77: {
78: if ((REGNO (operands[0])) == (REGNO (operands[3])))
79: return \"\\t\\t# NULL %0 <- %1 + %2; %3 <- %0 + %4\";
80: else
81: return \"\\t\\t# NULL %0 <- %1 + %2; %3 <- %0 + %4 and dead %0\";
82: }
83: else
84: return \"add%:\\t%3,%1,$0\\t# %0 <- %1 + %2; %3 <- %0 + %4 and dead %0\";
85: }
86: else
87: {
88: ops[0] = operands[3];
89: ops[1] = operands[1];
90: ops[2] = gen_rtx (CONST_INT, VOIDmode, i);
91: output_asm_insn (\"addi%:\\t%0,%1,%2\\t# simplification of:\", ops);
92: return \"\\t\\t\\t# %0 <- %1 + %2; %3 <- %0 + %4 and dead %0\";
93: }
94: }")
95:
96:
97:
98:
99: (define_peephole
100: [(set (match_operand:SI 0 "general_operand" "=r")
101: (plus:SI (match_operand:SI 1 "general_operand" "r")
102: (match_operand:SI 2 "general_operand" "IJ")))
103: (set (match_operand:SI 3 "general_operand" "=r")
104: (minus:SI (match_dup 0)
105: (match_operand:SI 4 "general_operand" "IJ")))]
106: "(((REGNO (operands[0])) == (REGNO (operands[3])))
107: ||
108: dead_or_set_p (insn, operands[0]))
109: &&
110: ( /* CONSTRAINTS */
111: (GET_CODE (operands[2]) == CONST_INT)
112: && ((CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I'))
113: ||(CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
114: && (GET_CODE (operands[4]) == CONST_INT)
115: && ((CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'I'))
116: ||(CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'J'))))
117: "
118: "*
119: {
120: rtx ops[3];
121: int i;
122: i = INTVAL (operands[2]) - INTVAL (operands[4]);
123: if (i == 0)
124: {
125: if ((REGNO (operands[3])) == (REGNO (operands[1])))
126: {
127: if ((REGNO (operands[0])) == (REGNO (operands[3])))
128: return \"\\t\\t# NULL %0 <- %1 + %2; %3 <- %0 - %4\";
129: else
130: return \"\\t\\t# NULL %0 <- %1 + %2; %3 <- %0 - %4 and dead %0\";
131: }
132: else
133: return \"add%:\\t%3,%1,$0\\t# %0 <- %1 + %2; %3 <- %0 - %4 and dead %0\";
134: }
135: else
136: {
137: ops[0] = operands[3];
138: ops[1] = operands[1];
139: ops[2] = gen_rtx (CONST_INT, VOIDmode, i);
140: output_asm_insn (\"addi%:\\t%0,%1,%2\\t# simplification of:\", ops);
141: return \"\\t\\t\\t# %0 <- %1 + %2; %3 <- %0 - %4 and dead %0\";
142: }
143: }")
144:
145:
146: (define_peephole
147: [(set (match_operand:SI 0 "general_operand" "=r")
148: (minus:SI (match_operand:SI 1 "general_operand" "r")
149: (match_operand:SI 2 "general_operand" "IJ")))
150: (set (match_operand:SI 3 "general_operand" "=r")
151: (plus:SI (match_dup 0)
152: (match_operand:SI 4 "general_operand" "IJ")))]
153: "(((REGNO (operands[0])) == (REGNO (operands[3])))
154: ||
155: dead_or_set_p (insn, operands[0]))
156: &&
157: ( /* CONSTRAINTS */
158: (GET_CODE (operands[2]) == CONST_INT)
159: && ((CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I'))
160: ||(CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J')))
161: && (GET_CODE (operands[4]) == CONST_INT)
162: && ((CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'I'))
163: ||(CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'J'))))
164: "
165: "*
166: {
167: rtx ops[3];
168: int i;
169: i = (- INTVAL (operands[2])) + INTVAL (operands[4]);
170: if (i == 0)
171: {
172: if ((REGNO (operands[3])) == (REGNO (operands[1])))
173: {
174: if ((REGNO (operands[0])) == (REGNO (operands[3])))
175: return \"\\t\\t# NULL %0 <- %1 - %2; %3 <- %0 + %4\";
176: else
177: return \"\\t\\t# NULL %0 <- %1 - %2; %3 <- %0 + %4 and dead %0\";
178: }
179: else
180: return \"add%:\\t%3,%1,$0\\t# %0 <- %1 - %2; %3 <- %0 + %4 and dead %0\";
181: }
182: else
183: {
184: ops[0] = operands[3];
185: ops[1] = operands[1];
186: ops[2] = gen_rtx (CONST_INT, VOIDmode, i);
187: output_asm_insn (\"addi%:\\t%0,%1,%2\\t# simplification of:\", ops);
188: return \"\\t\\t\\t# %0 <- %1 - %2; %3 <- %0 + %4 and dead %0\";
189: }
190: }")
191:
192:
193:
194:
195: (define_peephole
196: [(set (match_operand:SI 0 "general_operand" "=r")
197: (minus:SI (match_operand:SI 1 "general_operand" "r")
198: (match_operand:SI 2 "general_operand" "IJ")))
199: (set (match_operand:SI 3 "general_operand" "=r")
200: (minus:SI (match_dup 0)
201: (match_operand:SI 4 "general_operand" "IJ")))]
202: "((REGNO (operands[0]) == REGNO (operands[3])
203: || dead_or_set_p (insn, operands[0]))
204: &&
205: (GET_CODE (operands[2]) == CONST_INT
206: && (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I')
207: || CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
208: && GET_CODE (operands[4]) == CONST_INT
209: && (CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'I')
210: || CONST_OK_FOR_LETTER_P (INTVAL (operands[4]), 'J'))))"
211: "*
212: {
213: rtx ops[3];
214: int i = - (INTVAL (operands[2]) + INTVAL (operands[4]));
215:
216: if (i == 0)
217: {
218: if (REGNO (operands[3]) == REGNO (operands[1]))
219: {
220: if (REGNO (operands[0]) == REGNO (operands[3]))
221: return \"\\t\\t# NULL %0 <- %1 - %2; %3 <- %0 - %4\";
222: else
223: return \"\\t\\t# NULL %0 <- %1 - %2; %3 <- %0 - %4 and dead %0\";
224: }
225: else
226: return \"add%:\\t%3,%1,$0\\t# %0 <- %1 - %2; %3 <- %0 - %4 and dead %0\";
227: }
228: else
229: {
230: ops[0] = operands[3];
231: ops[1] = operands[1];
232: ops[2] = gen_rtx (CONST_INT, VOIDmode, i);
233: output_asm_insn (\"addi%:\\t%0,%1,%2\\t# simplification of:\", ops);
234: return \"\\t\\t\\t# %0 <- %1 - %2; %3 <- %0 - %4 and dead %0\";
235: }
236: }")
237:
238:
239: ;;
240: ;; ....................
241: ;;
242: ;; ARITHMETIC
243: ;;
244: ;; ....................
245: ;;
246:
247: (define_insn "adddf3"
248: [(set (match_operand:DF 0 "general_operand" "=f")
249: (plus:DF (match_operand:DF 1 "general_operand" "%f")
250: (match_operand:DF 2 "general_operand" "f")))]
251: ""
252: "add.d\\t%0,%1,%2")
253:
254: (define_insn "addsf3"
255: [(set (match_operand:SF 0 "general_operand" "=f")
256: (plus:SF (match_operand:SF 1 "general_operand" "%f")
257: (match_operand:SF 2 "general_operand" "f")))]
258: ""
259: "add.s\\t%0,%1,%2")
260:
261: (define_insn "addsi3"
262: [(set (match_operand:SI 0 "register_operand" "=r")
263: (plus:SI (match_operand:SI 1 "register_operand" "%r")
264: (match_operand:SI 2 "general_operand" "rIJ")))]
265: ""
266: "*
267: {
268: if (GET_CODE (operands[2]) == CONST_INT)
269: {
270: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I'))
271: return \"addi%:\\t%0,%1,%x2\\t#addsi3\\t%1,%d2 -> %0\";
272: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
273: return \"add%:\\t%0,%1,$0\\t#addsi3\\t%1,%2 -> %0\";
274: else abort_with_insn (insn, \"Constant does not fit descriptor\");
275: }
276: else
277: return \"add%:\\t%0,%1,%2\\t#addsi3\\t%1,%2 -> %0\";
278: }")
279:
280: (define_insn "addhi3"
281: [(set (match_operand:HI 0 "general_operand" "=r")
282: (plus:HI (match_operand:HI 1 "general_operand" "%r")
283: (match_operand:HI 2 "general_operand" "rIJ")))]
284: ""
285: "*
286: {
287: if (GET_CODE (operands[2]) == CONST_INT)
288: {
289: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I'))
290: return \"addi%:\\t%0,%1,%x2\\t#addhi3\\t%1,%d2 -> %0\";
291: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
292: return \"add%:\\t%0,%1,$0\\t#addhi3\\t%1,%2 -> %0\";
293: else abort_with_insn (insn, \"Constant does not fit descriptor\");
294: }
295: else
296: return \"add%:\\t%0,%1,%2\\t#addhi3 %1,%2 -> %0\";
297:
298: }")
299:
300: (define_insn "addqi3"
301: [(set (match_operand:QI 0 "general_operand" "=r")
302: (plus:QI (match_operand:QI 1 "general_operand" "%r")
303: (match_operand:QI 2 "general_operand" "rIJ")))]
304: ""
305: "*
306: {
307: if (GET_CODE (operands[2]) == CONST_INT)
308: {
309: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I'))
310: return \"addi%:\\t%0,%1,%x2\\t#addqi3\\t%1,%d2 -> %0\";
311: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
312: return \"add%:\\t%0,%1,$0\\t#addqi3\\t%1,%2 -> %0\";
313: else abort_with_insn (insn, \"Constant does not fit descriptor\");
314: }
315: else
316: return \"add%:\\t%0,%1,%2\\t#addqi3 %1,%2 -> %0\";
317: }")
318:
319: ;;- All kinds of subtract instructions.
320:
321: (define_insn "subdf3"
322: [(set (match_operand:DF 0 "general_operand" "=f")
323: (minus:DF (match_operand:DF 1 "general_operand" "f")
324: (match_operand:DF 2 "general_operand" "f")))]
325: ""
326: "sub.d\\t%0,%1,%2")
327:
328: (define_insn "subsf3"
329: [(set (match_operand:SF 0 "general_operand" "=f")
330: (minus:SF (match_operand:SF 1 "general_operand" "f")
331: (match_operand:SF 2 "general_operand" "f")))]
332: ""
333: "sub.s\\t%0,%1,%2")
334:
335: (define_insn "subsi3"
336: [(set (match_operand:SI 0 "general_operand" "=r")
337: (minus:SI (match_operand:SI 1 "general_operand" "r")
338: (match_operand:SI 2 "general_operand" "rIJ")))]
339: ""
340: "*
341: {
342: if (GET_CODE (operands[2]) == CONST_INT)
343: {
344: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I'))
345: {
346: rtx ops[4];
347: ops[0] = operands[0];
348: ops[1] = operands[1];
349: ops[3] = operands[2];
350: ops[2] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[2]));
351: output_asm_insn (\"addi%:\\t%0,%1,%x2\\t#subsi3\\t%1,%d3 -> %0\",
352: ops);
353: return \"\";
354: }
355: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
356: return \"sub%:\\t%0,%1,$0\\t#subsi3\\t%1,%2 -> %0\";
357: else abort_with_insn (insn, \"Constant does not fit descriptor\");
358: }
359: else
360: return \"sub%:\\t%0,%1,%2\\t#subsi3 %1,%2 -> %0\";
361: }")
362:
363: (define_insn "subhi3"
364: [(set (match_operand:HI 0 "general_operand" "=r")
365: (minus:HI (match_operand:HI 1 "general_operand" "r")
366: (match_operand:HI 2 "general_operand" "r")))]
367: ""
368: "*
369: {
370: if (GET_CODE (operands[2]) == CONST_INT)
371: {
372: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I'))
373: {
374: rtx ops[4];
375: ops[0] = operands[0];
376: ops[1] = operands[1];
377: ops[3] = operands[2];
378: ops[2] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[2]));
379: output_asm_insn (\"addi%:\\t%0,%1,%x2\\t#subhi3\\t%1,%d3 -> %0\"
380: , ops);
381: return \"\";
382: }
383: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
384: return \"sub%:\\t%0,%1,$0\\t#subhi3\\t%1,%2 -> %0\";
385: else abort_with_insn (insn, \"Constant does not fit descriptor\");
386: }
387: else
388: return \"sub%:\\t%0,%1,%2\\t#subhi3 %1,%2 -> %0\";
389: }")
390:
391: (define_insn "subqi3"
392: [(set (match_operand:QI 0 "general_operand" "=r")
393: (minus:QI (match_operand:QI 1 "general_operand" "r")
394: (match_operand:QI 2 "general_operand" "r")))]
395: ""
396: "*
397: {
398: if (GET_CODE (operands[2]) == CONST_INT)
399: {
400: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'I'))
401: {
402: rtx ops[4];
403: ops[0] = operands[0];
404: ops[1] = operands[1];
405: ops[3] = operands[2];
406: ops[2] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[2]));
407: output_asm_insn (\"addi%:\\t%0,%1,%x2\\t#subqi3\\t%1,%d3 -> %0\"
408: , ops);
409: return \"\";
410: }
411: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
412: return \"sub%:\\t%0,%1,$0\\t#subqi3\\t%1,%2 -> %0\";
413: else abort_with_insn (insn, \"Constant does not fit descriptor\");
414: }
415: else
416: return \"sub%:\\t%0,%1,%2\\t#subqi3 %1,%2 -> %0\";
417: }")
418:
419: ;;- Multiply instructions.
420:
421: (define_insn "muldf3"
422: [(set (match_operand:DF 0 "general_operand" "=f")
423: (mult:DF (match_operand:DF 1 "general_operand" "%f")
424: (match_operand:DF 2 "general_operand" "f")))]
425: ""
426: "mul.d\\t%0,%1,%2")
427:
428: (define_insn "mulsf3"
429: [(set (match_operand:SF 0 "general_operand" "=f")
430: (mult:SF (match_operand:SF 1 "general_operand" "%f")
431: (match_operand:SF 2 "general_operand" "f")))]
432: ""
433: "mul.s\\t%0,%1,%2")
434:
435: (define_insn "mulsi3"
436: [(set (match_operand:SI 0 "general_operand" "=r")
437: (mult:SI (match_operand:SI 1 "general_operand" "%r")
438: (match_operand:SI 2 "general_operand" "r")))]
439: ""
440: "mul\\t%0,%1,%2\\t#mulsi3 %1,%2 -> %0")
441:
442: (define_insn "mulhi3"
443: [(set (match_operand:HI 0 "general_operand" "=r")
444: (mult:HI (match_operand:HI 1 "general_operand" "%r")
445: (match_operand:HI 2 "general_operand" "r")))]
446: ""
447: "mul\\t%0,%1,%2\\t#mulhi3 %1,%2 -> %0")
448:
449: (define_insn "mulqi3"
450: [(set (match_operand:QI 0 "general_operand" "=r")
451: (mult:QI (match_operand:QI 1 "general_operand" "%r")
452: (match_operand:QI 2 "general_operand" "r")))]
453: ""
454: "mul\\t%0,%1,%2\\t#mulhi3 %1,%2 -> %0")
455:
456: ;;- Divide instructions.
457:
458: (define_insn "divdf3"
459: [(set (match_operand:DF 0 "general_operand" "=f")
460: (div:DF (match_operand:DF 1 "general_operand" "f")
461: (match_operand:DF 2 "general_operand" "f")))]
462: ""
463: "div.d\\t%0,\\t%1,%2")
464:
465: (define_insn "divsf3"
466: [(set (match_operand:SF 0 "general_operand" "=f")
467: (div:SF (match_operand:SF 1 "general_operand" "f")
468: (match_operand:SF 2 "general_operand" "f")))]
469: ""
470: "div.s\\t%0,%1,%2")
471:
472: (define_insn "divsi3"
473: [(set (match_operand:SI 0 "general_operand" "=r")
474: (div:SI (match_operand:SI 1 "general_operand" "r")
475: (match_operand:SI 2 "general_operand" "r")))]
476: ""
477: "div\\t%0,%1,%2\\t#divsi3 %1,%2 -> %0")
478:
479: (define_insn "divhi3"
480: [(set (match_operand:HI 0 "general_operand" "=r")
481: (div:HI (match_operand:HI 1 "general_operand" "r")
482: (match_operand:HI 2 "general_operand" "r")))]
483: ""
484: "div\\t%0,%1,%2\\t#divhi3 %1,%2 -> %0")
485:
486: (define_insn "divqi3"
487: [(set (match_operand:QI 0 "general_operand" "=r")
488: (div:QI (match_operand:QI 1 "general_operand" "r")
489: (match_operand:QI 2 "general_operand" "r")))]
490: ""
491: "div\\t%0,%1,%2\\t#divqi3 %1,%2 -> %0")
492:
493: ;;
494: ;; ....................
495: ;;
496: ;; LOGICAL
497: ;;
498: ;; ....................
499: ;;
500:
501: (define_insn "anddi3"
502: [(set (match_operand:DI 0 "general_operand" "=r")
503: (and:DI (match_operand:DI 1 "general_operand" "%r")
504: (match_operand:DI 2 "general_operand" "r")))]
505: ""
506: "*
507: {
508: rtx xops[3];
509: if ((REGNO (operands[0]) != (REGNO (operands[1]) +1))
510: &&
511: (REGNO (operands[0]) != (REGNO (operands[2]) +1)))
512: {
513: /* TAKE CARE OF OVERLAPS */
514: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0]));
515: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
516: xops[2] = gen_rtx (REG, SImode, REGNO (operands[2]));
517: output_asm_insn (\"and\\t%0,%1,%2\\t#anddi %1,%2 -> %0\", xops);
518: xops[0] = gen_rtx (REG, SImode, REGNO (xops[0])+1);
519: xops[1] = gen_rtx (REG, SImode, REGNO (xops[1])+1);
520: xops[2] = gen_rtx (REG, SImode, REGNO (xops[2])+1);
521: output_asm_insn (\"and\\t%0,%1,%2\\t#anddi %1,%2 -> %0\", xops);
522: }
523: else
524: abort ();
525: return \"\";
526: }")
527:
528: (define_insn "andsi3"
529: [(set (match_operand:SI 0 "general_operand" "=r,&r")
530: (and:SI (match_operand:SI 1 "general_operand" "%r,r")
1.1.1.2 ! root 531: (match_operand:SI 2 "general_operand" "rJ,K")))]
1.1 root 532: ""
533: "*
534: {
535: rtx xops[3];
536: if (GET_CODE (operands[2]) == CONST_INT)
537: {
1.1.1.2 ! root 538: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))
1.1 root 539: if (INTVAL (operands[2]) >= 0)
540: {
541: return \"andi\\t%0,%1,%x2\\t#andsi3\\t%1,%d2 -> %0\";
542: }
543: else
544: {
545: xops[0] = operands[0];
546: xops[1] = operands[1];;
547: xops[2] = gen_rtx (CONST_INT, VOIDmode,
548: (INTVAL (operands[2]))>>16);
549: output_asm_insn (\"lui\\t%0,%x2\\t#load higher part (andsi3)\",
550: xops);
551: xops[2] = gen_rtx (CONST_INT, VOIDmode,
552: 0xffff & (INTVAL (operands[2])));
553: output_asm_insn (\"addi%:\\t%0,$0,%x2\\t#load lower part (andsi3)\",
554: xops);
555: output_asm_insn (\"and\\t%0,%0,%1\\t#andsi3\", xops);
556: return \"\";
557: }
558: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
559: return \"and\\t%0,%1,$0\\t#andsi3\\t%1,%2 -> %0\";
560: else return \"ERROR op2 not zero \\t#andsi3\\t%1,%2 -> %0\";
561: }
562: else
563: return \"and\\t%0,%1,%2\\t#andsi3\\t%1,%2 -> %0\";
564: }")
565:
566: (define_insn "andhi3"
567: [(set (match_operand:HI 0 "general_operand" "=r")
568: (and:HI (match_operand:HI 1 "general_operand" "%r")
569: (match_operand:HI 2 "general_operand" "r")))]
570: ""
571: "and\\t%0,%1,%2\\t#andhi3 %1,%2 -> %0")
572:
573: (define_insn "andqi3"
574: [(set (match_operand:QI 0 "general_operand" "=r")
575: (and:QI (match_operand:QI 1 "general_operand" "%r")
576: (match_operand:QI 2 "general_operand" "r")))]
577: ""
578: "and\\t%0,%1,%2\\t#andqi3 %1,%2 -> %0")
579:
580: (define_insn "iordi3"
581: [(set (match_operand:DI 0 "general_operand" "=r")
582: (ior:DI (match_operand:DI 1 "general_operand" "%r")
583: (match_operand:DI 2 "general_operand" "r")))]
584: ""
585: "*
586: {
587: rtx xops[3];
588: if ((REGNO (operands[0]) != (REGNO (operands[1]) +1))
589: &&
590: (REGNO (operands[0]) != (REGNO (operands[2]) +1)))
591: {
592: /* TAKE CARE OF OVERLAPS */
593: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0]));
594: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
595: xops[2] = gen_rtx (REG, SImode, REGNO (operands[2]));
596: output_asm_insn (\"or\\t%0,%1,%2\\t#iordi3 %1,%2 -> %0\", xops);
597: xops[0] = gen_rtx (REG, SImode, REGNO (xops[0])+1);
598: xops[1] = gen_rtx (REG, SImode, REGNO (xops[1])+1);
599: xops[2] = gen_rtx (REG, SImode, REGNO (xops[2])+1);
600: output_asm_insn (\"or\\t%0,%1,%2\\t#iordi3 %1,%2 -> %0\", xops);
601: }
602: else
603: abort ();
604: return \"\";
605: }")
606:
607: (define_insn "iorsi3"
608: [(set (match_operand:SI 0 "general_operand" "=r")
609: (ior:SI (match_operand:SI 1 "general_operand" "%r")
1.1.1.2 ! root 610: (match_operand:SI 2 "general_operand" "rKJ")))]
1.1 root 611: ""
612: "*
613: {
614: if (GET_CODE (operands[2]) == CONST_INT)
615: {
1.1.1.2 ! root 616: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))
1.1 root 617: {
618: return \"ori\\t%0,%1,%x2\\t#iorsi3\\t%1,%d2 -> %0\";
619: }
620: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
621: return \"or\\t%0,%1,$0\\t#iorsi3\\t%1,%2 -> %0\";
622: else return \"ERROR op2 not zero \\t#iorsi3\\t%1,%2 -> %0\";
623: }
624: else
625: return \"or\\t%0,%1,%2\\t#iorsi3\\t%1,%2 -> %0\";
626: }")
627:
628: (define_insn "iorhi3"
629: [(set (match_operand:HI 0 "general_operand" "=r")
630: (ior:HI (match_operand:HI 1 "general_operand" "%r")
631: (match_operand:HI 2 "general_operand" "r")))]
632: ""
633: "or\\t%0,%1,%2\\t#iorhi3 %1,%2 -> %0")
634:
635: (define_insn "iorqi3"
636: [(set (match_operand:QI 0 "general_operand" "=r")
637: (ior:QI (match_operand:QI 1 "general_operand" "%r")
638: (match_operand:QI 2 "general_operand" "r")))]
639: ""
640: "or\\t%0,%1,%2\\t#iorqi3 %1,%2 -> %0")
641:
642: (define_insn "xordi3"
643: [(set (match_operand:DI 0 "general_operand" "=r")
644: (xor:DI (match_operand:DI 1 "general_operand" "r")
645: (match_operand:DI 2 "general_operand" "r")))]
646: ""
647: "*
648: {
649: rtx xops[3];
650: if ((REGNO (operands[0]) != (REGNO (operands[1]) +1))
651: &&
652: (REGNO (operands[0]) != (REGNO (operands[2]) +1)))
653: {
654: /* TAKE CARE OF OVERLAPS */
655: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0]));
656: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
657: xops[2] = gen_rtx (REG, SImode, REGNO (operands[2]));
658: output_asm_insn (\"xor\\t%0,%1,%2\\t#xordi3 %1,%2 -> %0\", xops);
659: xops[0] = gen_rtx (REG, SImode, REGNO (xops[0])+1);
660: xops[1] = gen_rtx (REG, SImode, REGNO (xops[1])+1);
661: xops[2] = gen_rtx (REG, SImode, REGNO (xops[2])+1);
662: output_asm_insn (\"xor\\t%0,%1,%2\\t#xordi3 %1,%2 -> %0\", xops);
663: }
664: else
665: abort ();
666: return \"\";
667: }")
668:
669: (define_insn "xorsi3"
670: [(set (match_operand:SI 0 "general_operand" "=r")
671: (xor:SI (match_operand:SI 1 "general_operand" "%r")
1.1.1.2 ! root 672: (match_operand:SI 2 "general_operand" "rKJ")))]
1.1 root 673: ""
674: "*
675: {
676: if (GET_CODE (operands[2]) == CONST_INT)
677: {
1.1.1.2 ! root 678: if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'K'))
1.1 root 679: {
680: return \"xori\\t%0,%1,%x2\\t#xorsi3\\t%1,%d2 -> %0\";
681: }
682: else if (CONST_OK_FOR_LETTER_P (INTVAL (operands[2]), 'J'))
683: return \"xor\\t%0,%1,$0\\t#xorsi3\\t%1,%2 -> %0\";
684: else return \"ERROR op2 not zero \\t#xorsi3\\t%1,%2 -> %0\";
685: }
686: else
687: return \"xor\\t%0,%1,%2\\t#xorsi3\\t%1,%2 -> %0\";
688: }")
689:
690: (define_insn "xorhi3"
691: [(set (match_operand:HI 0 "general_operand" "=r")
692: (xor:HI (match_operand:HI 1 "general_operand" "%r")
693: (match_operand:HI 2 "general_operand" "r")))]
694: ""
695: "xor\\t%0,%1,%2\\t#xorhi3 %1,%2 -> %0")
696:
697: (define_insn "xorqi3"
698: [(set (match_operand:QI 0 "general_operand" "=r")
699: (xor:QI (match_operand:QI 1 "general_operand" "%r")
700: (match_operand:QI 2 "general_operand" "r")))]
701: ""
702: "xor\\t%0,%1,%2\\t#xorqi3 %1,%2 -> %0")
703:
704: ;;
705: ;; ....................
706: ;;
707: ;; TRUNCATION
708: ;;
709: ;; ....................
710:
711: ;; Extension and truncation insns.
712: ;; Those for integer source operand
713: ;; are ordered widest source type first.
714:
715:
716: (define_insn "truncsiqi2"
717: [(set (match_operand:QI 0 "general_operand" "=r")
718: (truncate:QI (match_operand:SI 1 "general_operand" "r")))]
719: ""
720: "andi\\t%0,%1,0xff\\t#truncsiqi2\\t %1 -> %0")
721:
722: (define_insn "truncsihi2"
723: [(set (match_operand:HI 0 "general_operand" "=r")
724: (truncate:HI (match_operand:SI 1 "general_operand" "r")))]
725: ""
726: "*
727: output_asm_insn (\"sll\\t%0,%1,0x10\\t#truncsihi2\\t %1 -> %0\",
728: operands);
729: return \"sra\\t%0,%0,0x10\\t#truncsihi2\\t %1 -> %0\";
730: ")
731:
732: (define_insn "trunchiqi2"
733: [(set (match_operand:QI 0 "general_operand" "=r")
734: (truncate:QI (match_operand:HI 1 "general_operand" "r")))]
735: ""
736: "andi\\t%0,%1,0xff\\t#trunchiqi2\\t %1 -> %0")
737:
738: (define_insn "truncdfsf2"
739: [(set (match_operand:SF 0 "general_operand" "=f")
740: (float_truncate:SF (match_operand:DF 1 "general_operand" "f")))]
741: ""
742: "cvt.s.d\\t%0,%1\\t#truncdfsf2\\t %1 -> %0")
743:
744: ;;
745: ;; ....................
746: ;;
747: ;; ZERO EXTENSION
748: ;;
749: ;; ....................
750:
751: ;; Extension insns.
752: ;; Those for integer source operand
753: ;; are ordered widest source type first.
754:
755:
756:
757: (define_insn "zero_extendhisi2"
758: [(set (match_operand:SI 0 "general_operand" "=r,r")
759: (zero_extend:SI (match_operand:HI 1 "general_operand" "r,m")))]
760: ""
761: "*
762: {
763: if (which_alternative == 0)
764: {
765: output_asm_insn (\"sll\\t%0,%1,0x10\\t#zero_extendhisi2\\t %1 -> %0\",
766: operands);
767: return \"srl\\t%0,%0,0x10\\t#zero_extendhisi2\\t %1 -> %0\";
768: }
769: else
770: return \"lhu\\t%0,%1\\t#zero extendhisi2 %1 -> %0\";
771: }")
772:
773: (define_insn "zero_extendqihi2"
774: [(set (match_operand:HI 0 "general_operand" "=r")
775: (zero_extend:HI (match_operand:QI 1 "general_operand" "r")))]
776: ""
777: "*
778: output_asm_insn (\"sll\\t%0,%1,0x18\\t#zero_extendqihi2\\t %1 -> %0\",
779: operands);
780: return \"srl\\t%0,%0,0x18\\t#zero_extendqihi2\\t %1 -> %0\";
781: ")
782:
783:
784: (define_insn "zero_extendqisi2"
785: [(set (match_operand:SI 0 "general_operand" "=r,r")
786: (zero_extend:SI (match_operand:QI 1 "general_operand" "r,m")))]
787: ""
788: "*
789: {
790: if (which_alternative == 0)
791: {
792: return \"andi\\t%0,%1,0xff\\t#zero_extendqisi2\\t %1 -> %0\";
793: }
794: else
795: return \"lbu\\t%0,%1\\t#zero extendqisi2 %1 -> %0\";
796: }")
797:
798:
799: ;;
800: ;; ....................
801: ;;
802: ;; SIGN EXTENSION
803: ;;
804: ;; ....................
805:
806: ;; Extension insns.
807: ;; Those for integer source operand
808: ;; are ordered widest source type first.
809:
810:
811:
812: (define_insn "extendhisi2"
813: [(set (match_operand:SI 0 "general_operand" "=r,r")
814: (sign_extend:SI (match_operand:HI 1 "general_operand" "r,m")))]
815: ""
816: "*
817: {
818: if (which_alternative == 0)
819: {
820: output_asm_insn (\"sll\\t%0,%1,0x10\\t#sign extendhisi2\\t %1 -> %0\",
821: operands);
822: return \"sra\\t%0,%0,0x10\\t#sign extendhisi2\\t %1 -> %0\";
823: }
824: else
825: return \"lh\\t%0,%1\\t#sign extendhisi2 %1 -> %0\";
826: }")
827:
828: (define_insn "extendqihi2"
829: [(set (match_operand:HI 0 "general_operand" "=r")
830: (sign_extend:HI (match_operand:QI 1 "general_operand" "r")))]
831: ""
832: "*
833: output_asm_insn (\"sll\\t%0,%1,0x18\\t#sign extendqihi2\\t %1 -> %0\",
834: operands);
835: return \"sra\\t%0,%0,0x18\\t#sign extendqihi2\\t %1 -> %0\";
836: ")
837:
838:
839: (define_insn "extendqisi2"
840: [(set (match_operand:SI 0 "general_operand" "=r,r")
841: (sign_extend:SI (match_operand:QI 1 "general_operand" "r,m")))]
842: ""
843: "*
844: {
845: if (which_alternative == 0)
846: {
847: output_asm_insn (\"sll\\t%0,%1,0x18\\t#sign extendqisi2\\t %1 -> %0\",
848: operands);
849: return \"sra\\t%0,%0,0x18\\t#sign extendqisi2\\t %1 -> %0\";
850: }
851: else
852: return \"lb\\t%0,%1\\t#sign extendqisi2 %1 -> %0\";
853: }")
854:
855:
856: (define_insn "extendsfdf2"
857: [(set (match_operand:DF 0 "general_operand" "=f")
858: (float_extend:DF (match_operand:SF 1 "general_operand" "f")))]
859: ""
860: "cvt.d.s\\t%0,%1\\t#extendsfdf2\\t %1 -> %0")
861:
862:
863: ;;
864: ;; ....................
865: ;;
866: ;; CONVERSIONS
867: ;;
868: ;; ....................
869:
870:
871: (define_insn "fix_truncdfsi2"
872: [(set (match_operand:SI 0 "general_operand" "=r")
873: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "f"))))
874: (clobber (reg:DF 44))]
875: ""
876: "trunc.w.d\\t$f12,%1,%0\\t#fix_truncdfsi2\\t%1 -> %0\;mfc1\\t%0,$f12\\t#fix_truncdfsi2\\t%1 -> %0")
877:
878:
879: (define_insn "fix_truncsfsi2"
880: [(set (match_operand:SI 0 "general_operand" "=r")
881: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "f"))))
882: (clobber (reg:DF 44))]
883: ""
884: "trunc.w.s\\t$f12,%1,%0\\t#fix_truncsfsi2\\t%1 -> %0\;mfc1\\t%0,$f12\\t#fix_truncsfsi2\\t%1 -> %0")
885:
886: (define_insn "floatsidf2"
887: [(set (match_operand:DF 0 "general_operand" "=f")
888: (float:DF (match_operand:SI 1 "general_operand" "r")))]
889: ""
890: "mtc1\\t%1,%0\\t#floatsidf2\\t%1 -> %0\;cvt.d.w\\t%0,%0\\t#floatsidf2\\t%1 -> %0")
891:
892:
893: (define_insn "floatsisf2"
894: [(set (match_operand:SF 0 "general_operand" "=f")
895: (float:SF (match_operand:SI 1 "general_operand" "r")))]
896: ""
897: "mtc1\\t%1,%0\\t#floatsisf2\\t%1 -> %0\;cvt.s.w\\t%0,%0\\t#floatsisf2\\t%1 -> %0")
898:
899: ;;- Wild things used when
900: ;;- unions make double and int
901: ;;- overlap.
902: ;;-
903: ;;- This must be supported
904: ;;- since corresponding code
905: ;;- gets generated
906:
907: (define_insn ""
908: [(set (subreg:DF (match_operand:DI 0 "register_operand" "=ry") 0)
909: (match_operand:DF 1 "register_operand" "rf"))
910: (clobber (match_operand 2 "register_operand" "rf"))]
911: ""
912: "*
913: {
914: rtx xops[2];
915: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0]));
916: #ifndef DECSTATION
917: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])+1);
918: #else
919: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1]));
920: #endif
921: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> (subreg:DF %0 0) \\t likely Union\"
922: , xops);
923: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])+1);
924: #ifndef DECSTATION
925: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1]));
926: #else
927: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])+1);
928: #endif
929: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> (subreg:DF %0 0) \"
930: , xops);
931: return (\"\");
932: }")
933:
934:
935:
936: (define_insn ""
937: [(set (subreg:DF (match_operand:DI 0 "register_operand" "=ry") 0)
938: (match_operand:DF 1 "register_operand" "rf"))]
939: ""
940: "*
941: {
942: rtx xops[2];
943: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0]));
944: #ifndef DECSTATION
945: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])+1);
946: #else
947: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1]));
948: #endif
949: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> (subreg:DF %0 0) \\t likely Union\"
950: , xops);
951: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])+1);
952: #ifndef DECSTATION
953: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1]));
954: #else
955: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])+1);
956: #endif
957: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> (subreg:DF %0 0) \"
958: ,xops);
959: return (\"\");
960: }")
961:
962:
963:
964: (define_insn ""
965: [(set (match_operand:DF 0 "register_operand" "=rf")
966: (subreg:DF (match_operand:DI 1 "register_operand" "ry") 0))
967: (clobber (match_operand 2 "register_operand" "rf"))]
968: ""
969: "*
970: {
971: rtx xops[2];
972: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0]));
973: #ifndef DECSTATION
974: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1);
975: #else
976: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
977: #endif
978: output_asm_insn (\"mtc1\\t%1,%0\\t# (subreg:DF %1) -> %0 \\t\"
979: , xops);
980: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0])+1);
981: #ifndef DECSTATION
982: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
983: #else
984: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1);
985: #endif
986: output_asm_insn (\"mtc1\\t%1,%0\\t# (subreg:DF %1) -> %0 \\t\"
987: , xops);
988: return (\"\");
989: }")
990:
991:
992:
993: (define_insn ""
994: [(set (match_operand:DF 0 "register_operand" "=rf")
995: (subreg:DF (match_operand:DI 1 "register_operand" "ry") 0))]
996: ""
997: "*
998: {
999: rtx xops[2];
1000: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0]));
1001: #ifndef DECSTATION
1002: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1);
1003: #else
1004: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
1005: #endif
1006: output_asm_insn (\"mtc1\\t%1,%0\\t# (subreg:DF %1) -> %0 \\t\"
1007: , xops);
1008: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0])+1);
1009: #ifndef DECSTATION
1010: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
1011: #else
1012: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1);
1013: #endif
1014: output_asm_insn (\"mtc1\\t%1,%0\\t# (subreg:DF %1) -> %0 \\t\"
1015: , xops);
1016:
1017: return (\"\");
1018: }")
1019:
1020: ;;
1021: ;; ....................
1022: ;;
1023: ;; MOVES
1024: ;;
1025: ;; and
1026: ;;
1027: ;; LOADS AND STORES
1028: ;;
1029: ;; ....................
1030:
1031: (define_insn "movdi"
1032: [(set (match_operand:DI 0 "general_operand" "=r,*r,*m")
1033: (match_operand:DI 1 "general_operand" "r,*miF,*r"))]
1034: ""
1035: "*
1036: {
1037: extern rtx change_address ();
1038: extern rtx plus_constant ();
1039:
1040: if (which_alternative == 0)
1041: {
1042: rtx xops[2];
1043: if (REGNO (operands[0]) != (REGNO (operands[1]) +1))
1044: {
1045: /* TAKE CARE OF OVERLAPS */
1046: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0]));
1047: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
1048: output_asm_insn (\"add%:\\t%0,$0,%1\\t#movdi %1 -> %0\", xops);
1049: xops[0] = gen_rtx (REG, SImode, REGNO (xops[0])+1);
1050: xops[1] = gen_rtx (REG, SImode, REGNO (xops[1])+1);
1051: output_asm_insn (\"add%:\\t%0,$0,%1\\t#movdi %1 -> %0\", xops);
1052: }
1053: else
1054: {
1055: /* TAKE CARE OF OVERLAPS */
1056: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])+1);
1057: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1);
1058: output_asm_insn (\"add%:\\t%0,$0,%1\\t#movdi %1 -> %0\", xops);
1059: xops[0] = gen_rtx (REG, SImode, REGNO (xops[0])-1);
1060: xops[1] = gen_rtx (REG, SImode, REGNO (xops[1])-1);
1061: output_asm_insn (\"add%:\\t%0,$0,%1\\t#movdi %1 -> %0\", xops);
1062: }
1063: return \"\";
1064: }
1065: else if (which_alternative == 1)
1066: {
1067: /* No overlap here */
1068: rtx xops[2];
1069: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0]));
1070: if (GET_CODE (operands[1]) == MEM)
1071: {
1072: xops[1] = gen_rtx (MEM, SImode, XEXP (operands[1], 0));
1073: output_asm_insn (\"lw\\t%0,%1\\t#movdi %1 (mem) -> %0\", xops);
1074: }
1075: else if (CONSTANT_P (operands[1]))
1076: {
1077: #ifdef WORDS_BIG_ENDIAN
1078: xops[1] = const0_rtx;
1079: #else
1080: xops[1] = operands[1];
1081: #endif
1082: output_load_immediate (xops);
1083: }
1084: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1085: {
1086: xops[1] = gen_rtx (CONST_INT, VOIDmode,
1087: CONST_DOUBLE_LOW (operands[1]));
1088: output_load_immediate (xops);
1089: }
1090: else
1091: abort ();
1092: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])+1);
1093: if (offsettable_memref_p (operands[1]))
1094: {
1095: xops[1] = adj_offsettable_operand (gen_rtx (MEM, SImode,
1096: XEXP (operands[1], 0)),
1097: 4);
1098: output_asm_insn (\"lw\\t%0,%1\\t#movdi %1(mem) -> %0\", xops);
1099: }
1100: else if (GET_CODE (operands[1]) == MEM)
1101: {
1102: abort ();
1103: output_asm_insn (\"lw\\t%0,%1\\t#movdi %1(mem) -> %0\", xops);
1104: }
1105: else if (CONSTANT_P (operands[1]))
1106: {
1107: #ifdef WORDS_BIG_ENDIAN
1108: xops[1] = operands[1];
1109: #else
1110: xops[1] = const0_rtx;
1111: #endif
1112: output_load_immediate (xops);
1113: }
1114: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1115: {
1116: xops[1] = gen_rtx (CONST_INT, VOIDmode,
1117: CONST_DOUBLE_HIGH (operands[1]));
1118: output_load_immediate (xops);
1119: }
1120: else abort ();
1121: return \"\";
1122: }
1123: else
1124: {
1125: /* No overlap here */
1126: rtx xops[2];
1127: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
1128: if (GET_CODE (operands[0]) == MEM)
1129: xops[0] = gen_rtx (MEM, SImode, XEXP (operands[0], 0));
1130: else abort ();
1131: output_asm_insn (\"sw\\t%1,%0\\t#movdi %1 -> %0(mem)\", xops);
1132: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1);
1133: if (offsettable_memref_p (operands[0]))
1134: {
1135: xops[0] = adj_offsettable_operand (gen_rtx (MEM, SImode,
1136: XEXP (operands[0], 0)),
1137: 4);
1138: output_asm_insn (\"sw\\t%1,%0\\t#movdi %1 -> %0 (mem)\", xops);
1139: }
1140: else if (GET_CODE (operands[0]) == MEM)
1141: {
1142: abort ();
1143: output_asm_insn (\"sw\\t%1,%0\\t#movdi %1(mem) -> %0\", xops);
1144: }
1145: else abort ();
1146: return \"\";
1147: }
1148: }")
1149:
1150: (define_insn "movsi"
1151: [(set (match_operand:SI 0 "general_operand" "=r,r,m,r,r,m,*r")
1152: (match_operand:SI 1 "general_operand" "r,m,r,i,J,J,*p"))]
1153: ""
1154: "*
1155: {
1156: if (which_alternative >= 4)
1157: {
1158: if (which_alternative == 4)
1159: return \"add%:\\t%0,$0,$0\\t#movsi\\t%1 == 0 -> %0\";
1160: else if (which_alternative == 5)
1161: return \"sw\\t$0,%0\\t#movsi\\t%1 == 0 -> %0\";
1162: else if (which_alternative == 6)
1163: {
1164: rtx xops[4];
1165: register rtx addr;
1166: xops[0] = operands[0];
1167: addr = operands[1];
1168: if ((GET_CODE (addr) == PLUS)
1169: && (GET_CODE (XEXP (addr, 0)) == REG))
1170: {
1171: xops[1] = XEXP (addr, 0);
1172: xops[2] = XEXP (addr, 1);
1173: xops[3] = addr;
1174: output_asm_insn (\"addiu\\t%0,%1,%2\\t#movsi (*p)\\t%a3 -> %0\", xops);
1175: return \"\";
1176: }
1177: else abort ();
1178: }
1179: }
1180: else if ((GET_CODE (operands[0]) == REG) && (GET_CODE (operands[1]) == REG))
1181: return \"add%:\\t%0,$0,%1\\t#movsi\\t%1 -> %0 \";
1182: else if (GET_CODE (operands[0]) == REG
1183: &&
1184: GET_CODE (operands[1]) == CONST_INT)
1185: {
1186: output_load_immediate (operands);
1187: return \"\";
1188: }
1189: else if (GET_CODE (operands[0]) == REG)
1190: {
1191: if (GET_CODE (operands[1]) == SYMBOL_REF
1192: || GET_CODE (operands[1]) == LABEL_REF)
1193: return \"la\\t%0,%a1\\t#movsi %a1 -> %0\";
1194: else if (GET_CODE (operands[1]) == CONST)
1195: return \"la\\t%0,%a1\\t#movsi %a1(AExp) -> %0\";
1196: else
1197: return \"lw\\t%0,%1\\t#movsi %1 -> %0\";
1198: }
1199: else
1200: return \"sw\\t%1,%0\\t#movsi %1 -> %0\";
1201: }")
1202:
1203: (define_insn ""
1204: [(set (match_operand:SI 0 "register_operand" "=*r")
1205: (match_operand:SI 1 "address_operand" "*p"))]
1206: "FIXED_FRAME_PTR_REL_P (operands[1])"
1207: "*
1208: {
1209: rtx xops[4];
1210: register rtx addr;
1211: xops[0] = operands[0];
1212: addr = operands[1];
1213: if (GET_CODE (addr) == PLUS
1214: && GET_CODE (XEXP (addr, 0)) == REG)
1215: {
1216: xops[1] = XEXP (addr, 0);
1217: xops[2] = XEXP (addr, 1);
1218: xops[3] = addr;
1219: output_asm_insn (\"addiu\\t%0,%1,%2\\t#movsi (*p)\\t%a3 -> %0\", xops);
1220: return \"\";
1221: }
1222: else
1223: abort ();
1224: }")
1225:
1226: (define_insn "movhi"
1227: [(set (match_operand:HI 0 "general_operand" "=r,r,m,r,r,m")
1228: (match_operand:HI 1 "general_operand" "r,m,r,i,J,J"))]
1229: ""
1230: "*
1231: {
1232: if (which_alternative == 4)
1233: return \"add%:\\t%0,$0,$0\\t#movhi\\t%1 == 0 -> %0\";
1234: else if (which_alternative == 5)
1235: return \"sh\\t$0,%0\\t#movhi\\t%1 == 0 -> %0\";
1236: else if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG)
1237: return \"add%:\\t%0,$0,%1\\t#move.h %1 -> %0 \";
1238: else if (GET_CODE (operands[0]) == REG
1239: && GET_CODE (operands[1]) == CONST_INT)
1240: return \"addi%:\\t%0,$0,%x1\\t# movhi %1 -> %0\";
1241: else if (GET_CODE (operands[0]) == REG)
1242: return \"lh\\t%0,%1\\t#movhi %1 -> %0\";
1243: else
1244: return \"sh\\t%1,%0\\t#movhi %1 -> %0\";
1245: }")
1246:
1247: (define_insn "movqi"
1248: [(set (match_operand:QI 0 "general_operand" "=r,r,m,r,r,m")
1249: (match_operand:QI 1 "general_operand" "r,m,r,i,J,J"))]
1250: ""
1251: "*
1252: {
1253: if (which_alternative == 4)
1254: return \"add%:\\t%0,$0,$0\\t#movqi\\t%1 == 0 -> %0\";
1255: else if (which_alternative == 5)
1256: return \"sb\\t$0,%0\\t#movqi\\t%1 == 0 -> %0\";
1257: else if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG)
1258: return \"add%:\\t%0,$0,%1\\t#move.b %1 -> %0 \";
1259:
1260: if ((GET_CODE (operands[0]) == REG )
1261: &&
1262: (GET_CODE (operands[1]) == CONST_INT))
1263: return \"addi%:\\t%0,$0,%x1\\t# movqi %1 -> %0\";
1264:
1265: /* Should say that I am not padding high order
1266: ** bits correctly
1267: */
1268: else if (GET_CODE (operands[0]) == REG)
1269: return \"lb\\t%0,%1\\t#movqi %1 -> %0\";
1270: else
1271: return \"sb\\t%1,%0\\t#movqi %1 -> %0\";
1272: }")
1273:
1274: (define_insn "movsf"
1.1.1.2 ! root 1275: [(set (match_operand:SF 0 "general_operand" "=f,rf,m,f,!rf")
! 1276: (match_operand:SF 1 "general_operand" "f,m,rf,F,rf"))
1.1 root 1277: (clobber (reg:SI 24))]
1278: ""
1279: "*
1280: {
1281: if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG)
1.1.1.2 ! root 1282: {
! 1283: if (REGNO (operands[0]) >= 32)
! 1284: {
! 1285: if (REGNO (operands[1]) >= 32)
! 1286: return \"mov.s %0,%1\\t#movsf %1 -> %0 \";
! 1287: return \"mtc1 %1,%0\";
! 1288: }
! 1289: if (REGNO (operands[1]) >= 32)
! 1290: return \"mfc1 %0,%1\";
! 1291: return \"add%: %0,$0,%1\";
! 1292: }
1.1 root 1293:
1294: if (GET_CODE (operands[0]) == REG
1295: && GET_CODE (operands[1]) == CONST_DOUBLE)
1296: {
1297: rtx xops[3];
1298: xops[0] = operands[0];
1299: xops[1] = gen_rtx (CONST_INT, VOIDmode,
1300: (XINT (operands[1], 0))>>16);
1301: xops[2] = gen_rtx (CONST_INT, VOIDmode,
1302: XINT (operands[1], 0));
1303: output_asm_insn (\"lui\\t$24,%x1\\t#move high part of %2\", xops);
1304: xops[1] = gen_rtx (CONST_INT, VOIDmode,
1305: (XINT (operands[1], 0)) & 0xff);
1306: output_asm_insn (\"ori\\t$24,%x1\\t#move low part of %2\", xops);
1307: output_asm_insn (\"mtc1\\t$24,%0\", xops);
1308:
1309: xops[0] = gen_rtx (REG, SFmode, REGNO (xops[0])+1);
1310: xops[1] = gen_rtx (CONST_INT, VOIDmode,
1311: (XINT (operands[1], 1))>>16);
1312: xops[2] = gen_rtx (CONST_INT, VOIDmode,
1313: XINT (operands[1], 1));
1314: output_asm_insn (\"lui\\t$24,%x1\\t#move high part of %2\", xops);
1315: xops[1] = gen_rtx (CONST_INT, VOIDmode,
1316: (XINT (operands[1], 1)) & 0xff);
1317: output_asm_insn (\"ori\\t$24,%x1\\t#move low part of %2\", xops);
1318:
1319: output_asm_insn (\"mtc1\\t$24,%0\", xops);
1320: return \"cvt.s.d\\t %0,%0 \";
1321: }
1322: /* Should say that I am not padding high order
1323: ** bits correctly
1324: */
1325: else if (GET_CODE (operands[0]) == REG)
1.1.1.2 ! root 1326: {
! 1327: if (REGNO (operands[0]) < 32)
! 1328: return \"lw\\t %0,%1\\t#movsf %1 -> %0\";
! 1329: return \"l.s\\t %0,%1\\t#movsf %1 -> %0\";
! 1330: }
1.1 root 1331: else
1.1.1.2 ! root 1332: {
! 1333: if (REGNO (operands[1]) < 32)
! 1334: return \"sw\\t %1,%0\\t#movsf %1 -> %0\";
! 1335: return \"s.s\\t %1,%0\\t#movsf %1 -> %0\";
! 1336: }
1.1 root 1337: }")
1338:
1339: ;; ---
1340:
1341: (define_insn "movdf"
1342: [(set (match_operand:DF 0 "general_operand" "=f,f,m,f,*f,*y")
1343: (match_operand:DF 1 "general_operand" "f,m,f,F,*y,*f"))
1344: (clobber (reg:SI 24))]
1345: ""
1346: "*
1347: {
1348: if (which_alternative > 3)
1349: {
1350: rtx xops[2];
1351:
1352: if (REGNO (operands[1]) == 6)
1353: {
1354: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0]));
1355: #ifndef DECSTATION
1356: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1);
1357: #else
1358: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
1359: #endif
1360: output_asm_insn (\"mtc1\\t%1,%0\\t# %1 -> %0 \\tcalling sequence trick\"
1361: , xops);
1362: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0])+1);
1363: #ifndef DECSTATION
1364: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
1365: #else
1366: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1);
1367: #endif
1368: output_asm_insn (\"mtc1\\t%1,%0\\t# %1 -> %0 \\tcalling sequence trick\"
1369: , xops);
1370: return (\"\");
1371: }
1372: else if (REGNO (operands[0]) == 6)
1373: {
1374: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0]));
1375: #ifndef DECSTATION
1376: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])+1);
1377: #else
1378: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
1379: #endif
1380: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> %0 \\tcalling sequence trick\"
1381: , xops);
1382: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])+1);
1383: #ifndef DECSTATION
1384: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1]));
1385: #else
1386: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1);
1387: #endif
1388: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> %0 \\tcalling sequence trick\"
1389: , xops);
1390: return (\"\");
1391: }
1392: else
1393: abort_with_insn (insn,
1394: \"Matched *y constraint and register number wrong\");
1395: }
1396: else
1397: {
1398: if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG)
1399: return \"mov.d\\t%0,%1\\t#movdf %1 -> %0 \";
1400:
1401: if (GET_CODE (operands[0]) == REG
1402: && GET_CODE (operands[1]) == CONST_DOUBLE)
1403: {
1404: rtx xops[3];
1405: xops[0] = operands[0];
1406: xops[1] = gen_rtx (CONST_INT, VOIDmode,
1407: (XINT (operands[1], 0))>>16);
1408: xops[2] = gen_rtx (CONST_INT, VOIDmode,
1409: XINT (operands[1], 0));
1410: output_asm_insn (\"lui\\t$24,%x1\\t#move high part of %2\", xops);
1411: xops[1] = gen_rtx (CONST_INT, VOIDmode,
1412: (XINT (operands[1], 0)) & 0xff);
1413: output_asm_insn (\"ori\\t$24,%x1\\t#move low part of %2\", xops);
1414: output_asm_insn (\"mtc1\\t%0,$24\", xops);
1415:
1416: xops[0] = gen_rtx (REG, SFmode, REGNO (xops[0])+1);
1417: xops[1] = gen_rtx (CONST_INT, VOIDmode,
1418: (XINT (operands[1], 1))>>16);
1419: xops[2] = gen_rtx (CONST_INT, VOIDmode,
1420: XINT (operands[1], 1));
1421: output_asm_insn (\"lui\\t$24,%x1\\t#move high part of %2\", xops);
1422: xops[1] = gen_rtx (CONST_INT, VOIDmode,
1423: (XINT (operands[1], 1)) & 0xff);
1424: output_asm_insn (\"ori\\t$24,%x1\\t#move low part of %2\", xops);
1425:
1426: output_asm_insn (\"mtc1\\t%0,$24\", xops);
1427: return \"# \";
1428:
1429: }
1430: else if (GET_CODE (operands[0]) == REG)
1431: return \"l.d\\t %0,%1\\t#movdf %1 -> %0\";
1432: else
1433: return \"s.d\\t %1,%0\\t#movdf %1 -> %0\";
1434: }
1435: }")
1436:
1437: (define_insn ""
1438: [(set (match_operand:SF 0 "general_operand" "=f,f,m")
1439: (match_operand:SF 1 "general_operand" "f,m,f"))]
1440: ""
1441: "*
1442: {
1443: if (GET_CODE (operands[0]) == REG && GET_CODE (operands[1]) == REG)
1444: return \"mov.s %0,%1\\t#movsf %1 -> %0 \";
1445:
1446: if (GET_CODE (operands[0]) == REG)
1447: return \"l.s\\t %0,%1\\t#movsf %1 -> %0\";
1448: else
1449: return \"s.s\\t %1,%0\\t#movsf %1 -> %0\";
1450: }")
1451:
1452: ;; ---
1453:
1454: (define_insn ""
1455: [(set (match_operand:DF 0 "general_operand" "=f,f,m,*f,*y")
1456: (match_operand:DF 1 "general_operand" "f,m,f,*y,*f"))]
1457: ""
1458: "*
1459: {
1460: if (which_alternative > 2)
1461: {
1462: rtx xops[2];
1463: if (REGNO (operands[1]) == 6)
1464: {
1465: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0]));
1466: #ifndef DECSTATION
1467: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1);
1468: #else
1469: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
1470: #endif
1471: output_asm_insn (\"mtc1\\t%1,%0\\t# %1 -> %0 \\tcalling sequence trick\"
1472: , xops);
1473: xops[0] = gen_rtx (REG, DFmode, REGNO (operands[0])+1);
1474: #ifndef DECSTATION
1475: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
1476: #else
1477: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1);
1478: #endif
1479: output_asm_insn (\"mtc1\\t%1,%0\\t# %1 -> %0 \\tcalling sequence trick\"
1480: , xops);
1481: return (\"\");
1482: }
1483: else if (REGNO (operands[0]) == 6)
1484: {
1485: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0]));
1486: #ifndef DECSTATION
1487: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1])+1);
1488: #else
1489: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1]));
1490: #endif
1491: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> %0 \\tcalling sequence trick\"
1492: , xops);
1493: xops[0] = gen_rtx (REG, SImode, REGNO (operands[0])+1);
1494: #ifndef DECSTATION
1495: xops[1] = gen_rtx (REG, DFmode, REGNO (operands[1]));
1496: #else
1497: xops[1] = gen_rtx (REG, SImode, REGNO (operands[1])+1);
1498: #endif
1499: output_asm_insn (\"mfc1\\t%0,%1\\t# %1 -> %0 \\tcalling sequence trick\"
1500: , xops);
1501: return (\"\");
1502: }
1503: else
1504: abort_with_insn (insn,
1505: \"Matched *y constraint and register number wrong\");
1506: }
1507: else
1508: {
1509: if ((GET_CODE (operands[0]) == REG) && (GET_CODE (operands[1]) == REG))
1510: return \"mov.d\\t%0,%1\\t#movdf %1 -> %0 \";
1511:
1512: if (GET_CODE (operands[0]) == REG)
1513: return \"l.d\\t %0,%1\\t#movdf %1 -> %0\";
1514: else
1515: return \"s.d\\t %1,%0\\t#movdf %1 -> %0\";
1516: }
1517: }")
1518:
1519: (define_insn ""
1520: [(set (match_operand:SI 0 "general_operand" "=r")
1521: (match_operand:QI 1 "general_operand" "r"))]
1522: ""
1523: "andi\\t%0,%1,0xff\\t#Wild zero_extendqisi2\\t %1 -> %0")
1524:
1525:
1526:
1527:
1528: ;;
1529: ;; ....................
1530: ;;
1531: ;; OTHER ARITHMETIC AND SHIFT
1532: ;;
1533: ;; ....................
1534:
1535: (define_insn "ashlqi3"
1536: [(set (match_operand:QI 0 "general_operand" "=r")
1537: (ashift:QI (match_operand:QI 1 "general_operand" "r")
1538: (match_operand:SI 2 "arith32_operand" "ri")))]
1539: ""
1540: "*
1541: {
1542: if (GET_CODE (operands[2]) == CONST_INT)
1543: {
1544: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
1545: output_asm_insn (\"sll\\t%0,%1,%2\\t#ashlqi3\\t (%1<<%2) -> %0\", operands);
1546: }
1547: else
1548: output_asm_insn (\"sll\\t%0,%1,%2\\t#ashlqi3\\t (%1<<%2) -> %0 (asm syntax)\",
1549: operands);
1550: return \"andi\\t%0,%0,0xff\\t#ashlqi3\";
1551: }")
1552:
1553:
1554:
1555: (define_insn "ashlhi3"
1556: [(set (match_operand:HI 0 "general_operand" "=r")
1557: (ashift:HI (match_operand:HI 1 "general_operand" "r")
1558: (match_operand:SI 2 "arith32_operand" "ri")))]
1559: ""
1560: "*
1561: {
1562: if (GET_CODE (operands[2]) == CONST_INT)
1563: {
1564: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
1565: output_asm_insn (\"sll\\t%0,%1,%2\\t#ashlhi3\\t (%1<<%2) -> %0\",
1566: operands);
1567: }
1568: else
1569: output_asm_insn (\"sll\\t%0,%1,%2\\t#ashlhi3\\t (%1<<%2) -> %0 (asm syntax)\",
1570: operands);
1571: return \"sll\\t%0,%0,0x10\;sra\\t%0,%0,0x10\\t#ashlhi3\";
1572: }")
1573:
1574:
1575:
1576: (define_insn "ashlsi3"
1577: [(set (match_operand:SI 0 "general_operand" "=r")
1578: (ashift:SI (match_operand:SI 1 "general_operand" "r")
1579: (match_operand:SI 2 "arith32_operand" "ri")))]
1580: ""
1581: "*
1582: {
1583: if (GET_CODE (operands[2]) == CONST_INT)
1584: {
1585: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
1586: return \"sll\\t%0,%1,%2\\t#ashlsi3\\t (%1<<%2) -> %0\";
1587: }
1588: return \"sll\\t%0,%1,%2\\t#ashlsi3\\t (%1<<%2) -> %0 (asm syntax)\";
1589: }")
1590:
1591:
1592:
1593: (define_insn "ashrsi3"
1594: [(set (match_operand:SI 0 "general_operand" "=r")
1595: (ashiftrt:SI (match_operand:SI 1 "general_operand" "r")
1596: (match_operand:SI 2 "arith32_operand" "ri")))]
1597: ""
1598: "*
1599: {
1600: if (GET_CODE (operands[2]) == CONST_INT)
1601: {
1602: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
1603: return \"sra\\t%0,%1,%2\\t#ashrsi3\\t (%1>>%2) -> %0\";
1604: }
1605: return \"sra\\t%0,%1,%2\\t#ashrsi3\\t (%1>>%2) -> %0 (asm syntax for srav)\";
1606: }")
1607:
1608:
1609:
1610: (define_insn "lshrsi3"
1611: [(set (match_operand:SI 0 "general_operand" "=r")
1612: (lshiftrt:SI (match_operand:SI 1 "general_operand" "r")
1613: (match_operand:SI 2 "arith32_operand" "rn")))]
1614: ""
1615: "*
1616: {
1617: if (GET_CODE (operands[2]) == CONST_INT)
1618: {
1619: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
1620: return \"srl\\t%0,%1,%2\\t#lshrsi3\\t (%1>>%2) -> %0\";
1621: }
1622: return \"srl\\t%0,%1,%2\\t#lshrsi3\\t (%1>>%2) -> %0 (asm syntax)\";
1623: }")
1624:
1625:
1626:
1627:
1628: (define_insn "negsi2"
1629: [(set (match_operand:SI 0 "general_operand" "=r")
1.1.1.2 ! root 1630: (neg:SI (match_operand:SI 1 "general_operand" "r")))]
1.1 root 1631: ""
1632: "sub%:\\t%0,$0,%1\\t#negsi2")
1633:
1634:
1635: (define_insn "negdf2"
1636: [(set (match_operand:DF 0 "general_operand" "=f")
1637: (neg:DF (match_operand:DF 1 "general_operand" "f")))]
1638: ""
1639: "neg.d\\t%0,%1\\t#negdf2")
1640:
1641:
1642:
1643: (define_insn "negsf2"
1644:
1645: [(set (match_operand:SF 0 "general_operand" "=f")
1646: (neg:SF (match_operand:SF 1 "general_operand" "f")))]
1647: ""
1648: "neg.s\\t%0,%1\\t#negsf2")
1649:
1650:
1651: (define_insn "one_cmplsi2"
1652: [(set (match_operand:SI 0 "general_operand" "=r")
1.1.1.2 ! root 1653: (not:SI (match_operand:SI 1 "general_operand" "r")))]
1.1 root 1654: ""
1655: "nor\\t%0,$0,%1\\t#one_cmplsi2")
1656:
1657:
1658:
1659: (define_insn "one_cmplhi2"
1660: [(set (match_operand:HI 0 "general_operand" "=r")
1.1.1.2 ! root 1661: (not:HI (match_operand:HI 1 "general_operand" "r")))]
1.1 root 1662: ""
1663: "nor\\t%0,$0,%1\\t#one_cmplhi2")
1664:
1665:
1666:
1667: (define_insn "one_cmplqi2"
1668: [(set (match_operand:QI 0 "general_operand" "=r")
1.1.1.2 ! root 1669: (not:QI (match_operand:QI 1 "general_operand" "r")))]
1.1 root 1670: ""
1671: "nor\\t%0,$0,%1\\t#one_cmplqi2")
1672:
1673: ;;
1674: ;; ....................
1675: ;;
1676: ;; BRANCHES
1677: ;;
1678: ;; ....................
1679:
1680:
1681: ;;- MERGED CMPSI + BEQ
1682: (define_peephole
1683: [(set (cc0)
1684: (compare (match_operand:SI 0 "general_operand" "r")
1685: (match_operand:SI 1 "general_operand" "r")))
1686: (set (pc)
1687: (if_then_else (eq (cc0)
1688: (const_int 0))
1689: (label_ref (match_operand 2 "" ""))
1690: (pc)))]
1691: ""
1692: "beq \\t%0,%1,%l2\\t#beq MIPS primitive insn")
1693:
1694: ;;- MERGED CMPSI + INV BEQ
1695: (define_peephole
1696: [(set (cc0)
1697: (compare (match_operand:SI 0 "general_operand" "r")
1698: (match_operand:SI 1 "general_operand" "r")))
1699: (set (pc)
1700: (if_then_else (ne (cc0)
1701: (const_int 0))
1702: (pc)
1703: (label_ref (match_operand 2 "" ""))))]
1704: ""
1705: "beq \\t%0,%1,%l2\\t#beq inverted primitive insn")
1706: ;;- MERGED CMPSI + BNE
1707: (define_peephole
1708: [(set (cc0)
1709: (compare (match_operand:SI 0 "general_operand" "r")
1710: (match_operand:SI 1 "general_operand" "r")))
1711: (set (pc)
1712: (if_then_else (ne (cc0)
1713: (const_int 0))
1714: (label_ref (match_operand 2 "" ""))
1715: (pc)))]
1716: ""
1717: "bne \\t%0,%1,%l2\\t#bne MIPS primitive insn")
1718:
1719: ;;- MERGED CMPSI + INV BNE
1720: (define_peephole
1721: [(set (cc0)
1722: (compare (match_operand:SI 0 "general_operand" "r")
1723: (match_operand:SI 1 "general_operand" "r")))
1724: (set (pc)
1725: (if_then_else (eq (cc0)
1726: (const_int 0))
1727: (pc)
1728: (label_ref (match_operand 2 "" ""))))]
1729: ""
1730: "bne \\t%0,%1,%l2\\t#bne inverted primitive insn")
1731:
1732: ;;- MERGED CMPSI + BGT
1733: (define_peephole
1734: [(set (cc0)
1735: (compare (match_operand:SI 0 "general_operand" "r")
1736: (match_operand:SI 1 "general_operand" "r")))
1737: (set (pc)
1738: (if_then_else (gt (cc0)
1739: (const_int 0))
1740: (label_ref (match_operand 2 "" ""))
1741: (pc)))]
1742: ""
1743: "bgt \\t%0,%1,%l2\\t#bgt MIPS composite insn")
1744:
1745: ;;- MERGED CMPSI + INV BGT
1746: (define_peephole
1747: [(set (cc0)
1748: (compare (match_operand:SI 0 "general_operand" "r")
1749: (match_operand:SI 1 "general_operand" "r")))
1750: (set (pc)
1751: (if_then_else (le (cc0)
1752: (const_int 0))
1753: (pc)
1754: (label_ref (match_operand 2 "" ""))))]
1755: ""
1756: "bgt \\t%0,%1,%l2\\t#bgt inverted composite insn")
1757: ;;- MERGED CMPSI + BLT
1758: (define_peephole
1759: [(set (cc0)
1760: (compare (match_operand:SI 0 "general_operand" "r")
1761: (match_operand:SI 1 "general_operand" "r")))
1762: (set (pc)
1763: (if_then_else (lt (cc0)
1764: (const_int 0))
1765: (label_ref (match_operand 2 "" ""))
1766: (pc)))]
1767: ""
1768: "blt \\t%0,%1,%l2\\t#blt MIPS composite insn")
1769:
1770: ;;- MERGED CMPSI + INV BLT
1771: (define_peephole
1772: [(set (cc0)
1773: (compare (match_operand:SI 0 "general_operand" "r")
1774: (match_operand:SI 1 "general_operand" "r")))
1775: (set (pc)
1776: (if_then_else (ge (cc0)
1777: (const_int 0))
1778: (pc)
1779: (label_ref (match_operand 2 "" ""))))]
1780: ""
1781: "blt \\t%0,%1,%l2\\t#blt inverted composite insn")
1782: ;;- MERGED CMPSI + BGE
1783: (define_peephole
1784: [(set (cc0)
1785: (compare (match_operand:SI 0 "general_operand" "r")
1786: (match_operand:SI 1 "general_operand" "r")))
1787: (set (pc)
1788: (if_then_else (ge (cc0)
1789: (const_int 0))
1790: (label_ref (match_operand 2 "" ""))
1791: (pc)))]
1792: ""
1793: "bge \\t%0,%1,%l2\\t#bge composite insn")
1794:
1795: ;;- MERGED CMPSI + INV BGE
1796: (define_peephole
1797: [(set (cc0)
1798: (compare (match_operand:SI 0 "general_operand" "r")
1799: (match_operand:SI 1 "general_operand" "r")))
1800: (set (pc)
1801: (if_then_else (lt (cc0)
1802: (const_int 0))
1803: (pc)
1804: (label_ref (match_operand 2 "" ""))))]
1805: ""
1806: "bge \\t%0,%1,%l2\\t#bge inverted composite insn")
1807: ;;- MERGED CMPSI + BLE
1808: (define_peephole
1809: [(set (cc0)
1810: (compare (match_operand:SI 0 "general_operand" "r")
1811: (match_operand:SI 1 "general_operand" "r")))
1812: (set (pc)
1813: (if_then_else (le (cc0)
1814: (const_int 0))
1815: (label_ref (match_operand 2 "" ""))
1816: (pc)))]
1817: ""
1818: "ble \\t%0,%1,%l2\\t#ble composite insn")
1819:
1820: ;;- MERGED CMPSI + INV BLE
1821: (define_peephole
1822: [(set (cc0)
1823: (compare (match_operand:SI 0 "general_operand" "r")
1824: (match_operand:SI 1 "general_operand" "r")))
1825: (set (pc)
1826: (if_then_else (gt (cc0)
1827: (const_int 0))
1828: (pc)
1829: (label_ref (match_operand 2 "" ""))))]
1830: ""
1831: "ble \\t%0,%1,%l2\\t#ble inverted composite insn")
1832:
1833:
1834: ;;- MERGED CMPSI + BGT
1835: (define_peephole
1836: [(set (cc0)
1837: (compare (match_operand:SI 0 "general_operand" "r")
1838: (match_operand:SI 1 "general_operand" "r")))
1839: (set (pc)
1840: (if_then_else (gtu (cc0)
1841: (const_int 0))
1842: (label_ref (match_operand 2 "" ""))
1843: (pc)))]
1844: ""
1845: "bgtu \\t%0,%1,%l2\\t#bgtu MIPS composite insn")
1846:
1847: ;;- MERGED CMPSI + INV BGT
1848: (define_peephole
1849: [(set (cc0)
1850: (compare (match_operand:SI 0 "general_operand" "r")
1851: (match_operand:SI 1 "general_operand" "r")))
1852: (set (pc)
1853: (if_then_else (leu (cc0)
1854: (const_int 0))
1855: (pc)
1856: (label_ref (match_operand 2 "" ""))))]
1857: ""
1858: "bgtu \\t%0,%1,%l2\\t#bgtu inverted composite insn")
1859: ;;- MERGED CMPSI + INV BLTU
1860: (define_peephole
1861: [(set (cc0)
1862: (compare (match_operand:SI 0 "general_operand" "r")
1863: (match_operand:SI 1 "general_operand" "r")))
1864: (set (pc)
1865: (if_then_else (geu (cc0)
1866: (const_int 0))
1867: (pc)
1868: (label_ref (match_operand 2 "" ""))))]
1869: ""
1870: "bltu \\t%0,%1,%l2\\t#blt inverted composite insn")
1871: ;;- MERGED CMPSI + BGEU
1872: (define_peephole
1873: [(set (cc0)
1874: (compare (match_operand:SI 0 "general_operand" "r")
1875: (match_operand:SI 1 "general_operand" "r")))
1876: (set (pc)
1877: (if_then_else (geu (cc0)
1878: (const_int 0))
1879: (label_ref (match_operand 2 "" ""))
1880: (pc)))]
1881: ""
1882: "bgeu \\t%0,%1,%l2\\t#bgeu composite insn")
1883:
1884: ;;- MERGED CMPSI + INV BGEU
1885: (define_peephole
1886: [(set (cc0)
1887: (compare (match_operand:SI 0 "general_operand" "r")
1888: (match_operand:SI 1 "general_operand" "r")))
1889: (set (pc)
1890: (if_then_else (ltu (cc0)
1891: (const_int 0))
1892: (pc)
1893: (label_ref (match_operand 2 "" ""))))]
1894: ""
1895: "bgeu \\t%0,%1,%l2\\t#bgeu inverted composite insn")
1896: ;;- MERGED CMPSI + BLE
1897: (define_peephole
1898: [(set (cc0)
1899: (compare (match_operand:SI 0 "general_operand" "r")
1900: (match_operand:SI 1 "general_operand" "r")))
1901: (set (pc)
1902: (if_then_else (leu (cc0)
1903: (const_int 0))
1904: (label_ref (match_operand 2 "" ""))
1905: (pc)))]
1906: ""
1907: "bleu \\t%0,%1,%l2\\t#bleu composite insn")
1908:
1909: ;;- MERGED CMPSI + INV BLE
1910: (define_peephole
1911: [(set (cc0)
1912: (compare (match_operand:SI 0 "general_operand" "r")
1913: (match_operand:SI 1 "general_operand" "r")))
1914: (set (pc)
1915: (if_then_else (gtu (cc0)
1916: (const_int 0))
1917: (pc)
1918: (label_ref (match_operand 2 "" ""))))]
1919: ""
1920: "bleu \\t%0,%1,%l2\\t#bleu inverted composite insn")
1921: ;;- MERGED CMPSI + BLTU
1922: (define_peephole
1923: [(set (cc0)
1924: (compare (match_operand:SI 0 "general_operand" "r")
1925: (match_operand:SI 1 "general_operand" "r")))
1926: (set (pc)
1927: (if_then_else (ltu (cc0)
1928: (const_int 0))
1929: (label_ref (match_operand 2 "" ""))
1930: (pc)))]
1931: ""
1932: "bltu \\t%0,%1,%l2\\t#bltu MIPS composite insn")
1933:
1934: ;;- MERGED CMPSI + INV BLTU
1935: (define_peephole
1936: [(set (cc0)
1937: (compare (match_operand:SI 0 "general_operand" "r")
1938: (match_operand:SI 1 "general_operand" "r")))
1939: (set (pc)
1940: (if_then_else (geu (cc0)
1941: (const_int 0))
1942: (pc)
1943: (label_ref (match_operand 2 "" ""))))]
1944: ""
1945: "bltu \\t%0,%1,%l2\\t#bltu inverted composite insn")
1946:
1947: ;;- FLOATING POINT CASES
1948: ;;- --------------------
1949:
1950: ;;- MERGED CMPSF + BEQ
1951: (define_peephole
1952: [(set (cc0)
1953: (compare (match_operand:SF 0 "general_operand" "f")
1954: (match_operand:SF 1 "general_operand" "f")))
1955: (set (pc)
1956: (if_then_else (eq (cc0)
1957: (const_int 0))
1958: (label_ref (match_operand 2 "" ""))
1959: (pc)))]
1960: ""
1961: "c.eq.s\\t%0,%1\\t# Merged CMPSF + BEQ \;bc1t\\t%l2\\t# Merged CMPSF + BEQ ")
1962:
1963: ;;- MERGED CMPSF + INV BEQ
1964:
1965: (define_peephole
1966: [(set (cc0)
1967: (compare (match_operand:SF 0 "general_operand" "f")
1968: (match_operand:SF 1 "general_operand" "f")))
1969: (set (pc)
1970: (if_then_else (ne (cc0)
1971: (const_int 0))
1972: (pc)
1973: (label_ref (match_operand 2 "" ""))))]
1974: ""
1975: "c.eq.s\\t%0,%1\\t# Merged CMPSF + BEQ \;bc1t\\t%l2\\t# Merged CMPSF + BEQ ")
1976:
1977: ;;- MERGED CMPSF + BNE
1978:
1979: (define_peephole
1980: [(set (cc0)
1981: (compare (match_operand:SF 0 "general_operand" "f")
1982: (match_operand:SF 1 "general_operand" "f")))
1983: (set (pc)
1984: (if_then_else (ne (cc0)
1985: (const_int 0))
1986: (label_ref (match_operand 2 "" ""))
1987: (pc)))]
1988: ""
1989: "c.eq.s\\t%0,%1\\t# Merged CMPSF + BNE \;bc1f\\t%l2\\t# Merged CMPSF + BNE ")
1990:
1991: ;;- MERGED CMPSF + INV BNE
1992: (define_peephole
1993: [(set (cc0)
1994: (compare (match_operand:SF 0 "general_operand" "f")
1995: (match_operand:SF 1 "general_operand" "f")))
1996: (set (pc)
1997: (if_then_else (eq (cc0)
1998: (const_int 0))
1999: (pc)
2000: (label_ref (match_operand 2 "" ""))))]
2001: ""
2002: "c.eq.s\\t%0,%1\\t# Merged CMPSF + I.BNE \;bc1f\\t%l2\\t# Merged CMPSF +I.BNE ")
2003:
2004: ;;- MERGED CMPSF + BGT
2005: (define_peephole
2006: [(set (cc0)
2007: (compare (match_operand:SF 0 "general_operand" "f")
2008: (match_operand:SF 1 "general_operand" "f")))
2009: (set (pc)
2010: (if_then_else (gt (cc0)
2011: (const_int 0))
2012: (label_ref (match_operand 2 "" ""))
2013: (pc)))]
2014: ""
2015: "c.le.s\\t%0,%1\\t# Merged CMPSF + BGT \;bc1f\\t%l2\\t# Merged CMPSF + BGT ")
2016:
2017: ;;- MERGED CMPSF + INV BGT
2018: (define_peephole
2019: [(set (cc0)
2020: (compare (match_operand:SF 0 "general_operand" "f")
2021: (match_operand:SF 1 "general_operand" "f")))
2022: (set (pc)
2023: (if_then_else (le (cc0)
2024: (const_int 0))
2025: (pc)
2026: (label_ref (match_operand 2 "" ""))))]
2027: ""
2028: "c.le.s\\t%0,%1\\t# Merged CMPSF + I.BGT \;bc1f\\t%l2\\t# Merged CMPSF +I. BGT ")
2029:
2030: ;;- MERGED CMPSF + BLT
2031: (define_peephole
2032: [(set (cc0)
2033: (compare (match_operand:SF 0 "general_operand" "f")
2034: (match_operand:SF 1 "general_operand" "f")))
2035: (set (pc)
2036: (if_then_else (lt (cc0)
2037: (const_int 0))
2038: (label_ref (match_operand 2 "" ""))
2039: (pc)))]
2040: ""
2041: "c.lt.s\\t%0,%1\\t# Merged CMPSF + BLT \;bc1t\\t%l2\\t# Merged CMPSF + BLT ")
2042:
2043: ;;- MERGED CMPSF + INV BLT
2044: (define_peephole
2045: [(set (cc0)
2046: (compare (match_operand:SF 0 "general_operand" "f")
2047: (match_operand:SF 1 "general_operand" "f")))
2048: (set (pc)
2049: (if_then_else (ge (cc0)
2050: (const_int 0))
2051: (pc)
2052: (label_ref (match_operand 2 "" ""))))]
2053: ""
2054: "c.lt.s\\t%0,%1\\t# Merged CMPSF + I.BLT \;bc1t\\t%l2\\t# Merged CMPSF + I.BLT ")
2055:
2056: ;;- MERGED CMPSF + BGE
2057: (define_peephole
2058: [(set (cc0)
2059: (compare (match_operand:SF 0 "general_operand" "f")
2060: (match_operand:SF 1 "general_operand" "f")))
2061: (set (pc)
2062: (if_then_else (ge (cc0)
2063: (const_int 0))
2064: (label_ref (match_operand 2 "" ""))
2065: (pc)))]
2066: ""
2067: "c.lt.s\\t%0,%1\\t# Merged CMPSF + BGE \;bc1f\\t%l2\\t# Merged CMPSF + BGE")
2068:
2069: ;;- MERGED CMPSF + INV BGE
2070: (define_peephole
2071: [(set (cc0)
2072: (compare (match_operand:SF 0 "general_operand" "f")
2073: (match_operand:SF 1 "general_operand" "f")))
2074: (set (pc)
2075: (if_then_else (lt (cc0)
2076: (const_int 0))
2077: (pc)
2078: (label_ref (match_operand 2 "" ""))))]
2079: ""
2080: "c.lt.s\\t%0,%1\\t# Merged CMPSF +INV BGE \;bc1f\\t%l2\\t# Merged CMPSF +INV BGE ")
2081: ;;- MERGED CMPSF + BLE
2082: (define_peephole
2083: [(set (cc0)
2084: (compare (match_operand:SF 0 "general_operand" "f")
2085: (match_operand:SF 1 "general_operand" "f")))
2086: (set (pc)
2087: (if_then_else (le (cc0)
2088: (const_int 0))
2089: (label_ref (match_operand 2 "" ""))
2090: (pc)))]
2091: ""
2092: "c.le.s\\t%0,%1\\t# Merged CMPSF + BLE \;bc1t\\t%l2\\t# Merged CMPSF + BLE ")
2093:
2094: ;;- MERGED CMPSF + INV BLE
2095: (define_peephole
2096: [(set (cc0)
2097: (compare (match_operand:SF 0 "general_operand" "f")
2098: (match_operand:SF 1 "general_operand" "f")))
2099: (set (pc)
2100: (if_then_else (gt (cc0)
2101: (const_int 0))
2102: (pc)
2103: (label_ref (match_operand 2 "" ""))))]
2104: ""
2105: "c.le.s\\t%0,%1\\t# Merged CMPSF + INV BLE \;bc1t\\t%l2\\t# Merged CMPSF +I. BLE")
2106:
2107: ;;- DOUBLE FLOATING POINT CASES
2108: ;;- --------------------
2109:
2110: ;;- MERGED CMPDF + BEQ
2111:
2112: (define_peephole
2113: [(set (cc0)
2114: (compare (match_operand:DF 0 "general_operand" "f")
2115: (match_operand:DF 1 "general_operand" "f")))
2116: (set (pc)
2117: (if_then_else (eq (cc0)
2118: (const_int 0))
2119: (label_ref (match_operand 2 "" ""))
2120: (pc)))]
2121: ""
2122: "c.eq.d\\t%0,%1\\t# Merged CMPDF + BEQ \;bc1t\\t%l2\\t# Merged CMPDF + BEQ ")
2123:
2124: ;;- MERGED CMPDF + INV BEQ
2125:
2126: (define_peephole
2127: [(set (cc0)
2128: (compare (match_operand:DF 0 "general_operand" "f")
2129: (match_operand:DF 1 "general_operand" "f")))
2130: (set (pc)
2131: (if_then_else (ne (cc0)
2132: (const_int 0))
2133: (pc)
2134: (label_ref (match_operand 2 "" ""))))]
2135: ""
2136: "c.eq.d\\t%0,%1\\t# Merged CMPDF + I.BEQ \;bc1t\\t%l2\\t# Merged CMPDF +I. BEQ ")
2137:
2138: ;;- MERGED CMPDF + BNE
2139:
2140: (define_peephole
2141: [(set (cc0)
2142: (compare (match_operand:DF 0 "general_operand" "f")
2143: (match_operand:DF 1 "general_operand" "f")))
2144: (set (pc)
2145: (if_then_else (ne (cc0)
2146: (const_int 0))
2147: (label_ref (match_operand 2 "" ""))
2148: (pc)))]
2149: ""
2150: "c.eq.d\\t%0,%1\\t# Merged CMPDF + BNE \;bc1f\\t%l2\\t# Merged CMPDF + BNE ")
2151:
2152: ;;- MERGED CMPDF + INV BNE
2153: (define_peephole
2154: [(set (cc0)
2155: (compare (match_operand:DF 0 "general_operand" "f")
2156: (match_operand:DF 1 "general_operand" "f")))
2157: (set (pc)
2158: (if_then_else (eq (cc0)
2159: (const_int 0))
2160: (pc)
2161: (label_ref (match_operand 2 "" ""))))]
2162: ""
2163: "c.eq.d\\t%0,%1\\t# Merged CMPDF +I. BNE \;bc1f\\t%l2\\t# Merged CMPDF +I BNE")
2164:
2165: ;;- MERGED CMPDF + BGT
2166: (define_peephole
2167: [(set (cc0)
2168: (compare (match_operand:DF 0 "general_operand" "f")
2169: (match_operand:DF 1 "general_operand" "f")))
2170: (set (pc)
2171: (if_then_else (gt (cc0)
2172: (const_int 0))
2173: (label_ref (match_operand 2 "" ""))
2174: (pc)))]
2175: ""
2176: "c.le.d\\t%0,%1\\t# Merged CMPDF + BGT \;bc1f\\t%l2\\t# Merged CMPDF + BGT ")
2177:
2178: ;;- MERGED CMPDF + INV BGT
2179: (define_peephole
2180: [(set (cc0)
2181: (compare (match_operand:DF 0 "general_operand" "f")
2182: (match_operand:DF 1 "general_operand" "f")))
2183: (set (pc)
2184: (if_then_else (le (cc0)
2185: (const_int 0))
2186: (pc)
2187: (label_ref (match_operand 2 "" ""))))]
2188: ""
2189: "c.le.d\\t%0,%1\\t# Merged CMPDF + I. BGT \;bc1f\\t%l2\\t# Merged CMPDF + I. BGT ")
2190:
2191: ;;- MERGED CMPDF + BLT
2192: (define_peephole
2193: [(set (cc0)
2194: (compare (match_operand:DF 0 "general_operand" "f")
2195: (match_operand:DF 1 "general_operand" "f")))
2196: (set (pc)
2197: (if_then_else (lt (cc0)
2198: (const_int 0))
2199: (label_ref (match_operand 2 "" ""))
2200: (pc)))]
2201: ""
2202: "c.lt.d\\t%0,%1\\t# Merged CMPDF + BLT \;bc1t\\t%l2\\t# Merged CMPDF + BLT ")
2203:
2204: ;;- MERGED CMPDF + INV BLT
2205: (define_peephole
2206: [(set (cc0)
2207: (compare (match_operand:DF 0 "general_operand" "f")
2208: (match_operand:DF 1 "general_operand" "f")))
2209: (set (pc)
2210: (if_then_else (ge (cc0)
2211: (const_int 0))
2212: (pc)
2213: (label_ref (match_operand 2 "" ""))))]
2214: ""
2215: "c.lt.d\\t%0,%1\\t# Merged CMPDF + I.BLT \;bc1t\\t%l2\\t# Merged CMPDF + I.BLT")
2216:
2217: ;;- MERGED CMPDF + BGE
2218: (define_peephole
2219: [(set (cc0)
2220: (compare (match_operand:DF 0 "general_operand" "f")
2221: (match_operand:DF 1 "general_operand" "f")))
2222: (set (pc)
2223: (if_then_else (ge (cc0)
2224: (const_int 0))
2225: (label_ref (match_operand 2 "" ""))
2226: (pc)))]
2227: ""
2228: "c.lt.d\\t%0,%1\\t# Merged CMPDF + BGE \;bc1f\\t%l2\\t# Merged CMPDF + BGE")
2229:
2230: ;;- MERGED CMPDF + INV BGE
2231: (define_peephole
2232: [(set (cc0)
2233: (compare (match_operand:DF 0 "general_operand" "f")
2234: (match_operand:DF 1 "general_operand" "f")))
2235: (set (pc)
2236: (if_then_else (lt (cc0)
2237: (const_int 0))
2238: (pc)
2239: (label_ref (match_operand 2 "" ""))))]
2240: ""
2241: "c.lt.d\\t%0,%1\\t# Merged CMPDF +I. BGE \;bc1f\\t%l2\\t# Merged CMPDF +I. BGE")
2242: ;;- MERGED CMPDF + BLE
2243: (define_peephole
2244: [(set (cc0)
2245: (compare (match_operand:DF 0 "general_operand" "f")
2246: (match_operand:DF 1 "general_operand" "f")))
2247: (set (pc)
2248: (if_then_else (le (cc0)
2249: (const_int 0))
2250: (label_ref (match_operand 2 "" ""))
2251: (pc)))]
2252: ""
2253: "c.le.d\\t%0,%1\\t# Merged CMPDF + BLE \;bc1t\\t%l2\\t# Merged CMPDF + BLE ")
2254:
2255: ;;- MERGED CMPDF + INV BLE
2256: (define_peephole
2257: [(set (cc0)
2258: (compare (match_operand:DF 0 "general_operand" "f")
2259: (match_operand:DF 1 "general_operand" "f")))
2260: (set (pc)
2261: (if_then_else (gt (cc0)
2262: (const_int 0))
2263: (pc)
2264: (label_ref (match_operand 2 "" ""))))]
2265: ""
2266: "c.le.d\\t%0,%1\\t# Merged CMPDF +I. BLE \;bc1t\\t%l2\\t# Merged CMPDF + I.BLE ")
2267:
2268:
2269:
2270:
2271: ;;
2272: ;; ....................
2273: ;;
2274: ;; COMPARISONS
2275: ;;
2276: ;; ....................
2277:
2278: ;;- Order is significant here
2279: ;;- because there are untyped
2280: ;;- comparisons generated by
2281: ;;- the optimizer
2282: ;;- (set (cc0)
2283: ;;- (compare (const_int 2)
2284: ;;- (const_int 1)))
2285:
2286: (define_insn "cmpsi"
2287: [(set (cc0)
2288: (compare (match_operand:SI 0 "register_operand" "r")
2289: (match_operand:SI 1 "register_operand" "r")))]
2290: ""
2291: "*
2292: compare_collect (SImode, operands[0], operands[1]);
2293: return \" #\\tcmpsi\\t%0,%1\";
2294: ")
2295:
2296: ;; These patterns are hopelessly invalid, because
2297: ;; comparing subword values properly requires extending them.
2298:
2299: ;; (define_insn "cmphi"
2300: ;; [(set (cc0)
2301: ;; (compare (match_operand:HI 0 "general_operand" "r")
2302: ;; (match_operand:HI 1 "general_operand" "r")))]
2303: ;; ""
2304: ;; "*
2305: ;; compare_collect (HImode, operands[0], operands[1]);
2306: ;; return \" #\\tcmphi\\t%0,%1\";
2307: ;; ")
2308: ;;
2309: ;; (define_insn "cmpqi"
2310: ;; [(set (cc0)
2311: ;; (compare (match_operand:QI 0 "general_operand" "r")
2312: ;; (match_operand:QI 1 "general_operand" "r")))]
2313: ;; ""
2314: ;; "*
2315: ;; compare_collect (QImode, operands[0], operands[1]);
2316: ;; return \" #\\tcmpqi\\t%0,%1\";
2317: ;; ")
2318:
2319: (define_insn "cmpdf"
2320: [(set (cc0)
2321: (compare (match_operand:DF 0 "register_operand" "f")
2322: (match_operand:DF 1 "register_operand" "f")))]
2323: ""
2324: "*
2325: compare_collect (DFmode, operands[0], operands[1]);
2326: return \" #\\tcmpdf\\t%0,%1\" ;
2327: ")
2328:
2329: (define_insn "cmpsf"
2330: [(set (cc0)
2331: (compare (match_operand:SF 0 "register_operand" "f")
2332: (match_operand:SF 1 "register_operand" "f")))]
2333: ""
2334: "*
2335: compare_collect (SFmode, operands[0], operands[1]);
2336: return \" #\\tcmpsf\\t%0,%1\" ;
2337: ")
2338:
2339: (define_insn ""
2340: [(set (cc0)
2341: (match_operand:QI 0 "general_operand" "r"))]
2342: ""
2343: "*
2344: compare_collect (QImode, operands[0], gen_rtx (REG, QImode, 0));
2345: return \" #\\t (set (cc0)\\t%0)\";
2346: ")
2347:
2348: (define_insn ""
2349: [(set (cc0)
2350: (match_operand:HI 0 "general_operand" "r"))]
2351: ""
2352: "*
2353: compare_collect (HImode, operands[0], gen_rtx (REG, HImode, 0));
2354: return \" #\\t (set (cc0)\\t%0)\";
2355: ")
2356:
2357: (define_insn ""
2358: [(set (cc0)
2359: (match_operand:SI 0 "general_operand" "r"))]
2360: ""
2361: "*
2362: compare_collect (SImode, operands[0], gen_rtx (REG, SImode, 0));
2363: return \" #\\t (set (cc0)\\t%0)\";
2364: ")
2365:
2366: ;;
2367: ;; ....................
2368: ;;
2369: ;; BRANCHES
2370: ;;
2371: ;; ....................
2372:
2373: (define_insn "jump"
2374: [(set (pc)
2375: (label_ref (match_operand 0 "" "")))]
2376: ""
2377: "*
2378: {
2379: if (GET_CODE (operands[0]) == REG)
2380: return \"j\\t%%0\\t#jump %l0 (jr not asm syntax)\";
2381: else
2382: return \"j\\t%l0\\t#jump %l0\";
2383: }")
2384:
2385:
2386: (define_insn "beq"
2387: [(set (pc)
2388: (if_then_else (eq (cc0)
2389: (const_int 0))
2390: (label_ref (match_operand 0 "" ""))
2391: (pc)))]
2392: ""
2393: "*
2394: {
2395: rtx br_ops[3];
2396: enum machine_mode mode;
2397: compare_restore (br_ops, &mode, insn);
2398: br_ops[2] = operands[0];
2399: if (mode == DFmode)
2400: {
2401: output_asm_insn (\"c.eq.d\\t%0,%1\\t#beq\", br_ops);
2402: output_asm_insn (\"bc1t\\t%2\\t#beq\", br_ops);
2403: }
2404: else if (mode == SFmode)
2405: {
2406: output_asm_insn (\"c.eq.s\\t%0,%1\\t#beq\", br_ops);
2407: output_asm_insn (\"bc1t\\t%2\\t#beq\", br_ops);
2408: }
2409: else
2410: {
2411: output_asm_insn (\"beq\\t%0,%1,%2\\t#beq\", br_ops);
2412: }
2413: return \"\";
2414: }
2415: ")
2416:
2417: (define_insn "bne"
2418: [(set (pc)
2419: (if_then_else (ne (cc0)
2420: (const_int 0))
2421: (label_ref (match_operand 0 "" ""))
2422: (pc)))]
2423: ""
2424: "*
2425: {
2426: rtx br_ops[3];
2427: enum machine_mode mode;
2428: compare_restore (br_ops, &mode, insn);
2429: br_ops[2] = operands[0];
2430: if (mode == DFmode)
2431: {
2432: output_asm_insn (\"c.eq.d\\t%0,%1\\t#bne\", br_ops);
2433: output_asm_insn (\"bc1f\\t%2\\t#bne\", br_ops);
2434: }
2435: else if (mode == SFmode)
2436: {
2437: output_asm_insn (\"c.eq.s\\t%0,%1\\t#bne\", br_ops);
2438: output_asm_insn (\"bc1f\\t%2\\t#bne\", br_ops);
2439: }
2440: else
2441: {
2442: output_asm_insn (\"bne\\t%0,%1,%2\\t#bne\", br_ops);
2443: }
2444: return \"\";
2445: }
2446:
2447: ")
2448:
2449: (define_insn "bgt"
2450: [(set (pc)
2451: (if_then_else (gt (cc0)
2452: (const_int 0))
2453: (label_ref (match_operand 0 "" ""))
2454: (pc)))]
2455: ""
2456: "*
2457: {
2458: rtx br_ops[3];
2459: enum machine_mode mode;
2460: compare_restore (br_ops, &mode, insn);
2461: br_ops[2] = operands[0];
2462: if (mode == DFmode)
2463: {
2464: output_asm_insn (\"c.le.d\\t%0,%1\\t#bgt branch %0 > %1\", br_ops);
2465: output_asm_insn (\"bc1f\\t%2\\t#bgt\", br_ops);
2466: }
2467: else if (mode == SFmode)
2468: {
2469: output_asm_insn (\"c.le.s\\t%0,%1\\t#bgt branch %0 > %1\", br_ops);
2470: output_asm_insn (\"bc1f\\t%2\\t#bgt\", br_ops);
2471: }
2472: else
2473: {
2474: output_asm_insn (\"bgt\\t%0,%1,%2\\t#bgt\", br_ops);
2475: }
2476: return \"\";
2477: }
2478:
2479: ")
2480:
2481: (define_insn "blt"
2482: [(set (pc)
2483: (if_then_else (lt (cc0)
2484: (const_int 0))
2485: (label_ref (match_operand 0 "" ""))
2486: (pc)))]
2487: ""
2488: "*
2489: {
2490: rtx br_ops[3];
2491: enum machine_mode mode;
2492: compare_restore (br_ops, &mode, insn);
2493: br_ops[2] = operands[0];
2494: if (mode == DFmode)
2495: {
2496: output_asm_insn (\"c.lt.d\\t%0,%1\\t#blt\", br_ops);
2497: output_asm_insn (\"bc1t\\t%2\\t#blt\", br_ops);
2498: }
2499: else if (mode == SFmode)
2500: {
2501: output_asm_insn (\"c.lt.s\\t%0,%1\\t#blt\", br_ops);
2502: output_asm_insn (\"bc1t\\t%2\\t#blt\", br_ops);
2503: }
2504: else
2505: {
2506: output_asm_insn (\"blt\\t%0,%1,%2\\t#blt\", br_ops);
2507: }
2508: return \" #\\tblt \\t%l0\\t#blt\";
2509: }
2510: ")
2511:
2512: (define_insn "bgtu"
2513: [(set (pc)
2514: (if_then_else (gtu (cc0)
2515: (const_int 0))
2516: (label_ref (match_operand 0 "" ""))
2517: (pc)))]
2518: ""
2519: "*
2520: {
2521: rtx br_ops[3];
2522: enum machine_mode mode;
2523: compare_restore (br_ops, &mode, insn);
2524: br_ops[2] = operands[0];
2525: if (mode == DFmode)
2526: {
2527: output_asm_insn (\"c.le.d\\t%0,%1\\t#bgtu\", br_ops);
2528: output_asm_insn (\"bc1f\\t%2\\t#bgtu\", br_ops);
2529: }
2530: else if (mode == SFmode)
2531: {
2532: output_asm_insn (\"c.le.s\\t%0,%1\\t#bgtu\", br_ops);
2533: output_asm_insn (\"bc1f\\t%2\\t#bgtu\", br_ops);
2534: }
2535: else
2536: {
2537: output_asm_insn (\"bgtu\\t%0,%1,%2\\t#bgtu\", br_ops);
2538: }
2539: return \" #\\tbgtu \\t%l0\\t#bgtu\";
2540: }
2541:
2542: ")
2543:
2544: (define_insn "bltu"
2545: [(set (pc)
2546: (if_then_else (ltu (cc0)
2547: (const_int 0))
2548: (label_ref (match_operand 0 "" ""))
2549: (pc)))]
2550: ""
2551: "*
2552: {
2553: rtx br_ops[3];
2554: enum machine_mode mode;
2555: compare_restore (br_ops, &mode, insn);
2556: br_ops[2] = operands[0];
2557: if (mode == DFmode)
2558: {
2559: output_asm_insn (\"c.lt.d\\t%0,%1\\t#bltu\", br_ops);
2560: output_asm_insn (\"bc1t\\t%2\\t#bltu\", br_ops);
2561: }
2562: else if (mode == SFmode)
2563: {
2564: output_asm_insn (\"c.lt.s\\t%0,%1\\t#bltu\", br_ops);
2565: output_asm_insn (\"bc1t\\t%2\\t#bltu\", br_ops);
2566: }
2567: else
2568: {
2569: output_asm_insn (\"bltu\\t%0,%1,%2\\t#bltu\", br_ops);
2570: }
2571: return \"\";
2572: }
2573: ")
2574:
2575: (define_insn "bge"
2576: [(set (pc)
2577: (if_then_else (ge (cc0)
2578: (const_int 0))
2579: (label_ref (match_operand 0 "" ""))
2580: (pc)))]
2581: ""
2582: "*
2583: {
2584: rtx br_ops[3];
2585: enum machine_mode mode;
2586: compare_restore (br_ops, &mode, insn);
2587: br_ops[2] = operands[0];
2588: if (mode == DFmode)
2589: {
2590: output_asm_insn (\"c.lt.d\\t%0,%1\\t#bge\", br_ops);
2591: output_asm_insn (\"bc1f\\t%2\\t#bge\", br_ops);
2592: }
2593: else if (mode == SFmode)
2594: {
2595: output_asm_insn (\"c.lt.s\\t%0,%1\\t#bge\", br_ops);
2596: output_asm_insn (\"bc1f\\t%2\\t#bge\", br_ops);
2597: }
2598: else
2599: {
2600: output_asm_insn (\"bge\\t%0,%1,%2\\t#bge\", br_ops);
2601: }
2602: return \"\";
2603: }
2604: ")
2605:
2606: (define_insn "bgeu"
2607: [(set (pc)
2608: (if_then_else (geu (cc0)
2609: (const_int 0))
2610: (label_ref (match_operand 0 "" ""))
2611: (pc)))]
2612: ""
2613: "*
2614: {
2615: rtx br_ops[3];
2616: enum machine_mode mode;
2617: compare_restore (br_ops, &mode, insn);
2618: br_ops[2] = operands[0];
2619: if (mode == DFmode)
2620: {
2621: output_asm_insn (\"c.lt.d\\t%0,%1\\t#bgeu\", br_ops);
2622: output_asm_insn (\"bc1f\\t%2\\t#bgeu\", br_ops);
2623: }
2624: else if (mode == SFmode)
2625: {
2626: output_asm_insn (\"c.lt.s\\t%0,%1\\t#bgeu\", br_ops);
2627: output_asm_insn (\"bc1f\\t%2\\t#bgeu\", br_ops);
2628: }
2629: else
2630: {
2631: output_asm_insn (\"bgeu\\t%0,%1,%2\\t#bgeu\", br_ops);
2632: }
2633: return \"\";
2634: }
2635: ")
2636:
2637: (define_insn "ble"
2638: [(set (pc)
2639: (if_then_else (le (cc0)
2640: (const_int 0))
2641: (label_ref (match_operand 0 "" ""))
2642: (pc)))]
2643: ""
2644: "*
2645: {
2646: rtx br_ops[3];
2647: enum machine_mode mode;
2648: compare_restore (br_ops, &mode, insn);
2649: br_ops[2] = operands[0];
2650: if (mode == DFmode)
2651: {
2652: output_asm_insn (\"c.le.d\\t%0,%1\\t#ble\", br_ops);
2653: output_asm_insn (\"bc1t\\t%2\\t#ble\", br_ops);
2654: }
2655: else if (mode == SFmode)
2656: {
2657: output_asm_insn (\"c.le.s\\t%0,%1\\t#ble\", br_ops);
2658: output_asm_insn (\"bc1t\\t%2\\t#ble\", br_ops);
2659: }
2660: else
2661: {
2662: output_asm_insn (\"ble\\t%0,%1,%2\\t#ble\", br_ops);
2663: }
2664: return \"\";
2665: }
2666: ")
2667:
2668: (define_insn "bleu"
2669: [(set (pc)
2670: (if_then_else (leu (cc0)
2671: (const_int 0))
2672: (label_ref (match_operand 0 "" ""))
2673: (pc)))]
2674: ""
2675: "*
2676: {
2677: rtx br_ops[3];
2678: enum machine_mode mode;
2679: compare_restore (br_ops, &mode, insn);
2680: br_ops[2] = operands[0];
2681: if (mode == DFmode)
2682: {
2683: output_asm_insn (\"c.le.d\\t%0,%1\\t#ble\", br_ops);
2684: output_asm_insn (\"bc1t\\t%2\\t#ble\", br_ops);
2685: }
2686: else if (mode == SFmode)
2687: {
2688: output_asm_insn (\"c.le.s\\t%0,%1\\t#ble\", br_ops);
2689: output_asm_insn (\"bc1t\\t%2\\t#ble\", br_ops);
2690: }
2691: else
2692: {
2693: output_asm_insn (\"bleu\\t%0,%1,%2\\t#bleu\", br_ops);
2694: }
2695: return \" #\\tbleu \\t%l0\\t#bleu\";
2696: }
2697: ")
2698:
2699: (define_insn ""
2700: [(set (pc)
2701: (if_then_else (ne (cc0)
2702: (const_int 0))
2703: (pc)
2704: (label_ref (match_operand 0 "" ""))))]
2705: ""
2706: "*
2707: {
2708: rtx br_ops[3];
2709: enum machine_mode mode;
2710: compare_restore (br_ops, &mode, insn);
2711: br_ops[2] = operands[0];
2712: if (mode == DFmode)
2713: {
2714: output_asm_insn (\"c.eq.d\\t%0,%1\\t#beq\", br_ops);
2715: output_asm_insn (\"bc1t\\t%2\\t#beq\", br_ops);
2716: }
2717: else if (mode == SFmode)
2718: {
2719: output_asm_insn (\"c.eq.s\\t%0,%1\\t#beq\", br_ops);
2720: output_asm_insn (\"bc1t\\t%2\\t#beq\", br_ops);
2721: }
2722: else
2723: {
2724: output_asm_insn (\"beq\\t%0,%1,%2\\t#beq Inv.\", br_ops);
2725: }
2726: return \"\";
2727: }
2728: ")
2729:
2730: (define_insn ""
2731: [(set (pc)
2732: (if_then_else (eq (cc0)
2733: (const_int 0))
2734: (pc)
2735: (label_ref (match_operand 0 "" ""))))]
2736: ""
2737: "*
2738: {
2739: rtx br_ops[3];
2740: enum machine_mode mode;
2741: compare_restore (br_ops, &mode, insn);
2742: br_ops[2] = operands[0];
2743: if (mode == DFmode)
2744: {
2745: output_asm_insn (\"c.eq.d\\t%0,%1\\t#bne\", br_ops);
2746: output_asm_insn (\"bc1f\\t%2\\t#bne\", br_ops);
2747: }
2748: else if (mode == SFmode)
2749: {
2750: output_asm_insn (\"c.eq.s\\t%0,%1\\t#bne\", br_ops);
2751: output_asm_insn (\"bc1f\\t%2\\t#beq\", br_ops);
2752: }
2753: else
2754: {
2755: output_asm_insn (\"bne\\t%0,%1,%2\\t#bne Inv.\", br_ops);
2756: }
2757: return \"\";
2758: }
2759:
2760: ")
2761:
2762: (define_insn ""
2763: [(set (pc)
2764: (if_then_else (le (cc0)
2765: (const_int 0))
2766: (pc)
2767: (label_ref (match_operand 0 "" ""))))]
2768: ""
2769: "*
2770: {
2771: rtx br_ops[3];
2772: enum machine_mode mode;
2773: compare_restore (br_ops, &mode, insn);
2774: br_ops[2] = operands[0];
2775: if (mode == DFmode)
2776: {
2777: output_asm_insn (\"c.le.d\\t%0,%1\\t#bgt\", br_ops);
2778: output_asm_insn (\"bc1f\\t%2\\t#beq\", br_ops);
2779: }
2780: else if (mode == SFmode)
2781: {
2782: output_asm_insn (\"c.le.s\\t%0,%1\\t#bgt\", br_ops);
2783: output_asm_insn (\"bc1f\\t%2\\t#beq\", br_ops);
2784: }
2785: else
2786: {
2787: output_asm_insn (\"bgt\\t%0,%1,%2\\t#bgt Inv.\", br_ops);
2788: }
2789: return \"\";
2790: }
2791: ")
2792:
2793: (define_insn ""
2794: [(set (pc)
2795: (if_then_else (leu (cc0)
2796: (const_int 0))
2797: (pc)
2798: (label_ref (match_operand 0 "" ""))))]
2799: ""
2800: "*
2801: {
2802: rtx br_ops[3];
2803: enum machine_mode mode;
2804: compare_restore (br_ops, &mode, insn);
2805: br_ops[2] = operands[0];
2806: if (mode == DFmode)
2807: {
2808: output_asm_insn (\"c.le.d\\t%0,%1\\t#bgt\", br_ops);
2809: output_asm_insn (\"bc1f\\t%2\\t#beq\", br_ops);
2810: }
2811: else if (mode == SFmode)
2812: {
2813: output_asm_insn (\"c.le.s\\t%0,%1\\t#bgt\", br_ops);
2814: output_asm_insn (\"bc1f\\t%2\\t#beq\", br_ops);
2815: }
2816: else
2817: {
2818: output_asm_insn (\"bgtu\\t%0,%1,%2\\t#bgtu Inv.\", br_ops);
2819: }
2820: return \" #\\tbgtu \\t%l0\\t#bgtu\";
2821: }
2822: ")
2823:
2824: (define_insn ""
2825: [(set (pc)
2826: (if_then_else (ge (cc0)
2827: (const_int 0))
2828: (pc)
2829: (label_ref (match_operand 0 "" ""))))]
2830: ""
2831: "*
2832: {
2833: rtx br_ops[3];
2834: enum machine_mode mode;
2835: compare_restore (br_ops, &mode, insn);
2836: br_ops[2] = operands[0];
2837: if (mode == DFmode)
2838: {
2839: output_asm_insn (\"c.lt.d\\t%0,%1\\t#blt\", br_ops);
2840: output_asm_insn (\"bc1t\\t%2\\t#beq\", br_ops);
2841: }
2842: else if (mode == SFmode)
2843: {
2844: output_asm_insn (\"c.lt.s\\t%0,%1\\t#blt\", br_ops);
2845: output_asm_insn (\"bc1t\\t%2\\t#beq\", br_ops);
2846: }
2847: else
2848: {
2849: output_asm_insn (\"blt\\t%0,%1,%2\\t#blt Inv.\", br_ops);
2850: }
2851: return \"\";
2852: }
2853: ")
2854:
2855: (define_insn ""
2856: [(set (pc)
2857: (if_then_else (geu (cc0)
2858: (const_int 0))
2859: (pc)
2860: (label_ref (match_operand 0 "" ""))))]
2861: ""
2862: "*
2863: {
2864: rtx br_ops[3];
2865: enum machine_mode mode;
2866: compare_restore (br_ops, &mode, insn);
2867: br_ops[2] = operands[0];
2868: if (mode == DFmode)
2869: {
2870: output_asm_insn (\"c.lt.d\\t%0,%1\\t#bltu\", br_ops);
2871: output_asm_insn (\"bc1t\\t%2\\t#bltu\", br_ops);
2872: }
2873: else if (mode == SFmode)
2874: {
2875: output_asm_insn (\"c.lt.s\\t%0,%1\\t#bltu\", br_ops);
2876: output_asm_insn (\"bc1t\\t%2\\t#bltu\", br_ops);
2877: }
2878: else
2879: {
2880: output_asm_insn (\"bltu\\t%0,%1,%2\\t#bltu Inv.\", br_ops);
2881: }
2882: return \" #\\tbltu \\t%l0\\t#bltu\";
2883: }
2884: ")
2885:
2886: (define_insn ""
2887: [(set (pc)
2888: (if_then_else (lt (cc0)
2889: (const_int 0))
2890: (pc)
2891: (label_ref (match_operand 0 "" ""))))]
2892: ""
2893: "*
2894: {
2895: rtx br_ops[3];
2896: enum machine_mode mode;
2897: compare_restore (br_ops, &mode, insn);
2898: br_ops[2] = operands[0];
2899: if (mode == DFmode)
2900: {
2901: output_asm_insn (\"c.lt.d\\t%0,%1\\t#bge\", br_ops);
2902: output_asm_insn (\"bc1f\\t%2\\t#bge (DF) Inv.\", br_ops);
2903: }
2904: else if (mode == SFmode)
2905: {
2906: output_asm_insn (\"c.lt.s\\t%0,%1\\t#bge\", br_ops);
2907: output_asm_insn (\"bc1f\\t%2\\t#bge (SF) Inv.\", br_ops);
2908: }
2909: else
2910: {
2911: output_asm_insn (\"bge\\t%0,%1,%2\\t#bge Inv.\", br_ops);
2912: }
2913: return \"\";
2914: }
2915: ")
2916:
2917: (define_insn ""
2918: [(set (pc)
2919: (if_then_else (ltu (cc0)
2920: (const_int 0))
2921: (pc)
2922: (label_ref (match_operand 0 "" ""))))]
2923: ""
2924: "*
2925: {
2926: rtx br_ops[3];
2927: enum machine_mode mode;
2928: compare_restore (br_ops, &mode, insn);
2929: br_ops[2] = operands[0];
2930: if (mode == DFmode)
2931: {
2932: output_asm_insn (\"c.lt.d\\t%0,%1\\t#bge\", br_ops);
2933: output_asm_insn (\"bc1f\\t%2\\t#bgeu (DF) Inv.\", br_ops);
2934: }
2935: else if (mode == SFmode)
2936: {
2937: output_asm_insn (\"c.lt.s\\t%0,%1\\t#bge\", br_ops);
2938: output_asm_insn (\"bc1f\\t%2\\t#bgeu (SF )Inv.\", br_ops);
2939: }
2940: else
2941: {
2942: output_asm_insn (\"bgeu\\t%0,%1,%2\\t#bgeu Inv.\", br_ops);
2943: }
2944: return \" #\\tbgeu \\t%l0\\t#bgeu\";
2945: }
2946: ")
2947:
2948: (define_insn ""
2949: [(set (pc)
2950: (if_then_else (gt (cc0)
2951: (const_int 0))
2952: (pc)
2953: (label_ref (match_operand 0 "" ""))))]
2954: ""
2955: "*
2956: {
2957: rtx br_ops[3];
2958: enum machine_mode mode;
2959: compare_restore (br_ops, &mode, insn);
2960: br_ops[2] = operands[0];
2961: if (mode == DFmode)
2962: {
2963: output_asm_insn (\"c.le.d\\t%0,%1\\t#ble\", br_ops);
2964: output_asm_insn (\"bc1t\\t%2\\t#ble\", br_ops);
2965: }
2966: else if (mode == SFmode)
2967: {
2968: output_asm_insn (\"c.le.s\\t%0,%1\\t#ble\", br_ops);
2969: output_asm_insn (\"bc1t\\t%2\\t#ble\", br_ops);
2970: }
2971: else
2972: {
2973: output_asm_insn (\"ble\\t%0,%1,%2\\t#ble Inv.\", br_ops);
2974: }
2975: return \"\";
2976: }
2977: ")
2978:
2979: (define_insn ""
2980: [(set (pc)
2981: (if_then_else (gtu (cc0)
2982: (const_int 0))
2983: (pc)
2984: (label_ref (match_operand 0 "" ""))))]
2985: ""
2986: "*
2987: {
2988: rtx br_ops[3];
2989: enum machine_mode mode;
2990: compare_restore (br_ops, &mode, insn);
2991: br_ops[2] = operands[0];
2992: if (mode == DFmode)
2993: {
2994: output_asm_insn (\"c.le.d\\t%0,%1\\t#bleu\", br_ops);
2995: output_asm_insn (\"bc1t\\t%2\\t#bleu\", br_ops);
2996: }
2997: else if (mode == SFmode)
2998: {
2999: output_asm_insn (\"c.le.s\\t%0,%1\\t#bleu\", br_ops);
3000: output_asm_insn (\"bc1t\\t%2\\t#bleu\", br_ops);
3001: }
3002: else
3003: {
3004: output_asm_insn (\"bleu\\t%0,%1,%2\\t#bleu Inv.\", br_ops);
3005: }
3006: return \"\";
3007: }
3008: ")
3009:
3010: (define_insn "tablejump"
3011: [(set (pc)
3012: (match_operand:SI 0 "general_operand" "r"))
3013: (use (label_ref (match_operand 1 "" "")))]
3014: ""
3015: "j\\t%0\\t# tablejump, label %l1\\t (jr not asm syntax)")
3016:
3017: ;;
3018: ;; ....................
3019: ;;
3020: ;; LINKAGE
3021: ;;
3022: ;; ....................
3023:
3024: (define_insn "call"
3025: [(call (match_operand 0 "general_operand" "g")
3026: (match_operand 1 "general_operand" "g"))
3027: (clobber (reg:SI 31))]
3028: ""
3029: "*
3030: {
3031: if (GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
3032: return \"jal\\t%0\\t# call with %1 arguments\";
3033: else
3034: {
3035: operands[0] = XEXP (operands[0], 0);
3036: return \"jal\\t$31,%0\\t# call with %1 arguments (reg)\";
3037: }
3038: }" )
3039:
3040:
3041: (define_expand "call_value"
3042: [(set (match_operand 0 "" "=rf")
3043: (call (match_operand:SI 1 "memory_operand" "m")
3044: (match_operand 2 "" "i")))
3045: (clobber (reg:SI 31))]
3046: ;; operand 3 is next_arg_register
3047: ""
3048: "
3049: {
3050: rtx fn_rtx, nregs_rtx;
3051: rtvec vec;
3052:
3053: fn_rtx = operands[1];
3054:
3055: nregs_rtx = const0_rtx;
3056:
3057:
3058: vec = gen_rtvec (2,
3059: gen_rtx (SET, VOIDmode, operands[0],
3060: gen_rtx (CALL, VOIDmode, fn_rtx, nregs_rtx)),
3061: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)));
3062:
3063: emit_call_insn (gen_rtx (PARALLEL, VOIDmode, vec));
3064: DONE;
3065: }")
3066:
3067:
3068: (define_insn ""
3069: [(set (match_operand 0 "general_operand" "=g,f")
3070: (call (match_operand 1 "general_operand" "g,g")
3071: (match_operand 2 "general_operand" "g,g")))
3072: (clobber (match_operand 3 "general_operand" "g,g"))]
3073: ""
3074: "*
3075: {
3076: if (GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
3077: return \"jal\\t%1\\t# call %1 regle 2-call (VOIDmode)\";
3078: else
3079: {
3080: operands[1] = XEXP (operands[1], 0);
3081: return \"jal\\t$31,%1\\t# call %1 regle 2-call (VOIDmode, reg)\";
3082: }
3083: }")
3084:
3085: (define_insn "nop"
3086: [(const_int 0)]
3087: ""
3088: "nop")
3089:
3090: (define_expand "probe"
3091: [(set (reg:SI 29) (minus:SI (reg:SI 29) (const_int 4)))
3092: (set (mem:SI (reg:SI 29)) (const_int 0))
3093: (set (reg:SI 29) (plus:SI (reg:SI 29) (const_int 4)))]
3094: ""
3095: "")
3096:
3097: ;;
3098: ;;- Local variables:
3099: ;;- mode:emacs-lisp
3100: ;;- comment-start: ";;- "
3101: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
3102: ;;- eval: (modify-syntax-entry ?[ "(]")
3103: ;;- eval: (modify-syntax-entry ?] ")[")
3104: ;;- eval: (modify-syntax-entry ?{ "(}")
3105: ;;- eval: (modify-syntax-entry ?} "){")
3106: ;;- End:
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.