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1.1 root 1: ;; Mips.md Machine Description for MIPS based processors
2: ;; Contributed by A. Lichnewsky, [email protected]
3: ;; Changes by Michael Meissner, [email protected]
1.1.1.3 ! root 4: ;; 64 bit r4000 support by Ian Lance Taylor, [email protected], and
! 5: ;; Brendan Eich, [email protected].
! 6: ;; Copyright (C) 1989, 1990, 1991, 1992, 1993 Free Software Foundation, Inc.
1.1 root 7:
8: ;; This file is part of GNU CC.
9:
10: ;; GNU CC is free software; you can redistribute it and/or modify
11: ;; it under the terms of the GNU General Public License as published by
12: ;; the Free Software Foundation; either version 2, or (at your option)
13: ;; any later version.
14:
15: ;; GNU CC is distributed in the hope that it will be useful,
16: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
17: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18: ;; GNU General Public License for more details.
19:
20: ;; You should have received a copy of the GNU General Public License
21: ;; along with GNU CC; see the file COPYING. If not, write to
22: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23:
24:
25:
26: ;; ....................
27: ;;
28: ;; Attributes
29: ;;
30: ;; ....................
31:
32: ;; Classification of each insn.
33: ;; branch conditional branch
34: ;; jump unconditional jump
35: ;; call unconditional call
36: ;; load load instruction(s)
37: ;; store store instruction(s)
38: ;; move data movement within same register set
39: ;; xfer transfer to/from coprocessor
40: ;; hilo transfer of hi/lo registers
41: ;; arith integer arithmetic instruction
42: ;; darith double precision integer arithmetic instructions
43: ;; imul integer multiply
44: ;; idiv integer divide
45: ;; icmp integer compare
46: ;; fadd floating point add/subtract
47: ;; fmul floating point multiply
48: ;; fdiv floating point divide
49: ;; fabs floating point absolute value
50: ;; fneg floating point negation
51: ;; fcmp floating point compare
52: ;; fcvt floating point convert
53: ;; fsqrt floating point square root
54: ;; multi multiword sequence (or user asm statements)
55: ;; nop no operation
56:
57: (define_attr "type"
58: "unknown,branch,jump,call,load,store,move,xfer,hilo,arith,darith,imul,idiv,icmp,fadd,fmul,fdiv,fabs,fneg,fcmp,fcvt,fsqrt,multi,nop"
59: (const_string "unknown"))
60:
61: ;; Main data type used by the insn
62: (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW" (const_string "unknown"))
63:
64: ;; # instructions (4 bytes each)
65: (define_attr "length" "" (const_int 1))
66:
67: ;; whether or not an instruction has a mandatory delay slot
68: (define_attr "dslot" "no,yes"
69: (if_then_else (eq_attr "type" "branch,jump,call,load,xfer,hilo,fcmp")
70: (const_string "yes")
71: (const_string "no")))
72:
73: ;; Attribute describing the processor. This attribute must match exactly
74: ;; with the processor_type enumeration in mips.h.
75:
76: ;; Attribute describing the processor
77: ;; (define_attr "cpu" "default,r3000,r6000,r4000"
78: ;; (const
79: ;; (cond [(eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R3000")) (const_string "r3000")
80: ;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R4000")) (const_string "r4000")
81: ;; (eq (symbol_ref "mips_cpu") (symbol_ref "PROCESSOR_R6000")) (const_string "r6000")]
82: ;; (const_string "default"))))
83:
1.1.1.3 ! root 84: (define_attr "cpu" "default,r3000,r6000,r4000,r4600"
1.1 root 85: (const (symbol_ref "mips_cpu_attr")))
86:
87: ;; Attribute defining whether or not we can use the branch-likely instructions
88: ;; (MIPS ISA level 2)
89:
90: (define_attr "branch_likely" "no,yes"
91: (const
92: (if_then_else (ge (symbol_ref "mips_isa") (const_int 2))
93: (const_string "yes")
94: (const_string "no"))))
95:
96:
97: ;; Describe a user's asm statement.
98: (define_asm_attributes
99: [(set_attr "type" "multi")])
100:
1.1.1.2 root 101: ;; whether or not generating calls to position independent functions
102: (define_attr "abicalls" "no,yes"
103: (const (symbol_ref "mips_abicalls_attr")))
104:
1.1 root 105:
106:
107: ;; .........................
108: ;;
109: ;; Delay slots, can't describe load/fcmp/xfer delay slots here
110: ;;
111: ;; .........................
112:
113: (define_delay (eq_attr "type" "branch")
114: [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
115: (nil)
116: (and (eq_attr "branch_likely" "yes") (and (eq_attr "dslot" "no") (eq_attr "length" "1")))])
117:
1.1.1.2 root 118: (define_delay (eq_attr "type" "jump")
119: [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
120: (nil)
121: (nil)])
122:
123: (define_delay (and (eq_attr "type" "call") (eq_attr "abicalls" "no"))
1.1 root 124: [(and (eq_attr "dslot" "no") (eq_attr "length" "1"))
125: (nil)
126: (nil)])
127:
128:
129:
130: ;; .........................
131: ;;
132: ;; Functional units
133: ;;
134: ;; .........................
135:
136: ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
137: ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
138:
139: ;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
140:
141: (define_function_unit "memory" 1 0
1.1.1.3 ! root 142: (and (eq_attr "type" "load") (eq_attr "cpu" "!r3000,r4600"))
1.1 root 143: 3 0)
144:
145: (define_function_unit "memory" 1 0
1.1.1.3 ! root 146: (and (eq_attr "type" "load") (eq_attr "cpu" "r3000,r4600"))
1.1 root 147: 2 0)
148:
149: (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
150:
151: (define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
152:
1.1.1.3 ! root 153: (define_function_unit "imuldiv" 1 0
! 154: (eq_attr "type" "hilo")
! 155: 1 3)
! 156:
! 157: (define_function_unit "imuldiv" 1 0
! 158: (and (eq_attr "type" "imul") (eq_attr "cpu" "!r3000,r4000,r4600"))
! 159: 17 17)
1.1 root 160:
1.1.1.3 ! root 161: (define_function_unit "imuldiv" 1 0
1.1 root 162: (and (eq_attr "type" "imul") (eq_attr "cpu" "r3000"))
1.1.1.3 ! root 163: 12 12)
1.1 root 164:
1.1.1.3 ! root 165: (define_function_unit "imuldiv" 1 0
! 166: (and (eq_attr "type" "imul") (eq_attr "cpu" "r4000,r4600"))
! 167: 10 10)
1.1 root 168:
1.1.1.3 ! root 169: (define_function_unit "imuldiv" 1 0
! 170: (and (eq_attr "type" "idiv") (eq_attr "cpu" "!r3000,r4000,r4600"))
! 171: 38 38)
! 172:
! 173: (define_function_unit "imuldiv" 1 0
1.1 root 174: (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3000"))
1.1.1.3 ! root 175: 35 35)
! 176:
! 177: (define_function_unit "imuldiv" 1 0
! 178: (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600"))
! 179: 42 42)
1.1 root 180:
1.1.1.3 ! root 181: (define_function_unit "imuldiv" 1 0
1.1 root 182: (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
1.1.1.3 ! root 183: 69 69)
! 184:
! 185: (define_function_unit "adder" 1 1
! 186: (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3000,r6000"))
! 187: 3 0)
! 188:
! 189: (define_function_unit "adder" 1 1
! 190: (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3000,r6000"))
! 191: 2 0)
1.1 root 192:
193: (define_function_unit "adder" 1 1
194: (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3000,r6000"))
195: 4 0)
196:
197: (define_function_unit "adder" 1 1
198: (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3000"))
199: 2 0)
200:
201: (define_function_unit "adder" 1 1
202: (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
203: 3 0)
204:
205: (define_function_unit "adder" 1 1
1.1.1.3 ! root 206: (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "!r3000,r4600"))
1.1 root 207: 2 0)
208:
209: (define_function_unit "adder" 1 1
1.1.1.3 ! root 210: (and (eq_attr "type" "fabs,fneg") (eq_attr "cpu" "r3000,r4600"))
1.1 root 211: 1 0)
212:
213: (define_function_unit "mult" 1 1
1.1.1.3 ! root 214: (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r3000,r6000,r4600")))
1.1 root 215: 7 0)
216:
217: (define_function_unit "mult" 1 1
218: (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000")))
219: 4 0)
220:
221: (define_function_unit "mult" 1 1
222: (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
223: 5 0)
224:
225: (define_function_unit "mult" 1 1
1.1.1.3 ! root 226: (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600")))
! 227: 8 0)
! 228:
! 229: (define_function_unit "mult" 1 1
1.1 root 230: (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r6000")))
231: 8 0)
232:
233: (define_function_unit "mult" 1 1
234: (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000")))
235: 5 0)
236:
237: (define_function_unit "mult" 1 1
238: (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
239: 6 0)
240:
241: (define_function_unit "divide" 1 1
1.1.1.3 ! root 242: (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r3000,r6000,r4600")))
1.1 root 243: 23 0)
244:
245: (define_function_unit "divide" 1 1
246: (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3000")))
247: 12 0)
248:
249: (define_function_unit "divide" 1 1
250: (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
251: 15 0)
252:
253: (define_function_unit "divide" 1 1
1.1.1.3 ! root 254: (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600")))
! 255: 32 0)
! 256:
! 257: (define_function_unit "divide" 1 1
! 258: (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3000,r6000,r4600")))
1.1 root 259: 36 0)
260:
261: (define_function_unit "divide" 1 1
262: (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3000")))
263: 19 0)
264:
265: (define_function_unit "divide" 1 1
266: (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
267: 16 0)
268:
1.1.1.3 ! root 269: (define_function_unit "divide" 1 1
! 270: (and (eq_attr "type" "fdiv") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600")))
! 271: 61 0)
! 272:
! 273: ;;; ??? Is this number right?
! 274: (define_function_unit "divide" 1 1
! 275: (and (eq_attr "type" "fsqrt") (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600")))
! 276: 54 0)
! 277: (define_function_unit "divide" 1 1
! 278: (and (eq_attr "type" "fsqrt") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600")))
! 279: 31 0)
! 280:
! 281: ;;; ??? Is this number right?
! 282: (define_function_unit "divide" 1 1
! 283: (and (eq_attr "type" "fsqrt") (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600")))
! 284: 112 0)
! 285: (define_function_unit "divide" 1 1
! 286: (and (eq_attr "type" "fsqrt") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600")))
! 287: 60 0)
1.1 root 288:
289:
290: ;; The following functional units do not use the cpu type, and use
291: ;; much less memory in genattrtab.c.
292:
293: ;; (define_function_unit "memory" 1 0 (eq_attr "type" "load") 3 0)
294: ;; (define_function_unit "memory" 1 0 (eq_attr "type" "store") 1 0)
295: ;;
296: ;; (define_function_unit "fp_comp" 1 0 (eq_attr "type" "fcmp") 2 0)
297: ;;
298: ;; (define_function_unit "transfer" 1 0 (eq_attr "type" "xfer") 2 0)
299: ;; (define_function_unit "transfer" 1 0 (eq_attr "type" "hilo") 3 0)
300: ;;
301: ;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "imul") 17 0)
302: ;; (define_function_unit "imuldiv" 1 1 (eq_attr "type" "idiv") 38 0)
303: ;;
304: ;; (define_function_unit "adder" 1 1 (eq_attr "type" "fadd") 4 0)
305: ;; (define_function_unit "adder" 1 1 (eq_attr "type" "fabs,fneg") 2 0)
306: ;;
307: ;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "SF")) 7 0)
308: ;; (define_function_unit "mult" 1 1 (and (eq_attr "type" "fmul") (eq_attr "mode" "DF")) 8 0)
309: ;;
310: ;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "SF")) 23 0)
311: ;; (define_function_unit "divide" 1 1 (and (eq_attr "type" "fdiv") (eq_attr "mode" "DF")) 36 0)
312: ;;
313: ;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "SF")) 54 0)
314: ;; (define_function_unit "sqrt" 1 1 (and (eq_attr "type" "fsqrt") (eq_attr "mode" "DF")) 112 0)
315:
316:
317: ;;
318: ;; ....................
319: ;;
320: ;; ADDITION
321: ;;
322: ;; ....................
323: ;;
324:
325: (define_insn "adddf3"
326: [(set (match_operand:DF 0 "register_operand" "=f")
327: (plus:DF (match_operand:DF 1 "register_operand" "f")
328: (match_operand:DF 2 "register_operand" "f")))]
329: "TARGET_HARD_FLOAT"
330: "add.d\\t%0,%1,%2"
331: [(set_attr "type" "fadd")
332: (set_attr "mode" "DF")
333: (set_attr "length" "1")])
334:
335: (define_insn "addsf3"
336: [(set (match_operand:SF 0 "register_operand" "=f")
337: (plus:SF (match_operand:SF 1 "register_operand" "f")
338: (match_operand:SF 2 "register_operand" "f")))]
339: "TARGET_HARD_FLOAT"
340: "add.s\\t%0,%1,%2"
341: [(set_attr "type" "fadd")
342: (set_attr "mode" "SF")
343: (set_attr "length" "1")])
344:
345: (define_expand "addsi3"
346: [(set (match_operand:SI 0 "register_operand" "=d")
347: (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
348: (match_operand:SI 2 "arith_operand" "dI")))]
349: ""
350: "
351: {
352: if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768)
353: operands[2] = force_reg (SImode, operands[2]);
354: }")
355:
356: (define_insn "addsi3_internal"
357: [(set (match_operand:SI 0 "register_operand" "=d")
358: (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
359: (match_operand:SI 2 "arith_operand" "dI")))]
360: "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768"
1.1.1.3 ! root 361: "addu\\t%0,%z1,%2"
1.1 root 362: [(set_attr "type" "arith")
363: (set_attr "mode" "SI")
364: (set_attr "length" "1")])
365:
366: (define_expand "adddi3"
367: [(parallel [(set (match_operand:DI 0 "register_operand" "")
368: (plus:DI (match_operand:DI 1 "register_operand" "")
369: (match_operand:DI 2 "arith_operand" "")))
370: (clobber (match_dup 3))])]
1.1.1.3 ! root 371: "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
1.1 root 372: "
373: {
374: if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768)
1.1.1.2 root 375: operands[2] = force_reg (DImode, operands[2]);
1.1 root 376:
1.1.1.3 ! root 377: if (TARGET_64BIT)
! 378: {
! 379: emit_insn (gen_adddi3_internal_3 (operands[0], operands[1],
! 380: operands[2]));
! 381: DONE;
! 382: }
! 383:
1.1 root 384: operands[3] = gen_reg_rtx (SImode);
385: }")
386:
387: (define_insn "adddi3_internal_1"
388: [(set (match_operand:DI 0 "register_operand" "=d,&d")
389: (plus:DI (match_operand:DI 1 "register_operand" "0,d")
390: (match_operand:DI 2 "register_operand" "d,d")))
391: (clobber (match_operand:SI 3 "register_operand" "=d,d"))]
1.1.1.3 ! root 392: "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
1.1 root 393: "*
394: {
395: return (REGNO (operands[0]) == REGNO (operands[1])
396: && REGNO (operands[0]) == REGNO (operands[2]))
397: ? \"srl\\t%3,%L0,31\;sll\\t%M0,%M0,1\;sll\\t%L0,%L1,1\;addu\\t%M0,%M0,%3\"
398: : \"addu\\t%L0,%L1,%L2\;sltu\\t%3,%L0,%L2\;addu\\t%M0,%M1,%M2\;addu\\t%M0,%M0,%3\";
399: }"
400: [(set_attr "type" "darith")
401: (set_attr "mode" "DI")
402: (set_attr "length" "4")])
403:
404: (define_split
405: [(set (match_operand:DI 0 "register_operand" "")
406: (plus:DI (match_operand:DI 1 "register_operand" "")
407: (match_operand:DI 2 "register_operand" "")))
408: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 409: "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 410: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
411: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
412: && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
413: && (REGNO (operands[0]) != REGNO (operands[1])
414: || REGNO (operands[0]) != REGNO (operands[2]))"
415:
416: [(set (subreg:SI (match_dup 0) 0)
417: (plus:SI (subreg:SI (match_dup 1) 0)
418: (subreg:SI (match_dup 2) 0)))
419:
420: (set (match_dup 3)
421: (ltu:SI (subreg:SI (match_dup 0) 0)
422: (subreg:SI (match_dup 2) 0)))
423:
424: (set (subreg:SI (match_dup 0) 1)
425: (plus:SI (subreg:SI (match_dup 1) 1)
426: (subreg:SI (match_dup 2) 1)))
427:
428: (set (subreg:SI (match_dup 0) 1)
429: (plus:SI (subreg:SI (match_dup 0) 1)
430: (match_dup 3)))]
431: "")
432:
433: (define_split
434: [(set (match_operand:DI 0 "register_operand" "")
435: (plus:DI (match_operand:DI 1 "register_operand" "")
436: (match_operand:DI 2 "register_operand" "")))
437: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 438: "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 439: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
440: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
441: && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))
442: && (REGNO (operands[0]) != REGNO (operands[1])
443: || REGNO (operands[0]) != REGNO (operands[2]))"
444:
445: [(set (subreg:SI (match_dup 0) 1)
446: (plus:SI (subreg:SI (match_dup 1) 1)
447: (subreg:SI (match_dup 2) 1)))
448:
449: (set (match_dup 3)
450: (ltu:SI (subreg:SI (match_dup 0) 1)
451: (subreg:SI (match_dup 2) 1)))
452:
453: (set (subreg:SI (match_dup 0) 0)
454: (plus:SI (subreg:SI (match_dup 1) 0)
455: (subreg:SI (match_dup 2) 0)))
456:
457: (set (subreg:SI (match_dup 0) 0)
458: (plus:SI (subreg:SI (match_dup 0) 0)
459: (match_dup 3)))]
460: "")
461:
462: (define_insn "adddi3_internal_2"
463: [(set (match_operand:DI 0 "register_operand" "=d,d,d")
464: (plus:DI (match_operand:DI 1 "register_operand" "%d,%d,%d")
465: (match_operand:DI 2 "small_int" "P,J,N")))
466: (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
1.1.1.3 ! root 467: "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && INTVAL (operands[2]) != -32768"
1.1 root 468: "@
469: addu\\t%L0,%L1,%2\;sltu\\t%3,%L0,%2\;addu\\t%M0,%M1,%3
470: move\\t%L0,%L1\;move\\t%M0,%M1
471: subu\\t%L0,%L1,%n2\;sltu\\t%3,%L0,%2\;subu\\t%M0,%M1,1\;addu\\t%M0,%M0,%3"
472: [(set_attr "type" "darith")
473: (set_attr "mode" "DI")
474: (set_attr "length" "3,2,4")])
475:
476: (define_split
477: [(set (match_operand:DI 0 "register_operand" "")
478: (plus:DI (match_operand:DI 1 "register_operand" "")
479: (match_operand:DI 2 "small_int" "")))
480: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 481: "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 482: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
483: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
484: && INTVAL (operands[2]) > 0"
485:
486: [(set (subreg:SI (match_dup 0) 0)
487: (plus:SI (subreg:SI (match_dup 1) 0)
488: (match_dup 2)))
489:
490: (set (match_dup 3)
491: (ltu:SI (subreg:SI (match_dup 0) 0)
492: (match_dup 2)))
493:
494: (set (subreg:SI (match_dup 0) 1)
495: (plus:SI (subreg:SI (match_dup 1) 1)
496: (match_dup 3)))]
497: "")
498:
499: (define_split
500: [(set (match_operand:DI 0 "register_operand" "")
501: (plus:DI (match_operand:DI 1 "register_operand" "")
502: (match_operand:DI 2 "small_int" "")))
503: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 504: "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 505: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
506: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
507: && INTVAL (operands[2]) > 0"
508:
509: [(set (subreg:SI (match_dup 0) 1)
510: (plus:SI (subreg:SI (match_dup 1) 1)
511: (match_dup 2)))
512:
513: (set (match_dup 3)
514: (ltu:SI (subreg:SI (match_dup 0) 1)
515: (match_dup 2)))
516:
517: (set (subreg:SI (match_dup 0) 0)
518: (plus:SI (subreg:SI (match_dup 1) 0)
519: (match_dup 3)))]
520: "")
1.1.1.3 ! root 521:
! 522: (define_insn "adddi3_internal_3"
! 523: [(set (match_operand:DI 0 "register_operand" "=d")
! 524: (plus:DI (match_operand:DI 1 "reg_or_0_operand" "dJ")
! 525: (match_operand:DI 2 "arith_operand" "dI")))]
! 526: "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
! 527: "*
! 528: {
! 529: return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
! 530: ? \"dsubu\\t%0,%z1,%n2\"
! 531: : \"daddu\\t%0,%z1,%2\";
! 532: }"
! 533: [(set_attr "type" "darith")
! 534: (set_attr "mode" "DI")
! 535: (set_attr "length" "1")])
! 536:
! 537:
! 538: (define_insn "addsi3_internal_2"
! 539: [(set (match_operand:DI 0 "register_operand" "=d")
! 540: (sign_extend:DI (plus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
! 541: (match_operand:SI 2 "arith_operand" "dI"))))]
! 542: "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
! 543: "*
! 544: {
! 545: return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
! 546: ? \"subu\\t%0,%z1,%n2\"
! 547: : \"addu\\t%0,%z1,%2\";
! 548: }"
! 549: [(set_attr "type" "arith")
! 550: (set_attr "mode" "SI")
! 551: (set_attr "length" "1")])
! 552:
1.1 root 553:
554: ;;
555: ;; ....................
556: ;;
557: ;; SUBTRACTION
558: ;;
559: ;; ....................
560: ;;
561:
562: (define_insn "subdf3"
563: [(set (match_operand:DF 0 "register_operand" "=f")
564: (minus:DF (match_operand:DF 1 "register_operand" "f")
565: (match_operand:DF 2 "register_operand" "f")))]
566: "TARGET_HARD_FLOAT"
567: "sub.d\\t%0,%1,%2"
568: [(set_attr "type" "fadd")
569: (set_attr "mode" "DF")
570: (set_attr "length" "1")])
571:
572: (define_insn "subsf3"
573: [(set (match_operand:SF 0 "register_operand" "=f")
574: (minus:SF (match_operand:SF 1 "register_operand" "f")
575: (match_operand:SF 2 "register_operand" "f")))]
576: "TARGET_HARD_FLOAT"
577: "sub.s\\t%0,%1,%2"
578: [(set_attr "type" "fadd")
579: (set_attr "mode" "SF")
580: (set_attr "length" "1")])
581:
582: (define_expand "subsi3"
583: [(set (match_operand:SI 0 "register_operand" "=d")
584: (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
585: (match_operand:SI 2 "arith_operand" "dI")))]
586: ""
587: "
588: {
589: if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == -32768)
590: operands[2] = force_reg (SImode, operands[2]);
591: }")
592:
593: (define_insn "subsi3_internal"
594: [(set (match_operand:SI 0 "register_operand" "=d")
595: (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
596: (match_operand:SI 2 "arith_operand" "dI")))]
597: "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768"
1.1.1.3 ! root 598: "subu\\t%0,%z1,%2"
1.1 root 599: [(set_attr "type" "arith")
600: (set_attr "mode" "SI")
601: (set_attr "length" "1")])
602:
603: (define_expand "subdi3"
604: [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
605: (minus:DI (match_operand:DI 1 "register_operand" "d")
606: (match_operand:DI 2 "register_operand" "d")))
607: (clobber (match_dup 3))])]
1.1.1.3 ! root 608: "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
! 609: "
! 610: {
! 611: if (TARGET_64BIT)
! 612: {
! 613: emit_insn (gen_subdi3_internal_3 (operands[0], operands[1],
! 614: operands[2]));
! 615: DONE;
! 616: }
! 617:
! 618: operands[3] = gen_reg_rtx (SImode);
! 619: }")
1.1 root 620:
621: (define_insn "subdi3_internal"
622: [(set (match_operand:DI 0 "register_operand" "=d")
623: (minus:DI (match_operand:DI 1 "register_operand" "d")
624: (match_operand:DI 2 "register_operand" "d")))
625: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 626: "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
1.1 root 627: "sltu\\t%3,%L1,%L2\;subu\\t%L0,%L1,%L2\;subu\\t%M0,%M1,%M2\;subu\\t%M0,%M0,%3"
628: [(set_attr "type" "darith")
629: (set_attr "mode" "DI")
630: (set_attr "length" "4")])
631:
632: (define_split
633: [(set (match_operand:DI 0 "register_operand" "")
634: (minus:DI (match_operand:DI 1 "register_operand" "")
635: (match_operand:DI 2 "register_operand" "")))
636: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 637: "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 638: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
639: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
640: && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
641:
642: [(set (match_dup 3)
643: (ltu:SI (subreg:SI (match_dup 1) 0)
644: (subreg:SI (match_dup 2) 0)))
645:
646: (set (subreg:SI (match_dup 0) 0)
647: (minus:SI (subreg:SI (match_dup 1) 0)
648: (subreg:SI (match_dup 2) 0)))
649:
650: (set (subreg:SI (match_dup 0) 1)
651: (minus:SI (subreg:SI (match_dup 1) 1)
652: (subreg:SI (match_dup 2) 1)))
653:
654: (set (subreg:SI (match_dup 0) 1)
655: (minus:SI (subreg:SI (match_dup 0) 1)
656: (match_dup 3)))]
657: "")
658:
659: (define_split
660: [(set (match_operand:DI 0 "register_operand" "")
661: (minus:DI (match_operand:DI 1 "register_operand" "")
662: (match_operand:DI 2 "register_operand" "")))
663: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 664: "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 665: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
666: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
667: && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
668:
669: [(set (match_dup 3)
670: (ltu:SI (subreg:SI (match_dup 1) 1)
671: (subreg:SI (match_dup 2) 1)))
672:
673: (set (subreg:SI (match_dup 0) 1)
674: (minus:SI (subreg:SI (match_dup 1) 1)
675: (subreg:SI (match_dup 2) 1)))
676:
677: (set (subreg:SI (match_dup 0) 0)
678: (minus:SI (subreg:SI (match_dup 1) 0)
679: (subreg:SI (match_dup 2) 0)))
680:
681: (set (subreg:SI (match_dup 0) 0)
682: (minus:SI (subreg:SI (match_dup 0) 0)
683: (match_dup 3)))]
684: "")
685:
686: (define_insn "subdi3_internal_2"
687: [(set (match_operand:DI 0 "register_operand" "=d,d,d")
688: (minus:DI (match_operand:DI 1 "register_operand" "d,d,d")
689: (match_operand:DI 2 "small_int" "P,J,N")))
690: (clobber (match_operand:SI 3 "register_operand" "=d,d,d"))]
1.1.1.3 ! root 691: "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && INTVAL (operands[2]) != -32768"
1.1 root 692: "@
693: sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,%3
694: move\\t%L0,%L1\;move\\t%M0,%M1
695: sltu\\t%3,%L1,%2\;subu\\t%L0,%L1,%2\;subu\\t%M0,%M1,1\;subu\\t%M0,%M0,%3"
696: [(set_attr "type" "darith")
697: (set_attr "mode" "DI")
698: (set_attr "length" "3,2,4")])
699:
700: (define_split
701: [(set (match_operand:DI 0 "register_operand" "")
702: (minus:DI (match_operand:DI 1 "register_operand" "")
703: (match_operand:DI 2 "small_int" "")))
704: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 705: "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 706: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
707: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
708: && INTVAL (operands[2]) > 0"
709:
710: [(set (match_dup 3)
711: (ltu:SI (subreg:SI (match_dup 1) 0)
712: (match_dup 2)))
713:
714: (set (subreg:SI (match_dup 0) 0)
715: (minus:SI (subreg:SI (match_dup 1) 0)
716: (match_dup 2)))
717:
718: (set (subreg:SI (match_dup 0) 1)
719: (minus:SI (subreg:SI (match_dup 1) 1)
720: (match_dup 3)))]
721: "")
722:
723: (define_split
724: [(set (match_operand:DI 0 "register_operand" "")
725: (minus:DI (match_operand:DI 1 "register_operand" "")
726: (match_operand:DI 2 "small_int" "")))
727: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 728: "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 729: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
730: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
731: && INTVAL (operands[2]) > 0"
732:
733: [(set (match_dup 3)
734: (ltu:SI (subreg:SI (match_dup 1) 1)
735: (match_dup 2)))
736:
737: (set (subreg:SI (match_dup 0) 1)
738: (minus:SI (subreg:SI (match_dup 1) 1)
739: (match_dup 2)))
740:
741: (set (subreg:SI (match_dup 0) 0)
742: (minus:SI (subreg:SI (match_dup 1) 0)
743: (match_dup 3)))]
744: "")
745:
1.1.1.3 ! root 746: (define_insn "subdi3_internal_3"
! 747: [(set (match_operand:DI 0 "register_operand" "=d")
! 748: (minus:DI (match_operand:DI 1 "reg_or_0_operand" "dJ")
! 749: (match_operand:DI 2 "arith_operand" "dI")))]
! 750: "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
! 751: "*
! 752: {
! 753: return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
! 754: ? \"daddu\\t%0,%z1,%n2\"
! 755: : \"dsubu\\t%0,%z1,%2\";
! 756: }"
! 757: [(set_attr "type" "darith")
! 758: (set_attr "mode" "DI")
! 759: (set_attr "length" "1")])
! 760:
! 761:
! 762: (define_insn "subsi3_internal_2"
! 763: [(set (match_operand:DI 0 "register_operand" "=d")
! 764: (sign_extend:DI (minus:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
! 765: (match_operand:SI 2 "arith_operand" "dI"))))]
! 766: "TARGET_64BIT && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != -32768)"
! 767: "*
! 768: {
! 769: return (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
! 770: ? \"addu\\t%0,%z1,%n2\"
! 771: : \"subu\\t%0,%z1,%2\";
! 772: }"
! 773: [(set_attr "type" "arith")
! 774: (set_attr "mode" "DI")
! 775: (set_attr "length" "1")])
! 776:
1.1 root 777:
778: ;;
779: ;; ....................
780: ;;
781: ;; MULTIPLICATION
782: ;;
783: ;; ....................
784: ;;
785:
786: (define_insn "muldf3"
787: [(set (match_operand:DF 0 "register_operand" "=f")
788: (mult:DF (match_operand:DF 1 "register_operand" "f")
789: (match_operand:DF 2 "register_operand" "f")))]
790: "TARGET_HARD_FLOAT"
791: "mul.d\\t%0,%1,%2"
792: [(set_attr "type" "fmul")
793: (set_attr "mode" "DF")
794: (set_attr "length" "1")])
795:
796: (define_insn "mulsf3"
797: [(set (match_operand:SF 0 "register_operand" "=f")
798: (mult:SF (match_operand:SF 1 "register_operand" "f")
799: (match_operand:SF 2 "register_operand" "f")))]
800: "TARGET_HARD_FLOAT"
801: "mul.s\\t%0,%1,%2"
802: [(set_attr "type" "fmul")
803: (set_attr "mode" "SF")
804: (set_attr "length" "1")])
805:
806: (define_insn "mulsi3"
807: [(set (match_operand:SI 0 "register_operand" "=d")
808: (mult:SI (match_operand:SI 1 "register_operand" "d")
809: (match_operand:SI 2 "register_operand" "d")))
810: (clobber (reg:SI 64))
811: (clobber (reg:SI 65))]
812: ""
813: "*
814: {
815: rtx xoperands[10];
816:
817: xoperands[0] = operands[0];
818: xoperands[1] = gen_rtx (REG, SImode, LO_REGNUM);
819:
820: output_asm_insn (\"mult\\t%1,%2\", operands);
1.1.1.3 ! root 821: output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
1.1 root 822: return \"\";
823: }"
824: [(set_attr "type" "imul")
825: (set_attr "mode" "SI")
826: (set_attr "length" "3")]) ;; mult + mflo + delay
827:
1.1.1.3 ! root 828: ;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while
! 829: ;; a multiply is in progress, it may give an incorrect result. We solve
! 830: ;; this by not splitting on the r4000.
! 831:
1.1 root 832: (define_split
833: [(set (match_operand:SI 0 "register_operand" "")
834: (mult:SI (match_operand:SI 1 "register_operand" "")
835: (match_operand:SI 2 "register_operand" "")))
836: (clobber (reg:SI 64))
837: (clobber (reg:SI 65))]
1.1.1.3 ! root 838: "!TARGET_DEBUG_D_MODE && mips_cpu != PROCESSOR_R4000"
1.1 root 839: [(parallel [(set (reg:SI 65) ;; low register
840: (mult:SI (match_dup 1)
841: (match_dup 2)))
842: (clobber (reg:SI 64))])
843: (set (match_dup 0)
844: (reg:SI 65))]
845: "")
846:
847: (define_insn "mulsi3_internal"
848: [(set (reg:SI 65) ;; low register
849: (mult:SI (match_operand:SI 0 "register_operand" "d")
850: (match_operand:SI 1 "register_operand" "d")))
851: (clobber (reg:SI 64))]
852: ""
853: "mult\\t%0,%1"
854: [(set_attr "type" "imul")
855: (set_attr "mode" "SI")
856: (set_attr "length" "1")])
857:
1.1.1.3 ! root 858: (define_insn "muldi3"
! 859: [(set (match_operand:DI 0 "register_operand" "=d")
! 860: (mult:DI (match_operand:DI 1 "register_operand" "d")
! 861: (match_operand:DI 2 "register_operand" "d")))
! 862: (clobber (reg:DI 64))
! 863: (clobber (reg:DI 65))]
! 864: "TARGET_64BIT"
! 865: "*
! 866: {
! 867: rtx xoperands[10];
! 868:
! 869: xoperands[0] = operands[0];
! 870: xoperands[1] = gen_rtx (REG, DImode, LO_REGNUM);
! 871:
! 872: output_asm_insn (\"dmult\\t%1,%2\", operands);
! 873: output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
! 874: return \"\";
! 875: }"
! 876: [(set_attr "type" "imul")
! 877: (set_attr "mode" "DI")
! 878: (set_attr "length" "3")]) ;; mult + mflo + delay
! 879:
! 880: ;; ??? The R4000 (only) has a cpu bug. If a double-word shift executes while
! 881: ;; a multiply is in progress, it may give an incorrect result. We solve
! 882: ;; this by not splitting on the r4000.
! 883:
! 884: (define_split
! 885: [(set (match_operand:DI 0 "register_operand" "")
! 886: (mult:DI (match_operand:DI 1 "register_operand" "")
! 887: (match_operand:DI 2 "register_operand" "")))
! 888: (clobber (reg:DI 64))
! 889: (clobber (reg:DI 65))]
! 890: "TARGET_64BIT && !TARGET_DEBUG_D_MODE && mips_cpu != PROCESSOR_R4000"
! 891: [(parallel [(set (reg:DI 65) ;; low register
! 892: (mult:DI (match_dup 1)
! 893: (match_dup 2)))
! 894: (clobber (reg:DI 64))])
! 895: (set (match_dup 0)
! 896: (reg:DI 65))]
! 897: "")
! 898:
! 899: (define_insn "muldi3_internal"
! 900: [(set (reg:DI 65) ;; low register
! 901: (mult:DI (match_operand:DI 0 "register_operand" "d")
! 902: (match_operand:DI 1 "register_operand" "d")))
! 903: (clobber (reg:DI 64))]
! 904: "TARGET_64BIT"
! 905: "dmult\\t%0,%1"
! 906: [(set_attr "type" "imul")
! 907: (set_attr "mode" "DI")
! 908: (set_attr "length" "1")])
! 909:
! 910: ;; In 64 bit mode the mult instruction still writes 32 bits each to HI
! 911: ;; and LO, so to do mulsidi3 and umultsidi3 we need to pull the values
! 912: ;; out and combine them by hand into the single output register. Not
! 913: ;; supported for now.
! 914:
! 915: ;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
! 916:
1.1 root 917: (define_insn "mulsidi3"
918: [(set (match_operand:DI 0 "register_operand" "=d")
919: (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
920: (sign_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1.1.1.3 ! root 921: (clobber (reg:SI 64))
! 922: (clobber (reg:SI 65))]
! 923: "!TARGET_64BIT"
1.1 root 924: "*
925: {
926: rtx xoperands[10];
927:
928: xoperands[0] = operands[0];
929: xoperands[1] = gen_rtx (REG, DImode, MD_REG_FIRST);
930:
931: output_asm_insn (\"mult\\t%1,%2\", operands);
932: output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
933: return \"\";
934: }"
935: [(set_attr "type" "imul")
936: (set_attr "mode" "SI")
937: (set_attr "length" "4")]) ;; mult + mflo + mfhi + delay
938:
1.1.1.3 ! root 939: (define_insn "smulsi3_highpart"
! 940: [(set (match_operand:SI 0 "register_operand" "=d")
! 941: (truncate:SI
! 942: (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
! 943: (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))
! 944: (const_int 32))))
! 945: (clobber (reg:SI 64))
! 946: (clobber (reg:SI 65))]
! 947: ""
! 948: "*
! 949: {
! 950: rtx xoperands[10];
! 951:
! 952: xoperands[0] = operands[0];
! 953: xoperands[1] = gen_rtx (REG, SImode, HI_REGNUM);
! 954:
! 955: output_asm_insn (\"mult\\t%1,%2\", operands);
! 956: output_asm_insn (mips_move_1word (xoperands, insn, TRUE), xoperands);
! 957: return \"\";
! 958: }"
! 959: [(set_attr "type" "imul")
! 960: (set_attr "mode" "SI")
! 961: (set_attr "length" "3")]) ;; mult + mfhi + delay
! 962:
! 963: (define_split
! 964: [(set (match_operand:SI 0 "register_operand" "")
! 965: (truncate:SI
! 966: (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d"))
! 967: (sign_extend:DI (match_operand:SI 2 "register_operand" "d")))
! 968: (const_int 32))))
! 969: (clobber (reg:SI 64))
! 970: (clobber (reg:SI 65))]
! 971: "!TARGET_DEBUG_D_MODE"
! 972: [(parallel [(set (reg:SI 64) ;; high register
! 973: (truncate:SI
! 974: (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
! 975: (sign_extend:DI (match_dup 2)))
! 976: (const_int 32))))
! 977: (clobber (reg:SI 65))])
! 978: (set (match_dup 0)
! 979: (reg:SI 64))]
! 980: "")
! 981:
! 982: (define_insn "smulsi3_highpart_internal"
! 983: [(set (reg:SI 64) ;; high register
! 984: (truncate:SI
! 985: (lshiftrt:DI (mult:DI (sign_extend:DI (match_operand:SI 0 "register_operand" "d"))
! 986: (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))
! 987: (const_int 32))))
! 988: (clobber (reg:SI 65))]
! 989: ""
! 990: "mult\\t%0,%1"
! 991: [(set_attr "type" "imul")
! 992: (set_attr "mode" "SI")
! 993: (set_attr "length" "1")])
! 994:
1.1 root 995: (define_insn "umulsidi3"
996: [(set (match_operand:DI 0 "register_operand" "=d")
997: (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
998: (zero_extend:DI (match_operand:SI 2 "register_operand" "d"))))
1.1.1.3 ! root 999: (clobber (reg:SI 64))
! 1000: (clobber (reg:SI 65))]
! 1001: "!TARGET_64BIT"
1.1 root 1002: "*
1003: {
1004: rtx xoperands[10];
1005:
1006: xoperands[0] = operands[0];
1007: xoperands[1] = gen_rtx (REG, DImode, MD_REG_FIRST);
1008:
1009: output_asm_insn (\"multu\\t%1,%2\", operands);
1010: output_asm_insn (mips_move_2words (xoperands, insn), xoperands);
1011: return \"\";
1012: }"
1013: [(set_attr "type" "imul")
1014: (set_attr "mode" "SI")
1015: (set_attr "length" "4")]) ;; mult + mflo + mfhi + delay
1016:
1.1.1.3 ! root 1017: (define_insn "umulsi3_highpart"
! 1018: [(set (match_operand:SI 0 "register_operand" "=d")
! 1019: (truncate:SI
! 1020: (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
! 1021: (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))
! 1022: (const_int 32))))
! 1023: (clobber (reg:SI 64))
! 1024: (clobber (reg:SI 65))]
! 1025: ""
! 1026: "*
! 1027: {
! 1028: rtx xoperands[10];
! 1029:
! 1030: xoperands[0] = operands[0];
! 1031: xoperands[1] = gen_rtx (REG, SImode, HI_REGNUM);
! 1032:
! 1033: output_asm_insn (\"multu\\t%1,%2\", operands);
! 1034: output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
! 1035: return \"\";
! 1036: }"
! 1037: [(set_attr "type" "imul")
! 1038: (set_attr "mode" "SI")
! 1039: (set_attr "length" "3")]) ;; multu + mfhi + delay
! 1040:
! 1041: (define_split
! 1042: [(set (match_operand:SI 0 "register_operand" "")
! 1043: (truncate:SI
! 1044: (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "d"))
! 1045: (zero_extend:DI (match_operand:SI 2 "register_operand" "d")))
! 1046: (const_int 32))))
! 1047: (clobber (reg:SI 64))
! 1048: (clobber (reg:SI 65))]
! 1049: "!TARGET_DEBUG_D_MODE"
! 1050: [(parallel [(set (reg:SI 64) ;; high register
! 1051: (truncate:SI
! 1052: (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
! 1053: (zero_extend:DI (match_dup 2)))
! 1054: (const_int 32))))
! 1055: (clobber (reg:SI 65))])
! 1056: (set (match_dup 0)
! 1057: (reg:SI 64))]
! 1058: "")
! 1059:
! 1060: (define_insn "umulsi3_highpart_internal"
! 1061: [(set (reg:SI 64) ;; high register
! 1062: (truncate:SI
! 1063: (lshiftrt:DI (mult:DI (zero_extend:DI (match_operand:SI 0 "register_operand" "d"))
! 1064: (zero_extend:DI (match_operand:SI 1 "register_operand" "d")))
! 1065: (const_int 32))))
! 1066: (clobber (reg:SI 65))]
! 1067: ""
! 1068: "multu\\t%0,%1"
! 1069: [(set_attr "type" "imul")
! 1070: (set_attr "mode" "SI")
! 1071: (set_attr "length" "1")])
! 1072:
! 1073: (define_insn "smuldi3_highpart"
! 1074: [(set (match_operand:DI 0 "register_operand" "=d")
! 1075: (truncate:DI
! 1076: (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "d"))
! 1077: (sign_extend:TI (match_operand:DI 2 "register_operand" "d")))
! 1078: (const_int 64))))
! 1079: (clobber (reg:DI 64))
! 1080: (clobber (reg:DI 65))]
! 1081: "TARGET_64BIT"
! 1082: "*
! 1083: {
! 1084: rtx xoperands[10];
! 1085:
! 1086: xoperands[0] = operands[0];
! 1087: xoperands[1] = gen_rtx (REG, DImode, HI_REGNUM);
! 1088:
! 1089: output_asm_insn (\"dmult\\t%1,%2\", operands);
! 1090: output_asm_insn (mips_move_1word (xoperands, insn, TRUE), xoperands);
! 1091: return \"\";
! 1092: }"
! 1093: [(set_attr "type" "imul")
! 1094: (set_attr "mode" "DI")
! 1095: (set_attr "length" "3")]) ;; mult + mfhi + delay
! 1096:
! 1097: (define_split
! 1098: [(set (match_operand:DI 0 "register_operand" "")
! 1099: (truncate:DI
! 1100: (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 1 "register_operand" "d"))
! 1101: (sign_extend:TI (match_operand:DI 2 "register_operand" "d")))
! 1102: (const_int 64))))
! 1103: (clobber (reg:DI 64))
! 1104: (clobber (reg:DI 65))]
! 1105: "TARGET_64BIT && !TARGET_DEBUG_D_MODE"
! 1106: [(parallel [(set (reg:DI 64) ;; high register
! 1107: (truncate:DI
! 1108: (lshiftrt:TI (mult:TI (sign_extend:TI (match_dup 1))
! 1109: (sign_extend:TI (match_dup 2)))
! 1110: (const_int 64))))
! 1111: (clobber (reg:DI 65))])
! 1112: (set (match_dup 0)
! 1113: (reg:DI 64))]
! 1114: "")
! 1115:
! 1116: (define_insn "smuldi3_highpart_internal"
! 1117: [(set (reg:DI 64) ;; high register
! 1118: (truncate:DI
! 1119: (lshiftrt:TI (mult:TI (sign_extend:TI (match_operand:DI 0 "register_operand" "d"))
! 1120: (sign_extend:TI (match_operand:DI 1 "register_operand" "d")))
! 1121: (const_int 64))))
! 1122: (clobber (reg:DI 65))]
! 1123: "TARGET_64BIT"
! 1124: "dmult\\t%0,%1"
! 1125: [(set_attr "type" "imul")
! 1126: (set_attr "mode" "DI")
! 1127: (set_attr "length" "1")])
! 1128:
! 1129: (define_insn "umuldi3_highpart"
! 1130: [(set (match_operand:DI 0 "register_operand" "=d")
! 1131: (truncate:DI
! 1132: (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "d"))
! 1133: (zero_extend:TI (match_operand:DI 2 "register_operand" "d")))
! 1134: (const_int 64))))
! 1135: (clobber (reg:DI 64))
! 1136: (clobber (reg:DI 65))]
! 1137: "TARGET_64BIT"
! 1138: "*
! 1139: {
! 1140: rtx xoperands[10];
! 1141:
! 1142: xoperands[0] = operands[0];
! 1143: xoperands[1] = gen_rtx (REG, DImode, HI_REGNUM);
! 1144:
! 1145: output_asm_insn (\"dmultu\\t%1,%2\", operands);
! 1146: output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
! 1147: return \"\";
! 1148: }"
! 1149: [(set_attr "type" "imul")
! 1150: (set_attr "mode" "DI")
! 1151: (set_attr "length" "3")]) ;; multu + mfhi + delay
! 1152:
! 1153: (define_split
! 1154: [(set (match_operand:DI 0 "register_operand" "")
! 1155: (truncate:DI
! 1156: (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand" "d"))
! 1157: (zero_extend:TI (match_operand:DI 2 "register_operand" "d")))
! 1158: (const_int 64))))
! 1159: (clobber (reg:DI 64))
! 1160: (clobber (reg:DI 65))]
! 1161: "TARGET_64BIT && !TARGET_DEBUG_D_MODE"
! 1162: [(parallel [(set (reg:DI 64) ;; high register
! 1163: (truncate:DI
! 1164: (lshiftrt:TI (mult:TI (zero_extend:TI (match_dup 1))
! 1165: (zero_extend:TI (match_dup 2)))
! 1166: (const_int 64))))
! 1167: (clobber (reg:DI 65))])
! 1168: (set (match_dup 0)
! 1169: (reg:DI 64))]
! 1170: "")
! 1171:
! 1172: (define_insn "umuldi3_highpart_internal"
! 1173: [(set (reg:DI 64) ;; high register
! 1174: (truncate:DI
! 1175: (lshiftrt:TI (mult:TI (zero_extend:TI (match_operand:DI 0 "register_operand" "d"))
! 1176: (zero_extend:TI (match_operand:DI 1 "register_operand" "d")))
! 1177: (const_int 64))))
! 1178: (clobber (reg:DI 65))]
! 1179: "TARGET_64BIT"
! 1180: "dmultu\\t%0,%1"
! 1181: [(set_attr "type" "imul")
! 1182: (set_attr "mode" "DI")
! 1183: (set_attr "length" "1")])
1.1 root 1184:
1185: ;;
1186: ;; ....................
1187: ;;
1188: ;; DIVISION and REMAINDER
1189: ;;
1190: ;; ....................
1191: ;;
1192:
1193: (define_insn "divdf3"
1194: [(set (match_operand:DF 0 "register_operand" "=f")
1195: (div:DF (match_operand:DF 1 "register_operand" "f")
1196: (match_operand:DF 2 "register_operand" "f")))]
1197: "TARGET_HARD_FLOAT"
1198: "div.d\\t%0,%1,%2"
1199: [(set_attr "type" "fdiv")
1200: (set_attr "mode" "DF")
1201: (set_attr "length" "1")])
1202:
1203: (define_insn "divsf3"
1204: [(set (match_operand:SF 0 "register_operand" "=f")
1205: (div:SF (match_operand:SF 1 "register_operand" "f")
1206: (match_operand:SF 2 "register_operand" "f")))]
1207: "TARGET_HARD_FLOAT"
1208: "div.s\\t%0,%1,%2"
1209: [(set_attr "type" "fdiv")
1210: (set_attr "mode" "SF")
1211: (set_attr "length" "1")])
1212:
1213: ;; If optimizing, prefer the divmod functions over separate div and
1214: ;; mod functions, since this will allow using one instruction for both
1215: ;; the quotient and remainder. At present, the divmod is not moved out
1216: ;; of loops if it is constant within the loop, so allow -mdebugc to
1217: ;; use the old method of doing things.
1218:
1219: ;; 64 is the multiply/divide hi register
1220: ;; 65 is the multiply/divide lo register
1221:
1.1.1.3 ! root 1222: ;; ??? We can't accept constants here, because the MIPS assembler will replace
! 1223: ;; a divide by power of 2 with a shift, and then the remainder is no longer
! 1224: ;; available.
! 1225:
1.1 root 1226: (define_insn "divmodsi4"
1227: [(set (match_operand:SI 0 "register_operand" "=d")
1228: (div:SI (match_operand:SI 1 "register_operand" "d")
1229: (match_operand:SI 2 "register_operand" "d")))
1230: (set (match_operand:SI 3 "register_operand" "=d")
1231: (mod:SI (match_dup 1)
1232: (match_dup 2)))
1233: (clobber (reg:SI 64))
1234: (clobber (reg:SI 65))]
1235: "optimize"
1236: "*
1237: {
1238: if (find_reg_note (insn, REG_UNUSED, operands[3]))
1239: return \"div\\t%0,%1,%2\";
1240:
1241: if (find_reg_note (insn, REG_UNUSED, operands[0]))
1242: return \"rem\\t%3,%1,%2\";
1243:
1244: return \"div\\t%0,%1,%2\;mfhi\\t%3\";
1245: }"
1246: [(set_attr "type" "idiv")
1247: (set_attr "mode" "SI")
1.1.1.3 ! root 1248: (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
! 1249:
! 1250: (define_insn "divmoddi4"
! 1251: [(set (match_operand:DI 0 "register_operand" "=d")
! 1252: (div:DI (match_operand:DI 1 "register_operand" "d")
! 1253: (match_operand:DI 2 "register_operand" "d")))
! 1254: (set (match_operand:DI 3 "register_operand" "=d")
! 1255: (mod:DI (match_dup 1)
! 1256: (match_dup 2)))
! 1257: (clobber (reg:DI 64))
! 1258: (clobber (reg:DI 65))]
! 1259: "TARGET_64BIT && optimize"
! 1260: "*
! 1261: {
! 1262: if (find_reg_note (insn, REG_UNUSED, operands[3]))
! 1263: return \"ddiv\\t%0,%1,%2\";
! 1264:
! 1265: if (find_reg_note (insn, REG_UNUSED, operands[0]))
! 1266: return \"drem\\t%3,%1,%2\";
! 1267:
! 1268: return \"ddiv\\t%0,%1,%2\;mfhi\\t%3\";
! 1269: }"
! 1270: [(set_attr "type" "idiv")
! 1271: (set_attr "mode" "DI")
! 1272: (set_attr "length" "15")]) ;; various tests for dividing by 0 and such
1.1 root 1273:
1274: (define_insn "udivmodsi4"
1275: [(set (match_operand:SI 0 "register_operand" "=d")
1276: (udiv:SI (match_operand:SI 1 "register_operand" "d")
1277: (match_operand:SI 2 "register_operand" "d")))
1278: (set (match_operand:SI 3 "register_operand" "=d")
1279: (umod:SI (match_dup 1)
1280: (match_dup 2)))
1281: (clobber (reg:SI 64))
1282: (clobber (reg:SI 65))]
1283: "optimize"
1284: "*
1285: {
1286: if (find_reg_note (insn, REG_UNUSED, operands[3]))
1287: return \"divu\\t%0,%1,%2\";
1288:
1289: if (find_reg_note (insn, REG_UNUSED, operands[0]))
1290: return \"remu\\t%3,%1,%2\";
1291:
1292: return \"divu\\t%0,%1,%2\;mfhi\\t%3\";
1293: }"
1294: [(set_attr "type" "idiv")
1295: (set_attr "mode" "SI")
1.1.1.3 ! root 1296: (set_attr "length" "8")]) ;; various tests for dividing by 0 and such
1.1 root 1297:
1.1.1.3 ! root 1298: (define_insn "udivmoddi4"
! 1299: [(set (match_operand:DI 0 "register_operand" "=d")
! 1300: (udiv:DI (match_operand:DI 1 "register_operand" "d")
! 1301: (match_operand:DI 2 "register_operand" "d")))
! 1302: (set (match_operand:DI 3 "register_operand" "=d")
! 1303: (umod:DI (match_dup 1)
! 1304: (match_dup 2)))
! 1305: (clobber (reg:DI 64))
! 1306: (clobber (reg:DI 65))]
! 1307: "TARGET_64BIT && optimize"
! 1308: "*
! 1309: {
! 1310: if (find_reg_note (insn, REG_UNUSED, operands[3]))
! 1311: return \"ddivu\\t%0,%1,%2\";
! 1312:
! 1313: if (find_reg_note (insn, REG_UNUSED, operands[0]))
! 1314: return \"dremu\\t%3,%1,%2\";
! 1315:
! 1316: return \"ddivu\\t%0,%1,%2\;mfhi\\t%3\";
! 1317: }"
! 1318: [(set_attr "type" "idiv")
! 1319: (set_attr "mode" "DI")
! 1320: (set_attr "length" "8")]) ;; various tests for dividing by 0 and such
! 1321:
! 1322: (define_insn "divsi3"
! 1323: [(set (match_operand:SI 0 "register_operand" "=d")
! 1324: (div:SI (match_operand:SI 1 "register_operand" "d")
! 1325: (match_operand:SI 2 "nonmemory_operand" "di")))
! 1326: (clobber (reg:SI 64))
! 1327: (clobber (reg:SI 65))]
! 1328: "!optimize"
1.1 root 1329: "div\\t%0,%1,%2"
1330: [(set_attr "type" "idiv")
1331: (set_attr "mode" "SI")
1332: (set_attr "length" "13")]) ;; various tests for dividing by 0 and such
1333:
1.1.1.3 ! root 1334: (define_insn "divdi3"
! 1335: [(set (match_operand:DI 0 "register_operand" "=d")
! 1336: (div:DI (match_operand:DI 1 "register_operand" "d")
! 1337: (match_operand:DI 2 "nonmemory_operand" "di")))
! 1338: (clobber (reg:DI 64))
! 1339: (clobber (reg:DI 65))]
! 1340: "TARGET_64BIT && !optimize"
! 1341: "ddiv\\t%0,%1,%2"
! 1342: [(set_attr "type" "idiv")
! 1343: (set_attr "mode" "DI")
! 1344: (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
! 1345:
1.1 root 1346: (define_insn "modsi3"
1347: [(set (match_operand:SI 0 "register_operand" "=d")
1348: (mod:SI (match_operand:SI 1 "register_operand" "d")
1.1.1.3 ! root 1349: (match_operand:SI 2 "nonmemory_operand" "di")))
1.1 root 1350: (clobber (reg:SI 64))
1351: (clobber (reg:SI 65))]
1352: "!optimize"
1353: "rem\\t%0,%1,%2"
1354: [(set_attr "type" "idiv")
1355: (set_attr "mode" "SI")
1.1.1.3 ! root 1356: (set_attr "length" "13")]) ;; various tests for dividing by 0 and such
! 1357:
! 1358: (define_insn "moddi3"
! 1359: [(set (match_operand:DI 0 "register_operand" "=d")
! 1360: (mod:DI (match_operand:DI 1 "register_operand" "d")
! 1361: (match_operand:DI 2 "nonmemory_operand" "di")))
! 1362: (clobber (reg:DI 64))
! 1363: (clobber (reg:DI 65))]
! 1364: "TARGET_64BIT && !optimize"
! 1365: "drem\\t%0,%1,%2"
! 1366: [(set_attr "type" "idiv")
! 1367: (set_attr "mode" "DI")
1.1 root 1368: (set_attr "length" "14")]) ;; various tests for dividing by 0 and such
1369:
1370: (define_insn "udivsi3"
1371: [(set (match_operand:SI 0 "register_operand" "=d")
1372: (udiv:SI (match_operand:SI 1 "register_operand" "d")
1.1.1.3 ! root 1373: (match_operand:SI 2 "nonmemory_operand" "di")))
1.1 root 1374: (clobber (reg:SI 64))
1375: (clobber (reg:SI 65))]
1376: "!optimize"
1377: "divu\\t%0,%1,%2"
1378: [(set_attr "type" "idiv")
1379: (set_attr "mode" "SI")
1.1.1.3 ! root 1380: (set_attr "length" "7")]) ;; various tests for dividing by 0 and such
! 1381:
! 1382: (define_insn "udivdi3"
! 1383: [(set (match_operand:DI 0 "register_operand" "=d")
! 1384: (udiv:DI (match_operand:DI 1 "register_operand" "d")
! 1385: (match_operand:DI 2 "nonmemory_operand" "di")))
! 1386: (clobber (reg:DI 64))
! 1387: (clobber (reg:DI 65))]
! 1388: "TARGET_64BIT && !optimize"
! 1389: "ddivu\\t%0,%1,%2"
! 1390: [(set_attr "type" "idiv")
! 1391: (set_attr "mode" "DI")
! 1392: (set_attr "length" "7")]) ;; various tests for dividing by 0 and such
1.1 root 1393:
1394: (define_insn "umodsi3"
1395: [(set (match_operand:SI 0 "register_operand" "=d")
1396: (umod:SI (match_operand:SI 1 "register_operand" "d")
1.1.1.3 ! root 1397: (match_operand:SI 2 "nonmemory_operand" "di")))
1.1 root 1398: (clobber (reg:SI 64))
1399: (clobber (reg:SI 65))]
1400: "!optimize"
1401: "remu\\t%0,%1,%2"
1402: [(set_attr "type" "idiv")
1403: (set_attr "mode" "SI")
1.1.1.3 ! root 1404: (set_attr "length" "7")]) ;; various tests for dividing by 0 and such
! 1405:
! 1406: (define_insn "umoddi3"
! 1407: [(set (match_operand:DI 0 "register_operand" "=d")
! 1408: (umod:DI (match_operand:DI 1 "register_operand" "d")
! 1409: (match_operand:DI 2 "nonmemory_operand" "di")))
! 1410: (clobber (reg:DI 64))
! 1411: (clobber (reg:DI 65))]
! 1412: "TARGET_64BIT && !optimize"
! 1413: "dremu\\t%0,%1,%2"
! 1414: [(set_attr "type" "idiv")
! 1415: (set_attr "mode" "DI")
! 1416: (set_attr "length" "7")]) ;; various tests for dividing by 0 and such
1.1 root 1417:
1418:
1419: ;;
1420: ;; ....................
1421: ;;
1422: ;; SQUARE ROOT
1423: ;;
1424: ;; ....................
1425:
1426: (define_insn "sqrtdf2"
1427: [(set (match_operand:DF 0 "register_operand" "=f")
1428: (sqrt:DF (match_operand:DF 1 "register_operand" "f")))]
1429: "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
1430: "sqrt.d\\t%0,%1"
1.1.1.3 ! root 1431: [(set_attr "type" "fsqrt")
1.1 root 1432: (set_attr "mode" "DF")
1433: (set_attr "length" "1")])
1434:
1435: (define_insn "sqrtsf2"
1436: [(set (match_operand:SF 0 "register_operand" "=f")
1437: (sqrt:SF (match_operand:SF 1 "register_operand" "f")))]
1438: "TARGET_HARD_FLOAT && HAVE_SQRT_P()"
1439: "sqrt.s\\t%0,%1"
1.1.1.3 ! root 1440: [(set_attr "type" "fsqrt")
1.1 root 1441: (set_attr "mode" "SF")
1442: (set_attr "length" "1")])
1443:
1444:
1445: ;;
1446: ;; ....................
1447: ;;
1448: ;; ABSOLUTE VALUE
1449: ;;
1450: ;; ....................
1451:
1452: ;; Do not use the integer abs macro instruction, since that signals an
1453: ;; exception on -2147483648 (sigh).
1454:
1455: (define_insn "abssi2"
1456: [(set (match_operand:SI 0 "register_operand" "=d")
1457: (abs:SI (match_operand:SI 1 "register_operand" "d")))]
1458: ""
1459: "*
1460: {
1461: dslots_jump_total++;
1462: dslots_jump_filled++;
1463: operands[2] = const0_rtx;
1464:
1.1.1.3 ! root 1465: if (REGNO (operands[0]) == REGNO (operands[1]))
! 1466: {
! 1467: if (mips_isa >= 2)
! 1468: return \"%(bltzl\\t%1,1f\\n\\tsubu\\t%0,%z2,%0\\n1:%)\";
! 1469: else
! 1470: return \"bgez\\t%1,1f%#\\n\\tsubu\\t%0,%z2,%0\\n1:\";
! 1471: }
! 1472: else
! 1473: return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tsubu\\t%0,%z2,%0\\n1:%)\";
1.1 root 1474: }"
1475: [(set_attr "type" "multi")
1476: (set_attr "mode" "SI")
1477: (set_attr "length" "3")])
1478:
1.1.1.3 ! root 1479: (define_insn "absdi2"
! 1480: [(set (match_operand:DI 0 "register_operand" "=d")
! 1481: (abs:DI (match_operand:DI 1 "register_operand" "d")))]
! 1482: "TARGET_64BIT"
! 1483: "*
! 1484: {
! 1485: dslots_jump_total++;
! 1486: dslots_jump_filled++;
! 1487: operands[2] = const0_rtx;
! 1488:
! 1489: if (REGNO (operands[0]) == REGNO (operands[1]))
! 1490: return \"%(bltzl\\t%1,1f\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\";
! 1491: else
! 1492: return \"%(bgez\\t%1,1f\\n\\tmove\\t%0,%1\\n\\tdsubu\\t%0,%z2,%0\\n1:%)\";
! 1493: }"
! 1494: [(set_attr "type" "multi")
! 1495: (set_attr "mode" "DI")
! 1496: (set_attr "length" "3")])
! 1497:
1.1 root 1498: (define_insn "absdf2"
1499: [(set (match_operand:DF 0 "register_operand" "=f")
1500: (abs:DF (match_operand:DF 1 "register_operand" "f")))]
1501: "TARGET_HARD_FLOAT"
1502: "abs.d\\t%0,%1"
1503: [(set_attr "type" "fabs")
1504: (set_attr "mode" "DF")
1505: (set_attr "length" "1")])
1506:
1507: (define_insn "abssf2"
1508: [(set (match_operand:SF 0 "register_operand" "=f")
1509: (abs:SF (match_operand:SF 1 "register_operand" "f")))]
1510: "TARGET_HARD_FLOAT"
1511: "abs.s\\t%0,%1"
1512: [(set_attr "type" "fabs")
1513: (set_attr "mode" "SF")
1514: (set_attr "length" "1")])
1515:
1516:
1517: ;;
1518: ;; ....................
1519: ;;
1520: ;; FIND FIRST BIT INSTRUCTION
1521: ;;
1522: ;; ....................
1523: ;;
1524:
1525: (define_insn "ffssi2"
1526: [(set (match_operand:SI 0 "register_operand" "=&d")
1527: (ffs:SI (match_operand:SI 1 "register_operand" "d")))
1528: (clobber (match_scratch:SI 2 "=&d"))
1529: (clobber (match_scratch:SI 3 "=&d"))]
1530: ""
1531: "*
1532: {
1533: dslots_jump_total += 2;
1534: dslots_jump_filled += 2;
1535: operands[4] = const0_rtx;
1536:
1537: if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
1538: return \"%(\\
1539: move\\t%0,%z4\\n\\
1540: \\tbeq\\t%1,%z4,2f\\n\\
1541: 1:\\tand\\t%2,%1,0x0001\\n\\
1542: \\taddu\\t%0,%0,1\\n\\
1543: \\tbeq\\t%2,%z4,1b\\n\\
1544: \\tsrl\\t%1,%1,1\\n\\
1545: 2:%)\";
1546:
1547: return \"%(\\
1548: move\\t%0,%z4\\n\\
1549: \\tmove\\t%3,%1\\n\\
1550: \\tbeq\\t%3,%z4,2f\\n\\
1551: 1:\\tand\\t%2,%3,0x0001\\n\\
1552: \\taddu\\t%0,%0,1\\n\\
1553: \\tbeq\\t%2,%z4,1b\\n\\
1554: \\tsrl\\t%3,%3,1\\n\\
1555: 2:%)\";
1556: }"
1557: [(set_attr "type" "multi")
1558: (set_attr "mode" "SI")
1559: (set_attr "length" "6")])
1560:
1.1.1.3 ! root 1561: (define_insn "ffsdi2"
! 1562: [(set (match_operand:DI 0 "register_operand" "=&d")
! 1563: (ffs:DI (match_operand:DI 1 "register_operand" "d")))
! 1564: (clobber (match_scratch:DI 2 "=&d"))
! 1565: (clobber (match_scratch:DI 3 "=&d"))]
! 1566: "TARGET_64BIT"
! 1567: "*
! 1568: {
! 1569: dslots_jump_total += 2;
! 1570: dslots_jump_filled += 2;
! 1571: operands[4] = const0_rtx;
! 1572:
! 1573: if (optimize && find_reg_note (insn, REG_DEAD, operands[1]))
! 1574: return \"%(\\
! 1575: move\\t%0,%z4\\n\\
! 1576: \\tbeq\\t%1,%z4,2f\\n\\
! 1577: 1:\\tand\\t%2,%1,0x0001\\n\\
! 1578: \\tdaddu\\t%0,%0,1\\n\\
! 1579: \\tbeq\\t%2,%z4,1b\\n\\
! 1580: \\tdsrl\\t%1,%1,1\\n\\
! 1581: 2:%)\";
! 1582:
! 1583: return \"%(\\
! 1584: move\\t%0,%z4\\n\\
! 1585: \\tmove\\t%3,%1\\n\\
! 1586: \\tbeq\\t%3,%z4,2f\\n\\
! 1587: 1:\\tand\\t%2,%3,0x0001\\n\\
! 1588: \\tdaddu\\t%0,%0,1\\n\\
! 1589: \\tbeq\\t%2,%z4,1b\\n\\
! 1590: \\tdsrl\\t%3,%3,1\\n\\
! 1591: 2:%)\";
! 1592: }"
! 1593: [(set_attr "type" "multi")
! 1594: (set_attr "mode" "DI")
! 1595: (set_attr "length" "6")])
! 1596:
1.1 root 1597:
1598: ;;
1599: ;; ....................
1600: ;;
1601: ;; NEGATION and ONE'S COMPLEMENT
1602: ;;
1603: ;; ....................
1604:
1605: (define_insn "negsi2"
1606: [(set (match_operand:SI 0 "register_operand" "=d")
1607: (neg:SI (match_operand:SI 1 "register_operand" "d")))]
1608: ""
1609: "*
1610: {
1611: operands[2] = const0_rtx;
1612: return \"subu\\t%0,%z2,%1\";
1613: }"
1614: [(set_attr "type" "arith")
1615: (set_attr "mode" "SI")
1616: (set_attr "length" "1")])
1617:
1.1.1.2 root 1618: (define_expand "negdi2"
1.1 root 1619: [(parallel [(set (match_operand:DI 0 "register_operand" "=d")
1620: (neg:DI (match_operand:DI 1 "register_operand" "d")))
1621: (clobber (match_dup 2))])]
1.1.1.3 ! root 1622: "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
! 1623: "
! 1624: {
! 1625: if (TARGET_64BIT)
! 1626: {
! 1627: emit_insn (gen_negdi2_internal_2 (operands[0], operands[1]));
! 1628: DONE;
! 1629: }
! 1630:
! 1631: operands[2] = gen_reg_rtx (SImode);
! 1632: }")
1.1 root 1633:
1.1.1.2 root 1634: (define_insn "negdi2_internal"
1.1 root 1635: [(set (match_operand:DI 0 "register_operand" "=d")
1636: (neg:DI (match_operand:DI 1 "register_operand" "d")))
1637: (clobber (match_operand:SI 2 "register_operand" "=d"))]
1.1.1.3 ! root 1638: "! TARGET_64BIT && !TARGET_DEBUG_G_MODE"
1.1 root 1639: "*
1640: {
1641: operands[3] = const0_rtx;
1642: return \"subu\\t%L0,%z3,%L1\;subu\\t%M0,%z3,%M1\;sltu\\t%2,%z3,%L0\;subu\\t%M0,%M0,%2\";
1643: }"
1644: [(set_attr "type" "darith")
1645: (set_attr "mode" "DI")
1646: (set_attr "length" "4")])
1647:
1.1.1.3 ! root 1648: (define_insn "negdi2_internal_2"
! 1649: [(set (match_operand:DI 0 "register_operand" "=d")
! 1650: (neg:DI (match_operand:DI 1 "register_operand" "d")))]
! 1651: "TARGET_64BIT"
! 1652: "*
! 1653: {
! 1654: operands[2] = const0_rtx;
! 1655: return \"dsubu\\t%0,%z2,%1\";
! 1656: }"
! 1657: [(set_attr "type" "arith")
! 1658: (set_attr "mode" "DI")
! 1659: (set_attr "length" "1")])
! 1660:
1.1 root 1661: (define_insn "negdf2"
1662: [(set (match_operand:DF 0 "register_operand" "=f")
1663: (neg:DF (match_operand:DF 1 "register_operand" "f")))]
1664: "TARGET_HARD_FLOAT"
1665: "neg.d\\t%0,%1"
1666: [(set_attr "type" "fneg")
1667: (set_attr "mode" "DF")
1668: (set_attr "length" "1")])
1669:
1670: (define_insn "negsf2"
1671: [(set (match_operand:SF 0 "register_operand" "=f")
1672: (neg:SF (match_operand:SF 1 "register_operand" "f")))]
1673: "TARGET_HARD_FLOAT"
1674: "neg.s\\t%0,%1"
1675: [(set_attr "type" "fneg")
1676: (set_attr "mode" "SF")
1677: (set_attr "length" "1")])
1678:
1679: (define_insn "one_cmplsi2"
1680: [(set (match_operand:SI 0 "register_operand" "=d")
1681: (not:SI (match_operand:SI 1 "register_operand" "d")))]
1682: ""
1683: "*
1684: {
1685: operands[2] = const0_rtx;
1686: return \"nor\\t%0,%z2,%1\";
1687: }"
1688: [(set_attr "type" "arith")
1689: (set_attr "mode" "SI")
1690: (set_attr "length" "1")])
1691:
1692: (define_insn "one_cmpldi2"
1693: [(set (match_operand:DI 0 "register_operand" "=d")
1.1.1.3 ! root 1694: (not:DI (match_operand:DI 1 "register_operand" "d")))]
1.1 root 1695: ""
1696: "*
1697: {
1698: operands[2] = const0_rtx;
1.1.1.3 ! root 1699: if (TARGET_64BIT)
! 1700: return \"nor\\t%0,%z2,%1\";
1.1 root 1701: return \"nor\\t%M0,%z2,%M1\;nor\\t%L0,%z2,%L1\";
1702: }"
1703: [(set_attr "type" "darith")
1704: (set_attr "mode" "DI")
1.1.1.3 ! root 1705: (set (attr "length")
! 1706: (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
! 1707: (const_int 1)
! 1708: (const_int 2)))])
1.1 root 1709:
1710: (define_split
1711: [(set (match_operand:DI 0 "register_operand" "")
1712: (not:DI (match_operand:DI 1 "register_operand" "")))]
1.1.1.3 ! root 1713: "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 1714: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1715: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
1716:
1717: [(set (subreg:SI (match_dup 0) 0) (not:SI (subreg:SI (match_dup 1) 0)))
1718: (set (subreg:SI (match_dup 0) 1) (not:SI (subreg:SI (match_dup 1) 1)))]
1719: "")
1720:
1721: ;; Simple hack to recognize the "nor" instruction on the MIPS
1722: ;; This must appear before the normal or patterns, so that the
1723: ;; combiner will correctly fold things.
1724:
1725: (define_insn "norsi3"
1726: [(set (match_operand:SI 0 "register_operand" "=d")
1727: (not:SI (ior:SI (match_operand:SI 1 "reg_or_0_operand" "dJ")
1728: (match_operand:SI 2 "reg_or_0_operand" "dJ"))))]
1729: ""
1730: "nor\\t%0,%z1,%z2"
1731: [(set_attr "type" "arith")
1732: (set_attr "mode" "SI")
1733: (set_attr "length" "1")])
1734:
1735: (define_insn "nordi3"
1736: [(set (match_operand:DI 0 "register_operand" "=d")
1737: (not:DI (ior:DI (match_operand:DI 1 "register_operand" "d")
1738: (match_operand:DI 2 "register_operand" "d"))))]
1739: ""
1.1.1.3 ! root 1740: "*
! 1741: {
! 1742: if (TARGET_64BIT)
! 1743: return \"nor\\t%0,%z1,%z2\";
! 1744: return \"nor\\t%M0,%M1,%M2\;nor\\t%L0,%L1,%L2\";
! 1745: }"
1.1 root 1746: [(set_attr "type" "darith")
1747: (set_attr "mode" "DI")
1.1.1.3 ! root 1748: (set (attr "length")
! 1749: (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
! 1750: (const_int 1)
! 1751: (const_int 2)))])
1.1 root 1752:
1753: (define_split
1754: [(set (match_operand:DI 0 "register_operand" "")
1755: (not:DI (ior:DI (match_operand:DI 1 "register_operand" "")
1756: (match_operand:DI 2 "register_operand" ""))))]
1.1.1.3 ! root 1757: "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 1758: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1759: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1760: && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1761:
1762: [(set (subreg:SI (match_dup 0) 0) (not:SI (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0))))
1763: (set (subreg:SI (match_dup 0) 1) (not:SI (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1))))]
1764: "")
1765:
1766:
1767: ;;
1768: ;; ....................
1769: ;;
1770: ;; LOGICAL
1771: ;;
1772: ;; ....................
1773: ;;
1774:
1775: (define_insn "andsi3"
1776: [(set (match_operand:SI 0 "register_operand" "=d,d")
1777: (and:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
1778: (match_operand:SI 2 "uns_arith_operand" "d,K")))]
1779: ""
1780: "@
1781: and\\t%0,%1,%2
1782: andi\\t%0,%1,%x2"
1783: [(set_attr "type" "arith")
1784: (set_attr "mode" "SI")
1785: (set_attr "length" "1")])
1786:
1787: (define_insn "anddi3"
1788: [(set (match_operand:DI 0 "register_operand" "=d")
1789: (and:DI (match_operand:DI 1 "register_operand" "d")
1790: (match_operand:DI 2 "register_operand" "d")))]
1.1.1.3 ! root 1791: "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
! 1792: "*
! 1793: {
! 1794: if (TARGET_64BIT)
! 1795: return \"and\\t%0,%1,%2\";
! 1796: return \"and\\t%M0,%M1,%M2\;and\\t%L0,%L1,%L2\";
! 1797: }"
1.1 root 1798: [(set_attr "type" "darith")
1799: (set_attr "mode" "DI")
1.1.1.3 ! root 1800: (set (attr "length")
! 1801: (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
! 1802: (const_int 1)
! 1803: (const_int 2)))])
1.1 root 1804:
1805: (define_split
1806: [(set (match_operand:DI 0 "register_operand" "")
1807: (and:DI (match_operand:DI 1 "register_operand" "")
1808: (match_operand:DI 2 "register_operand" "")))]
1.1.1.3 ! root 1809: "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 1810: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1811: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1812: && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1813:
1814: [(set (subreg:SI (match_dup 0) 0) (and:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
1815: (set (subreg:SI (match_dup 0) 1) (and:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
1816: "")
1817:
1.1.1.3 ! root 1818: (define_insn "anddi3_internal1"
! 1819: [(set (match_operand:DI 0 "register_operand" "=d,d")
! 1820: (and:DI (match_operand:DI 1 "register_operand" "%d,d")
! 1821: (match_operand:DI 2 "uns_arith_operand" "d,K")))]
! 1822: "TARGET_64BIT"
! 1823: "@
! 1824: and\\t%0,%1,%2
! 1825: andi\\t%0,%1,%x2"
! 1826: [(set_attr "type" "arith")
! 1827: (set_attr "mode" "DI")
! 1828: (set_attr "length" "1")])
! 1829:
1.1 root 1830: (define_insn "iorsi3"
1831: [(set (match_operand:SI 0 "register_operand" "=d,d")
1832: (ior:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
1833: (match_operand:SI 2 "uns_arith_operand" "d,K")))]
1834: ""
1835: "@
1836: or\\t%0,%1,%2
1837: ori\\t%0,%1,%x2"
1838: [(set_attr "type" "arith")
1839: (set_attr "mode" "SI")
1840: (set_attr "length" "1")])
1841:
1.1.1.3 ! root 1842: ;;; ??? There is no iordi3 pattern which accepts 'K' constants when
! 1843: ;;; TARGET_64BIT
! 1844:
1.1 root 1845: (define_insn "iordi3"
1846: [(set (match_operand:DI 0 "register_operand" "=d")
1847: (ior:DI (match_operand:DI 1 "register_operand" "d")
1848: (match_operand:DI 2 "register_operand" "d")))]
1.1.1.3 ! root 1849: "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
! 1850: "*
! 1851: {
! 1852: if (TARGET_64BIT)
! 1853: return \"or\\t%0,%1,%2\";
! 1854: return \"or\\t%M0,%M1,%M2\;or\\t%L0,%L1,%L2\";
! 1855: }"
1.1 root 1856: [(set_attr "type" "darith")
1857: (set_attr "mode" "DI")
1.1.1.3 ! root 1858: (set (attr "length")
! 1859: (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
! 1860: (const_int 1)
! 1861: (const_int 2)))])
1.1 root 1862:
1863: (define_split
1864: [(set (match_operand:DI 0 "register_operand" "")
1865: (ior:DI (match_operand:DI 1 "register_operand" "")
1866: (match_operand:DI 2 "register_operand" "")))]
1.1.1.3 ! root 1867: "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 1868: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1869: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1870: && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1871:
1872: [(set (subreg:SI (match_dup 0) 0) (ior:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
1873: (set (subreg:SI (match_dup 0) 1) (ior:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
1874: "")
1875:
1876: (define_insn "xorsi3"
1877: [(set (match_operand:SI 0 "register_operand" "=d,d")
1878: (xor:SI (match_operand:SI 1 "uns_arith_operand" "%d,d")
1879: (match_operand:SI 2 "uns_arith_operand" "d,K")))]
1880: ""
1881: "@
1882: xor\\t%0,%1,%2
1883: xori\\t%0,%1,%x2"
1884: [(set_attr "type" "arith")
1885: (set_attr "mode" "SI")
1886: (set_attr "length" "1")])
1887:
1.1.1.3 ! root 1888: ;; ??? If delete the 32-bit long long patterns, then could merge this with
! 1889: ;; the following xordi3_internal pattern.
1.1 root 1890: (define_insn "xordi3"
1891: [(set (match_operand:DI 0 "register_operand" "=d")
1892: (xor:DI (match_operand:DI 1 "register_operand" "d")
1893: (match_operand:DI 2 "register_operand" "d")))]
1.1.1.3 ! root 1894: "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
! 1895: "*
! 1896: {
! 1897: if (TARGET_64BIT)
! 1898: return \"xor\\t%0,%1,%2\";
! 1899: return \"xor\\t%M0,%M1,%M2\;xor\\t%L0,%L1,%L2\";
! 1900: }"
1.1 root 1901: [(set_attr "type" "darith")
1902: (set_attr "mode" "DI")
1.1.1.3 ! root 1903: (set (attr "length")
! 1904: (if_then_else (ge (symbol_ref "mips_isa") (const_int 3))
! 1905: (const_int 1)
! 1906: (const_int 2)))])
1.1 root 1907:
1908: (define_split
1909: [(set (match_operand:DI 0 "register_operand" "")
1910: (xor:DI (match_operand:DI 1 "register_operand" "")
1911: (match_operand:DI 2 "register_operand" "")))]
1.1.1.3 ! root 1912: "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 1913: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
1914: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))
1915: && GET_CODE (operands[2]) == REG && GP_REG_P (REGNO (operands[2]))"
1916:
1917: [(set (subreg:SI (match_dup 0) 0) (xor:SI (subreg:SI (match_dup 1) 0) (subreg:SI (match_dup 2) 0)))
1918: (set (subreg:SI (match_dup 0) 1) (xor:SI (subreg:SI (match_dup 1) 1) (subreg:SI (match_dup 2) 1)))]
1919: "")
1920:
1.1.1.3 ! root 1921: (define_insn "xordi3_immed"
! 1922: [(set (match_operand:DI 0 "register_operand" "d")
! 1923: (xor:DI (match_operand:DI 1 "register_operand" "d")
! 1924: (match_operand:DI 2 "uns_arith_operand" "K")))]
! 1925: "TARGET_64BIT"
! 1926: "xori\\t%0,%1,%x2"
! 1927: [(set_attr "type" "arith")
! 1928: (set_attr "mode" "DI")
! 1929: (set_attr "length" "1")])
! 1930:
1.1 root 1931:
1932: ;;
1933: ;; ....................
1934: ;;
1935: ;; TRUNCATION
1936: ;;
1937: ;; ....................
1938:
1939: (define_insn "truncdfsf2"
1940: [(set (match_operand:SF 0 "register_operand" "=f")
1941: (float_truncate:SF (match_operand:DF 1 "register_operand" "f")))]
1942: "TARGET_HARD_FLOAT"
1943: "cvt.s.d\\t%0,%1"
1944: [(set_attr "type" "fcvt")
1945: (set_attr "mode" "SF")
1946: (set_attr "length" "1")])
1947:
1.1.1.3 ! root 1948: ;; ??? This should be a define expand.
! 1949: ;; See the zero_extendsidi2 pattern.
! 1950: ;; ??? We tried define expands, but they did not work. Too many shift
! 1951: ;; instructions were optimized away. Perhaps add combiner patterns to
! 1952: ;; recognize cases where shifts and truncates can be combined.
! 1953: (define_insn "truncdisi2"
! 1954: [(set (match_operand:SI 0 "register_operand" "=d")
! 1955: (truncate:SI (match_operand:DI 1 "register_operand" "d")))]
! 1956: "TARGET_64BIT"
! 1957: "dsll\\t%0,%1,32\;dsra\\t%0,%0,32"
! 1958: [(set_attr "type" "darith")
! 1959: (set_attr "mode" "SI")
! 1960: (set_attr "length" "2")])
! 1961:
! 1962: (define_insn "truncdihi2"
! 1963: [(set (match_operand:HI 0 "register_operand" "=d")
! 1964: (truncate:HI (match_operand:DI 1 "register_operand" "d")))]
! 1965: "TARGET_64BIT"
! 1966: "andi\\t%0,%1,0xffff"
! 1967: [(set_attr "type" "darith")
! 1968: (set_attr "mode" "HI")
! 1969: (set_attr "length" "1")])
! 1970:
! 1971: (define_insn "truncdiqi2"
! 1972: [(set (match_operand:QI 0 "register_operand" "=d")
! 1973: (truncate:QI (match_operand:DI 1 "register_operand" "d")))]
! 1974: "TARGET_64BIT"
! 1975: "andi\\t%0,%1,0x00ff"
! 1976: [(set_attr "type" "darith")
! 1977: (set_attr "mode" "QI")
! 1978: (set_attr "length" "1")])
1.1 root 1979:
1980: ;;
1981: ;; ....................
1982: ;;
1983: ;; ZERO EXTENSION
1984: ;;
1985: ;; ....................
1986:
1987: ;; Extension insns.
1.1.1.3 ! root 1988: ;; Those for integer source operand are ordered widest source type first.
! 1989:
! 1990: (define_expand "zero_extendsidi2"
! 1991: [(set (match_operand:DI 0 "register_operand" "")
! 1992: (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
! 1993: "TARGET_64BIT"
! 1994: "
! 1995: {
! 1996: if (optimize && GET_CODE (operands[1]) == MEM)
! 1997: operands[1] = force_not_mem (operands[1]);
! 1998:
! 1999: if (GET_CODE (operands[1]) != MEM)
! 2000: {
! 2001: rtx op1 = gen_lowpart (DImode, operands[1]);
! 2002: rtx temp = gen_reg_rtx (DImode);
! 2003: rtx shift = gen_rtx (CONST_INT, VOIDmode, 32);
! 2004:
! 2005: emit_insn (gen_ashldi3 (temp, op1, shift));
! 2006: emit_insn (gen_lshrdi3 (operands[0], temp, shift));
! 2007: DONE;
! 2008: }
! 2009: }")
! 2010:
! 2011: (define_insn "zero_extendsidi2_internal"
! 2012: [(set (match_operand:DI 0 "register_operand" "=d,d")
! 2013: (zero_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))]
! 2014: "TARGET_64BIT"
! 2015: "* return mips_move_1word (operands, insn, TRUE);"
! 2016: [(set_attr "type" "load")
! 2017: (set_attr "mode" "DI")
! 2018: (set_attr "length" "1,2")])
1.1 root 2019:
2020: (define_insn "zero_extendhisi2"
2021: [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2022: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
2023: ""
2024: "*
2025: {
2026: if (which_alternative == 0)
2027: return \"andi\\t%0,%1,0xffff\";
2028: else
2029: return mips_move_1word (operands, insn, TRUE);
2030: }"
2031: [(set_attr "type" "arith,load,load")
2032: (set_attr "mode" "SI")
2033: (set_attr "length" "1,1,2")])
2034:
1.1.1.3 ! root 2035: (define_insn "zero_extendhidi2"
! 2036: [(set (match_operand:DI 0 "register_operand" "=d,d,d")
! 2037: (zero_extend:DI (match_operand:HI 1 "nonimmediate_operand" "d,R,m")))]
! 2038: "TARGET_64BIT"
! 2039: "*
! 2040: {
! 2041: if (which_alternative == 0)
! 2042: return \"andi\\t%0,%1,0xffff\";
! 2043: else
! 2044: return mips_move_1word (operands, insn, TRUE);
! 2045: }"
! 2046: [(set_attr "type" "arith,load,load")
! 2047: (set_attr "mode" "DI")
! 2048: (set_attr "length" "1,1,2")])
! 2049:
1.1 root 2050: (define_insn "zero_extendqihi2"
2051: [(set (match_operand:HI 0 "register_operand" "=d,d,d")
2052: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
2053: ""
2054: "*
2055: {
2056: if (which_alternative == 0)
2057: return \"andi\\t%0,%1,0x00ff\";
2058: else
2059: return mips_move_1word (operands, insn, TRUE);
2060: }"
2061: [(set_attr "type" "arith,load,load")
2062: (set_attr "mode" "HI")
2063: (set_attr "length" "1,1,2")])
2064:
2065: (define_insn "zero_extendqisi2"
2066: [(set (match_operand:SI 0 "register_operand" "=d,d,d")
2067: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
2068: ""
2069: "*
2070: {
2071: if (which_alternative == 0)
2072: return \"andi\\t%0,%1,0x00ff\";
2073: else
2074: return mips_move_1word (operands, insn, TRUE);
2075: }"
2076: [(set_attr "type" "arith,load,load")
2077: (set_attr "mode" "SI")
2078: (set_attr "length" "1,1,2")])
2079:
1.1.1.3 ! root 2080: (define_insn "zero_extendqidi2"
! 2081: [(set (match_operand:DI 0 "register_operand" "=d,d,d")
! 2082: (zero_extend:DI (match_operand:QI 1 "nonimmediate_operand" "d,R,m")))]
! 2083: "TARGET_64BIT"
! 2084: "*
! 2085: {
! 2086: if (which_alternative == 0)
! 2087: return \"andi\\t%0,%1,0x00ff\";
! 2088: else
! 2089: return mips_move_1word (operands, insn, TRUE);
! 2090: }"
! 2091: [(set_attr "type" "arith,load,load")
! 2092: (set_attr "mode" "DI")
! 2093: (set_attr "length" "1,1,2")])
! 2094:
1.1 root 2095:
2096: ;;
2097: ;; ....................
2098: ;;
2099: ;; SIGN EXTENSION
2100: ;;
2101: ;; ....................
2102:
2103: ;; Extension insns.
1.1.1.3 ! root 2104: ;; Those for integer source operand are ordered widest source type first.
! 2105:
! 2106: (define_expand "extendsidi2"
! 2107: [(set (match_operand:DI 0 "register_operand" "")
! 2108: (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))]
! 2109: "TARGET_64BIT"
! 2110: "
! 2111: {
! 2112: if (optimize && GET_CODE (operands[1]) == MEM)
! 2113: operands[1] = force_not_mem (operands[1]);
! 2114:
! 2115: if (GET_CODE (operands[1]) != MEM)
! 2116: {
! 2117: rtx op1 = gen_lowpart (DImode, operands[1]);
! 2118: rtx temp = gen_reg_rtx (DImode);
! 2119: rtx shift = gen_rtx (CONST_INT, VOIDmode, 32);
! 2120:
! 2121: emit_insn (gen_ashldi3 (temp, op1, shift));
! 2122: emit_insn (gen_ashrdi3 (operands[0], temp, shift));
! 2123: DONE;
! 2124: }
! 2125: }")
! 2126:
! 2127: (define_insn "extendsidi2_internal"
! 2128: [(set (match_operand:DI 0 "register_operand" "=d,d")
! 2129: (sign_extend:DI (match_operand:SI 1 "memory_operand" "R,m")))]
! 2130: "TARGET_64BIT"
! 2131: "* return mips_move_1word (operands, insn, FALSE);"
! 2132: [(set_attr "type" "load")
! 2133: (set_attr "mode" "DI")
! 2134: (set_attr "length" "1,2")])
1.1 root 2135:
2136: ;; These patterns originally accepted general_operands, however, slightly
2137: ;; better code is generated by only accepting register_operands, and then
2138: ;; letting combine generate the lh and lb insns.
2139:
1.1.1.3 ! root 2140: (define_expand "extendhidi2"
! 2141: [(set (match_operand:DI 0 "register_operand" "")
! 2142: (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))]
! 2143: "TARGET_64BIT"
! 2144: "
! 2145: {
! 2146: if (optimize && GET_CODE (operands[1]) == MEM)
! 2147: operands[1] = force_not_mem (operands[1]);
! 2148:
! 2149: if (GET_CODE (operands[1]) != MEM)
! 2150: {
! 2151: rtx op1 = gen_lowpart (DImode, operands[1]);
! 2152: rtx temp = gen_reg_rtx (DImode);
! 2153: rtx shift = gen_rtx (CONST_INT, VOIDmode, 48);
! 2154:
! 2155: emit_insn (gen_ashldi3 (temp, op1, shift));
! 2156: emit_insn (gen_ashrdi3 (operands[0], temp, shift));
! 2157: DONE;
! 2158: }
! 2159: }")
! 2160:
! 2161: (define_insn "extendhidi2_internal"
! 2162: [(set (match_operand:DI 0 "register_operand" "=d,d")
! 2163: (sign_extend:DI (match_operand:HI 1 "memory_operand" "R,m")))]
! 2164: "TARGET_64BIT"
! 2165: "* return mips_move_1word (operands, insn, FALSE);"
! 2166: [(set_attr "type" "load")
! 2167: (set_attr "mode" "DI")
! 2168: (set_attr "length" "1,2")])
! 2169:
1.1 root 2170: (define_expand "extendhisi2"
2171: [(set (match_operand:SI 0 "register_operand" "")
2172: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "")))]
2173: ""
2174: "
2175: {
2176: if (optimize && GET_CODE (operands[1]) == MEM)
2177: operands[1] = force_not_mem (operands[1]);
2178:
2179: if (GET_CODE (operands[1]) != MEM)
2180: {
2181: rtx op1 = gen_lowpart (SImode, operands[1]);
2182: rtx temp = gen_reg_rtx (SImode);
2183: rtx shift = gen_rtx (CONST_INT, VOIDmode, 16);
2184:
2185: emit_insn (gen_ashlsi3 (temp, op1, shift));
2186: emit_insn (gen_ashrsi3 (operands[0], temp, shift));
2187: DONE;
2188: }
2189: }")
2190:
2191: (define_insn "extendhisi2_internal"
2192: [(set (match_operand:SI 0 "register_operand" "=d,d")
2193: (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,m")))]
2194: ""
2195: "* return mips_move_1word (operands, insn, FALSE);"
2196: [(set_attr "type" "load")
2197: (set_attr "mode" "SI")
2198: (set_attr "length" "1,2")])
2199:
2200: (define_expand "extendqihi2"
2201: [(set (match_operand:HI 0 "register_operand" "")
2202: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "")))]
2203: ""
2204: "
2205: {
2206: if (optimize && GET_CODE (operands[1]) == MEM)
2207: operands[1] = force_not_mem (operands[1]);
2208:
2209: if (GET_CODE (operands[1]) != MEM)
2210: {
2211: rtx op0 = gen_lowpart (SImode, operands[0]);
2212: rtx op1 = gen_lowpart (SImode, operands[1]);
2213: rtx temp = gen_reg_rtx (SImode);
2214: rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
2215:
2216: emit_insn (gen_ashlsi3 (temp, op1, shift));
2217: emit_insn (gen_ashrsi3 (op0, temp, shift));
2218: DONE;
2219: }
2220: }")
2221:
2222: (define_insn "extendqihi2_internal"
2223: [(set (match_operand:HI 0 "register_operand" "=d,d")
2224: (sign_extend:HI (match_operand:QI 1 "memory_operand" "R,m")))]
2225: ""
2226: "* return mips_move_1word (operands, insn, FALSE);"
2227: [(set_attr "type" "load")
2228: (set_attr "mode" "SI")
2229: (set_attr "length" "1,2")])
2230:
2231:
2232: (define_expand "extendqisi2"
2233: [(set (match_operand:SI 0 "register_operand" "")
2234: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
2235: ""
2236: "
2237: {
2238: if (optimize && GET_CODE (operands[1]) == MEM)
2239: operands[1] = force_not_mem (operands[1]);
2240:
2241: if (GET_CODE (operands[1]) != MEM)
2242: {
2243: rtx op1 = gen_lowpart (SImode, operands[1]);
2244: rtx temp = gen_reg_rtx (SImode);
2245: rtx shift = gen_rtx (CONST_INT, VOIDmode, 24);
2246:
2247: emit_insn (gen_ashlsi3 (temp, op1, shift));
2248: emit_insn (gen_ashrsi3 (operands[0], temp, shift));
2249: DONE;
2250: }
2251: }")
2252:
2253: (define_insn "extendqisi2_insn"
2254: [(set (match_operand:SI 0 "register_operand" "=d,d")
2255: (sign_extend:SI (match_operand:QI 1 "memory_operand" "R,m")))]
2256: ""
2257: "* return mips_move_1word (operands, insn, FALSE);"
2258: [(set_attr "type" "load")
2259: (set_attr "mode" "SI")
2260: (set_attr "length" "1,2")])
2261:
1.1.1.3 ! root 2262: (define_expand "extendqidi2"
! 2263: [(set (match_operand:DI 0 "register_operand" "")
! 2264: (sign_extend:DI (match_operand:QI 1 "nonimmediate_operand" "")))]
! 2265: "TARGET_64BIT"
! 2266: "
! 2267: {
! 2268: if (optimize && GET_CODE (operands[1]) == MEM)
! 2269: operands[1] = force_not_mem (operands[1]);
! 2270:
! 2271: if (GET_CODE (operands[1]) != MEM)
! 2272: {
! 2273: rtx op1 = gen_lowpart (DImode, operands[1]);
! 2274: rtx temp = gen_reg_rtx (DImode);
! 2275: rtx shift = gen_rtx (CONST_INT, VOIDmode, 56);
! 2276:
! 2277: emit_insn (gen_ashldi3 (temp, op1, shift));
! 2278: emit_insn (gen_ashrdi3 (operands[0], temp, shift));
! 2279: DONE;
! 2280: }
! 2281: }")
! 2282:
! 2283: (define_insn "extendqidi2_insn"
! 2284: [(set (match_operand:DI 0 "register_operand" "=d,d")
! 2285: (sign_extend:DI (match_operand:QI 1 "memory_operand" "R,m")))]
! 2286: "TARGET_64BIT"
! 2287: "* return mips_move_1word (operands, insn, FALSE);"
! 2288: [(set_attr "type" "load")
! 2289: (set_attr "mode" "DI")
! 2290: (set_attr "length" "1,2")])
! 2291:
1.1 root 2292:
2293: (define_insn "extendsfdf2"
2294: [(set (match_operand:DF 0 "register_operand" "=f")
2295: (float_extend:DF (match_operand:SF 1 "register_operand" "f")))]
2296: "TARGET_HARD_FLOAT"
2297: "cvt.d.s\\t%0,%1"
2298: [(set_attr "type" "fcvt")
2299: (set_attr "mode" "DF")
2300: (set_attr "length" "1")])
2301:
2302:
2303:
2304: ;;
2305: ;; ....................
2306: ;;
2307: ;; CONVERSIONS
2308: ;;
2309: ;; ....................
2310:
1.1.1.2 root 2311: ;; The SImode scratch register can not be shared with address regs used for
2312: ;; operand zero, because then the address in the move instruction will be
2313: ;; clobbered. We mark the scratch register as early clobbered to prevent this.
2314:
1.1 root 2315: (define_insn "fix_truncdfsi2"
2316: [(set (match_operand:SI 0 "general_operand" "=d,*f,R,o")
2317: (fix:SI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
1.1.1.2 root 2318: (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
1.1 root 2319: (clobber (match_scratch:DF 3 "=f,*X,f,f"))]
2320: "TARGET_HARD_FLOAT"
2321: "*
2322: {
2323: rtx xoperands[10];
2324:
2325: if (which_alternative == 1)
2326: return \"trunc.w.d %0,%1,%2\";
2327:
2328: output_asm_insn (\"trunc.w.d %3,%1,%2\", operands);
2329:
2330: xoperands[0] = operands[0];
2331: xoperands[1] = operands[3];
2332: output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
2333: return \"\";
2334: }"
2335: [(set_attr "type" "fcvt")
2336: (set_attr "mode" "DF")
2337: (set_attr "length" "11,9,10,11")])
2338:
2339:
2340: (define_insn "fix_truncsfsi2"
2341: [(set (match_operand:SI 0 "general_operand" "=d,*f,R,o")
2342: (fix:SI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
1.1.1.2 root 2343: (clobber (match_scratch:SI 2 "=d,*d,&d,&d"))
1.1 root 2344: (clobber (match_scratch:SF 3 "=f,*X,f,f"))]
2345: "TARGET_HARD_FLOAT"
2346: "*
2347: {
2348: rtx xoperands[10];
2349:
2350: if (which_alternative == 1)
2351: return \"trunc.w.s %0,%1,%2\";
2352:
2353: output_asm_insn (\"trunc.w.s %3,%1,%2\", operands);
2354:
2355: xoperands[0] = operands[0];
2356: xoperands[1] = operands[3];
2357: output_asm_insn (mips_move_1word (xoperands, insn, FALSE), xoperands);
2358: return \"\";
2359: }"
2360: [(set_attr "type" "fcvt")
2361: (set_attr "mode" "SF")
2362: (set_attr "length" "11,9,10,11")])
2363:
2364:
1.1.1.3 ! root 2365: ;;; ??? trunc.l.d is mentioned in the appendix of the 1993 r4000/r4600 manuals
! 2366: ;;; but not in the chapter that describes the FPU. It is not mentioned at all
! 2367: ;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
! 2368:
! 2369: ;;; Deleting this means that we now need two libgcc2.a libraries. One for
! 2370: ;;; the 32 bit calling convention and one for the 64 bit calling convention.
! 2371:
! 2372: ;;; If this is disabled, then fixuns_truncdfdi2 must be disabled also.
! 2373:
! 2374: (define_insn "fix_truncdfdi2"
! 2375: [(set (match_operand:DI 0 "general_operand" "=d,*f,R,o")
! 2376: (fix:DI (match_operand:DF 1 "register_operand" "f,*f,f,f")))
! 2377: (clobber (match_scratch:DF 2 "=f,*X,f,f"))]
! 2378: "TARGET_HARD_FLOAT && TARGET_64BIT"
! 2379: "*
! 2380: {
! 2381: rtx xoperands[10];
! 2382:
! 2383: if (which_alternative == 1)
! 2384: return \"trunc.l.d %0,%1\";
! 2385:
! 2386: output_asm_insn (\"trunc.l.d %2,%1\", operands);
! 2387:
! 2388: xoperands[0] = operands[0];
! 2389: xoperands[1] = operands[2];
! 2390: output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands);
! 2391: return \"\";
! 2392: }"
! 2393: [(set_attr "type" "fcvt")
! 2394: (set_attr "mode" "DF")
! 2395: (set_attr "length" "2,1,2,3")])
! 2396:
! 2397:
! 2398: ;;; ??? trunc.l.s is mentioned in the appendix of the 1993 r4000/r4600 manuals
! 2399: ;;; but not in the chapter that describes the FPU. It is not mentioned at all
! 2400: ;;; in the 1991 manuals. The r4000 at Cygnus does not have this instruction.
! 2401: (define_insn "fix_truncsfdi2"
! 2402: [(set (match_operand:DI 0 "general_operand" "=d,*f,R,o")
! 2403: (fix:DI (match_operand:SF 1 "register_operand" "f,*f,f,f")))
! 2404: (clobber (match_scratch:DF 2 "=f,*X,f,f"))]
! 2405: "TARGET_HARD_FLOAT && TARGET_64BIT"
! 2406: "*
! 2407: {
! 2408: rtx xoperands[10];
! 2409:
! 2410: if (which_alternative == 1)
! 2411: return \"trunc.l.s %0,%1\";
! 2412:
! 2413: output_asm_insn (\"trunc.l.s %2,%1\", operands);
! 2414:
! 2415: xoperands[0] = operands[0];
! 2416: xoperands[1] = operands[2];
! 2417: output_asm_insn (mips_move_2words (xoperands, insn, FALSE), xoperands);
! 2418: return \"\";
! 2419: }"
! 2420: [(set_attr "type" "fcvt")
! 2421: (set_attr "mode" "SF")
! 2422: (set_attr "length" "2,1,2,3")])
! 2423:
! 2424:
1.1 root 2425: (define_insn "floatsidf2"
2426: [(set (match_operand:DF 0 "register_operand" "=f,f,f")
2427: (float:DF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
2428: "TARGET_HARD_FLOAT"
2429: "*
2430: {
2431: dslots_load_total++;
2432: if (GET_CODE (operands[1]) == MEM)
2433: return \"l.s\\t%0,%1%#\;cvt.d.w\\t%0,%0\";
2434:
2435: return \"mtc1\\t%1,%0%#\;cvt.d.w\\t%0,%0\";
2436: }"
2437: [(set_attr "type" "fcvt")
2438: (set_attr "mode" "DF")
2439: (set_attr "length" "3,4,3")])
2440:
2441:
1.1.1.3 ! root 2442: (define_insn "floatdidf2"
! 2443: [(set (match_operand:DF 0 "register_operand" "=f,f,f")
! 2444: (float:DF (match_operand:DI 1 "nonimmediate_operand" "d,R,m")))]
! 2445: "TARGET_HARD_FLOAT && TARGET_64BIT"
! 2446: "*
! 2447: {
! 2448: dslots_load_total++;
! 2449: if (GET_CODE (operands[1]) == MEM)
! 2450: return \"l.d\\t%0,%1%#\;cvt.d.l\\t%0,%0\";
! 2451:
! 2452: return \"dmtc1\\t%1,%0%#\;cvt.d.l\\t%0,%0\";
! 2453: }"
! 2454: [(set_attr "type" "fcvt")
! 2455: (set_attr "mode" "DF")
! 2456: (set_attr "length" "3,4,3")])
! 2457:
! 2458:
1.1 root 2459: (define_insn "floatsisf2"
2460: [(set (match_operand:SF 0 "register_operand" "=f,f,f")
2461: (float:SF (match_operand:SI 1 "nonimmediate_operand" "d,R,m")))]
2462: "TARGET_HARD_FLOAT"
2463: "*
2464: {
2465: dslots_load_total++;
2466: if (GET_CODE (operands[1]) == MEM)
2467: return \"l.s\\t%0,%1%#\;cvt.s.w\\t%0,%0\";
2468:
2469: return \"mtc1\\t%1,%0%#\;cvt.s.w\\t%0,%0\";
2470: }"
2471: [(set_attr "type" "fcvt")
2472: (set_attr "mode" "SF")
2473: (set_attr "length" "3,4,3")])
2474:
2475:
1.1.1.3 ! root 2476: (define_insn "floatdisf2"
! 2477: [(set (match_operand:SF 0 "register_operand" "=f,f,f")
! 2478: (float:SF (match_operand:DI 1 "nonimmediate_operand" "d,R,m")))]
! 2479: "TARGET_HARD_FLOAT && TARGET_64BIT"
! 2480: "*
! 2481: {
! 2482: dslots_load_total++;
! 2483: if (GET_CODE (operands[1]) == MEM)
! 2484: return \"l.d\\t%0,%1%#\;cvt.s.l\\t%0,%0\";
! 2485:
! 2486: return \"dmtc1\\t%1,%0%#\;cvt.s.l\\t%0,%0\";
! 2487: }"
! 2488: [(set_attr "type" "fcvt")
! 2489: (set_attr "mode" "SF")
! 2490: (set_attr "length" "3,4,3")])
! 2491:
! 2492:
1.1 root 2493: (define_expand "fixuns_truncdfsi2"
2494: [(set (match_operand:SI 0 "register_operand" "")
2495: (unsigned_fix:SI (match_operand:DF 1 "register_operand" "")))]
2496: "TARGET_HARD_FLOAT"
2497: "
2498: {
2499: rtx reg1 = gen_reg_rtx (DFmode);
2500: rtx reg2 = gen_reg_rtx (DFmode);
2501: rtx reg3 = gen_reg_rtx (SImode);
2502: rtx label1 = gen_label_rtx ();
2503: rtx label2 = gen_label_rtx ();
2504: REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
2505:
2506: if (reg1) /* turn off complaints about unreached code */
2507: {
2508: emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
2509: do_pending_stack_adjust ();
2510:
2511: emit_insn (gen_cmpdf (operands[1], reg1));
2512: emit_jump_insn (gen_bge (label1));
2513:
2514: emit_insn (gen_fix_truncdfsi2 (operands[0], operands[1]));
2515: emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
2516: gen_rtx (LABEL_REF, VOIDmode, label2)));
2517: emit_barrier ();
2518:
2519: emit_label (label1);
2520: emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
2521: emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
2522:
2523: emit_insn (gen_fix_truncdfsi2 (operands[0], reg2));
2524: emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2525:
2526: emit_label (label2);
2527:
2528: /* allow REG_NOTES to be set on last insn (labels don't have enough
2529: fields, and can't be used for REG_NOTES anyway). */
2530: emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
2531: DONE;
2532: }
2533: }")
2534:
2535:
1.1.1.3 ! root 2536: (define_expand "fixuns_truncdfdi2"
! 2537: [(set (match_operand:DI 0 "register_operand" "")
! 2538: (unsigned_fix:DI (match_operand:DF 1 "register_operand" "")))]
! 2539: "TARGET_HARD_FLOAT && TARGET_64BIT"
! 2540: "
! 2541: {
! 2542: rtx reg1 = gen_reg_rtx (DFmode);
! 2543: rtx reg2 = gen_reg_rtx (DFmode);
! 2544: rtx reg3 = gen_reg_rtx (DImode);
! 2545: rtx label1 = gen_label_rtx ();
! 2546: rtx label2 = gen_label_rtx ();
! 2547: REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
! 2548:
! 2549: if (reg1) /* turn off complaints about unreached code */
! 2550: {
! 2551: emit_move_insn (reg1, immed_real_const_1 (offset, DFmode));
! 2552: do_pending_stack_adjust ();
! 2553:
! 2554: emit_insn (gen_cmpdf (operands[1], reg1));
! 2555: emit_jump_insn (gen_bge (label1));
! 2556:
! 2557: emit_insn (gen_fix_truncdfdi2 (operands[0], operands[1]));
! 2558: emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
! 2559: gen_rtx (LABEL_REF, VOIDmode, label2)));
! 2560: emit_barrier ();
! 2561:
! 2562: emit_label (label1);
! 2563: emit_move_insn (reg2, gen_rtx (MINUS, DFmode, operands[1], reg1));
! 2564: emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
! 2565: emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
! 2566:
! 2567: emit_insn (gen_fix_truncdfdi2 (operands[0], reg2));
! 2568: emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
! 2569:
! 2570: emit_label (label2);
! 2571:
! 2572: /* allow REG_NOTES to be set on last insn (labels don't have enough
! 2573: fields, and can't be used for REG_NOTES anyway). */
! 2574: emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
! 2575: DONE;
! 2576: }
! 2577: }")
! 2578:
! 2579:
1.1 root 2580: (define_expand "fixuns_truncsfsi2"
2581: [(set (match_operand:SI 0 "register_operand" "")
2582: (unsigned_fix:SI (match_operand:SF 1 "register_operand" "")))]
2583: "TARGET_HARD_FLOAT"
2584: "
2585: {
2586: rtx reg1 = gen_reg_rtx (SFmode);
2587: rtx reg2 = gen_reg_rtx (SFmode);
2588: rtx reg3 = gen_reg_rtx (SImode);
2589: rtx label1 = gen_label_rtx ();
2590: rtx label2 = gen_label_rtx ();
2591: REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 31);
2592:
2593: if (reg1) /* turn off complaints about unreached code */
2594: {
2595: emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
2596: do_pending_stack_adjust ();
2597:
2598: emit_insn (gen_cmpsf (operands[1], reg1));
2599: emit_jump_insn (gen_bge (label1));
2600:
2601: emit_insn (gen_fix_truncsfsi2 (operands[0], operands[1]));
2602: emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
2603: gen_rtx (LABEL_REF, VOIDmode, label2)));
2604: emit_barrier ();
2605:
2606: emit_label (label1);
2607: emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
2608: emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
2609:
2610: emit_insn (gen_fix_truncsfsi2 (operands[0], reg2));
2611: emit_insn (gen_iorsi3 (operands[0], operands[0], reg3));
2612:
2613: emit_label (label2);
2614:
2615: /* allow REG_NOTES to be set on last insn (labels don't have enough
2616: fields, and can't be used for REG_NOTES anyway). */
2617: emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
2618: DONE;
2619: }
2620: }")
2621:
1.1.1.3 ! root 2622:
! 2623: (define_expand "fixuns_truncsfdi2"
! 2624: [(set (match_operand:DI 0 "register_operand" "")
! 2625: (unsigned_fix:DI (match_operand:SF 1 "register_operand" "")))]
! 2626: "TARGET_HARD_FLOAT && TARGET_64BIT"
! 2627: "
! 2628: {
! 2629: rtx reg1 = gen_reg_rtx (SFmode);
! 2630: rtx reg2 = gen_reg_rtx (SFmode);
! 2631: rtx reg3 = gen_reg_rtx (DImode);
! 2632: rtx label1 = gen_label_rtx ();
! 2633: rtx label2 = gen_label_rtx ();
! 2634: REAL_VALUE_TYPE offset = REAL_VALUE_LDEXP (1.0, 63);
! 2635:
! 2636: if (reg1) /* turn off complaints about unreached code */
! 2637: {
! 2638: emit_move_insn (reg1, immed_real_const_1 (offset, SFmode));
! 2639: do_pending_stack_adjust ();
! 2640:
! 2641: emit_insn (gen_cmpsf (operands[1], reg1));
! 2642: emit_jump_insn (gen_bge (label1));
! 2643:
! 2644: emit_insn (gen_fix_truncsfdi2 (operands[0], operands[1]));
! 2645: emit_jump_insn (gen_rtx (SET, VOIDmode, pc_rtx,
! 2646: gen_rtx (LABEL_REF, VOIDmode, label2)));
! 2647: emit_barrier ();
! 2648:
! 2649: emit_label (label1);
! 2650: emit_move_insn (reg2, gen_rtx (MINUS, SFmode, operands[1], reg1));
! 2651: emit_move_insn (reg3, gen_rtx (CONST_INT, VOIDmode, 0x80000000));
! 2652: emit_insn (gen_ashldi3 (reg3, reg3, GEN_INT (32)));
! 2653:
! 2654: emit_insn (gen_fix_truncsfdi2 (operands[0], reg2));
! 2655: emit_insn (gen_iordi3 (operands[0], operands[0], reg3));
! 2656:
! 2657: emit_label (label2);
! 2658:
! 2659: /* allow REG_NOTES to be set on last insn (labels don't have enough
! 2660: fields, and can't be used for REG_NOTES anyway). */
! 2661: emit_insn (gen_rtx (USE, VOIDmode, stack_pointer_rtx));
! 2662: DONE;
! 2663: }
! 2664: }")
! 2665:
1.1 root 2666:
2667: ;;
2668: ;; ....................
2669: ;;
2670: ;; DATA MOVEMENT
2671: ;;
2672: ;; ....................
2673:
1.1.1.3 ! root 2674: ;; Bit field extract patterns which use lwl/lwr.
! 2675:
! 2676: ;; ??? There should be DImode variants for 64 bit code, but the current
! 2677: ;; bitfield scheme can't handle that. We would need to add new optabs
! 2678: ;; in order to make that work.
! 2679:
! 2680: ;; ??? There could be HImode variants for the ulh/ulhu/ush macros.
! 2681: ;; It isn't clear whether this will give better code.
! 2682:
! 2683: (define_expand "extv"
! 2684: [(set (match_operand:SI 0 "register_operand" "")
! 2685: (sign_extract:SI (match_operand:QI 1 "memory_operand" "")
! 2686: (match_operand:SI 2 "immediate_operand" "")
! 2687: (match_operand:SI 3 "immediate_operand" "")))]
! 2688: ""
! 2689: "
! 2690: {
! 2691: /* If this isn't a 32 bit field, and it doesn't start on a byte boundary
! 2692: then fail. */
! 2693: if (INTVAL (operands[2]) != 32 || (INTVAL (operands[3]) % 8) != 0)
! 2694: FAIL;
! 2695:
! 2696: /* This can happen for a 64 bit target, when extracting a value from
! 2697: a 64 bit union member. extract_bit_field doesn't verify that our
! 2698: source matches the predicate, so we force it to be a MEM here. */
! 2699: if (GET_CODE (operands[1]) != MEM)
! 2700: FAIL;
! 2701:
! 2702: /* Otherwise, emit a lwl/lwr pair to load the value. */
! 2703: emit_insn (gen_movsi_ulw (operands[0], operands[1]));
! 2704: DONE;
! 2705: }")
! 2706:
! 2707: (define_expand "extzv"
! 2708: [(set (match_operand:SI 0 "register_operand" "")
! 2709: (zero_extract:SI (match_operand:QI 1 "memory_operand" "")
! 2710: (match_operand:SI 2 "immediate_operand" "")
! 2711: (match_operand:SI 3 "immediate_operand" "")))]
! 2712: ""
! 2713: "
! 2714: {
! 2715: /* If this isn't a 32 bit field, and it doesn't start on a byte boundary
! 2716: then fail. */
! 2717: if (INTVAL (operands[2]) != 32 || (INTVAL (operands[3]) % 8) != 0)
! 2718: FAIL;
! 2719:
! 2720: /* This can happen for a 64 bit target, when extracting a value from
! 2721: a 64 bit union member. extract_bit_field doesn't verify that our
! 2722: source matches the predicate, so we force it to be a MEM here. */
! 2723: if (GET_CODE (operands[1]) != MEM)
! 2724: FAIL;
! 2725:
! 2726: /* Otherwise, emit a lwl/lwr pair to load the value. */
! 2727: emit_insn (gen_movsi_ulw (operands[0], operands[1]));
! 2728: DONE;
! 2729: }")
1.1 root 2730:
1.1.1.3 ! root 2731: (define_expand "insv"
! 2732: [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "")
! 2733: (match_operand:SI 1 "immediate_operand" "")
! 2734: (match_operand:SI 2 "immediate_operand" ""))
! 2735: (match_operand:SI 3 "register_operand" ""))]
1.1 root 2736: ""
2737: "
2738: {
1.1.1.3 ! root 2739: /* If this isn't a 32 bit field, and it doesn't start on a byte boundary
! 2740: then fail. */
! 2741: if (INTVAL (operands[1]) != 32 || (INTVAL (operands[2]) % 8) != 0)
! 2742: FAIL;
1.1 root 2743:
1.1.1.3 ! root 2744: /* This can happen for a 64 bit target, when storing into a 32 bit union
! 2745: member. store_bit_field doesn't verify that our target matches the
! 2746: predicate, so we force it to be a MEM here. */
! 2747: if (GET_CODE (operands[0]) != MEM)
! 2748: FAIL;
1.1 root 2749:
1.1.1.3 ! root 2750: /* Otherwise, emit a swl/swr pair to load the value. */
! 2751: emit_insn (gen_movsi_usw (operands[0], operands[3]));
! 2752: DONE;
1.1 root 2753: }")
2754:
1.1.1.3 ! root 2755: ;; unaligned word moves generated by the bit field patterns
! 2756:
1.1 root 2757: (define_insn "movsi_ulw"
1.1.1.3 ! root 2758: [(set (match_operand:SI 0 "register_operand" "=&d,&d")
! 2759: (unspec [(match_operand:QI 1 "general_operand" "R,o")] 0))]
1.1 root 2760: ""
2761: "*
2762: {
1.1.1.3 ! root 2763: rtx offset = const0_rtx;
! 2764: rtx addr = XEXP (operands[1], 0);
! 2765: rtx mem_addr = eliminate_constant_term (addr, &offset);
1.1 root 2766: char *ret;
2767:
2768: if (TARGET_STATS)
2769: mips_count_memory_refs (operands[1], 2);
2770:
2771: /* The stack/frame pointers are always aligned, so we can convert
2772: to the faster lw if we are referencing an aligned stack location. */
2773:
1.1.1.3 ! root 2774: if ((INTVAL (offset) & 3) == 0
1.1 root 2775: && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
2776: ret = \"lw\\t%0,%1\";
2777: else
1.1.1.3 ! root 2778: ret = \"ulw\\t%0,%1\";
1.1 root 2779:
2780: return mips_fill_delay_slot (ret, DELAY_LOAD, operands, insn);
2781: }"
1.1.1.3 ! root 2782: [(set_attr "type" "load,load")
1.1 root 2783: (set_attr "mode" "SI")
1.1.1.3 ! root 2784: (set_attr "length" "2,4")])
1.1 root 2785:
2786: (define_insn "movsi_usw"
1.1.1.3 ! root 2787: [(set (match_operand:QI 0 "memory_operand" "=R,o")
! 2788: (unspec [(match_operand:SI 1 "reg_or_0_operand" "dJ,dJ")] 1))]
1.1 root 2789: ""
2790: "*
2791: {
2792: rtx offset = const0_rtx;
2793: rtx addr = XEXP (operands[0], 0);
2794: rtx mem_addr = eliminate_constant_term (addr, &offset);
2795:
2796: if (TARGET_STATS)
2797: mips_count_memory_refs (operands[0], 2);
2798:
2799: /* The stack/frame pointers are always aligned, so we can convert
2800: to the faster sw if we are referencing an aligned stack location. */
2801:
1.1.1.3 ! root 2802: if ((INTVAL (offset) & 3) == 0
1.1 root 2803: && (mem_addr == stack_pointer_rtx || mem_addr == frame_pointer_rtx))
2804: return \"sw\\t%1,%0\";
2805:
2806: return \"usw\\t%z1,%0\";
2807: }"
2808: [(set_attr "type" "store")
2809: (set_attr "mode" "SI")
2810: (set_attr "length" "2,4")])
2811:
2812: ;; 64-bit integer moves
2813:
2814: ;; Unlike most other insns, the move insns can't be split with
2815: ;; different predicates, because register spilling and other parts of
2816: ;; the compiler, have memoized the insn number already.
2817:
2818: (define_expand "movdi"
2819: [(set (match_operand:DI 0 "nonimmediate_operand" "")
2820: (match_operand:DI 1 "general_operand" ""))]
2821: ""
2822: "
2823: {
2824: if ((reload_in_progress | reload_completed) == 0
2825: && !register_operand (operands[0], DImode)
2826: && !register_operand (operands[1], DImode)
2827: && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
2828: && operands[1] != CONST0_RTX (DImode))
2829: {
2830: rtx temp = force_reg (DImode, operands[1]);
2831: emit_move_insn (operands[0], temp);
2832: DONE;
2833: }
2834: }")
2835:
2836: (define_insn "movdi_internal"
2837: [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,R,o,*d,*x")
2838: (match_operand:DI 1 "general_operand" "d,iF,R,o,d,d,*x,*d"))]
1.1.1.3 ! root 2839: "!TARGET_64BIT
! 2840: && (register_operand (operands[0], DImode)
! 2841: || register_operand (operands[1], DImode)
! 2842: || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
! 2843: || operands[1] == CONST0_RTX (DImode))"
1.1 root 2844: "* return mips_move_2words (operands, insn); "
2845: [(set_attr "type" "move,arith,load,load,store,store,hilo,hilo")
2846: (set_attr "mode" "DI")
1.1.1.3 ! root 2847: (set_attr "length" "2,4,2,4,2,4,2,2")])
1.1 root 2848:
2849: (define_split
2850: [(set (match_operand:DI 0 "register_operand" "")
2851: (match_operand:DI 1 "register_operand" ""))]
1.1.1.3 ! root 2852: "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 2853: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
2854: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
2855:
2856: [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
2857: (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
2858: "")
2859:
1.1.1.3 ! root 2860: (define_insn "movdi_internal2"
! 2861: [(set (match_operand:DI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*x")
! 2862: (match_operand:DI 1 "general_operand" " d,S,IKL,Mnis,R,m,dJ,dJ,*x,*d"))]
! 2863: "TARGET_64BIT
! 2864: && (register_operand (operands[0], DImode)
! 2865: || register_operand (operands[1], DImode)
! 2866: || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
! 2867: || operands[1] == CONST0_RTX (DImode))"
! 2868: "* return mips_move_2words (operands, insn); "
! 2869: [(set_attr "type" "move,load,arith,arith,load,load,store,store,hilo,hilo")
! 2870: (set_attr "mode" "DI")
! 2871: (set_attr "length" "1,2,1,2,1,2,1,2,1,1")])
! 2872:
1.1 root 2873:
2874: ;; 32-bit Integer moves
2875:
2876: (define_split
2877: [(set (match_operand:SI 0 "register_operand" "")
2878: (match_operand:SI 1 "large_int" ""))]
2879: "!TARGET_DEBUG_D_MODE"
2880: [(set (match_dup 0)
2881: (match_dup 2))
2882: (set (match_dup 0)
2883: (ior:SI (match_dup 0)
2884: (match_dup 3)))]
2885: "
2886: {
2887: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff0000);
2888: operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0x0000ffff);
2889: }")
2890:
2891: ;; Unlike most other insns, the move insns can't be split with
2892: ;; different predicates, because register spilling and other parts of
2893: ;; the compiler, have memoized the insn number already.
2894:
2895: (define_expand "movsi"
2896: [(set (match_operand:SI 0 "nonimmediate_operand" "")
2897: (match_operand:SI 1 "general_operand" ""))]
2898: ""
2899: "
2900: {
1.1.1.3 ! root 2901: /* If we are generating embedded PIC code, and we are referring to a
! 2902: symbol in the .text section, we must use an offset from the start
! 2903: of the function. */
! 2904: if (TARGET_EMBEDDED_PIC
! 2905: && (GET_CODE (operands[1]) == LABEL_REF
! 2906: || (GET_CODE (operands[1]) == SYMBOL_REF
! 2907: && ! SYMBOL_REF_FLAG (operands[1]))))
! 2908: {
! 2909: rtx temp;
! 2910:
! 2911: temp = embedded_pic_offset (operands[1]);
! 2912: temp = gen_rtx (PLUS, Pmode, embedded_pic_fnaddr_rtx,
! 2913: force_reg (SImode, temp));
! 2914: emit_move_insn (operands[0], force_reg (SImode, temp));
! 2915: DONE;
! 2916: }
! 2917:
! 2918: /* If operands[1] is a constant address illegal for pic, then we need to
! 2919: handle it just like LEGITIMIZE_ADDRESS does. */
! 2920: if (flag_pic && pic_address_needs_scratch (operands[1]))
! 2921: {
! 2922: rtx temp = force_reg (SImode, XEXP (XEXP (operands[1], 0), 0));
! 2923: rtx temp2 = XEXP (XEXP (operands[1], 0), 1);
! 2924:
! 2925: if (! SMALL_INT (temp2))
! 2926: temp2 = force_reg (SImode, temp2);
! 2927:
! 2928: emit_move_insn (operands[0], gen_rtx (PLUS, SImode, temp, temp2));
! 2929: DONE;
! 2930: }
! 2931:
1.1 root 2932: if ((reload_in_progress | reload_completed) == 0
2933: && !register_operand (operands[0], SImode)
2934: && !register_operand (operands[1], SImode)
2935: && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0))
2936: {
2937: rtx temp = force_reg (SImode, operands[1]);
2938: emit_move_insn (operands[0], temp);
2939: DONE;
2940: }
2941: }")
2942:
2943: ;; The difference between these two is whether or not ints are allowed
2944: ;; in FP registers (off by default, use -mdebugh to enable).
2945:
2946: (define_insn "movsi_internal1"
2947: [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*f*z,*f,*f,*f,*R,*m,*x,*d")
2948: (match_operand:SI 1 "general_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*f*z,*d,*f,*R,*m,*f,*f,*d,*x"))]
2949: "TARGET_DEBUG_H_MODE
2950: && (register_operand (operands[0], SImode)
2951: || register_operand (operands[1], SImode)
2952: || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
1.1.1.3 ! root 2953: "* return mips_move_1word (operands, insn, FALSE);"
1.1 root 2954: [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,move,load,load,store,store,hilo,hilo")
2955: (set_attr "mode" "SI")
2956: (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1,2,1,2,1,1")])
2957:
2958: (define_insn "movsi_internal2"
2959: [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d,d,R,m,*d,*z,*d,*x")
2960: (match_operand:SI 1 "general_operand" "d,S,IKL,Mnis,R,m,dJ,dJ,*z,*d,*x,*d"))]
2961: "!TARGET_DEBUG_H_MODE
2962: && (register_operand (operands[0], SImode)
2963: || register_operand (operands[1], SImode)
2964: || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
1.1.1.3 ! root 2965: "* return mips_move_1word (operands, insn, FALSE);"
1.1 root 2966: [(set_attr "type" "move,load,arith,arith,load,load,store,store,xfer,xfer,hilo,hilo")
2967: (set_attr "mode" "SI")
2968: (set_attr "length" "1,2,1,2,1,2,1,2,1,1,1,1")])
2969:
2970:
2971: ;; 16-bit Integer moves
2972:
2973: ;; Unlike most other insns, the move insns can't be split with
2974: ;; different predicates, because register spilling and other parts of
2975: ;; the compiler, have memoized the insn number already.
2976: ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
2977:
2978: (define_expand "movhi"
2979: [(set (match_operand:HI 0 "nonimmediate_operand" "")
2980: (match_operand:HI 1 "general_operand" ""))]
2981: ""
2982: "
2983: {
2984: if ((reload_in_progress | reload_completed) == 0
2985: && !register_operand (operands[0], HImode)
2986: && !register_operand (operands[1], HImode)
2987: && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0))
2988: {
2989: rtx temp = force_reg (HImode, operands[1]);
2990: emit_move_insn (operands[0], temp);
2991: DONE;
2992: }
2993: }")
2994:
2995: ;; The difference between these two is whether or not ints are allowed
2996: ;; in FP registers (off by default, use -mdebugh to enable).
2997:
2998: (define_insn "movhi_internal1"
2999: [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f,*f*z,*x,*d")
3000: (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
3001: "TARGET_DEBUG_H_MODE
3002: && (register_operand (operands[0], HImode)
3003: || register_operand (operands[1], HImode)
3004: || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
3005: "* return mips_move_1word (operands, insn, TRUE);"
3006: [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
3007: (set_attr "mode" "HI")
3008: (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")])
3009:
3010: (define_insn "movhi_internal2"
3011: [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
3012: (match_operand:HI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
3013: "!TARGET_DEBUG_H_MODE
3014: && (register_operand (operands[0], HImode)
3015: || register_operand (operands[1], HImode)
3016: || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
3017: "* return mips_move_1word (operands, insn, TRUE);"
3018: [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
3019: (set_attr "mode" "HI")
3020: (set_attr "length" "1,1,1,2,1,2,1,1,1,1")])
3021:
3022:
3023: ;; 8-bit Integer moves
3024:
3025: ;; Unlike most other insns, the move insns can't be split with
3026: ;; different predicates, because register spilling and other parts of
3027: ;; the compiler, have memoized the insn number already.
3028: ;; Unsigned loads are used because BYTE_LOADS_ZERO_EXTEND is defined
3029:
3030: (define_expand "movqi"
3031: [(set (match_operand:QI 0 "nonimmediate_operand" "")
3032: (match_operand:QI 1 "general_operand" ""))]
3033: ""
3034: "
3035: {
3036: if ((reload_in_progress | reload_completed) == 0
3037: && !register_operand (operands[0], QImode)
3038: && !register_operand (operands[1], QImode)
3039: && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0))
3040: {
3041: rtx temp = force_reg (QImode, operands[1]);
3042: emit_move_insn (operands[0], temp);
3043: DONE;
3044: }
3045: }")
3046:
3047: ;; The difference between these two is whether or not ints are allowed
3048: ;; in FP registers (off by default, use -mdebugh to enable).
3049:
3050: (define_insn "movqi_internal1"
3051: [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*f*z,*f,*x,*d")
3052: (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*f*z,*d,*f,*d,*x"))]
3053: "TARGET_DEBUG_H_MODE
3054: && (register_operand (operands[0], QImode)
3055: || register_operand (operands[1], QImode)
3056: || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
3057: "* return mips_move_1word (operands, insn, TRUE);"
3058: [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,move,hilo,hilo")
3059: (set_attr "mode" "QI")
3060: (set_attr "length" "1,1,1,2,1,2,1,1,1,1,1")])
3061:
3062: (define_insn "movqi_internal2"
3063: [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,m,*d,*z,*x,*d")
3064: (match_operand:QI 1 "general_operand" "d,IK,R,m,dJ,dJ,*z,*d,*d,*x"))]
3065: "!TARGET_DEBUG_H_MODE
3066: && (register_operand (operands[0], QImode)
3067: || register_operand (operands[1], QImode)
3068: || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0))"
3069: "* return mips_move_1word (operands, insn, TRUE);"
3070: [(set_attr "type" "move,arith,load,load,store,store,xfer,xfer,hilo,hilo")
3071: (set_attr "mode" "QI")
3072: (set_attr "length" "1,1,1,2,1,2,1,1,1,1")])
3073:
3074:
3075: ;; 32-bit floating point moves
3076:
3077: (define_expand "movsf"
3078: [(set (match_operand:SF 0 "nonimmediate_operand" "")
3079: (match_operand:SF 1 "general_operand" ""))]
3080: ""
3081: "
3082: {
3083: if ((reload_in_progress | reload_completed) == 0
3084: && !register_operand (operands[0], SFmode)
3085: && !register_operand (operands[1], SFmode)
3086: && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
3087: && operands[1] != CONST0_RTX (SFmode))
3088: {
3089: rtx temp = force_reg (SFmode, operands[1]);
3090: emit_move_insn (operands[0], temp);
3091: DONE;
3092: }
3093: }")
3094:
3095: (define_insn "movsf_internal1"
3096: [(set (match_operand:SF 0 "nonimmediate_operand" "=f,f,f,f,R,m,*f,*d,*d,*d,*d,*R,*m")
1.1.1.3 ! root 3097: (match_operand:SF 1 "general_operand" "f,G,R,Fm,fG,fG,*d,*f,*G*d,*R,*F*m,*d,*d"))]
1.1 root 3098: "TARGET_HARD_FLOAT
3099: && (register_operand (operands[0], SFmode)
3100: || register_operand (operands[1], SFmode)
3101: || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
3102: || operands[1] == CONST0_RTX (SFmode))"
3103: "* return mips_move_1word (operands, insn, FALSE);"
3104: [(set_attr "type" "move,xfer,load,load,store,store,xfer,xfer,move,load,load,store,store")
3105: (set_attr "mode" "SF")
3106: (set_attr "length" "1,1,1,2,1,2,1,1,1,1,2,1,2")])
3107:
3108:
3109: (define_insn "movsf_internal2"
3110: [(set (match_operand:SF 0 "nonimmediate_operand" "=d,d,d,R,m")
1.1.1.3 ! root 3111: (match_operand:SF 1 "general_operand" " Gd,R,Fm,d,d"))]
1.1 root 3112: "TARGET_SOFT_FLOAT
3113: && (register_operand (operands[0], SFmode)
3114: || register_operand (operands[1], SFmode)
3115: || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
3116: || operands[1] == CONST0_RTX (SFmode))"
3117: "* return mips_move_1word (operands, insn, FALSE);"
3118: [(set_attr "type" "move,load,load,store,store")
3119: (set_attr "mode" "SF")
3120: (set_attr "length" "1,1,2,1,2")])
3121:
3122:
3123: ;; 64-bit floating point moves
3124:
3125: (define_expand "movdf"
3126: [(set (match_operand:DF 0 "nonimmediate_operand" "")
3127: (match_operand:DF 1 "general_operand" ""))]
3128: ""
3129: "
3130: {
3131: if ((reload_in_progress | reload_completed) == 0
3132: && !register_operand (operands[0], DFmode)
3133: && !register_operand (operands[1], DFmode)
3134: && (GET_CODE (operands[1]) != CONST_INT || INTVAL (operands[1]) != 0)
3135: && operands[1] != CONST0_RTX (DFmode))
3136: {
3137: rtx temp = force_reg (DFmode, operands[1]);
3138: emit_move_insn (operands[0], temp);
3139: DONE;
3140: }
3141: }")
3142:
3143: (define_insn "movdf_internal1"
3144: [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,f,R,o,f,*f,*d,*d,*d,*d,*R,*o")
1.1.1.3 ! root 3145: (match_operand:DF 1 "general_operand" "f,R,o,fG,fG,F,*d,*f,*d*G,*R,*o*F,*d,*d"))]
! 3146: "TARGET_HARD_FLOAT && !(TARGET_FLOAT64 && !TARGET_64BIT)
1.1 root 3147: && (register_operand (operands[0], DFmode)
3148: || register_operand (operands[1], DFmode)
3149: || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
3150: || operands[1] == CONST0_RTX (DFmode))"
3151: "* return mips_move_2words (operands, insn); "
3152: [(set_attr "type" "move,load,load,store,store,load,xfer,xfer,move,load,load,store,store")
3153: (set_attr "mode" "DF")
3154: (set_attr "length" "1,2,4,2,4,4,2,2,2,2,4,2,4")])
3155:
1.1.1.3 ! root 3156: (define_insn "movdf_internal1a"
! 3157: [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f,R,R,o,o,f,*d,*d,*d,*o,*R")
! 3158: (match_operand:DF 1 "general_operand" " f,o,f,G,f,G,F,*F,*o,*R,*d,*d"))]
! 3159: "TARGET_HARD_FLOAT && (TARGET_FLOAT64 && !TARGET_64BIT)
! 3160: && (register_operand (operands[0], DFmode)
! 3161: || register_operand (operands[1], DFmode))
! 3162: || (GET_CODE (operands [0]) == MEM
! 3163: && ((GET_CODE (operands[1]) == CONST_INT
! 3164: && INTVAL (operands[1]) == 0)
! 3165: || operands[1] == CONST0_RTX (DFmode)))"
! 3166: "* return mips_move_2words (operands, insn); "
! 3167: [(set_attr "type" "move,load,store,store,store,store,load,load,load,load,store,store")
! 3168: (set_attr "mode" "DF")
! 3169: (set_attr "length" "1,2,1,1,2,2,2,2,2,1,2,1")])
! 3170:
1.1 root 3171: (define_insn "movdf_internal2"
3172: [(set (match_operand:DF 0 "nonimmediate_operand" "=d,d,d,R,o")
1.1.1.3 ! root 3173: (match_operand:DF 1 "general_operand" "dG,R,oF,d,d"))]
1.1 root 3174: "TARGET_SOFT_FLOAT
3175: && (register_operand (operands[0], DFmode)
3176: || register_operand (operands[1], DFmode)
3177: || (GET_CODE (operands[1]) == CONST_INT && INTVAL (operands[1]) == 0)
3178: || operands[1] == CONST0_RTX (DFmode))"
3179: "* return mips_move_2words (operands, insn); "
3180: [(set_attr "type" "move,load,load,store,store")
3181: (set_attr "mode" "DF")
3182: (set_attr "length" "2,2,4,2,4")])
3183:
3184: (define_split
3185: [(set (match_operand:DF 0 "register_operand" "")
3186: (match_operand:DF 1 "register_operand" ""))]
1.1.1.3 ! root 3187: "reload_completed && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 3188: && GET_CODE (operands[0]) == REG && GP_REG_P (REGNO (operands[0]))
3189: && GET_CODE (operands[1]) == REG && GP_REG_P (REGNO (operands[1]))"
3190: [(set (subreg:SI (match_dup 0) 0) (subreg:SI (match_dup 1) 0))
3191: (set (subreg:SI (match_dup 0) 1) (subreg:SI (match_dup 1) 1))]
3192: "")
3193:
3194:
3195: ;; Block moves, see mips.c for more details.
3196: ;; Argument 0 is the destination
3197: ;; Argument 1 is the source
3198: ;; Argument 2 is the length
3199: ;; Argument 3 is the alignment
3200:
3201: (define_expand "movstrsi"
3202: [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
3203: (mem:BLK (match_operand:BLK 1 "general_operand" "")))
3204: (use (match_operand:SI 2 "arith32_operand" ""))
3205: (use (match_operand:SI 3 "immediate_operand" ""))])]
3206: ""
3207: "
3208: {
3209: if (operands[0]) /* avoid unused code messages */
3210: {
3211: expand_block_move (operands);
3212: DONE;
3213: }
3214: }")
3215:
3216: ;; Insn generated by block moves
3217:
3218: (define_insn "movstrsi_internal"
3219: [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
3220: (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
3221: (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
3222: (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
3223: (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
3224: (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
3225: (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
3226: (use (match_operand:SI 3 "small_int" "I")) ;; alignment
3227: (use (const_int 0))] ;; normal block move
3228: ""
3229: "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NORMAL);"
3230: [(set_attr "type" "multi")
3231: (set_attr "mode" "none")
3232: (set_attr "length" "20")])
3233:
3234: ;; Split a block move into 2 parts, the first part is everything
3235: ;; except for the last move, and the second part is just the last
3236: ;; store, which is exactly 1 instruction (ie, not a usw), so it can
3237: ;; fill a delay slot. This also prevents a bug in delayed branches
3238: ;; from showing up, which reuses one of the registers in our clobbers.
3239:
3240: (define_split
3241: [(set (mem:BLK (match_operand:SI 0 "register_operand" ""))
3242: (mem:BLK (match_operand:SI 1 "register_operand" "")))
3243: (clobber (match_operand:SI 4 "register_operand" ""))
3244: (clobber (match_operand:SI 5 "register_operand" ""))
3245: (clobber (match_operand:SI 6 "register_operand" ""))
3246: (clobber (match_operand:SI 7 "register_operand" ""))
3247: (use (match_operand:SI 2 "small_int" ""))
3248: (use (match_operand:SI 3 "small_int" ""))
3249: (use (const_int 0))]
3250:
3251: "reload_completed && !TARGET_DEBUG_D_MODE && INTVAL (operands[2]) > 0"
3252:
3253: ;; All but the last move
3254: [(parallel [(set (mem:BLK (match_dup 0))
3255: (mem:BLK (match_dup 1)))
3256: (clobber (match_dup 4))
3257: (clobber (match_dup 5))
3258: (clobber (match_dup 6))
3259: (clobber (match_dup 7))
3260: (use (match_dup 2))
3261: (use (match_dup 3))
3262: (use (const_int 1))])
3263:
3264: ;; The last store, so it can fill a delay slot
3265: (parallel [(set (mem:BLK (match_dup 0))
3266: (mem:BLK (match_dup 1)))
3267: (clobber (match_dup 4))
3268: (clobber (match_dup 5))
3269: (clobber (match_dup 6))
3270: (clobber (match_dup 7))
3271: (use (match_dup 2))
3272: (use (match_dup 3))
3273: (use (const_int 2))])]
3274:
3275: "")
3276:
3277: (define_insn "movstrsi_internal2"
3278: [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
3279: (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
3280: (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
3281: (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
3282: (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
3283: (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
3284: (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
3285: (use (match_operand:SI 3 "small_int" "I")) ;; alignment
3286: (use (const_int 1))] ;; all but last store
3287: ""
3288: "* return output_block_move (insn, operands, 4, BLOCK_MOVE_NOT_LAST);"
3289: [(set_attr "type" "multi")
3290: (set_attr "mode" "none")
3291: (set_attr "length" "20")])
3292:
3293: (define_insn "movstrsi_internal3"
3294: [(set (match_operand:BLK 0 "memory_operand" "=Ro") ;; destination
3295: (match_operand:BLK 1 "memory_operand" "Ro")) ;; source
3296: (clobber (match_scratch:SI 4 "=&d")) ;; temp 1
3297: (clobber (match_scratch:SI 5 "=&d")) ;; temp 2
3298: (clobber (match_scratch:SI 6 "=&d")) ;; temp 3
3299: (clobber (match_scratch:SI 7 "=&d")) ;; temp 4
3300: (use (match_operand:SI 2 "small_int" "I")) ;; # bytes to move
3301: (use (match_operand:SI 3 "small_int" "I")) ;; alignment
1.1.1.3 ! root 3302: (use (const_int 2))] ;; just last store of block move
1.1 root 3303: ""
3304: "* return output_block_move (insn, operands, 4, BLOCK_MOVE_LAST);"
3305: [(set_attr "type" "store")
3306: (set_attr "mode" "none")
3307: (set_attr "length" "1")])
3308:
3309:
3310: ;;
3311: ;; ....................
3312: ;;
3313: ;; SHIFTS
3314: ;;
3315: ;; ....................
3316:
3317: (define_insn "ashlsi3"
3318: [(set (match_operand:SI 0 "register_operand" "=d")
3319: (ashift:SI (match_operand:SI 1 "register_operand" "d")
3320: (match_operand:SI 2 "arith_operand" "dI")))]
3321: ""
3322: "*
3323: {
3324: if (GET_CODE (operands[2]) == CONST_INT)
3325: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
3326:
3327: return \"sll\\t%0,%1,%2\";
3328: }"
3329: [(set_attr "type" "arith")
3330: (set_attr "mode" "SI")
3331: (set_attr "length" "1")])
3332:
3333:
3334: (define_expand "ashldi3"
3335: [(parallel [(set (match_operand:DI 0 "register_operand" "")
3336: (ashift:DI (match_operand:DI 1 "register_operand" "")
3337: (match_operand:SI 2 "arith_operand" "")))
3338: (clobber (match_dup 3))])]
1.1.1.3 ! root 3339: "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
! 3340: "
! 3341: {
! 3342: if (TARGET_64BIT)
! 3343: {
! 3344: emit_insn (gen_ashldi3_internal4 (operands[0], operands[1],
! 3345: operands[2]));
! 3346: DONE;
! 3347: }
! 3348:
! 3349: operands[3] = gen_reg_rtx (SImode);
! 3350: }")
1.1 root 3351:
3352:
3353: (define_insn "ashldi3_internal"
3354: [(set (match_operand:DI 0 "register_operand" "=&d")
3355: (ashift:DI (match_operand:DI 1 "register_operand" "d")
3356: (match_operand:SI 2 "register_operand" "d")))
3357: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 3358: "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
1.1 root 3359: "*
3360: {
3361: operands[4] = const0_rtx;
3362: dslots_jump_total += 3;
3363: dslots_jump_filled += 2;
3364:
3365: return \"sll\\t%3,%2,26\\n\\
3366: \\tbgez\\t%3,1f\\n\\
3367: \\tsll\\t%M0,%L1,%2\\n\\
3368: \\t%(b\\t3f\\n\\
3369: \\tmove\\t%L0,%z4%)\\n\\
3370: \\n\\
3371: 1:\\n\\
3372: \\t%(beq\\t%3,%z4,2f\\n\\
3373: \\tsll\\t%M0,%M1,%2%)\\n\\
3374: \\n\\
3375: \\tsubu\\t%3,%z4,%2\\n\\
3376: \\tsrl\\t%3,%L1,%3\\n\\
3377: \\tor\\t%M0,%M0,%3\\n\\
3378: 2:\\n\\
3379: \\tsll\\t%L0,%L1,%2\\n\\
3380: 3:\";
3381: }"
3382: [(set_attr "type" "darith")
3383: (set_attr "mode" "SI")
3384: (set_attr "length" "12")])
3385:
3386:
3387: (define_insn "ashldi3_internal2"
3388: [(set (match_operand:DI 0 "register_operand" "=d")
3389: (ashift:DI (match_operand:DI 1 "register_operand" "d")
3390: (match_operand:SI 2 "small_int" "IJK")))
3391: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 3392: "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
1.1 root 3393: "*
3394: {
3395: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
3396: operands[4] = const0_rtx;
3397: return \"sll\\t%M0,%L1,%2\;move\\t%L0,%z4\";
3398: }"
3399: [(set_attr "type" "darith")
3400: (set_attr "mode" "DI")
3401: (set_attr "length" "2")])
3402:
3403:
3404: (define_split
3405: [(set (match_operand:DI 0 "register_operand" "")
3406: (ashift:DI (match_operand:DI 1 "register_operand" "")
3407: (match_operand:SI 2 "small_int" "")))
3408: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 3409: "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 3410: && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3411: && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3412: && (INTVAL (operands[2]) & 32) != 0"
3413:
3414: [(set (subreg:SI (match_dup 0) 1) (ashift:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
3415: (set (subreg:SI (match_dup 0) 0) (const_int 0))]
3416:
3417: "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
3418:
3419:
3420: (define_split
3421: [(set (match_operand:DI 0 "register_operand" "")
3422: (ashift:DI (match_operand:DI 1 "register_operand" "")
3423: (match_operand:SI 2 "small_int" "")))
3424: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 3425: "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 3426: && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3427: && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3428: && (INTVAL (operands[2]) & 32) != 0"
3429:
3430: [(set (subreg:SI (match_dup 0) 0) (ashift:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
3431: (set (subreg:SI (match_dup 0) 1) (const_int 0))]
3432:
3433: "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
3434:
3435:
3436: (define_insn "ashldi3_internal3"
3437: [(set (match_operand:DI 0 "register_operand" "=d")
3438: (ashift:DI (match_operand:DI 1 "register_operand" "d")
3439: (match_operand:SI 2 "small_int" "IJK")))
3440: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 3441: "!TARGET_64BIT && !TARGET_DEBUG_G_MODE
1.1 root 3442: && (INTVAL (operands[2]) & 63) < 32
3443: && (INTVAL (operands[2]) & 63) != 0"
3444: "*
3445: {
3446: int amount = INTVAL (operands[2]);
3447:
3448: operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3449: operands[4] = const0_rtx;
3450: operands[5] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3451:
3452: return \"sll\\t%M0,%M1,%2\;srl\\t%3,%L1,%5\;or\\t%M0,%M0,%3\;sll\\t%L0,%L1,%2\";
3453: }"
3454: [(set_attr "type" "darith")
3455: (set_attr "mode" "DI")
3456: (set_attr "length" "4")])
3457:
3458:
3459: (define_split
3460: [(set (match_operand:DI 0 "register_operand" "")
3461: (ashift:DI (match_operand:DI 1 "register_operand" "")
3462: (match_operand:SI 2 "small_int" "")))
3463: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 3464: "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 3465: && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3466: && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3467: && (INTVAL (operands[2]) & 63) < 32
3468: && (INTVAL (operands[2]) & 63) != 0"
3469:
3470: [(set (subreg:SI (match_dup 0) 1)
3471: (ashift:SI (subreg:SI (match_dup 1) 1)
3472: (match_dup 2)))
3473:
3474: (set (match_dup 3)
3475: (lshiftrt:SI (subreg:SI (match_dup 1) 0)
3476: (match_dup 4)))
3477:
3478: (set (subreg:SI (match_dup 0) 1)
3479: (ior:SI (subreg:SI (match_dup 0) 1)
3480: (match_dup 3)))
3481:
3482: (set (subreg:SI (match_dup 0) 0)
3483: (ashift:SI (subreg:SI (match_dup 1) 0)
3484: (match_dup 2)))]
3485: "
3486: {
3487: int amount = INTVAL (operands[2]);
3488: operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3489: operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3490: }")
3491:
3492:
3493: (define_split
3494: [(set (match_operand:DI 0 "register_operand" "")
3495: (ashift:DI (match_operand:DI 1 "register_operand" "")
3496: (match_operand:SI 2 "small_int" "")))
3497: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 3498: "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 3499: && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3500: && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3501: && (INTVAL (operands[2]) & 63) < 32
3502: && (INTVAL (operands[2]) & 63) != 0"
3503:
3504: [(set (subreg:SI (match_dup 0) 0)
3505: (ashift:SI (subreg:SI (match_dup 1) 0)
3506: (match_dup 2)))
3507:
3508: (set (match_dup 3)
3509: (lshiftrt:SI (subreg:SI (match_dup 1) 1)
3510: (match_dup 4)))
3511:
3512: (set (subreg:SI (match_dup 0) 0)
3513: (ior:SI (subreg:SI (match_dup 0) 0)
3514: (match_dup 3)))
3515:
3516: (set (subreg:SI (match_dup 0) 1)
3517: (ashift:SI (subreg:SI (match_dup 1) 1)
3518: (match_dup 2)))]
3519: "
3520: {
3521: int amount = INTVAL (operands[2]);
3522: operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3523: operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3524: }")
3525:
3526:
1.1.1.3 ! root 3527: (define_insn "ashldi3_internal4"
! 3528: [(set (match_operand:DI 0 "register_operand" "=d")
! 3529: (ashift:DI (match_operand:DI 1 "register_operand" "d")
! 3530: (match_operand:SI 2 "arith_operand" "dI")))]
! 3531: "TARGET_64BIT"
! 3532: "*
! 3533: {
! 3534: if (GET_CODE (operands[2]) == CONST_INT)
! 3535: operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
! 3536:
! 3537: return \"dsll\\t%0,%1,%2\";
! 3538: }"
! 3539: [(set_attr "type" "arith")
! 3540: (set_attr "mode" "DI")
! 3541: (set_attr "length" "1")])
! 3542:
! 3543:
1.1 root 3544: (define_insn "ashrsi3"
3545: [(set (match_operand:SI 0 "register_operand" "=d")
3546: (ashiftrt:SI (match_operand:SI 1 "register_operand" "d")
3547: (match_operand:SI 2 "arith_operand" "dI")))]
3548: ""
3549: "*
3550: {
3551: if (GET_CODE (operands[2]) == CONST_INT)
3552: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
3553:
3554: return \"sra\\t%0,%1,%2\";
3555: }"
3556: [(set_attr "type" "arith")
3557: (set_attr "mode" "SI")
3558: (set_attr "length" "1")])
3559:
3560:
3561: (define_expand "ashrdi3"
3562: [(parallel [(set (match_operand:DI 0 "register_operand" "")
3563: (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
3564: (match_operand:SI 2 "arith_operand" "")))
3565: (clobber (match_dup 3))])]
1.1.1.3 ! root 3566: "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
! 3567: "
! 3568: {
! 3569: if (TARGET_64BIT)
! 3570: {
! 3571: emit_insn (gen_ashrdi3_internal4 (operands[0], operands[1],
! 3572: operands[2]));
! 3573: DONE;
! 3574: }
! 3575:
! 3576: operands[3] = gen_reg_rtx (SImode);
! 3577: }")
1.1 root 3578:
3579:
3580: (define_insn "ashrdi3_internal"
3581: [(set (match_operand:DI 0 "register_operand" "=&d")
3582: (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3583: (match_operand:SI 2 "register_operand" "d")))
3584: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 3585: "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
1.1 root 3586: "*
3587: {
3588: operands[4] = const0_rtx;
3589: dslots_jump_total += 3;
3590: dslots_jump_filled += 2;
3591:
3592: return \"sll\\t%3,%2,26\\n\\
3593: \\tbgez\\t%3,1f\\n\\
3594: \\tsra\\t%L0,%M1,%2\\n\\
3595: \\t%(b\\t3f\\n\\
3596: \\tsra\\t%M0,%M1,31%)\\n\\
3597: \\n\\
3598: 1:\\n\\
3599: \\t%(beq\\t%3,%z4,2f\\n\\
3600: \\tsrl\\t%L0,%L1,%2%)\\n\\
3601: \\n\\
3602: \\tsubu\\t%3,%z4,%2\\n\\
3603: \\tsll\\t%3,%M1,%3\\n\\
3604: \\tor\\t%L0,%L0,%3\\n\\
3605: 2:\\n\\
3606: \\tsra\\t%M0,%M1,%2\\n\\
3607: 3:\";
3608: }"
3609: [(set_attr "type" "darith")
3610: (set_attr "mode" "DI")
3611: (set_attr "length" "12")])
3612:
3613:
3614: (define_insn "ashrdi3_internal2"
3615: [(set (match_operand:DI 0 "register_operand" "=d")
3616: (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3617: (match_operand:SI 2 "small_int" "IJK")))
3618: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 3619: "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
1.1 root 3620: "*
3621: {
3622: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
3623: return \"sra\\t%L0,%M1,%2\;sra\\t%M0,%M1,31\";
3624: }"
3625: [(set_attr "type" "darith")
3626: (set_attr "mode" "DI")
3627: (set_attr "length" "2")])
3628:
3629:
3630: (define_split
3631: [(set (match_operand:DI 0 "register_operand" "")
3632: (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
3633: (match_operand:SI 2 "small_int" "")))
3634: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 3635: "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 3636: && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3637: && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3638: && (INTVAL (operands[2]) & 32) != 0"
3639:
3640: [(set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
3641: (set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 1) (const_int 31)))]
3642:
3643: "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
3644:
3645:
3646: (define_split
3647: [(set (match_operand:DI 0 "register_operand" "")
3648: (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
3649: (match_operand:SI 2 "small_int" "")))
3650: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 3651: "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 3652: && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3653: && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3654: && (INTVAL (operands[2]) & 32) != 0"
3655:
3656: [(set (subreg:SI (match_dup 0) 1) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
3657: (set (subreg:SI (match_dup 0) 0) (ashiftrt:SI (subreg:SI (match_dup 1) 0) (const_int 31)))]
3658:
3659: "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
3660:
3661:
3662: (define_insn "ashrdi3_internal3"
3663: [(set (match_operand:DI 0 "register_operand" "=d")
3664: (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
3665: (match_operand:SI 2 "small_int" "IJK")))
3666: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 3667: "!TARGET_64BIT && !TARGET_DEBUG_G_MODE
1.1 root 3668: && (INTVAL (operands[2]) & 63) < 32
3669: && (INTVAL (operands[2]) & 63) != 0"
3670: "*
3671: {
3672: int amount = INTVAL (operands[2]);
3673:
3674: operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3675: operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3676:
3677: return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;sra\\t%M0,%M1,%2\";
3678: }"
3679: [(set_attr "type" "darith")
3680: (set_attr "mode" "DI")
3681: (set_attr "length" "4")])
3682:
3683:
3684: (define_split
3685: [(set (match_operand:DI 0 "register_operand" "")
3686: (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
3687: (match_operand:SI 2 "small_int" "")))
3688: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 3689: "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 3690: && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3691: && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3692: && (INTVAL (operands[2]) & 63) < 32
3693: && (INTVAL (operands[2]) & 63) != 0"
3694:
3695: [(set (subreg:SI (match_dup 0) 0)
3696: (lshiftrt:SI (subreg:SI (match_dup 1) 0)
3697: (match_dup 2)))
3698:
3699: (set (match_dup 3)
3700: (ashift:SI (subreg:SI (match_dup 1) 1)
3701: (match_dup 4)))
3702:
3703: (set (subreg:SI (match_dup 0) 0)
3704: (ior:SI (subreg:SI (match_dup 0) 0)
3705: (match_dup 3)))
3706:
3707: (set (subreg:SI (match_dup 0) 1)
3708: (ashiftrt:SI (subreg:SI (match_dup 1) 1)
3709: (match_dup 2)))]
3710: "
3711: {
3712: int amount = INTVAL (operands[2]);
3713: operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3714: operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3715: }")
3716:
3717:
3718: (define_split
3719: [(set (match_operand:DI 0 "register_operand" "")
3720: (ashiftrt:DI (match_operand:DI 1 "register_operand" "")
3721: (match_operand:SI 2 "small_int" "")))
3722: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 3723: "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 3724: && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3725: && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3726: && (INTVAL (operands[2]) & 63) < 32
3727: && (INTVAL (operands[2]) & 63) != 0"
3728:
3729: [(set (subreg:SI (match_dup 0) 1)
3730: (lshiftrt:SI (subreg:SI (match_dup 1) 1)
3731: (match_dup 2)))
3732:
3733: (set (match_dup 3)
3734: (ashift:SI (subreg:SI (match_dup 1) 0)
3735: (match_dup 4)))
3736:
3737: (set (subreg:SI (match_dup 0) 1)
3738: (ior:SI (subreg:SI (match_dup 0) 1)
3739: (match_dup 3)))
3740:
3741: (set (subreg:SI (match_dup 0) 0)
3742: (ashiftrt:SI (subreg:SI (match_dup 1) 0)
3743: (match_dup 2)))]
3744: "
3745: {
3746: int amount = INTVAL (operands[2]);
3747: operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3748: operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3749: }")
3750:
3751:
1.1.1.3 ! root 3752: (define_insn "ashrdi3_internal4"
! 3753: [(set (match_operand:DI 0 "register_operand" "=d")
! 3754: (ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
! 3755: (match_operand:SI 2 "arith_operand" "dI")))]
! 3756: "TARGET_64BIT"
! 3757: "*
! 3758: {
! 3759: if (GET_CODE (operands[2]) == CONST_INT)
! 3760: operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
! 3761:
! 3762: return \"dsra\\t%0,%1,%2\";
! 3763: }"
! 3764: [(set_attr "type" "arith")
! 3765: (set_attr "mode" "DI")
! 3766: (set_attr "length" "1")])
! 3767:
! 3768:
1.1 root 3769: (define_insn "lshrsi3"
3770: [(set (match_operand:SI 0 "register_operand" "=d")
3771: (lshiftrt:SI (match_operand:SI 1 "register_operand" "d")
3772: (match_operand:SI 2 "arith_operand" "dI")))]
3773: ""
3774: "*
3775: {
3776: if (GET_CODE (operands[2]) == CONST_INT)
3777: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
3778:
3779: return \"srl\\t%0,%1,%2\";
3780: }"
3781: [(set_attr "type" "arith")
3782: (set_attr "mode" "SI")
3783: (set_attr "length" "1")])
3784:
3785:
3786: (define_expand "lshrdi3"
3787: [(parallel [(set (match_operand:DI 0 "register_operand" "")
3788: (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
3789: (match_operand:SI 2 "arith_operand" "")))
3790: (clobber (match_dup 3))])]
1.1.1.3 ! root 3791: "TARGET_64BIT || !TARGET_DEBUG_G_MODE"
! 3792: "
! 3793: {
! 3794: if (TARGET_64BIT)
! 3795: {
! 3796: emit_insn (gen_lshrdi3_internal4 (operands[0], operands[1],
! 3797: operands[2]));
! 3798: DONE;
! 3799: }
! 3800:
! 3801: operands[3] = gen_reg_rtx (SImode);
! 3802: }")
1.1 root 3803:
3804:
3805: (define_insn "lshrdi3_internal"
3806: [(set (match_operand:DI 0 "register_operand" "=&d")
3807: (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3808: (match_operand:SI 2 "register_operand" "d")))
3809: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 3810: "!TARGET_64BIT && !TARGET_DEBUG_G_MODE"
1.1 root 3811: "*
3812: {
3813: operands[4] = const0_rtx;
3814: dslots_jump_total += 3;
3815: dslots_jump_filled += 2;
3816:
3817: return \"sll\\t%3,%2,26\\n\\
3818: \\tbgez\\t%3,1f\\n\\
3819: \\tsrl\\t%L0,%M1,%2\\n\\
3820: \\t%(b\\t3f\\n\\
3821: \\tmove\\t%M0,%z4%)\\n\\
3822: \\n\\
3823: 1:\\n\\
3824: \\t%(beq\\t%3,%z4,2f\\n\\
3825: \\tsrl\\t%L0,%L1,%2%)\\n\\
3826: \\n\\
3827: \\tsubu\\t%3,%z4,%2\\n\\
3828: \\tsll\\t%3,%M1,%3\\n\\
3829: \\tor\\t%L0,%L0,%3\\n\\
3830: 2:\\n\\
3831: \\tsrl\\t%M0,%M1,%2\\n\\
3832: 3:\";
3833: }"
3834: [(set_attr "type" "darith")
3835: (set_attr "mode" "DI")
3836: (set_attr "length" "12")])
3837:
3838:
3839: (define_insn "lshrdi3_internal2"
3840: [(set (match_operand:DI 0 "register_operand" "=d")
3841: (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3842: (match_operand:SI 2 "small_int" "IJK")))
3843: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 3844: "!TARGET_64BIT && !TARGET_DEBUG_G_MODE && (INTVAL (operands[2]) & 32) != 0"
1.1 root 3845: "*
3846: {
3847: operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);
3848: operands[4] = const0_rtx;
3849: return \"srl\\t%L0,%M1,%2\;move\\t%M0,%z4\";
3850: }"
3851: [(set_attr "type" "darith")
3852: (set_attr "mode" "DI")
3853: (set_attr "length" "2")])
3854:
3855:
3856: (define_split
3857: [(set (match_operand:DI 0 "register_operand" "")
3858: (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
3859: (match_operand:SI 2 "small_int" "")))
3860: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 3861: "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 3862: && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3863: && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3864: && (INTVAL (operands[2]) & 32) != 0"
3865:
3866: [(set (subreg:SI (match_dup 0) 0) (lshiftrt:SI (subreg:SI (match_dup 1) 1) (match_dup 2)))
3867: (set (subreg:SI (match_dup 0) 1) (const_int 0))]
3868:
3869: "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
3870:
3871:
3872: (define_split
3873: [(set (match_operand:DI 0 "register_operand" "")
3874: (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
3875: (match_operand:SI 2 "small_int" "")))
3876: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 3877: "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 3878: && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3879: && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3880: && (INTVAL (operands[2]) & 32) != 0"
3881:
3882: [(set (subreg:SI (match_dup 0) 1) (lshiftrt:SI (subreg:SI (match_dup 1) 0) (match_dup 2)))
3883: (set (subreg:SI (match_dup 0) 0) (const_int 0))]
3884:
3885: "operands[2] = gen_rtx (CONST_INT, VOIDmode, (XINT (operands[2], 0))& 0x1f);")
3886:
3887:
3888: (define_insn "lshrdi3_internal3"
3889: [(set (match_operand:DI 0 "register_operand" "=d")
3890: (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
3891: (match_operand:SI 2 "small_int" "IJK")))
3892: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 3893: "!TARGET_64BIT && !TARGET_DEBUG_G_MODE
1.1 root 3894: && (INTVAL (operands[2]) & 63) < 32
3895: && (INTVAL (operands[2]) & 63) != 0"
3896: "*
3897: {
3898: int amount = INTVAL (operands[2]);
3899:
3900: operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3901: operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3902:
3903: return \"srl\\t%L0,%L1,%2\;sll\\t%3,%M1,%4\;or\\t%L0,%L0,%3\;srl\\t%M0,%M1,%2\";
3904: }"
3905: [(set_attr "type" "darith")
3906: (set_attr "mode" "DI")
3907: (set_attr "length" "4")])
3908:
3909:
3910: (define_split
3911: [(set (match_operand:DI 0 "register_operand" "")
3912: (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
3913: (match_operand:SI 2 "small_int" "")))
3914: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 3915: "reload_completed && !WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 3916: && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3917: && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3918: && (INTVAL (operands[2]) & 63) < 32
3919: && (INTVAL (operands[2]) & 63) != 0"
3920:
3921: [(set (subreg:SI (match_dup 0) 0)
3922: (lshiftrt:SI (subreg:SI (match_dup 1) 0)
3923: (match_dup 2)))
3924:
3925: (set (match_dup 3)
3926: (ashift:SI (subreg:SI (match_dup 1) 1)
3927: (match_dup 4)))
3928:
3929: (set (subreg:SI (match_dup 0) 0)
3930: (ior:SI (subreg:SI (match_dup 0) 0)
3931: (match_dup 3)))
3932:
3933: (set (subreg:SI (match_dup 0) 1)
3934: (lshiftrt:SI (subreg:SI (match_dup 1) 1)
3935: (match_dup 2)))]
3936: "
3937: {
3938: int amount = INTVAL (operands[2]);
3939: operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3940: operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3941: }")
3942:
3943:
3944: (define_split
3945: [(set (match_operand:DI 0 "register_operand" "")
3946: (lshiftrt:DI (match_operand:DI 1 "register_operand" "")
3947: (match_operand:SI 2 "small_int" "")))
3948: (clobber (match_operand:SI 3 "register_operand" ""))]
1.1.1.3 ! root 3949: "reload_completed && WORDS_BIG_ENDIAN && !TARGET_64BIT && !TARGET_DEBUG_D_MODE && !TARGET_DEBUG_G_MODE
1.1 root 3950: && GET_CODE (operands[0]) == REG && REGNO (operands[0]) < FIRST_PSEUDO_REGISTER
3951: && GET_CODE (operands[1]) == REG && REGNO (operands[1]) < FIRST_PSEUDO_REGISTER
3952: && (INTVAL (operands[2]) & 63) < 32
3953: && (INTVAL (operands[2]) & 63) != 0"
3954:
3955: [(set (subreg:SI (match_dup 0) 1)
3956: (lshiftrt:SI (subreg:SI (match_dup 1) 1)
3957: (match_dup 2)))
3958:
3959: (set (match_dup 3)
3960: (ashift:SI (subreg:SI (match_dup 1) 0)
3961: (match_dup 4)))
3962:
3963: (set (subreg:SI (match_dup 0) 1)
3964: (ior:SI (subreg:SI (match_dup 0) 1)
3965: (match_dup 3)))
3966:
3967: (set (subreg:SI (match_dup 0) 0)
3968: (lshiftrt:SI (subreg:SI (match_dup 1) 0)
3969: (match_dup 2)))]
3970: "
3971: {
3972: int amount = INTVAL (operands[2]);
3973: operands[2] = gen_rtx (CONST_INT, VOIDmode, (amount & 31));
3974: operands[4] = gen_rtx (CONST_INT, VOIDmode, ((-amount) & 31));
3975: }")
3976:
1.1.1.3 ! root 3977:
! 3978: (define_insn "lshrdi3_internal4"
! 3979: [(set (match_operand:DI 0 "register_operand" "=d")
! 3980: (lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
! 3981: (match_operand:SI 2 "arith_operand" "dI")))]
! 3982: "TARGET_64BIT"
! 3983: "*
! 3984: {
! 3985: if (GET_CODE (operands[2]) == CONST_INT)
! 3986: operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f);
! 3987:
! 3988: return \"dsrl\\t%0,%1,%2\";
! 3989: }"
! 3990: [(set_attr "type" "arith")
! 3991: (set_attr "mode" "DI")
! 3992: (set_attr "length" "1")])
! 3993:
1.1 root 3994:
3995: ;;
3996: ;; ....................
3997: ;;
3998: ;; COMPARISONS
3999: ;;
4000: ;; ....................
4001:
4002: ;; Flow here is rather complex:
4003: ;;
1.1.1.3 ! root 4004: ;; 1) The cmp{si,di,sf,df} routine is called. It deposits the
1.1 root 4005: ;; arguments into the branch_cmp array, and the type into
4006: ;; branch_type. No RTL is generated.
4007: ;;
4008: ;; 2) The appropriate branch define_expand is called, which then
4009: ;; creates the appropriate RTL for the comparison and branch.
4010: ;; Different CC modes are used, based on what type of branch is
4011: ;; done, so that we can constrain things appropriately. There
4012: ;; are assumptions in the rest of GCC that break if we fold the
4013: ;; operands into the branchs for integer operations, and use cc0
4014: ;; for floating point, so we use the fp status register instead.
4015: ;; If needed, an appropriate temporary is created to hold the
4016: ;; of the integer compare.
4017:
4018: (define_expand "cmpsi"
4019: [(set (cc0)
4020: (compare:CC (match_operand:SI 0 "register_operand" "")
4021: (match_operand:SI 1 "arith_operand" "")))]
4022: ""
4023: "
4024: {
4025: if (operands[0]) /* avoid unused code message */
4026: {
4027: branch_cmp[0] = operands[0];
4028: branch_cmp[1] = operands[1];
4029: branch_type = CMP_SI;
4030: DONE;
4031: }
4032: }")
4033:
4034: (define_expand "tstsi"
4035: [(set (cc0)
4036: (match_operand:SI 0 "register_operand" ""))]
4037: ""
4038: "
4039: {
4040: if (operands[0]) /* avoid unused code message */
4041: {
4042: branch_cmp[0] = operands[0];
4043: branch_cmp[1] = const0_rtx;
4044: branch_type = CMP_SI;
4045: DONE;
4046: }
4047: }")
4048:
1.1.1.3 ! root 4049: (define_expand "cmpdi"
! 4050: [(set (cc0)
! 4051: (compare:CC (match_operand:DI 0 "register_operand" "")
! 4052: (match_operand:DI 1 "arith_operand" "")))]
! 4053: "TARGET_64BIT"
! 4054: "
! 4055: {
! 4056: if (operands[0]) /* avoid unused code message */
! 4057: {
! 4058: branch_cmp[0] = operands[0];
! 4059: branch_cmp[1] = operands[1];
! 4060: branch_type = CMP_DI;
! 4061: DONE;
! 4062: }
! 4063: }")
! 4064:
! 4065: (define_expand "tstdi"
! 4066: [(set (cc0)
! 4067: (match_operand:DI 0 "register_operand" ""))]
! 4068: "TARGET_64BIT"
! 4069: "
! 4070: {
! 4071: if (operands[0]) /* avoid unused code message */
! 4072: {
! 4073: branch_cmp[0] = operands[0];
! 4074: branch_cmp[1] = const0_rtx;
! 4075: branch_type = CMP_DI;
! 4076: DONE;
! 4077: }
! 4078: }")
! 4079:
1.1 root 4080: (define_expand "cmpdf"
4081: [(set (cc0)
4082: (compare:CC_FP (match_operand:DF 0 "register_operand" "")
4083: (match_operand:DF 1 "register_operand" "")))]
4084: "TARGET_HARD_FLOAT"
4085: "
4086: {
4087: if (operands[0]) /* avoid unused code message */
4088: {
4089: branch_cmp[0] = operands[0];
4090: branch_cmp[1] = operands[1];
4091: branch_type = CMP_DF;
4092: DONE;
4093: }
4094: }")
4095:
4096: (define_expand "cmpsf"
4097: [(set (cc0)
4098: (compare:CC_FP (match_operand:SF 0 "register_operand" "")
4099: (match_operand:SF 1 "register_operand" "")))]
4100: "TARGET_HARD_FLOAT"
4101: "
4102: {
4103: if (operands[0]) /* avoid unused code message */
4104: {
4105: branch_cmp[0] = operands[0];
4106: branch_cmp[1] = operands[1];
4107: branch_type = CMP_SF;
4108: DONE;
4109: }
4110: }")
4111:
4112:
4113: ;;
4114: ;; ....................
4115: ;;
4116: ;; CONDITIONAL BRANCHES
4117: ;;
4118: ;; ....................
4119:
4120: (define_insn "branch_fp_ne"
4121: [(set (pc)
4122: (if_then_else (ne:CC_FP (reg:CC_FP 66)
4123: (const_int 0))
4124: (match_operand 0 "pc_or_label_operand" "")
4125: (match_operand 1 "pc_or_label_operand" "")))]
1.1.1.3 ! root 4126: "TARGET_HARD_FLOAT"
1.1 root 4127: "*
4128: {
4129: mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
4130: return (operands[0] != pc_rtx) ? \"%*bc1t%?\\t%0\" : \"%*bc1f%?\\t%1\";
4131: }"
4132: [(set_attr "type" "branch")
4133: (set_attr "mode" "none")
4134: (set_attr "length" "1")])
4135:
4136: (define_insn "branch_fp_ne_rev"
4137: [(set (pc)
4138: (if_then_else (ne:CC_REV_FP (reg:CC_REV_FP 66)
4139: (const_int 0))
4140: (match_operand 0 "pc_or_label_operand" "")
4141: (match_operand 1 "pc_or_label_operand" "")))]
1.1.1.3 ! root 4142: "TARGET_HARD_FLOAT"
1.1 root 4143: "*
4144: {
4145: mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
4146: return (operands[0] != pc_rtx) ? \"%*bc1f%?\\t%0\" : \"%*bc1t%?\\t%1\";
4147: }"
4148: [(set_attr "type" "branch")
4149: (set_attr "mode" "none")
4150: (set_attr "length" "1")])
4151:
4152: (define_insn "branch_fp_eq"
4153: [(set (pc)
4154: (if_then_else (eq:CC_FP (reg:CC_FP 66)
4155: (const_int 0))
4156: (match_operand 0 "pc_or_label_operand" "")
4157: (match_operand 1 "pc_or_label_operand" "")))]
1.1.1.3 ! root 4158: "TARGET_HARD_FLOAT"
1.1 root 4159: "*
4160: {
4161: mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
4162: return (operands[0] != pc_rtx) ? \"%*bc1f%?\\t%0\" : \"%*bc1t%?\\t%1\";
4163: }"
4164: [(set_attr "type" "branch")
4165: (set_attr "mode" "none")
4166: (set_attr "length" "1")])
4167:
4168: (define_insn "branch_fp_eq_rev"
4169: [(set (pc)
4170: (if_then_else (eq:CC_REV_FP (reg:CC_REV_FP 66)
4171: (const_int 0))
4172: (match_operand 0 "pc_or_label_operand" "")
4173: (match_operand 1 "pc_or_label_operand" "")))]
1.1.1.3 ! root 4174: "TARGET_HARD_FLOAT"
1.1 root 4175: "*
4176: {
4177: mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
4178: return (operands[0] != pc_rtx) ? \"%*bc1t%?\\t%0\" : \"%*bc1f%?\\t%1\";
4179: }"
4180: [(set_attr "type" "branch")
4181: (set_attr "mode" "none")
4182: (set_attr "length" "1")])
4183:
4184:
4185: (define_insn "branch_zero"
4186: [(set (pc)
4187: (if_then_else (match_operator:SI 0 "cmp_op"
4188: [(match_operand:SI 1 "register_operand" "d")
4189: (const_int 0)])
4190: (match_operand 2 "pc_or_label_operand" "")
4191: (match_operand 3 "pc_or_label_operand" "")))]
4192: ""
4193: "*
4194: {
4195: mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
4196: if (operands[2] != pc_rtx)
4197: { /* normal jump */
4198: switch (GET_CODE (operands[0]))
4199: {
4200: case EQ: return \"%*beq%?\\t%z1,%.,%2\";
4201: case NE: return \"%*bne%?\\t%z1,%.,%2\";
4202: case GTU: return \"%*bne%?\\t%z1,%.,%2\";
4203: case LEU: return \"%*beq%?\\t%z1,%.,%2\";
4204: case GEU: return \"%*j\\t%2\";
4205: case LTU: return \"%*bne%?\\t%.,%.,%2\";
4206: }
4207:
4208: return \"%*b%C0z%?\\t%z1,%2\";
4209: }
4210: else
4211: { /* inverted jump */
4212: switch (GET_CODE (operands[0]))
4213: {
4214: case EQ: return \"%*bne%?\\t%z1,%.,%3\";
4215: case NE: return \"%*beq%?\\t%z1,%.,%3\";
4216: case GTU: return \"%*beq%?\\t%z1,%.,%3\";
4217: case LEU: return \"%*bne%?\\t%z1,%.,%3\";
4218: case GEU: return \"%*beq%?\\t%.,%.,%3\";
4219: case LTU: return \"%*j\\t%3\";
4220: }
4221:
4222: return \"%*b%N0z%?\\t%z1,%3\";
4223: }
4224: }"
4225: [(set_attr "type" "branch")
4226: (set_attr "mode" "none")
4227: (set_attr "length" "1")])
4228:
4229:
1.1.1.3 ! root 4230: (define_insn "branch_zero_di"
! 4231: [(set (pc)
! 4232: (if_then_else (match_operator:DI 0 "cmp_op"
! 4233: [(match_operand:DI 1 "register_operand" "d")
! 4234: (const_int 0)])
! 4235: (match_operand 2 "pc_or_label_operand" "")
! 4236: (match_operand 3 "pc_or_label_operand" "")))]
! 4237: ""
! 4238: "*
! 4239: {
! 4240: mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
! 4241: if (operands[2] != pc_rtx)
! 4242: { /* normal jump */
! 4243: switch (GET_CODE (operands[0]))
! 4244: {
! 4245: case EQ: return \"%*beq%?\\t%z1,%.,%2\";
! 4246: case NE: return \"%*bne%?\\t%z1,%.,%2\";
! 4247: case GTU: return \"%*bne%?\\t%z1,%.,%2\";
! 4248: case LEU: return \"%*beq%?\\t%z1,%.,%2\";
! 4249: case GEU: return \"%*j\\t%2\";
! 4250: case LTU: return \"%*bne%?\\t%.,%.,%2\";
! 4251: }
! 4252:
! 4253: return \"%*b%C0z%?\\t%z1,%2\";
! 4254: }
! 4255: else
! 4256: { /* inverted jump */
! 4257: switch (GET_CODE (operands[0]))
! 4258: {
! 4259: case EQ: return \"%*bne%?\\t%z1,%.,%3\";
! 4260: case NE: return \"%*beq%?\\t%z1,%.,%3\";
! 4261: case GTU: return \"%*beq%?\\t%z1,%.,%3\";
! 4262: case LEU: return \"%*bne%?\\t%z1,%.,%3\";
! 4263: case GEU: return \"%*beq%?\\t%.,%.,%3\";
! 4264: case LTU: return \"%*j\\t%3\";
! 4265: }
! 4266:
! 4267: return \"%*b%N0z%?\\t%z1,%3\";
! 4268: }
! 4269: }"
! 4270: [(set_attr "type" "branch")
! 4271: (set_attr "mode" "none")
! 4272: (set_attr "length" "1")])
! 4273:
! 4274:
1.1 root 4275: (define_insn "branch_equality"
4276: [(set (pc)
4277: (if_then_else (match_operator:SI 0 "equality_op"
4278: [(match_operand:SI 1 "register_operand" "d")
4279: (match_operand:SI 2 "register_operand" "d")])
4280: (match_operand 3 "pc_or_label_operand" "")
4281: (match_operand 4 "pc_or_label_operand" "")))]
4282: ""
4283: "*
4284: {
4285: mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
4286: return (operands[3] != pc_rtx)
4287: ? \"%*b%C0%?\\t%z1,%z2,%3\"
4288: : \"%*b%N0%?\\t%z1,%z2,%4\";
4289: }"
4290: [(set_attr "type" "branch")
4291: (set_attr "mode" "none")
4292: (set_attr "length" "1")])
4293:
4294:
1.1.1.3 ! root 4295: (define_insn "branch_equality_di"
! 4296: [(set (pc)
! 4297: (if_then_else (match_operator:DI 0 "equality_op"
! 4298: [(match_operand:DI 1 "register_operand" "d")
! 4299: (match_operand:DI 2 "register_operand" "d")])
! 4300: (match_operand 3 "pc_or_label_operand" "")
! 4301: (match_operand 4 "pc_or_label_operand" "")))]
! 4302: ""
! 4303: "*
! 4304: {
! 4305: mips_branch_likely = (final_sequence && INSN_ANNULLED_BRANCH_P (insn));
! 4306: return (operands[3] != pc_rtx)
! 4307: ? \"%*b%C0%?\\t%z1,%z2,%3\"
! 4308: : \"%*b%N0%?\\t%z1,%z2,%4\";
! 4309: }"
! 4310: [(set_attr "type" "branch")
! 4311: (set_attr "mode" "none")
! 4312: (set_attr "length" "1")])
! 4313:
! 4314:
1.1 root 4315: (define_expand "beq"
4316: [(set (pc)
4317: (if_then_else (eq:CC_EQ (cc0)
4318: (const_int 0))
4319: (label_ref (match_operand 0 "" ""))
4320: (pc)))]
4321: ""
4322: "
4323: {
4324: if (operands[0]) /* avoid unused code warning */
4325: {
4326: gen_conditional_branch (operands, EQ);
4327: DONE;
4328: }
4329: }")
4330:
4331: (define_expand "bne"
4332: [(set (pc)
4333: (if_then_else (ne:CC_EQ (cc0)
4334: (const_int 0))
4335: (label_ref (match_operand 0 "" ""))
4336: (pc)))]
4337: ""
4338: "
4339: {
4340: if (operands[0]) /* avoid unused code warning */
4341: {
4342: gen_conditional_branch (operands, NE);
4343: DONE;
4344: }
4345: }")
4346:
4347: (define_expand "bgt"
4348: [(set (pc)
4349: (if_then_else (gt:CC (cc0)
4350: (const_int 0))
4351: (label_ref (match_operand 0 "" ""))
4352: (pc)))]
4353: ""
4354: "
4355: {
4356: if (operands[0]) /* avoid unused code warning */
4357: {
4358: gen_conditional_branch (operands, GT);
4359: DONE;
4360: }
4361: }")
4362:
4363: (define_expand "bge"
4364: [(set (pc)
4365: (if_then_else (ge:CC (cc0)
4366: (const_int 0))
4367: (label_ref (match_operand 0 "" ""))
4368: (pc)))]
4369: ""
4370: "
4371: {
4372: if (operands[0]) /* avoid unused code warning */
4373: {
4374: gen_conditional_branch (operands, GE);
4375: DONE;
4376: }
4377: }")
4378:
4379: (define_expand "blt"
4380: [(set (pc)
4381: (if_then_else (lt:CC (cc0)
4382: (const_int 0))
4383: (label_ref (match_operand 0 "" ""))
4384: (pc)))]
4385: ""
4386: "
4387: {
4388: if (operands[0]) /* avoid unused code warning */
4389: {
4390: gen_conditional_branch (operands, LT);
4391: DONE;
4392: }
4393: }")
4394:
4395: (define_expand "ble"
4396: [(set (pc)
4397: (if_then_else (le:CC (cc0)
4398: (const_int 0))
4399: (label_ref (match_operand 0 "" ""))
4400: (pc)))]
4401: ""
4402: "
4403: {
4404: if (operands[0]) /* avoid unused code warning */
4405: {
4406: gen_conditional_branch (operands, LE);
4407: DONE;
4408: }
4409: }")
4410:
4411: (define_expand "bgtu"
4412: [(set (pc)
4413: (if_then_else (gtu:CC (cc0)
4414: (const_int 0))
4415: (label_ref (match_operand 0 "" ""))
4416: (pc)))]
4417: ""
4418: "
4419: {
4420: if (operands[0]) /* avoid unused code warning */
4421: {
4422: gen_conditional_branch (operands, GTU);
4423: DONE;
4424: }
4425: }")
4426:
4427: (define_expand "bgeu"
4428: [(set (pc)
4429: (if_then_else (geu:CC (cc0)
4430: (const_int 0))
4431: (label_ref (match_operand 0 "" ""))
4432: (pc)))]
4433: ""
4434: "
4435: {
4436: if (operands[0]) /* avoid unused code warning */
4437: {
4438: gen_conditional_branch (operands, GEU);
4439: DONE;
4440: }
4441: }")
4442:
4443:
4444: (define_expand "bltu"
4445: [(set (pc)
4446: (if_then_else (ltu:CC (cc0)
4447: (const_int 0))
4448: (label_ref (match_operand 0 "" ""))
4449: (pc)))]
4450: ""
4451: "
4452: {
4453: if (operands[0]) /* avoid unused code warning */
4454: {
4455: gen_conditional_branch (operands, LTU);
4456: DONE;
4457: }
4458: }")
4459:
4460: (define_expand "bleu"
4461: [(set (pc)
4462: (if_then_else (leu:CC (cc0)
4463: (const_int 0))
4464: (label_ref (match_operand 0 "" ""))
4465: (pc)))]
4466: ""
4467: "
4468: {
4469: if (operands[0]) /* avoid unused code warning */
4470: {
4471: gen_conditional_branch (operands, LEU);
4472: DONE;
4473: }
4474: }")
4475:
4476:
4477: ;;
4478: ;; ....................
4479: ;;
4480: ;; SETTING A REGISTER FROM A COMPARISON
4481: ;;
4482: ;; ....................
4483:
4484: (define_expand "seq"
4485: [(set (match_operand:SI 0 "register_operand" "=d")
4486: (eq:SI (match_dup 1)
4487: (match_dup 2)))]
4488: ""
4489: "
4490: {
1.1.1.3 ! root 4491: if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
1.1 root 4492: FAIL;
4493:
4494: /* set up operands from compare. */
4495: operands[1] = branch_cmp[0];
4496: operands[2] = branch_cmp[1];
4497:
1.1.1.3 ! root 4498: if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
1.1 root 4499: {
4500: gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
4501: DONE;
4502: }
4503:
4504: if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4505: operands[2] = force_reg (SImode, operands[2]);
4506:
4507: /* fall through and generate default code */
4508: }")
4509:
4510:
4511: (define_insn "seq_si_zero"
4512: [(set (match_operand:SI 0 "register_operand" "=d")
4513: (eq:SI (match_operand:SI 1 "register_operand" "d")
4514: (const_int 0)))]
4515: ""
4516: "sltu\\t%0,%1,1"
1.1.1.3 ! root 4517: [(set_attr "type" "arith")
1.1 root 4518: (set_attr "mode" "SI")
4519: (set_attr "length" "1")])
4520:
1.1.1.3 ! root 4521: (define_insn "seq_di_zero"
! 4522: [(set (match_operand:DI 0 "register_operand" "=d")
! 4523: (eq:DI (match_operand:DI 1 "register_operand" "d")
! 4524: (const_int 0)))]
! 4525: "TARGET_64BIT"
! 4526: "sltu\\t%0,%1,1"
! 4527: [(set_attr "type" "arith")
! 4528: (set_attr "mode" "DI")
! 4529: (set_attr "length" "1")])
! 4530:
1.1 root 4531: (define_insn "seq_si"
4532: [(set (match_operand:SI 0 "register_operand" "=d,d")
4533: (eq:SI (match_operand:SI 1 "register_operand" "%d,d")
4534: (match_operand:SI 2 "uns_arith_operand" "d,K")))]
4535: "TARGET_DEBUG_C_MODE"
4536: "@
4537: xor\\t%0,%1,%2\;sltu\\t%0,%0,1
4538: xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
1.1.1.3 ! root 4539: [(set_attr "type" "arith")
1.1 root 4540: (set_attr "mode" "SI")
4541: (set_attr "length" "2")])
4542:
4543: (define_split
4544: [(set (match_operand:SI 0 "register_operand" "")
4545: (eq:SI (match_operand:SI 1 "register_operand" "")
4546: (match_operand:SI 2 "uns_arith_operand" "")))]
4547: "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
4548: && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
4549: [(set (match_dup 0)
4550: (xor:SI (match_dup 1)
4551: (match_dup 2)))
4552: (set (match_dup 0)
4553: (ltu:SI (match_dup 0)
4554: (const_int 1)))]
4555: "")
4556:
1.1.1.3 ! root 4557: (define_insn "seq_di"
! 4558: [(set (match_operand:DI 0 "register_operand" "=d,d")
! 4559: (eq:DI (match_operand:DI 1 "register_operand" "%d,d")
! 4560: (match_operand:DI 2 "uns_arith_operand" "d,K")))]
! 4561: "TARGET_64BIT && TARGET_DEBUG_C_MODE"
! 4562: "@
! 4563: xor\\t%0,%1,%2\;sltu\\t%0,%0,1
! 4564: xori\\t%0,%1,%2\;sltu\\t%0,%0,1"
! 4565: [(set_attr "type" "arith")
! 4566: (set_attr "mode" "DI")
! 4567: (set_attr "length" "2")])
! 4568:
! 4569: (define_split
! 4570: [(set (match_operand:DI 0 "register_operand" "")
! 4571: (eq:DI (match_operand:DI 1 "register_operand" "")
! 4572: (match_operand:DI 2 "uns_arith_operand" "")))]
! 4573: "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
! 4574: && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
! 4575: [(set (match_dup 0)
! 4576: (xor:DI (match_dup 1)
! 4577: (match_dup 2)))
! 4578: (set (match_dup 0)
! 4579: (ltu:DI (match_dup 0)
! 4580: (const_int 1)))]
! 4581: "")
! 4582:
1.1 root 4583: (define_expand "sne"
4584: [(set (match_operand:SI 0 "register_operand" "=d")
4585: (ne:SI (match_dup 1)
4586: (match_dup 2)))]
4587: ""
4588: "
4589: {
1.1.1.3 ! root 4590: if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
1.1 root 4591: FAIL;
4592:
4593: /* set up operands from compare. */
4594: operands[1] = branch_cmp[0];
4595: operands[2] = branch_cmp[1];
4596:
1.1.1.3 ! root 4597: if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
1.1 root 4598: {
4599: gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
4600: DONE;
4601: }
4602:
4603: if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
4604: operands[2] = force_reg (SImode, operands[2]);
4605:
4606: /* fall through and generate default code */
4607: }")
4608:
4609: (define_insn "sne_si_zero"
4610: [(set (match_operand:SI 0 "register_operand" "=d")
4611: (ne:SI (match_operand:SI 1 "register_operand" "d")
4612: (const_int 0)))]
4613: ""
4614: "sltu\\t%0,%.,%1"
1.1.1.3 ! root 4615: [(set_attr "type" "arith")
1.1 root 4616: (set_attr "mode" "SI")
4617: (set_attr "length" "1")])
4618:
1.1.1.3 ! root 4619: (define_insn "sne_di_zero"
! 4620: [(set (match_operand:DI 0 "register_operand" "=d")
! 4621: (ne:DI (match_operand:DI 1 "register_operand" "d")
! 4622: (const_int 0)))]
! 4623: "TARGET_64BIT"
! 4624: "sltu\\t%0,%.,%1"
! 4625: [(set_attr "type" "arith")
! 4626: (set_attr "mode" "DI")
! 4627: (set_attr "length" "1")])
! 4628:
1.1 root 4629: (define_insn "sne_si"
4630: [(set (match_operand:SI 0 "register_operand" "=d,d")
4631: (ne:SI (match_operand:SI 1 "register_operand" "%d,d")
4632: (match_operand:SI 2 "uns_arith_operand" "d,K")))]
4633: "TARGET_DEBUG_C_MODE"
4634: "@
4635: xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
4636: xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
1.1.1.3 ! root 4637: [(set_attr "type" "arith")
1.1 root 4638: (set_attr "mode" "SI")
4639: (set_attr "length" "2")])
4640:
4641: (define_split
4642: [(set (match_operand:SI 0 "register_operand" "")
4643: (ne:SI (match_operand:SI 1 "register_operand" "")
4644: (match_operand:SI 2 "uns_arith_operand" "")))]
4645: "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
4646: && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
4647: [(set (match_dup 0)
1.1.1.3 ! root 4648: (xor:SI (match_dup 1)
! 4649: (match_dup 2)))
! 4650: (set (match_dup 0)
! 4651: (gtu:SI (match_dup 0)
! 4652: (const_int 0)))]
! 4653: "")
! 4654:
! 4655: (define_insn "sne_di"
! 4656: [(set (match_operand:DI 0 "register_operand" "=d,d")
! 4657: (ne:DI (match_operand:DI 1 "register_operand" "%d,d")
! 4658: (match_operand:DI 2 "uns_arith_operand" "d,K")))]
! 4659: "TARGET_64BIT && TARGET_DEBUG_C_MODE"
! 4660: "@
! 4661: xor\\t%0,%1,%2\;sltu\\t%0,%.,%0
! 4662: xori\\t%0,%1,%x2\;sltu\\t%0,%.,%0"
! 4663: [(set_attr "type" "arith")
! 4664: (set_attr "mode" "DI")
! 4665: (set_attr "length" "2")])
! 4666:
! 4667: (define_split
! 4668: [(set (match_operand:DI 0 "register_operand" "")
! 4669: (ne:DI (match_operand:DI 1 "register_operand" "")
! 4670: (match_operand:DI 2 "uns_arith_operand" "")))]
! 4671: "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
! 4672: && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
! 4673: [(set (match_dup 0)
! 4674: (xor:DI (match_dup 1)
1.1 root 4675: (match_dup 2)))
4676: (set (match_dup 0)
1.1.1.3 ! root 4677: (gtu:DI (match_dup 0)
1.1 root 4678: (const_int 0)))]
4679: "")
4680:
4681: (define_expand "sgt"
4682: [(set (match_operand:SI 0 "register_operand" "=d")
4683: (gt:SI (match_dup 1)
4684: (match_dup 2)))]
4685: ""
4686: "
4687: {
1.1.1.3 ! root 4688: if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
1.1 root 4689: FAIL;
4690:
4691: /* set up operands from compare. */
4692: operands[1] = branch_cmp[0];
4693: operands[2] = branch_cmp[1];
4694:
1.1.1.3 ! root 4695: if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
1.1 root 4696: {
4697: gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
4698: DONE;
4699: }
4700:
4701: if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
4702: operands[2] = force_reg (SImode, operands[2]);
4703:
4704: /* fall through and generate default code */
4705: }")
4706:
4707: (define_insn "sgt_si"
4708: [(set (match_operand:SI 0 "register_operand" "=d")
4709: (gt:SI (match_operand:SI 1 "register_operand" "d")
4710: (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
4711: ""
4712: "slt\\t%0,%z2,%1"
1.1.1.3 ! root 4713: [(set_attr "type" "arith")
1.1 root 4714: (set_attr "mode" "SI")
4715: (set_attr "length" "1")])
4716:
1.1.1.3 ! root 4717: (define_insn "sgt_di"
! 4718: [(set (match_operand:DI 0 "register_operand" "=d")
! 4719: (gt:DI (match_operand:DI 1 "register_operand" "d")
! 4720: (match_operand:DI 2 "reg_or_0_operand" "dJ")))]
! 4721: "TARGET_64BIT"
! 4722: "slt\\t%0,%z2,%1"
! 4723: [(set_attr "type" "arith")
! 4724: (set_attr "mode" "DI")
! 4725: (set_attr "length" "1")])
! 4726:
1.1 root 4727: (define_expand "sge"
4728: [(set (match_operand:SI 0 "register_operand" "=d")
4729: (ge:SI (match_dup 1)
4730: (match_dup 2)))]
4731: ""
4732: "
4733: {
1.1.1.3 ! root 4734: if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
1.1 root 4735: FAIL;
4736:
4737: /* set up operands from compare. */
4738: operands[1] = branch_cmp[0];
4739: operands[2] = branch_cmp[1];
4740:
1.1.1.3 ! root 4741: if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
1.1 root 4742: {
4743: gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
4744: DONE;
4745: }
4746:
4747: /* fall through and generate default code */
4748: }")
4749:
4750: (define_insn "sge_si"
4751: [(set (match_operand:SI 0 "register_operand" "=d")
4752: (ge:SI (match_operand:SI 1 "register_operand" "d")
4753: (match_operand:SI 2 "arith_operand" "dI")))]
4754: "TARGET_DEBUG_C_MODE"
4755: "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
1.1.1.3 ! root 4756: [(set_attr "type" "arith")
1.1 root 4757: (set_attr "mode" "SI")
4758: (set_attr "length" "2")])
4759:
4760: (define_split
4761: [(set (match_operand:SI 0 "register_operand" "")
4762: (ge:SI (match_operand:SI 1 "register_operand" "")
4763: (match_operand:SI 2 "arith_operand" "")))]
4764: "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
4765: [(set (match_dup 0)
4766: (lt:SI (match_dup 1)
4767: (match_dup 2)))
4768: (set (match_dup 0)
4769: (xor:SI (match_dup 0)
4770: (const_int 1)))]
4771: "")
4772:
1.1.1.3 ! root 4773: (define_insn "sge_di"
! 4774: [(set (match_operand:DI 0 "register_operand" "=d")
! 4775: (ge:DI (match_operand:DI 1 "register_operand" "d")
! 4776: (match_operand:DI 2 "arith_operand" "dI")))]
! 4777: "TARGET_64BIT && TARGET_DEBUG_C_MODE"
! 4778: "slt\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
! 4779: [(set_attr "type" "arith")
! 4780: (set_attr "mode" "DI")
! 4781: (set_attr "length" "2")])
! 4782:
! 4783: (define_split
! 4784: [(set (match_operand:DI 0 "register_operand" "")
! 4785: (ge:DI (match_operand:DI 1 "register_operand" "")
! 4786: (match_operand:DI 2 "arith_operand" "")))]
! 4787: "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
! 4788: [(set (match_dup 0)
! 4789: (lt:DI (match_dup 1)
! 4790: (match_dup 2)))
! 4791: (set (match_dup 0)
! 4792: (xor:DI (match_dup 0)
! 4793: (const_int 1)))]
! 4794: "")
! 4795:
1.1 root 4796: (define_expand "slt"
4797: [(set (match_operand:SI 0 "register_operand" "=d")
4798: (lt:SI (match_dup 1)
4799: (match_dup 2)))]
4800: ""
4801: "
4802: {
1.1.1.3 ! root 4803: if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
1.1 root 4804: FAIL;
4805:
4806: /* set up operands from compare. */
4807: operands[1] = branch_cmp[0];
4808: operands[2] = branch_cmp[1];
4809:
1.1.1.3 ! root 4810: if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
1.1 root 4811: {
4812: gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
4813: DONE;
4814: }
4815:
4816: /* fall through and generate default code */
4817: }")
4818:
4819: (define_insn "slt_si"
4820: [(set (match_operand:SI 0 "register_operand" "=d")
4821: (lt:SI (match_operand:SI 1 "register_operand" "d")
4822: (match_operand:SI 2 "arith_operand" "dI")))]
4823: ""
4824: "slt\\t%0,%1,%2"
1.1.1.3 ! root 4825: [(set_attr "type" "arith")
1.1 root 4826: (set_attr "mode" "SI")
4827: (set_attr "length" "1")])
4828:
1.1.1.3 ! root 4829: (define_insn "slt_di"
! 4830: [(set (match_operand:DI 0 "register_operand" "=d")
! 4831: (lt:DI (match_operand:DI 1 "register_operand" "d")
! 4832: (match_operand:DI 2 "arith_operand" "dI")))]
! 4833: "TARGET_64BIT"
! 4834: "slt\\t%0,%1,%2"
! 4835: [(set_attr "type" "arith")
! 4836: (set_attr "mode" "DI")
! 4837: (set_attr "length" "1")])
! 4838:
1.1 root 4839: (define_expand "sle"
4840: [(set (match_operand:SI 0 "register_operand" "=d")
4841: (le:SI (match_dup 1)
4842: (match_dup 2)))]
4843: ""
4844: "
4845: {
1.1.1.3 ! root 4846: if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
1.1 root 4847: FAIL;
4848:
4849: /* set up operands from compare. */
4850: operands[1] = branch_cmp[0];
4851: operands[2] = branch_cmp[1];
4852:
1.1.1.3 ! root 4853: if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
1.1 root 4854: {
4855: gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
4856: DONE;
4857: }
4858:
4859: if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
4860: operands[2] = force_reg (SImode, operands[2]);
4861:
4862: /* fall through and generate default code */
4863: }")
4864:
4865: (define_insn "sle_si_const"
4866: [(set (match_operand:SI 0 "register_operand" "=d")
4867: (le:SI (match_operand:SI 1 "register_operand" "d")
4868: (match_operand:SI 2 "small_int" "I")))]
4869: "INTVAL (operands[2]) < 32767"
4870: "*
4871: {
4872: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
4873: return \"slt\\t%0,%1,%2\";
4874: }"
1.1.1.3 ! root 4875: [(set_attr "type" "arith")
1.1 root 4876: (set_attr "mode" "SI")
4877: (set_attr "length" "1")])
4878:
1.1.1.3 ! root 4879: (define_insn "sle_di_const"
! 4880: [(set (match_operand:DI 0 "register_operand" "=d")
! 4881: (le:DI (match_operand:DI 1 "register_operand" "d")
! 4882: (match_operand:DI 2 "small_int" "I")))]
! 4883: "TARGET_64BIT && INTVAL (operands[2]) < 32767"
! 4884: "*
! 4885: {
! 4886: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
! 4887: return \"slt\\t%0,%1,%2\";
! 4888: }"
! 4889: [(set_attr "type" "arith")
! 4890: (set_attr "mode" "DI")
! 4891: (set_attr "length" "1")])
! 4892:
1.1 root 4893: (define_insn "sle_si_reg"
4894: [(set (match_operand:SI 0 "register_operand" "=d")
4895: (le:SI (match_operand:SI 1 "register_operand" "d")
4896: (match_operand:SI 2 "register_operand" "d")))]
4897: "TARGET_DEBUG_C_MODE"
4898: "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
1.1.1.3 ! root 4899: [(set_attr "type" "arith")
1.1 root 4900: (set_attr "mode" "SI")
4901: (set_attr "length" "2")])
4902:
4903: (define_split
4904: [(set (match_operand:SI 0 "register_operand" "")
4905: (le:SI (match_operand:SI 1 "register_operand" "")
4906: (match_operand:SI 2 "register_operand" "")))]
4907: "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
4908: [(set (match_dup 0)
4909: (lt:SI (match_dup 2)
4910: (match_dup 1)))
4911: (set (match_dup 0)
4912: (xor:SI (match_dup 0)
4913: (const_int 1)))]
4914: "")
4915:
1.1.1.3 ! root 4916: (define_insn "sle_di_reg"
! 4917: [(set (match_operand:DI 0 "register_operand" "=d")
! 4918: (le:DI (match_operand:DI 1 "register_operand" "d")
! 4919: (match_operand:DI 2 "register_operand" "d")))]
! 4920: "TARGET_64BIT && TARGET_DEBUG_C_MODE"
! 4921: "slt\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
! 4922: [(set_attr "type" "arith")
! 4923: (set_attr "mode" "DI")
! 4924: (set_attr "length" "2")])
! 4925:
! 4926: (define_split
! 4927: [(set (match_operand:DI 0 "register_operand" "")
! 4928: (le:DI (match_operand:DI 1 "register_operand" "")
! 4929: (match_operand:DI 2 "register_operand" "")))]
! 4930: "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
! 4931: [(set (match_dup 0)
! 4932: (lt:DI (match_dup 2)
! 4933: (match_dup 1)))
! 4934: (set (match_dup 0)
! 4935: (xor:DI (match_dup 0)
! 4936: (const_int 1)))]
! 4937: "")
! 4938:
1.1 root 4939: (define_expand "sgtu"
4940: [(set (match_operand:SI 0 "register_operand" "=d")
4941: (gtu:SI (match_dup 1)
4942: (match_dup 2)))]
4943: ""
4944: "
4945: {
1.1.1.3 ! root 4946: if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
1.1 root 4947: FAIL;
4948:
4949: /* set up operands from compare. */
4950: operands[1] = branch_cmp[0];
4951: operands[2] = branch_cmp[1];
4952:
1.1.1.3 ! root 4953: if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
1.1 root 4954: {
4955: gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
4956: DONE;
4957: }
4958:
4959: if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
4960: operands[2] = force_reg (SImode, operands[2]);
4961:
4962: /* fall through and generate default code */
4963: }")
4964:
4965: (define_insn "sgtu_si"
4966: [(set (match_operand:SI 0 "register_operand" "=d")
4967: (gtu:SI (match_operand:SI 1 "register_operand" "d")
4968: (match_operand:SI 2 "reg_or_0_operand" "dJ")))]
4969: ""
4970: "sltu\\t%0,%z2,%1"
1.1.1.3 ! root 4971: [(set_attr "type" "arith")
1.1 root 4972: (set_attr "mode" "SI")
4973: (set_attr "length" "1")])
4974:
1.1.1.3 ! root 4975: (define_insn "sgtu_di"
! 4976: [(set (match_operand:DI 0 "register_operand" "=d")
! 4977: (gtu:DI (match_operand:DI 1 "register_operand" "d")
! 4978: (match_operand:DI 2 "reg_or_0_operand" "dJ")))]
! 4979: "TARGET_64BIT"
! 4980: "sltu\\t%0,%z2,%1"
! 4981: [(set_attr "type" "arith")
! 4982: (set_attr "mode" "DI")
! 4983: (set_attr "length" "1")])
! 4984:
1.1 root 4985: (define_expand "sgeu"
4986: [(set (match_operand:SI 0 "register_operand" "=d")
4987: (geu:SI (match_dup 1)
4988: (match_dup 2)))]
4989: ""
4990: "
4991: {
1.1.1.3 ! root 4992: if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
1.1 root 4993: FAIL;
4994:
4995: /* set up operands from compare. */
4996: operands[1] = branch_cmp[0];
4997: operands[2] = branch_cmp[1];
4998:
1.1.1.3 ! root 4999: if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
1.1 root 5000: {
5001: gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
5002: DONE;
5003: }
5004:
5005: /* fall through and generate default code */
5006: }")
5007:
5008: (define_insn "sgeu_si"
5009: [(set (match_operand:SI 0 "register_operand" "=d")
5010: (geu:SI (match_operand:SI 1 "register_operand" "d")
5011: (match_operand:SI 2 "arith_operand" "dI")))]
5012: "TARGET_DEBUG_C_MODE"
5013: "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
1.1.1.3 ! root 5014: [(set_attr "type" "arith")
1.1 root 5015: (set_attr "mode" "SI")
5016: (set_attr "length" "2")])
5017:
5018: (define_split
5019: [(set (match_operand:SI 0 "register_operand" "")
5020: (geu:SI (match_operand:SI 1 "register_operand" "")
5021: (match_operand:SI 2 "arith_operand" "")))]
5022: "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
5023: [(set (match_dup 0)
5024: (ltu:SI (match_dup 1)
5025: (match_dup 2)))
5026: (set (match_dup 0)
5027: (xor:SI (match_dup 0)
5028: (const_int 1)))]
5029: "")
5030:
1.1.1.3 ! root 5031: (define_insn "sgeu_di"
! 5032: [(set (match_operand:DI 0 "register_operand" "=d")
! 5033: (geu:DI (match_operand:DI 1 "register_operand" "d")
! 5034: (match_operand:DI 2 "arith_operand" "dI")))]
! 5035: "TARGET_64BIT && TARGET_DEBUG_C_MODE"
! 5036: "sltu\\t%0,%1,%2\;xori\\t%0,%0,0x0001"
! 5037: [(set_attr "type" "arith")
! 5038: (set_attr "mode" "DI")
! 5039: (set_attr "length" "2")])
! 5040:
! 5041: (define_split
! 5042: [(set (match_operand:DI 0 "register_operand" "")
! 5043: (geu:DI (match_operand:DI 1 "register_operand" "")
! 5044: (match_operand:DI 2 "arith_operand" "")))]
! 5045: "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
! 5046: [(set (match_dup 0)
! 5047: (ltu:DI (match_dup 1)
! 5048: (match_dup 2)))
! 5049: (set (match_dup 0)
! 5050: (xor:DI (match_dup 0)
! 5051: (const_int 1)))]
! 5052: "")
! 5053:
1.1 root 5054: (define_expand "sltu"
5055: [(set (match_operand:SI 0 "register_operand" "=d")
5056: (ltu:SI (match_dup 1)
5057: (match_dup 2)))]
5058: ""
5059: "
5060: {
1.1.1.3 ! root 5061: if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
1.1 root 5062: FAIL;
5063:
5064: /* set up operands from compare. */
5065: operands[1] = branch_cmp[0];
5066: operands[2] = branch_cmp[1];
5067:
1.1.1.3 ! root 5068: if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
1.1 root 5069: {
5070: gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
5071: DONE;
5072: }
5073:
5074: /* fall through and generate default code */
5075: }")
5076:
5077: (define_insn "sltu_si"
5078: [(set (match_operand:SI 0 "register_operand" "=d")
5079: (ltu:SI (match_operand:SI 1 "register_operand" "d")
5080: (match_operand:SI 2 "arith_operand" "dI")))]
5081: ""
5082: "sltu\\t%0,%1,%2"
1.1.1.3 ! root 5083: [(set_attr "type" "arith")
1.1 root 5084: (set_attr "mode" "SI")
5085: (set_attr "length" "1")])
5086:
1.1.1.3 ! root 5087: (define_insn "sltu_di"
! 5088: [(set (match_operand:DI 0 "register_operand" "=d")
! 5089: (ltu:DI (match_operand:DI 1 "register_operand" "d")
! 5090: (match_operand:DI 2 "arith_operand" "dI")))]
! 5091: "TARGET_64BIT"
! 5092: "sltu\\t%0,%1,%2"
! 5093: [(set_attr "type" "arith")
! 5094: (set_attr "mode" "DI")
! 5095: (set_attr "length" "1")])
! 5096:
1.1 root 5097: (define_expand "sleu"
5098: [(set (match_operand:SI 0 "register_operand" "=d")
5099: (leu:SI (match_dup 1)
5100: (match_dup 2)))]
5101: ""
5102: "
5103: {
1.1.1.3 ! root 5104: if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
1.1 root 5105: FAIL;
5106:
5107: /* set up operands from compare. */
5108: operands[1] = branch_cmp[0];
5109: operands[2] = branch_cmp[1];
5110:
1.1.1.3 ! root 5111: if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
1.1 root 5112: {
5113: gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
5114: DONE;
5115: }
5116:
5117: if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
5118: operands[2] = force_reg (SImode, operands[2]);
5119:
5120: /* fall through and generate default code */
5121: }")
5122:
5123: (define_insn "sleu_si_const"
5124: [(set (match_operand:SI 0 "register_operand" "=d")
5125: (leu:SI (match_operand:SI 1 "register_operand" "d")
5126: (match_operand:SI 2 "small_int" "I")))]
5127: "INTVAL (operands[2]) < 32767"
5128: "*
5129: {
5130: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
5131: return \"sltu\\t%0,%1,%2\";
5132: }"
1.1.1.3 ! root 5133: [(set_attr "type" "arith")
1.1 root 5134: (set_attr "mode" "SI")
5135: (set_attr "length" "1")])
5136:
1.1.1.3 ! root 5137: (define_insn "sleu_di_const"
! 5138: [(set (match_operand:DI 0 "register_operand" "=d")
! 5139: (leu:DI (match_operand:DI 1 "register_operand" "d")
! 5140: (match_operand:DI 2 "small_int" "I")))]
! 5141: "TARGET_64BIT && INTVAL (operands[2]) < 32767"
! 5142: "*
! 5143: {
! 5144: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2])+1);
! 5145: return \"sltu\\t%0,%1,%2\";
! 5146: }"
! 5147: [(set_attr "type" "arith")
! 5148: (set_attr "mode" "DI")
! 5149: (set_attr "length" "1")])
! 5150:
1.1 root 5151: (define_insn "sleu_si_reg"
5152: [(set (match_operand:SI 0 "register_operand" "=d")
5153: (leu:SI (match_operand:SI 1 "register_operand" "d")
5154: (match_operand:SI 2 "register_operand" "d")))]
5155: "TARGET_DEBUG_C_MODE"
5156: "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
1.1.1.3 ! root 5157: [(set_attr "type" "arith")
1.1 root 5158: (set_attr "mode" "SI")
5159: (set_attr "length" "2")])
5160:
5161: (define_split
5162: [(set (match_operand:SI 0 "register_operand" "")
5163: (leu:SI (match_operand:SI 1 "register_operand" "")
5164: (match_operand:SI 2 "register_operand" "")))]
5165: "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
5166: [(set (match_dup 0)
5167: (ltu:SI (match_dup 2)
5168: (match_dup 1)))
5169: (set (match_dup 0)
5170: (xor:SI (match_dup 0)
5171: (const_int 1)))]
5172: "")
5173:
1.1.1.3 ! root 5174: (define_insn "sleu_di_reg"
! 5175: [(set (match_operand:DI 0 "register_operand" "=d")
! 5176: (leu:DI (match_operand:DI 1 "register_operand" "d")
! 5177: (match_operand:DI 2 "register_operand" "d")))]
! 5178: "TARGET_64BIT && TARGET_DEBUG_C_MODE"
! 5179: "sltu\\t%0,%z2,%1\;xori\\t%0,%0,0x0001"
! 5180: [(set_attr "type" "arith")
! 5181: (set_attr "mode" "DI")
! 5182: (set_attr "length" "2")])
! 5183:
! 5184: (define_split
! 5185: [(set (match_operand:DI 0 "register_operand" "")
! 5186: (leu:DI (match_operand:DI 1 "register_operand" "")
! 5187: (match_operand:DI 2 "register_operand" "")))]
! 5188: "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE"
! 5189: [(set (match_dup 0)
! 5190: (ltu:DI (match_dup 2)
! 5191: (match_dup 1)))
! 5192: (set (match_dup 0)
! 5193: (xor:DI (match_dup 0)
! 5194: (const_int 1)))]
! 5195: "")
! 5196:
1.1 root 5197:
5198: ;;
5199: ;; ....................
5200: ;;
5201: ;; FLOATING POINT COMPARISONS
5202: ;;
5203: ;; ....................
5204:
5205: (define_insn "seq_df"
5206: [(set (reg:CC_FP 66)
5207: (eq:CC_FP (match_operand:DF 0 "register_operand" "f")
5208: (match_operand:DF 1 "register_operand" "f")))]
1.1.1.3 ! root 5209: "TARGET_HARD_FLOAT"
1.1 root 5210: "*
5211: {
5212: rtx xoperands[10];
5213: xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5214: xoperands[1] = operands[0];
5215: xoperands[2] = operands[1];
5216:
5217: return mips_fill_delay_slot (\"c.eq.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5218: }"
5219: [(set_attr "type" "fcmp")
5220: (set_attr "mode" "FPSW")
5221: (set_attr "length" "1")])
5222:
5223: (define_insn "sne_df"
5224: [(set (reg:CC_REV_FP 66)
5225: (ne:CC_REV_FP (match_operand:DF 0 "register_operand" "f")
5226: (match_operand:DF 1 "register_operand" "f")))]
1.1.1.3 ! root 5227: "TARGET_HARD_FLOAT"
1.1 root 5228: "*
5229: {
5230: rtx xoperands[10];
5231: xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5232: xoperands[1] = operands[0];
5233: xoperands[2] = operands[1];
5234:
5235: return mips_fill_delay_slot (\"c.eq.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5236: }"
5237: [(set_attr "type" "fcmp")
5238: (set_attr "mode" "FPSW")
5239: (set_attr "length" "1")])
5240:
5241: (define_insn "slt_df"
5242: [(set (reg:CC_FP 66)
5243: (lt:CC_FP (match_operand:DF 0 "register_operand" "f")
5244: (match_operand:DF 1 "register_operand" "f")))]
1.1.1.3 ! root 5245: "TARGET_HARD_FLOAT"
1.1 root 5246: "*
5247: {
5248: rtx xoperands[10];
5249: xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5250: xoperands[1] = operands[0];
5251: xoperands[2] = operands[1];
5252:
5253: return mips_fill_delay_slot (\"c.lt.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5254: }"
5255: [(set_attr "type" "fcmp")
5256: (set_attr "mode" "FPSW")
5257: (set_attr "length" "1")])
5258:
5259: (define_insn "sle_df"
5260: [(set (reg:CC_FP 66)
5261: (le:CC_FP (match_operand:DF 0 "register_operand" "f")
5262: (match_operand:DF 1 "register_operand" "f")))]
1.1.1.3 ! root 5263: "TARGET_HARD_FLOAT"
1.1 root 5264: "*
5265: {
5266: rtx xoperands[10];
5267: xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5268: xoperands[1] = operands[0];
5269: xoperands[2] = operands[1];
5270:
5271: return mips_fill_delay_slot (\"c.le.d\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5272: }"
5273: [(set_attr "type" "fcmp")
5274: (set_attr "mode" "FPSW")
5275: (set_attr "length" "1")])
5276:
5277: (define_insn "sgt_df"
5278: [(set (reg:CC_FP 66)
5279: (gt:CC_FP (match_operand:DF 0 "register_operand" "f")
5280: (match_operand:DF 1 "register_operand" "f")))]
1.1.1.3 ! root 5281: "TARGET_HARD_FLOAT"
1.1 root 5282: "*
5283: {
5284: rtx xoperands[10];
5285: xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5286: xoperands[1] = operands[0];
5287: xoperands[2] = operands[1];
5288:
5289: return mips_fill_delay_slot (\"c.lt.d\\t%1,%0\", DELAY_FCMP, xoperands, insn);
5290: }"
5291: [(set_attr "type" "fcmp")
5292: (set_attr "mode" "FPSW")
5293: (set_attr "length" "1")])
5294:
5295: (define_insn "sge_df"
5296: [(set (reg:CC_FP 66)
5297: (ge:CC_FP (match_operand:DF 0 "register_operand" "f")
5298: (match_operand:DF 1 "register_operand" "f")))]
1.1.1.3 ! root 5299: "TARGET_HARD_FLOAT"
1.1 root 5300: "*
5301: {
5302: rtx xoperands[10];
5303: xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5304: xoperands[1] = operands[0];
5305: xoperands[2] = operands[1];
5306:
5307: return mips_fill_delay_slot (\"c.le.d\\t%1,%0\", DELAY_FCMP, xoperands, insn);
5308: }"
5309: [(set_attr "type" "fcmp")
5310: (set_attr "mode" "FPSW")
5311: (set_attr "length" "1")])
5312:
5313: (define_insn "seq_sf"
5314: [(set (reg:CC_FP 66)
5315: (eq:CC_FP (match_operand:SF 0 "register_operand" "f")
5316: (match_operand:SF 1 "register_operand" "f")))]
1.1.1.3 ! root 5317: "TARGET_HARD_FLOAT"
1.1 root 5318: "*
5319: {
5320: rtx xoperands[10];
5321: xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5322: xoperands[1] = operands[0];
5323: xoperands[2] = operands[1];
5324:
5325: return mips_fill_delay_slot (\"c.eq.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5326: }"
5327: [(set_attr "type" "fcmp")
5328: (set_attr "mode" "FPSW")
5329: (set_attr "length" "1")])
5330:
5331: (define_insn "sne_sf"
5332: [(set (reg:CC_REV_FP 66)
5333: (ne:CC_REV_FP (match_operand:SF 0 "register_operand" "f")
5334: (match_operand:SF 1 "register_operand" "f")))]
1.1.1.3 ! root 5335: "TARGET_HARD_FLOAT"
1.1 root 5336: "*
5337: {
5338: rtx xoperands[10];
5339: xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5340: xoperands[1] = operands[0];
5341: xoperands[2] = operands[1];
5342:
5343: return mips_fill_delay_slot (\"c.eq.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5344: }"
5345: [(set_attr "type" "fcmp")
5346: (set_attr "mode" "FPSW")
5347: (set_attr "length" "1")])
5348:
5349: (define_insn "slt_sf"
5350: [(set (reg:CC_FP 66)
5351: (lt:CC_FP (match_operand:SF 0 "register_operand" "f")
5352: (match_operand:SF 1 "register_operand" "f")))]
1.1.1.3 ! root 5353: "TARGET_HARD_FLOAT"
1.1 root 5354: "*
5355: {
5356: rtx xoperands[10];
5357: xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5358: xoperands[1] = operands[0];
5359: xoperands[2] = operands[1];
5360:
5361: return mips_fill_delay_slot (\"c.lt.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5362: }"
5363: [(set_attr "type" "fcmp")
5364: (set_attr "mode" "FPSW")
5365: (set_attr "length" "1")])
5366:
5367: (define_insn "sle_sf"
5368: [(set (reg:CC_FP 66)
5369: (le:CC_FP (match_operand:SF 0 "register_operand" "f")
5370: (match_operand:SF 1 "register_operand" "f")))]
1.1.1.3 ! root 5371: "TARGET_HARD_FLOAT"
1.1 root 5372: "*
5373: {
5374: rtx xoperands[10];
5375: xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5376: xoperands[1] = operands[0];
5377: xoperands[2] = operands[1];
5378:
5379: return mips_fill_delay_slot (\"c.le.s\\t%0,%1\", DELAY_FCMP, xoperands, insn);
5380: }"
5381: [(set_attr "type" "fcmp")
5382: (set_attr "mode" "FPSW")
5383: (set_attr "length" "1")])
5384:
5385: (define_insn "sgt_sf"
5386: [(set (reg:CC_FP 66)
5387: (gt:CC_FP (match_operand:SF 0 "register_operand" "f")
5388: (match_operand:SF 1 "register_operand" "f")))]
1.1.1.3 ! root 5389: "TARGET_HARD_FLOAT"
1.1 root 5390: "*
5391: {
5392: rtx xoperands[10];
5393: xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5394: xoperands[1] = operands[0];
5395: xoperands[2] = operands[1];
5396:
5397: return mips_fill_delay_slot (\"c.lt.s\\t%1,%0\", DELAY_FCMP, xoperands, insn);
5398: }"
5399: [(set_attr "type" "fcmp")
5400: (set_attr "mode" "FPSW")
5401: (set_attr "length" "1")])
5402:
5403: (define_insn "sge_sf"
5404: [(set (reg:CC_FP 66)
5405: (ge:CC_FP (match_operand:SF 0 "register_operand" "f")
5406: (match_operand:SF 1 "register_operand" "f")))]
1.1.1.3 ! root 5407: "TARGET_HARD_FLOAT"
1.1 root 5408: "*
5409: {
5410: rtx xoperands[10];
5411: xoperands[0] = gen_rtx (REG, CC_FPmode, FPSW_REGNUM);
5412: xoperands[1] = operands[0];
5413: xoperands[2] = operands[1];
5414:
5415: return mips_fill_delay_slot (\"c.le.s\\t%1,%0\", DELAY_FCMP, xoperands, insn);
5416: }"
5417: [(set_attr "type" "fcmp")
5418: (set_attr "mode" "FPSW")
5419: (set_attr "length" "1")])
5420:
5421:
5422: ;;
5423: ;; ....................
5424: ;;
5425: ;; UNCONDITIONAL BRANCHES
5426: ;;
5427: ;; ....................
5428:
5429: ;; Unconditional branches.
5430:
5431: (define_insn "jump"
5432: [(set (pc)
5433: (label_ref (match_operand 0 "" "")))]
5434: ""
5435: "*
5436: {
5437: if (GET_CODE (operands[0]) == REG)
5438: return \"%*j\\t%0\";
5439: else
5440: return \"%*j\\t%l0\";
5441: }"
5442: [(set_attr "type" "jump")
5443: (set_attr "mode" "none")
5444: (set_attr "length" "1")])
5445:
1.1.1.3 ! root 5446: (define_expand "indirect_jump"
! 5447: [(set (pc) (match_operand 0 "register_operand" "d"))]
1.1 root 5448: ""
1.1.1.3 ! root 5449: "
! 5450: {
! 5451: rtx dest;
! 5452:
! 5453: if (operands[0]) /* eliminate unused code warnings */
! 5454: {
! 5455: dest = operands[0];
! 5456: if (GET_CODE (dest) != REG || GET_MODE (dest) != Pmode)
! 5457: operands[0] = copy_to_mode_reg (Pmode, dest);
! 5458:
! 5459: if (!TARGET_LONG64)
! 5460: emit_jump_insn (gen_indirect_jump_internal1 (operands[0]));
! 5461: else
! 5462: emit_jump_insn (gen_indirect_jump_internal2 (operands[0]));
! 5463:
! 5464: DONE;
! 5465: }
! 5466: }")
! 5467:
! 5468: (define_insn "indirect_jump_internal1"
! 5469: [(set (pc) (match_operand:SI 0 "register_operand" "d"))]
! 5470: "!TARGET_LONG64"
! 5471: "%*j\\t%0"
! 5472: [(set_attr "type" "jump")
! 5473: (set_attr "mode" "none")
! 5474: (set_attr "length" "1")])
! 5475:
! 5476: (define_insn "indirect_jump_internal2"
! 5477: [(set (pc) (match_operand:DI 0 "register_operand" "d"))]
! 5478: "TARGET_LONG64"
1.1 root 5479: "%*j\\t%0"
5480: [(set_attr "type" "jump")
5481: (set_attr "mode" "none")
5482: (set_attr "length" "1")])
5483:
1.1.1.3 ! root 5484: (define_expand "tablejump"
1.1 root 5485: [(set (pc)
1.1.1.3 ! root 5486: (match_operand 0 "register_operand" "d"))
1.1 root 5487: (use (label_ref (match_operand 1 "" "")))]
5488: ""
1.1.1.3 ! root 5489: "
! 5490: {
! 5491: rtx dest;
! 5492:
! 5493: if (operands[0]) /* eliminate unused code warnings */
! 5494: {
! 5495: if (GET_MODE (operands[0]) != Pmode)
! 5496: abort ();
! 5497:
! 5498: if (!TARGET_LONG64)
! 5499: emit_jump_insn (gen_tablejump_internal1 (operands[0], operands[1]));
! 5500: else
! 5501: emit_jump_insn (gen_tablejump_internal2 (operands[0], operands[1]));
! 5502:
! 5503: DONE;
! 5504: }
! 5505: }")
! 5506:
! 5507: (define_insn "tablejump_internal1"
! 5508: [(set (pc)
! 5509: (match_operand:SI 0 "register_operand" "d"))
! 5510: (use (label_ref (match_operand 1 "" "")))]
! 5511: "!TARGET_LONG64"
! 5512: "*
! 5513: {
! 5514: /* .cpadd expands to add REG,REG,$gp when pic, and nothing when not pic. */
! 5515: if (TARGET_ABICALLS)
! 5516: output_asm_insn (\".cpadd\\t%0\", operands);
! 5517: return \"%*j\\t%0\";
! 5518: }"
1.1 root 5519: [(set_attr "type" "jump")
5520: (set_attr "mode" "none")
1.1.1.3 ! root 5521: (set (attr "length")
! 5522: (if_then_else (eq_attr "abicalls" "yes")
! 5523: (const_int 2)
! 5524: (const_int 1)))])
! 5525:
! 5526: (define_insn "tablejump_internal2"
! 5527: [(set (pc)
! 5528: (match_operand:DI 0 "register_operand" "d"))
! 5529: (use (label_ref (match_operand 1 "" "")))]
! 5530: "TARGET_LONG64"
! 5531: "*
! 5532: {
! 5533: /* .cpdadd expands to dadd REG,REG,$gp when pic, and nothing when not pic. */
! 5534: if (TARGET_ABICALLS)
! 5535: output_asm_insn (\".cpdadd\\t%0\", operands);
! 5536: return \"%*j\\t%0\";
! 5537: }"
! 5538: [(set_attr "type" "jump")
! 5539: (set_attr "mode" "none")
! 5540: (set (attr "length")
! 5541: (if_then_else (eq_attr "abicalls" "yes")
! 5542: (const_int 2)
! 5543: (const_int 1)))])
1.1 root 5544:
5545: ;; Function return, only allow after optimization, so that we can
5546: ;; eliminate jumps to jumps if no stack space is used.
5547:
5548: ;; (define_expand "return"
5549: ;; [(set (pc) (reg:SI 31))]
5550: ;; "simple_epilogue_p ()"
5551: ;; "")
5552:
5553: (define_expand "return"
5554: [(parallel [(return)
5555: (use (reg:SI 31))])]
5556: "simple_epilogue_p ()"
5557: "")
5558:
5559: (define_insn "return_internal"
5560: [(parallel [(return)
5561: (use (match_operand:SI 0 "register_operand" "d"))])]
5562: ""
5563: "%*j\\t%0"
5564: [(set_attr "type" "jump")
5565: (set_attr "mode" "none")
5566: (set_attr "length" "1")])
5567:
1.1.1.3 ! root 5568: ;; Implement a switch statement when generating embedded PIC code.
! 5569: ;; Switches are implemented by `tablejump' when not using -membedded-pic.
! 5570:
! 5571: (define_expand "casesi"
! 5572: [(set (match_dup 5)
! 5573: (minus:SI (match_operand:SI 0 "register_operand" "d")
! 5574: (match_operand:SI 1 "arith_operand" "dI")))
! 5575: (set (cc0)
! 5576: (compare:CC (match_dup 5)
! 5577: (match_operand:SI 2 "arith_operand" "")))
! 5578: (set (pc)
! 5579: (if_then_else (gtu (cc0)
! 5580: (const_int 0))
! 5581: (label_ref (match_operand 4 "" ""))
! 5582: (pc)))
! 5583: (parallel
! 5584: [(set (pc)
! 5585: (mem:SI (plus:SI (mult:SI (match_dup 5)
! 5586: (const_int 4))
! 5587: (label_ref (match_operand 3 "" "")))))
! 5588: (clobber (match_scratch:SI 6 ""))
! 5589: (clobber (reg:SI 31))])]
! 5590: "TARGET_EMBEDDED_PIC"
! 5591: "
! 5592: {
! 5593: /* We need slightly different code for eight byte table entries. */
! 5594: if (TARGET_LONG64)
! 5595: abort ();
! 5596:
! 5597: if (operands[0])
! 5598: {
! 5599: rtx reg = gen_reg_rtx (SImode);
! 5600:
! 5601: /* If the index is too large, go to the default label. */
! 5602: emit_insn (gen_subsi3 (reg, operands[0], operands[1]));
! 5603: emit_insn (gen_cmpsi (reg, operands[2]));
! 5604: emit_insn (gen_bgtu (operands[4]));
! 5605:
! 5606: /* Do the PIC jump. */
! 5607: emit_insn (gen_casesi_internal (reg, operands[3], gen_reg_rtx (SImode)));
! 5608:
! 5609: DONE;
! 5610: }
! 5611: }")
! 5612:
! 5613: ;; An embedded PIC switch statement looks like this:
! 5614: ;; bal $LS1
! 5615: ;; sll $reg,$index,2
! 5616: ;; $LS1:
! 5617: ;; addu $reg,$reg,$31
! 5618: ;; lw $reg,$L1-$LS1($reg)
! 5619: ;; addu $reg,$reg,$31
! 5620: ;; j $reg
! 5621: ;; $L1:
! 5622: ;; .word case1-$LS1
! 5623: ;; .word case2-$LS1
! 5624: ;; ...
! 5625:
! 5626: (define_insn "casesi_internal"
! 5627: [(set (pc)
! 5628: (mem:SI (plus:SI (mult:SI (match_operand:SI 0 "register_operand" "d")
! 5629: (const_int 4))
! 5630: (label_ref (match_operand 1 "" "")))))
! 5631: (clobber (match_operand:SI 2 "register_operand" "d"))
! 5632: (clobber (reg:SI 31))]
! 5633: "TARGET_EMBEDDED_PIC"
! 5634: "*
! 5635: {
! 5636: output_asm_insn (\"%(bal\\t%S1\;sll\\t%0,2\\n%S1:\", operands);
! 5637: output_asm_insn (\"addu\\t%0,%0,$31%)\", operands);
! 5638: output_asm_insn (\"lw\\t%0,%1-%S1(%0)\;addu\\t%0,%0,$31\", operands);
! 5639: return \"j\\t%0\";
! 5640: }"
! 5641: [(set_attr "type" "jump")
! 5642: (set_attr "mode" "none")
! 5643: (set_attr "length" "6")])
! 5644:
1.1 root 5645:
5646: ;;
5647: ;; ....................
5648: ;;
5649: ;; Function prologue/epilogue
5650: ;;
5651: ;; ....................
5652: ;;
5653:
5654: (define_expand "prologue"
5655: [(const_int 1)]
5656: ""
5657: "
5658: {
5659: if (mips_isa >= 0) /* avoid unused code warnings */
5660: {
5661: mips_expand_prologue ();
5662: DONE;
5663: }
5664: }")
5665:
5666: ;; Block any insns from being moved before this point, since the
5667: ;; profiling call to mcount can use various registers that aren't
5668: ;; saved or used to pass arguments.
5669:
5670: (define_insn "blockage"
5671: [(unspec_volatile [(const_int 0)] 0)]
5672: ""
5673: ""
5674: [(set_attr "type" "unknown")
5675: (set_attr "mode" "none")
5676: (set_attr "length" "0")])
5677:
5678: ;; At present, don't expand the epilogue, reorg.c will clobber the
5679: ;; return register in compiling gen_lowpart (emit-rtl.c).
5680: ;;
5681: ;; (define_expand "epilogue"
5682: ;; [(const_int 2)]
5683: ;; ""
5684: ;; "
5685: ;; {
5686: ;; if (mips_isa >= 0) /* avoid unused code warnings */
5687: ;; {
5688: ;; mips_expand_epilogue ();
5689: ;; DONE;
5690: ;; }
5691: ;; }")
5692:
1.1.1.3 ! root 5693: ;; When generating embedded PIC code we need to get the address of the
! 5694: ;; current function. This specialized instruction does just that.
! 5695:
! 5696: (define_insn "get_fnaddr"
! 5697: [(set (match_operand 0 "register_operand" "d")
! 5698: (unspec [(match_operand 1 "" "")] 1))
! 5699: (clobber (reg:SI 31))]
! 5700: "TARGET_EMBEDDED_PIC
! 5701: && GET_CODE (operands[1]) == SYMBOL_REF"
! 5702: "%($LF%= = . + 8\;bal\\t$LF%=\;la\\t%0,%1-$LF%=%)\;addu\\t%0,%0,$31"
! 5703: [(set_attr "type" "call")
! 5704: (set_attr "mode" "none")
! 5705: (set_attr "length" "4")])
! 5706:
1.1 root 5707:
5708: ;;
5709: ;; ....................
5710: ;;
5711: ;; FUNCTION CALLS
5712: ;;
5713: ;; ....................
5714:
5715: ;; calls.c now passes a third argument, make saber happy
5716:
5717: (define_expand "call"
5718: [(parallel [(call (match_operand 0 "memory_operand" "m")
5719: (match_operand 1 "" "i"))
5720: (clobber (reg:SI 31))
5721: (use (match_operand 2 "" "")) ;; next_arg_reg
5722: (use (match_operand 3 "" ""))])] ;; struct_value_size_rtx
5723: ""
5724: "
5725: {
5726: rtx addr;
5727:
5728: if (operands[0]) /* eliminate unused code warnings */
5729: {
5730: addr = XEXP (operands[0], 0);
5731: if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
5732: || ! call_insn_operand (operands[0], VOIDmode))
5733: XEXP (operands[0], 0) = copy_to_mode_reg (Pmode, addr);
5734:
5735: /* In order to pass small structures by value in registers
5736: compatibly with the MIPS compiler, we need to shift the value
5737: into the high part of the register. Function_arg has encoded
5738: a PARALLEL rtx, holding a vector of adjustments to be made
5739: as the next_arg_reg variable, so we split up the insns,
5740: and emit them separately. */
5741:
5742: if (operands[2] != (rtx)0 && GET_CODE (operands[2]) == PARALLEL)
5743: {
5744: rtvec adjust = XVEC (operands[2], 0);
5745: int num = GET_NUM_ELEM (adjust);
5746: int i;
5747:
5748: for (i = 0; i < num; i++)
5749: emit_insn (RTVEC_ELT (adjust, i));
5750: }
5751:
5752: emit_call_insn (gen_call_internal1 (operands[0], operands[1],
1.1.1.3 ! root 5753: gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
1.1 root 5754: DONE;
5755: }
5756: }")
5757:
5758: (define_insn "call_internal1"
5759: [(call (match_operand 0 "call_insn_operand" "m")
5760: (match_operand 1 "" "i"))
5761: (clobber (match_operand:SI 2 "register_operand" "=d"))]
1.1.1.2 root 5762: "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
1.1 root 5763: "*
5764: {
5765: register rtx target = XEXP (operands[0], 0);
5766:
5767: if (GET_CODE (target) == SYMBOL_REF)
5768: return \"%*jal\\t%0\";
5769:
5770: else if (GET_CODE (target) == CONST_INT)
5771: {
5772: operands[0] = target;
5773: return \"%*%[li\\t%@,%0\\n\\tjal\\t%2,%@%]\";
5774: }
5775:
5776: else
5777: {
5778: operands[0] = target;
5779: return \"%*jal\\t%2,%0\";
5780: }
5781: }"
5782: [(set_attr "type" "call")
5783: (set_attr "mode" "none")
5784: (set_attr "length" "1")])
5785:
5786: (define_insn "call_internal2"
1.1.1.2 root 5787: [(call (match_operand 0 "call_insn_operand" "m")
5788: (match_operand 1 "" "i"))
5789: (clobber (match_operand:SI 2 "register_operand" "=d"))]
5790: "TARGET_ABICALLS && !TARGET_LONG_CALLS"
5791: "*
5792: {
5793: register rtx target = XEXP (operands[0], 0);
5794:
5795: if (GET_CODE (target) == SYMBOL_REF)
5796: return \"jal\\t%0\";
5797:
5798: else if (GET_CODE (target) == CONST_INT)
5799: {
5800: operands[0] = target;
5801: return \"li\\t%^,%0\\n\\tjal\\t%2,%^\";
5802: }
5803:
5804: else
5805: {
5806: operands[0] = target;
5807: if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
5808: return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
5809: else
5810: return \"jal\\t%2,%0\";
5811: }
5812: }"
5813: [(set_attr "type" "call")
5814: (set_attr "mode" "none")
5815: (set_attr "length" "2")])
5816:
1.1.1.3 ! root 5817: (define_insn "call_internal3a"
1.1 root 5818: [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
5819: (match_operand 1 "" "i"))
5820: (clobber (match_operand:SI 2 "register_operand" "=d"))]
1.1.1.3 ! root 5821: "!TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS"
! 5822: "%*jal\\t%2,%0"
! 5823: [(set_attr "type" "call")
! 5824: (set_attr "mode" "none")
! 5825: (set_attr "length" "1")])
! 5826:
! 5827: (define_insn "call_internal3b"
! 5828: [(call (mem:DI (match_operand:DI 0 "register_operand" "r"))
! 5829: (match_operand 1 "" "i"))
! 5830: (clobber (match_operand:SI 2 "register_operand" "=d"))]
! 5831: "TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS"
1.1 root 5832: "%*jal\\t%2,%0"
5833: [(set_attr "type" "call")
5834: (set_attr "mode" "none")
5835: (set_attr "length" "1")])
5836:
1.1.1.3 ! root 5837: (define_insn "call_internal4a"
1.1.1.2 root 5838: [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
5839: (match_operand 1 "" "i"))
5840: (clobber (match_operand:SI 2 "register_operand" "=d"))]
1.1.1.3 ! root 5841: "!TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS"
1.1.1.2 root 5842: "*
5843: {
5844: if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
5845: return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
5846: else
5847: return \"jal\\t%2,%0\";
5848: }"
5849: [(set_attr "type" "call")
5850: (set_attr "mode" "none")
5851: (set_attr "length" "2")])
5852:
1.1.1.3 ! root 5853: (define_insn "call_internal4b"
! 5854: [(call (mem:DI (match_operand:DI 0 "register_operand" "r"))
! 5855: (match_operand 1 "" "i"))
! 5856: (clobber (match_operand:SI 2 "register_operand" "=d"))]
! 5857: "TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS"
! 5858: "*
! 5859: {
! 5860: if (REGNO (operands[0]) != PIC_FUNCTION_ADDR_REGNUM)
! 5861: return \"move\\t%^,%0\\n\\tjal\\t%2,%^\";
! 5862: else
! 5863: return \"jal\\t%2,%0\";
! 5864: }"
! 5865: [(set_attr "type" "call")
! 5866: (set_attr "mode" "none")
! 5867: (set_attr "length" "2")])
1.1 root 5868:
5869: ;; calls.c now passes a fourth argument, make saber happy
5870:
5871: (define_expand "call_value"
5872: [(parallel [(set (match_operand 0 "register_operand" "=df")
5873: (call (match_operand 1 "memory_operand" "m")
5874: (match_operand 2 "" "i")))
5875: (clobber (reg:SI 31))
5876: (use (match_operand 3 "" ""))])] ;; next_arg_reg
5877: ""
5878: "
5879: {
5880: rtx addr;
5881:
5882: if (operands[0]) /* eliminate unused code warning */
5883: {
5884: addr = XEXP (operands[1], 0);
5885: if ((GET_CODE (addr) != REG && (!CONSTANT_ADDRESS_P (addr) || TARGET_LONG_CALLS))
5886: || ! call_insn_operand (operands[1], VOIDmode))
5887: XEXP (operands[1], 0) = copy_to_mode_reg (Pmode, addr);
5888:
5889: /* In order to pass small structures by value in registers
5890: compatibly with the MIPS compiler, we need to shift the value
5891: into the high part of the register. Function_arg has encoded
5892: a PARALLEL rtx, holding a vector of adjustments to be made
5893: as the next_arg_reg variable, so we split up the insns,
5894: and emit them separately. */
5895:
5896: if (operands[3] != (rtx)0 && GET_CODE (operands[3]) == PARALLEL)
5897: {
5898: rtvec adjust = XVEC (operands[3], 0);
5899: int num = GET_NUM_ELEM (adjust);
5900: int i;
5901:
5902: for (i = 0; i < num; i++)
5903: emit_insn (RTVEC_ELT (adjust, i));
5904: }
5905:
5906: emit_call_insn (gen_call_value_internal1 (operands[0], operands[1], operands[2],
1.1.1.3 ! root 5907: gen_rtx (REG, SImode, GP_REG_FIRST + 31)));
1.1 root 5908:
5909: DONE;
5910: }
5911:
5912: }")
5913:
5914: (define_insn "call_value_internal1"
5915: [(set (match_operand 0 "register_operand" "=df")
5916: (call (match_operand 1 "call_insn_operand" "m")
5917: (match_operand 2 "" "i")))
5918: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.2 root 5919: "!TARGET_ABICALLS && !TARGET_LONG_CALLS"
1.1 root 5920: "*
5921: {
5922: register rtx target = XEXP (operands[1], 0);
5923:
5924: if (GET_CODE (target) == SYMBOL_REF)
5925: return \"%*jal\\t%1\";
5926:
5927: else if (GET_CODE (target) == CONST_INT)
5928: {
5929: operands[1] = target;
5930: return \"%*%[li\\t%@,%1\\n\\tjal\\t%3,%@%]\";
5931: }
5932:
5933: else
5934: {
5935: operands[1] = target;
5936: return \"%*jal\\t%3,%1\";
5937: }
5938: }"
5939: [(set_attr "type" "call")
5940: (set_attr "mode" "none")
5941: (set_attr "length" "1")])
5942:
5943: (define_insn "call_value_internal2"
5944: [(set (match_operand 0 "register_operand" "=df")
1.1.1.2 root 5945: (call (match_operand 1 "call_insn_operand" "m")
5946: (match_operand 2 "" "i")))
5947: (clobber (match_operand:SI 3 "register_operand" "=d"))]
5948: "TARGET_ABICALLS && !TARGET_LONG_CALLS"
5949: "*
5950: {
5951: register rtx target = XEXP (operands[1], 0);
5952:
5953: if (GET_CODE (target) == SYMBOL_REF)
5954: return \"jal\\t%1\";
5955:
5956: else if (GET_CODE (target) == CONST_INT)
5957: {
5958: operands[1] = target;
5959: return \"li\\t%^,%1\\n\\tjal\\t%3,%^\";
5960: }
5961:
5962: else
5963: {
5964: operands[1] = target;
5965: if (REGNO (target) != PIC_FUNCTION_ADDR_REGNUM)
5966: return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
5967: else
5968: return \"jal\\t%3,%1\";
5969: }
5970: }"
5971: [(set_attr "type" "call")
5972: (set_attr "mode" "none")
5973: (set_attr "length" "2")])
5974:
1.1.1.3 ! root 5975: (define_insn "call_value_internal3a"
1.1.1.2 root 5976: [(set (match_operand 0 "register_operand" "=df")
1.1 root 5977: (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
5978: (match_operand 2 "" "i")))
5979: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 5980: "!TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS"
! 5981: "%*jal\\t%3,%1"
! 5982: [(set_attr "type" "call")
! 5983: (set_attr "mode" "none")
! 5984: (set_attr "length" "1")])
! 5985:
! 5986: (define_insn "call_value_internal3b"
! 5987: [(set (match_operand 0 "register_operand" "=df")
! 5988: (call (mem:DI (match_operand:DI 1 "register_operand" "r"))
! 5989: (match_operand 2 "" "i")))
! 5990: (clobber (match_operand:SI 3 "register_operand" "=d"))]
! 5991: "TARGET_LONG64 && !TARGET_ABICALLS && TARGET_LONG_CALLS"
1.1 root 5992: "%*jal\\t%3,%1"
5993: [(set_attr "type" "call")
5994: (set_attr "mode" "none")
5995: (set_attr "length" "1")])
5996:
1.1.1.3 ! root 5997: (define_insn "call_value_internal4a"
1.1.1.2 root 5998: [(set (match_operand 0 "register_operand" "=df")
5999: (call (mem:SI (match_operand:SI 1 "register_operand" "r"))
6000: (match_operand 2 "" "i")))
6001: (clobber (match_operand:SI 3 "register_operand" "=d"))]
1.1.1.3 ! root 6002: "!TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS"
! 6003: "*
! 6004: {
! 6005: if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
! 6006: return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
! 6007: else
! 6008: return \"jal\\t%3,%1\";
! 6009: }"
! 6010: [(set_attr "type" "call")
! 6011: (set_attr "mode" "none")
! 6012: (set_attr "length" "2")])
! 6013:
! 6014: (define_insn "call_value_internal4b"
! 6015: [(set (match_operand 0 "register_operand" "=df")
! 6016: (call (mem:DI (match_operand:DI 1 "register_operand" "r"))
! 6017: (match_operand 2 "" "i")))
! 6018: (clobber (match_operand:SI 3 "register_operand" "=d"))]
! 6019: "TARGET_LONG64 && TARGET_ABICALLS && TARGET_LONG_CALLS"
1.1.1.2 root 6020: "*
6021: {
6022: if (REGNO (operands[1]) != PIC_FUNCTION_ADDR_REGNUM)
6023: return \"move\\t%^,%1\\n\\tjal\\t%3,%^\";
6024: else
6025: return \"jal\\t%3,%1\";
6026: }"
6027: [(set_attr "type" "call")
6028: (set_attr "mode" "none")
6029: (set_attr "length" "2")])
6030:
1.1 root 6031: ;; Call subroutine returning any type.
6032:
6033: (define_expand "untyped_call"
6034: [(parallel [(call (match_operand 0 "" "")
6035: (const_int 0))
6036: (match_operand 1 "" "")
6037: (match_operand 2 "" "")])]
6038: ""
6039: "
6040: {
6041: if (operands[0]) /* silence statement not reached warnings */
6042: {
6043: int i;
6044:
6045: emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6046:
6047: for (i = 0; i < XVECLEN (operands[2], 0); i++)
6048: {
6049: rtx set = XVECEXP (operands[2], 0, i);
6050: emit_move_insn (SET_DEST (set), SET_SRC (set));
6051: }
6052:
6053: emit_insn (gen_blockage ());
6054: DONE;
6055: }
6056: }")
6057:
6058: ;;
6059: ;; ....................
6060: ;;
6061: ;; MISC.
6062: ;;
6063: ;; ....................
6064: ;;
6065:
6066: (define_insn "nop"
6067: [(const_int 0)]
6068: ""
6069: "%(nop%)"
6070: [(set_attr "type" "nop")
6071: (set_attr "mode" "none")
6072: (set_attr "length" "1")])
6073:
6074: (define_expand "probe"
6075: [(set (match_dup 0)
6076: (match_dup 1))]
6077: ""
6078: "
6079: {
6080: operands[0] = gen_reg_rtx (SImode);
6081: operands[1] = gen_rtx (MEM, SImode, stack_pointer_rtx);
6082: MEM_VOLATILE_P (operands[1]) = TRUE;
6083:
6084: /* fall through and generate default code */
6085: }")
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