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1.1 ! root 1: ;; BUGS: ! 2: ;; Insert no-op between an insn with memory read-write operands ! 3: ;; following by a scale-indexing operation. ! 4: ;; The Sequent assembler does not allow addresses to be used ! 5: ;; except in insns which explicitly compute an effective address. ! 6: ;; I.e., one cannot say "cmpd _p,@_x" ! 7: ;; Implement unsigned multiplication?? ! 8: ! 9: ;;- Machine descrption for GNU compiler ! 10: ;;- ns32000 Version ! 11: ;; Copyright (C) 1988 Free Software Foundation, Inc. ! 12: ;; Contributed by Michael Tiemann ([email protected]) ! 13: ! 14: ;; This file is part of GNU CC. ! 15: ! 16: ;; GNU CC is free software; you can redistribute it and/or modify ! 17: ;; it under the terms of the GNU General Public License as published by ! 18: ;; the Free Software Foundation; either version 1, or (at your option) ! 19: ;; any later version. ! 20: ! 21: ;; GNU CC is distributed in the hope that it will be useful, ! 22: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of ! 23: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ! 24: ;; GNU General Public License for more details. ! 25: ! 26: ;; You should have received a copy of the GNU General Public License ! 27: ;; along with GNU CC; see the file COPYING. If not, write to ! 28: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. ! 29: ! 30: ! 31: ;;- Instruction patterns. When multiple patterns apply, ! 32: ;;- the first one in the file is chosen. ! 33: ;;- ! 34: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. ! 35: ;;- ! 36: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code ! 37: ;;- updates for most instructions. ! 38: ! 39: ; tstsi is first test insn so that it is the one to match ! 40: ; a constant argument. ! 41: ! 42: (define_insn "tstsi" ! 43: [(set (cc0) ! 44: (match_operand:SI 0 "general_operand" "rmn"))] ! 45: "" ! 46: "* ! 47: { cc_status.flags |= CC_REVERSED; ! 48: operands[1] = const0_rtx; ! 49: return \"cmpqd %1,%0\"; }") ! 50: ! 51: (define_insn "tsthi" ! 52: [(set (cc0) ! 53: (match_operand:HI 0 "general_operand" "g"))] ! 54: "" ! 55: "* ! 56: { cc_status.flags |= CC_REVERSED; ! 57: operands[1] = const0_rtx; ! 58: return \"cmpqw %1,%0\"; }") ! 59: ! 60: (define_insn "tstqi" ! 61: [(set (cc0) ! 62: (match_operand:QI 0 "general_operand" "g"))] ! 63: "" ! 64: "* ! 65: { cc_status.flags |= CC_REVERSED; ! 66: operands[1] = const0_rtx; ! 67: return \"cmpqb %1,%0\"; }") ! 68: ! 69: (define_insn "tstdf" ! 70: [(set (cc0) ! 71: (match_operand:DF 0 "general_operand" "fmF"))] ! 72: "TARGET_32081" ! 73: "* ! 74: { cc_status.flags |= CC_REVERSED; ! 75: operands[1] = dconst0_rtx; ! 76: return \"cmpl %1,%0\"; }") ! 77: ! 78: (define_insn "tstsf" ! 79: [(set (cc0) ! 80: (match_operand:SF 0 "general_operand" "fmF"))] ! 81: "TARGET_32081" ! 82: "* ! 83: { cc_status.flags |= CC_REVERSED; ! 84: operands[1] = fconst0_rtx; ! 85: return \"cmpf %1,%0\"; }") ! 86: ! 87: ;; Put cmpsi first among compare insns so it matches two CONST_INT operands. ! 88: ! 89: (define_insn "cmpsi" ! 90: [(set (cc0) ! 91: (compare (match_operand:SI 0 "general_operand" "rmn") ! 92: (match_operand:SI 1 "general_operand" "rmn")))] ! 93: "" ! 94: "* ! 95: { ! 96: if (GET_CODE (operands[1]) == CONST_INT) ! 97: { ! 98: int i = INTVAL (operands[1]); ! 99: if (i <= 7 && i >= -8) ! 100: { ! 101: cc_status.flags |= CC_REVERSED; ! 102: return \"cmpqd %1,%0\"; ! 103: } ! 104: } ! 105: cc_status.flags &= ~CC_REVERSED; ! 106: if (GET_CODE (operands[0]) == CONST_INT) ! 107: { ! 108: int i = INTVAL (operands[0]); ! 109: if (i <= 7 && i >= -8) ! 110: return \"cmpqd %0,%1\"; ! 111: } ! 112: return \"cmpd %0,%1\"; ! 113: }") ! 114: ! 115: (define_insn "cmphi" ! 116: [(set (cc0) ! 117: (compare (match_operand:HI 0 "general_operand" "g") ! 118: (match_operand:HI 1 "general_operand" "g")))] ! 119: "" ! 120: "* ! 121: { ! 122: if (GET_CODE (operands[1]) == CONST_INT) ! 123: { ! 124: short i = INTVAL (operands[1]); ! 125: if (i <= 7 && i >= -8) ! 126: { ! 127: cc_status.flags |= CC_REVERSED; ! 128: if (INTVAL (operands[1]) > 7) ! 129: operands[1] = gen_rtx(CONST_INT, VOIDmode, i); ! 130: return \"cmpqw %1,%0\"; ! 131: } ! 132: } ! 133: cc_status.flags &= ~CC_REVERSED; ! 134: if (GET_CODE (operands[0]) == CONST_INT) ! 135: { ! 136: short i = INTVAL (operands[0]); ! 137: if (i <= 7 && i >= -8) ! 138: { ! 139: if (INTVAL (operands[0]) > 7) ! 140: operands[0] = gen_rtx(CONST_INT, VOIDmode, i); ! 141: return \"cmpqw %0,%1\"; ! 142: } ! 143: } ! 144: return \"cmpw %0,%1\"; ! 145: }") ! 146: ! 147: (define_insn "cmpqi" ! 148: [(set (cc0) ! 149: (compare (match_operand:QI 0 "general_operand" "g") ! 150: (match_operand:QI 1 "general_operand" "g")))] ! 151: "" ! 152: "* ! 153: { ! 154: if (GET_CODE (operands[1]) == CONST_INT) ! 155: { ! 156: char i = INTVAL (operands[1]); ! 157: if (i <= 7 && i >= -8) ! 158: { ! 159: cc_status.flags |= CC_REVERSED; ! 160: if (INTVAL (operands[1]) > 7) ! 161: operands[1] = gen_rtx(CONST_INT, VOIDmode, i); ! 162: return \"cmpqb %1,%0\"; ! 163: } ! 164: } ! 165: cc_status.flags &= ~CC_REVERSED; ! 166: if (GET_CODE (operands[0]) == CONST_INT) ! 167: { ! 168: char i = INTVAL (operands[0]); ! 169: if (i <= 7 && i >= -8) ! 170: { ! 171: if (INTVAL (operands[0]) > 7) ! 172: operands[0] = gen_rtx(CONST_INT, VOIDmode, i); ! 173: return \"cmpqb %0,%1\"; ! 174: } ! 175: } ! 176: return \"cmpb %0,%1\"; ! 177: }") ! 178: ! 179: (define_insn "cmpdf" ! 180: [(set (cc0) ! 181: (compare (match_operand:DF 0 "general_operand" "fmF") ! 182: (match_operand:DF 1 "general_operand" "fmF")))] ! 183: "TARGET_32081" ! 184: "cmpl %0,%1") ! 185: ! 186: (define_insn "cmpsf" ! 187: [(set (cc0) ! 188: (compare (match_operand:SF 0 "general_operand" "fmF") ! 189: (match_operand:SF 1 "general_operand" "fmF")))] ! 190: "TARGET_32081" ! 191: "cmpf %0,%1") ! 192: ! 193: (define_insn "movdf" ! 194: [(set (match_operand:DF 0 "general_operand" "=&fg<") ! 195: (match_operand:DF 1 "general_operand" "fFg"))] ! 196: "" ! 197: "* ! 198: { ! 199: if (FP_REG_P (operands[0])) ! 200: { ! 201: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE) ! 202: return \"movl %1,%0\"; ! 203: if (REG_P (operands[1])) ! 204: { ! 205: rtx xoperands[2]; ! 206: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); ! 207: output_asm_insn (\"movd %1,tos\", xoperands); ! 208: output_asm_insn (\"movd %1,tos\", operands); ! 209: return \"movl tos,%0\"; ! 210: } ! 211: return \"movl %1,%0\"; ! 212: } ! 213: else if (FP_REG_P (operands[1])) ! 214: { ! 215: if (REG_P (operands[0])) ! 216: { ! 217: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands); ! 218: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); ! 219: return \"movd tos,%0\"; ! 220: } ! 221: else ! 222: return \"movl %1,%0\"; ! 223: } ! 224: return output_move_double (operands); ! 225: }") ! 226: ! 227: (define_insn "movsf" ! 228: [(set (match_operand:SF 0 "general_operand" "=fg<") ! 229: (match_operand:SF 1 "general_operand" "fFg"))] ! 230: "" ! 231: "* ! 232: { ! 233: if (FP_REG_P (operands[0])) ! 234: { ! 235: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) ! 236: return \"movd %1,tos\;movf tos,%0\"; ! 237: else ! 238: return \"movf %1,%0\"; ! 239: } ! 240: else if (FP_REG_P (operands[1])) ! 241: { ! 242: if (REG_P (operands[0])) ! 243: return \"movf %1,tos\;movd tos,%0\"; ! 244: return \"movf %1,%0\"; ! 245: } ! 246: else if (GET_CODE (operands[1]) == CONST_DOUBLE) ! 247: { ! 248: /* Is there a better machine-independent way to to this? */ ! 249: operands[1] = gen_rtx (CONST_INT, VOIDmode, ! 250: CONST_DOUBLE_LOW (operands[1])); ! 251: return \"movd %1,%0\"; ! 252: } ! 253: else return \"movd %1,%0\"; ! 254: }") ! 255: ! 256: (define_insn "" ! 257: [(set (match_operand:TI 0 "memory_operand" "=m") ! 258: (match_operand:TI 1 "memory_operand" "m"))] ! 259: "" ! 260: "movmd %1,%0,4") ! 261: ! 262: (define_insn "movdi" ! 263: [(set (match_operand:DI 0 "general_operand" "=&g<") ! 264: (match_operand:DI 1 "general_operand" "gF"))] ! 265: "" ! 266: "* return output_move_double (operands); ") ! 267: ! 268: ;; This special case must precede movsi. ! 269: (define_insn "" ! 270: [(set (reg:SI 17) ! 271: (match_operand:SI 0 "general_operand" "rmn"))] ! 272: "" ! 273: "lprd sp,%0") ! 274: ! 275: (define_insn "movsi" ! 276: [(set (match_operand:SI 0 "general_operand" "=g<") ! 277: (match_operand:SI 1 "general_operand" "gx"))] ! 278: "" ! 279: "* ! 280: { if (GET_CODE (operands[1]) == CONST_INT) ! 281: { ! 282: int i = INTVAL (operands[1]); ! 283: if (i <= 7 && i >= -8) ! 284: return \"movqd %1,%0\"; ! 285: if (i < 0x4000 && i >= -0x4000) ! 286: #ifdef GNX_V3 ! 287: return \"addr %c1,%0\"; ! 288: #else ! 289: return \"addr @%c1,%0\"; ! 290: #endif ! 291: return \"movd %1,%0\"; ! 292: } ! 293: else if (GET_CODE (operands[1]) == REG) ! 294: { ! 295: if (REGNO (operands[1]) < 16) ! 296: return \"movd %1,%0\"; ! 297: else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM) ! 298: { ! 299: if (GET_CODE(operands[0]) == REG) ! 300: return \"sprd fp,%0\"; ! 301: else ! 302: return \"addr 0(fp),%0\" ; ! 303: } ! 304: else if (REGNO (operands[1]) == STACK_POINTER_REGNUM) ! 305: { ! 306: if (GET_CODE(operands[0]) == REG) ! 307: return \"sprd sp,%0\"; ! 308: else ! 309: return \"addr 0(sp),%0\" ; ! 310: } ! 311: else abort (0); ! 312: } ! 313: else if (GET_CODE (operands[1]) == MEM) ! 314: return \"movd %1,%0\"; ! 315: /* Check if this effective address can be ! 316: calculated faster by pulling it apart. */ ! 317: if (REG_P (operands[0]) ! 318: && GET_CODE (operands[1]) == MULT ! 319: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT ! 320: && (INTVAL (XEXP (operands[1], 1)) == 2 ! 321: || INTVAL (XEXP (operands[1], 1)) == 4)) ! 322: { ! 323: rtx xoperands[3]; ! 324: xoperands[0] = operands[0]; ! 325: xoperands[1] = XEXP (operands[1], 0); ! 326: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1); ! 327: return output_shift_insn (xoperands); ! 328: } ! 329: return \"addr %a1,%0\"; ! 330: }") ! 331: ! 332: (define_insn "movhi" ! 333: [(set (match_operand:HI 0 "general_operand" "=g<") ! 334: (match_operand:HI 1 "general_operand" "g"))] ! 335: "" ! 336: "* ! 337: { ! 338: if (GET_CODE (operands[1]) == CONST_INT) ! 339: { ! 340: short i = INTVAL (operands[1]); ! 341: if (i <= 7 && i >= -8) ! 342: { ! 343: if (INTVAL (operands[1]) > 7) ! 344: operands[1] = ! 345: gen_rtx (CONST_INT, VOIDmode, i); ! 346: return \"movqw %1,%0\"; ! 347: } ! 348: } ! 349: return \"movw %1,%0\"; ! 350: }") ! 351: ! 352: (define_insn "movstricthi" ! 353: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r")) ! 354: (match_operand:HI 1 "general_operand" "g"))] ! 355: "" ! 356: "* ! 357: { ! 358: if (GET_CODE (operands[1]) == CONST_INT ! 359: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8) ! 360: return \"movqw %1,%0\"; ! 361: return \"movw %1,%0\"; ! 362: }") ! 363: ! 364: (define_insn "movqi" ! 365: [(set (match_operand:QI 0 "general_operand" "=g<") ! 366: (match_operand:QI 1 "general_operand" "g"))] ! 367: "" ! 368: "* ! 369: { if (GET_CODE (operands[1]) == CONST_INT) ! 370: { ! 371: char char_val = (char)INTVAL (operands[1]); ! 372: if (char_val <= 7 && char_val >= -8) ! 373: { ! 374: if (INTVAL (operands[1]) > 7) ! 375: operands[1] = ! 376: gen_rtx (CONST_INT, VOIDmode, char_val); ! 377: return \"movqb %1,%0\"; ! 378: } ! 379: } ! 380: return \"movb %1,%0\"; ! 381: }") ! 382: ! 383: (define_insn "movstrictqi" ! 384: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r")) ! 385: (match_operand:QI 1 "general_operand" "g"))] ! 386: "" ! 387: "* ! 388: { ! 389: if (GET_CODE (operands[1]) == CONST_INT ! 390: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9) ! 391: return \"movqb %1,%0\"; ! 392: return \"movb %1,%0\"; ! 393: }") ! 394: ! 395: ;; The definition of this insn does not really explain what it does, ! 396: ;; but it should suffice ! 397: ;; that anything generated as this insn will be recognized as one ! 398: ;; and that it won't successfully combine with anything. ! 399: (define_insn "movstrsi" ! 400: [(set (match_operand:BLK 0 "general_operand" "=g") ! 401: (match_operand:BLK 1 "general_operand" "g")) ! 402: (use (match_operand:SI 2 "general_operand" "rmn")) ! 403: (clobber (reg:SI 0)) ! 404: (clobber (reg:SI 1)) ! 405: (clobber (reg:SI 2))] ! 406: "" ! 407: "* ! 408: { ! 409: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) ! 410: abort (); ! 411: operands[0] = XEXP (operands[0], 0); ! 412: operands[1] = XEXP (operands[1], 0); ! 413: if (GET_CODE (operands[0]) == MEM) ! 414: if (GET_CODE (operands[1]) == MEM) ! 415: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands); ! 416: else ! 417: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands); ! 418: else if (GET_CODE (operands[1]) == MEM) ! 419: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands); ! 420: else ! 421: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands); ! 422: ! 423: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0) ! 424: { ! 425: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2); ! 426: if ((unsigned) INTVAL (operands[2]) <= 7) ! 427: return \"movqd %2,r0\;movsd\"; ! 428: else ! 429: return \"movd %2,r0\;movsd\"; ! 430: } ! 431: else ! 432: { ! 433: return \"movd %2,r0\;movsb\"; ! 434: } ! 435: }") ! 436: ! 437: ;; Extension and truncation insns. ! 438: ;; Those for integer source operand ! 439: ;; are ordered widest source type first. ! 440: ! 441: (define_insn "truncsiqi2" ! 442: [(set (match_operand:QI 0 "general_operand" "=g<") ! 443: (truncate:QI (match_operand:SI 1 "general_operand" "rmn")))] ! 444: "" ! 445: "movb %1,%0") ! 446: ! 447: (define_insn "truncsihi2" ! 448: [(set (match_operand:HI 0 "general_operand" "=g<") ! 449: (truncate:HI (match_operand:SI 1 "general_operand" "rmn")))] ! 450: "" ! 451: "movw %1,%0") ! 452: ! 453: (define_insn "trunchiqi2" ! 454: [(set (match_operand:QI 0 "general_operand" "=g<") ! 455: (truncate:QI (match_operand:HI 1 "general_operand" "g")))] ! 456: "" ! 457: "movb %1,%0") ! 458: ! 459: (define_insn "extendhisi2" ! 460: [(set (match_operand:SI 0 "general_operand" "=g<") ! 461: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))] ! 462: "" ! 463: "movxwd %1,%0") ! 464: ! 465: (define_insn "extendqihi2" ! 466: [(set (match_operand:HI 0 "general_operand" "=g<") ! 467: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))] ! 468: "" ! 469: "movxbw %1,%0") ! 470: ! 471: (define_insn "extendqisi2" ! 472: [(set (match_operand:SI 0 "general_operand" "=g<") ! 473: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))] ! 474: "" ! 475: "movxbd %1,%0") ! 476: ! 477: (define_insn "extendsfdf2" ! 478: [(set (match_operand:DF 0 "general_operand" "=fm<") ! 479: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))] ! 480: "TARGET_32081" ! 481: "movfl %1,%0") ! 482: ! 483: (define_insn "truncdfsf2" ! 484: [(set (match_operand:SF 0 "general_operand" "=fm<") ! 485: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))] ! 486: "TARGET_32081" ! 487: "movlf %1,%0") ! 488: ! 489: (define_insn "zero_extendhisi2" ! 490: [(set (match_operand:SI 0 "general_operand" "=g<") ! 491: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))] ! 492: "" ! 493: "movzwd %1,%0") ! 494: ! 495: (define_insn "zero_extendqihi2" ! 496: [(set (match_operand:HI 0 "general_operand" "=g<") ! 497: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))] ! 498: "" ! 499: "movzbw %1,%0") ! 500: ! 501: (define_insn "zero_extendqisi2" ! 502: [(set (match_operand:SI 0 "general_operand" "=g<") ! 503: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))] ! 504: "" ! 505: "movzbd %1,%0") ! 506: ! 507: ;; Fix-to-float conversion insns. ! 508: ;; Note that the ones that start with SImode come first. ! 509: ;; That is so that an operand that is a CONST_INT ! 510: ;; (and therefore lacks a specific machine mode). ! 511: ;; will be recognized as SImode (which is always valid) ! 512: ;; rather than as QImode or HImode. ! 513: ! 514: ;; Rumor has it that the National part does not correctly convert ! 515: ;; constant ints to floats. This conversion is therefore disabled. ! 516: ;; A register must be used to perform the conversion. ! 517: ! 518: (define_insn "floatsisf2" ! 519: [(set (match_operand:SF 0 "general_operand" "=fm<") ! 520: (float:SF (match_operand:SI 1 "general_operand" "rm")))] ! 521: "TARGET_32081" ! 522: "movdf %1,%0") ! 523: ! 524: (define_insn "floatsidf2" ! 525: [(set (match_operand:DF 0 "general_operand" "=fm<") ! 526: (float:DF (match_operand:SI 1 "general_operand" "rm")))] ! 527: "TARGET_32081" ! 528: "movdl %1,%0") ! 529: ! 530: (define_insn "floathisf2" ! 531: [(set (match_operand:SF 0 "general_operand" "=fm<") ! 532: (float:SF (match_operand:HI 1 "general_operand" "rm")))] ! 533: "TARGET_32081" ! 534: "movwf %1,%0") ! 535: ! 536: (define_insn "floathidf2" ! 537: [(set (match_operand:DF 0 "general_operand" "=fm<") ! 538: (float:DF (match_operand:HI 1 "general_operand" "rm")))] ! 539: "TARGET_32081" ! 540: "movwl %1,%0") ! 541: ! 542: (define_insn "floatqisf2" ! 543: [(set (match_operand:SF 0 "general_operand" "=fm<") ! 544: (float:SF (match_operand:QI 1 "general_operand" "rm")))] ! 545: "TARGET_32081" ! 546: "movbf %1,%0") ! 547: ! 548: ; Some assemblers warn that this insn doesn't work. ! 549: ; Maybe they know something we don't. ! 550: ;(define_insn "floatqidf2" ! 551: ; [(set (match_operand:DF 0 "general_operand" "=fm<") ! 552: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))] ! 553: ; "TARGET_32081" ! 554: ; "movbl %1,%0") ! 555: ! 556: ;; Float-to-fix conversion insns. ! 557: ;; The sequent compiler always generates "trunc" insns. ! 558: ! 559: (define_insn "fixsfqi2" ! 560: [(set (match_operand:QI 0 "general_operand" "=g<") ! 561: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] ! 562: "TARGET_32081" ! 563: "truncfb %1,%0") ! 564: ! 565: (define_insn "fixsfhi2" ! 566: [(set (match_operand:HI 0 "general_operand" "=g<") ! 567: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] ! 568: "TARGET_32081" ! 569: "truncfw %1,%0") ! 570: ! 571: (define_insn "fixsfsi2" ! 572: [(set (match_operand:SI 0 "general_operand" "=g<") ! 573: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] ! 574: "TARGET_32081" ! 575: "truncfd %1,%0") ! 576: ! 577: (define_insn "fixdfqi2" ! 578: [(set (match_operand:QI 0 "general_operand" "=g<") ! 579: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] ! 580: "TARGET_32081" ! 581: "trunclb %1,%0") ! 582: ! 583: (define_insn "fixdfhi2" ! 584: [(set (match_operand:HI 0 "general_operand" "=g<") ! 585: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] ! 586: "TARGET_32081" ! 587: "trunclw %1,%0") ! 588: ! 589: (define_insn "fixdfsi2" ! 590: [(set (match_operand:SI 0 "general_operand" "=g<") ! 591: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] ! 592: "TARGET_32081" ! 593: "truncld %1,%0") ! 594: ! 595: ;; Unsigned ! 596: ! 597: (define_insn "fixunssfqi2" ! 598: [(set (match_operand:QI 0 "general_operand" "=g<") ! 599: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] ! 600: "TARGET_32081" ! 601: "truncfb %1,%0") ! 602: ! 603: (define_insn "fixunssfhi2" ! 604: [(set (match_operand:HI 0 "general_operand" "=g<") ! 605: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] ! 606: "TARGET_32081" ! 607: "truncfw %1,%0") ! 608: ! 609: (define_insn "fixunssfsi2" ! 610: [(set (match_operand:SI 0 "general_operand" "=g<") ! 611: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] ! 612: "TARGET_32081" ! 613: "truncfd %1,%0") ! 614: ! 615: (define_insn "fixunsdfqi2" ! 616: [(set (match_operand:QI 0 "general_operand" "=g<") ! 617: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] ! 618: "TARGET_32081" ! 619: "trunclb %1,%0") ! 620: ! 621: (define_insn "fixunsdfhi2" ! 622: [(set (match_operand:HI 0 "general_operand" "=g<") ! 623: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] ! 624: "TARGET_32081" ! 625: "trunclw %1,%0") ! 626: ! 627: (define_insn "fixunsdfsi2" ! 628: [(set (match_operand:SI 0 "general_operand" "=g<") ! 629: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] ! 630: "TARGET_32081" ! 631: "truncld %1,%0") ! 632: ! 633: ;;; These are not yet used by GCC ! 634: (define_insn "fix_truncsfqi2" ! 635: [(set (match_operand:QI 0 "general_operand" "=g<") ! 636: (fix:QI (match_operand:SF 1 "general_operand" "fm")))] ! 637: "TARGET_32081" ! 638: "truncfb %1,%0") ! 639: ! 640: (define_insn "fix_truncsfhi2" ! 641: [(set (match_operand:HI 0 "general_operand" "=g<") ! 642: (fix:HI (match_operand:SF 1 "general_operand" "fm")))] ! 643: "TARGET_32081" ! 644: "truncfw %1,%0") ! 645: ! 646: (define_insn "fix_truncsfsi2" ! 647: [(set (match_operand:SI 0 "general_operand" "=g<") ! 648: (fix:SI (match_operand:SF 1 "general_operand" "fm")))] ! 649: "TARGET_32081" ! 650: "truncfd %1,%0") ! 651: ! 652: (define_insn "fix_truncdfqi2" ! 653: [(set (match_operand:QI 0 "general_operand" "=g<") ! 654: (fix:QI (match_operand:DF 1 "general_operand" "fm")))] ! 655: "TARGET_32081" ! 656: "trunclb %1,%0") ! 657: ! 658: (define_insn "fix_truncdfhi2" ! 659: [(set (match_operand:HI 0 "general_operand" "=g<") ! 660: (fix:HI (match_operand:DF 1 "general_operand" "fm")))] ! 661: "TARGET_32081" ! 662: "trunclw %1,%0") ! 663: ! 664: (define_insn "fix_truncdfsi2" ! 665: [(set (match_operand:SI 0 "general_operand" "=g<") ! 666: (fix:SI (match_operand:DF 1 "general_operand" "fm")))] ! 667: "TARGET_32081" ! 668: "truncld %1,%0") ! 669: ! 670: ;;- All kinds of add instructions. ! 671: ! 672: (define_insn "adddf3" ! 673: [(set (match_operand:DF 0 "general_operand" "=fm") ! 674: (plus:DF (match_operand:DF 1 "general_operand" "%0") ! 675: (match_operand:DF 2 "general_operand" "fmF")))] ! 676: "TARGET_32081" ! 677: "addl %2,%0") ! 678: ! 679: ! 680: (define_insn "addsf3" ! 681: [(set (match_operand:SF 0 "general_operand" "=fm") ! 682: (plus:SF (match_operand:SF 1 "general_operand" "%0") ! 683: (match_operand:SF 2 "general_operand" "fmF")))] ! 684: "TARGET_32081" ! 685: "addf %2,%0") ! 686: ! 687: (define_insn "" ! 688: [(set (reg:SI 17) ! 689: (plus:SI (reg:SI 17) ! 690: (match_operand:SI 0 "immediate_operand" "i")))] ! 691: "GET_CODE (operands[0]) == CONST_INT" ! 692: "* ! 693: { ! 694: #if defined(ns32532) ! 695: if (INTVAL(operands[0]) == 8) ! 696: return \"cmpd tos,tos # adjsp -8\"; ! 697: #endif ! 698: #if defined(ns32532) || defined(ns32332) ! 699: if (INTVAL(operands[0]) == 4) ! 700: return \"cmpqd %$0,tos # adjsp -4\"; ! 701: #endif ! 702: if (INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64) ! 703: return \"adjspb %$%n0\"; ! 704: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192) ! 705: return \"adjspw %$%n0\"; ! 706: return \"adjspd %$%n0\"; ! 707: }") ! 708: ! 709: (define_insn "" ! 710: [(set (match_operand:SI 0 "general_operand" "=g<") ! 711: (plus:SI (reg:SI 16) ! 712: (match_operand:SI 1 "immediate_operand" "i")))] ! 713: "GET_CODE (operands[1]) == CONST_INT" ! 714: "addr %c1(fp),%0") ! 715: ! 716: (define_insn "" ! 717: [(set (match_operand:SI 0 "general_operand" "=g<") ! 718: (plus:SI (reg:SI 17) ! 719: (match_operand:SI 1 "immediate_operand" "i")))] ! 720: "GET_CODE (operands[1]) == CONST_INT" ! 721: "addr %c1(sp),%0") ! 722: ! 723: (define_insn "addsi3" ! 724: [(set (match_operand:SI 0 "general_operand" "=g,=g<") ! 725: (plus:SI (match_operand:SI 1 "general_operand" "%0,%r") ! 726: (match_operand:SI 2 "general_operand" "rmn,n")))] ! 727: "" ! 728: "* ! 729: { ! 730: if (which_alternative == 1) ! 731: return \"addr %c2(%1),%0\"; ! 732: if (GET_CODE (operands[2]) == CONST_INT) ! 733: { ! 734: int i = INTVAL (operands[2]); ! 735: ! 736: if (i <= 7 && i >= -8) ! 737: return \"addqd %2,%0\"; ! 738: else if (GET_CODE (operands[0]) == REG ! 739: && i < 0x4000 && i >= -0x4000) ! 740: return \"addr %c2(%0),%0\"; ! 741: } ! 742: return \"addd %2,%0\"; ! 743: }") ! 744: ! 745: (define_insn "addhi3" ! 746: [(set (match_operand:HI 0 "general_operand" "=g") ! 747: (plus:HI (match_operand:HI 1 "general_operand" "%0") ! 748: (match_operand:HI 2 "general_operand" "g")))] ! 749: "" ! 750: "* ! 751: { if (GET_CODE (operands[2]) == CONST_INT) ! 752: { ! 753: int i = INTVAL (operands[2]); ! 754: if (i <= 7 && i >= -8) ! 755: return \"addqw %2,%0\"; ! 756: } ! 757: return \"addw %2,%0\"; ! 758: }") ! 759: ! 760: (define_insn "" ! 761: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r")) ! 762: (plus:HI (match_operand:HI 1 "general_operand" "0") ! 763: (match_operand:HI 2 "general_operand" "g")))] ! 764: "" ! 765: "* ! 766: { ! 767: if (GET_CODE (operands[1]) == CONST_INT ! 768: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8) ! 769: return \"addqw %1,%0\"; ! 770: return \"addw %1,%0\"; ! 771: }") ! 772: ! 773: (define_insn "addqi3" ! 774: [(set (match_operand:QI 0 "general_operand" "=g") ! 775: (plus:QI (match_operand:QI 1 "general_operand" "%0") ! 776: (match_operand:QI 2 "general_operand" "g")))] ! 777: "" ! 778: "* ! 779: { if (GET_CODE (operands[2]) == CONST_INT) ! 780: { ! 781: int i = INTVAL (operands[2]); ! 782: if (i <= 7 && i >= -8) ! 783: return \"addqb %2,%0\"; ! 784: } ! 785: return \"addb %2,%0\"; ! 786: }") ! 787: ! 788: (define_insn "" ! 789: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r")) ! 790: (plus:QI (match_operand:QI 1 "general_operand" "0") ! 791: (match_operand:QI 2 "general_operand" "g")))] ! 792: "" ! 793: "* ! 794: { ! 795: if (GET_CODE (operands[1]) == CONST_INT ! 796: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8) ! 797: return \"addqb %1,%0\"; ! 798: return \"addb %1,%0\"; ! 799: }") ! 800: ! 801: ;;- All kinds of subtract instructions. ! 802: ! 803: (define_insn "subdf3" ! 804: [(set (match_operand:DF 0 "general_operand" "=fm") ! 805: (minus:DF (match_operand:DF 1 "general_operand" "0") ! 806: (match_operand:DF 2 "general_operand" "fmF")))] ! 807: "TARGET_32081" ! 808: "subl %2,%0") ! 809: ! 810: (define_insn "subsf3" ! 811: [(set (match_operand:SF 0 "general_operand" "=fm") ! 812: (minus:SF (match_operand:SF 1 "general_operand" "0") ! 813: (match_operand:SF 2 "general_operand" "fmF")))] ! 814: "TARGET_32081" ! 815: "subf %2,%0") ! 816: ! 817: (define_insn "" ! 818: [(set (reg:SI 17) ! 819: (minus:SI (reg:SI 17) ! 820: (match_operand:SI 0 "immediate_operand" "i")))] ! 821: "GET_CODE (operands[0]) == CONST_INT" ! 822: "* ! 823: { ! 824: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64 ! 825: && INTVAL(operands[0]) > -64) ! 826: return \"adjspb %0\"; ! 827: return \"adjspd %0\"; ! 828: }") ! 829: ! 830: (define_insn "subsi3" ! 831: [(set (match_operand:SI 0 "general_operand" "=g") ! 832: (minus:SI (match_operand:SI 1 "general_operand" "0") ! 833: (match_operand:SI 2 "general_operand" "rmn")))] ! 834: "" ! 835: "* ! 836: { if (GET_CODE (operands[2]) == CONST_INT) ! 837: { ! 838: int i = INTVAL (operands[2]); ! 839: ! 840: if (i <= 8 && i >= -7) ! 841: return \"addqd %$%n2,%0\"; ! 842: } ! 843: return \"subd %2,%0\"; ! 844: }") ! 845: ! 846: (define_insn "subhi3" ! 847: [(set (match_operand:HI 0 "general_operand" "=g") ! 848: (minus:HI (match_operand:HI 1 "general_operand" "0") ! 849: (match_operand:HI 2 "general_operand" "g")))] ! 850: "" ! 851: "* ! 852: { if (GET_CODE (operands[2]) == CONST_INT) ! 853: { ! 854: int i = INTVAL (operands[2]); ! 855: ! 856: if (i <= 8 && i >= -7) ! 857: return \"addqw %$%n2,%0\"; ! 858: } ! 859: return \"subw %2,%0\"; ! 860: }") ! 861: ! 862: (define_insn "" ! 863: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r")) ! 864: (minus:HI (match_operand:HI 1 "general_operand" "0") ! 865: (match_operand:HI 2 "general_operand" "g")))] ! 866: "" ! 867: "* ! 868: { ! 869: if (GET_CODE (operands[1]) == CONST_INT ! 870: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9) ! 871: return \"addqw %$%n1,%0\"; ! 872: return \"subw %1,%0\"; ! 873: }") ! 874: ! 875: (define_insn "subqi3" ! 876: [(set (match_operand:QI 0 "general_operand" "=g") ! 877: (minus:QI (match_operand:QI 1 "general_operand" "0") ! 878: (match_operand:QI 2 "general_operand" "g")))] ! 879: "" ! 880: "* ! 881: { if (GET_CODE (operands[2]) == CONST_INT) ! 882: { ! 883: int i = INTVAL (operands[2]); ! 884: ! 885: if (i <= 8 && i >= -7) ! 886: return \"addqb %$%n2,%0\"; ! 887: } ! 888: return \"subb %2,%0\"; ! 889: }") ! 890: ! 891: (define_insn "" ! 892: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r")) ! 893: (minus:QI (match_operand:QI 1 "general_operand" "0") ! 894: (match_operand:QI 2 "general_operand" "g")))] ! 895: "" ! 896: "* ! 897: { ! 898: if (GET_CODE (operands[1]) == CONST_INT ! 899: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9) ! 900: return \"addqb %$%n1,%0\"; ! 901: return \"subb %1,%0\"; ! 902: }") ! 903: ! 904: ;;- Multiply instructions. ! 905: ! 906: (define_insn "muldf3" ! 907: [(set (match_operand:DF 0 "general_operand" "=fm") ! 908: (mult:DF (match_operand:DF 1 "general_operand" "%0") ! 909: (match_operand:DF 2 "general_operand" "fmF")))] ! 910: "TARGET_32081" ! 911: "mull %2,%0") ! 912: ! 913: (define_insn "mulsf3" ! 914: [(set (match_operand:SF 0 "general_operand" "=fm") ! 915: (mult:SF (match_operand:SF 1 "general_operand" "%0") ! 916: (match_operand:SF 2 "general_operand" "fmF")))] ! 917: "TARGET_32081" ! 918: "mulf %2,%0") ! 919: ! 920: (define_insn "mulsi3" ! 921: [(set (match_operand:SI 0 "general_operand" "=g") ! 922: (mult:SI (match_operand:SI 1 "general_operand" "%0") ! 923: (match_operand:SI 2 "general_operand" "rmn")))] ! 924: "" ! 925: "muld %2,%0") ! 926: ! 927: (define_insn "mulhi3" ! 928: [(set (match_operand:HI 0 "general_operand" "=g") ! 929: (mult:HI (match_operand:HI 1 "general_operand" "%0") ! 930: (match_operand:HI 2 "general_operand" "g")))] ! 931: "" ! 932: "mulw %2,%0") ! 933: ! 934: (define_insn "mulqi3" ! 935: [(set (match_operand:QI 0 "general_operand" "=g") ! 936: (mult:QI (match_operand:QI 1 "general_operand" "%0") ! 937: (match_operand:QI 2 "general_operand" "g")))] ! 938: "" ! 939: "mulb %2,%0") ! 940: ! 941: (define_insn "umulsi3" ! 942: [(set (match_operand:SI 0 "general_operand" "=g") ! 943: (umult:SI (match_operand:SI 1 "general_operand" "%0") ! 944: (match_operand:SI 2 "general_operand" "rmn")))] ! 945: "" ! 946: "muld %2,%0") ! 947: ! 948: (define_insn "umulhi3" ! 949: [(set (match_operand:HI 0 "general_operand" "=g") ! 950: (umult:HI (match_operand:HI 1 "general_operand" "%0") ! 951: (match_operand:HI 2 "general_operand" "g")))] ! 952: "" ! 953: "mulw %2,%0") ! 954: ! 955: (define_insn "umulqi3" ! 956: [(set (match_operand:QI 0 "general_operand" "=g") ! 957: (umult:QI (match_operand:QI 1 "general_operand" "%0") ! 958: (match_operand:QI 2 "general_operand" "g")))] ! 959: "" ! 960: "mulb %2,%0") ! 961: ! 962: (define_insn "umulsidi3" ! 963: [(set (match_operand:DI 0 "general_operand" "=g") ! 964: (umult:DI (match_operand:SI 1 "general_operand" "0") ! 965: (match_operand:SI 2 "general_operand" "rmn")))] ! 966: "" ! 967: "meid %2,%0") ! 968: ! 969: ;;- Divide instructions. ! 970: ! 971: (define_insn "divdf3" ! 972: [(set (match_operand:DF 0 "general_operand" "=fm") ! 973: (div:DF (match_operand:DF 1 "general_operand" "0") ! 974: (match_operand:DF 2 "general_operand" "fmF")))] ! 975: "TARGET_32081" ! 976: "divl %2,%0") ! 977: ! 978: (define_insn "divsf3" ! 979: [(set (match_operand:SF 0 "general_operand" "=fm") ! 980: (div:SF (match_operand:SF 1 "general_operand" "0") ! 981: (match_operand:SF 2 "general_operand" "fmF")))] ! 982: "TARGET_32081" ! 983: "divf %2,%0") ! 984: ! 985: (define_insn "divsi3" ! 986: [(set (match_operand:SI 0 "general_operand" "=g") ! 987: (div:SI (match_operand:SI 1 "general_operand" "0") ! 988: (match_operand:SI 2 "general_operand" "rmn")))] ! 989: "" ! 990: "quod %2,%0") ! 991: ! 992: (define_insn "divhi3" ! 993: [(set (match_operand:HI 0 "general_operand" "=g") ! 994: (div:HI (match_operand:HI 1 "general_operand" "0") ! 995: (match_operand:HI 2 "general_operand" "g")))] ! 996: "" ! 997: "quow %2,%0") ! 998: ! 999: (define_insn "divqi3" ! 1000: [(set (match_operand:QI 0 "general_operand" "=g") ! 1001: (div:QI (match_operand:QI 1 "general_operand" "0") ! 1002: (match_operand:QI 2 "general_operand" "g")))] ! 1003: "" ! 1004: "quob %2,%0") ! 1005: ! 1006: (define_insn "udivsi3" ! 1007: [(set (match_operand:SI 0 "register_operand" "=r") ! 1008: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) ! 1009: (match_operand:SI 2 "general_operand" "rmn")))] ! 1010: "" ! 1011: "* ! 1012: { ! 1013: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); ! 1014: return \"deid %2,%0\;movd %1,%0\"; ! 1015: }") ! 1016: ! 1017: (define_insn "udivhi3" ! 1018: [(set (match_operand:HI 0 "register_operand" "=r") ! 1019: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) ! 1020: (match_operand:HI 2 "general_operand" "g")))] ! 1021: "" ! 1022: "* ! 1023: { ! 1024: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1); ! 1025: return \"deiw %2,%0\;movw %1,%0\"; ! 1026: }") ! 1027: ! 1028: (define_insn "udivqi3" ! 1029: [(set (match_operand:QI 0 "register_operand" "=r") ! 1030: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) ! 1031: (match_operand:QI 2 "general_operand" "g")))] ! 1032: "" ! 1033: "* ! 1034: { ! 1035: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1); ! 1036: return \"deib %2,%0\;movb %1,%0\"; ! 1037: }") ! 1038: ! 1039: ;; Remainder instructions. ! 1040: ! 1041: (define_insn "modsi3" ! 1042: [(set (match_operand:SI 0 "general_operand" "=g") ! 1043: (mod:SI (match_operand:SI 1 "general_operand" "0") ! 1044: (match_operand:SI 2 "general_operand" "rmn")))] ! 1045: "" ! 1046: "remd %2,%0") ! 1047: ! 1048: (define_insn "modhi3" ! 1049: [(set (match_operand:HI 0 "general_operand" "=g") ! 1050: (mod:HI (match_operand:HI 1 "general_operand" "0") ! 1051: (match_operand:HI 2 "general_operand" "g")))] ! 1052: "" ! 1053: "remw %2,%0") ! 1054: ! 1055: (define_insn "modqi3" ! 1056: [(set (match_operand:QI 0 "general_operand" "=g") ! 1057: (mod:QI (match_operand:QI 1 "general_operand" "0") ! 1058: (match_operand:QI 2 "general_operand" "g")))] ! 1059: "" ! 1060: "remb %2,%0") ! 1061: ! 1062: (define_insn "umodsi3" ! 1063: [(set (match_operand:SI 0 "register_operand" "=r") ! 1064: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) ! 1065: (match_operand:SI 2 "general_operand" "rmn")))] ! 1066: "" ! 1067: "deid %2,%0") ! 1068: ! 1069: (define_insn "umodhi3" ! 1070: [(set (match_operand:HI 0 "register_operand" "=r") ! 1071: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) ! 1072: (match_operand:HI 2 "general_operand" "g")))] ! 1073: "" ! 1074: "deiw %2,%0") ! 1075: ! 1076: (define_insn "umodqi3" ! 1077: [(set (match_operand:QI 0 "register_operand" "=r") ! 1078: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) ! 1079: (match_operand:QI 2 "general_operand" "g")))] ! 1080: "" ! 1081: "deib %2,%0") ! 1082: ! 1083: ; This isn't be usable in its current form. ! 1084: ;(define_insn "udivmoddisi4" ! 1085: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1) ! 1086: ; (udiv:SI (match_operand:DI 1 "general_operand" "0") ! 1087: ; (match_operand:SI 2 "general_operand" "rmn"))) ! 1088: ; (set (subreg:SI (match_dup 0) 0) ! 1089: ; (umod:SI (match_dup 1) (match_dup 2)))] ! 1090: ; "" ! 1091: ; "deid %2,%0") ! 1092: ! 1093: ;;- Logical Instructions: AND ! 1094: ! 1095: (define_insn "andsi3" ! 1096: [(set (match_operand:SI 0 "general_operand" "=g") ! 1097: (and:SI (match_operand:SI 1 "general_operand" "%0") ! 1098: (match_operand:SI 2 "general_operand" "rmn")))] ! 1099: "" ! 1100: "* ! 1101: { ! 1102: if (GET_CODE (operands[2]) == CONST_INT) ! 1103: { ! 1104: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff) ! 1105: { ! 1106: if (INTVAL (operands[2]) == 0xffffff00) ! 1107: return \"movqb %$0,%0\"; ! 1108: else ! 1109: { ! 1110: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1111: INTVAL (operands[2]) & 0xff); ! 1112: return \"andb %2,%0\"; ! 1113: } ! 1114: } ! 1115: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff) ! 1116: { ! 1117: if (INTVAL (operands[2]) == 0xffff0000) ! 1118: return \"movqw %$0,%0\"; ! 1119: else ! 1120: { ! 1121: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1122: INTVAL (operands[2]) & 0xffff); ! 1123: return \"andw %2,%0\"; ! 1124: } ! 1125: } ! 1126: } ! 1127: return \"andd %2,%0\"; ! 1128: }") ! 1129: ! 1130: (define_insn "andhi3" ! 1131: [(set (match_operand:HI 0 "general_operand" "=g") ! 1132: (and:HI (match_operand:HI 1 "general_operand" "%0") ! 1133: (match_operand:HI 2 "general_operand" "g")))] ! 1134: "" ! 1135: "* ! 1136: { ! 1137: if (GET_CODE (operands[2]) == CONST_INT ! 1138: && (INTVAL (operands[2]) | 0xff) == 0xffffffff) ! 1139: { ! 1140: if (INTVAL (operands[2]) == 0xffffff00) ! 1141: return \"movqb %$0,%0\"; ! 1142: else ! 1143: { ! 1144: operands[2] = gen_rtx (CONST_INT, VOIDmode, ! 1145: INTVAL (operands[2]) & 0xff); ! 1146: return \"andb %2,%0\"; ! 1147: } ! 1148: } ! 1149: return \"andw %2,%0\"; ! 1150: }") ! 1151: ! 1152: (define_insn "andqi3" ! 1153: [(set (match_operand:QI 0 "general_operand" "=g") ! 1154: (and:QI (match_operand:QI 1 "general_operand" "%0") ! 1155: (match_operand:QI 2 "general_operand" "g")))] ! 1156: "" ! 1157: "andb %2,%0") ! 1158: ! 1159: (define_insn "andcbsi3" ! 1160: [(set (match_operand:SI 0 "general_operand" "=g") ! 1161: (and:SI (match_operand:SI 1 "general_operand" "0") ! 1162: (not:SI (match_operand:SI 2 "general_operand" "rmn"))))] ! 1163: "" ! 1164: "* ! 1165: { ! 1166: if (GET_CODE (operands[2]) == CONST_INT) ! 1167: { ! 1168: if ((INTVAL (operands[2]) & 0xffffff00) == 0) ! 1169: return \"bicb %2,%0\"; ! 1170: if ((INTVAL (operands[2]) & 0xffff0000) == 0) ! 1171: return \"bicw %2,%0\"; ! 1172: } ! 1173: return \"bicd %2,%0\"; ! 1174: }") ! 1175: ! 1176: (define_insn "" ! 1177: [(set (match_operand:SI 0 "general_operand" "=g") ! 1178: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn")) ! 1179: (match_operand:SI 2 "general_operand" "0")))] ! 1180: "" ! 1181: "* ! 1182: { ! 1183: if (GET_CODE (operands[1]) == CONST_INT) ! 1184: { ! 1185: if ((INTVAL (operands[1]) & 0xffffff00) == 0) ! 1186: return \"bicb %1,%0\"; ! 1187: if ((INTVAL (operands[1]) & 0xffff0000) == 0) ! 1188: return \"bicw %1,%0\"; ! 1189: } ! 1190: return \"bicd %1,%0\"; ! 1191: }") ! 1192: ! 1193: (define_insn "andcbhi3" ! 1194: [(set (match_operand:HI 0 "general_operand" "=g") ! 1195: (and:HI (match_operand:HI 1 "general_operand" "%0") ! 1196: (not:HI (match_operand:HI 2 "general_operand" "g"))))] ! 1197: "" ! 1198: "* ! 1199: { ! 1200: if (GET_CODE (operands[2]) == CONST_INT ! 1201: && (INTVAL (operands[2]) & 0xffffff00) == 0) ! 1202: return \"bicb %2,%0\"; ! 1203: return \"bicw %2,%0\"; ! 1204: }") ! 1205: ! 1206: (define_insn "" ! 1207: [(set (match_operand:HI 0 "general_operand" "=g") ! 1208: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g")) ! 1209: (match_operand:HI 2 "general_operand" "0")))] ! 1210: "" ! 1211: "* ! 1212: { ! 1213: if (GET_CODE (operands[1]) == CONST_INT ! 1214: && (INTVAL (operands[1]) & 0xffffff00) == 0) ! 1215: return \"bicb %1,%0\"; ! 1216: return \"bicw %1,%0\"; ! 1217: }") ! 1218: ! 1219: (define_insn "andcbqi3" ! 1220: [(set (match_operand:QI 0 "general_operand" "=g") ! 1221: (and:QI (match_operand:QI 1 "general_operand" "%0") ! 1222: (not:QI (match_operand:QI 2 "general_operand" "g"))))] ! 1223: "" ! 1224: "bicb %2,%0") ! 1225: ! 1226: (define_insn "" ! 1227: [(set (match_operand:QI 0 "general_operand" "=g") ! 1228: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g")) ! 1229: (match_operand:QI 2 "general_operand" "0")))] ! 1230: "" ! 1231: "bicb %1,%0") ! 1232: ! 1233: ;;- Bit set instructions. ! 1234: ! 1235: (define_insn "iorsi3" ! 1236: [(set (match_operand:SI 0 "general_operand" "=g") ! 1237: (ior:SI (match_operand:SI 1 "general_operand" "%0") ! 1238: (match_operand:SI 2 "general_operand" "rmn")))] ! 1239: "" ! 1240: "* ! 1241: { ! 1242: if (GET_CODE (operands[2]) == CONST_INT) { ! 1243: if ((INTVAL (operands[2]) & 0xffffff00) == 0) ! 1244: return \"orb %2,%0\"; ! 1245: if ((INTVAL (operands[2]) & 0xffff0000) == 0) ! 1246: return \"orw %2,%0\"; ! 1247: } ! 1248: return \"ord %2,%0\"; ! 1249: }") ! 1250: ! 1251: (define_insn "iorhi3" ! 1252: [(set (match_operand:HI 0 "general_operand" "=g") ! 1253: (ior:HI (match_operand:HI 1 "general_operand" "%0") ! 1254: (match_operand:HI 2 "general_operand" "g")))] ! 1255: "" ! 1256: "* ! 1257: { ! 1258: if (GET_CODE(operands[2]) == CONST_INT && ! 1259: (INTVAL(operands[2]) & 0xffffff00) == 0) ! 1260: return \"orb %2,%0\"; ! 1261: return \"orw %2,%0\"; ! 1262: }") ! 1263: ! 1264: (define_insn "iorqi3" ! 1265: [(set (match_operand:QI 0 "general_operand" "=g") ! 1266: (ior:QI (match_operand:QI 1 "general_operand" "%0") ! 1267: (match_operand:QI 2 "general_operand" "g")))] ! 1268: "" ! 1269: "orb %2,%0") ! 1270: ! 1271: ;;- xor instructions. ! 1272: ! 1273: (define_insn "xorsi3" ! 1274: [(set (match_operand:SI 0 "general_operand" "=g") ! 1275: (xor:SI (match_operand:SI 1 "general_operand" "%0") ! 1276: (match_operand:SI 2 "general_operand" "rmn")))] ! 1277: "" ! 1278: "* ! 1279: { ! 1280: if (GET_CODE (operands[2]) == CONST_INT) { ! 1281: if ((INTVAL (operands[2]) & 0xffffff00) == 0) ! 1282: return \"xorb %2,%0\"; ! 1283: if ((INTVAL (operands[2]) & 0xffff0000) == 0) ! 1284: return \"xorw %2,%0\"; ! 1285: } ! 1286: return \"xord %2,%0\"; ! 1287: }") ! 1288: ! 1289: (define_insn "xorhi3" ! 1290: [(set (match_operand:HI 0 "general_operand" "=g") ! 1291: (xor:HI (match_operand:HI 1 "general_operand" "%0") ! 1292: (match_operand:HI 2 "general_operand" "g")))] ! 1293: "" ! 1294: "* ! 1295: { ! 1296: if (GET_CODE(operands[2]) == CONST_INT && ! 1297: (INTVAL(operands[2]) & 0xffffff00) == 0) ! 1298: return \"xorb %2,%0\"; ! 1299: return \"xorw %2,%0\"; ! 1300: }") ! 1301: ! 1302: (define_insn "xorqi3" ! 1303: [(set (match_operand:QI 0 "general_operand" "=g") ! 1304: (xor:QI (match_operand:QI 1 "general_operand" "%0") ! 1305: (match_operand:QI 2 "general_operand" "g")))] ! 1306: "" ! 1307: "xorb %2,%0") ! 1308: ! 1309: (define_insn "negdf2" ! 1310: [(set (match_operand:DF 0 "general_operand" "=fm<") ! 1311: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))] ! 1312: "TARGET_32081" ! 1313: "negl %1,%0") ! 1314: ! 1315: (define_insn "negsf2" ! 1316: [(set (match_operand:SF 0 "general_operand" "=fm<") ! 1317: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))] ! 1318: "TARGET_32081" ! 1319: "negf %1,%0") ! 1320: ! 1321: (define_insn "negsi2" ! 1322: [(set (match_operand:SI 0 "general_operand" "=g<") ! 1323: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))] ! 1324: "" ! 1325: "negd %1,%0") ! 1326: ! 1327: (define_insn "neghi2" ! 1328: [(set (match_operand:HI 0 "general_operand" "=g<") ! 1329: (neg:HI (match_operand:HI 1 "general_operand" "g")))] ! 1330: "" ! 1331: "negw %1,%0") ! 1332: ! 1333: (define_insn "negqi2" ! 1334: [(set (match_operand:QI 0 "general_operand" "=g<") ! 1335: (neg:QI (match_operand:QI 1 "general_operand" "g")))] ! 1336: "" ! 1337: "negb %1,%0") ! 1338: ! 1339: (define_insn "one_cmplsi2" ! 1340: [(set (match_operand:SI 0 "general_operand" "=g<") ! 1341: (not:SI (match_operand:SI 1 "general_operand" "rmn")))] ! 1342: "" ! 1343: "comd %1,%0") ! 1344: ! 1345: (define_insn "one_cmplhi2" ! 1346: [(set (match_operand:HI 0 "general_operand" "=g<") ! 1347: (not:HI (match_operand:HI 1 "general_operand" "g")))] ! 1348: "" ! 1349: "comw %1,%0") ! 1350: ! 1351: (define_insn "one_cmplqi2" ! 1352: [(set (match_operand:QI 0 "general_operand" "=g<") ! 1353: (not:QI (match_operand:QI 1 "general_operand" "g")))] ! 1354: "" ! 1355: "comb %1,%0") ! 1356: ! 1357: ;; arithmetic left and right shift operations ! 1358: ! 1359: (define_insn "ashlsi3" ! 1360: [(set (match_operand:SI 0 "general_operand" "=g,g") ! 1361: (ashift:SI (match_operand:SI 1 "general_operand" "r,0") ! 1362: (match_operand:SI 2 "general_operand" "I,rmn")))] ! 1363: "" ! 1364: "* output_shift_insn (operands);") ! 1365: ! 1366: (define_insn "ashlhi3" ! 1367: [(set (match_operand:HI 0 "general_operand" "=g") ! 1368: (ashift:HI (match_operand:HI 1 "general_operand" "0") ! 1369: (match_operand:SI 2 "general_operand" "rmn")))] ! 1370: "" ! 1371: "* ! 1372: { if (GET_CODE (operands[2]) == CONST_INT) ! 1373: if (INTVAL (operands[2]) == 1) ! 1374: return \"addw %1,%0\"; ! 1375: else if (INTVAL (operands[2]) == 2) ! 1376: return \"addw %1,%0\;addw %0,%0\"; ! 1377: return \"ashw %2,%0\"; ! 1378: }") ! 1379: ! 1380: (define_insn "ashlqi3" ! 1381: [(set (match_operand:QI 0 "general_operand" "=g") ! 1382: (ashift:QI (match_operand:QI 1 "general_operand" "0") ! 1383: (match_operand:SI 2 "general_operand" "rmn")))] ! 1384: "" ! 1385: "* ! 1386: { if (GET_CODE (operands[2]) == CONST_INT) ! 1387: if (INTVAL (operands[2]) == 1) ! 1388: return \"addb %1,%0\"; ! 1389: else if (INTVAL (operands[2]) == 2) ! 1390: return \"addb %1,%0\;addb %0,%0\"; ! 1391: return \"ashb %2,%0\"; ! 1392: }") ! 1393: ! 1394: ;; Arithmetic right shift on the 32k works by negating the shift count. ! 1395: (define_expand "ashrsi3" ! 1396: [(set (match_operand:SI 0 "general_operand" "=g") ! 1397: (ashift:SI (match_operand:SI 1 "general_operand" "g") ! 1398: (match_operand:SI 2 "general_operand" "g")))] ! 1399: "" ! 1400: " ! 1401: { ! 1402: operands[2] = negate_rtx (SImode, operands[2]); ! 1403: }") ! 1404: ! 1405: (define_expand "ashrhi3" ! 1406: [(set (match_operand:HI 0 "general_operand" "=g") ! 1407: (ashift:HI (match_operand:HI 1 "general_operand" "g") ! 1408: (match_operand:SI 2 "general_operand" "g")))] ! 1409: "" ! 1410: " ! 1411: { ! 1412: operands[2] = negate_rtx (SImode, operands[2]); ! 1413: }") ! 1414: ! 1415: (define_expand "ashrqi3" ! 1416: [(set (match_operand:QI 0 "general_operand" "=g") ! 1417: (ashift:QI (match_operand:QI 1 "general_operand" "g") ! 1418: (match_operand:SI 2 "general_operand" "g")))] ! 1419: "" ! 1420: " ! 1421: { ! 1422: operands[2] = negate_rtx (SImode, operands[2]); ! 1423: }") ! 1424: ! 1425: ;; logical shift instructions ! 1426: ! 1427: (define_insn "lshlsi3" ! 1428: [(set (match_operand:SI 0 "general_operand" "=g") ! 1429: (lshift:SI (match_operand:SI 1 "general_operand" "0") ! 1430: (match_operand:SI 2 "general_operand" "rmn")))] ! 1431: "" ! 1432: "lshd %2,%0") ! 1433: ! 1434: (define_insn "lshlhi3" ! 1435: [(set (match_operand:HI 0 "general_operand" "=g") ! 1436: (lshift:HI (match_operand:HI 1 "general_operand" "0") ! 1437: (match_operand:SI 2 "general_operand" "rmn")))] ! 1438: "" ! 1439: "lshw %2,%0") ! 1440: ! 1441: (define_insn "lshlqi3" ! 1442: [(set (match_operand:QI 0 "general_operand" "=g") ! 1443: (lshift:QI (match_operand:QI 1 "general_operand" "0") ! 1444: (match_operand:SI 2 "general_operand" "rmn")))] ! 1445: "" ! 1446: "lshb %2,%0") ! 1447: ! 1448: ;; Logical right shift on the 32k works by negating the shift count. ! 1449: (define_expand "lshrsi3" ! 1450: [(set (match_operand:SI 0 "general_operand" "=g") ! 1451: (lshift:SI (match_operand:SI 1 "general_operand" "g") ! 1452: (match_operand:SI 2 "general_operand" "g")))] ! 1453: "" ! 1454: " ! 1455: { ! 1456: operands[2] = negate_rtx (SImode, operands[2]); ! 1457: }") ! 1458: ! 1459: (define_expand "lshrhi3" ! 1460: [(set (match_operand:HI 0 "general_operand" "=g") ! 1461: (lshift:HI (match_operand:HI 1 "general_operand" "g") ! 1462: (match_operand:SI 2 "general_operand" "g")))] ! 1463: "" ! 1464: " ! 1465: { ! 1466: operands[2] = negate_rtx (SImode, operands[2]); ! 1467: }") ! 1468: ! 1469: (define_expand "lshrqi3" ! 1470: [(set (match_operand:QI 0 "general_operand" "=g") ! 1471: (lshift:QI (match_operand:QI 1 "general_operand" "g") ! 1472: (match_operand:SI 2 "general_operand" "g")))] ! 1473: "" ! 1474: " ! 1475: { ! 1476: operands[2] = negate_rtx (SImode, operands[2]); ! 1477: }") ! 1478: ! 1479: ;; Rotate instructions ! 1480: ! 1481: (define_insn "rotlsi3" ! 1482: [(set (match_operand:SI 0 "general_operand" "=g") ! 1483: (rotate:SI (match_operand:SI 1 "general_operand" "0") ! 1484: (match_operand:SI 2 "general_operand" "rmn")))] ! 1485: "" ! 1486: "rotd %2,%0") ! 1487: ! 1488: (define_insn "rotlhi3" ! 1489: [(set (match_operand:HI 0 "general_operand" "=g") ! 1490: (rotate:HI (match_operand:HI 1 "general_operand" "0") ! 1491: (match_operand:SI 2 "general_operand" "rmn")))] ! 1492: "" ! 1493: "rotw %2,%0") ! 1494: ! 1495: (define_insn "rotlqi3" ! 1496: [(set (match_operand:QI 0 "general_operand" "=g") ! 1497: (rotate:QI (match_operand:QI 1 "general_operand" "0") ! 1498: (match_operand:SI 2 "general_operand" "rmn")))] ! 1499: "" ! 1500: "rotb %2,%0") ! 1501: ! 1502: ;; Right rotate on the 32k works by negating the shift count. ! 1503: (define_expand "rotrsi3" ! 1504: [(set (match_operand:SI 0 "general_operand" "=g") ! 1505: (rotate:SI (match_operand:SI 1 "general_operand" "g") ! 1506: (match_operand:SI 2 "general_operand" "g")))] ! 1507: "" ! 1508: " ! 1509: { ! 1510: operands[2] = negate_rtx (SImode, operands[2]); ! 1511: }") ! 1512: ! 1513: (define_expand "rotrhi3" ! 1514: [(set (match_operand:HI 0 "general_operand" "=g") ! 1515: (rotate:HI (match_operand:HI 1 "general_operand" "g") ! 1516: (match_operand:SI 2 "general_operand" "g")))] ! 1517: "" ! 1518: " ! 1519: { ! 1520: operands[2] = negate_rtx (SImode, operands[2]); ! 1521: }") ! 1522: ! 1523: (define_expand "rotrqi3" ! 1524: [(set (match_operand:QI 0 "general_operand" "=g") ! 1525: (rotate:QI (match_operand:QI 1 "general_operand" "g") ! 1526: (match_operand:SI 2 "general_operand" "g")))] ! 1527: "" ! 1528: " ! 1529: { ! 1530: operands[2] = negate_rtx (SImode, operands[2]); ! 1531: }") ! 1532: ! 1533: ;;- load or push effective address ! 1534: ;; These come after the move, add, and multiply patterns ! 1535: ;; because we don't want pushl $1 turned into pushad 1. ! 1536: ! 1537: (define_insn "" ! 1538: [(set (match_operand:SI 0 "general_operand" "=g<") ! 1539: (match_operand:QI 1 "address_operand" "p"))] ! 1540: "" ! 1541: "* ! 1542: { ! 1543: if (REG_P (operands[0]) ! 1544: && GET_CODE (operands[1]) == MULT ! 1545: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT ! 1546: && (INTVAL (XEXP (operands[1], 1)) == 2 ! 1547: || INTVAL (XEXP (operands[1], 1)) == 4)) ! 1548: { ! 1549: rtx xoperands[3]; ! 1550: xoperands[0] = operands[0]; ! 1551: xoperands[1] = XEXP (operands[1], 0); ! 1552: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1); ! 1553: return output_shift_insn (xoperands); ! 1554: } ! 1555: return \"addr %a1,%0\"; ! 1556: }") ! 1557: ! 1558: ;;; Index insns. These are about the same speed as multiply-add counterparts. ! 1559: ;;; but slower then using power-of-2 shifts if we can use them ! 1560: ; ! 1561: ;(define_insn "" ! 1562: ; [(set (match_operand:SI 0 "register_operand" "=r") ! 1563: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn") ! 1564: ; (mult:SI (match_operand:SI 2 "register_operand" "0") ! 1565: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))] ! 1566: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8" ! 1567: ; "indexd %0,%3,%1") ! 1568: ; ! 1569: ;(define_insn "" ! 1570: ; [(set (match_operand:SI 0 "register_operand" "=r") ! 1571: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0") ! 1572: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1))) ! 1573: ; (match_operand:SI 3 "general_operand" "rmn")))] ! 1574: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8" ! 1575: ; "indexd %0,%2,%3") ! 1576: ! 1577: ;; Set, Clear, and Invert bit ! 1578: ! 1579: (define_insn "" ! 1580: [(set (match_operand:SI 0 "general_operand" "=g") ! 1581: (ior:SI ! 1582: (ashift:SI (const_int 1) ! 1583: (match_operand:SI 1 "general_operand" "rmn")) ! 1584: (match_dup 0)))] ! 1585: "" ! 1586: "sbitd %1,%0") ! 1587: ! 1588: (define_insn "" ! 1589: [(set (match_operand:SI 0 "general_operand" "=g") ! 1590: (ior:SI ! 1591: (match_dup 0) ! 1592: (ashift:SI (const_int 1) ! 1593: (match_operand:SI 1 "general_operand" "rmn"))))] ! 1594: "" ! 1595: "sbitd %1,%0") ! 1596: ! 1597: (define_insn "" ! 1598: [(set (match_operand:QI 0 "general_operand" "=g") ! 1599: (ior:QI ! 1600: (subreg:QI ! 1601: (ashift:SI (const_int 1) ! 1602: (match_operand:QI 1 "general_operand" "rmn")) 0) ! 1603: (match_dup 0)))] ! 1604: "" ! 1605: "sbitb %1,%0") ! 1606: ! 1607: (define_insn "" ! 1608: [(set (match_operand:QI 0 "general_operand" "=g") ! 1609: (ior:QI ! 1610: (match_dup 0) ! 1611: (subreg:QI ! 1612: (ashift:SI (const_int 1) ! 1613: (match_operand:QI 1 "general_operand" "rmn")) 0)))] ! 1614: "" ! 1615: "sbitb %1,%0") ! 1616: ! 1617: (define_insn "" ! 1618: [(set (match_operand:SI 0 "general_operand" "=g") ! 1619: (and:SI ! 1620: (not:SI ! 1621: (ashift:SI (const_int 1) ! 1622: (match_operand:SI 1 "general_operand" "rmn"))) ! 1623: (match_dup 0)))] ! 1624: "" ! 1625: "cbitd %1,%0") ! 1626: ! 1627: (define_insn "" ! 1628: [(set (match_operand:SI 0 "general_operand" "=g") ! 1629: (and:SI ! 1630: (match_dup 0) ! 1631: (not:SI ! 1632: (ashift:SI (const_int 1) ! 1633: (match_operand:SI 1 "general_operand" "rmn")))))] ! 1634: "" ! 1635: "cbitd %1,%0") ! 1636: ! 1637: (define_insn "" ! 1638: [(set (match_operand:QI 0 "general_operand" "=g") ! 1639: (and:QI ! 1640: (subreg:QI ! 1641: (not:SI ! 1642: (ashift:SI (const_int 1) ! 1643: (match_operand:QI 1 "general_operand" "rmn"))) 0) ! 1644: (match_dup 0)))] ! 1645: "" ! 1646: "cbitb %1,%0") ! 1647: ! 1648: (define_insn "" ! 1649: [(set (match_operand:QI 0 "general_operand" "=g") ! 1650: (and:QI ! 1651: (match_dup 0) ! 1652: (subreg:QI ! 1653: (not:SI ! 1654: (ashift:SI (const_int 1) ! 1655: (match_operand:QI 1 "general_operand" "rmn"))) 0)))] ! 1656: "" ! 1657: "cbitb %1,%0") ! 1658: ! 1659: (define_insn "" ! 1660: [(set (match_operand:SI 0 "general_operand" "=g") ! 1661: (xor:SI ! 1662: (ashift:SI (const_int 1) ! 1663: (match_operand:SI 1 "general_operand" "rmn")) ! 1664: (match_dup 0)))] ! 1665: "" ! 1666: "ibitd %1,%0") ! 1667: ! 1668: (define_insn "" ! 1669: [(set (match_operand:SI 0 "general_operand" "=g") ! 1670: (xor:SI ! 1671: (match_dup 0) ! 1672: (ashift:SI (const_int 1) ! 1673: (match_operand:SI 1 "general_operand" "rmn"))))] ! 1674: "" ! 1675: "ibitd %1,%0") ! 1676: ! 1677: (define_insn "" ! 1678: [(set (match_operand:QI 0 "general_operand" "=g") ! 1679: (xor:QI ! 1680: (subreg:QI ! 1681: (ashift:SI (const_int 1) ! 1682: (match_operand:QI 1 "general_operand" "rmn")) 0) ! 1683: (match_dup 0)))] ! 1684: "" ! 1685: "ibitb %1,%0") ! 1686: ! 1687: (define_insn "" ! 1688: [(set (match_operand:QI 0 "general_operand" "=g") ! 1689: (xor:QI ! 1690: (match_dup 0) ! 1691: (subreg:QI ! 1692: (ashift:SI (const_int 1) ! 1693: (match_operand:QI 1 "general_operand" "rmn")) 0)))] ! 1694: "" ! 1695: "ibitb %1,%0") ! 1696: ! 1697: ;; Recognize jbs and jbc instructions. ! 1698: ! 1699: (define_insn "" ! 1700: [(set (cc0) ! 1701: (zero_extract (match_operand:SI 0 "general_operand" "rm") ! 1702: (const_int 1) ! 1703: (match_operand:SI 1 "general_operand" "rmn")))] ! 1704: "" ! 1705: "* ! 1706: { cc_status.flags = CC_Z_IN_F; ! 1707: return \"tbitd %1,%0\"; ! 1708: }") ! 1709: ! 1710: (define_insn "" ! 1711: [(set (cc0) ! 1712: (compare (zero_extract (match_operand:SI 0 "general_operand" "rm") ! 1713: (const_int 1) ! 1714: (match_operand:SI 1 "general_operand" "rmn")) ! 1715: (const_int 1)))] ! 1716: "" ! 1717: "* ! 1718: { cc_status.flags = CC_Z_IN_NOT_F; ! 1719: return \"tbitd %1,%0\"; ! 1720: }") ! 1721: ! 1722: (define_insn "" ! 1723: [(set (cc0) ! 1724: (zero_extract (match_operand:HI 0 "general_operand" "g") ! 1725: (const_int 1) ! 1726: (match_operand:HI 1 "general_operand" "g")))] ! 1727: "" ! 1728: "* ! 1729: { cc_status.flags = CC_Z_IN_F; ! 1730: return \"tbitw %1,%0\"; ! 1731: }") ! 1732: ! 1733: (define_insn "" ! 1734: [(set (cc0) ! 1735: (compare (zero_extract (match_operand:HI 0 "general_operand" "g") ! 1736: (const_int 1) ! 1737: (match_operand:HI 1 "general_operand" "rmn")) ! 1738: (const_int 1)))] ! 1739: "" ! 1740: "* ! 1741: { cc_status.flags = CC_Z_IN_NOT_F; ! 1742: return \"tbitw %1,%0\"; ! 1743: }") ! 1744: ! 1745: (define_insn "" ! 1746: [(set (cc0) ! 1747: (zero_extract (match_operand:QI 0 "general_operand" "g") ! 1748: (const_int 1) ! 1749: (match_operand:QI 1 "general_operand" "g")))] ! 1750: "" ! 1751: "* ! 1752: { cc_status.flags = CC_Z_IN_F; ! 1753: return \"tbitb %1,%0\"; ! 1754: }") ! 1755: ! 1756: (define_insn "" ! 1757: [(set (cc0) ! 1758: (compare (zero_extract:SI (match_operand:QI 0 "general_operand" "g") ! 1759: (const_int 1) ! 1760: (match_operand:QI 1 "general_operand" "rmn")) ! 1761: (const_int 1)))] ! 1762: "" ! 1763: "* ! 1764: { cc_status.flags = CC_Z_IN_NOT_F; ! 1765: return \"tbitb %1,%0\"; ! 1766: }") ! 1767: ! 1768: (define_insn "" ! 1769: [(set (cc0) ! 1770: (and:SI (match_operand:SI 0 "general_operand" "rm") ! 1771: (match_operand:SI 1 "immediate_operand" "i")))] ! 1772: "GET_CODE (operands[1]) == CONST_INT ! 1773: && exact_log2 (INTVAL (operands[1])) >= 0" ! 1774: "* ! 1775: { ! 1776: operands[1] ! 1777: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1]))); ! 1778: cc_status.flags = CC_Z_IN_F; ! 1779: return \"tbitd %1,%0\"; ! 1780: }") ! 1781: ! 1782: ;; extract(base, width, offset) ! 1783: ;; Signed bitfield extraction is not supported in hardware on the ! 1784: ;; NS 32032. It is therefore better to let GCC figure out a ! 1785: ;; good strategy for generating the proper instruction sequence ! 1786: ;; and represent it as rtl. ! 1787: ! 1788: ;; Optimize the case of extracting a byte or word from a register. ! 1789: ;; Otherwise we must load a register with the offset of the ! 1790: ;; chunk we want, and perform an extract insn (each of which ! 1791: ;; is very expensive). Since we use the stack to do our bit-twiddling ! 1792: ;; we cannot use it for a destination. Perhaps things are fast ! 1793: ;; enough on the 32532 that such hacks are not needed. ! 1794: ! 1795: (define_insn "" ! 1796: [(set (match_operand:SI 0 "general_operand" "=ro") ! 1797: (zero_extract:SI (match_operand:SI 1 "register_operand" "r") ! 1798: (match_operand:SI 2 "const_int" "i") ! 1799: (match_operand:SI 3 "const_int" "i")))] ! 1800: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) ! 1801: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)" ! 1802: "* ! 1803: { ! 1804: output_asm_insn (\"movd %1,tos\", operands); ! 1805: if (INTVAL (operands[2]) == 16) ! 1806: { ! 1807: if (INTVAL (operands[3]) == 8) ! 1808: output_asm_insn (\"movzwd 1(sp),%0\", operands); ! 1809: else ! 1810: output_asm_insn (\"movzwd 2(sp),%0\", operands); ! 1811: } ! 1812: else ! 1813: { ! 1814: if (INTVAL (operands[3]) == 8) ! 1815: output_asm_insn (\"movzbd 1(sp),%0\", operands); ! 1816: else if (INTVAL (operands[3]) == 16) ! 1817: output_asm_insn (\"movzbd 2(sp),%0\", operands); ! 1818: else ! 1819: output_asm_insn (\"movzbd 3(sp),%0\", operands); ! 1820: } ! 1821: #if defined(ns32532) || defined(ns32332) ! 1822: return \"cmpqd %$0,tos # adjsp -4\"; ! 1823: #else ! 1824: return \"adjspb %$-4\"; ! 1825: #endif ! 1826: }") ! 1827: ! 1828: (define_insn "" ! 1829: [(set (match_operand:SI 0 "general_operand" "=ro") ! 1830: (zero_extract:SI (match_operand:HI 1 "register_operand" "r") ! 1831: (match_operand:SI 2 "const_int" "i") ! 1832: (match_operand:SI 3 "const_int" "i")))] ! 1833: "INTVAL (operands[2]) == 8 && INTVAL (operands[3]) == 8" ! 1834: "movw %1,tos\;movzbd 1(sp),%0\;adjspb %$-2") ! 1835: ! 1836: (define_insn "extzv" ! 1837: [(set (match_operand:SI 0 "general_operand" "=g<,g<") ! 1838: (zero_extract:SI (match_operand:SI 1 "general_operand" "rm,o") ! 1839: (match_operand:SI 2 "const_int" "i,i") ! 1840: (match_operand:SI 3 "general_operand" "rK,n")))] ! 1841: "" ! 1842: "* ! 1843: { if (GET_CODE (operands[3]) == CONST_INT) ! 1844: { ! 1845: if (INTVAL (operands[3]) >= 8) ! 1846: operands[1] = adj_offsettable_operand (operands[1], ! 1847: INTVAL (operands[3]) >> 3); ! 1848: return \"extsd %1,%0,%3,%2\"; ! 1849: } ! 1850: else return \"extd %3,%1,%0,%2\"; ! 1851: }") ! 1852: ! 1853: (define_insn "" ! 1854: [(set (match_operand:SI 0 "general_operand" "=g<,g<") ! 1855: (zero_extract:SI (match_operand:HI 1 "general_operand" "rm,o") ! 1856: (match_operand:SI 2 "const_int" "i,i") ! 1857: (match_operand:SI 3 "general_operand" "rK,n")))] ! 1858: "" ! 1859: "* ! 1860: { if (GET_CODE (operands[3]) == CONST_INT) ! 1861: { ! 1862: if (INTVAL (operands[3]) >= 8) ! 1863: operands[1] = adj_offsettable_operand (operands[1], ! 1864: INTVAL (operands[3]) >> 3); ! 1865: return \"extsd %1,%0,%3,%2\"; ! 1866: } ! 1867: else return \"extd %3,%1,%0,%2\"; ! 1868: }") ! 1869: ! 1870: (define_insn "" ! 1871: [(set (match_operand:SI 0 "general_operand" "=g<") ! 1872: (zero_extract:SI (match_operand:QI 1 "general_operand" "g") ! 1873: (match_operand:SI 2 "const_int" "i") ! 1874: (match_operand:SI 3 "general_operand" "rn")))] ! 1875: "" ! 1876: "* ! 1877: { if (GET_CODE (operands[3]) == CONST_INT) ! 1878: return \"extsd %1,%0,%3,%2\"; ! 1879: else return \"extd %3,%1,%0,%2\"; ! 1880: }") ! 1881: ! 1882: (define_insn "insv" ! 1883: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g,o") ! 1884: (match_operand:SI 1 "const_int" "i,i") ! 1885: (match_operand:SI 2 "general_operand" "rK,n")) ! 1886: (match_operand:SI 3 "general_operand" "rm,rm"))] ! 1887: "" ! 1888: "* ! 1889: { if (GET_CODE (operands[2]) == CONST_INT) ! 1890: { ! 1891: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8) ! 1892: { ! 1893: operands[0] = adj_offsettable_operand (operands[0], ! 1894: INTVAL (operands[2]) / 8); ! 1895: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8); ! 1896: } ! 1897: if (INTVAL (operands[1]) <= 8) ! 1898: return \"inssb %3,%0,%2,%1\"; ! 1899: else if (INTVAL (operands[1]) <= 16) ! 1900: return \"inssw %3,%0,%2,%1\"; ! 1901: else ! 1902: return \"inssd %3,%0,%2,%1\"; ! 1903: } ! 1904: return \"insd %2,%3,%0,%1\"; ! 1905: }") ! 1906: ! 1907: (define_insn "" ! 1908: [(set (zero_extract:SI (match_operand:HI 0 "general_operand" "+g,o") ! 1909: (match_operand:SI 1 "const_int" "i,i") ! 1910: (match_operand:SI 2 "general_operand" "rK,n")) ! 1911: (match_operand:SI 3 "general_operand" "rm,rm"))] ! 1912: "" ! 1913: "* ! 1914: { if (GET_CODE (operands[2]) == CONST_INT) ! 1915: { ! 1916: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8) ! 1917: { ! 1918: operands[0] = adj_offsettable_operand (operands[0], ! 1919: INTVAL (operands[2]) / 8); ! 1920: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8); ! 1921: } ! 1922: if (INTVAL (operands[1]) <= 8) ! 1923: return \"inssb %3,%0,%2,%1\"; ! 1924: else if (INTVAL (operands[1]) <= 16) ! 1925: return \"inssw %3,%0,%2,%1\"; ! 1926: else ! 1927: return \"inssd %3,%0,%2,%1\"; ! 1928: } ! 1929: return \"insd %2,%3,%0,%1\"; ! 1930: }") ! 1931: ! 1932: (define_insn "" ! 1933: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "=g") ! 1934: (match_operand:SI 1 "const_int" "i") ! 1935: (match_operand:SI 2 "general_operand" "rn")) ! 1936: (match_operand:SI 3 "general_operand" "rm"))] ! 1937: "" ! 1938: "* ! 1939: { if (GET_CODE (operands[2]) == CONST_INT) ! 1940: if (INTVAL (operands[1]) <= 8) ! 1941: return \"inssb %3,%0,%2,%1\"; ! 1942: else if (INTVAL (operands[1]) <= 16) ! 1943: return \"inssw %3,%0,%2,%1\"; ! 1944: else ! 1945: return \"inssd %3,%0,%2,%1\"; ! 1946: return \"insd %2,%3,%0,%1\"; ! 1947: }") ! 1948: ! 1949: ! 1950: (define_insn "jump" ! 1951: [(set (pc) ! 1952: (label_ref (match_operand 0 "" "")))] ! 1953: "" ! 1954: "br %l0") ! 1955: ! 1956: (define_insn "beq" ! 1957: [(set (pc) ! 1958: (if_then_else (eq (cc0) ! 1959: (const_int 0)) ! 1960: (label_ref (match_operand 0 "" "")) ! 1961: (pc)))] ! 1962: "" ! 1963: "* ! 1964: { if (cc_prev_status.flags & CC_Z_IN_F) ! 1965: return \"bfc %l0\"; ! 1966: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 1967: return \"bfs %l0\"; ! 1968: else return \"beq %l0\"; ! 1969: }") ! 1970: ! 1971: (define_insn "bne" ! 1972: [(set (pc) ! 1973: (if_then_else (ne (cc0) ! 1974: (const_int 0)) ! 1975: (label_ref (match_operand 0 "" "")) ! 1976: (pc)))] ! 1977: "" ! 1978: "* ! 1979: { if (cc_prev_status.flags & CC_Z_IN_F) ! 1980: return \"bfs %l0\"; ! 1981: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 1982: return \"bfc %l0\"; ! 1983: else return \"bne %l0\"; ! 1984: }") ! 1985: ! 1986: (define_insn "bgt" ! 1987: [(set (pc) ! 1988: (if_then_else (gt (cc0) ! 1989: (const_int 0)) ! 1990: (label_ref (match_operand 0 "" "")) ! 1991: (pc)))] ! 1992: "" ! 1993: "bgt %l0") ! 1994: ! 1995: (define_insn "bgtu" ! 1996: [(set (pc) ! 1997: (if_then_else (gtu (cc0) ! 1998: (const_int 0)) ! 1999: (label_ref (match_operand 0 "" "")) ! 2000: (pc)))] ! 2001: "" ! 2002: "bhi %l0") ! 2003: ! 2004: (define_insn "blt" ! 2005: [(set (pc) ! 2006: (if_then_else (lt (cc0) ! 2007: (const_int 0)) ! 2008: (label_ref (match_operand 0 "" "")) ! 2009: (pc)))] ! 2010: "" ! 2011: "blt %l0") ! 2012: ! 2013: (define_insn "bltu" ! 2014: [(set (pc) ! 2015: (if_then_else (ltu (cc0) ! 2016: (const_int 0)) ! 2017: (label_ref (match_operand 0 "" "")) ! 2018: (pc)))] ! 2019: "" ! 2020: "blo %l0") ! 2021: ! 2022: (define_insn "bge" ! 2023: [(set (pc) ! 2024: (if_then_else (ge (cc0) ! 2025: (const_int 0)) ! 2026: (label_ref (match_operand 0 "" "")) ! 2027: (pc)))] ! 2028: "" ! 2029: "bge %l0") ! 2030: ! 2031: (define_insn "bgeu" ! 2032: [(set (pc) ! 2033: (if_then_else (geu (cc0) ! 2034: (const_int 0)) ! 2035: (label_ref (match_operand 0 "" "")) ! 2036: (pc)))] ! 2037: "" ! 2038: "bhs %l0") ! 2039: ! 2040: (define_insn "ble" ! 2041: [(set (pc) ! 2042: (if_then_else (le (cc0) ! 2043: (const_int 0)) ! 2044: (label_ref (match_operand 0 "" "")) ! 2045: (pc)))] ! 2046: "" ! 2047: "ble %l0") ! 2048: ! 2049: (define_insn "bleu" ! 2050: [(set (pc) ! 2051: (if_then_else (leu (cc0) ! 2052: (const_int 0)) ! 2053: (label_ref (match_operand 0 "" "")) ! 2054: (pc)))] ! 2055: "" ! 2056: "bls %l0") ! 2057: ! 2058: (define_insn "" ! 2059: [(set (pc) ! 2060: (if_then_else (eq (cc0) ! 2061: (const_int 0)) ! 2062: (pc) ! 2063: (label_ref (match_operand 0 "" ""))))] ! 2064: "" ! 2065: "* ! 2066: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2067: return \"bfs %l0\"; ! 2068: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2069: return \"bfc %l0\"; ! 2070: else return \"bne %l0\"; ! 2071: }") ! 2072: ! 2073: (define_insn "" ! 2074: [(set (pc) ! 2075: (if_then_else (ne (cc0) ! 2076: (const_int 0)) ! 2077: (pc) ! 2078: (label_ref (match_operand 0 "" ""))))] ! 2079: "" ! 2080: "* ! 2081: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2082: return \"bfc %l0\"; ! 2083: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2084: return \"bfs %l0\"; ! 2085: else return \"beq %l0\"; ! 2086: }") ! 2087: ! 2088: (define_insn "" ! 2089: [(set (pc) ! 2090: (if_then_else (gt (cc0) ! 2091: (const_int 0)) ! 2092: (pc) ! 2093: (label_ref (match_operand 0 "" ""))))] ! 2094: "" ! 2095: "ble %l0") ! 2096: ! 2097: (define_insn "" ! 2098: [(set (pc) ! 2099: (if_then_else (gtu (cc0) ! 2100: (const_int 0)) ! 2101: (pc) ! 2102: (label_ref (match_operand 0 "" ""))))] ! 2103: "" ! 2104: "bls %l0") ! 2105: ! 2106: (define_insn "" ! 2107: [(set (pc) ! 2108: (if_then_else (lt (cc0) ! 2109: (const_int 0)) ! 2110: (pc) ! 2111: (label_ref (match_operand 0 "" ""))))] ! 2112: "" ! 2113: "bge %l0") ! 2114: ! 2115: (define_insn "" ! 2116: [(set (pc) ! 2117: (if_then_else (ltu (cc0) ! 2118: (const_int 0)) ! 2119: (pc) ! 2120: (label_ref (match_operand 0 "" ""))))] ! 2121: "" ! 2122: "bhs %l0") ! 2123: ! 2124: (define_insn "" ! 2125: [(set (pc) ! 2126: (if_then_else (ge (cc0) ! 2127: (const_int 0)) ! 2128: (pc) ! 2129: (label_ref (match_operand 0 "" ""))))] ! 2130: "" ! 2131: "blt %l0") ! 2132: ! 2133: (define_insn "" ! 2134: [(set (pc) ! 2135: (if_then_else (geu (cc0) ! 2136: (const_int 0)) ! 2137: (pc) ! 2138: (label_ref (match_operand 0 "" ""))))] ! 2139: "" ! 2140: "blo %l0") ! 2141: ! 2142: (define_insn "" ! 2143: [(set (pc) ! 2144: (if_then_else (le (cc0) ! 2145: (const_int 0)) ! 2146: (pc) ! 2147: (label_ref (match_operand 0 "" ""))))] ! 2148: "" ! 2149: "bgt %l0") ! 2150: ! 2151: (define_insn "" ! 2152: [(set (pc) ! 2153: (if_then_else (leu (cc0) ! 2154: (const_int 0)) ! 2155: (pc) ! 2156: (label_ref (match_operand 0 "" ""))))] ! 2157: "" ! 2158: "bhi %l0") ! 2159: ! 2160: ;; Subtract-and-jump and Add-and-jump insns. ! 2161: ;; These can actually be used for adding numbers in the range -8 to 7 ! 2162: ! 2163: (define_insn "" ! 2164: [(set (pc) ! 2165: (if_then_else ! 2166: (ne (minus:SI (match_operand:SI 0 "general_operand" "+g") ! 2167: (match_operand:SI 1 "general_operand" "i")) ! 2168: (const_int 0)) ! 2169: (label_ref (match_operand 2 "" "")) ! 2170: (pc))) ! 2171: (set (match_dup 0) ! 2172: (minus:SI (match_dup 0) ! 2173: (match_dup 1)))] ! 2174: "GET_CODE (operands[1]) == CONST_INT ! 2175: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8" ! 2176: "acbd %$%n1,%0,%l2") ! 2177: ! 2178: (define_insn "" ! 2179: [(set (pc) ! 2180: (if_then_else ! 2181: (ne (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 2182: (match_operand:SI 1 "general_operand" "i")) ! 2183: (const_int 0)) ! 2184: (label_ref (match_operand 2 "" "")) ! 2185: (pc))) ! 2186: (set (match_dup 0) ! 2187: (plus:SI (match_dup 0) ! 2188: (match_dup 1)))] ! 2189: "GET_CODE (operands[1]) == CONST_INT ! 2190: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8" ! 2191: "acbd %1,%0,%l2") ! 2192: ! 2193: ;; Reversed ! 2194: ! 2195: (define_insn "" ! 2196: [(set (pc) ! 2197: (if_then_else ! 2198: (eq (minus:SI (match_operand:SI 0 "general_operand" "+g") ! 2199: (match_operand:SI 1 "general_operand" "i")) ! 2200: (const_int 0)) ! 2201: (pc) ! 2202: (label_ref (match_operand 2 "" "")))) ! 2203: (set (match_dup 0) ! 2204: (minus:SI (match_dup 0) ! 2205: (match_dup 1)))] ! 2206: "GET_CODE (operands[1]) == CONST_INT ! 2207: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8" ! 2208: "acbd %$%n1,%0,%l2") ! 2209: ! 2210: (define_insn "" ! 2211: [(set (pc) ! 2212: (if_then_else ! 2213: (eq (plus:SI (match_operand:SI 0 "general_operand" "+g") ! 2214: (match_operand:SI 1 "general_operand" "i")) ! 2215: (const_int 0)) ! 2216: (pc) ! 2217: (label_ref (match_operand 2 "" "")))) ! 2218: (set (match_dup 0) ! 2219: (plus:SI (match_dup 0) ! 2220: (match_dup 1)))] ! 2221: "GET_CODE (operands[1]) == CONST_INT ! 2222: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8" ! 2223: "acbd %1,%0,%l2") ! 2224: ! 2225: (define_insn "call" ! 2226: [(call (match_operand:QI 0 "general_operand" "g") ! 2227: (match_operand:QI 1 "general_operand" "g"))] ! 2228: "" ! 2229: "* ! 2230: { ! 2231: if (GET_CODE (operands[0]) == MEM) ! 2232: { ! 2233: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0))) ! 2234: #ifdef GNX_V3 ! 2235: return \"bsr %0\"; ! 2236: #else ! 2237: return \"bsr %?%a0\"; ! 2238: #endif ! 2239: if (GET_CODE (XEXP (operands[0], 0)) == REG) ! 2240: #ifdef GNX_V3 ! 2241: return \"jsr %0\"; ! 2242: #else ! 2243: return \"jsr %a0\"; ! 2244: #endif ! 2245: } ! 2246: return \"jsr %0\"; ! 2247: }") ! 2248: ! 2249: (define_insn "call_value" ! 2250: [(set (match_operand 0 "" "=fg") ! 2251: (call (match_operand:QI 1 "general_operand" "g") ! 2252: (match_operand:QI 2 "general_operand" "g")))] ! 2253: "" ! 2254: "* ! 2255: { ! 2256: if (GET_CODE (operands[1]) == MEM) ! 2257: { ! 2258: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0))) ! 2259: #ifdef GNX_V3 ! 2260: return \"bsr %1\"; ! 2261: #else ! 2262: return \"bsr %?%a1\"; ! 2263: #endif ! 2264: if (GET_CODE (XEXP (operands[1], 0)) == REG) ! 2265: #ifdef GNX_V3 ! 2266: return \"jsr %1\"; ! 2267: #else ! 2268: return \"jsr %a1\"; ! 2269: #endif ! 2270: } ! 2271: return \"jsr %1\"; ! 2272: }") ! 2273: ! 2274: (define_insn "return" ! 2275: [(return)] ! 2276: "0" ! 2277: "ret 0") ! 2278: ! 2279: (define_insn "abssf2" ! 2280: [(set (match_operand:SF 0 "general_operand" "=fm<") ! 2281: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))] ! 2282: "TARGET_32081" ! 2283: "absf %1,%0") ! 2284: ! 2285: (define_insn "absdf2" ! 2286: [(set (match_operand:DF 0 "general_operand" "=fm<") ! 2287: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))] ! 2288: "TARGET_32081" ! 2289: "absl %1,%0") ! 2290: ! 2291: (define_insn "abssi2" ! 2292: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2293: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))] ! 2294: "" ! 2295: "absd %1,%0") ! 2296: ! 2297: (define_insn "abshi2" ! 2298: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2299: (abs:HI (match_operand:HI 1 "general_operand" "g")))] ! 2300: "" ! 2301: "absw %1,%0") ! 2302: ! 2303: (define_insn "absqi2" ! 2304: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2305: (abs:QI (match_operand:QI 1 "general_operand" "g")))] ! 2306: "" ! 2307: "absb %1,%0") ! 2308: ! 2309: (define_insn "nop" ! 2310: [(const_int 0)] ! 2311: "" ! 2312: "nop") ! 2313: ! 2314: ;;(define_insn "tablejump" ! 2315: ;; [(set (pc) ! 2316: ;; (plus:SI (match_operand:SI 0 "general_operand" "g") ! 2317: ;; (pc)))] ! 2318: ;; "" ! 2319: ;; "cased %0") ! 2320: ! 2321: (define_insn "tablejump" ! 2322: [(set (pc) ! 2323: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g"))) ! 2324: (use (label_ref (match_operand 1 "" "")))] ! 2325: "" ! 2326: "* ! 2327: { ! 2328: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", ! 2329: CODE_LABEL_NUMBER (operands[1])); ! 2330: return \"casew %0\"; ! 2331: }") ! 2332: ! 2333: ;;(define_insn "" ! 2334: ;; [(set (pc) ! 2335: ;; (plus:SI (match_operand:QI 0 "general_operand" "g") ! 2336: ;; (pc)))] ! 2337: ;; "" ! 2338: ;; "caseb %0") ! 2339: ! 2340: ;; Scondi instructions ! 2341: (define_insn "seq" ! 2342: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2343: (eq (cc0) (const_int 0)))] ! 2344: "" ! 2345: "* ! 2346: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2347: return \"sfcd %0\"; ! 2348: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2349: return \"sfsd %0\"; ! 2350: else return \"seqd %0\"; ! 2351: }") ! 2352: ! 2353: (define_insn "" ! 2354: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2355: (eq (cc0) (const_int 0)))] ! 2356: "" ! 2357: "* ! 2358: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2359: return \"sfcw %0\"; ! 2360: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2361: return \"sfsw %0\"; ! 2362: else return \"seqw %0\"; ! 2363: }") ! 2364: ! 2365: (define_insn "" ! 2366: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2367: (eq (cc0) (const_int 0)))] ! 2368: "" ! 2369: "* ! 2370: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2371: return \"sfcb %0\"; ! 2372: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2373: return \"sfsb %0\"; ! 2374: else return \"seqb %0\"; ! 2375: }") ! 2376: ! 2377: (define_insn "sne" ! 2378: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2379: (ne (cc0) (const_int 0)))] ! 2380: "" ! 2381: "* ! 2382: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2383: return \"sfsd %0\"; ! 2384: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2385: return \"sfcd %0\"; ! 2386: else return \"sned %0\"; ! 2387: }") ! 2388: ! 2389: (define_insn "" ! 2390: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2391: (ne (cc0) (const_int 0)))] ! 2392: "" ! 2393: "* ! 2394: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2395: return \"sfsw %0\"; ! 2396: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2397: return \"sfcw %0\"; ! 2398: else return \"snew %0\"; ! 2399: }") ! 2400: ! 2401: (define_insn "" ! 2402: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2403: (ne (cc0) (const_int 0)))] ! 2404: "" ! 2405: "* ! 2406: { if (cc_prev_status.flags & CC_Z_IN_F) ! 2407: return \"sfsb %0\"; ! 2408: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) ! 2409: return \"sfcb %0\"; ! 2410: else return \"sneb %0\"; ! 2411: }") ! 2412: ! 2413: (define_insn "sgt" ! 2414: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2415: (gt (cc0) (const_int 0)))] ! 2416: "" ! 2417: "sgtd %0") ! 2418: ! 2419: (define_insn "" ! 2420: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2421: (gt (cc0) (const_int 0)))] ! 2422: "" ! 2423: "sgtw %0") ! 2424: ! 2425: (define_insn "" ! 2426: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2427: (gt (cc0) (const_int 0)))] ! 2428: "" ! 2429: "sgtb %0") ! 2430: ! 2431: (define_insn "sgtu" ! 2432: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2433: (gtu (cc0) (const_int 0)))] ! 2434: "" ! 2435: "shid %0") ! 2436: ! 2437: (define_insn "" ! 2438: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2439: (gtu (cc0) (const_int 0)))] ! 2440: "" ! 2441: "shiw %0") ! 2442: ! 2443: (define_insn "" ! 2444: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2445: (gtu (cc0) (const_int 0)))] ! 2446: "" ! 2447: "shib %0") ! 2448: ! 2449: (define_insn "slt" ! 2450: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2451: (lt (cc0) (const_int 0)))] ! 2452: "" ! 2453: "sltd %0") ! 2454: ! 2455: (define_insn "" ! 2456: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2457: (lt (cc0) (const_int 0)))] ! 2458: "" ! 2459: "sltw %0") ! 2460: ! 2461: (define_insn "" ! 2462: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2463: (lt (cc0) (const_int 0)))] ! 2464: "" ! 2465: "sltb %0") ! 2466: ! 2467: (define_insn "sltu" ! 2468: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2469: (ltu (cc0) (const_int 0)))] ! 2470: "" ! 2471: "slod %0") ! 2472: ! 2473: (define_insn "" ! 2474: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2475: (ltu (cc0) (const_int 0)))] ! 2476: "" ! 2477: "slow %0") ! 2478: ! 2479: (define_insn "" ! 2480: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2481: (ltu (cc0) (const_int 0)))] ! 2482: "" ! 2483: "slob %0") ! 2484: ! 2485: (define_insn "sge" ! 2486: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2487: (ge (cc0) (const_int 0)))] ! 2488: "" ! 2489: "sged %0") ! 2490: ! 2491: (define_insn "" ! 2492: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2493: (ge (cc0) (const_int 0)))] ! 2494: "" ! 2495: "sgew %0") ! 2496: ! 2497: (define_insn "" ! 2498: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2499: (ge (cc0) (const_int 0)))] ! 2500: "" ! 2501: "sgeb %0") ! 2502: ! 2503: (define_insn "sgeu" ! 2504: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2505: (geu (cc0) (const_int 0)))] ! 2506: "" ! 2507: "shsd %0") ! 2508: ! 2509: (define_insn "" ! 2510: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2511: (geu (cc0) (const_int 0)))] ! 2512: "" ! 2513: "shsw %0") ! 2514: ! 2515: (define_insn "" ! 2516: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2517: (geu (cc0) (const_int 0)))] ! 2518: "" ! 2519: "shsb %0") ! 2520: ! 2521: (define_insn "sle" ! 2522: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2523: (le (cc0) (const_int 0)))] ! 2524: "" ! 2525: "sled %0") ! 2526: ! 2527: (define_insn "" ! 2528: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2529: (le (cc0) (const_int 0)))] ! 2530: "" ! 2531: "slew %0") ! 2532: ! 2533: (define_insn "" ! 2534: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2535: (le (cc0) (const_int 0)))] ! 2536: "" ! 2537: "sleb %0") ! 2538: ! 2539: (define_insn "sleu" ! 2540: [(set (match_operand:SI 0 "general_operand" "=g<") ! 2541: (leu (cc0) (const_int 0)))] ! 2542: "" ! 2543: "slsd %0") ! 2544: ! 2545: (define_insn "" ! 2546: [(set (match_operand:HI 0 "general_operand" "=g<") ! 2547: (leu (cc0) (const_int 0)))] ! 2548: "" ! 2549: "slsw %0") ! 2550: ! 2551: (define_insn "" ! 2552: [(set (match_operand:QI 0 "general_operand" "=g<") ! 2553: (leu (cc0) (const_int 0)))] ! 2554: "" ! 2555: "slsb %0") ! 2556: ! 2557: ;;- Local variables: ! 2558: ;;- mode:emacs-lisp ! 2559: ;;- comment-start: ";;- " ! 2560: ;;- eval: (set-syntax-table (copy-sequence (syntax-table))) ! 2561: ;;- eval: (modify-syntax-entry ?[ "(]") ! 2562: ;;- eval: (modify-syntax-entry ?] ")[") ! 2563: ;;- eval: (modify-syntax-entry ?{ "(}") ! 2564: ;;- eval: (modify-syntax-entry ?} "){") ! 2565: ;;- End:
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