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1.1 root 1: ; BUGS:
2: ;; Insert no-op between an insn with memory read-write operands
3: ;; following by a scale-indexing operation.
4: ;; The Sequent assembler does not allow addresses to be used
5: ;; except in insns which explicitly compute an effective address.
6: ;; I.e., one cannot say "cmpd _p,@_x"
7: ;; Implement unsigned multiplication??
8:
9: ;;- Machine descrption for GNU compiler
10: ;;- ns32000 Version
11: ;; Copyright (C) 1988 Free Software Foundation, Inc.
12: ;; Contributed by Michael Tiemann ([email protected])
13:
14: ;; This file is part of GNU CC.
15:
16: ;; GNU CC is free software; you can redistribute it and/or modify
17: ;; it under the terms of the GNU General Public License as published by
18: ;; the Free Software Foundation; either version 2, or (at your option)
19: ;; any later version.
20:
21: ;; GNU CC is distributed in the hope that it will be useful,
22: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
23: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24: ;; GNU General Public License for more details.
25:
26: ;; You should have received a copy of the GNU General Public License
27: ;; along with GNU CC; see the file COPYING. If not, write to
28: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
29:
30:
31: ;;- Instruction patterns. When multiple patterns apply,
32: ;;- the first one in the file is chosen.
33: ;;-
34: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
35: ;;-
36: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
37: ;;- updates for most instructions.
38:
39: ;; We don't want to allow a constant operand for test insns because
40: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
41: ;; be folded while optimizing anyway.
42:
43: (define_insn "tstsi"
44: [(set (cc0)
45: (match_operand:SI 0 "nonimmediate_operand" "rm"))]
46: ""
47: "*
48: { cc_status.flags |= CC_REVERSED;
49: operands[1] = const0_rtx;
50: return \"cmpqd %1,%0\"; }")
51:
52: (define_insn "tsthi"
53: [(set (cc0)
54: (match_operand:HI 0 "nonimmediate_operand" "g"))]
55: ""
56: "*
57: { cc_status.flags |= CC_REVERSED;
58: operands[1] = const0_rtx;
59: return \"cmpqw %1,%0\"; }")
60:
61: (define_insn "tstqi"
62: [(set (cc0)
63: (match_operand:QI 0 "nonimmediate_operand" "g"))]
64: ""
65: "*
66: { cc_status.flags |= CC_REVERSED;
67: operands[1] = const0_rtx;
68: return \"cmpqb %1,%0\"; }")
69:
70: (define_insn "tstdf"
71: [(set (cc0)
72: (match_operand:DF 0 "general_operand" "fmF"))]
73: "TARGET_32081"
74: "*
75: { cc_status.flags |= CC_REVERSED;
76: operands[1] = CONST0_RTX (DFmode);
77: return \"cmpl %1,%0\"; }")
78:
79: (define_insn "tstsf"
80: [(set (cc0)
81: (match_operand:SF 0 "general_operand" "fmF"))]
82: "TARGET_32081"
83: "*
84: { cc_status.flags |= CC_REVERSED;
85: operands[1] = CONST0_RTX (SFmode);
86: return \"cmpf %1,%0\"; }")
87:
88: (define_insn "cmpsi"
89: [(set (cc0)
90: (compare (match_operand:SI 0 "nonimmediate_operand" "rmn")
91: (match_operand:SI 1 "general_operand" "rmn")))]
92: ""
93: "*
94: {
95: if (GET_CODE (operands[1]) == CONST_INT)
96: {
97: int i = INTVAL (operands[1]);
98: if (i <= 7 && i >= -8)
99: {
100: cc_status.flags |= CC_REVERSED;
101: return \"cmpqd %1,%0\";
102: }
103: }
104: cc_status.flags &= ~CC_REVERSED;
105: if (GET_CODE (operands[0]) == CONST_INT)
106: {
107: int i = INTVAL (operands[0]);
108: if (i <= 7 && i >= -8)
109: return \"cmpqd %0,%1\";
110: }
111: return \"cmpd %0,%1\";
112: }")
113:
114: (define_insn "cmphi"
115: [(set (cc0)
116: (compare (match_operand:HI 0 "nonimmediate_operand" "g")
117: (match_operand:HI 1 "general_operand" "g")))]
118: ""
119: "*
120: {
121: if (GET_CODE (operands[1]) == CONST_INT)
122: {
123: short i = INTVAL (operands[1]);
124: if (i <= 7 && i >= -8)
125: {
126: cc_status.flags |= CC_REVERSED;
127: if (INTVAL (operands[1]) > 7)
128: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
129: return \"cmpqw %1,%0\";
130: }
131: }
132: cc_status.flags &= ~CC_REVERSED;
133: if (GET_CODE (operands[0]) == CONST_INT)
134: {
135: short i = INTVAL (operands[0]);
136: if (i <= 7 && i >= -8)
137: {
138: if (INTVAL (operands[0]) > 7)
139: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
140: return \"cmpqw %0,%1\";
141: }
142: }
143: return \"cmpw %0,%1\";
144: }")
145:
146: (define_insn "cmpqi"
147: [(set (cc0)
148: (compare (match_operand:QI 0 "nonimmediate_operand" "g")
149: (match_operand:QI 1 "general_operand" "g")))]
150: ""
151: "*
152: {
153: if (GET_CODE (operands[1]) == CONST_INT)
154: {
155: char i = INTVAL (operands[1]);
156: if (i <= 7 && i >= -8)
157: {
158: cc_status.flags |= CC_REVERSED;
159: if (INTVAL (operands[1]) > 7)
160: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
161: return \"cmpqb %1,%0\";
162: }
163: }
164: cc_status.flags &= ~CC_REVERSED;
165: if (GET_CODE (operands[0]) == CONST_INT)
166: {
167: char i = INTVAL (operands[0]);
168: if (i <= 7 && i >= -8)
169: {
170: if (INTVAL (operands[0]) > 7)
171: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
172: return \"cmpqb %0,%1\";
173: }
174: }
175: return \"cmpb %0,%1\";
176: }")
177:
178: (define_insn "cmpdf"
179: [(set (cc0)
180: (compare (match_operand:DF 0 "general_operand" "fmF")
181: (match_operand:DF 1 "general_operand" "fmF")))]
182: "TARGET_32081"
183: "cmpl %0,%1")
184:
185: (define_insn "cmpsf"
186: [(set (cc0)
187: (compare (match_operand:SF 0 "general_operand" "fmF")
188: (match_operand:SF 1 "general_operand" "fmF")))]
189: "TARGET_32081"
190: "cmpf %0,%1")
191:
192: (define_insn "movdf"
193: [(set (match_operand:DF 0 "general_operand" "=&fg<")
194: (match_operand:DF 1 "general_operand" "fFg"))]
195: ""
196: "*
197: {
198: if (FP_REG_P (operands[0]))
199: {
200: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
201: return \"movl %1,%0\";
202: if (REG_P (operands[1]))
203: {
204: rtx xoperands[2];
205: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
206: output_asm_insn (\"movd %1,tos\", xoperands);
207: output_asm_insn (\"movd %1,tos\", operands);
208: return \"movl tos,%0\";
209: }
210: return \"movl %1,%0\";
211: }
212: else if (FP_REG_P (operands[1]))
213: {
214: if (REG_P (operands[0]))
215: {
216: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
217: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
218: return \"movd tos,%0\";
219: }
220: else
221: return \"movl %1,%0\";
222: }
223: return output_move_double (operands);
224: }")
225:
226: (define_insn "movsf"
227: [(set (match_operand:SF 0 "general_operand" "=fg<")
228: (match_operand:SF 1 "general_operand" "fFg"))]
229: ""
230: "*
231: {
232: if (FP_REG_P (operands[0]))
233: {
234: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
235: return \"movd %1,tos\;movf tos,%0\";
236: else
237: return \"movf %1,%0\";
238: }
239: else if (FP_REG_P (operands[1]))
240: {
241: if (REG_P (operands[0]))
242: return \"movf %1,tos\;movd tos,%0\";
243: return \"movf %1,%0\";
244: }
245: #if 0
246: #ifndef GAS_SYNTAX
247: /* GAS understands floating constants in ordinary movd instructions
248: but other assemblers might object. */
249: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
250: {
251: union {int i[2]; float f; double d;} convrt;
252: convrt.i[0] = CONST_DOUBLE_LOW (operands[1]);
253: convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]);
254: convrt.f = convrt.d;
255:
256: /* Is there a better machine-independent way to to this? */
257: operands[1] = gen_rtx (CONST_INT, VOIDmode, convrt.i[0]);
258: return \"movd %1,%0\";
259: }
260: #endif
261: #endif
262: else return \"movd %1,%0\";
263: }")
264:
265: (define_insn ""
266: [(set (match_operand:TI 0 "memory_operand" "=m")
267: (match_operand:TI 1 "memory_operand" "m"))]
268: ""
269: "movmd %1,%0,4")
270:
271: (define_insn "movdi"
272: [(set (match_operand:DI 0 "general_operand" "=&g<,*f,g")
273: (match_operand:DI 1 "general_operand" "gF,g,*f"))]
274: ""
275: "*
276: {
277: if (FP_REG_P (operands[0]))
278: {
279: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
280: return \"movl %1,%0\";
281: if (REG_P (operands[1]))
282: {
283: rtx xoperands[2];
284: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
285: output_asm_insn (\"movd %1,tos\", xoperands);
286: output_asm_insn (\"movd %1,tos\", operands);
287: return \"movl tos,%0\";
288: }
289: return \"movl %1,%0\";
290: }
291: else if (FP_REG_P (operands[1]))
292: {
293: if (REG_P (operands[0]))
294: {
295: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
296: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
297: return \"movd tos,%0\";
298: }
299: else
300: return \"movl %1,%0\";
301: }
302: return output_move_double (operands);
303: }")
304:
305: ;; This special case must precede movsi.
306: (define_insn ""
307: [(set (reg:SI 17)
308: (match_operand:SI 0 "general_operand" "rmn"))]
309: ""
310: "lprd sp,%0")
311:
312: (define_insn "movsi"
313: [(set (match_operand:SI 0 "general_operand" "=g<,*f,g")
314: (match_operand:SI 1 "general_operand" "gxy,g,*f"))]
315: ""
316: "*
317: {
318: if (FP_REG_P (operands[0]))
319: {
320: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
321: return \"movd %1,tos\;movf tos,%0\";
322: else
323: return \"movf %1,%0\";
324: }
325: else if (FP_REG_P (operands[1]))
326: {
327: if (REG_P (operands[0]))
328: return \"movf %1,tos\;movd tos,%0\";
329: return \"movf %1,%0\";
330: }
331: if (GET_CODE (operands[1]) == CONST_INT)
332: {
333: int i = INTVAL (operands[1]);
334: if (i <= 7 && i >= -8)
335: return \"movqd %1,%0\";
336: if (i < 0x4000 && i >= -0x4000 && ! TARGET_32532)
337: #if defined (GNX_V3) || defined (UTEK_ASM)
338: return \"addr %c1,%0\";
339: #else
340: return \"addr @%c1,%0\";
341: #endif
342: return \"movd %1,%0\";
343: }
344: else if (GET_CODE (operands[1]) == REG)
345: {
346: if (REGNO (operands[1]) < 16)
347: return \"movd %1,%0\";
348: else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM)
349: {
350: if (GET_CODE(operands[0]) == REG)
351: return \"sprd fp,%0\";
352: else
353: return \"addr 0(fp),%0\" ;
354: }
355: else if (REGNO (operands[1]) == STACK_POINTER_REGNUM)
356: {
357: if (GET_CODE(operands[0]) == REG)
358: return \"sprd sp,%0\";
359: else
360: return \"addr 0(sp),%0\" ;
361: }
362: else abort ();
363: }
364: else if (GET_CODE (operands[1]) == MEM)
365: return \"movd %1,%0\";
366: /* Check if this effective address can be
367: calculated faster by pulling it apart. */
368: if (REG_P (operands[0])
369: && GET_CODE (operands[1]) == MULT
370: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
371: && (INTVAL (XEXP (operands[1], 1)) == 2
372: || INTVAL (XEXP (operands[1], 1)) == 4))
373: {
374: rtx xoperands[3];
375: xoperands[0] = operands[0];
376: xoperands[1] = XEXP (operands[1], 0);
377: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
378: return output_shift_insn (xoperands);
379: }
380: return \"addr %a1,%0\";
381: }")
382:
383: (define_insn "movhi"
384: [(set (match_operand:HI 0 "general_operand" "=g<,*f,g")
385: (match_operand:HI 1 "general_operand" "g,g,*f"))]
386: ""
387: "*
388: {
389: if (GET_CODE (operands[1]) == CONST_INT)
390: {
391: short i = INTVAL (operands[1]);
392: if (i <= 7 && i >= -8)
393: {
394: if (INTVAL (operands[1]) > 7)
395: operands[1] =
396: gen_rtx (CONST_INT, VOIDmode, i);
397: return \"movqw %1,%0\";
398: }
399: return \"movw %1,%0\";
400: }
401: else if (FP_REG_P (operands[0]))
402: {
403: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
404: return \"movwf %1,tos\;movf tos,%0\";
405: else
406: return \"movwf %1,%0\";
407: }
408: else if (FP_REG_P (operands[1]))
409: {
410: if (REG_P (operands[0]))
411: return \"movf %1,tos\;movd tos,%0\";
412: return \"movf %1,%0\";
413: }
414: else
415: return \"movw %1,%0\";
416: }")
417:
418: (define_insn "movstricthi"
419: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
420: (match_operand:HI 1 "general_operand" "g"))]
421: ""
422: "*
423: {
424: if (GET_CODE (operands[1]) == CONST_INT
425: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
426: return \"movqw %1,%0\";
427: return \"movw %1,%0\";
428: }")
429:
430: (define_insn "movqi"
431: [(set (match_operand:QI 0 "general_operand" "=g<,*f,g")
432: (match_operand:QI 1 "general_operand" "g,g,*f"))]
433: ""
434: "*
435: { if (GET_CODE (operands[1]) == CONST_INT)
436: {
437: char char_val = (char)INTVAL (operands[1]);
438: if (char_val <= 7 && char_val >= -8)
439: {
440: if (INTVAL (operands[1]) > 7)
441: operands[1] =
442: gen_rtx (CONST_INT, VOIDmode, char_val);
443: return \"movqb %1,%0\";
444: }
445: return \"movb %1,%0\";
446: }
447: else if (FP_REG_P (operands[0]))
448: {
449: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
450: return \"movbf %1,tos\;movf tos,%0\";
451: else
452: return \"movbf %1,%0\";
453: }
454: else if (FP_REG_P (operands[1]))
455: {
456: if (REG_P (operands[0]))
457: return \"movf %1,tos\;movd tos,%0\";
458: return \"movf %1,%0\";
459: }
460: else
461: return \"movb %1,%0\";
462: }")
463:
464: (define_insn "movstrictqi"
465: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
466: (match_operand:QI 1 "general_operand" "g"))]
467: ""
468: "*
469: {
470: if (GET_CODE (operands[1]) == CONST_INT
471: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
472: return \"movqb %1,%0\";
473: return \"movb %1,%0\";
474: }")
475:
476: ;; The definition of this insn does not really explain what it does,
477: ;; but it should suffice
478: ;; that anything generated as this insn will be recognized as one
479: ;; and that it won't successfully combine with anything.
480: (define_insn "movstrsi"
481: [(set (match_operand:BLK 0 "general_operand" "=g")
482: (match_operand:BLK 1 "general_operand" "g"))
483: (use (match_operand:SI 2 "general_operand" "rmn"))
484: (clobber (reg:SI 0))
485: (clobber (reg:SI 1))
486: (clobber (reg:SI 2))]
487: ""
488: "*
489: {
490: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
491: abort ();
492: operands[0] = XEXP (operands[0], 0);
493: operands[1] = XEXP (operands[1], 0);
494: if (GET_CODE (operands[0]) == MEM)
495: if (GET_CODE (operands[1]) == MEM)
496: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
497: else
498: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
499: else if (GET_CODE (operands[1]) == MEM)
500: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
501: else
502: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
503:
504: #ifdef UTEK_ASM
505: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
506: {
507: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
508: if ((unsigned) INTVAL (operands[2]) <= 7)
509: return \"movqd %2,r0\;movsd $0\";
510: else
511: return \"movd %2,r0\;movsd $0\";
512: }
513: else
514: {
515: return \"movd %2,r0\;movsb $0\";
516: }
517: #else
518: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
519: {
520: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
521: if ((unsigned) INTVAL (operands[2]) <= 7)
522: return \"movqd %2,r0\;movsd\";
523: else
524: return \"movd %2,r0\;movsd\";
525: }
526: else
527: {
528: return \"movd %2,r0\;movsb\";
529: }
530: #endif
531: }")
532:
533: ;; Extension and truncation insns.
534: ;; Those for integer source operand
535: ;; are ordered widest source type first.
536:
537: (define_insn "truncsiqi2"
538: [(set (match_operand:QI 0 "general_operand" "=g<")
539: (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "rmn")))]
540: ""
541: "movb %1,%0")
542:
543: (define_insn "truncsihi2"
544: [(set (match_operand:HI 0 "general_operand" "=g<")
545: (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "rmn")))]
546: ""
547: "movw %1,%0")
548:
549: (define_insn "trunchiqi2"
550: [(set (match_operand:QI 0 "general_operand" "=g<")
551: (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
552: ""
553: "movb %1,%0")
554:
555: (define_insn "extendhisi2"
556: [(set (match_operand:SI 0 "general_operand" "=g<")
557: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
558: ""
559: "movxwd %1,%0")
560:
561: (define_insn "extendqihi2"
562: [(set (match_operand:HI 0 "general_operand" "=g<")
563: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
564: ""
565: "movxbw %1,%0")
566:
567: (define_insn "extendqisi2"
568: [(set (match_operand:SI 0 "general_operand" "=g<")
569: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
570: ""
571: "movxbd %1,%0")
572:
573: (define_insn "extendsfdf2"
574: [(set (match_operand:DF 0 "general_operand" "=fm<")
575: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
576: "TARGET_32081"
577: "movfl %1,%0")
578:
579: (define_insn "truncdfsf2"
580: [(set (match_operand:SF 0 "general_operand" "=fm<")
581: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
582: "TARGET_32081"
583: "movlf %1,%0")
584:
585: (define_insn "zero_extendhisi2"
586: [(set (match_operand:SI 0 "general_operand" "=g<")
587: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
588: ""
589: "movzwd %1,%0")
590:
591: (define_insn "zero_extendqihi2"
592: [(set (match_operand:HI 0 "general_operand" "=g<")
593: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
594: ""
595: "movzbw %1,%0")
596:
597: (define_insn "zero_extendqisi2"
598: [(set (match_operand:SI 0 "general_operand" "=g<")
599: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
600: ""
601: "movzbd %1,%0")
602:
603: ;; Fix-to-float conversion insns.
604: ;; Note that the ones that start with SImode come first.
605: ;; That is so that an operand that is a CONST_INT
606: ;; (and therefore lacks a specific machine mode).
607: ;; will be recognized as SImode (which is always valid)
608: ;; rather than as QImode or HImode.
609:
610: ;; Rumor has it that the National part does not correctly convert
611: ;; constant ints to floats. This conversion is therefore disabled.
612: ;; A register must be used to perform the conversion.
613:
614: (define_insn "floatsisf2"
615: [(set (match_operand:SF 0 "general_operand" "=fm<")
616: (float:SF (match_operand:SI 1 "general_operand" "rm")))]
617: "TARGET_32081"
618: "movdf %1,%0")
619:
620: (define_insn "floatsidf2"
621: [(set (match_operand:DF 0 "general_operand" "=fm<")
622: (float:DF (match_operand:SI 1 "general_operand" "rm")))]
623: "TARGET_32081"
624: "movdl %1,%0")
625:
626: (define_insn "floathisf2"
627: [(set (match_operand:SF 0 "general_operand" "=fm<")
628: (float:SF (match_operand:HI 1 "general_operand" "rm")))]
629: "TARGET_32081"
630: "movwf %1,%0")
631:
632: (define_insn "floathidf2"
633: [(set (match_operand:DF 0 "general_operand" "=fm<")
634: (float:DF (match_operand:HI 1 "general_operand" "rm")))]
635: "TARGET_32081"
636: "movwl %1,%0")
637:
638: (define_insn "floatqisf2"
639: [(set (match_operand:SF 0 "general_operand" "=fm<")
640: (float:SF (match_operand:QI 1 "general_operand" "rm")))]
641: "TARGET_32081"
642: "movbf %1,%0")
643:
644: ; Some assemblers warn that this insn doesn't work.
645: ; Maybe they know something we don't.
646: ;(define_insn "floatqidf2"
647: ; [(set (match_operand:DF 0 "general_operand" "=fm<")
648: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
649: ; "TARGET_32081"
650: ; "movbl %1,%0")
651:
652: ;; Float-to-fix conversion insns.
653: ;; The sequent compiler always generates "trunc" insns.
654:
655: (define_insn "fixsfqi2"
656: [(set (match_operand:QI 0 "general_operand" "=g<")
657: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
658: "TARGET_32081"
659: "truncfb %1,%0")
660:
661: (define_insn "fixsfhi2"
662: [(set (match_operand:HI 0 "general_operand" "=g<")
663: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
664: "TARGET_32081"
665: "truncfw %1,%0")
666:
667: (define_insn "fixsfsi2"
668: [(set (match_operand:SI 0 "general_operand" "=g<")
669: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
670: "TARGET_32081"
671: "truncfd %1,%0")
672:
673: (define_insn "fixdfqi2"
674: [(set (match_operand:QI 0 "general_operand" "=g<")
675: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
676: "TARGET_32081"
677: "trunclb %1,%0")
678:
679: (define_insn "fixdfhi2"
680: [(set (match_operand:HI 0 "general_operand" "=g<")
681: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
682: "TARGET_32081"
683: "trunclw %1,%0")
684:
685: (define_insn "fixdfsi2"
686: [(set (match_operand:SI 0 "general_operand" "=g<")
687: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
688: "TARGET_32081"
689: "truncld %1,%0")
690:
691: ;; Unsigned
692:
693: (define_insn "fixunssfqi2"
694: [(set (match_operand:QI 0 "general_operand" "=g<")
695: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
696: "TARGET_32081"
697: "truncfb %1,%0")
698:
699: (define_insn "fixunssfhi2"
700: [(set (match_operand:HI 0 "general_operand" "=g<")
701: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
702: "TARGET_32081"
703: "truncfw %1,%0")
704:
705: (define_insn "fixunssfsi2"
706: [(set (match_operand:SI 0 "general_operand" "=g<")
707: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
708: "TARGET_32081"
709: "truncfd %1,%0")
710:
711: (define_insn "fixunsdfqi2"
712: [(set (match_operand:QI 0 "general_operand" "=g<")
713: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
714: "TARGET_32081"
715: "trunclb %1,%0")
716:
717: (define_insn "fixunsdfhi2"
718: [(set (match_operand:HI 0 "general_operand" "=g<")
719: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
720: "TARGET_32081"
721: "trunclw %1,%0")
722:
723: (define_insn "fixunsdfsi2"
724: [(set (match_operand:SI 0 "general_operand" "=g<")
725: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
726: "TARGET_32081"
727: "truncld %1,%0")
728:
729: ;;; These are not yet used by GCC
730: (define_insn "fix_truncsfqi2"
731: [(set (match_operand:QI 0 "general_operand" "=g<")
732: (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
733: "TARGET_32081"
734: "truncfb %1,%0")
735:
736: (define_insn "fix_truncsfhi2"
737: [(set (match_operand:HI 0 "general_operand" "=g<")
738: (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
739: "TARGET_32081"
740: "truncfw %1,%0")
741:
742: (define_insn "fix_truncsfsi2"
743: [(set (match_operand:SI 0 "general_operand" "=g<")
744: (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
745: "TARGET_32081"
746: "truncfd %1,%0")
747:
748: (define_insn "fix_truncdfqi2"
749: [(set (match_operand:QI 0 "general_operand" "=g<")
750: (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
751: "TARGET_32081"
752: "trunclb %1,%0")
753:
754: (define_insn "fix_truncdfhi2"
755: [(set (match_operand:HI 0 "general_operand" "=g<")
756: (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
757: "TARGET_32081"
758: "trunclw %1,%0")
759:
760: (define_insn "fix_truncdfsi2"
761: [(set (match_operand:SI 0 "general_operand" "=g<")
762: (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
763: "TARGET_32081"
764: "truncld %1,%0")
765:
766: ;;- All kinds of add instructions.
767:
768: (define_insn "adddf3"
769: [(set (match_operand:DF 0 "general_operand" "=fm")
770: (plus:DF (match_operand:DF 1 "general_operand" "%0")
771: (match_operand:DF 2 "general_operand" "fmF")))]
772: "TARGET_32081"
773: "addl %2,%0")
774:
775:
776: (define_insn "addsf3"
777: [(set (match_operand:SF 0 "general_operand" "=fm")
778: (plus:SF (match_operand:SF 1 "general_operand" "%0")
779: (match_operand:SF 2 "general_operand" "fmF")))]
780: "TARGET_32081"
781: "addf %2,%0")
782:
783: (define_insn ""
784: [(set (reg:SI 17)
785: (plus:SI (reg:SI 17)
786: (match_operand:SI 0 "immediate_operand" "i")))]
787: "GET_CODE (operands[0]) == CONST_INT"
788: "*
789: {
790: #ifndef SEQUENT_ADJUST_STACK
791: if (TARGET_32532)
792: if (INTVAL (operands[0]) == 8)
793: return \"cmpd tos,tos\";
794: if (TARGET_32532 || TARGET_32332)
795: if (INTVAL (operands[0]) == 4)
796: return \"cmpqd %$0,tos\";
797: #endif
798: if (! TARGET_32532)
799: {
800: if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64)
801: return \"adjspb %$%n0\";
802: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
803: return \"adjspw %$%n0\";
804: }
805: return \"adjspd %$%n0\";
806: }")
807:
808: (define_insn ""
809: [(set (match_operand:SI 0 "general_operand" "=g<")
810: (plus:SI (reg:SI 16)
811: (match_operand:SI 1 "immediate_operand" "i")))]
812: "GET_CODE (operands[1]) == CONST_INT"
813: "addr %c1(fp),%0")
814:
815: (define_insn ""
816: [(set (match_operand:SI 0 "general_operand" "=g<")
817: (plus:SI (reg:SI 17)
818: (match_operand:SI 1 "immediate_operand" "i")))]
819: "GET_CODE (operands[1]) == CONST_INT"
820: "addr %c1(sp),%0")
821:
822: (define_insn "addsi3"
823: [(set (match_operand:SI 0 "general_operand" "=g,=g<")
824: (plus:SI (match_operand:SI 1 "general_operand" "%0,%r")
825: (match_operand:SI 2 "general_operand" "rmn,n")))]
826: ""
827: "*
828: {
829: if (which_alternative == 1)
830: {
831: int i = INTVAL (operands[2]);
832: if ( i < 0x40000000 && i >= -0x40000000 )
833: return \"addr %c2(%1),%0\";
834: else
835: return \"movd %1,%0\;addd %2,%0\";
836: }
837: if (GET_CODE (operands[2]) == CONST_INT)
838: {
839: int i = INTVAL (operands[2]);
840:
841: if (i <= 7 && i >= -8)
842: return \"addqd %2,%0\";
843: else if (GET_CODE (operands[0]) == REG
844: && i < 0x4000 && i >= -0x4000 && ! TARGET_32532)
845: return \"addr %c2(%0),%0\";
846: }
847: return \"addd %2,%0\";
848: }")
849:
850: (define_insn "addhi3"
851: [(set (match_operand:HI 0 "general_operand" "=g")
852: (plus:HI (match_operand:HI 1 "general_operand" "%0")
853: (match_operand:HI 2 "general_operand" "g")))]
854: ""
855: "*
856: { if (GET_CODE (operands[2]) == CONST_INT)
857: {
858: int i = INTVAL (operands[2]);
859: if (i <= 7 && i >= -8)
860: return \"addqw %2,%0\";
861: }
862: return \"addw %2,%0\";
863: }")
864:
865: (define_insn ""
866: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
867: (plus:HI (match_operand:HI 1 "general_operand" "0")
868: (match_operand:HI 2 "general_operand" "g")))]
869: ""
870: "*
871: {
872: if (GET_CODE (operands[1]) == CONST_INT
873: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
874: return \"addqw %1,%0\";
875: return \"addw %1,%0\";
876: }")
877:
878: (define_insn "addqi3"
879: [(set (match_operand:QI 0 "general_operand" "=g")
880: (plus:QI (match_operand:QI 1 "general_operand" "%0")
881: (match_operand:QI 2 "general_operand" "g")))]
882: ""
883: "*
884: { if (GET_CODE (operands[2]) == CONST_INT)
885: {
886: int i = INTVAL (operands[2]);
887: if (i <= 7 && i >= -8)
888: return \"addqb %2,%0\";
889: }
890: return \"addb %2,%0\";
891: }")
892:
893: (define_insn ""
894: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
895: (plus:QI (match_operand:QI 1 "general_operand" "0")
896: (match_operand:QI 2 "general_operand" "g")))]
897: ""
898: "*
899: {
900: if (GET_CODE (operands[1]) == CONST_INT
901: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
902: return \"addqb %1,%0\";
903: return \"addb %1,%0\";
904: }")
905:
906: ;;- All kinds of subtract instructions.
907:
908: (define_insn "subdf3"
909: [(set (match_operand:DF 0 "general_operand" "=fm")
910: (minus:DF (match_operand:DF 1 "general_operand" "0")
911: (match_operand:DF 2 "general_operand" "fmF")))]
912: "TARGET_32081"
913: "subl %2,%0")
914:
915: (define_insn "subsf3"
916: [(set (match_operand:SF 0 "general_operand" "=fm")
917: (minus:SF (match_operand:SF 1 "general_operand" "0")
918: (match_operand:SF 2 "general_operand" "fmF")))]
919: "TARGET_32081"
920: "subf %2,%0")
921:
922: (define_insn ""
923: [(set (reg:SI 17)
924: (minus:SI (reg:SI 17)
925: (match_operand:SI 0 "immediate_operand" "i")))]
926: "GET_CODE (operands[0]) == CONST_INT"
927: "*
928: {
929: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64
930: && INTVAL(operands[0]) > -64 && ! TARGET_32532)
931: return \"adjspb %0\";
932: return \"adjspd %0\";
933: }")
934:
935: (define_insn "subsi3"
936: [(set (match_operand:SI 0 "general_operand" "=g")
937: (minus:SI (match_operand:SI 1 "general_operand" "0")
938: (match_operand:SI 2 "general_operand" "rmn")))]
939: ""
940: "*
941: { if (GET_CODE (operands[2]) == CONST_INT)
942: {
943: int i = INTVAL (operands[2]);
944:
945: if (i <= 8 && i >= -7)
946: return \"addqd %$%n2,%0\";
947: }
948: return \"subd %2,%0\";
949: }")
950:
951: (define_insn "subhi3"
952: [(set (match_operand:HI 0 "general_operand" "=g")
953: (minus:HI (match_operand:HI 1 "general_operand" "0")
954: (match_operand:HI 2 "general_operand" "g")))]
955: ""
956: "*
957: { if (GET_CODE (operands[2]) == CONST_INT)
958: {
959: int i = INTVAL (operands[2]);
960:
961: if (i <= 8 && i >= -7)
962: return \"addqw %$%n2,%0\";
963: }
964: return \"subw %2,%0\";
965: }")
966:
967: (define_insn ""
968: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
969: (minus:HI (match_operand:HI 1 "general_operand" "0")
970: (match_operand:HI 2 "general_operand" "g")))]
971: ""
972: "*
973: {
974: if (GET_CODE (operands[1]) == CONST_INT
975: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
976: return \"addqw %$%n1,%0\";
977: return \"subw %1,%0\";
978: }")
979:
980: (define_insn "subqi3"
981: [(set (match_operand:QI 0 "general_operand" "=g")
982: (minus:QI (match_operand:QI 1 "general_operand" "0")
983: (match_operand:QI 2 "general_operand" "g")))]
984: ""
985: "*
986: { if (GET_CODE (operands[2]) == CONST_INT)
987: {
988: int i = INTVAL (operands[2]);
989:
990: if (i <= 8 && i >= -7)
991: return \"addqb %$%n2,%0\";
992: }
993: return \"subb %2,%0\";
994: }")
995:
996: (define_insn ""
997: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
998: (minus:QI (match_operand:QI 1 "general_operand" "0")
999: (match_operand:QI 2 "general_operand" "g")))]
1000: ""
1001: "*
1002: {
1003: if (GET_CODE (operands[1]) == CONST_INT
1004: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1005: return \"addqb %$%n1,%0\";
1006: return \"subb %1,%0\";
1007: }")
1008:
1009: ;;- Multiply instructions.
1010:
1011: (define_insn "muldf3"
1012: [(set (match_operand:DF 0 "general_operand" "=fm")
1013: (mult:DF (match_operand:DF 1 "general_operand" "%0")
1014: (match_operand:DF 2 "general_operand" "fmF")))]
1015: "TARGET_32081"
1016: "mull %2,%0")
1017:
1018: (define_insn "mulsf3"
1019: [(set (match_operand:SF 0 "general_operand" "=fm")
1020: (mult:SF (match_operand:SF 1 "general_operand" "%0")
1021: (match_operand:SF 2 "general_operand" "fmF")))]
1022: "TARGET_32081"
1023: "mulf %2,%0")
1024:
1025: (define_insn "mulsi3"
1026: [(set (match_operand:SI 0 "general_operand" "=g")
1027: (mult:SI (match_operand:SI 1 "general_operand" "%0")
1028: (match_operand:SI 2 "general_operand" "rmn")))]
1029: ""
1030: "muld %2,%0")
1031:
1032: (define_insn "mulhi3"
1033: [(set (match_operand:HI 0 "general_operand" "=g")
1034: (mult:HI (match_operand:HI 1 "general_operand" "%0")
1035: (match_operand:HI 2 "general_operand" "g")))]
1036: ""
1037: "mulw %2,%0")
1038:
1039: (define_insn "mulqi3"
1040: [(set (match_operand:QI 0 "general_operand" "=g")
1041: (mult:QI (match_operand:QI 1 "general_operand" "%0")
1042: (match_operand:QI 2 "general_operand" "g")))]
1043: ""
1044: "mulb %2,%0")
1045:
1046: (define_insn "umulsidi3"
1047: [(set (match_operand:DI 0 "general_operand" "=g")
1048: (mult:DI (zero_extend:DI
1049: (match_operand:SI 1 "nonimmediate_operand" "0"))
1050: (zero_extend:DI
1051: (match_operand:SI 2 "nonimmediate_operand" "rmn"))))]
1052: ""
1053: "meid %2,%0")
1054:
1055: ;;- Divide instructions.
1056:
1057: (define_insn "divdf3"
1058: [(set (match_operand:DF 0 "general_operand" "=fm")
1059: (div:DF (match_operand:DF 1 "general_operand" "0")
1060: (match_operand:DF 2 "general_operand" "fmF")))]
1061: "TARGET_32081"
1062: "divl %2,%0")
1063:
1064: (define_insn "divsf3"
1065: [(set (match_operand:SF 0 "general_operand" "=fm")
1066: (div:SF (match_operand:SF 1 "general_operand" "0")
1067: (match_operand:SF 2 "general_operand" "fmF")))]
1068: "TARGET_32081"
1069: "divf %2,%0")
1070:
1071: (define_insn "divsi3"
1072: [(set (match_operand:SI 0 "general_operand" "=g")
1073: (div:SI (match_operand:SI 1 "general_operand" "0")
1074: (match_operand:SI 2 "general_operand" "rmn")))]
1075: ""
1076: "quod %2,%0")
1077:
1078: (define_insn "divhi3"
1079: [(set (match_operand:HI 0 "general_operand" "=g")
1080: (div:HI (match_operand:HI 1 "general_operand" "0")
1081: (match_operand:HI 2 "general_operand" "g")))]
1082: ""
1083: "quow %2,%0")
1084:
1085: (define_insn "divqi3"
1086: [(set (match_operand:QI 0 "general_operand" "=g")
1087: (div:QI (match_operand:QI 1 "general_operand" "0")
1088: (match_operand:QI 2 "general_operand" "g")))]
1089: ""
1090: "quob %2,%0")
1091:
1092: (define_insn "udivsi3"
1093: [(set (match_operand:SI 0 "register_operand" "=r")
1094: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1095: (match_operand:SI 2 "general_operand" "rmn")))]
1096: ""
1097: "*
1098: {
1099: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1100: return \"deid %2,%0\;movd %1,%0\";
1101: }")
1102:
1103: (define_insn "udivhi3"
1104: [(set (match_operand:HI 0 "register_operand" "=r")
1105: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1106: (match_operand:HI 2 "general_operand" "g")))]
1107: ""
1108: "*
1109: {
1110: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
1111: return \"deiw %2,%0\;movw %1,%0\";
1112: }")
1113:
1114: (define_insn "udivqi3"
1115: [(set (match_operand:QI 0 "register_operand" "=r")
1116: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1117: (match_operand:QI 2 "general_operand" "g")))]
1118: ""
1119: "*
1120: {
1121: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
1122: return \"deib %2,%0\;movb %1,%0\";
1123: }")
1124:
1125: ;; Remainder instructions.
1126:
1127: (define_insn "modsi3"
1128: [(set (match_operand:SI 0 "general_operand" "=g")
1129: (mod:SI (match_operand:SI 1 "general_operand" "0")
1130: (match_operand:SI 2 "general_operand" "rmn")))]
1131: ""
1132: "remd %2,%0")
1133:
1134: (define_insn "modhi3"
1135: [(set (match_operand:HI 0 "general_operand" "=g")
1136: (mod:HI (match_operand:HI 1 "general_operand" "0")
1137: (match_operand:HI 2 "general_operand" "g")))]
1138: ""
1139: "remw %2,%0")
1140:
1141: (define_insn "modqi3"
1142: [(set (match_operand:QI 0 "general_operand" "=g")
1143: (mod:QI (match_operand:QI 1 "general_operand" "0")
1144: (match_operand:QI 2 "general_operand" "g")))]
1145: ""
1146: "remb %2,%0")
1147:
1148: (define_insn "umodsi3"
1149: [(set (match_operand:SI 0 "register_operand" "=r")
1150: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1151: (match_operand:SI 2 "general_operand" "rmn")))]
1152: ""
1153: "deid %2,%0")
1154:
1155: (define_insn "umodhi3"
1156: [(set (match_operand:HI 0 "register_operand" "=r")
1157: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1158: (match_operand:HI 2 "general_operand" "g")))]
1159: ""
1160: "deiw %2,%0")
1161:
1162: (define_insn "umodqi3"
1163: [(set (match_operand:QI 0 "register_operand" "=r")
1164: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1165: (match_operand:QI 2 "general_operand" "g")))]
1166: ""
1167: "deib %2,%0")
1168:
1169: ; This isn't be usable in its current form.
1170: ;(define_insn "udivmoddisi4"
1171: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1172: ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1173: ; (match_operand:SI 2 "general_operand" "rmn")))
1174: ; (set (subreg:SI (match_dup 0) 0)
1175: ; (umod:SI (match_dup 1) (match_dup 2)))]
1176: ; ""
1177: ; "deid %2,%0")
1178:
1179: ;;- Logical Instructions: AND
1180:
1181: (define_insn "andsi3"
1182: [(set (match_operand:SI 0 "general_operand" "=g")
1183: (and:SI (match_operand:SI 1 "general_operand" "%0")
1184: (match_operand:SI 2 "general_operand" "rmn")))]
1185: ""
1186: "*
1187: {
1188: if (GET_CODE (operands[2]) == CONST_INT)
1189: {
1190: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1191: {
1192: if (INTVAL (operands[2]) == 0xffffff00)
1193: return \"movqb %$0,%0\";
1194: else
1195: {
1196: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1197: INTVAL (operands[2]) & 0xff);
1198: return \"andb %2,%0\";
1199: }
1200: }
1201: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1202: {
1203: if (INTVAL (operands[2]) == 0xffff0000)
1204: return \"movqw %$0,%0\";
1205: else
1206: {
1207: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1208: INTVAL (operands[2]) & 0xffff);
1209: return \"andw %2,%0\";
1210: }
1211: }
1212: }
1213: return \"andd %2,%0\";
1214: }")
1215:
1216: (define_insn "andhi3"
1217: [(set (match_operand:HI 0 "general_operand" "=g")
1218: (and:HI (match_operand:HI 1 "general_operand" "%0")
1219: (match_operand:HI 2 "general_operand" "g")))]
1220: ""
1221: "*
1222: {
1223: if (GET_CODE (operands[2]) == CONST_INT
1224: && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1225: {
1226: if (INTVAL (operands[2]) == 0xffffff00)
1227: return \"movqb %$0,%0\";
1228: else
1229: {
1230: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1231: INTVAL (operands[2]) & 0xff);
1232: return \"andb %2,%0\";
1233: }
1234: }
1235: return \"andw %2,%0\";
1236: }")
1237:
1238: (define_insn "andqi3"
1239: [(set (match_operand:QI 0 "general_operand" "=g")
1240: (and:QI (match_operand:QI 1 "general_operand" "%0")
1241: (match_operand:QI 2 "general_operand" "g")))]
1242: ""
1243: "andb %2,%0")
1244:
1245: (define_insn ""
1246: [(set (match_operand:SI 0 "general_operand" "=g")
1247: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1248: (match_operand:SI 2 "general_operand" "0")))]
1249: ""
1250: "bicd %1,%0")
1251:
1252: (define_insn ""
1253: [(set (match_operand:HI 0 "general_operand" "=g")
1254: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1255: (match_operand:HI 2 "general_operand" "0")))]
1256: ""
1257: "bicw %1,%0")
1258:
1259: (define_insn ""
1260: [(set (match_operand:QI 0 "general_operand" "=g")
1261: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1262: (match_operand:QI 2 "general_operand" "0")))]
1263: ""
1264: "bicb %1,%0")
1265:
1266: ;;- Bit set instructions.
1267:
1268: (define_insn "iorsi3"
1269: [(set (match_operand:SI 0 "general_operand" "=g")
1270: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1271: (match_operand:SI 2 "general_operand" "rmn")))]
1272: ""
1273: "*
1274: {
1275: if (GET_CODE (operands[2]) == CONST_INT) {
1276: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1277: return \"orb %2,%0\";
1278: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1279: return \"orw %2,%0\";
1280: }
1281: return \"ord %2,%0\";
1282: }")
1283:
1284: (define_insn "iorhi3"
1285: [(set (match_operand:HI 0 "general_operand" "=g")
1286: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1287: (match_operand:HI 2 "general_operand" "g")))]
1288: ""
1289: "*
1290: {
1291: if (GET_CODE(operands[2]) == CONST_INT &&
1292: (INTVAL(operands[2]) & 0xffffff00) == 0)
1293: return \"orb %2,%0\";
1294: return \"orw %2,%0\";
1295: }")
1296:
1297: (define_insn "iorqi3"
1298: [(set (match_operand:QI 0 "general_operand" "=g")
1299: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1300: (match_operand:QI 2 "general_operand" "g")))]
1301: ""
1302: "orb %2,%0")
1303:
1304: ;;- xor instructions.
1305:
1306: (define_insn "xorsi3"
1307: [(set (match_operand:SI 0 "general_operand" "=g")
1308: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1309: (match_operand:SI 2 "general_operand" "rmn")))]
1310: ""
1311: "*
1312: {
1313: if (GET_CODE (operands[2]) == CONST_INT) {
1314: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1315: return \"xorb %2,%0\";
1316: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1317: return \"xorw %2,%0\";
1318: }
1319: return \"xord %2,%0\";
1320: }")
1321:
1322: (define_insn "xorhi3"
1323: [(set (match_operand:HI 0 "general_operand" "=g")
1324: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1325: (match_operand:HI 2 "general_operand" "g")))]
1326: ""
1327: "*
1328: {
1329: if (GET_CODE(operands[2]) == CONST_INT &&
1330: (INTVAL(operands[2]) & 0xffffff00) == 0)
1331: return \"xorb %2,%0\";
1332: return \"xorw %2,%0\";
1333: }")
1334:
1335: (define_insn "xorqi3"
1336: [(set (match_operand:QI 0 "general_operand" "=g")
1337: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1338: (match_operand:QI 2 "general_operand" "g")))]
1339: ""
1340: "xorb %2,%0")
1341:
1342: (define_insn "negdf2"
1343: [(set (match_operand:DF 0 "general_operand" "=fm<")
1344: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1345: "TARGET_32081"
1346: "negl %1,%0")
1347:
1348: (define_insn "negsf2"
1349: [(set (match_operand:SF 0 "general_operand" "=fm<")
1350: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1351: "TARGET_32081"
1352: "negf %1,%0")
1353:
1354: (define_insn "negsi2"
1355: [(set (match_operand:SI 0 "general_operand" "=g<")
1356: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1357: ""
1358: "negd %1,%0")
1359:
1360: (define_insn "neghi2"
1361: [(set (match_operand:HI 0 "general_operand" "=g<")
1362: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1363: ""
1364: "negw %1,%0")
1365:
1366: (define_insn "negqi2"
1367: [(set (match_operand:QI 0 "general_operand" "=g<")
1368: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1369: ""
1370: "negb %1,%0")
1371:
1372: (define_insn "one_cmplsi2"
1373: [(set (match_operand:SI 0 "general_operand" "=g<")
1374: (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1375: ""
1376: "comd %1,%0")
1377:
1378: (define_insn "one_cmplhi2"
1379: [(set (match_operand:HI 0 "general_operand" "=g<")
1380: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1381: ""
1382: "comw %1,%0")
1383:
1384: (define_insn "one_cmplqi2"
1385: [(set (match_operand:QI 0 "general_operand" "=g<")
1386: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1387: ""
1388: "comb %1,%0")
1389:
1390: ;; arithmetic left and right shift operations
1391: ;; on the 32532 we will always use lshd for arithmetic left shifts,
1392: ;; because it is three times faster. Broken programs which
1393: ;; use negative shift counts are probably broken differently
1394: ;; than elsewhere.
1395:
1396: ;; alternative 0 never matches on the 32532
1397: (define_insn "ashlsi3"
1398: [(set (match_operand:SI 0 "general_operand" "=g,g")
1399: (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1400: (match_operand:SI 2 "general_operand" "I,rmn")))]
1401: ""
1402: "*
1403: { if (TARGET_32532)
1404: return \"lshd %2,%0\";
1405: else
1406: return output_shift_insn (operands);
1407: }")
1408:
1409: (define_insn "ashlhi3"
1410: [(set (match_operand:HI 0 "general_operand" "=g")
1411: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1412: (match_operand:SI 2 "general_operand" "rmn")))]
1413: ""
1414: "*
1415: { if (GET_CODE (operands[2]) == CONST_INT)
1416: {
1417: if (INTVAL (operands[2]) == 1)
1418: return \"addw %0,%0\";
1419: else if (INTVAL (operands[2]) == 2 && !TARGET_32532)
1420: return \"addw %0,%0\;addw %0,%0\";
1421: }
1422: if (TARGET_32532)
1423: return \"lshw %2,%0\";
1424: else
1425: return \"ashw %2,%0\";
1426: }")
1427:
1428: (define_insn "ashlqi3"
1429: [(set (match_operand:QI 0 "general_operand" "=g")
1430: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1431: (match_operand:SI 2 "general_operand" "rmn")))]
1432: ""
1433: "*
1434: { if (GET_CODE (operands[2]) == CONST_INT)
1435: {
1436: if (INTVAL (operands[2]) == 1)
1437: return \"addb %0,%0\";
1438: else if (INTVAL (operands[2]) == 2 && !TARGET_32532)
1439: return \"addb %0,%0\;addb %0,%0\";
1440: }
1441: if (TARGET_32532)
1442: return \"lshb %2,%0\";
1443: else
1444: return \"ashb %2,%0\";
1445: }")
1446:
1447: ;; Arithmetic right shift on the 32k works by negating the shift count.
1448: (define_expand "ashrsi3"
1449: [(set (match_operand:SI 0 "general_operand" "=g")
1450: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1451: (match_operand:SI 2 "general_operand" "g")))]
1452: ""
1453: "
1454: {
1455: if (GET_CODE (operands[2]) != CONST_INT)
1456: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1457: }")
1458:
1459: (define_insn ""
1460: [(set (match_operand:SI 0 "general_operand" "=g")
1461: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1462: (match_operand:SI 2 "immediate_operand" "i")))]
1463: ""
1464: "ashd %$%n2,%0")
1465:
1466: (define_insn ""
1467: [(set (match_operand:SI 0 "general_operand" "=g")
1468: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1469: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1470: ""
1471: "ashd %2,%0")
1472:
1473: (define_expand "ashrhi3"
1474: [(set (match_operand:HI 0 "general_operand" "=g")
1475: (ashiftrt:HI (match_operand:HI 1 "general_operand" "g")
1476: (match_operand:SI 2 "general_operand" "g")))]
1477: ""
1478: "
1479: {
1480: if (GET_CODE (operands[2]) != CONST_INT)
1481: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1482: }")
1483:
1484: (define_insn ""
1485: [(set (match_operand:HI 0 "general_operand" "=g")
1486: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1487: (match_operand:SI 2 "immediate_operand" "i")))]
1488: ""
1489: "ashw %$%n2,%0")
1490:
1491: (define_insn ""
1492: [(set (match_operand:HI 0 "general_operand" "=g")
1493: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1494: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1495: ""
1496: "ashw %2,%0")
1497:
1498: (define_expand "ashrqi3"
1499: [(set (match_operand:QI 0 "general_operand" "=g")
1500: (ashiftrt:QI (match_operand:QI 1 "general_operand" "g")
1501: (match_operand:SI 2 "general_operand" "g")))]
1502: ""
1503: "
1504: {
1505: if (GET_CODE (operands[2]) != CONST_INT)
1506: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1507: }")
1508:
1509: (define_insn ""
1510: [(set (match_operand:QI 0 "general_operand" "=g")
1511: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1512: (match_operand:SI 2 "immediate_operand" "i")))]
1513: ""
1514: "ashb %$%n2,%0")
1515:
1516: (define_insn ""
1517: [(set (match_operand:QI 0 "general_operand" "=g")
1518: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1519: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1520: ""
1521: "ashb %2,%0")
1522:
1523: ;; logical shift instructions
1524:
1525: (define_insn "lshlsi3"
1526: [(set (match_operand:SI 0 "general_operand" "=g")
1527: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1528: (match_operand:SI 2 "general_operand" "rmn")))]
1529: ""
1530: "lshd %2,%0")
1531:
1532: (define_insn "lshlhi3"
1533: [(set (match_operand:HI 0 "general_operand" "=g")
1534: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1535: (match_operand:SI 2 "general_operand" "rmn")))]
1536: ""
1537: "lshw %2,%0")
1538:
1539: (define_insn "lshlqi3"
1540: [(set (match_operand:QI 0 "general_operand" "=g")
1541: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1542: (match_operand:SI 2 "general_operand" "rmn")))]
1543: ""
1544: "lshb %2,%0")
1545:
1546: ;; Logical right shift on the 32k works by negating the shift count.
1547: (define_expand "lshrsi3"
1548: [(set (match_operand:SI 0 "general_operand" "=g")
1549: (lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
1550: (match_operand:SI 2 "general_operand" "g")))]
1551: ""
1552: "
1553: {
1554: if (GET_CODE (operands[2]) != CONST_INT)
1555: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1556: }")
1557:
1558: (define_insn ""
1559: [(set (match_operand:SI 0 "general_operand" "=g")
1560: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1561: (match_operand:SI 2 "immediate_operand" "i")))]
1562: ""
1563: "lshd %$%n2,%0")
1564:
1565: (define_insn ""
1566: [(set (match_operand:SI 0 "general_operand" "=g")
1567: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1568: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1569: ""
1570: "lshd %2,%0")
1571:
1572: (define_expand "lshrhi3"
1573: [(set (match_operand:HI 0 "general_operand" "=g")
1574: (lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
1575: (match_operand:SI 2 "general_operand" "g")))]
1576: ""
1577: "
1578: {
1579: if (GET_CODE (operands[2]) != CONST_INT)
1580: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1581: }")
1582:
1583: (define_insn ""
1584: [(set (match_operand:HI 0 "general_operand" "=g")
1585: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1586: (match_operand:SI 2 "immediate_operand" "i")))]
1587: ""
1588: "lshw %$%n2,%0")
1589:
1590: (define_insn ""
1591: [(set (match_operand:HI 0 "general_operand" "=g")
1592: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1593: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1594: ""
1595: "lshw %2,%0")
1596:
1597: (define_expand "lshrqi3"
1598: [(set (match_operand:QI 0 "general_operand" "=g")
1599: (lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
1600: (match_operand:SI 2 "general_operand" "g")))]
1601: ""
1602: "
1603: {
1604: if (GET_CODE (operands[2]) != CONST_INT)
1605: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1606: }")
1607:
1608: (define_insn ""
1609: [(set (match_operand:QI 0 "general_operand" "=g")
1610: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1611: (match_operand:SI 2 "immediate_operand" "i")))]
1612: ""
1613: "lshb %$%n2,%0")
1614:
1615: (define_insn ""
1616: [(set (match_operand:QI 0 "general_operand" "=g")
1617: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1618: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1619: ""
1620: "lshb %2,%0")
1621:
1622: ;; Rotate instructions
1623:
1624: (define_insn "rotlsi3"
1625: [(set (match_operand:SI 0 "general_operand" "=g")
1626: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1627: (match_operand:SI 2 "general_operand" "rmn")))]
1628: ""
1629: "rotd %2,%0")
1630:
1631: (define_insn "rotlhi3"
1632: [(set (match_operand:HI 0 "general_operand" "=g")
1633: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1634: (match_operand:SI 2 "general_operand" "rmn")))]
1635: ""
1636: "rotw %2,%0")
1637:
1638: (define_insn "rotlqi3"
1639: [(set (match_operand:QI 0 "general_operand" "=g")
1640: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1641: (match_operand:SI 2 "general_operand" "rmn")))]
1642: ""
1643: "rotb %2,%0")
1644:
1645: ;; Right rotate on the 32k works by negating the shift count.
1646: (define_expand "rotrsi3"
1647: [(set (match_operand:SI 0 "general_operand" "=g")
1648: (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1649: (match_operand:SI 2 "general_operand" "g")))]
1650: ""
1651: "
1652: {
1653: if (GET_CODE (operands[2]) != CONST_INT)
1654: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1655: }")
1656:
1657: (define_insn ""
1658: [(set (match_operand:SI 0 "general_operand" "=g")
1659: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1660: (match_operand:SI 2 "immediate_operand" "i")))]
1661: ""
1662: "rotd %$%n2,%0")
1663:
1664: (define_insn ""
1665: [(set (match_operand:SI 0 "general_operand" "=g")
1666: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1667: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1668: ""
1669: "rotd %2,%0")
1670:
1671: (define_expand "rotrhi3"
1672: [(set (match_operand:HI 0 "general_operand" "=g")
1673: (rotatert:HI (match_operand:HI 1 "general_operand" "g")
1674: (match_operand:SI 2 "general_operand" "g")))]
1675: ""
1676: "
1677: {
1678: if (GET_CODE (operands[2]) != CONST_INT)
1679: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1680: }")
1681:
1682: (define_insn ""
1683: [(set (match_operand:HI 0 "general_operand" "=g")
1684: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1685: (match_operand:SI 2 "immediate_operand" "i")))]
1686: ""
1687: "rotw %$%n2,%0")
1688:
1689: (define_insn ""
1690: [(set (match_operand:HI 0 "general_operand" "=g")
1691: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1692: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1693: ""
1694: "rotw %2,%0")
1695:
1696: (define_expand "rotrqi3"
1697: [(set (match_operand:QI 0 "general_operand" "=g")
1698: (rotatert:QI (match_operand:QI 1 "general_operand" "g")
1699: (match_operand:SI 2 "general_operand" "g")))]
1700: ""
1701: "
1702: {
1703: if (GET_CODE (operands[2]) != CONST_INT)
1704: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1705: }")
1706:
1707: (define_insn ""
1708: [(set (match_operand:QI 0 "general_operand" "=g")
1709: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1710: (match_operand:SI 2 "immediate_operand" "i")))]
1711: ""
1712: "rotb %$%n2,%0")
1713:
1714: (define_insn ""
1715: [(set (match_operand:QI 0 "general_operand" "=g")
1716: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1717: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1718: ""
1719: "rotb %2,%0")
1720:
1721: ;;- load or push effective address
1722: ;; These come after the move, add, and multiply patterns
1723: ;; because we don't want pushl $1 turned into pushad 1.
1724:
1725: (define_insn ""
1726: [(set (match_operand:SI 0 "general_operand" "=g<")
1727: (match_operand:QI 1 "address_operand" "p"))]
1728: ""
1729: "*
1730: {
1731: if (REG_P (operands[0])
1732: && GET_CODE (operands[1]) == MULT
1733: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1734: && (INTVAL (XEXP (operands[1], 1)) == 2
1735: || INTVAL (XEXP (operands[1], 1)) == 4))
1736: {
1737: rtx xoperands[3];
1738: xoperands[0] = operands[0];
1739: xoperands[1] = XEXP (operands[1], 0);
1740: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
1741: return output_shift_insn (xoperands);
1742: }
1743: return \"addr %a1,%0\";
1744: }")
1745:
1746: ;;; Index insns. These are about the same speed as multiply-add counterparts.
1747: ;;; but slower then using power-of-2 shifts if we can use them
1748: ;
1749: ;(define_insn ""
1750: ; [(set (match_operand:SI 0 "register_operand" "=r")
1751: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1752: ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1753: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1754: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1755: ; "indexd %0,%3,%1")
1756: ;
1757: ;(define_insn ""
1758: ; [(set (match_operand:SI 0 "register_operand" "=r")
1759: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1760: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1761: ; (match_operand:SI 3 "general_operand" "rmn")))]
1762: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1763: ; "indexd %0,%2,%3")
1764:
1765: ;; Set, Clear, and Invert bit
1766:
1767: (define_insn ""
1768: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
1769: (const_int 1)
1770: (match_operand:SI 1 "general_operand" "rmn"))
1771: (const_int 1))]
1772: ""
1773: "sbitd %1,%0")
1774:
1775: (define_insn ""
1776: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
1777: (const_int 1)
1778: (match_operand:SI 1 "general_operand" "rmn"))
1779: (const_int 0))]
1780: ""
1781: "cbitd %1,%0")
1782:
1783: (define_insn ""
1784: [(set (match_operand:SI 0 "general_operand" "+g")
1785: (xor:SI (ashift:SI (const_int 1)
1786: (match_operand:SI 1 "general_operand" "rmn"))
1787: (match_dup 0)))]
1788: ""
1789: "ibitd %1,%0")
1790:
1791: (define_insn ""
1792: [(set (match_operand:QI 0 "general_operand" "=g")
1793: (xor:QI (subreg:QI
1794: (ashift:SI (const_int 1)
1795: (match_operand:QI 1 "general_operand" "rmn")) 0)
1796: (match_dup 0)))]
1797: ""
1798: "ibitb %1,%0")
1799:
1800: ;; Recognize jbs and jbc instructions.
1801:
1802: (define_insn ""
1803: [(set (cc0)
1804: (zero_extract (match_operand:SI 0 "general_operand" "rm")
1805: (const_int 1)
1806: (match_operand:SI 1 "general_operand" "g")))]
1807: ""
1808: "*
1809: { cc_status.flags = CC_Z_IN_F;
1810: return \"tbitd %1,%0\";
1811: }")
1812:
1813: ;; extract(base, width, offset)
1814: ;; Signed bitfield extraction is not supported in hardware on the
1815: ;; NS 32032. It is therefore better to let GCC figure out a
1816: ;; good strategy for generating the proper instruction sequence
1817: ;; and represent it as rtl.
1818:
1819: ;; Optimize the case of extracting a byte or word from a register.
1820: ;; Otherwise we must load a register with the offset of the
1821: ;; chunk we want, and perform an extract insn (each of which
1822: ;; is very expensive). Since we use the stack to do our bit-twiddling
1823: ;; we cannot use it for a destination. Perhaps things are fast
1824: ;; enough on the 32532 that such hacks are not needed.
1825:
1826: (define_insn ""
1827: [(set (match_operand:SI 0 "general_operand" "=ro")
1828: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1829: (match_operand:SI 2 "const_int_operand" "i")
1830: (match_operand:SI 3 "const_int_operand" "i")))]
1831: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1832: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
1833: "*
1834: {
1835: output_asm_insn (\"movd %1,tos\", operands);
1836: if (INTVAL (operands[2]) == 16)
1837: {
1838: if (INTVAL (operands[3]) == 8)
1839: output_asm_insn (\"movzwd 1(sp),%0\", operands);
1840: else
1841: output_asm_insn (\"movzwd 2(sp),%0\", operands);
1842: }
1843: else
1844: {
1845: if (INTVAL (operands[3]) == 8)
1846: output_asm_insn (\"movzbd 1(sp),%0\", operands);
1847: else if (INTVAL (operands[3]) == 16)
1848: output_asm_insn (\"movzbd 2(sp),%0\", operands);
1849: else
1850: output_asm_insn (\"movzbd 3(sp),%0\", operands);
1851: }
1852: if (TARGET_32532 || TARGET_32332)
1853: return \"cmpqd %$0,tos\";
1854: else
1855: return \"adjspb %$-4\";
1856: }")
1857:
1858: (define_insn "extzv"
1859: [(set (match_operand:SI 0 "general_operand" "=g<")
1860: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1861: (match_operand:SI 2 "const_int_operand" "i")
1862: (match_operand:SI 3 "general_operand" "rK")))]
1863: ""
1864: "*
1865: { if (GET_CODE (operands[3]) == CONST_INT)
1866: return \"extsd %1,%0,%3,%2\";
1867: else return \"extd %3,%1,%0,%2\";
1868: }")
1869:
1870: (define_insn ""
1871: [(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o")
1872: (match_operand:SI 1 "const_int_operand" "i")
1873: (match_operand:SI 2 "general_operand" "rn"))
1874: (match_operand:SI 3 "general_operand" "rm"))]
1875: ""
1876: "*
1877: { if (GET_CODE (operands[2]) == CONST_INT)
1878: {
1879: if (INTVAL (operands[2]) >= 8)
1880: {
1881: operands[0] = adj_offsettable_operand (operands[0],
1882: INTVAL (operands[2]) / 8);
1883: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1884: }
1885: if (INTVAL (operands[1]) <= 8)
1886: return \"inssb %3,%0,%2,%1\";
1887: else if (INTVAL (operands[1]) <= 16)
1888: return \"inssw %3,%0,%2,%1\";
1889: else
1890: return \"inssd %3,%0,%2,%1\";
1891: }
1892: return \"insd %2,%3,%0,%1\";
1893: }")
1894:
1895: (define_insn ""
1896: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1897: (match_operand:SI 1 "const_int_operand" "i")
1898: (match_operand:SI 2 "general_operand" "rK"))
1899: (match_operand:SI 3 "general_operand" "rm"))]
1900: ""
1901: "*
1902: { if (GET_CODE (operands[2]) == CONST_INT)
1903: if (INTVAL (operands[1]) <= 8)
1904: return \"inssb %3,%0,%2,%1\";
1905: else if (INTVAL (operands[1]) <= 16)
1906: return \"inssw %3,%0,%2,%1\";
1907: else
1908: return \"inssd %3,%0,%2,%1\";
1909: return \"insd %2,%3,%0,%1\";
1910: }")
1911:
1912: (define_insn "insv"
1913: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1914: (match_operand:SI 1 "const_int_operand" "i")
1915: (match_operand:SI 2 "general_operand" "rK"))
1916: (match_operand:SI 3 "general_operand" "rm"))]
1917: ""
1918: "*
1919: { if (GET_CODE (operands[2]) == CONST_INT)
1920: if (INTVAL (operands[1]) <= 8)
1921: return \"inssb %3,%0,%2,%1\";
1922: else if (INTVAL (operands[1]) <= 16)
1923: return \"inssw %3,%0,%2,%1\";
1924: else
1925: return \"inssd %3,%0,%2,%1\";
1926: return \"insd %2,%3,%0,%1\";
1927: }")
1928:
1929:
1930: (define_insn "jump"
1931: [(set (pc)
1932: (label_ref (match_operand 0 "" "")))]
1933: ""
1934: "br %l0")
1935:
1936: (define_insn "beq"
1937: [(set (pc)
1938: (if_then_else (eq (cc0)
1939: (const_int 0))
1940: (label_ref (match_operand 0 "" ""))
1941: (pc)))]
1942: ""
1943: "*
1944: { if (cc_prev_status.flags & CC_Z_IN_F)
1945: return \"bfc %l0\";
1946: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1947: return \"bfs %l0\";
1948: else return \"beq %l0\";
1949: }")
1950:
1951: (define_insn "bne"
1952: [(set (pc)
1953: (if_then_else (ne (cc0)
1954: (const_int 0))
1955: (label_ref (match_operand 0 "" ""))
1956: (pc)))]
1957: ""
1958: "*
1959: { if (cc_prev_status.flags & CC_Z_IN_F)
1960: return \"bfs %l0\";
1961: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1962: return \"bfc %l0\";
1963: else return \"bne %l0\";
1964: }")
1965:
1966: (define_insn "bgt"
1967: [(set (pc)
1968: (if_then_else (gt (cc0)
1969: (const_int 0))
1970: (label_ref (match_operand 0 "" ""))
1971: (pc)))]
1972: ""
1973: "bgt %l0")
1974:
1975: (define_insn "bgtu"
1976: [(set (pc)
1977: (if_then_else (gtu (cc0)
1978: (const_int 0))
1979: (label_ref (match_operand 0 "" ""))
1980: (pc)))]
1981: ""
1982: "bhi %l0")
1983:
1984: (define_insn "blt"
1985: [(set (pc)
1986: (if_then_else (lt (cc0)
1987: (const_int 0))
1988: (label_ref (match_operand 0 "" ""))
1989: (pc)))]
1990: ""
1991: "blt %l0")
1992:
1993: (define_insn "bltu"
1994: [(set (pc)
1995: (if_then_else (ltu (cc0)
1996: (const_int 0))
1997: (label_ref (match_operand 0 "" ""))
1998: (pc)))]
1999: ""
2000: "blo %l0")
2001:
2002: (define_insn "bge"
2003: [(set (pc)
2004: (if_then_else (ge (cc0)
2005: (const_int 0))
2006: (label_ref (match_operand 0 "" ""))
2007: (pc)))]
2008: ""
2009: "bge %l0")
2010:
2011: (define_insn "bgeu"
2012: [(set (pc)
2013: (if_then_else (geu (cc0)
2014: (const_int 0))
2015: (label_ref (match_operand 0 "" ""))
2016: (pc)))]
2017: ""
2018: "bhs %l0")
2019:
2020: (define_insn "ble"
2021: [(set (pc)
2022: (if_then_else (le (cc0)
2023: (const_int 0))
2024: (label_ref (match_operand 0 "" ""))
2025: (pc)))]
2026: ""
2027: "ble %l0")
2028:
2029: (define_insn "bleu"
2030: [(set (pc)
2031: (if_then_else (leu (cc0)
2032: (const_int 0))
2033: (label_ref (match_operand 0 "" ""))
2034: (pc)))]
2035: ""
2036: "bls %l0")
2037:
2038: (define_insn ""
2039: [(set (pc)
2040: (if_then_else (eq (cc0)
2041: (const_int 0))
2042: (pc)
2043: (label_ref (match_operand 0 "" ""))))]
2044: ""
2045: "*
2046: { if (cc_prev_status.flags & CC_Z_IN_F)
2047: return \"bfs %l0\";
2048: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2049: return \"bfc %l0\";
2050: else return \"bne %l0\";
2051: }")
2052:
2053: (define_insn ""
2054: [(set (pc)
2055: (if_then_else (ne (cc0)
2056: (const_int 0))
2057: (pc)
2058: (label_ref (match_operand 0 "" ""))))]
2059: ""
2060: "*
2061: { if (cc_prev_status.flags & CC_Z_IN_F)
2062: return \"bfc %l0\";
2063: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2064: return \"bfs %l0\";
2065: else return \"beq %l0\";
2066: }")
2067:
2068: (define_insn ""
2069: [(set (pc)
2070: (if_then_else (gt (cc0)
2071: (const_int 0))
2072: (pc)
2073: (label_ref (match_operand 0 "" ""))))]
2074: ""
2075: "ble %l0")
2076:
2077: (define_insn ""
2078: [(set (pc)
2079: (if_then_else (gtu (cc0)
2080: (const_int 0))
2081: (pc)
2082: (label_ref (match_operand 0 "" ""))))]
2083: ""
2084: "bls %l0")
2085:
2086: (define_insn ""
2087: [(set (pc)
2088: (if_then_else (lt (cc0)
2089: (const_int 0))
2090: (pc)
2091: (label_ref (match_operand 0 "" ""))))]
2092: ""
2093: "bge %l0")
2094:
2095: (define_insn ""
2096: [(set (pc)
2097: (if_then_else (ltu (cc0)
2098: (const_int 0))
2099: (pc)
2100: (label_ref (match_operand 0 "" ""))))]
2101: ""
2102: "bhs %l0")
2103:
2104: (define_insn ""
2105: [(set (pc)
2106: (if_then_else (ge (cc0)
2107: (const_int 0))
2108: (pc)
2109: (label_ref (match_operand 0 "" ""))))]
2110: ""
2111: "blt %l0")
2112:
2113: (define_insn ""
2114: [(set (pc)
2115: (if_then_else (geu (cc0)
2116: (const_int 0))
2117: (pc)
2118: (label_ref (match_operand 0 "" ""))))]
2119: ""
2120: "blo %l0")
2121:
2122: (define_insn ""
2123: [(set (pc)
2124: (if_then_else (le (cc0)
2125: (const_int 0))
2126: (pc)
2127: (label_ref (match_operand 0 "" ""))))]
2128: ""
2129: "bgt %l0")
2130:
2131: (define_insn ""
2132: [(set (pc)
2133: (if_then_else (leu (cc0)
2134: (const_int 0))
2135: (pc)
2136: (label_ref (match_operand 0 "" ""))))]
2137: ""
2138: "bhi %l0")
2139:
2140: ;; Subtract-and-jump and Add-and-jump insns.
2141: ;; These can actually be used for adding numbers in the range -8 to 7
2142:
2143: (define_insn ""
2144: [(set (pc)
2145: (if_then_else
2146: (ne (match_operand:SI 0 "general_operand" "+g")
2147: (match_operand:SI 1 "const_int_operand" "i"))
2148: (label_ref (match_operand 2 "" ""))
2149: (pc)))
2150: (set (match_dup 0)
2151: (minus:SI (match_dup 0)
2152: (match_dup 1)))]
2153: "INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2154: "acbd %$%n1,%0,%l2")
2155:
2156: (define_insn ""
2157: [(set (pc)
2158: (if_then_else
2159: (ne (match_operand:SI 0 "general_operand" "+g")
2160: (match_operand:SI 1 "const_int_operand" "i"))
2161: (label_ref (match_operand 2 "" ""))
2162: (pc)))
2163: (set (match_dup 0)
2164: (plus:SI (match_dup 0)
2165: (match_operand:SI 3 "const_int_operand" "i")))]
2166: "INTVAL (operands[1]) == - INTVAL (operands[3])
2167: && INTVAL (operands[3]) >= -8 && INTVAL (operands[3]) < 8"
2168: "acbd %3,%0,%l2")
2169:
2170: (define_insn "call"
2171: [(call (match_operand:QI 0 "memory_operand" "m")
2172: (match_operand:QI 1 "general_operand" "g"))]
2173: ""
2174: "*
2175: {
2176: #ifndef JSR_ALWAYS
2177: if (GET_CODE (operands[0]) == MEM)
2178: {
2179: rtx temp = XEXP (operands[0], 0);
2180: if (CONSTANT_ADDRESS_P (temp))
2181: {
2182: operands[0] = temp;
2183: return \"bsr %0\";
2184: #if 0
2185: #ifdef GNX_V3
2186: return \"bsr %0\";
2187: #else
2188: return \"bsr %?%a0\";
2189: #endif
2190: #endif
2191: }
2192: if (GET_CODE (XEXP (operands[0], 0)) == REG)
2193: return \"jsr %0\";
2194: #if 0
2195: return \"jsr %a0\";
2196: #endif
2197: }
2198: #endif /* not JSR_ALWAYS */
2199: return \"jsr %0\";
2200: }")
2201:
2202: (define_insn "call_value"
2203: [(set (match_operand 0 "" "=rf")
2204: (call (match_operand:QI 1 "memory_operand" "m")
2205: (match_operand:QI 2 "general_operand" "g")))]
2206: ""
2207: "*
2208: {
2209: #ifndef JSR_ALWAYS
2210: if (GET_CODE (operands[1]) == MEM)
2211: {
2212: rtx temp = XEXP (operands[1], 0);
2213: if (CONSTANT_ADDRESS_P (temp))
2214: {
2215: operands[1] = temp;
2216: return \"bsr %1\";
2217: #if 0
2218: #ifdef GNX_V3
2219: return \"bsr %1\";
2220: #else
2221: return \"bsr %?%a1\";
2222: #endif
2223: #endif
2224: }
2225: if (GET_CODE (XEXP (operands[1], 0)) == REG)
2226: return \"jsr %1\";
2227: #if 0
2228: return \"jsr %a1\";
2229: #endif
2230: }
2231: #endif /* not JSR_ALWAYS */
2232: return \"jsr %1\";
2233: }")
2234:
2235: (define_insn "return"
2236: [(return)]
2237: "0"
2238: "ret 0")
2239:
2240: (define_insn "abssf2"
2241: [(set (match_operand:SF 0 "general_operand" "=fm<")
2242: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2243: "TARGET_32081"
2244: "absf %1,%0")
2245:
2246: (define_insn "absdf2"
2247: [(set (match_operand:DF 0 "general_operand" "=fm<")
2248: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2249: "TARGET_32081"
2250: "absl %1,%0")
2251:
2252: (define_insn "abssi2"
2253: [(set (match_operand:SI 0 "general_operand" "=g<")
2254: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2255: ""
2256: "absd %1,%0")
2257:
2258: (define_insn "abshi2"
2259: [(set (match_operand:HI 0 "general_operand" "=g<")
2260: (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2261: ""
2262: "absw %1,%0")
2263:
2264: (define_insn "absqi2"
2265: [(set (match_operand:QI 0 "general_operand" "=g<")
2266: (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2267: ""
2268: "absb %1,%0")
2269:
2270: (define_insn "nop"
2271: [(const_int 0)]
2272: ""
2273: "nop")
2274:
2275: (define_insn "indirect_jump"
2276: [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2277: ""
2278: "jump %0")
2279:
2280: ;;(define_insn "tablejump"
2281: ;; [(set (pc)
2282: ;; (plus:SI (match_operand:SI 0 "general_operand" "g")
2283: ;; (pc)))]
2284: ;; ""
2285: ;; "cased %0")
2286:
2287: (define_insn "tablejump"
2288: [(set (pc)
2289: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g")))
2290: (use (label_ref (match_operand 1 "" "")))]
2291: ""
2292: "*
2293: {
2294: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2295: CODE_LABEL_NUMBER (operands[1]));
2296: return \"casew %0\";
2297: }")
2298:
2299: ;;(define_insn ""
2300: ;; [(set (pc)
2301: ;; (plus:SI (match_operand:QI 0 "general_operand" "g")
2302: ;; (pc)))]
2303: ;; ""
2304: ;; "caseb %0")
2305:
2306: ;; Scondi instructions
2307: (define_insn "seq"
2308: [(set (match_operand:SI 0 "general_operand" "=g<")
2309: (eq:SI (cc0) (const_int 0)))]
2310: ""
2311: "*
2312: { if (cc_prev_status.flags & CC_Z_IN_F)
2313: return \"sfcd %0\";
2314: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2315: return \"sfsd %0\";
2316: else return \"seqd %0\";
2317: }")
2318:
2319: (define_insn ""
2320: [(set (match_operand:HI 0 "general_operand" "=g<")
2321: (eq:HI (cc0) (const_int 0)))]
2322: ""
2323: "*
2324: { if (cc_prev_status.flags & CC_Z_IN_F)
2325: return \"sfcw %0\";
2326: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2327: return \"sfsw %0\";
2328: else return \"seqw %0\";
2329: }")
2330:
2331: (define_insn ""
2332: [(set (match_operand:QI 0 "general_operand" "=g<")
2333: (eq:QI (cc0) (const_int 0)))]
2334: ""
2335: "*
2336: { if (cc_prev_status.flags & CC_Z_IN_F)
2337: return \"sfcb %0\";
2338: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2339: return \"sfsb %0\";
2340: else return \"seqb %0\";
2341: }")
2342:
2343: (define_insn "sne"
2344: [(set (match_operand:SI 0 "general_operand" "=g<")
2345: (ne:SI (cc0) (const_int 0)))]
2346: ""
2347: "*
2348: { if (cc_prev_status.flags & CC_Z_IN_F)
2349: return \"sfsd %0\";
2350: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2351: return \"sfcd %0\";
2352: else return \"sned %0\";
2353: }")
2354:
2355: (define_insn ""
2356: [(set (match_operand:HI 0 "general_operand" "=g<")
2357: (ne:HI (cc0) (const_int 0)))]
2358: ""
2359: "*
2360: { if (cc_prev_status.flags & CC_Z_IN_F)
2361: return \"sfsw %0\";
2362: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2363: return \"sfcw %0\";
2364: else return \"snew %0\";
2365: }")
2366:
2367: (define_insn ""
2368: [(set (match_operand:QI 0 "general_operand" "=g<")
2369: (ne:QI (cc0) (const_int 0)))]
2370: ""
2371: "*
2372: { if (cc_prev_status.flags & CC_Z_IN_F)
2373: return \"sfsb %0\";
2374: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2375: return \"sfcb %0\";
2376: else return \"sneb %0\";
2377: }")
2378:
2379: (define_insn "sgt"
2380: [(set (match_operand:SI 0 "general_operand" "=g<")
2381: (gt:SI (cc0) (const_int 0)))]
2382: ""
2383: "sgtd %0")
2384:
2385: (define_insn ""
2386: [(set (match_operand:HI 0 "general_operand" "=g<")
2387: (gt:HI (cc0) (const_int 0)))]
2388: ""
2389: "sgtw %0")
2390:
2391: (define_insn ""
2392: [(set (match_operand:QI 0 "general_operand" "=g<")
2393: (gt:QI (cc0) (const_int 0)))]
2394: ""
2395: "sgtb %0")
2396:
2397: (define_insn "sgtu"
2398: [(set (match_operand:SI 0 "general_operand" "=g<")
2399: (gtu:SI (cc0) (const_int 0)))]
2400: ""
2401: "shid %0")
2402:
2403: (define_insn ""
2404: [(set (match_operand:HI 0 "general_operand" "=g<")
2405: (gtu:HI (cc0) (const_int 0)))]
2406: ""
2407: "shiw %0")
2408:
2409: (define_insn ""
2410: [(set (match_operand:QI 0 "general_operand" "=g<")
2411: (gtu:QI (cc0) (const_int 0)))]
2412: ""
2413: "shib %0")
2414:
2415: (define_insn "slt"
2416: [(set (match_operand:SI 0 "general_operand" "=g<")
2417: (lt:SI (cc0) (const_int 0)))]
2418: ""
2419: "sltd %0")
2420:
2421: (define_insn ""
2422: [(set (match_operand:HI 0 "general_operand" "=g<")
2423: (lt:HI (cc0) (const_int 0)))]
2424: ""
2425: "sltw %0")
2426:
2427: (define_insn ""
2428: [(set (match_operand:QI 0 "general_operand" "=g<")
2429: (lt:QI (cc0) (const_int 0)))]
2430: ""
2431: "sltb %0")
2432:
2433: (define_insn "sltu"
2434: [(set (match_operand:SI 0 "general_operand" "=g<")
2435: (ltu:SI (cc0) (const_int 0)))]
2436: ""
2437: "slod %0")
2438:
2439: (define_insn ""
2440: [(set (match_operand:HI 0 "general_operand" "=g<")
2441: (ltu:HI (cc0) (const_int 0)))]
2442: ""
2443: "slow %0")
2444:
2445: (define_insn ""
2446: [(set (match_operand:QI 0 "general_operand" "=g<")
2447: (ltu:QI (cc0) (const_int 0)))]
2448: ""
2449: "slob %0")
2450:
2451: (define_insn "sge"
2452: [(set (match_operand:SI 0 "general_operand" "=g<")
2453: (ge:SI (cc0) (const_int 0)))]
2454: ""
2455: "sged %0")
2456:
2457: (define_insn ""
2458: [(set (match_operand:HI 0 "general_operand" "=g<")
2459: (ge:HI (cc0) (const_int 0)))]
2460: ""
2461: "sgew %0")
2462:
2463: (define_insn ""
2464: [(set (match_operand:QI 0 "general_operand" "=g<")
2465: (ge:QI (cc0) (const_int 0)))]
2466: ""
2467: "sgeb %0")
2468:
2469: (define_insn "sgeu"
2470: [(set (match_operand:SI 0 "general_operand" "=g<")
2471: (geu:SI (cc0) (const_int 0)))]
2472: ""
2473: "shsd %0")
2474:
2475: (define_insn ""
2476: [(set (match_operand:HI 0 "general_operand" "=g<")
2477: (geu:HI (cc0) (const_int 0)))]
2478: ""
2479: "shsw %0")
2480:
2481: (define_insn ""
2482: [(set (match_operand:QI 0 "general_operand" "=g<")
2483: (geu:QI (cc0) (const_int 0)))]
2484: ""
2485: "shsb %0")
2486:
2487: (define_insn "sle"
2488: [(set (match_operand:SI 0 "general_operand" "=g<")
2489: (le:SI (cc0) (const_int 0)))]
2490: ""
2491: "sled %0")
2492:
2493: (define_insn ""
2494: [(set (match_operand:HI 0 "general_operand" "=g<")
2495: (le:HI (cc0) (const_int 0)))]
2496: ""
2497: "slew %0")
2498:
2499: (define_insn ""
2500: [(set (match_operand:QI 0 "general_operand" "=g<")
2501: (le:QI (cc0) (const_int 0)))]
2502: ""
2503: "sleb %0")
2504:
2505: (define_insn "sleu"
2506: [(set (match_operand:SI 0 "general_operand" "=g<")
2507: (leu:SI (cc0) (const_int 0)))]
2508: ""
2509: "slsd %0")
2510:
2511: (define_insn ""
2512: [(set (match_operand:HI 0 "general_operand" "=g<")
2513: (leu:HI (cc0) (const_int 0)))]
2514: ""
2515: "slsw %0")
2516:
2517: (define_insn ""
2518: [(set (match_operand:QI 0 "general_operand" "=g<")
2519: (leu:QI (cc0) (const_int 0)))]
2520: ""
2521: "slsb %0")
2522:
2523: ;;- Local variables:
2524: ;;- mode:emacs-lisp
2525: ;;- comment-start: ";;- "
2526: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2527: ;;- eval: (modify-syntax-entry ?[ "(]")
2528: ;;- eval: (modify-syntax-entry ?] ")[")
2529: ;;- eval: (modify-syntax-entry ?{ "(}")
2530: ;;- eval: (modify-syntax-entry ?} "){")
2531: ;;- End:
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