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1.1 root 1: ;; BUGS:
2: ;; Insert no-op between an insn with memory read-write operands
3: ;; following by a scale-indexing operation.
4: ;; The Sequent assembler does not allow addresses to be used
5: ;; except in insns which explicitly compute an effective address.
6: ;; I.e., one cannot say "cmpd _p,@_x"
7: ;; Implement unsigned multiplication??
8:
9: ;;- Machine descrption for GNU compiler
10: ;;- ns32000 Version
11: ;; Copyright (C) 1988 Free Software Foundation, Inc.
12: ;; Contributed by Michael Tiemann ([email protected])
13:
14: ;; This file is part of GNU CC.
15:
16: ;; GNU CC is free software; you can redistribute it and/or modify
17: ;; it under the terms of the GNU General Public License as published by
18: ;; the Free Software Foundation; either version 1, or (at your option)
19: ;; any later version.
20:
21: ;; GNU CC is distributed in the hope that it will be useful,
22: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
23: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24: ;; GNU General Public License for more details.
25:
26: ;; You should have received a copy of the GNU General Public License
27: ;; along with GNU CC; see the file COPYING. If not, write to
28: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
29:
30:
31: ;;- Instruction patterns. When multiple patterns apply,
32: ;;- the first one in the file is chosen.
33: ;;-
34: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
35: ;;-
36: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
37: ;;- updates for most instructions.
38:
39: ; tstsi is first test insn so that it is the one to match
40: ; a constant argument.
41:
42: (define_insn "tstsi"
43: [(set (cc0)
44: (match_operand:SI 0 "general_operand" "rmn"))]
45: ""
46: "*
47: { cc_status.flags |= CC_REVERSED;
48: operands[1] = const0_rtx;
49: return \"cmpqd %1,%0\"; }")
50:
51: (define_insn "tsthi"
52: [(set (cc0)
53: (match_operand:HI 0 "general_operand" "g"))]
54: ""
55: "*
56: { cc_status.flags |= CC_REVERSED;
57: operands[1] = const0_rtx;
58: return \"cmpqw %1,%0\"; }")
59:
60: (define_insn "tstqi"
61: [(set (cc0)
62: (match_operand:QI 0 "general_operand" "g"))]
63: ""
64: "*
65: { cc_status.flags |= CC_REVERSED;
66: operands[1] = const0_rtx;
67: return \"cmpqb %1,%0\"; }")
68:
69: (define_insn "tstdf"
70: [(set (cc0)
71: (match_operand:DF 0 "general_operand" "fmF"))]
72: "TARGET_32081"
73: "*
74: { cc_status.flags |= CC_REVERSED;
75: operands[1] = dconst0_rtx;
76: return \"cmpl %1,%0\"; }")
77:
78: (define_insn "tstsf"
79: [(set (cc0)
80: (match_operand:SF 0 "general_operand" "fmF"))]
81: "TARGET_32081"
82: "*
83: { cc_status.flags |= CC_REVERSED;
84: operands[1] = fconst0_rtx;
85: return \"cmpf %1,%0\"; }")
86:
87: ;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
88:
89: (define_insn "cmpsi"
90: [(set (cc0)
91: (compare (match_operand:SI 0 "general_operand" "rmn")
92: (match_operand:SI 1 "general_operand" "rmn")))]
93: ""
94: "*
95: {
96: if (GET_CODE (operands[1]) == CONST_INT)
97: {
98: int i = INTVAL (operands[1]);
99: if (i <= 7 && i >= -8)
100: {
101: cc_status.flags |= CC_REVERSED;
102: return \"cmpqd %1,%0\";
103: }
104: }
105: cc_status.flags &= ~CC_REVERSED;
106: if (GET_CODE (operands[0]) == CONST_INT)
107: {
108: int i = INTVAL (operands[0]);
109: if (i <= 7 && i >= -8)
110: return \"cmpqd %0,%1\";
111: }
112: return \"cmpd %0,%1\";
113: }")
114:
115: (define_insn "cmphi"
116: [(set (cc0)
117: (compare (match_operand:HI 0 "general_operand" "g")
118: (match_operand:HI 1 "general_operand" "g")))]
119: ""
120: "*
121: {
122: if (GET_CODE (operands[1]) == CONST_INT)
123: {
124: short i = INTVAL (operands[1]);
125: if (i <= 7 && i >= -8)
126: {
127: cc_status.flags |= CC_REVERSED;
128: if (INTVAL (operands[1]) > 7)
129: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
130: return \"cmpqw %1,%0\";
131: }
132: }
133: cc_status.flags &= ~CC_REVERSED;
134: if (GET_CODE (operands[0]) == CONST_INT)
135: {
136: short i = INTVAL (operands[0]);
137: if (i <= 7 && i >= -8)
138: {
139: if (INTVAL (operands[0]) > 7)
140: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
141: return \"cmpqw %0,%1\";
142: }
143: }
144: return \"cmpw %0,%1\";
145: }")
146:
147: (define_insn "cmpqi"
148: [(set (cc0)
149: (compare (match_operand:QI 0 "general_operand" "g")
150: (match_operand:QI 1 "general_operand" "g")))]
151: ""
152: "*
153: {
154: if (GET_CODE (operands[1]) == CONST_INT)
155: {
156: char i = INTVAL (operands[1]);
157: if (i <= 7 && i >= -8)
158: {
159: cc_status.flags |= CC_REVERSED;
160: if (INTVAL (operands[1]) > 7)
161: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
162: return \"cmpqb %1,%0\";
163: }
164: }
165: cc_status.flags &= ~CC_REVERSED;
166: if (GET_CODE (operands[0]) == CONST_INT)
167: {
168: char i = INTVAL (operands[0]);
169: if (i <= 7 && i >= -8)
170: {
171: if (INTVAL (operands[0]) > 7)
172: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
173: return \"cmpqb %0,%1\";
174: }
175: }
176: return \"cmpb %0,%1\";
177: }")
178:
179: (define_insn "cmpdf"
180: [(set (cc0)
181: (compare (match_operand:DF 0 "general_operand" "fmF")
182: (match_operand:DF 1 "general_operand" "fmF")))]
183: "TARGET_32081"
184: "cmpl %0,%1")
185:
186: (define_insn "cmpsf"
187: [(set (cc0)
188: (compare (match_operand:SF 0 "general_operand" "fmF")
189: (match_operand:SF 1 "general_operand" "fmF")))]
190: "TARGET_32081"
191: "cmpf %0,%1")
192:
193: (define_insn "movdf"
194: [(set (match_operand:DF 0 "general_operand" "=&fg<")
195: (match_operand:DF 1 "general_operand" "fFg"))]
196: ""
197: "*
198: {
199: if (FP_REG_P (operands[0]))
200: {
201: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
202: return \"movl %1,%0\";
203: if (REG_P (operands[1]))
204: {
205: rtx xoperands[2];
206: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
207: output_asm_insn (\"movd %1,tos\", xoperands);
208: output_asm_insn (\"movd %1,tos\", operands);
209: return \"movl tos,%0\";
210: }
211: return \"movl %1,%0\";
212: }
213: else if (FP_REG_P (operands[1]))
214: {
215: if (REG_P (operands[0]))
216: {
217: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
218: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
219: return \"movd tos,%0\";
220: }
221: else
222: return \"movl %1,%0\";
223: }
224: return output_move_double (operands);
225: }")
226:
227: (define_insn "movsf"
228: [(set (match_operand:SF 0 "general_operand" "=fg<")
229: (match_operand:SF 1 "general_operand" "fFg"))]
230: ""
231: "*
232: {
233: if (FP_REG_P (operands[0]))
234: {
235: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
236: return \"movd %1,tos\;movf tos,%0\";
237: else
238: return \"movf %1,%0\";
239: }
240: else if (FP_REG_P (operands[1]))
241: {
242: if (REG_P (operands[0]))
243: return \"movf %1,tos\;movd tos,%0\";
244: return \"movf %1,%0\";
245: }
246: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
247: {
1.1.1.2 ! root 248: union {int i[2]; float f; double d;} convrt;
! 249: convrt.i[0] = CONST_DOUBLE_LOW (operands[1]);
! 250: convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]);
! 251: convrt.f = convrt.d;
! 252:
1.1 root 253: /* Is there a better machine-independent way to to this? */
1.1.1.2 ! root 254: operands[1] = gen_rtx (CONST_INT, VOIDmode, convrt.i[0]);
1.1 root 255: return \"movd %1,%0\";
256: }
257: else return \"movd %1,%0\";
258: }")
259:
260: (define_insn ""
261: [(set (match_operand:TI 0 "memory_operand" "=m")
262: (match_operand:TI 1 "memory_operand" "m"))]
263: ""
264: "movmd %1,%0,4")
265:
266: (define_insn "movdi"
267: [(set (match_operand:DI 0 "general_operand" "=&g<")
268: (match_operand:DI 1 "general_operand" "gF"))]
269: ""
270: "* return output_move_double (operands); ")
271:
272: ;; This special case must precede movsi.
273: (define_insn ""
274: [(set (reg:SI 17)
275: (match_operand:SI 0 "general_operand" "rmn"))]
276: ""
277: "lprd sp,%0")
278:
279: (define_insn "movsi"
280: [(set (match_operand:SI 0 "general_operand" "=g<")
281: (match_operand:SI 1 "general_operand" "gx"))]
282: ""
283: "*
284: { if (GET_CODE (operands[1]) == CONST_INT)
285: {
286: int i = INTVAL (operands[1]);
287: if (i <= 7 && i >= -8)
288: return \"movqd %1,%0\";
289: if (i < 0x4000 && i >= -0x4000)
290: #ifdef GNX_V3
291: return \"addr %c1,%0\";
292: #else
293: return \"addr @%c1,%0\";
294: #endif
295: return \"movd %1,%0\";
296: }
297: else if (GET_CODE (operands[1]) == REG)
298: {
299: if (REGNO (operands[1]) < 16)
300: return \"movd %1,%0\";
301: else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM)
302: {
303: if (GET_CODE(operands[0]) == REG)
304: return \"sprd fp,%0\";
305: else
306: return \"addr 0(fp),%0\" ;
307: }
308: else if (REGNO (operands[1]) == STACK_POINTER_REGNUM)
309: {
310: if (GET_CODE(operands[0]) == REG)
311: return \"sprd sp,%0\";
312: else
313: return \"addr 0(sp),%0\" ;
314: }
315: else abort (0);
316: }
317: else if (GET_CODE (operands[1]) == MEM)
318: return \"movd %1,%0\";
319: /* Check if this effective address can be
320: calculated faster by pulling it apart. */
321: if (REG_P (operands[0])
322: && GET_CODE (operands[1]) == MULT
323: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
324: && (INTVAL (XEXP (operands[1], 1)) == 2
325: || INTVAL (XEXP (operands[1], 1)) == 4))
326: {
327: rtx xoperands[3];
328: xoperands[0] = operands[0];
329: xoperands[1] = XEXP (operands[1], 0);
330: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
331: return output_shift_insn (xoperands);
332: }
333: return \"addr %a1,%0\";
334: }")
335:
336: (define_insn "movhi"
337: [(set (match_operand:HI 0 "general_operand" "=g<")
338: (match_operand:HI 1 "general_operand" "g"))]
339: ""
340: "*
341: {
342: if (GET_CODE (operands[1]) == CONST_INT)
343: {
344: short i = INTVAL (operands[1]);
345: if (i <= 7 && i >= -8)
346: {
347: if (INTVAL (operands[1]) > 7)
348: operands[1] =
349: gen_rtx (CONST_INT, VOIDmode, i);
350: return \"movqw %1,%0\";
351: }
352: }
353: return \"movw %1,%0\";
354: }")
355:
356: (define_insn "movstricthi"
357: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
358: (match_operand:HI 1 "general_operand" "g"))]
359: ""
360: "*
361: {
362: if (GET_CODE (operands[1]) == CONST_INT
363: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
364: return \"movqw %1,%0\";
365: return \"movw %1,%0\";
366: }")
367:
368: (define_insn "movqi"
369: [(set (match_operand:QI 0 "general_operand" "=g<")
370: (match_operand:QI 1 "general_operand" "g"))]
371: ""
372: "*
373: { if (GET_CODE (operands[1]) == CONST_INT)
374: {
375: char char_val = (char)INTVAL (operands[1]);
376: if (char_val <= 7 && char_val >= -8)
377: {
378: if (INTVAL (operands[1]) > 7)
379: operands[1] =
380: gen_rtx (CONST_INT, VOIDmode, char_val);
381: return \"movqb %1,%0\";
382: }
383: }
384: return \"movb %1,%0\";
385: }")
386:
387: (define_insn "movstrictqi"
388: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
389: (match_operand:QI 1 "general_operand" "g"))]
390: ""
391: "*
392: {
393: if (GET_CODE (operands[1]) == CONST_INT
394: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
395: return \"movqb %1,%0\";
396: return \"movb %1,%0\";
397: }")
398:
399: ;; The definition of this insn does not really explain what it does,
400: ;; but it should suffice
401: ;; that anything generated as this insn will be recognized as one
402: ;; and that it won't successfully combine with anything.
403: (define_insn "movstrsi"
404: [(set (match_operand:BLK 0 "general_operand" "=g")
405: (match_operand:BLK 1 "general_operand" "g"))
406: (use (match_operand:SI 2 "general_operand" "rmn"))
407: (clobber (reg:SI 0))
408: (clobber (reg:SI 1))
409: (clobber (reg:SI 2))]
410: ""
411: "*
412: {
413: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
414: abort ();
415: operands[0] = XEXP (operands[0], 0);
416: operands[1] = XEXP (operands[1], 0);
417: if (GET_CODE (operands[0]) == MEM)
418: if (GET_CODE (operands[1]) == MEM)
419: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
420: else
421: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
422: else if (GET_CODE (operands[1]) == MEM)
423: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
424: else
425: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
426:
427: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
428: {
429: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
430: if ((unsigned) INTVAL (operands[2]) <= 7)
431: return \"movqd %2,r0\;movsd\";
432: else
433: return \"movd %2,r0\;movsd\";
434: }
435: else
436: {
437: return \"movd %2,r0\;movsb\";
438: }
439: }")
440:
441: ;; Extension and truncation insns.
442: ;; Those for integer source operand
443: ;; are ordered widest source type first.
444:
445: (define_insn "truncsiqi2"
446: [(set (match_operand:QI 0 "general_operand" "=g<")
447: (truncate:QI (match_operand:SI 1 "general_operand" "rmn")))]
448: ""
449: "movb %1,%0")
450:
451: (define_insn "truncsihi2"
452: [(set (match_operand:HI 0 "general_operand" "=g<")
453: (truncate:HI (match_operand:SI 1 "general_operand" "rmn")))]
454: ""
455: "movw %1,%0")
456:
457: (define_insn "trunchiqi2"
458: [(set (match_operand:QI 0 "general_operand" "=g<")
459: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
460: ""
461: "movb %1,%0")
462:
463: (define_insn "extendhisi2"
464: [(set (match_operand:SI 0 "general_operand" "=g<")
465: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
466: ""
467: "movxwd %1,%0")
468:
469: (define_insn "extendqihi2"
470: [(set (match_operand:HI 0 "general_operand" "=g<")
471: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
472: ""
473: "movxbw %1,%0")
474:
475: (define_insn "extendqisi2"
476: [(set (match_operand:SI 0 "general_operand" "=g<")
477: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
478: ""
479: "movxbd %1,%0")
480:
481: (define_insn "extendsfdf2"
482: [(set (match_operand:DF 0 "general_operand" "=fm<")
483: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
484: "TARGET_32081"
485: "movfl %1,%0")
486:
487: (define_insn "truncdfsf2"
488: [(set (match_operand:SF 0 "general_operand" "=fm<")
489: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
490: "TARGET_32081"
491: "movlf %1,%0")
492:
493: (define_insn "zero_extendhisi2"
494: [(set (match_operand:SI 0 "general_operand" "=g<")
495: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
496: ""
497: "movzwd %1,%0")
498:
499: (define_insn "zero_extendqihi2"
500: [(set (match_operand:HI 0 "general_operand" "=g<")
501: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
502: ""
503: "movzbw %1,%0")
504:
505: (define_insn "zero_extendqisi2"
506: [(set (match_operand:SI 0 "general_operand" "=g<")
507: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
508: ""
509: "movzbd %1,%0")
510:
511: ;; Fix-to-float conversion insns.
512: ;; Note that the ones that start with SImode come first.
513: ;; That is so that an operand that is a CONST_INT
514: ;; (and therefore lacks a specific machine mode).
515: ;; will be recognized as SImode (which is always valid)
516: ;; rather than as QImode or HImode.
517:
518: ;; Rumor has it that the National part does not correctly convert
519: ;; constant ints to floats. This conversion is therefore disabled.
520: ;; A register must be used to perform the conversion.
521:
522: (define_insn "floatsisf2"
523: [(set (match_operand:SF 0 "general_operand" "=fm<")
524: (float:SF (match_operand:SI 1 "general_operand" "rm")))]
525: "TARGET_32081"
526: "movdf %1,%0")
527:
528: (define_insn "floatsidf2"
529: [(set (match_operand:DF 0 "general_operand" "=fm<")
530: (float:DF (match_operand:SI 1 "general_operand" "rm")))]
531: "TARGET_32081"
532: "movdl %1,%0")
533:
534: (define_insn "floathisf2"
535: [(set (match_operand:SF 0 "general_operand" "=fm<")
536: (float:SF (match_operand:HI 1 "general_operand" "rm")))]
537: "TARGET_32081"
538: "movwf %1,%0")
539:
540: (define_insn "floathidf2"
541: [(set (match_operand:DF 0 "general_operand" "=fm<")
542: (float:DF (match_operand:HI 1 "general_operand" "rm")))]
543: "TARGET_32081"
544: "movwl %1,%0")
545:
546: (define_insn "floatqisf2"
547: [(set (match_operand:SF 0 "general_operand" "=fm<")
548: (float:SF (match_operand:QI 1 "general_operand" "rm")))]
549: "TARGET_32081"
550: "movbf %1,%0")
551:
552: ; Some assemblers warn that this insn doesn't work.
553: ; Maybe they know something we don't.
554: ;(define_insn "floatqidf2"
555: ; [(set (match_operand:DF 0 "general_operand" "=fm<")
556: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
557: ; "TARGET_32081"
558: ; "movbl %1,%0")
559:
560: ;; Float-to-fix conversion insns.
561: ;; The sequent compiler always generates "trunc" insns.
562:
563: (define_insn "fixsfqi2"
564: [(set (match_operand:QI 0 "general_operand" "=g<")
565: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
566: "TARGET_32081"
567: "truncfb %1,%0")
568:
569: (define_insn "fixsfhi2"
570: [(set (match_operand:HI 0 "general_operand" "=g<")
571: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
572: "TARGET_32081"
573: "truncfw %1,%0")
574:
575: (define_insn "fixsfsi2"
576: [(set (match_operand:SI 0 "general_operand" "=g<")
577: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
578: "TARGET_32081"
579: "truncfd %1,%0")
580:
581: (define_insn "fixdfqi2"
582: [(set (match_operand:QI 0 "general_operand" "=g<")
583: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
584: "TARGET_32081"
585: "trunclb %1,%0")
586:
587: (define_insn "fixdfhi2"
588: [(set (match_operand:HI 0 "general_operand" "=g<")
589: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
590: "TARGET_32081"
591: "trunclw %1,%0")
592:
593: (define_insn "fixdfsi2"
594: [(set (match_operand:SI 0 "general_operand" "=g<")
595: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
596: "TARGET_32081"
597: "truncld %1,%0")
598:
599: ;; Unsigned
600:
601: (define_insn "fixunssfqi2"
602: [(set (match_operand:QI 0 "general_operand" "=g<")
603: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
604: "TARGET_32081"
605: "truncfb %1,%0")
606:
607: (define_insn "fixunssfhi2"
608: [(set (match_operand:HI 0 "general_operand" "=g<")
609: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
610: "TARGET_32081"
611: "truncfw %1,%0")
612:
613: (define_insn "fixunssfsi2"
614: [(set (match_operand:SI 0 "general_operand" "=g<")
615: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
616: "TARGET_32081"
617: "truncfd %1,%0")
618:
619: (define_insn "fixunsdfqi2"
620: [(set (match_operand:QI 0 "general_operand" "=g<")
621: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
622: "TARGET_32081"
623: "trunclb %1,%0")
624:
625: (define_insn "fixunsdfhi2"
626: [(set (match_operand:HI 0 "general_operand" "=g<")
627: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
628: "TARGET_32081"
629: "trunclw %1,%0")
630:
631: (define_insn "fixunsdfsi2"
632: [(set (match_operand:SI 0 "general_operand" "=g<")
633: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
634: "TARGET_32081"
635: "truncld %1,%0")
636:
637: ;;; These are not yet used by GCC
638: (define_insn "fix_truncsfqi2"
639: [(set (match_operand:QI 0 "general_operand" "=g<")
640: (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
641: "TARGET_32081"
642: "truncfb %1,%0")
643:
644: (define_insn "fix_truncsfhi2"
645: [(set (match_operand:HI 0 "general_operand" "=g<")
646: (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
647: "TARGET_32081"
648: "truncfw %1,%0")
649:
650: (define_insn "fix_truncsfsi2"
651: [(set (match_operand:SI 0 "general_operand" "=g<")
652: (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
653: "TARGET_32081"
654: "truncfd %1,%0")
655:
656: (define_insn "fix_truncdfqi2"
657: [(set (match_operand:QI 0 "general_operand" "=g<")
658: (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
659: "TARGET_32081"
660: "trunclb %1,%0")
661:
662: (define_insn "fix_truncdfhi2"
663: [(set (match_operand:HI 0 "general_operand" "=g<")
664: (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
665: "TARGET_32081"
666: "trunclw %1,%0")
667:
668: (define_insn "fix_truncdfsi2"
669: [(set (match_operand:SI 0 "general_operand" "=g<")
670: (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
671: "TARGET_32081"
672: "truncld %1,%0")
673:
674: ;;- All kinds of add instructions.
675:
676: (define_insn "adddf3"
677: [(set (match_operand:DF 0 "general_operand" "=fm")
678: (plus:DF (match_operand:DF 1 "general_operand" "%0")
679: (match_operand:DF 2 "general_operand" "fmF")))]
680: "TARGET_32081"
681: "addl %2,%0")
682:
683:
684: (define_insn "addsf3"
685: [(set (match_operand:SF 0 "general_operand" "=fm")
686: (plus:SF (match_operand:SF 1 "general_operand" "%0")
687: (match_operand:SF 2 "general_operand" "fmF")))]
688: "TARGET_32081"
689: "addf %2,%0")
690:
691: (define_insn ""
692: [(set (reg:SI 17)
693: (plus:SI (reg:SI 17)
694: (match_operand:SI 0 "immediate_operand" "i")))]
695: "GET_CODE (operands[0]) == CONST_INT"
696: "*
697: {
1.1.1.2 ! root 698: if (INTVAL (operands[0]) == 8)
! 699: return \"cmpd tos,tos # adjsp -8\";
! 700: if (INTVAL (operands[0]) == 4)
! 701: return \"cmpqd %$0,tos # adjsp -4\";
! 702: if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64)
1.1 root 703: return \"adjspb %$%n0\";
704: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
705: return \"adjspw %$%n0\";
706: return \"adjspd %$%n0\";
707: }")
708:
709: (define_insn ""
710: [(set (match_operand:SI 0 "general_operand" "=g<")
711: (plus:SI (reg:SI 16)
712: (match_operand:SI 1 "immediate_operand" "i")))]
713: "GET_CODE (operands[1]) == CONST_INT"
714: "addr %c1(fp),%0")
715:
716: (define_insn ""
717: [(set (match_operand:SI 0 "general_operand" "=g<")
718: (plus:SI (reg:SI 17)
719: (match_operand:SI 1 "immediate_operand" "i")))]
720: "GET_CODE (operands[1]) == CONST_INT"
721: "addr %c1(sp),%0")
722:
723: (define_insn "addsi3"
724: [(set (match_operand:SI 0 "general_operand" "=g,=g<")
725: (plus:SI (match_operand:SI 1 "general_operand" "%0,%r")
726: (match_operand:SI 2 "general_operand" "rmn,n")))]
727: ""
728: "*
729: {
730: if (which_alternative == 1)
731: return \"addr %c2(%1),%0\";
732: if (GET_CODE (operands[2]) == CONST_INT)
733: {
734: int i = INTVAL (operands[2]);
735:
736: if (i <= 7 && i >= -8)
737: return \"addqd %2,%0\";
738: else if (GET_CODE (operands[0]) == REG
739: && i < 0x4000 && i >= -0x4000)
740: return \"addr %c2(%0),%0\";
741: }
742: return \"addd %2,%0\";
743: }")
744:
745: (define_insn "addhi3"
746: [(set (match_operand:HI 0 "general_operand" "=g")
747: (plus:HI (match_operand:HI 1 "general_operand" "%0")
748: (match_operand:HI 2 "general_operand" "g")))]
749: ""
750: "*
751: { if (GET_CODE (operands[2]) == CONST_INT)
752: {
753: int i = INTVAL (operands[2]);
754: if (i <= 7 && i >= -8)
755: return \"addqw %2,%0\";
756: }
757: return \"addw %2,%0\";
758: }")
759:
760: (define_insn ""
761: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
762: (plus:HI (match_operand:HI 1 "general_operand" "0")
763: (match_operand:HI 2 "general_operand" "g")))]
764: ""
765: "*
766: {
767: if (GET_CODE (operands[1]) == CONST_INT
768: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
769: return \"addqw %1,%0\";
770: return \"addw %1,%0\";
771: }")
772:
773: (define_insn "addqi3"
774: [(set (match_operand:QI 0 "general_operand" "=g")
775: (plus:QI (match_operand:QI 1 "general_operand" "%0")
776: (match_operand:QI 2 "general_operand" "g")))]
777: ""
778: "*
779: { if (GET_CODE (operands[2]) == CONST_INT)
780: {
781: int i = INTVAL (operands[2]);
782: if (i <= 7 && i >= -8)
783: return \"addqb %2,%0\";
784: }
785: return \"addb %2,%0\";
786: }")
787:
788: (define_insn ""
789: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
790: (plus:QI (match_operand:QI 1 "general_operand" "0")
791: (match_operand:QI 2 "general_operand" "g")))]
792: ""
793: "*
794: {
795: if (GET_CODE (operands[1]) == CONST_INT
796: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
797: return \"addqb %1,%0\";
798: return \"addb %1,%0\";
799: }")
800:
801: ;;- All kinds of subtract instructions.
802:
803: (define_insn "subdf3"
804: [(set (match_operand:DF 0 "general_operand" "=fm")
805: (minus:DF (match_operand:DF 1 "general_operand" "0")
806: (match_operand:DF 2 "general_operand" "fmF")))]
807: "TARGET_32081"
808: "subl %2,%0")
809:
810: (define_insn "subsf3"
811: [(set (match_operand:SF 0 "general_operand" "=fm")
812: (minus:SF (match_operand:SF 1 "general_operand" "0")
813: (match_operand:SF 2 "general_operand" "fmF")))]
814: "TARGET_32081"
815: "subf %2,%0")
816:
817: (define_insn ""
818: [(set (reg:SI 17)
819: (minus:SI (reg:SI 17)
820: (match_operand:SI 0 "immediate_operand" "i")))]
821: "GET_CODE (operands[0]) == CONST_INT"
822: "*
823: {
824: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64
825: && INTVAL(operands[0]) > -64)
826: return \"adjspb %0\";
827: return \"adjspd %0\";
828: }")
829:
830: (define_insn "subsi3"
831: [(set (match_operand:SI 0 "general_operand" "=g")
832: (minus:SI (match_operand:SI 1 "general_operand" "0")
833: (match_operand:SI 2 "general_operand" "rmn")))]
834: ""
835: "*
836: { if (GET_CODE (operands[2]) == CONST_INT)
837: {
838: int i = INTVAL (operands[2]);
839:
840: if (i <= 8 && i >= -7)
841: return \"addqd %$%n2,%0\";
842: }
843: return \"subd %2,%0\";
844: }")
845:
846: (define_insn "subhi3"
847: [(set (match_operand:HI 0 "general_operand" "=g")
848: (minus:HI (match_operand:HI 1 "general_operand" "0")
849: (match_operand:HI 2 "general_operand" "g")))]
850: ""
851: "*
852: { if (GET_CODE (operands[2]) == CONST_INT)
853: {
854: int i = INTVAL (operands[2]);
855:
856: if (i <= 8 && i >= -7)
857: return \"addqw %$%n2,%0\";
858: }
859: return \"subw %2,%0\";
860: }")
861:
862: (define_insn ""
863: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
864: (minus:HI (match_operand:HI 1 "general_operand" "0")
865: (match_operand:HI 2 "general_operand" "g")))]
866: ""
867: "*
868: {
869: if (GET_CODE (operands[1]) == CONST_INT
870: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
871: return \"addqw %$%n1,%0\";
872: return \"subw %1,%0\";
873: }")
874:
875: (define_insn "subqi3"
876: [(set (match_operand:QI 0 "general_operand" "=g")
877: (minus:QI (match_operand:QI 1 "general_operand" "0")
878: (match_operand:QI 2 "general_operand" "g")))]
879: ""
880: "*
881: { if (GET_CODE (operands[2]) == CONST_INT)
882: {
883: int i = INTVAL (operands[2]);
884:
885: if (i <= 8 && i >= -7)
886: return \"addqb %$%n2,%0\";
887: }
888: return \"subb %2,%0\";
889: }")
890:
891: (define_insn ""
892: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
893: (minus:QI (match_operand:QI 1 "general_operand" "0")
894: (match_operand:QI 2 "general_operand" "g")))]
895: ""
896: "*
897: {
898: if (GET_CODE (operands[1]) == CONST_INT
899: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
900: return \"addqb %$%n1,%0\";
901: return \"subb %1,%0\";
902: }")
903:
904: ;;- Multiply instructions.
905:
906: (define_insn "muldf3"
907: [(set (match_operand:DF 0 "general_operand" "=fm")
908: (mult:DF (match_operand:DF 1 "general_operand" "%0")
909: (match_operand:DF 2 "general_operand" "fmF")))]
910: "TARGET_32081"
911: "mull %2,%0")
912:
913: (define_insn "mulsf3"
914: [(set (match_operand:SF 0 "general_operand" "=fm")
915: (mult:SF (match_operand:SF 1 "general_operand" "%0")
916: (match_operand:SF 2 "general_operand" "fmF")))]
917: "TARGET_32081"
918: "mulf %2,%0")
919:
920: (define_insn "mulsi3"
921: [(set (match_operand:SI 0 "general_operand" "=g")
922: (mult:SI (match_operand:SI 1 "general_operand" "%0")
923: (match_operand:SI 2 "general_operand" "rmn")))]
924: ""
925: "muld %2,%0")
926:
927: (define_insn "mulhi3"
928: [(set (match_operand:HI 0 "general_operand" "=g")
929: (mult:HI (match_operand:HI 1 "general_operand" "%0")
930: (match_operand:HI 2 "general_operand" "g")))]
931: ""
932: "mulw %2,%0")
933:
934: (define_insn "mulqi3"
935: [(set (match_operand:QI 0 "general_operand" "=g")
936: (mult:QI (match_operand:QI 1 "general_operand" "%0")
937: (match_operand:QI 2 "general_operand" "g")))]
938: ""
939: "mulb %2,%0")
940:
941: (define_insn "umulsi3"
942: [(set (match_operand:SI 0 "general_operand" "=g")
943: (umult:SI (match_operand:SI 1 "general_operand" "%0")
944: (match_operand:SI 2 "general_operand" "rmn")))]
945: ""
946: "muld %2,%0")
947:
948: (define_insn "umulhi3"
949: [(set (match_operand:HI 0 "general_operand" "=g")
950: (umult:HI (match_operand:HI 1 "general_operand" "%0")
951: (match_operand:HI 2 "general_operand" "g")))]
952: ""
953: "mulw %2,%0")
954:
955: (define_insn "umulqi3"
956: [(set (match_operand:QI 0 "general_operand" "=g")
957: (umult:QI (match_operand:QI 1 "general_operand" "%0")
958: (match_operand:QI 2 "general_operand" "g")))]
959: ""
960: "mulb %2,%0")
961:
962: (define_insn "umulsidi3"
963: [(set (match_operand:DI 0 "general_operand" "=g")
964: (umult:DI (match_operand:SI 1 "general_operand" "0")
965: (match_operand:SI 2 "general_operand" "rmn")))]
966: ""
967: "meid %2,%0")
968:
969: ;;- Divide instructions.
970:
971: (define_insn "divdf3"
972: [(set (match_operand:DF 0 "general_operand" "=fm")
973: (div:DF (match_operand:DF 1 "general_operand" "0")
974: (match_operand:DF 2 "general_operand" "fmF")))]
975: "TARGET_32081"
976: "divl %2,%0")
977:
978: (define_insn "divsf3"
979: [(set (match_operand:SF 0 "general_operand" "=fm")
980: (div:SF (match_operand:SF 1 "general_operand" "0")
981: (match_operand:SF 2 "general_operand" "fmF")))]
982: "TARGET_32081"
983: "divf %2,%0")
984:
985: (define_insn "divsi3"
986: [(set (match_operand:SI 0 "general_operand" "=g")
987: (div:SI (match_operand:SI 1 "general_operand" "0")
988: (match_operand:SI 2 "general_operand" "rmn")))]
989: ""
990: "quod %2,%0")
991:
992: (define_insn "divhi3"
993: [(set (match_operand:HI 0 "general_operand" "=g")
994: (div:HI (match_operand:HI 1 "general_operand" "0")
995: (match_operand:HI 2 "general_operand" "g")))]
996: ""
997: "quow %2,%0")
998:
999: (define_insn "divqi3"
1000: [(set (match_operand:QI 0 "general_operand" "=g")
1001: (div:QI (match_operand:QI 1 "general_operand" "0")
1002: (match_operand:QI 2 "general_operand" "g")))]
1003: ""
1004: "quob %2,%0")
1005:
1006: (define_insn "udivsi3"
1007: [(set (match_operand:SI 0 "register_operand" "=r")
1008: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1009: (match_operand:SI 2 "general_operand" "rmn")))]
1010: ""
1011: "*
1012: {
1013: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1014: return \"deid %2,%0\;movd %1,%0\";
1015: }")
1016:
1017: (define_insn "udivhi3"
1018: [(set (match_operand:HI 0 "register_operand" "=r")
1019: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1020: (match_operand:HI 2 "general_operand" "g")))]
1021: ""
1022: "*
1023: {
1024: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
1025: return \"deiw %2,%0\;movw %1,%0\";
1026: }")
1027:
1028: (define_insn "udivqi3"
1029: [(set (match_operand:QI 0 "register_operand" "=r")
1030: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1031: (match_operand:QI 2 "general_operand" "g")))]
1032: ""
1033: "*
1034: {
1035: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
1036: return \"deib %2,%0\;movb %1,%0\";
1037: }")
1038:
1039: ;; Remainder instructions.
1040:
1041: (define_insn "modsi3"
1042: [(set (match_operand:SI 0 "general_operand" "=g")
1043: (mod:SI (match_operand:SI 1 "general_operand" "0")
1044: (match_operand:SI 2 "general_operand" "rmn")))]
1045: ""
1046: "remd %2,%0")
1047:
1048: (define_insn "modhi3"
1049: [(set (match_operand:HI 0 "general_operand" "=g")
1050: (mod:HI (match_operand:HI 1 "general_operand" "0")
1051: (match_operand:HI 2 "general_operand" "g")))]
1052: ""
1053: "remw %2,%0")
1054:
1055: (define_insn "modqi3"
1056: [(set (match_operand:QI 0 "general_operand" "=g")
1057: (mod:QI (match_operand:QI 1 "general_operand" "0")
1058: (match_operand:QI 2 "general_operand" "g")))]
1059: ""
1060: "remb %2,%0")
1061:
1062: (define_insn "umodsi3"
1063: [(set (match_operand:SI 0 "register_operand" "=r")
1064: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1065: (match_operand:SI 2 "general_operand" "rmn")))]
1066: ""
1067: "deid %2,%0")
1068:
1069: (define_insn "umodhi3"
1070: [(set (match_operand:HI 0 "register_operand" "=r")
1071: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1072: (match_operand:HI 2 "general_operand" "g")))]
1073: ""
1074: "deiw %2,%0")
1075:
1076: (define_insn "umodqi3"
1077: [(set (match_operand:QI 0 "register_operand" "=r")
1078: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1079: (match_operand:QI 2 "general_operand" "g")))]
1080: ""
1081: "deib %2,%0")
1082:
1083: ; This isn't be usable in its current form.
1084: ;(define_insn "udivmoddisi4"
1085: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1086: ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1087: ; (match_operand:SI 2 "general_operand" "rmn")))
1088: ; (set (subreg:SI (match_dup 0) 0)
1089: ; (umod:SI (match_dup 1) (match_dup 2)))]
1090: ; ""
1091: ; "deid %2,%0")
1092:
1093: ;;- Logical Instructions: AND
1094:
1095: (define_insn "andsi3"
1096: [(set (match_operand:SI 0 "general_operand" "=g")
1097: (and:SI (match_operand:SI 1 "general_operand" "%0")
1098: (match_operand:SI 2 "general_operand" "rmn")))]
1099: ""
1100: "*
1101: {
1102: if (GET_CODE (operands[2]) == CONST_INT)
1103: {
1104: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1105: {
1106: if (INTVAL (operands[2]) == 0xffffff00)
1107: return \"movqb %$0,%0\";
1108: else
1109: {
1110: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1111: INTVAL (operands[2]) & 0xff);
1112: return \"andb %2,%0\";
1113: }
1114: }
1115: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1116: {
1117: if (INTVAL (operands[2]) == 0xffff0000)
1118: return \"movqw %$0,%0\";
1119: else
1120: {
1121: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1122: INTVAL (operands[2]) & 0xffff);
1123: return \"andw %2,%0\";
1124: }
1125: }
1126: }
1127: return \"andd %2,%0\";
1128: }")
1129:
1130: (define_insn "andhi3"
1131: [(set (match_operand:HI 0 "general_operand" "=g")
1132: (and:HI (match_operand:HI 1 "general_operand" "%0")
1133: (match_operand:HI 2 "general_operand" "g")))]
1134: ""
1135: "*
1136: {
1137: if (GET_CODE (operands[2]) == CONST_INT
1138: && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1139: {
1140: if (INTVAL (operands[2]) == 0xffffff00)
1141: return \"movqb %$0,%0\";
1142: else
1143: {
1144: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1145: INTVAL (operands[2]) & 0xff);
1146: return \"andb %2,%0\";
1147: }
1148: }
1149: return \"andw %2,%0\";
1150: }")
1151:
1152: (define_insn "andqi3"
1153: [(set (match_operand:QI 0 "general_operand" "=g")
1154: (and:QI (match_operand:QI 1 "general_operand" "%0")
1155: (match_operand:QI 2 "general_operand" "g")))]
1156: ""
1157: "andb %2,%0")
1158:
1159: (define_insn "andcbsi3"
1160: [(set (match_operand:SI 0 "general_operand" "=g")
1161: (and:SI (match_operand:SI 1 "general_operand" "0")
1162: (not:SI (match_operand:SI 2 "general_operand" "rmn"))))]
1163: ""
1164: "*
1165: {
1166: if (GET_CODE (operands[2]) == CONST_INT)
1167: {
1168: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1169: return \"bicb %2,%0\";
1170: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1171: return \"bicw %2,%0\";
1172: }
1173: return \"bicd %2,%0\";
1174: }")
1175:
1176: (define_insn ""
1177: [(set (match_operand:SI 0 "general_operand" "=g")
1178: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1179: (match_operand:SI 2 "general_operand" "0")))]
1180: ""
1181: "*
1182: {
1183: if (GET_CODE (operands[1]) == CONST_INT)
1184: {
1185: if ((INTVAL (operands[1]) & 0xffffff00) == 0)
1186: return \"bicb %1,%0\";
1187: if ((INTVAL (operands[1]) & 0xffff0000) == 0)
1188: return \"bicw %1,%0\";
1189: }
1190: return \"bicd %1,%0\";
1191: }")
1192:
1193: (define_insn "andcbhi3"
1194: [(set (match_operand:HI 0 "general_operand" "=g")
1195: (and:HI (match_operand:HI 1 "general_operand" "%0")
1196: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
1197: ""
1198: "*
1199: {
1200: if (GET_CODE (operands[2]) == CONST_INT
1201: && (INTVAL (operands[2]) & 0xffffff00) == 0)
1202: return \"bicb %2,%0\";
1203: return \"bicw %2,%0\";
1204: }")
1205:
1206: (define_insn ""
1207: [(set (match_operand:HI 0 "general_operand" "=g")
1208: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1209: (match_operand:HI 2 "general_operand" "0")))]
1210: ""
1211: "*
1212: {
1213: if (GET_CODE (operands[1]) == CONST_INT
1214: && (INTVAL (operands[1]) & 0xffffff00) == 0)
1215: return \"bicb %1,%0\";
1216: return \"bicw %1,%0\";
1217: }")
1218:
1219: (define_insn "andcbqi3"
1220: [(set (match_operand:QI 0 "general_operand" "=g")
1221: (and:QI (match_operand:QI 1 "general_operand" "%0")
1222: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
1223: ""
1224: "bicb %2,%0")
1225:
1226: (define_insn ""
1227: [(set (match_operand:QI 0 "general_operand" "=g")
1228: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1229: (match_operand:QI 2 "general_operand" "0")))]
1230: ""
1231: "bicb %1,%0")
1232:
1233: ;;- Bit set instructions.
1234:
1235: (define_insn "iorsi3"
1236: [(set (match_operand:SI 0 "general_operand" "=g")
1237: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1238: (match_operand:SI 2 "general_operand" "rmn")))]
1239: ""
1240: "*
1241: {
1242: if (GET_CODE (operands[2]) == CONST_INT) {
1243: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1244: return \"orb %2,%0\";
1245: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1246: return \"orw %2,%0\";
1247: }
1248: return \"ord %2,%0\";
1249: }")
1250:
1251: (define_insn "iorhi3"
1252: [(set (match_operand:HI 0 "general_operand" "=g")
1253: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1254: (match_operand:HI 2 "general_operand" "g")))]
1255: ""
1256: "*
1257: {
1258: if (GET_CODE(operands[2]) == CONST_INT &&
1259: (INTVAL(operands[2]) & 0xffffff00) == 0)
1260: return \"orb %2,%0\";
1261: return \"orw %2,%0\";
1262: }")
1263:
1264: (define_insn "iorqi3"
1265: [(set (match_operand:QI 0 "general_operand" "=g")
1266: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1267: (match_operand:QI 2 "general_operand" "g")))]
1268: ""
1269: "orb %2,%0")
1270:
1271: ;;- xor instructions.
1272:
1273: (define_insn "xorsi3"
1274: [(set (match_operand:SI 0 "general_operand" "=g")
1275: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1276: (match_operand:SI 2 "general_operand" "rmn")))]
1277: ""
1278: "*
1279: {
1280: if (GET_CODE (operands[2]) == CONST_INT) {
1281: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1282: return \"xorb %2,%0\";
1283: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1284: return \"xorw %2,%0\";
1285: }
1286: return \"xord %2,%0\";
1287: }")
1288:
1289: (define_insn "xorhi3"
1290: [(set (match_operand:HI 0 "general_operand" "=g")
1291: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1292: (match_operand:HI 2 "general_operand" "g")))]
1293: ""
1294: "*
1295: {
1296: if (GET_CODE(operands[2]) == CONST_INT &&
1297: (INTVAL(operands[2]) & 0xffffff00) == 0)
1298: return \"xorb %2,%0\";
1299: return \"xorw %2,%0\";
1300: }")
1301:
1302: (define_insn "xorqi3"
1303: [(set (match_operand:QI 0 "general_operand" "=g")
1304: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1305: (match_operand:QI 2 "general_operand" "g")))]
1306: ""
1307: "xorb %2,%0")
1308:
1309: (define_insn "negdf2"
1310: [(set (match_operand:DF 0 "general_operand" "=fm<")
1311: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1312: "TARGET_32081"
1313: "negl %1,%0")
1314:
1315: (define_insn "negsf2"
1316: [(set (match_operand:SF 0 "general_operand" "=fm<")
1317: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1318: "TARGET_32081"
1319: "negf %1,%0")
1320:
1321: (define_insn "negsi2"
1322: [(set (match_operand:SI 0 "general_operand" "=g<")
1323: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1324: ""
1325: "negd %1,%0")
1326:
1327: (define_insn "neghi2"
1328: [(set (match_operand:HI 0 "general_operand" "=g<")
1329: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1330: ""
1331: "negw %1,%0")
1332:
1333: (define_insn "negqi2"
1334: [(set (match_operand:QI 0 "general_operand" "=g<")
1335: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1336: ""
1337: "negb %1,%0")
1338:
1339: (define_insn "one_cmplsi2"
1340: [(set (match_operand:SI 0 "general_operand" "=g<")
1341: (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1342: ""
1343: "comd %1,%0")
1344:
1345: (define_insn "one_cmplhi2"
1346: [(set (match_operand:HI 0 "general_operand" "=g<")
1347: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1348: ""
1349: "comw %1,%0")
1350:
1351: (define_insn "one_cmplqi2"
1352: [(set (match_operand:QI 0 "general_operand" "=g<")
1353: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1354: ""
1355: "comb %1,%0")
1356:
1357: ;; arithmetic left and right shift operations
1358:
1359: (define_insn "ashlsi3"
1360: [(set (match_operand:SI 0 "general_operand" "=g,g")
1361: (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1362: (match_operand:SI 2 "general_operand" "I,rmn")))]
1363: ""
1364: "* output_shift_insn (operands);")
1365:
1366: (define_insn "ashlhi3"
1367: [(set (match_operand:HI 0 "general_operand" "=g")
1368: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1369: (match_operand:SI 2 "general_operand" "rmn")))]
1370: ""
1371: "*
1372: { if (GET_CODE (operands[2]) == CONST_INT)
1373: if (INTVAL (operands[2]) == 1)
1374: return \"addw %1,%0\";
1375: else if (INTVAL (operands[2]) == 2)
1376: return \"addw %1,%0\;addw %0,%0\";
1377: return \"ashw %2,%0\";
1378: }")
1379:
1380: (define_insn "ashlqi3"
1381: [(set (match_operand:QI 0 "general_operand" "=g")
1382: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1383: (match_operand:SI 2 "general_operand" "rmn")))]
1384: ""
1385: "*
1386: { if (GET_CODE (operands[2]) == CONST_INT)
1387: if (INTVAL (operands[2]) == 1)
1388: return \"addb %1,%0\";
1389: else if (INTVAL (operands[2]) == 2)
1390: return \"addb %1,%0\;addb %0,%0\";
1391: return \"ashb %2,%0\";
1392: }")
1393:
1394: ;; Arithmetic right shift on the 32k works by negating the shift count.
1395: (define_expand "ashrsi3"
1396: [(set (match_operand:SI 0 "general_operand" "=g")
1397: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1398: (match_operand:SI 2 "general_operand" "g")))]
1399: ""
1400: "
1401: {
1402: operands[2] = negate_rtx (SImode, operands[2]);
1403: }")
1404:
1405: (define_expand "ashrhi3"
1406: [(set (match_operand:HI 0 "general_operand" "=g")
1407: (ashift:HI (match_operand:HI 1 "general_operand" "g")
1408: (match_operand:SI 2 "general_operand" "g")))]
1409: ""
1410: "
1411: {
1412: operands[2] = negate_rtx (SImode, operands[2]);
1413: }")
1414:
1415: (define_expand "ashrqi3"
1416: [(set (match_operand:QI 0 "general_operand" "=g")
1417: (ashift:QI (match_operand:QI 1 "general_operand" "g")
1418: (match_operand:SI 2 "general_operand" "g")))]
1419: ""
1420: "
1421: {
1422: operands[2] = negate_rtx (SImode, operands[2]);
1423: }")
1424:
1425: ;; logical shift instructions
1426:
1427: (define_insn "lshlsi3"
1428: [(set (match_operand:SI 0 "general_operand" "=g")
1429: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1430: (match_operand:SI 2 "general_operand" "rmn")))]
1431: ""
1432: "lshd %2,%0")
1433:
1434: (define_insn "lshlhi3"
1435: [(set (match_operand:HI 0 "general_operand" "=g")
1436: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1437: (match_operand:SI 2 "general_operand" "rmn")))]
1438: ""
1439: "lshw %2,%0")
1440:
1441: (define_insn "lshlqi3"
1442: [(set (match_operand:QI 0 "general_operand" "=g")
1443: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1444: (match_operand:SI 2 "general_operand" "rmn")))]
1445: ""
1446: "lshb %2,%0")
1447:
1448: ;; Logical right shift on the 32k works by negating the shift count.
1449: (define_expand "lshrsi3"
1450: [(set (match_operand:SI 0 "general_operand" "=g")
1451: (lshift:SI (match_operand:SI 1 "general_operand" "g")
1452: (match_operand:SI 2 "general_operand" "g")))]
1453: ""
1454: "
1455: {
1456: operands[2] = negate_rtx (SImode, operands[2]);
1457: }")
1458:
1459: (define_expand "lshrhi3"
1460: [(set (match_operand:HI 0 "general_operand" "=g")
1461: (lshift:HI (match_operand:HI 1 "general_operand" "g")
1462: (match_operand:SI 2 "general_operand" "g")))]
1463: ""
1464: "
1465: {
1466: operands[2] = negate_rtx (SImode, operands[2]);
1467: }")
1468:
1469: (define_expand "lshrqi3"
1470: [(set (match_operand:QI 0 "general_operand" "=g")
1471: (lshift:QI (match_operand:QI 1 "general_operand" "g")
1472: (match_operand:SI 2 "general_operand" "g")))]
1473: ""
1474: "
1475: {
1476: operands[2] = negate_rtx (SImode, operands[2]);
1477: }")
1478:
1479: ;; Rotate instructions
1480:
1481: (define_insn "rotlsi3"
1482: [(set (match_operand:SI 0 "general_operand" "=g")
1483: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1484: (match_operand:SI 2 "general_operand" "rmn")))]
1485: ""
1486: "rotd %2,%0")
1487:
1488: (define_insn "rotlhi3"
1489: [(set (match_operand:HI 0 "general_operand" "=g")
1490: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1491: (match_operand:SI 2 "general_operand" "rmn")))]
1492: ""
1493: "rotw %2,%0")
1494:
1495: (define_insn "rotlqi3"
1496: [(set (match_operand:QI 0 "general_operand" "=g")
1497: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1498: (match_operand:SI 2 "general_operand" "rmn")))]
1499: ""
1500: "rotb %2,%0")
1501:
1502: ;; Right rotate on the 32k works by negating the shift count.
1503: (define_expand "rotrsi3"
1504: [(set (match_operand:SI 0 "general_operand" "=g")
1505: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1506: (match_operand:SI 2 "general_operand" "g")))]
1507: ""
1508: "
1509: {
1510: operands[2] = negate_rtx (SImode, operands[2]);
1511: }")
1512:
1513: (define_expand "rotrhi3"
1514: [(set (match_operand:HI 0 "general_operand" "=g")
1515: (rotate:HI (match_operand:HI 1 "general_operand" "g")
1516: (match_operand:SI 2 "general_operand" "g")))]
1517: ""
1518: "
1519: {
1520: operands[2] = negate_rtx (SImode, operands[2]);
1521: }")
1522:
1523: (define_expand "rotrqi3"
1524: [(set (match_operand:QI 0 "general_operand" "=g")
1525: (rotate:QI (match_operand:QI 1 "general_operand" "g")
1526: (match_operand:SI 2 "general_operand" "g")))]
1527: ""
1528: "
1529: {
1530: operands[2] = negate_rtx (SImode, operands[2]);
1531: }")
1532:
1533: ;;- load or push effective address
1534: ;; These come after the move, add, and multiply patterns
1535: ;; because we don't want pushl $1 turned into pushad 1.
1536:
1537: (define_insn ""
1538: [(set (match_operand:SI 0 "general_operand" "=g<")
1539: (match_operand:QI 1 "address_operand" "p"))]
1540: ""
1541: "*
1542: {
1543: if (REG_P (operands[0])
1544: && GET_CODE (operands[1]) == MULT
1545: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1546: && (INTVAL (XEXP (operands[1], 1)) == 2
1547: || INTVAL (XEXP (operands[1], 1)) == 4))
1548: {
1549: rtx xoperands[3];
1550: xoperands[0] = operands[0];
1551: xoperands[1] = XEXP (operands[1], 0);
1552: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
1553: return output_shift_insn (xoperands);
1554: }
1555: return \"addr %a1,%0\";
1556: }")
1557:
1558: ;;; Index insns. These are about the same speed as multiply-add counterparts.
1559: ;;; but slower then using power-of-2 shifts if we can use them
1560: ;
1561: ;(define_insn ""
1562: ; [(set (match_operand:SI 0 "register_operand" "=r")
1563: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1564: ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1565: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1566: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1567: ; "indexd %0,%3,%1")
1568: ;
1569: ;(define_insn ""
1570: ; [(set (match_operand:SI 0 "register_operand" "=r")
1571: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1572: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1573: ; (match_operand:SI 3 "general_operand" "rmn")))]
1574: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1575: ; "indexd %0,%2,%3")
1576:
1577: ;; Set, Clear, and Invert bit
1578:
1579: (define_insn ""
1580: [(set (match_operand:SI 0 "general_operand" "=g")
1581: (ior:SI
1582: (ashift:SI (const_int 1)
1583: (match_operand:SI 1 "general_operand" "rmn"))
1584: (match_dup 0)))]
1585: ""
1586: "sbitd %1,%0")
1587:
1588: (define_insn ""
1589: [(set (match_operand:SI 0 "general_operand" "=g")
1590: (ior:SI
1591: (match_dup 0)
1592: (ashift:SI (const_int 1)
1593: (match_operand:SI 1 "general_operand" "rmn"))))]
1594: ""
1595: "sbitd %1,%0")
1596:
1597: (define_insn ""
1598: [(set (match_operand:QI 0 "general_operand" "=g")
1599: (ior:QI
1600: (subreg:QI
1601: (ashift:SI (const_int 1)
1602: (match_operand:QI 1 "general_operand" "rmn")) 0)
1603: (match_dup 0)))]
1604: ""
1605: "sbitb %1,%0")
1606:
1607: (define_insn ""
1608: [(set (match_operand:QI 0 "general_operand" "=g")
1609: (ior:QI
1610: (match_dup 0)
1611: (subreg:QI
1612: (ashift:SI (const_int 1)
1613: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1614: ""
1615: "sbitb %1,%0")
1616:
1617: (define_insn ""
1618: [(set (match_operand:SI 0 "general_operand" "=g")
1619: (and:SI
1620: (not:SI
1621: (ashift:SI (const_int 1)
1622: (match_operand:SI 1 "general_operand" "rmn")))
1623: (match_dup 0)))]
1624: ""
1625: "cbitd %1,%0")
1626:
1627: (define_insn ""
1628: [(set (match_operand:SI 0 "general_operand" "=g")
1629: (and:SI
1630: (match_dup 0)
1631: (not:SI
1632: (ashift:SI (const_int 1)
1633: (match_operand:SI 1 "general_operand" "rmn")))))]
1634: ""
1635: "cbitd %1,%0")
1636:
1637: (define_insn ""
1638: [(set (match_operand:QI 0 "general_operand" "=g")
1639: (and:QI
1640: (subreg:QI
1641: (not:SI
1642: (ashift:SI (const_int 1)
1643: (match_operand:QI 1 "general_operand" "rmn"))) 0)
1644: (match_dup 0)))]
1645: ""
1646: "cbitb %1,%0")
1647:
1648: (define_insn ""
1649: [(set (match_operand:QI 0 "general_operand" "=g")
1650: (and:QI
1651: (match_dup 0)
1652: (subreg:QI
1653: (not:SI
1654: (ashift:SI (const_int 1)
1655: (match_operand:QI 1 "general_operand" "rmn"))) 0)))]
1656: ""
1657: "cbitb %1,%0")
1658:
1659: (define_insn ""
1660: [(set (match_operand:SI 0 "general_operand" "=g")
1661: (xor:SI
1662: (ashift:SI (const_int 1)
1663: (match_operand:SI 1 "general_operand" "rmn"))
1664: (match_dup 0)))]
1665: ""
1666: "ibitd %1,%0")
1667:
1668: (define_insn ""
1669: [(set (match_operand:SI 0 "general_operand" "=g")
1670: (xor:SI
1671: (match_dup 0)
1672: (ashift:SI (const_int 1)
1673: (match_operand:SI 1 "general_operand" "rmn"))))]
1674: ""
1675: "ibitd %1,%0")
1676:
1677: (define_insn ""
1678: [(set (match_operand:QI 0 "general_operand" "=g")
1679: (xor:QI
1680: (subreg:QI
1681: (ashift:SI (const_int 1)
1682: (match_operand:QI 1 "general_operand" "rmn")) 0)
1683: (match_dup 0)))]
1684: ""
1685: "ibitb %1,%0")
1686:
1687: (define_insn ""
1688: [(set (match_operand:QI 0 "general_operand" "=g")
1689: (xor:QI
1690: (match_dup 0)
1691: (subreg:QI
1692: (ashift:SI (const_int 1)
1693: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1694: ""
1695: "ibitb %1,%0")
1696:
1697: ;; Recognize jbs and jbc instructions.
1698:
1699: (define_insn ""
1700: [(set (cc0)
1701: (zero_extract (match_operand:SI 0 "general_operand" "rm")
1702: (const_int 1)
1703: (match_operand:SI 1 "general_operand" "rmn")))]
1704: ""
1705: "*
1706: { cc_status.flags = CC_Z_IN_F;
1707: return \"tbitd %1,%0\";
1708: }")
1709:
1710: (define_insn ""
1711: [(set (cc0)
1712: (compare (zero_extract (match_operand:SI 0 "general_operand" "rm")
1713: (const_int 1)
1714: (match_operand:SI 1 "general_operand" "rmn"))
1715: (const_int 1)))]
1716: ""
1717: "*
1718: { cc_status.flags = CC_Z_IN_NOT_F;
1719: return \"tbitd %1,%0\";
1720: }")
1721:
1722: (define_insn ""
1723: [(set (cc0)
1724: (zero_extract (match_operand:HI 0 "general_operand" "g")
1725: (const_int 1)
1726: (match_operand:HI 1 "general_operand" "g")))]
1727: ""
1728: "*
1729: { cc_status.flags = CC_Z_IN_F;
1730: return \"tbitw %1,%0\";
1731: }")
1732:
1733: (define_insn ""
1734: [(set (cc0)
1735: (compare (zero_extract (match_operand:HI 0 "general_operand" "g")
1736: (const_int 1)
1737: (match_operand:HI 1 "general_operand" "rmn"))
1738: (const_int 1)))]
1739: ""
1740: "*
1741: { cc_status.flags = CC_Z_IN_NOT_F;
1742: return \"tbitw %1,%0\";
1743: }")
1744:
1745: (define_insn ""
1746: [(set (cc0)
1747: (zero_extract (match_operand:QI 0 "general_operand" "g")
1748: (const_int 1)
1749: (match_operand:QI 1 "general_operand" "g")))]
1750: ""
1751: "*
1752: { cc_status.flags = CC_Z_IN_F;
1753: return \"tbitb %1,%0\";
1754: }")
1755:
1756: (define_insn ""
1757: [(set (cc0)
1758: (compare (zero_extract:SI (match_operand:QI 0 "general_operand" "g")
1759: (const_int 1)
1760: (match_operand:QI 1 "general_operand" "rmn"))
1761: (const_int 1)))]
1762: ""
1763: "*
1764: { cc_status.flags = CC_Z_IN_NOT_F;
1765: return \"tbitb %1,%0\";
1766: }")
1767:
1768: (define_insn ""
1769: [(set (cc0)
1770: (and:SI (match_operand:SI 0 "general_operand" "rm")
1771: (match_operand:SI 1 "immediate_operand" "i")))]
1772: "GET_CODE (operands[1]) == CONST_INT
1773: && exact_log2 (INTVAL (operands[1])) >= 0"
1774: "*
1775: {
1776: operands[1]
1777: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1778: cc_status.flags = CC_Z_IN_F;
1779: return \"tbitd %1,%0\";
1780: }")
1781:
1782: ;; extract(base, width, offset)
1783: ;; Signed bitfield extraction is not supported in hardware on the
1784: ;; NS 32032. It is therefore better to let GCC figure out a
1785: ;; good strategy for generating the proper instruction sequence
1786: ;; and represent it as rtl.
1787:
1788: ;; Optimize the case of extracting a byte or word from a register.
1789: ;; Otherwise we must load a register with the offset of the
1790: ;; chunk we want, and perform an extract insn (each of which
1791: ;; is very expensive). Since we use the stack to do our bit-twiddling
1792: ;; we cannot use it for a destination. Perhaps things are fast
1793: ;; enough on the 32532 that such hacks are not needed.
1794:
1795: (define_insn ""
1796: [(set (match_operand:SI 0 "general_operand" "=ro")
1797: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1798: (match_operand:SI 2 "const_int" "i")
1799: (match_operand:SI 3 "const_int" "i")))]
1800: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1801: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
1802: "*
1803: {
1804: output_asm_insn (\"movd %1,tos\", operands);
1805: if (INTVAL (operands[2]) == 16)
1806: {
1807: if (INTVAL (operands[3]) == 8)
1808: output_asm_insn (\"movzwd 1(sp),%0\", operands);
1809: else
1810: output_asm_insn (\"movzwd 2(sp),%0\", operands);
1811: }
1812: else
1813: {
1814: if (INTVAL (operands[3]) == 8)
1815: output_asm_insn (\"movzbd 1(sp),%0\", operands);
1816: else if (INTVAL (operands[3]) == 16)
1817: output_asm_insn (\"movzbd 2(sp),%0\", operands);
1818: else
1819: output_asm_insn (\"movzbd 3(sp),%0\", operands);
1820: }
1821: return \"cmpqd %$0,tos # adjsp -4\";
1822: }")
1823:
1824: (define_insn ""
1825: [(set (match_operand:SI 0 "general_operand" "=ro")
1826: (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
1827: (match_operand:SI 2 "const_int" "i")
1828: (match_operand:SI 3 "const_int" "i")))]
1829: "INTVAL (operands[2]) == 8 && INTVAL (operands[3]) == 8"
1830: "movw %1,tos\;movzbd 1(sp),%0\;adjspb %$-2")
1831:
1832: (define_insn "extzv"
1833: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1834: (zero_extract:SI (match_operand:SI 1 "general_operand" "rm,o")
1835: (match_operand:SI 2 "const_int" "i,i")
1836: (match_operand:SI 3 "general_operand" "rK,n")))]
1837: ""
1838: "*
1839: { if (GET_CODE (operands[3]) == CONST_INT)
1840: {
1841: if (INTVAL (operands[3]) >= 8)
1842: operands[1] = adj_offsettable_operand (operands[1],
1843: INTVAL (operands[3]) >> 3);
1844: return \"extsd %1,%0,%3,%2\";
1845: }
1846: else return \"extd %3,%1,%0,%2\";
1847: }")
1848:
1849: (define_insn ""
1850: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1851: (zero_extract:SI (match_operand:HI 1 "general_operand" "rm,o")
1852: (match_operand:SI 2 "const_int" "i,i")
1853: (match_operand:SI 3 "general_operand" "rK,n")))]
1854: ""
1855: "*
1856: { if (GET_CODE (operands[3]) == CONST_INT)
1857: {
1858: if (INTVAL (operands[3]) >= 8)
1859: operands[1] = adj_offsettable_operand (operands[1],
1860: INTVAL (operands[3]) >> 3);
1861: return \"extsd %1,%0,%3,%2\";
1862: }
1863: else return \"extd %3,%1,%0,%2\";
1864: }")
1865:
1866: (define_insn ""
1867: [(set (match_operand:SI 0 "general_operand" "=g<")
1868: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1869: (match_operand:SI 2 "const_int" "i")
1870: (match_operand:SI 3 "general_operand" "rn")))]
1871: ""
1872: "*
1873: { if (GET_CODE (operands[3]) == CONST_INT)
1874: return \"extsd %1,%0,%3,%2\";
1875: else return \"extd %3,%1,%0,%2\";
1876: }")
1877:
1878: (define_insn "insv"
1879: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g,o")
1880: (match_operand:SI 1 "const_int" "i,i")
1881: (match_operand:SI 2 "general_operand" "rK,n"))
1882: (match_operand:SI 3 "general_operand" "rm,rm"))]
1883: ""
1884: "*
1885: { if (GET_CODE (operands[2]) == CONST_INT)
1886: {
1887: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
1888: {
1889: operands[0] = adj_offsettable_operand (operands[0],
1890: INTVAL (operands[2]) / 8);
1891: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1892: }
1893: if (INTVAL (operands[1]) <= 8)
1894: return \"inssb %3,%0,%2,%1\";
1895: else if (INTVAL (operands[1]) <= 16)
1896: return \"inssw %3,%0,%2,%1\";
1897: else
1898: return \"inssd %3,%0,%2,%1\";
1899: }
1900: return \"insd %2,%3,%0,%1\";
1901: }")
1902:
1903: (define_insn ""
1904: [(set (zero_extract:SI (match_operand:HI 0 "general_operand" "+g,o")
1905: (match_operand:SI 1 "const_int" "i,i")
1906: (match_operand:SI 2 "general_operand" "rK,n"))
1907: (match_operand:SI 3 "general_operand" "rm,rm"))]
1908: ""
1909: "*
1910: { if (GET_CODE (operands[2]) == CONST_INT)
1911: {
1912: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
1913: {
1914: operands[0] = adj_offsettable_operand (operands[0],
1915: INTVAL (operands[2]) / 8);
1916: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1917: }
1918: if (INTVAL (operands[1]) <= 8)
1919: return \"inssb %3,%0,%2,%1\";
1920: else if (INTVAL (operands[1]) <= 16)
1921: return \"inssw %3,%0,%2,%1\";
1922: else
1923: return \"inssd %3,%0,%2,%1\";
1924: }
1925: return \"insd %2,%3,%0,%1\";
1926: }")
1927:
1928: (define_insn ""
1929: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "=g")
1930: (match_operand:SI 1 "const_int" "i")
1931: (match_operand:SI 2 "general_operand" "rn"))
1932: (match_operand:SI 3 "general_operand" "rm"))]
1933: ""
1934: "*
1935: { if (GET_CODE (operands[2]) == CONST_INT)
1936: if (INTVAL (operands[1]) <= 8)
1937: return \"inssb %3,%0,%2,%1\";
1938: else if (INTVAL (operands[1]) <= 16)
1939: return \"inssw %3,%0,%2,%1\";
1940: else
1941: return \"inssd %3,%0,%2,%1\";
1942: return \"insd %2,%3,%0,%1\";
1943: }")
1944:
1945:
1946: (define_insn "jump"
1947: [(set (pc)
1948: (label_ref (match_operand 0 "" "")))]
1949: ""
1950: "br %l0")
1951:
1952: (define_insn "beq"
1953: [(set (pc)
1954: (if_then_else (eq (cc0)
1955: (const_int 0))
1956: (label_ref (match_operand 0 "" ""))
1957: (pc)))]
1958: ""
1959: "*
1960: { if (cc_prev_status.flags & CC_Z_IN_F)
1961: return \"bfc %l0\";
1962: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1963: return \"bfs %l0\";
1964: else return \"beq %l0\";
1965: }")
1966:
1967: (define_insn "bne"
1968: [(set (pc)
1969: (if_then_else (ne (cc0)
1970: (const_int 0))
1971: (label_ref (match_operand 0 "" ""))
1972: (pc)))]
1973: ""
1974: "*
1975: { if (cc_prev_status.flags & CC_Z_IN_F)
1976: return \"bfs %l0\";
1977: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1978: return \"bfc %l0\";
1979: else return \"bne %l0\";
1980: }")
1981:
1982: (define_insn "bgt"
1983: [(set (pc)
1984: (if_then_else (gt (cc0)
1985: (const_int 0))
1986: (label_ref (match_operand 0 "" ""))
1987: (pc)))]
1988: ""
1989: "bgt %l0")
1990:
1991: (define_insn "bgtu"
1992: [(set (pc)
1993: (if_then_else (gtu (cc0)
1994: (const_int 0))
1995: (label_ref (match_operand 0 "" ""))
1996: (pc)))]
1997: ""
1998: "bhi %l0")
1999:
2000: (define_insn "blt"
2001: [(set (pc)
2002: (if_then_else (lt (cc0)
2003: (const_int 0))
2004: (label_ref (match_operand 0 "" ""))
2005: (pc)))]
2006: ""
2007: "blt %l0")
2008:
2009: (define_insn "bltu"
2010: [(set (pc)
2011: (if_then_else (ltu (cc0)
2012: (const_int 0))
2013: (label_ref (match_operand 0 "" ""))
2014: (pc)))]
2015: ""
2016: "blo %l0")
2017:
2018: (define_insn "bge"
2019: [(set (pc)
2020: (if_then_else (ge (cc0)
2021: (const_int 0))
2022: (label_ref (match_operand 0 "" ""))
2023: (pc)))]
2024: ""
2025: "bge %l0")
2026:
2027: (define_insn "bgeu"
2028: [(set (pc)
2029: (if_then_else (geu (cc0)
2030: (const_int 0))
2031: (label_ref (match_operand 0 "" ""))
2032: (pc)))]
2033: ""
2034: "bhs %l0")
2035:
2036: (define_insn "ble"
2037: [(set (pc)
2038: (if_then_else (le (cc0)
2039: (const_int 0))
2040: (label_ref (match_operand 0 "" ""))
2041: (pc)))]
2042: ""
2043: "ble %l0")
2044:
2045: (define_insn "bleu"
2046: [(set (pc)
2047: (if_then_else (leu (cc0)
2048: (const_int 0))
2049: (label_ref (match_operand 0 "" ""))
2050: (pc)))]
2051: ""
2052: "bls %l0")
2053:
2054: (define_insn ""
2055: [(set (pc)
2056: (if_then_else (eq (cc0)
2057: (const_int 0))
2058: (pc)
2059: (label_ref (match_operand 0 "" ""))))]
2060: ""
2061: "*
2062: { if (cc_prev_status.flags & CC_Z_IN_F)
2063: return \"bfs %l0\";
2064: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2065: return \"bfc %l0\";
2066: else return \"bne %l0\";
2067: }")
2068:
2069: (define_insn ""
2070: [(set (pc)
2071: (if_then_else (ne (cc0)
2072: (const_int 0))
2073: (pc)
2074: (label_ref (match_operand 0 "" ""))))]
2075: ""
2076: "*
2077: { if (cc_prev_status.flags & CC_Z_IN_F)
2078: return \"bfc %l0\";
2079: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2080: return \"bfs %l0\";
2081: else return \"beq %l0\";
2082: }")
2083:
2084: (define_insn ""
2085: [(set (pc)
2086: (if_then_else (gt (cc0)
2087: (const_int 0))
2088: (pc)
2089: (label_ref (match_operand 0 "" ""))))]
2090: ""
2091: "ble %l0")
2092:
2093: (define_insn ""
2094: [(set (pc)
2095: (if_then_else (gtu (cc0)
2096: (const_int 0))
2097: (pc)
2098: (label_ref (match_operand 0 "" ""))))]
2099: ""
2100: "bls %l0")
2101:
2102: (define_insn ""
2103: [(set (pc)
2104: (if_then_else (lt (cc0)
2105: (const_int 0))
2106: (pc)
2107: (label_ref (match_operand 0 "" ""))))]
2108: ""
2109: "bge %l0")
2110:
2111: (define_insn ""
2112: [(set (pc)
2113: (if_then_else (ltu (cc0)
2114: (const_int 0))
2115: (pc)
2116: (label_ref (match_operand 0 "" ""))))]
2117: ""
2118: "bhs %l0")
2119:
2120: (define_insn ""
2121: [(set (pc)
2122: (if_then_else (ge (cc0)
2123: (const_int 0))
2124: (pc)
2125: (label_ref (match_operand 0 "" ""))))]
2126: ""
2127: "blt %l0")
2128:
2129: (define_insn ""
2130: [(set (pc)
2131: (if_then_else (geu (cc0)
2132: (const_int 0))
2133: (pc)
2134: (label_ref (match_operand 0 "" ""))))]
2135: ""
2136: "blo %l0")
2137:
2138: (define_insn ""
2139: [(set (pc)
2140: (if_then_else (le (cc0)
2141: (const_int 0))
2142: (pc)
2143: (label_ref (match_operand 0 "" ""))))]
2144: ""
2145: "bgt %l0")
2146:
2147: (define_insn ""
2148: [(set (pc)
2149: (if_then_else (leu (cc0)
2150: (const_int 0))
2151: (pc)
2152: (label_ref (match_operand 0 "" ""))))]
2153: ""
2154: "bhi %l0")
2155:
2156: ;; Subtract-and-jump and Add-and-jump insns.
2157: ;; These can actually be used for adding numbers in the range -8 to 7
2158:
2159: (define_insn ""
2160: [(set (pc)
2161: (if_then_else
2162: (ne (minus:SI (match_operand:SI 0 "general_operand" "+g")
2163: (match_operand:SI 1 "general_operand" "i"))
2164: (const_int 0))
2165: (label_ref (match_operand 2 "" ""))
2166: (pc)))
2167: (set (match_dup 0)
2168: (minus:SI (match_dup 0)
2169: (match_dup 1)))]
2170: "GET_CODE (operands[1]) == CONST_INT
2171: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2172: "acbd %$%n1,%0,%l2")
2173:
2174: (define_insn ""
2175: [(set (pc)
2176: (if_then_else
2177: (ne (plus:SI (match_operand:SI 0 "general_operand" "+g")
2178: (match_operand:SI 1 "general_operand" "i"))
2179: (const_int 0))
2180: (label_ref (match_operand 2 "" ""))
2181: (pc)))
2182: (set (match_dup 0)
2183: (plus:SI (match_dup 0)
2184: (match_dup 1)))]
2185: "GET_CODE (operands[1]) == CONST_INT
2186: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2187: "acbd %1,%0,%l2")
2188:
2189: ;; Reversed
2190:
2191: (define_insn ""
2192: [(set (pc)
2193: (if_then_else
2194: (eq (minus:SI (match_operand:SI 0 "general_operand" "+g")
2195: (match_operand:SI 1 "general_operand" "i"))
2196: (const_int 0))
2197: (pc)
2198: (label_ref (match_operand 2 "" ""))))
2199: (set (match_dup 0)
2200: (minus:SI (match_dup 0)
2201: (match_dup 1)))]
2202: "GET_CODE (operands[1]) == CONST_INT
2203: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2204: "acbd %$%n1,%0,%l2")
2205:
2206: (define_insn ""
2207: [(set (pc)
2208: (if_then_else
2209: (eq (plus:SI (match_operand:SI 0 "general_operand" "+g")
2210: (match_operand:SI 1 "general_operand" "i"))
2211: (const_int 0))
2212: (pc)
2213: (label_ref (match_operand 2 "" ""))))
2214: (set (match_dup 0)
2215: (plus:SI (match_dup 0)
2216: (match_dup 1)))]
2217: "GET_CODE (operands[1]) == CONST_INT
2218: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2219: "acbd %1,%0,%l2")
2220:
2221: (define_insn "call"
2222: [(call (match_operand:QI 0 "general_operand" "g")
2223: (match_operand:QI 1 "general_operand" "g"))]
2224: ""
2225: "*
2226: {
2227: if (GET_CODE (operands[0]) == MEM)
2228: {
2229: if (CONSTANT_ADDRESS_P (XEXP (operands[0], 0)))
2230: #ifdef GNX_V3
2231: return \"bsr %0\";
2232: #else
2233: return \"bsr %?%a0\";
2234: #endif
2235: if (GET_CODE (XEXP (operands[0], 0)) == REG)
2236: #ifdef GNX_V3
2237: return \"jsr %0\";
2238: #else
2239: return \"jsr %a0\";
2240: #endif
2241: }
2242: return \"jsr %0\";
2243: }")
2244:
2245: (define_insn "call_value"
2246: [(set (match_operand 0 "" "=fg")
2247: (call (match_operand:QI 1 "general_operand" "g")
2248: (match_operand:QI 2 "general_operand" "g")))]
2249: ""
2250: "*
2251: {
2252: if (GET_CODE (operands[1]) == MEM)
2253: {
2254: if (CONSTANT_ADDRESS_P (XEXP (operands[1], 0)))
2255: #ifdef GNX_V3
2256: return \"bsr %1\";
2257: #else
2258: return \"bsr %?%a1\";
2259: #endif
2260: if (GET_CODE (XEXP (operands[1], 0)) == REG)
2261: #ifdef GNX_V3
2262: return \"jsr %1\";
2263: #else
2264: return \"jsr %a1\";
2265: #endif
2266: }
2267: return \"jsr %1\";
2268: }")
2269:
2270: (define_insn "return"
2271: [(return)]
2272: "0"
2273: "ret 0")
2274:
2275: (define_insn "abssf2"
2276: [(set (match_operand:SF 0 "general_operand" "=fm<")
2277: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2278: "TARGET_32081"
2279: "absf %1,%0")
2280:
2281: (define_insn "absdf2"
2282: [(set (match_operand:DF 0 "general_operand" "=fm<")
2283: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2284: "TARGET_32081"
2285: "absl %1,%0")
2286:
2287: (define_insn "abssi2"
2288: [(set (match_operand:SI 0 "general_operand" "=g<")
2289: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2290: ""
2291: "absd %1,%0")
2292:
2293: (define_insn "abshi2"
2294: [(set (match_operand:HI 0 "general_operand" "=g<")
2295: (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2296: ""
2297: "absw %1,%0")
2298:
2299: (define_insn "absqi2"
2300: [(set (match_operand:QI 0 "general_operand" "=g<")
2301: (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2302: ""
2303: "absb %1,%0")
2304:
2305: (define_insn "nop"
2306: [(const_int 0)]
2307: ""
2308: "nop")
2309:
2310: ;;(define_insn "tablejump"
2311: ;; [(set (pc)
2312: ;; (plus:SI (match_operand:SI 0 "general_operand" "g")
2313: ;; (pc)))]
2314: ;; ""
2315: ;; "cased %0")
2316:
2317: (define_insn "tablejump"
2318: [(set (pc)
2319: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g")))
2320: (use (label_ref (match_operand 1 "" "")))]
2321: ""
2322: "*
2323: {
2324: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2325: CODE_LABEL_NUMBER (operands[1]));
2326: return \"casew %0\";
2327: }")
2328:
2329: ;;(define_insn ""
2330: ;; [(set (pc)
2331: ;; (plus:SI (match_operand:QI 0 "general_operand" "g")
2332: ;; (pc)))]
2333: ;; ""
2334: ;; "caseb %0")
2335:
2336: ;; Scondi instructions
2337: (define_insn "seq"
2338: [(set (match_operand:SI 0 "general_operand" "=g<")
2339: (eq (cc0) (const_int 0)))]
2340: ""
2341: "*
2342: { if (cc_prev_status.flags & CC_Z_IN_F)
2343: return \"sfcd %0\";
2344: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2345: return \"sfsd %0\";
2346: else return \"seqd %0\";
2347: }")
2348:
2349: (define_insn ""
2350: [(set (match_operand:HI 0 "general_operand" "=g<")
2351: (eq (cc0) (const_int 0)))]
2352: ""
2353: "*
2354: { if (cc_prev_status.flags & CC_Z_IN_F)
2355: return \"sfcw %0\";
2356: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2357: return \"sfsw %0\";
2358: else return \"seqw %0\";
2359: }")
2360:
2361: (define_insn ""
2362: [(set (match_operand:QI 0 "general_operand" "=g<")
2363: (eq (cc0) (const_int 0)))]
2364: ""
2365: "*
2366: { if (cc_prev_status.flags & CC_Z_IN_F)
2367: return \"sfcb %0\";
2368: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2369: return \"sfsb %0\";
2370: else return \"seqb %0\";
2371: }")
2372:
2373: (define_insn "sne"
2374: [(set (match_operand:SI 0 "general_operand" "=g<")
2375: (ne (cc0) (const_int 0)))]
2376: ""
2377: "*
2378: { if (cc_prev_status.flags & CC_Z_IN_F)
2379: return \"sfsd %0\";
2380: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2381: return \"sfcd %0\";
2382: else return \"sned %0\";
2383: }")
2384:
2385: (define_insn ""
2386: [(set (match_operand:HI 0 "general_operand" "=g<")
2387: (ne (cc0) (const_int 0)))]
2388: ""
2389: "*
2390: { if (cc_prev_status.flags & CC_Z_IN_F)
2391: return \"sfsw %0\";
2392: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2393: return \"sfcw %0\";
2394: else return \"snew %0\";
2395: }")
2396:
2397: (define_insn ""
2398: [(set (match_operand:QI 0 "general_operand" "=g<")
2399: (ne (cc0) (const_int 0)))]
2400: ""
2401: "*
2402: { if (cc_prev_status.flags & CC_Z_IN_F)
2403: return \"sfsb %0\";
2404: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2405: return \"sfcb %0\";
2406: else return \"sneb %0\";
2407: }")
2408:
2409: (define_insn "sgt"
2410: [(set (match_operand:SI 0 "general_operand" "=g<")
2411: (gt (cc0) (const_int 0)))]
2412: ""
2413: "sgtd %0")
2414:
2415: (define_insn ""
2416: [(set (match_operand:HI 0 "general_operand" "=g<")
2417: (gt (cc0) (const_int 0)))]
2418: ""
2419: "sgtw %0")
2420:
2421: (define_insn ""
2422: [(set (match_operand:QI 0 "general_operand" "=g<")
2423: (gt (cc0) (const_int 0)))]
2424: ""
2425: "sgtb %0")
2426:
2427: (define_insn "sgtu"
2428: [(set (match_operand:SI 0 "general_operand" "=g<")
2429: (gtu (cc0) (const_int 0)))]
2430: ""
2431: "shid %0")
2432:
2433: (define_insn ""
2434: [(set (match_operand:HI 0 "general_operand" "=g<")
2435: (gtu (cc0) (const_int 0)))]
2436: ""
2437: "shiw %0")
2438:
2439: (define_insn ""
2440: [(set (match_operand:QI 0 "general_operand" "=g<")
2441: (gtu (cc0) (const_int 0)))]
2442: ""
2443: "shib %0")
2444:
2445: (define_insn "slt"
2446: [(set (match_operand:SI 0 "general_operand" "=g<")
2447: (lt (cc0) (const_int 0)))]
2448: ""
2449: "sltd %0")
2450:
2451: (define_insn ""
2452: [(set (match_operand:HI 0 "general_operand" "=g<")
2453: (lt (cc0) (const_int 0)))]
2454: ""
2455: "sltw %0")
2456:
2457: (define_insn ""
2458: [(set (match_operand:QI 0 "general_operand" "=g<")
2459: (lt (cc0) (const_int 0)))]
2460: ""
2461: "sltb %0")
2462:
2463: (define_insn "sltu"
2464: [(set (match_operand:SI 0 "general_operand" "=g<")
2465: (ltu (cc0) (const_int 0)))]
2466: ""
2467: "slod %0")
2468:
2469: (define_insn ""
2470: [(set (match_operand:HI 0 "general_operand" "=g<")
2471: (ltu (cc0) (const_int 0)))]
2472: ""
2473: "slow %0")
2474:
2475: (define_insn ""
2476: [(set (match_operand:QI 0 "general_operand" "=g<")
2477: (ltu (cc0) (const_int 0)))]
2478: ""
2479: "slob %0")
2480:
2481: (define_insn "sge"
2482: [(set (match_operand:SI 0 "general_operand" "=g<")
2483: (ge (cc0) (const_int 0)))]
2484: ""
2485: "sged %0")
2486:
2487: (define_insn ""
2488: [(set (match_operand:HI 0 "general_operand" "=g<")
2489: (ge (cc0) (const_int 0)))]
2490: ""
2491: "sgew %0")
2492:
2493: (define_insn ""
2494: [(set (match_operand:QI 0 "general_operand" "=g<")
2495: (ge (cc0) (const_int 0)))]
2496: ""
2497: "sgeb %0")
2498:
2499: (define_insn "sgeu"
2500: [(set (match_operand:SI 0 "general_operand" "=g<")
2501: (geu (cc0) (const_int 0)))]
2502: ""
2503: "shsd %0")
2504:
2505: (define_insn ""
2506: [(set (match_operand:HI 0 "general_operand" "=g<")
2507: (geu (cc0) (const_int 0)))]
2508: ""
2509: "shsw %0")
2510:
2511: (define_insn ""
2512: [(set (match_operand:QI 0 "general_operand" "=g<")
2513: (geu (cc0) (const_int 0)))]
2514: ""
2515: "shsb %0")
2516:
2517: (define_insn "sle"
2518: [(set (match_operand:SI 0 "general_operand" "=g<")
2519: (le (cc0) (const_int 0)))]
2520: ""
2521: "sled %0")
2522:
2523: (define_insn ""
2524: [(set (match_operand:HI 0 "general_operand" "=g<")
2525: (le (cc0) (const_int 0)))]
2526: ""
2527: "slew %0")
2528:
2529: (define_insn ""
2530: [(set (match_operand:QI 0 "general_operand" "=g<")
2531: (le (cc0) (const_int 0)))]
2532: ""
2533: "sleb %0")
2534:
2535: (define_insn "sleu"
2536: [(set (match_operand:SI 0 "general_operand" "=g<")
2537: (leu (cc0) (const_int 0)))]
2538: ""
2539: "slsd %0")
2540:
2541: (define_insn ""
2542: [(set (match_operand:HI 0 "general_operand" "=g<")
2543: (leu (cc0) (const_int 0)))]
2544: ""
2545: "slsw %0")
2546:
2547: (define_insn ""
2548: [(set (match_operand:QI 0 "general_operand" "=g<")
2549: (leu (cc0) (const_int 0)))]
2550: ""
2551: "slsb %0")
2552:
2553: ;;- Local variables:
2554: ;;- mode:emacs-lisp
2555: ;;- comment-start: ";;- "
2556: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2557: ;;- eval: (modify-syntax-entry ?[ "(]")
2558: ;;- eval: (modify-syntax-entry ?] ")[")
2559: ;;- eval: (modify-syntax-entry ?{ "(}")
2560: ;;- eval: (modify-syntax-entry ?} "){")
2561: ;;- End:
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