![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to ns32k.md CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GCC 1.x] / gcc / config|
Return to ns32k.md CVS log | Up to [GCC 1.x] / gcc / config |
1.1 root 1: ;; BUGS:
2: ;; Insert no-op between an insn with memory read-write operands
3: ;; following by a scale-indexing operation.
4: ;; The Sequent assembler does not allow addresses to be used
5: ;; except in insns which explicitly compute an effective address.
6: ;; I.e., one cannot say "cmpd _p,@_x"
7: ;; Implement unsigned multiplication??
8:
9: ;;- Machine descrption for GNU compiler
10: ;;- ns32000 Version
11: ;; Copyright (C) 1988 Free Software Foundation, Inc.
12: ;; Contributed by Michael Tiemann ([email protected])
13:
14: ;; This file is part of GNU CC.
15:
16: ;; GNU CC is free software; you can redistribute it and/or modify
17: ;; it under the terms of the GNU General Public License as published by
18: ;; the Free Software Foundation; either version 1, or (at your option)
19: ;; any later version.
20:
21: ;; GNU CC is distributed in the hope that it will be useful,
22: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
23: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24: ;; GNU General Public License for more details.
25:
26: ;; You should have received a copy of the GNU General Public License
27: ;; along with GNU CC; see the file COPYING. If not, write to
28: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
29:
30:
31: ;;- Instruction patterns. When multiple patterns apply,
32: ;;- the first one in the file is chosen.
33: ;;-
34: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
35: ;;-
36: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
37: ;;- updates for most instructions.
38:
39: ; tstsi is first test insn so that it is the one to match
40: ; a constant argument.
41:
42: (define_insn "tstsi"
43: [(set (cc0)
44: (match_operand:SI 0 "general_operand" "rmn"))]
45: ""
46: "*
47: { cc_status.flags |= CC_REVERSED;
48: operands[1] = const0_rtx;
49: return \"cmpqd %1,%0\"; }")
50:
51: (define_insn "tsthi"
52: [(set (cc0)
53: (match_operand:HI 0 "general_operand" "g"))]
54: ""
55: "*
56: { cc_status.flags |= CC_REVERSED;
57: operands[1] = const0_rtx;
58: return \"cmpqw %1,%0\"; }")
59:
60: (define_insn "tstqi"
61: [(set (cc0)
62: (match_operand:QI 0 "general_operand" "g"))]
63: ""
64: "*
65: { cc_status.flags |= CC_REVERSED;
66: operands[1] = const0_rtx;
67: return \"cmpqb %1,%0\"; }")
68:
69: (define_insn "tstdf"
70: [(set (cc0)
71: (match_operand:DF 0 "general_operand" "fmF"))]
72: "TARGET_32081"
73: "*
74: { cc_status.flags |= CC_REVERSED;
75: operands[1] = dconst0_rtx;
76: return \"cmpl %1,%0\"; }")
77:
78: (define_insn "tstsf"
79: [(set (cc0)
80: (match_operand:SF 0 "general_operand" "fmF"))]
81: "TARGET_32081"
82: "*
83: { cc_status.flags |= CC_REVERSED;
84: operands[1] = fconst0_rtx;
85: return \"cmpf %1,%0\"; }")
86:
87: ;; Put cmpsi first among compare insns so it matches two CONST_INT operands.
88:
89: (define_insn "cmpsi"
90: [(set (cc0)
91: (compare (match_operand:SI 0 "general_operand" "rmn")
92: (match_operand:SI 1 "general_operand" "rmn")))]
93: ""
94: "*
95: {
96: if (GET_CODE (operands[1]) == CONST_INT)
97: {
98: int i = INTVAL (operands[1]);
99: if (i <= 7 && i >= -8)
100: {
101: cc_status.flags |= CC_REVERSED;
102: return \"cmpqd %1,%0\";
103: }
104: }
105: cc_status.flags &= ~CC_REVERSED;
106: if (GET_CODE (operands[0]) == CONST_INT)
107: {
108: int i = INTVAL (operands[0]);
109: if (i <= 7 && i >= -8)
110: return \"cmpqd %0,%1\";
111: }
112: return \"cmpd %0,%1\";
113: }")
114:
115: (define_insn "cmphi"
116: [(set (cc0)
117: (compare (match_operand:HI 0 "general_operand" "g")
118: (match_operand:HI 1 "general_operand" "g")))]
119: ""
120: "*
121: {
122: if (GET_CODE (operands[1]) == CONST_INT)
123: {
124: short i = INTVAL (operands[1]);
125: if (i <= 7 && i >= -8)
126: {
127: cc_status.flags |= CC_REVERSED;
128: if (INTVAL (operands[1]) > 7)
129: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
130: return \"cmpqw %1,%0\";
131: }
132: }
133: cc_status.flags &= ~CC_REVERSED;
134: if (GET_CODE (operands[0]) == CONST_INT)
135: {
136: short i = INTVAL (operands[0]);
137: if (i <= 7 && i >= -8)
138: {
139: if (INTVAL (operands[0]) > 7)
140: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
141: return \"cmpqw %0,%1\";
142: }
143: }
144: return \"cmpw %0,%1\";
145: }")
146:
147: (define_insn "cmpqi"
148: [(set (cc0)
149: (compare (match_operand:QI 0 "general_operand" "g")
150: (match_operand:QI 1 "general_operand" "g")))]
151: ""
152: "*
153: {
154: if (GET_CODE (operands[1]) == CONST_INT)
155: {
156: char i = INTVAL (operands[1]);
157: if (i <= 7 && i >= -8)
158: {
159: cc_status.flags |= CC_REVERSED;
160: if (INTVAL (operands[1]) > 7)
161: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
162: return \"cmpqb %1,%0\";
163: }
164: }
165: cc_status.flags &= ~CC_REVERSED;
166: if (GET_CODE (operands[0]) == CONST_INT)
167: {
168: char i = INTVAL (operands[0]);
169: if (i <= 7 && i >= -8)
170: {
171: if (INTVAL (operands[0]) > 7)
172: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
173: return \"cmpqb %0,%1\";
174: }
175: }
176: return \"cmpb %0,%1\";
177: }")
178:
179: (define_insn "cmpdf"
180: [(set (cc0)
181: (compare (match_operand:DF 0 "general_operand" "fmF")
182: (match_operand:DF 1 "general_operand" "fmF")))]
183: "TARGET_32081"
184: "cmpl %0,%1")
185:
186: (define_insn "cmpsf"
187: [(set (cc0)
188: (compare (match_operand:SF 0 "general_operand" "fmF")
189: (match_operand:SF 1 "general_operand" "fmF")))]
190: "TARGET_32081"
191: "cmpf %0,%1")
192:
193: (define_insn "movdf"
194: [(set (match_operand:DF 0 "general_operand" "=&fg<")
195: (match_operand:DF 1 "general_operand" "fFg"))]
196: ""
197: "*
198: {
199: if (FP_REG_P (operands[0]))
200: {
201: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
202: return \"movl %1,%0\";
203: if (REG_P (operands[1]))
204: {
205: rtx xoperands[2];
206: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
207: output_asm_insn (\"movd %1,tos\", xoperands);
208: output_asm_insn (\"movd %1,tos\", operands);
209: return \"movl tos,%0\";
210: }
211: return \"movl %1,%0\";
212: }
213: else if (FP_REG_P (operands[1]))
214: {
215: if (REG_P (operands[0]))
216: {
217: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
218: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
219: return \"movd tos,%0\";
220: }
221: else
222: return \"movl %1,%0\";
223: }
224: return output_move_double (operands);
225: }")
226:
227: (define_insn "movsf"
228: [(set (match_operand:SF 0 "general_operand" "=fg<")
229: (match_operand:SF 1 "general_operand" "fFg"))]
230: ""
231: "*
232: {
233: if (FP_REG_P (operands[0]))
234: {
235: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
236: return \"movd %1,tos\;movf tos,%0\";
237: else
238: return \"movf %1,%0\";
239: }
240: else if (FP_REG_P (operands[1]))
241: {
242: if (REG_P (operands[0]))
243: return \"movf %1,tos\;movd tos,%0\";
244: return \"movf %1,%0\";
245: }
1.1.1.3 ! root 246: #ifndef GAS_SYNTAX
! 247: /* GAS understands floating constants in ordinary movd instructions
! 248: * but other assembers might object.
! 249: */
1.1 root 250: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
251: {
1.1.1.2 root 252: union {int i[2]; float f; double d;} convrt;
253: convrt.i[0] = CONST_DOUBLE_LOW (operands[1]);
254: convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]);
255: convrt.f = convrt.d;
256:
1.1 root 257: /* Is there a better machine-independent way to to this? */
1.1.1.2 root 258: operands[1] = gen_rtx (CONST_INT, VOIDmode, convrt.i[0]);
1.1 root 259: return \"movd %1,%0\";
260: }
1.1.1.3 ! root 261: #endif
1.1 root 262: else return \"movd %1,%0\";
263: }")
264:
265: (define_insn ""
266: [(set (match_operand:TI 0 "memory_operand" "=m")
267: (match_operand:TI 1 "memory_operand" "m"))]
268: ""
269: "movmd %1,%0,4")
270:
271: (define_insn "movdi"
1.1.1.3 ! root 272: [(set (match_operand:DI 0 "general_operand" "=&g<,*f,g")
! 273: (match_operand:DI 1 "general_operand" "gF,g,*f"))]
1.1 root 274: ""
1.1.1.3 ! root 275: "*
! 276: {
! 277: if (FP_REG_P (operands[0]))
! 278: {
! 279: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
! 280: return \"movl %1,%0\";
! 281: if (REG_P (operands[1]))
! 282: {
! 283: rtx xoperands[2];
! 284: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
! 285: output_asm_insn (\"movd %1,tos\", xoperands);
! 286: output_asm_insn (\"movd %1,tos\", operands);
! 287: return \"movl tos,%0\";
! 288: }
! 289: return \"movl %1,%0\";
! 290: }
! 291: else if (FP_REG_P (operands[1]))
! 292: {
! 293: if (REG_P (operands[0]))
! 294: {
! 295: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
! 296: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
! 297: return \"movd tos,%0\";
! 298: }
! 299: else
! 300: return \"movl %1,%0\";
! 301: }
! 302: return output_move_double (operands);
! 303: }")
1.1 root 304:
305: ;; This special case must precede movsi.
306: (define_insn ""
307: [(set (reg:SI 17)
308: (match_operand:SI 0 "general_operand" "rmn"))]
309: ""
310: "lprd sp,%0")
311:
312: (define_insn "movsi"
1.1.1.3 ! root 313: [(set (match_operand:SI 0 "general_operand" "=g<,*f,g")
! 314: (match_operand:SI 1 "general_operand" "gx,g,*f"))]
1.1 root 315: ""
316: "*
1.1.1.3 ! root 317: {
! 318: if (FP_REG_P (operands[0]))
! 319: {
! 320: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
! 321: return \"movd %1,tos\;movf tos,%0\";
! 322: else
! 323: return \"movf %1,%0\";
! 324: }
! 325: else if (FP_REG_P (operands[1]))
! 326: {
! 327: if (REG_P (operands[0]))
! 328: return \"movf %1,tos\;movd tos,%0\";
! 329: return \"movf %1,%0\";
! 330: }
! 331: if (GET_CODE (operands[1]) == CONST_INT)
1.1 root 332: {
333: int i = INTVAL (operands[1]);
334: if (i <= 7 && i >= -8)
335: return \"movqd %1,%0\";
336: if (i < 0x4000 && i >= -0x4000)
337: #ifdef GNX_V3
338: return \"addr %c1,%0\";
339: #else
340: return \"addr @%c1,%0\";
341: #endif
342: return \"movd %1,%0\";
343: }
344: else if (GET_CODE (operands[1]) == REG)
345: {
346: if (REGNO (operands[1]) < 16)
347: return \"movd %1,%0\";
348: else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM)
349: {
350: if (GET_CODE(operands[0]) == REG)
351: return \"sprd fp,%0\";
352: else
353: return \"addr 0(fp),%0\" ;
354: }
355: else if (REGNO (operands[1]) == STACK_POINTER_REGNUM)
356: {
357: if (GET_CODE(operands[0]) == REG)
358: return \"sprd sp,%0\";
359: else
360: return \"addr 0(sp),%0\" ;
361: }
362: else abort (0);
363: }
364: else if (GET_CODE (operands[1]) == MEM)
365: return \"movd %1,%0\";
366: /* Check if this effective address can be
367: calculated faster by pulling it apart. */
368: if (REG_P (operands[0])
369: && GET_CODE (operands[1]) == MULT
370: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
371: && (INTVAL (XEXP (operands[1], 1)) == 2
372: || INTVAL (XEXP (operands[1], 1)) == 4))
373: {
374: rtx xoperands[3];
375: xoperands[0] = operands[0];
376: xoperands[1] = XEXP (operands[1], 0);
377: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
378: return output_shift_insn (xoperands);
379: }
380: return \"addr %a1,%0\";
381: }")
382:
383: (define_insn "movhi"
384: [(set (match_operand:HI 0 "general_operand" "=g<")
385: (match_operand:HI 1 "general_operand" "g"))]
386: ""
387: "*
388: {
389: if (GET_CODE (operands[1]) == CONST_INT)
390: {
391: short i = INTVAL (operands[1]);
392: if (i <= 7 && i >= -8)
393: {
394: if (INTVAL (operands[1]) > 7)
395: operands[1] =
396: gen_rtx (CONST_INT, VOIDmode, i);
397: return \"movqw %1,%0\";
398: }
399: }
400: return \"movw %1,%0\";
401: }")
402:
403: (define_insn "movstricthi"
404: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
405: (match_operand:HI 1 "general_operand" "g"))]
406: ""
407: "*
408: {
409: if (GET_CODE (operands[1]) == CONST_INT
410: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
411: return \"movqw %1,%0\";
412: return \"movw %1,%0\";
413: }")
414:
415: (define_insn "movqi"
416: [(set (match_operand:QI 0 "general_operand" "=g<")
417: (match_operand:QI 1 "general_operand" "g"))]
418: ""
419: "*
420: { if (GET_CODE (operands[1]) == CONST_INT)
421: {
422: char char_val = (char)INTVAL (operands[1]);
423: if (char_val <= 7 && char_val >= -8)
424: {
425: if (INTVAL (operands[1]) > 7)
426: operands[1] =
427: gen_rtx (CONST_INT, VOIDmode, char_val);
428: return \"movqb %1,%0\";
429: }
430: }
431: return \"movb %1,%0\";
432: }")
433:
434: (define_insn "movstrictqi"
435: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
436: (match_operand:QI 1 "general_operand" "g"))]
437: ""
438: "*
439: {
440: if (GET_CODE (operands[1]) == CONST_INT
441: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
442: return \"movqb %1,%0\";
443: return \"movb %1,%0\";
444: }")
445:
446: ;; The definition of this insn does not really explain what it does,
447: ;; but it should suffice
448: ;; that anything generated as this insn will be recognized as one
449: ;; and that it won't successfully combine with anything.
450: (define_insn "movstrsi"
451: [(set (match_operand:BLK 0 "general_operand" "=g")
452: (match_operand:BLK 1 "general_operand" "g"))
453: (use (match_operand:SI 2 "general_operand" "rmn"))
454: (clobber (reg:SI 0))
455: (clobber (reg:SI 1))
456: (clobber (reg:SI 2))]
457: ""
458: "*
459: {
460: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
461: abort ();
462: operands[0] = XEXP (operands[0], 0);
463: operands[1] = XEXP (operands[1], 0);
464: if (GET_CODE (operands[0]) == MEM)
465: if (GET_CODE (operands[1]) == MEM)
466: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
467: else
468: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
469: else if (GET_CODE (operands[1]) == MEM)
470: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
471: else
472: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
473:
474: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
475: {
476: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
477: if ((unsigned) INTVAL (operands[2]) <= 7)
478: return \"movqd %2,r0\;movsd\";
479: else
480: return \"movd %2,r0\;movsd\";
481: }
482: else
483: {
484: return \"movd %2,r0\;movsb\";
485: }
486: }")
487:
488: ;; Extension and truncation insns.
489: ;; Those for integer source operand
490: ;; are ordered widest source type first.
491:
492: (define_insn "truncsiqi2"
493: [(set (match_operand:QI 0 "general_operand" "=g<")
494: (truncate:QI (match_operand:SI 1 "general_operand" "rmn")))]
495: ""
496: "movb %1,%0")
497:
498: (define_insn "truncsihi2"
499: [(set (match_operand:HI 0 "general_operand" "=g<")
500: (truncate:HI (match_operand:SI 1 "general_operand" "rmn")))]
501: ""
502: "movw %1,%0")
503:
504: (define_insn "trunchiqi2"
505: [(set (match_operand:QI 0 "general_operand" "=g<")
506: (truncate:QI (match_operand:HI 1 "general_operand" "g")))]
507: ""
508: "movb %1,%0")
509:
510: (define_insn "extendhisi2"
511: [(set (match_operand:SI 0 "general_operand" "=g<")
512: (sign_extend:SI (match_operand:HI 1 "general_operand" "g")))]
513: ""
514: "movxwd %1,%0")
515:
516: (define_insn "extendqihi2"
517: [(set (match_operand:HI 0 "general_operand" "=g<")
518: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))]
519: ""
520: "movxbw %1,%0")
521:
522: (define_insn "extendqisi2"
523: [(set (match_operand:SI 0 "general_operand" "=g<")
524: (sign_extend:SI (match_operand:QI 1 "general_operand" "g")))]
525: ""
526: "movxbd %1,%0")
527:
528: (define_insn "extendsfdf2"
529: [(set (match_operand:DF 0 "general_operand" "=fm<")
530: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
531: "TARGET_32081"
532: "movfl %1,%0")
533:
534: (define_insn "truncdfsf2"
535: [(set (match_operand:SF 0 "general_operand" "=fm<")
536: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
537: "TARGET_32081"
538: "movlf %1,%0")
539:
540: (define_insn "zero_extendhisi2"
541: [(set (match_operand:SI 0 "general_operand" "=g<")
542: (zero_extend:SI (match_operand:HI 1 "general_operand" "g")))]
543: ""
544: "movzwd %1,%0")
545:
546: (define_insn "zero_extendqihi2"
547: [(set (match_operand:HI 0 "general_operand" "=g<")
548: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))]
549: ""
550: "movzbw %1,%0")
551:
552: (define_insn "zero_extendqisi2"
553: [(set (match_operand:SI 0 "general_operand" "=g<")
554: (zero_extend:SI (match_operand:QI 1 "general_operand" "g")))]
555: ""
556: "movzbd %1,%0")
557:
558: ;; Fix-to-float conversion insns.
559: ;; Note that the ones that start with SImode come first.
560: ;; That is so that an operand that is a CONST_INT
561: ;; (and therefore lacks a specific machine mode).
562: ;; will be recognized as SImode (which is always valid)
563: ;; rather than as QImode or HImode.
564:
565: ;; Rumor has it that the National part does not correctly convert
566: ;; constant ints to floats. This conversion is therefore disabled.
567: ;; A register must be used to perform the conversion.
568:
569: (define_insn "floatsisf2"
570: [(set (match_operand:SF 0 "general_operand" "=fm<")
571: (float:SF (match_operand:SI 1 "general_operand" "rm")))]
572: "TARGET_32081"
573: "movdf %1,%0")
574:
575: (define_insn "floatsidf2"
576: [(set (match_operand:DF 0 "general_operand" "=fm<")
577: (float:DF (match_operand:SI 1 "general_operand" "rm")))]
578: "TARGET_32081"
579: "movdl %1,%0")
580:
581: (define_insn "floathisf2"
582: [(set (match_operand:SF 0 "general_operand" "=fm<")
583: (float:SF (match_operand:HI 1 "general_operand" "rm")))]
584: "TARGET_32081"
585: "movwf %1,%0")
586:
587: (define_insn "floathidf2"
588: [(set (match_operand:DF 0 "general_operand" "=fm<")
589: (float:DF (match_operand:HI 1 "general_operand" "rm")))]
590: "TARGET_32081"
591: "movwl %1,%0")
592:
593: (define_insn "floatqisf2"
594: [(set (match_operand:SF 0 "general_operand" "=fm<")
595: (float:SF (match_operand:QI 1 "general_operand" "rm")))]
596: "TARGET_32081"
597: "movbf %1,%0")
598:
599: ; Some assemblers warn that this insn doesn't work.
600: ; Maybe they know something we don't.
601: ;(define_insn "floatqidf2"
602: ; [(set (match_operand:DF 0 "general_operand" "=fm<")
603: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
604: ; "TARGET_32081"
605: ; "movbl %1,%0")
606:
607: ;; Float-to-fix conversion insns.
608: ;; The sequent compiler always generates "trunc" insns.
609:
610: (define_insn "fixsfqi2"
611: [(set (match_operand:QI 0 "general_operand" "=g<")
612: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
613: "TARGET_32081"
614: "truncfb %1,%0")
615:
616: (define_insn "fixsfhi2"
617: [(set (match_operand:HI 0 "general_operand" "=g<")
618: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
619: "TARGET_32081"
620: "truncfw %1,%0")
621:
622: (define_insn "fixsfsi2"
623: [(set (match_operand:SI 0 "general_operand" "=g<")
624: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
625: "TARGET_32081"
626: "truncfd %1,%0")
627:
628: (define_insn "fixdfqi2"
629: [(set (match_operand:QI 0 "general_operand" "=g<")
630: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
631: "TARGET_32081"
632: "trunclb %1,%0")
633:
634: (define_insn "fixdfhi2"
635: [(set (match_operand:HI 0 "general_operand" "=g<")
636: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
637: "TARGET_32081"
638: "trunclw %1,%0")
639:
640: (define_insn "fixdfsi2"
641: [(set (match_operand:SI 0 "general_operand" "=g<")
642: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
643: "TARGET_32081"
644: "truncld %1,%0")
645:
646: ;; Unsigned
647:
648: (define_insn "fixunssfqi2"
649: [(set (match_operand:QI 0 "general_operand" "=g<")
650: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
651: "TARGET_32081"
652: "truncfb %1,%0")
653:
654: (define_insn "fixunssfhi2"
655: [(set (match_operand:HI 0 "general_operand" "=g<")
656: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
657: "TARGET_32081"
658: "truncfw %1,%0")
659:
660: (define_insn "fixunssfsi2"
661: [(set (match_operand:SI 0 "general_operand" "=g<")
662: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
663: "TARGET_32081"
664: "truncfd %1,%0")
665:
666: (define_insn "fixunsdfqi2"
667: [(set (match_operand:QI 0 "general_operand" "=g<")
668: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
669: "TARGET_32081"
670: "trunclb %1,%0")
671:
672: (define_insn "fixunsdfhi2"
673: [(set (match_operand:HI 0 "general_operand" "=g<")
674: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
675: "TARGET_32081"
676: "trunclw %1,%0")
677:
678: (define_insn "fixunsdfsi2"
679: [(set (match_operand:SI 0 "general_operand" "=g<")
680: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
681: "TARGET_32081"
682: "truncld %1,%0")
683:
684: ;;; These are not yet used by GCC
685: (define_insn "fix_truncsfqi2"
686: [(set (match_operand:QI 0 "general_operand" "=g<")
687: (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
688: "TARGET_32081"
689: "truncfb %1,%0")
690:
691: (define_insn "fix_truncsfhi2"
692: [(set (match_operand:HI 0 "general_operand" "=g<")
693: (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
694: "TARGET_32081"
695: "truncfw %1,%0")
696:
697: (define_insn "fix_truncsfsi2"
698: [(set (match_operand:SI 0 "general_operand" "=g<")
699: (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
700: "TARGET_32081"
701: "truncfd %1,%0")
702:
703: (define_insn "fix_truncdfqi2"
704: [(set (match_operand:QI 0 "general_operand" "=g<")
705: (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
706: "TARGET_32081"
707: "trunclb %1,%0")
708:
709: (define_insn "fix_truncdfhi2"
710: [(set (match_operand:HI 0 "general_operand" "=g<")
711: (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
712: "TARGET_32081"
713: "trunclw %1,%0")
714:
715: (define_insn "fix_truncdfsi2"
716: [(set (match_operand:SI 0 "general_operand" "=g<")
717: (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
718: "TARGET_32081"
719: "truncld %1,%0")
720:
721: ;;- All kinds of add instructions.
722:
723: (define_insn "adddf3"
724: [(set (match_operand:DF 0 "general_operand" "=fm")
725: (plus:DF (match_operand:DF 1 "general_operand" "%0")
726: (match_operand:DF 2 "general_operand" "fmF")))]
727: "TARGET_32081"
728: "addl %2,%0")
729:
730:
731: (define_insn "addsf3"
732: [(set (match_operand:SF 0 "general_operand" "=fm")
733: (plus:SF (match_operand:SF 1 "general_operand" "%0")
734: (match_operand:SF 2 "general_operand" "fmF")))]
735: "TARGET_32081"
736: "addf %2,%0")
737:
738: (define_insn ""
739: [(set (reg:SI 17)
740: (plus:SI (reg:SI 17)
741: (match_operand:SI 0 "immediate_operand" "i")))]
742: "GET_CODE (operands[0]) == CONST_INT"
743: "*
744: {
1.1.1.3 ! root 745: #ifndef SEQUENT_ADJUST_STACK
1.1.1.2 root 746: if (INTVAL (operands[0]) == 8)
1.1.1.3 ! root 747: return \"cmpd tos,tos\";
1.1.1.2 root 748: if (INTVAL (operands[0]) == 4)
1.1.1.3 ! root 749: return \"cmpqd %$0,tos\";
! 750: #endif
1.1.1.2 root 751: if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64)
1.1 root 752: return \"adjspb %$%n0\";
753: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
754: return \"adjspw %$%n0\";
755: return \"adjspd %$%n0\";
756: }")
757:
758: (define_insn ""
759: [(set (match_operand:SI 0 "general_operand" "=g<")
760: (plus:SI (reg:SI 16)
761: (match_operand:SI 1 "immediate_operand" "i")))]
762: "GET_CODE (operands[1]) == CONST_INT"
763: "addr %c1(fp),%0")
764:
765: (define_insn ""
766: [(set (match_operand:SI 0 "general_operand" "=g<")
767: (plus:SI (reg:SI 17)
768: (match_operand:SI 1 "immediate_operand" "i")))]
769: "GET_CODE (operands[1]) == CONST_INT"
770: "addr %c1(sp),%0")
771:
772: (define_insn "addsi3"
773: [(set (match_operand:SI 0 "general_operand" "=g,=g<")
774: (plus:SI (match_operand:SI 1 "general_operand" "%0,%r")
775: (match_operand:SI 2 "general_operand" "rmn,n")))]
776: ""
777: "*
778: {
779: if (which_alternative == 1)
1.1.1.3 ! root 780: {
! 781: int i = INTVAL (operands[2]);
! 782: if ( i < 0x40000000 && i >= -0x40000000 )
! 783: return \"addr %c2(%1),%0\";
! 784: else
! 785: return \"movd %1,%0\;addd %2,%0\";
! 786: }
1.1 root 787: if (GET_CODE (operands[2]) == CONST_INT)
788: {
789: int i = INTVAL (operands[2]);
790:
791: if (i <= 7 && i >= -8)
792: return \"addqd %2,%0\";
793: else if (GET_CODE (operands[0]) == REG
794: && i < 0x4000 && i >= -0x4000)
795: return \"addr %c2(%0),%0\";
796: }
797: return \"addd %2,%0\";
798: }")
799:
800: (define_insn "addhi3"
801: [(set (match_operand:HI 0 "general_operand" "=g")
802: (plus:HI (match_operand:HI 1 "general_operand" "%0")
803: (match_operand:HI 2 "general_operand" "g")))]
804: ""
805: "*
806: { if (GET_CODE (operands[2]) == CONST_INT)
807: {
808: int i = INTVAL (operands[2]);
809: if (i <= 7 && i >= -8)
810: return \"addqw %2,%0\";
811: }
812: return \"addw %2,%0\";
813: }")
814:
815: (define_insn ""
816: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
817: (plus:HI (match_operand:HI 1 "general_operand" "0")
818: (match_operand:HI 2 "general_operand" "g")))]
819: ""
820: "*
821: {
822: if (GET_CODE (operands[1]) == CONST_INT
823: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
824: return \"addqw %1,%0\";
825: return \"addw %1,%0\";
826: }")
827:
828: (define_insn "addqi3"
829: [(set (match_operand:QI 0 "general_operand" "=g")
830: (plus:QI (match_operand:QI 1 "general_operand" "%0")
831: (match_operand:QI 2 "general_operand" "g")))]
832: ""
833: "*
834: { if (GET_CODE (operands[2]) == CONST_INT)
835: {
836: int i = INTVAL (operands[2]);
837: if (i <= 7 && i >= -8)
838: return \"addqb %2,%0\";
839: }
840: return \"addb %2,%0\";
841: }")
842:
843: (define_insn ""
844: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
845: (plus:QI (match_operand:QI 1 "general_operand" "0")
846: (match_operand:QI 2 "general_operand" "g")))]
847: ""
848: "*
849: {
850: if (GET_CODE (operands[1]) == CONST_INT
851: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
852: return \"addqb %1,%0\";
853: return \"addb %1,%0\";
854: }")
855:
856: ;;- All kinds of subtract instructions.
857:
858: (define_insn "subdf3"
859: [(set (match_operand:DF 0 "general_operand" "=fm")
860: (minus:DF (match_operand:DF 1 "general_operand" "0")
861: (match_operand:DF 2 "general_operand" "fmF")))]
862: "TARGET_32081"
863: "subl %2,%0")
864:
865: (define_insn "subsf3"
866: [(set (match_operand:SF 0 "general_operand" "=fm")
867: (minus:SF (match_operand:SF 1 "general_operand" "0")
868: (match_operand:SF 2 "general_operand" "fmF")))]
869: "TARGET_32081"
870: "subf %2,%0")
871:
872: (define_insn ""
873: [(set (reg:SI 17)
874: (minus:SI (reg:SI 17)
875: (match_operand:SI 0 "immediate_operand" "i")))]
876: "GET_CODE (operands[0]) == CONST_INT"
877: "*
878: {
879: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64
880: && INTVAL(operands[0]) > -64)
881: return \"adjspb %0\";
882: return \"adjspd %0\";
883: }")
884:
885: (define_insn "subsi3"
886: [(set (match_operand:SI 0 "general_operand" "=g")
887: (minus:SI (match_operand:SI 1 "general_operand" "0")
888: (match_operand:SI 2 "general_operand" "rmn")))]
889: ""
890: "*
891: { if (GET_CODE (operands[2]) == CONST_INT)
892: {
893: int i = INTVAL (operands[2]);
894:
895: if (i <= 8 && i >= -7)
896: return \"addqd %$%n2,%0\";
897: }
898: return \"subd %2,%0\";
899: }")
900:
901: (define_insn "subhi3"
902: [(set (match_operand:HI 0 "general_operand" "=g")
903: (minus:HI (match_operand:HI 1 "general_operand" "0")
904: (match_operand:HI 2 "general_operand" "g")))]
905: ""
906: "*
907: { if (GET_CODE (operands[2]) == CONST_INT)
908: {
909: int i = INTVAL (operands[2]);
910:
911: if (i <= 8 && i >= -7)
912: return \"addqw %$%n2,%0\";
913: }
914: return \"subw %2,%0\";
915: }")
916:
917: (define_insn ""
918: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
919: (minus:HI (match_operand:HI 1 "general_operand" "0")
920: (match_operand:HI 2 "general_operand" "g")))]
921: ""
922: "*
923: {
924: if (GET_CODE (operands[1]) == CONST_INT
925: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
926: return \"addqw %$%n1,%0\";
927: return \"subw %1,%0\";
928: }")
929:
930: (define_insn "subqi3"
931: [(set (match_operand:QI 0 "general_operand" "=g")
932: (minus:QI (match_operand:QI 1 "general_operand" "0")
933: (match_operand:QI 2 "general_operand" "g")))]
934: ""
935: "*
936: { if (GET_CODE (operands[2]) == CONST_INT)
937: {
938: int i = INTVAL (operands[2]);
939:
940: if (i <= 8 && i >= -7)
941: return \"addqb %$%n2,%0\";
942: }
943: return \"subb %2,%0\";
944: }")
945:
946: (define_insn ""
947: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
948: (minus:QI (match_operand:QI 1 "general_operand" "0")
949: (match_operand:QI 2 "general_operand" "g")))]
950: ""
951: "*
952: {
953: if (GET_CODE (operands[1]) == CONST_INT
954: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
955: return \"addqb %$%n1,%0\";
956: return \"subb %1,%0\";
957: }")
958:
959: ;;- Multiply instructions.
960:
961: (define_insn "muldf3"
962: [(set (match_operand:DF 0 "general_operand" "=fm")
963: (mult:DF (match_operand:DF 1 "general_operand" "%0")
964: (match_operand:DF 2 "general_operand" "fmF")))]
965: "TARGET_32081"
966: "mull %2,%0")
967:
968: (define_insn "mulsf3"
969: [(set (match_operand:SF 0 "general_operand" "=fm")
970: (mult:SF (match_operand:SF 1 "general_operand" "%0")
971: (match_operand:SF 2 "general_operand" "fmF")))]
972: "TARGET_32081"
973: "mulf %2,%0")
974:
975: (define_insn "mulsi3"
976: [(set (match_operand:SI 0 "general_operand" "=g")
977: (mult:SI (match_operand:SI 1 "general_operand" "%0")
978: (match_operand:SI 2 "general_operand" "rmn")))]
979: ""
980: "muld %2,%0")
981:
982: (define_insn "mulhi3"
983: [(set (match_operand:HI 0 "general_operand" "=g")
984: (mult:HI (match_operand:HI 1 "general_operand" "%0")
985: (match_operand:HI 2 "general_operand" "g")))]
986: ""
987: "mulw %2,%0")
988:
989: (define_insn "mulqi3"
990: [(set (match_operand:QI 0 "general_operand" "=g")
991: (mult:QI (match_operand:QI 1 "general_operand" "%0")
992: (match_operand:QI 2 "general_operand" "g")))]
993: ""
994: "mulb %2,%0")
995:
996: (define_insn "umulsi3"
997: [(set (match_operand:SI 0 "general_operand" "=g")
998: (umult:SI (match_operand:SI 1 "general_operand" "%0")
999: (match_operand:SI 2 "general_operand" "rmn")))]
1000: ""
1001: "muld %2,%0")
1002:
1003: (define_insn "umulhi3"
1004: [(set (match_operand:HI 0 "general_operand" "=g")
1005: (umult:HI (match_operand:HI 1 "general_operand" "%0")
1006: (match_operand:HI 2 "general_operand" "g")))]
1007: ""
1008: "mulw %2,%0")
1009:
1010: (define_insn "umulqi3"
1011: [(set (match_operand:QI 0 "general_operand" "=g")
1012: (umult:QI (match_operand:QI 1 "general_operand" "%0")
1013: (match_operand:QI 2 "general_operand" "g")))]
1014: ""
1015: "mulb %2,%0")
1016:
1017: (define_insn "umulsidi3"
1018: [(set (match_operand:DI 0 "general_operand" "=g")
1019: (umult:DI (match_operand:SI 1 "general_operand" "0")
1020: (match_operand:SI 2 "general_operand" "rmn")))]
1021: ""
1022: "meid %2,%0")
1023:
1024: ;;- Divide instructions.
1025:
1026: (define_insn "divdf3"
1027: [(set (match_operand:DF 0 "general_operand" "=fm")
1028: (div:DF (match_operand:DF 1 "general_operand" "0")
1029: (match_operand:DF 2 "general_operand" "fmF")))]
1030: "TARGET_32081"
1031: "divl %2,%0")
1032:
1033: (define_insn "divsf3"
1034: [(set (match_operand:SF 0 "general_operand" "=fm")
1035: (div:SF (match_operand:SF 1 "general_operand" "0")
1036: (match_operand:SF 2 "general_operand" "fmF")))]
1037: "TARGET_32081"
1038: "divf %2,%0")
1039:
1040: (define_insn "divsi3"
1041: [(set (match_operand:SI 0 "general_operand" "=g")
1042: (div:SI (match_operand:SI 1 "general_operand" "0")
1043: (match_operand:SI 2 "general_operand" "rmn")))]
1044: ""
1045: "quod %2,%0")
1046:
1047: (define_insn "divhi3"
1048: [(set (match_operand:HI 0 "general_operand" "=g")
1049: (div:HI (match_operand:HI 1 "general_operand" "0")
1050: (match_operand:HI 2 "general_operand" "g")))]
1051: ""
1052: "quow %2,%0")
1053:
1054: (define_insn "divqi3"
1055: [(set (match_operand:QI 0 "general_operand" "=g")
1056: (div:QI (match_operand:QI 1 "general_operand" "0")
1057: (match_operand:QI 2 "general_operand" "g")))]
1058: ""
1059: "quob %2,%0")
1060:
1061: (define_insn "udivsi3"
1062: [(set (match_operand:SI 0 "register_operand" "=r")
1063: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1064: (match_operand:SI 2 "general_operand" "rmn")))]
1065: ""
1066: "*
1067: {
1068: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1069: return \"deid %2,%0\;movd %1,%0\";
1070: }")
1071:
1072: (define_insn "udivhi3"
1073: [(set (match_operand:HI 0 "register_operand" "=r")
1074: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1075: (match_operand:HI 2 "general_operand" "g")))]
1076: ""
1077: "*
1078: {
1079: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
1080: return \"deiw %2,%0\;movw %1,%0\";
1081: }")
1082:
1083: (define_insn "udivqi3"
1084: [(set (match_operand:QI 0 "register_operand" "=r")
1085: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1086: (match_operand:QI 2 "general_operand" "g")))]
1087: ""
1088: "*
1089: {
1090: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
1091: return \"deib %2,%0\;movb %1,%0\";
1092: }")
1093:
1094: ;; Remainder instructions.
1095:
1096: (define_insn "modsi3"
1097: [(set (match_operand:SI 0 "general_operand" "=g")
1098: (mod:SI (match_operand:SI 1 "general_operand" "0")
1099: (match_operand:SI 2 "general_operand" "rmn")))]
1100: ""
1101: "remd %2,%0")
1102:
1103: (define_insn "modhi3"
1104: [(set (match_operand:HI 0 "general_operand" "=g")
1105: (mod:HI (match_operand:HI 1 "general_operand" "0")
1106: (match_operand:HI 2 "general_operand" "g")))]
1107: ""
1108: "remw %2,%0")
1109:
1110: (define_insn "modqi3"
1111: [(set (match_operand:QI 0 "general_operand" "=g")
1112: (mod:QI (match_operand:QI 1 "general_operand" "0")
1113: (match_operand:QI 2 "general_operand" "g")))]
1114: ""
1115: "remb %2,%0")
1116:
1117: (define_insn "umodsi3"
1118: [(set (match_operand:SI 0 "register_operand" "=r")
1119: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1120: (match_operand:SI 2 "general_operand" "rmn")))]
1121: ""
1122: "deid %2,%0")
1123:
1124: (define_insn "umodhi3"
1125: [(set (match_operand:HI 0 "register_operand" "=r")
1126: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1127: (match_operand:HI 2 "general_operand" "g")))]
1128: ""
1129: "deiw %2,%0")
1130:
1131: (define_insn "umodqi3"
1132: [(set (match_operand:QI 0 "register_operand" "=r")
1133: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1134: (match_operand:QI 2 "general_operand" "g")))]
1135: ""
1136: "deib %2,%0")
1137:
1138: ; This isn't be usable in its current form.
1139: ;(define_insn "udivmoddisi4"
1140: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1141: ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1142: ; (match_operand:SI 2 "general_operand" "rmn")))
1143: ; (set (subreg:SI (match_dup 0) 0)
1144: ; (umod:SI (match_dup 1) (match_dup 2)))]
1145: ; ""
1146: ; "deid %2,%0")
1147:
1148: ;;- Logical Instructions: AND
1149:
1150: (define_insn "andsi3"
1151: [(set (match_operand:SI 0 "general_operand" "=g")
1152: (and:SI (match_operand:SI 1 "general_operand" "%0")
1153: (match_operand:SI 2 "general_operand" "rmn")))]
1154: ""
1155: "*
1156: {
1157: if (GET_CODE (operands[2]) == CONST_INT)
1158: {
1159: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1160: {
1161: if (INTVAL (operands[2]) == 0xffffff00)
1162: return \"movqb %$0,%0\";
1163: else
1164: {
1165: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1166: INTVAL (operands[2]) & 0xff);
1167: return \"andb %2,%0\";
1168: }
1169: }
1170: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1171: {
1172: if (INTVAL (operands[2]) == 0xffff0000)
1173: return \"movqw %$0,%0\";
1174: else
1175: {
1176: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1177: INTVAL (operands[2]) & 0xffff);
1178: return \"andw %2,%0\";
1179: }
1180: }
1181: }
1182: return \"andd %2,%0\";
1183: }")
1184:
1185: (define_insn "andhi3"
1186: [(set (match_operand:HI 0 "general_operand" "=g")
1187: (and:HI (match_operand:HI 1 "general_operand" "%0")
1188: (match_operand:HI 2 "general_operand" "g")))]
1189: ""
1190: "*
1191: {
1192: if (GET_CODE (operands[2]) == CONST_INT
1193: && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1194: {
1195: if (INTVAL (operands[2]) == 0xffffff00)
1196: return \"movqb %$0,%0\";
1197: else
1198: {
1199: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1200: INTVAL (operands[2]) & 0xff);
1201: return \"andb %2,%0\";
1202: }
1203: }
1204: return \"andw %2,%0\";
1205: }")
1206:
1207: (define_insn "andqi3"
1208: [(set (match_operand:QI 0 "general_operand" "=g")
1209: (and:QI (match_operand:QI 1 "general_operand" "%0")
1210: (match_operand:QI 2 "general_operand" "g")))]
1211: ""
1212: "andb %2,%0")
1213:
1214: (define_insn "andcbsi3"
1215: [(set (match_operand:SI 0 "general_operand" "=g")
1216: (and:SI (match_operand:SI 1 "general_operand" "0")
1217: (not:SI (match_operand:SI 2 "general_operand" "rmn"))))]
1218: ""
1219: "*
1220: {
1221: if (GET_CODE (operands[2]) == CONST_INT)
1222: {
1223: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1224: return \"bicb %2,%0\";
1225: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1226: return \"bicw %2,%0\";
1227: }
1228: return \"bicd %2,%0\";
1229: }")
1230:
1231: (define_insn ""
1232: [(set (match_operand:SI 0 "general_operand" "=g")
1233: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1234: (match_operand:SI 2 "general_operand" "0")))]
1235: ""
1236: "*
1237: {
1238: if (GET_CODE (operands[1]) == CONST_INT)
1239: {
1240: if ((INTVAL (operands[1]) & 0xffffff00) == 0)
1241: return \"bicb %1,%0\";
1242: if ((INTVAL (operands[1]) & 0xffff0000) == 0)
1243: return \"bicw %1,%0\";
1244: }
1245: return \"bicd %1,%0\";
1246: }")
1247:
1248: (define_insn "andcbhi3"
1249: [(set (match_operand:HI 0 "general_operand" "=g")
1250: (and:HI (match_operand:HI 1 "general_operand" "%0")
1251: (not:HI (match_operand:HI 2 "general_operand" "g"))))]
1252: ""
1253: "*
1254: {
1255: if (GET_CODE (operands[2]) == CONST_INT
1256: && (INTVAL (operands[2]) & 0xffffff00) == 0)
1257: return \"bicb %2,%0\";
1258: return \"bicw %2,%0\";
1259: }")
1260:
1261: (define_insn ""
1262: [(set (match_operand:HI 0 "general_operand" "=g")
1263: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1264: (match_operand:HI 2 "general_operand" "0")))]
1265: ""
1266: "*
1267: {
1268: if (GET_CODE (operands[1]) == CONST_INT
1269: && (INTVAL (operands[1]) & 0xffffff00) == 0)
1270: return \"bicb %1,%0\";
1271: return \"bicw %1,%0\";
1272: }")
1273:
1274: (define_insn "andcbqi3"
1275: [(set (match_operand:QI 0 "general_operand" "=g")
1276: (and:QI (match_operand:QI 1 "general_operand" "%0")
1277: (not:QI (match_operand:QI 2 "general_operand" "g"))))]
1278: ""
1279: "bicb %2,%0")
1280:
1281: (define_insn ""
1282: [(set (match_operand:QI 0 "general_operand" "=g")
1283: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1284: (match_operand:QI 2 "general_operand" "0")))]
1285: ""
1286: "bicb %1,%0")
1287:
1288: ;;- Bit set instructions.
1289:
1290: (define_insn "iorsi3"
1291: [(set (match_operand:SI 0 "general_operand" "=g")
1292: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1293: (match_operand:SI 2 "general_operand" "rmn")))]
1294: ""
1295: "*
1296: {
1297: if (GET_CODE (operands[2]) == CONST_INT) {
1298: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1299: return \"orb %2,%0\";
1300: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1301: return \"orw %2,%0\";
1302: }
1303: return \"ord %2,%0\";
1304: }")
1305:
1306: (define_insn "iorhi3"
1307: [(set (match_operand:HI 0 "general_operand" "=g")
1308: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1309: (match_operand:HI 2 "general_operand" "g")))]
1310: ""
1311: "*
1312: {
1313: if (GET_CODE(operands[2]) == CONST_INT &&
1314: (INTVAL(operands[2]) & 0xffffff00) == 0)
1315: return \"orb %2,%0\";
1316: return \"orw %2,%0\";
1317: }")
1318:
1319: (define_insn "iorqi3"
1320: [(set (match_operand:QI 0 "general_operand" "=g")
1321: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1322: (match_operand:QI 2 "general_operand" "g")))]
1323: ""
1324: "orb %2,%0")
1325:
1326: ;;- xor instructions.
1327:
1328: (define_insn "xorsi3"
1329: [(set (match_operand:SI 0 "general_operand" "=g")
1330: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1331: (match_operand:SI 2 "general_operand" "rmn")))]
1332: ""
1333: "*
1334: {
1335: if (GET_CODE (operands[2]) == CONST_INT) {
1336: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1337: return \"xorb %2,%0\";
1338: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1339: return \"xorw %2,%0\";
1340: }
1341: return \"xord %2,%0\";
1342: }")
1343:
1344: (define_insn "xorhi3"
1345: [(set (match_operand:HI 0 "general_operand" "=g")
1346: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1347: (match_operand:HI 2 "general_operand" "g")))]
1348: ""
1349: "*
1350: {
1351: if (GET_CODE(operands[2]) == CONST_INT &&
1352: (INTVAL(operands[2]) & 0xffffff00) == 0)
1353: return \"xorb %2,%0\";
1354: return \"xorw %2,%0\";
1355: }")
1356:
1357: (define_insn "xorqi3"
1358: [(set (match_operand:QI 0 "general_operand" "=g")
1359: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1360: (match_operand:QI 2 "general_operand" "g")))]
1361: ""
1362: "xorb %2,%0")
1363:
1364: (define_insn "negdf2"
1365: [(set (match_operand:DF 0 "general_operand" "=fm<")
1366: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1367: "TARGET_32081"
1368: "negl %1,%0")
1369:
1370: (define_insn "negsf2"
1371: [(set (match_operand:SF 0 "general_operand" "=fm<")
1372: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1373: "TARGET_32081"
1374: "negf %1,%0")
1375:
1376: (define_insn "negsi2"
1377: [(set (match_operand:SI 0 "general_operand" "=g<")
1378: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1379: ""
1380: "negd %1,%0")
1381:
1382: (define_insn "neghi2"
1383: [(set (match_operand:HI 0 "general_operand" "=g<")
1384: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1385: ""
1386: "negw %1,%0")
1387:
1388: (define_insn "negqi2"
1389: [(set (match_operand:QI 0 "general_operand" "=g<")
1390: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1391: ""
1392: "negb %1,%0")
1393:
1394: (define_insn "one_cmplsi2"
1395: [(set (match_operand:SI 0 "general_operand" "=g<")
1396: (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1397: ""
1398: "comd %1,%0")
1399:
1400: (define_insn "one_cmplhi2"
1401: [(set (match_operand:HI 0 "general_operand" "=g<")
1402: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1403: ""
1404: "comw %1,%0")
1405:
1406: (define_insn "one_cmplqi2"
1407: [(set (match_operand:QI 0 "general_operand" "=g<")
1408: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1409: ""
1410: "comb %1,%0")
1411:
1412: ;; arithmetic left and right shift operations
1413:
1414: (define_insn "ashlsi3"
1415: [(set (match_operand:SI 0 "general_operand" "=g,g")
1416: (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1417: (match_operand:SI 2 "general_operand" "I,rmn")))]
1418: ""
1.1.1.3 ! root 1419: "* return output_shift_insn (operands);")
1.1 root 1420:
1421: (define_insn "ashlhi3"
1422: [(set (match_operand:HI 0 "general_operand" "=g")
1423: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1424: (match_operand:SI 2 "general_operand" "rmn")))]
1425: ""
1426: "*
1427: { if (GET_CODE (operands[2]) == CONST_INT)
1428: if (INTVAL (operands[2]) == 1)
1.1.1.3 ! root 1429: return \"addw %0,%0\";
1.1 root 1430: else if (INTVAL (operands[2]) == 2)
1.1.1.3 ! root 1431: return \"addw %0,%0\;addw %0,%0\";
1.1 root 1432: return \"ashw %2,%0\";
1433: }")
1434:
1435: (define_insn "ashlqi3"
1436: [(set (match_operand:QI 0 "general_operand" "=g")
1437: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1438: (match_operand:SI 2 "general_operand" "rmn")))]
1439: ""
1440: "*
1441: { if (GET_CODE (operands[2]) == CONST_INT)
1442: if (INTVAL (operands[2]) == 1)
1443: return \"addb %1,%0\";
1444: else if (INTVAL (operands[2]) == 2)
1445: return \"addb %1,%0\;addb %0,%0\";
1446: return \"ashb %2,%0\";
1447: }")
1448:
1449: ;; Arithmetic right shift on the 32k works by negating the shift count.
1450: (define_expand "ashrsi3"
1451: [(set (match_operand:SI 0 "general_operand" "=g")
1452: (ashift:SI (match_operand:SI 1 "general_operand" "g")
1453: (match_operand:SI 2 "general_operand" "g")))]
1454: ""
1455: "
1456: {
1457: operands[2] = negate_rtx (SImode, operands[2]);
1458: }")
1459:
1460: (define_expand "ashrhi3"
1461: [(set (match_operand:HI 0 "general_operand" "=g")
1462: (ashift:HI (match_operand:HI 1 "general_operand" "g")
1463: (match_operand:SI 2 "general_operand" "g")))]
1464: ""
1465: "
1466: {
1467: operands[2] = negate_rtx (SImode, operands[2]);
1468: }")
1469:
1470: (define_expand "ashrqi3"
1471: [(set (match_operand:QI 0 "general_operand" "=g")
1472: (ashift:QI (match_operand:QI 1 "general_operand" "g")
1473: (match_operand:SI 2 "general_operand" "g")))]
1474: ""
1475: "
1476: {
1477: operands[2] = negate_rtx (SImode, operands[2]);
1478: }")
1479:
1480: ;; logical shift instructions
1481:
1482: (define_insn "lshlsi3"
1483: [(set (match_operand:SI 0 "general_operand" "=g")
1484: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1485: (match_operand:SI 2 "general_operand" "rmn")))]
1486: ""
1487: "lshd %2,%0")
1488:
1489: (define_insn "lshlhi3"
1490: [(set (match_operand:HI 0 "general_operand" "=g")
1491: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1492: (match_operand:SI 2 "general_operand" "rmn")))]
1493: ""
1494: "lshw %2,%0")
1495:
1496: (define_insn "lshlqi3"
1497: [(set (match_operand:QI 0 "general_operand" "=g")
1498: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1499: (match_operand:SI 2 "general_operand" "rmn")))]
1500: ""
1501: "lshb %2,%0")
1502:
1503: ;; Logical right shift on the 32k works by negating the shift count.
1504: (define_expand "lshrsi3"
1505: [(set (match_operand:SI 0 "general_operand" "=g")
1506: (lshift:SI (match_operand:SI 1 "general_operand" "g")
1507: (match_operand:SI 2 "general_operand" "g")))]
1508: ""
1509: "
1510: {
1511: operands[2] = negate_rtx (SImode, operands[2]);
1512: }")
1513:
1514: (define_expand "lshrhi3"
1515: [(set (match_operand:HI 0 "general_operand" "=g")
1516: (lshift:HI (match_operand:HI 1 "general_operand" "g")
1517: (match_operand:SI 2 "general_operand" "g")))]
1518: ""
1519: "
1520: {
1521: operands[2] = negate_rtx (SImode, operands[2]);
1522: }")
1523:
1524: (define_expand "lshrqi3"
1525: [(set (match_operand:QI 0 "general_operand" "=g")
1526: (lshift:QI (match_operand:QI 1 "general_operand" "g")
1527: (match_operand:SI 2 "general_operand" "g")))]
1528: ""
1529: "
1530: {
1531: operands[2] = negate_rtx (SImode, operands[2]);
1532: }")
1533:
1534: ;; Rotate instructions
1535:
1536: (define_insn "rotlsi3"
1537: [(set (match_operand:SI 0 "general_operand" "=g")
1538: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1539: (match_operand:SI 2 "general_operand" "rmn")))]
1540: ""
1541: "rotd %2,%0")
1542:
1543: (define_insn "rotlhi3"
1544: [(set (match_operand:HI 0 "general_operand" "=g")
1545: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1546: (match_operand:SI 2 "general_operand" "rmn")))]
1547: ""
1548: "rotw %2,%0")
1549:
1550: (define_insn "rotlqi3"
1551: [(set (match_operand:QI 0 "general_operand" "=g")
1552: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1553: (match_operand:SI 2 "general_operand" "rmn")))]
1554: ""
1555: "rotb %2,%0")
1556:
1557: ;; Right rotate on the 32k works by negating the shift count.
1558: (define_expand "rotrsi3"
1559: [(set (match_operand:SI 0 "general_operand" "=g")
1560: (rotate:SI (match_operand:SI 1 "general_operand" "g")
1561: (match_operand:SI 2 "general_operand" "g")))]
1562: ""
1563: "
1564: {
1565: operands[2] = negate_rtx (SImode, operands[2]);
1566: }")
1567:
1568: (define_expand "rotrhi3"
1569: [(set (match_operand:HI 0 "general_operand" "=g")
1570: (rotate:HI (match_operand:HI 1 "general_operand" "g")
1571: (match_operand:SI 2 "general_operand" "g")))]
1572: ""
1573: "
1574: {
1575: operands[2] = negate_rtx (SImode, operands[2]);
1576: }")
1577:
1578: (define_expand "rotrqi3"
1579: [(set (match_operand:QI 0 "general_operand" "=g")
1580: (rotate:QI (match_operand:QI 1 "general_operand" "g")
1581: (match_operand:SI 2 "general_operand" "g")))]
1582: ""
1583: "
1584: {
1585: operands[2] = negate_rtx (SImode, operands[2]);
1586: }")
1587:
1588: ;;- load or push effective address
1589: ;; These come after the move, add, and multiply patterns
1590: ;; because we don't want pushl $1 turned into pushad 1.
1591:
1592: (define_insn ""
1593: [(set (match_operand:SI 0 "general_operand" "=g<")
1594: (match_operand:QI 1 "address_operand" "p"))]
1595: ""
1596: "*
1597: {
1598: if (REG_P (operands[0])
1599: && GET_CODE (operands[1]) == MULT
1600: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1601: && (INTVAL (XEXP (operands[1], 1)) == 2
1602: || INTVAL (XEXP (operands[1], 1)) == 4))
1603: {
1604: rtx xoperands[3];
1605: xoperands[0] = operands[0];
1606: xoperands[1] = XEXP (operands[1], 0);
1607: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
1608: return output_shift_insn (xoperands);
1609: }
1610: return \"addr %a1,%0\";
1611: }")
1612:
1613: ;;; Index insns. These are about the same speed as multiply-add counterparts.
1614: ;;; but slower then using power-of-2 shifts if we can use them
1615: ;
1616: ;(define_insn ""
1617: ; [(set (match_operand:SI 0 "register_operand" "=r")
1618: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1619: ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1620: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1621: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1622: ; "indexd %0,%3,%1")
1623: ;
1624: ;(define_insn ""
1625: ; [(set (match_operand:SI 0 "register_operand" "=r")
1626: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1627: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1628: ; (match_operand:SI 3 "general_operand" "rmn")))]
1629: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1630: ; "indexd %0,%2,%3")
1631:
1632: ;; Set, Clear, and Invert bit
1633:
1634: (define_insn ""
1635: [(set (match_operand:SI 0 "general_operand" "=g")
1636: (ior:SI
1637: (ashift:SI (const_int 1)
1638: (match_operand:SI 1 "general_operand" "rmn"))
1639: (match_dup 0)))]
1640: ""
1641: "sbitd %1,%0")
1642:
1643: (define_insn ""
1644: [(set (match_operand:SI 0 "general_operand" "=g")
1645: (ior:SI
1646: (match_dup 0)
1647: (ashift:SI (const_int 1)
1648: (match_operand:SI 1 "general_operand" "rmn"))))]
1649: ""
1650: "sbitd %1,%0")
1651:
1652: (define_insn ""
1653: [(set (match_operand:QI 0 "general_operand" "=g")
1654: (ior:QI
1655: (subreg:QI
1656: (ashift:SI (const_int 1)
1657: (match_operand:QI 1 "general_operand" "rmn")) 0)
1658: (match_dup 0)))]
1659: ""
1660: "sbitb %1,%0")
1661:
1662: (define_insn ""
1663: [(set (match_operand:QI 0 "general_operand" "=g")
1664: (ior:QI
1665: (match_dup 0)
1666: (subreg:QI
1667: (ashift:SI (const_int 1)
1668: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1669: ""
1670: "sbitb %1,%0")
1671:
1672: (define_insn ""
1673: [(set (match_operand:SI 0 "general_operand" "=g")
1674: (and:SI
1675: (not:SI
1676: (ashift:SI (const_int 1)
1677: (match_operand:SI 1 "general_operand" "rmn")))
1678: (match_dup 0)))]
1679: ""
1680: "cbitd %1,%0")
1681:
1682: (define_insn ""
1683: [(set (match_operand:SI 0 "general_operand" "=g")
1684: (and:SI
1685: (match_dup 0)
1686: (not:SI
1687: (ashift:SI (const_int 1)
1688: (match_operand:SI 1 "general_operand" "rmn")))))]
1689: ""
1690: "cbitd %1,%0")
1691:
1692: (define_insn ""
1693: [(set (match_operand:QI 0 "general_operand" "=g")
1694: (and:QI
1695: (subreg:QI
1696: (not:SI
1697: (ashift:SI (const_int 1)
1698: (match_operand:QI 1 "general_operand" "rmn"))) 0)
1699: (match_dup 0)))]
1700: ""
1701: "cbitb %1,%0")
1702:
1703: (define_insn ""
1704: [(set (match_operand:QI 0 "general_operand" "=g")
1705: (and:QI
1706: (match_dup 0)
1707: (subreg:QI
1708: (not:SI
1709: (ashift:SI (const_int 1)
1710: (match_operand:QI 1 "general_operand" "rmn"))) 0)))]
1711: ""
1712: "cbitb %1,%0")
1713:
1714: (define_insn ""
1715: [(set (match_operand:SI 0 "general_operand" "=g")
1716: (xor:SI
1717: (ashift:SI (const_int 1)
1718: (match_operand:SI 1 "general_operand" "rmn"))
1719: (match_dup 0)))]
1720: ""
1721: "ibitd %1,%0")
1722:
1723: (define_insn ""
1724: [(set (match_operand:SI 0 "general_operand" "=g")
1725: (xor:SI
1726: (match_dup 0)
1727: (ashift:SI (const_int 1)
1728: (match_operand:SI 1 "general_operand" "rmn"))))]
1729: ""
1730: "ibitd %1,%0")
1731:
1732: (define_insn ""
1733: [(set (match_operand:QI 0 "general_operand" "=g")
1734: (xor:QI
1735: (subreg:QI
1736: (ashift:SI (const_int 1)
1737: (match_operand:QI 1 "general_operand" "rmn")) 0)
1738: (match_dup 0)))]
1739: ""
1740: "ibitb %1,%0")
1741:
1742: (define_insn ""
1743: [(set (match_operand:QI 0 "general_operand" "=g")
1744: (xor:QI
1745: (match_dup 0)
1746: (subreg:QI
1747: (ashift:SI (const_int 1)
1748: (match_operand:QI 1 "general_operand" "rmn")) 0)))]
1749: ""
1750: "ibitb %1,%0")
1751:
1752: ;; Recognize jbs and jbc instructions.
1753:
1754: (define_insn ""
1755: [(set (cc0)
1756: (zero_extract (match_operand:SI 0 "general_operand" "rm")
1757: (const_int 1)
1758: (match_operand:SI 1 "general_operand" "rmn")))]
1759: ""
1760: "*
1761: { cc_status.flags = CC_Z_IN_F;
1762: return \"tbitd %1,%0\";
1763: }")
1764:
1765: (define_insn ""
1766: [(set (cc0)
1767: (compare (zero_extract (match_operand:SI 0 "general_operand" "rm")
1768: (const_int 1)
1769: (match_operand:SI 1 "general_operand" "rmn"))
1770: (const_int 1)))]
1771: ""
1772: "*
1773: { cc_status.flags = CC_Z_IN_NOT_F;
1774: return \"tbitd %1,%0\";
1775: }")
1776:
1777: (define_insn ""
1778: [(set (cc0)
1.1.1.3 ! root 1779: (zero_extract (match_operand:HI 0 "general_operand" "rm")
1.1 root 1780: (const_int 1)
1781: (match_operand:HI 1 "general_operand" "g")))]
1782: ""
1783: "*
1784: { cc_status.flags = CC_Z_IN_F;
1785: return \"tbitw %1,%0\";
1786: }")
1787:
1788: (define_insn ""
1789: [(set (cc0)
1.1.1.3 ! root 1790: (compare (zero_extract (match_operand:HI 0 "general_operand" "rm")
1.1 root 1791: (const_int 1)
1.1.1.3 ! root 1792: (match_operand:HI 1 "general_operand" "g"))
1.1 root 1793: (const_int 1)))]
1794: ""
1795: "*
1796: { cc_status.flags = CC_Z_IN_NOT_F;
1797: return \"tbitw %1,%0\";
1798: }")
1799:
1800: (define_insn ""
1801: [(set (cc0)
1.1.1.3 ! root 1802: (zero_extract (match_operand:QI 0 "general_operand" "rm")
1.1 root 1803: (const_int 1)
1804: (match_operand:QI 1 "general_operand" "g")))]
1805: ""
1806: "*
1807: { cc_status.flags = CC_Z_IN_F;
1808: return \"tbitb %1,%0\";
1809: }")
1810:
1811: (define_insn ""
1812: [(set (cc0)
1.1.1.3 ! root 1813: (compare (zero_extract:SI (match_operand:QI 0 "general_operand" "rm")
1.1 root 1814: (const_int 1)
1815: (match_operand:QI 1 "general_operand" "rmn"))
1816: (const_int 1)))]
1817: ""
1818: "*
1819: { cc_status.flags = CC_Z_IN_NOT_F;
1820: return \"tbitb %1,%0\";
1821: }")
1822:
1823: (define_insn ""
1824: [(set (cc0)
1825: (and:SI (match_operand:SI 0 "general_operand" "rm")
1826: (match_operand:SI 1 "immediate_operand" "i")))]
1827: "GET_CODE (operands[1]) == CONST_INT
1828: && exact_log2 (INTVAL (operands[1])) >= 0"
1829: "*
1830: {
1831: operands[1]
1832: = gen_rtx (CONST_INT, VOIDmode, exact_log2 (INTVAL (operands[1])));
1833: cc_status.flags = CC_Z_IN_F;
1834: return \"tbitd %1,%0\";
1835: }")
1836:
1837: ;; extract(base, width, offset)
1838: ;; Signed bitfield extraction is not supported in hardware on the
1839: ;; NS 32032. It is therefore better to let GCC figure out a
1840: ;; good strategy for generating the proper instruction sequence
1841: ;; and represent it as rtl.
1842:
1843: ;; Optimize the case of extracting a byte or word from a register.
1844: ;; Otherwise we must load a register with the offset of the
1845: ;; chunk we want, and perform an extract insn (each of which
1846: ;; is very expensive). Since we use the stack to do our bit-twiddling
1847: ;; we cannot use it for a destination. Perhaps things are fast
1848: ;; enough on the 32532 that such hacks are not needed.
1849:
1850: (define_insn ""
1851: [(set (match_operand:SI 0 "general_operand" "=ro")
1852: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1853: (match_operand:SI 2 "const_int" "i")
1854: (match_operand:SI 3 "const_int" "i")))]
1855: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1856: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
1857: "*
1858: {
1859: output_asm_insn (\"movd %1,tos\", operands);
1860: if (INTVAL (operands[2]) == 16)
1861: {
1862: if (INTVAL (operands[3]) == 8)
1863: output_asm_insn (\"movzwd 1(sp),%0\", operands);
1864: else
1865: output_asm_insn (\"movzwd 2(sp),%0\", operands);
1866: }
1867: else
1868: {
1869: if (INTVAL (operands[3]) == 8)
1870: output_asm_insn (\"movzbd 1(sp),%0\", operands);
1871: else if (INTVAL (operands[3]) == 16)
1872: output_asm_insn (\"movzbd 2(sp),%0\", operands);
1873: else
1874: output_asm_insn (\"movzbd 3(sp),%0\", operands);
1875: }
1.1.1.3 ! root 1876: return \"cmpqd %$0,tos\";
1.1 root 1877: }")
1878:
1879: (define_insn ""
1880: [(set (match_operand:SI 0 "general_operand" "=ro")
1881: (zero_extract:SI (match_operand:HI 1 "register_operand" "r")
1882: (match_operand:SI 2 "const_int" "i")
1883: (match_operand:SI 3 "const_int" "i")))]
1884: "INTVAL (operands[2]) == 8 && INTVAL (operands[3]) == 8"
1885: "movw %1,tos\;movzbd 1(sp),%0\;adjspb %$-2")
1886:
1887: (define_insn "extzv"
1888: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1889: (zero_extract:SI (match_operand:SI 1 "general_operand" "rm,o")
1890: (match_operand:SI 2 "const_int" "i,i")
1891: (match_operand:SI 3 "general_operand" "rK,n")))]
1892: ""
1893: "*
1894: { if (GET_CODE (operands[3]) == CONST_INT)
1895: {
1896: if (INTVAL (operands[3]) >= 8)
1897: operands[1] = adj_offsettable_operand (operands[1],
1898: INTVAL (operands[3]) >> 3);
1899: return \"extsd %1,%0,%3,%2\";
1900: }
1901: else return \"extd %3,%1,%0,%2\";
1902: }")
1903:
1904: (define_insn ""
1905: [(set (match_operand:SI 0 "general_operand" "=g<,g<")
1906: (zero_extract:SI (match_operand:HI 1 "general_operand" "rm,o")
1907: (match_operand:SI 2 "const_int" "i,i")
1908: (match_operand:SI 3 "general_operand" "rK,n")))]
1909: ""
1910: "*
1911: { if (GET_CODE (operands[3]) == CONST_INT)
1912: {
1913: if (INTVAL (operands[3]) >= 8)
1914: operands[1] = adj_offsettable_operand (operands[1],
1915: INTVAL (operands[3]) >> 3);
1916: return \"extsd %1,%0,%3,%2\";
1917: }
1918: else return \"extd %3,%1,%0,%2\";
1919: }")
1920:
1921: (define_insn ""
1922: [(set (match_operand:SI 0 "general_operand" "=g<")
1923: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1924: (match_operand:SI 2 "const_int" "i")
1925: (match_operand:SI 3 "general_operand" "rn")))]
1926: ""
1927: "*
1928: { if (GET_CODE (operands[3]) == CONST_INT)
1929: return \"extsd %1,%0,%3,%2\";
1930: else return \"extd %3,%1,%0,%2\";
1931: }")
1932:
1933: (define_insn "insv"
1934: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g,o")
1935: (match_operand:SI 1 "const_int" "i,i")
1936: (match_operand:SI 2 "general_operand" "rK,n"))
1937: (match_operand:SI 3 "general_operand" "rm,rm"))]
1938: ""
1939: "*
1940: { if (GET_CODE (operands[2]) == CONST_INT)
1941: {
1942: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
1943: {
1944: operands[0] = adj_offsettable_operand (operands[0],
1945: INTVAL (operands[2]) / 8);
1946: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1947: }
1948: if (INTVAL (operands[1]) <= 8)
1949: return \"inssb %3,%0,%2,%1\";
1950: else if (INTVAL (operands[1]) <= 16)
1951: return \"inssw %3,%0,%2,%1\";
1952: else
1953: return \"inssd %3,%0,%2,%1\";
1954: }
1955: return \"insd %2,%3,%0,%1\";
1956: }")
1957:
1958: (define_insn ""
1959: [(set (zero_extract:SI (match_operand:HI 0 "general_operand" "+g,o")
1960: (match_operand:SI 1 "const_int" "i,i")
1961: (match_operand:SI 2 "general_operand" "rK,n"))
1962: (match_operand:SI 3 "general_operand" "rm,rm"))]
1963: ""
1964: "*
1965: { if (GET_CODE (operands[2]) == CONST_INT)
1966: {
1967: if (GET_CODE (operands[0]) == MEM && INTVAL (operands[2]) >= 8)
1968: {
1969: operands[0] = adj_offsettable_operand (operands[0],
1970: INTVAL (operands[2]) / 8);
1971: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1972: }
1973: if (INTVAL (operands[1]) <= 8)
1974: return \"inssb %3,%0,%2,%1\";
1975: else if (INTVAL (operands[1]) <= 16)
1976: return \"inssw %3,%0,%2,%1\";
1977: else
1978: return \"inssd %3,%0,%2,%1\";
1979: }
1980: return \"insd %2,%3,%0,%1\";
1981: }")
1982:
1983: (define_insn ""
1984: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "=g")
1985: (match_operand:SI 1 "const_int" "i")
1986: (match_operand:SI 2 "general_operand" "rn"))
1987: (match_operand:SI 3 "general_operand" "rm"))]
1988: ""
1989: "*
1990: { if (GET_CODE (operands[2]) == CONST_INT)
1991: if (INTVAL (operands[1]) <= 8)
1992: return \"inssb %3,%0,%2,%1\";
1993: else if (INTVAL (operands[1]) <= 16)
1994: return \"inssw %3,%0,%2,%1\";
1995: else
1996: return \"inssd %3,%0,%2,%1\";
1997: return \"insd %2,%3,%0,%1\";
1998: }")
1999:
2000:
2001: (define_insn "jump"
2002: [(set (pc)
2003: (label_ref (match_operand 0 "" "")))]
2004: ""
2005: "br %l0")
2006:
2007: (define_insn "beq"
2008: [(set (pc)
2009: (if_then_else (eq (cc0)
2010: (const_int 0))
2011: (label_ref (match_operand 0 "" ""))
2012: (pc)))]
2013: ""
2014: "*
2015: { if (cc_prev_status.flags & CC_Z_IN_F)
2016: return \"bfc %l0\";
2017: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2018: return \"bfs %l0\";
2019: else return \"beq %l0\";
2020: }")
2021:
2022: (define_insn "bne"
2023: [(set (pc)
2024: (if_then_else (ne (cc0)
2025: (const_int 0))
2026: (label_ref (match_operand 0 "" ""))
2027: (pc)))]
2028: ""
2029: "*
2030: { if (cc_prev_status.flags & CC_Z_IN_F)
2031: return \"bfs %l0\";
2032: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2033: return \"bfc %l0\";
2034: else return \"bne %l0\";
2035: }")
2036:
2037: (define_insn "bgt"
2038: [(set (pc)
2039: (if_then_else (gt (cc0)
2040: (const_int 0))
2041: (label_ref (match_operand 0 "" ""))
2042: (pc)))]
2043: ""
2044: "bgt %l0")
2045:
2046: (define_insn "bgtu"
2047: [(set (pc)
2048: (if_then_else (gtu (cc0)
2049: (const_int 0))
2050: (label_ref (match_operand 0 "" ""))
2051: (pc)))]
2052: ""
2053: "bhi %l0")
2054:
2055: (define_insn "blt"
2056: [(set (pc)
2057: (if_then_else (lt (cc0)
2058: (const_int 0))
2059: (label_ref (match_operand 0 "" ""))
2060: (pc)))]
2061: ""
2062: "blt %l0")
2063:
2064: (define_insn "bltu"
2065: [(set (pc)
2066: (if_then_else (ltu (cc0)
2067: (const_int 0))
2068: (label_ref (match_operand 0 "" ""))
2069: (pc)))]
2070: ""
2071: "blo %l0")
2072:
2073: (define_insn "bge"
2074: [(set (pc)
2075: (if_then_else (ge (cc0)
2076: (const_int 0))
2077: (label_ref (match_operand 0 "" ""))
2078: (pc)))]
2079: ""
2080: "bge %l0")
2081:
2082: (define_insn "bgeu"
2083: [(set (pc)
2084: (if_then_else (geu (cc0)
2085: (const_int 0))
2086: (label_ref (match_operand 0 "" ""))
2087: (pc)))]
2088: ""
2089: "bhs %l0")
2090:
2091: (define_insn "ble"
2092: [(set (pc)
2093: (if_then_else (le (cc0)
2094: (const_int 0))
2095: (label_ref (match_operand 0 "" ""))
2096: (pc)))]
2097: ""
2098: "ble %l0")
2099:
2100: (define_insn "bleu"
2101: [(set (pc)
2102: (if_then_else (leu (cc0)
2103: (const_int 0))
2104: (label_ref (match_operand 0 "" ""))
2105: (pc)))]
2106: ""
2107: "bls %l0")
2108:
2109: (define_insn ""
2110: [(set (pc)
2111: (if_then_else (eq (cc0)
2112: (const_int 0))
2113: (pc)
2114: (label_ref (match_operand 0 "" ""))))]
2115: ""
2116: "*
2117: { if (cc_prev_status.flags & CC_Z_IN_F)
2118: return \"bfs %l0\";
2119: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2120: return \"bfc %l0\";
2121: else return \"bne %l0\";
2122: }")
2123:
2124: (define_insn ""
2125: [(set (pc)
2126: (if_then_else (ne (cc0)
2127: (const_int 0))
2128: (pc)
2129: (label_ref (match_operand 0 "" ""))))]
2130: ""
2131: "*
2132: { if (cc_prev_status.flags & CC_Z_IN_F)
2133: return \"bfc %l0\";
2134: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2135: return \"bfs %l0\";
2136: else return \"beq %l0\";
2137: }")
2138:
2139: (define_insn ""
2140: [(set (pc)
2141: (if_then_else (gt (cc0)
2142: (const_int 0))
2143: (pc)
2144: (label_ref (match_operand 0 "" ""))))]
2145: ""
2146: "ble %l0")
2147:
2148: (define_insn ""
2149: [(set (pc)
2150: (if_then_else (gtu (cc0)
2151: (const_int 0))
2152: (pc)
2153: (label_ref (match_operand 0 "" ""))))]
2154: ""
2155: "bls %l0")
2156:
2157: (define_insn ""
2158: [(set (pc)
2159: (if_then_else (lt (cc0)
2160: (const_int 0))
2161: (pc)
2162: (label_ref (match_operand 0 "" ""))))]
2163: ""
2164: "bge %l0")
2165:
2166: (define_insn ""
2167: [(set (pc)
2168: (if_then_else (ltu (cc0)
2169: (const_int 0))
2170: (pc)
2171: (label_ref (match_operand 0 "" ""))))]
2172: ""
2173: "bhs %l0")
2174:
2175: (define_insn ""
2176: [(set (pc)
2177: (if_then_else (ge (cc0)
2178: (const_int 0))
2179: (pc)
2180: (label_ref (match_operand 0 "" ""))))]
2181: ""
2182: "blt %l0")
2183:
2184: (define_insn ""
2185: [(set (pc)
2186: (if_then_else (geu (cc0)
2187: (const_int 0))
2188: (pc)
2189: (label_ref (match_operand 0 "" ""))))]
2190: ""
2191: "blo %l0")
2192:
2193: (define_insn ""
2194: [(set (pc)
2195: (if_then_else (le (cc0)
2196: (const_int 0))
2197: (pc)
2198: (label_ref (match_operand 0 "" ""))))]
2199: ""
2200: "bgt %l0")
2201:
2202: (define_insn ""
2203: [(set (pc)
2204: (if_then_else (leu (cc0)
2205: (const_int 0))
2206: (pc)
2207: (label_ref (match_operand 0 "" ""))))]
2208: ""
2209: "bhi %l0")
2210:
2211: ;; Subtract-and-jump and Add-and-jump insns.
2212: ;; These can actually be used for adding numbers in the range -8 to 7
2213:
2214: (define_insn ""
2215: [(set (pc)
2216: (if_then_else
2217: (ne (minus:SI (match_operand:SI 0 "general_operand" "+g")
2218: (match_operand:SI 1 "general_operand" "i"))
2219: (const_int 0))
2220: (label_ref (match_operand 2 "" ""))
2221: (pc)))
2222: (set (match_dup 0)
2223: (minus:SI (match_dup 0)
2224: (match_dup 1)))]
2225: "GET_CODE (operands[1]) == CONST_INT
2226: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2227: "acbd %$%n1,%0,%l2")
2228:
2229: (define_insn ""
2230: [(set (pc)
2231: (if_then_else
2232: (ne (plus:SI (match_operand:SI 0 "general_operand" "+g")
2233: (match_operand:SI 1 "general_operand" "i"))
2234: (const_int 0))
2235: (label_ref (match_operand 2 "" ""))
2236: (pc)))
2237: (set (match_dup 0)
2238: (plus:SI (match_dup 0)
2239: (match_dup 1)))]
2240: "GET_CODE (operands[1]) == CONST_INT
2241: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2242: "acbd %1,%0,%l2")
2243:
2244: ;; Reversed
2245:
2246: (define_insn ""
2247: [(set (pc)
2248: (if_then_else
2249: (eq (minus:SI (match_operand:SI 0 "general_operand" "+g")
2250: (match_operand:SI 1 "general_operand" "i"))
2251: (const_int 0))
2252: (pc)
2253: (label_ref (match_operand 2 "" ""))))
2254: (set (match_dup 0)
2255: (minus:SI (match_dup 0)
2256: (match_dup 1)))]
2257: "GET_CODE (operands[1]) == CONST_INT
2258: && INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2259: "acbd %$%n1,%0,%l2")
2260:
2261: (define_insn ""
2262: [(set (pc)
2263: (if_then_else
2264: (eq (plus:SI (match_operand:SI 0 "general_operand" "+g")
2265: (match_operand:SI 1 "general_operand" "i"))
2266: (const_int 0))
2267: (pc)
2268: (label_ref (match_operand 2 "" ""))))
2269: (set (match_dup 0)
2270: (plus:SI (match_dup 0)
2271: (match_dup 1)))]
2272: "GET_CODE (operands[1]) == CONST_INT
2273: && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 8"
2274: "acbd %1,%0,%l2")
2275:
2276: (define_insn "call"
2277: [(call (match_operand:QI 0 "general_operand" "g")
2278: (match_operand:QI 1 "general_operand" "g"))]
2279: ""
2280: "*
2281: {
1.1.1.3 ! root 2282: #ifndef JSR_ALWAYS
1.1 root 2283: if (GET_CODE (operands[0]) == MEM)
2284: {
1.1.1.3 ! root 2285: rtx temp = XEXP (operands[0], 0);
! 2286: if (CONSTANT_ADDRESS_P (temp))
! 2287: {
! 2288: #ifdef GAS_SYNTAX
! 2289: operands[0] = temp;
! 2290: return \"bsr %0\";
! 2291: #else
1.1 root 2292: #ifdef GNX_V3
1.1.1.3 ! root 2293: return \"bsr %0\";
1.1 root 2294: #else
1.1.1.3 ! root 2295: return \"bsr %?%a0\";
! 2296: #endif
1.1 root 2297: #endif
1.1.1.3 ! root 2298: }
1.1 root 2299: if (GET_CODE (XEXP (operands[0], 0)) == REG)
1.1.1.3 ! root 2300: #if defined(GNX_V3) || defined(GAS_SYNTAX)
1.1 root 2301: return \"jsr %0\";
2302: #else
2303: return \"jsr %a0\";
2304: #endif
2305: }
1.1.1.3 ! root 2306: #endif /* not JSR_ALWAYS */
1.1 root 2307: return \"jsr %0\";
2308: }")
2309:
2310: (define_insn "call_value"
2311: [(set (match_operand 0 "" "=fg")
2312: (call (match_operand:QI 1 "general_operand" "g")
2313: (match_operand:QI 2 "general_operand" "g")))]
2314: ""
2315: "*
2316: {
1.1.1.3 ! root 2317: #ifndef JSR_ALWAYS
! 2318: if (GET_CODE (operands[0]) == MEM)
1.1 root 2319: {
1.1.1.3 ! root 2320: rtx temp = XEXP (operands[0], 0);
! 2321: if (CONSTANT_ADDRESS_P (temp))
! 2322: {
! 2323: #ifdef GAS_SYNTAX
! 2324: operands[0] = temp;
! 2325: return \"bsr %1\";
! 2326: #else
1.1 root 2327: #ifdef GNX_V3
1.1.1.3 ! root 2328: return \"bsr %1\";
1.1 root 2329: #else
1.1.1.3 ! root 2330: return \"bsr %?%a1\";
1.1 root 2331: #endif
1.1.1.3 ! root 2332: #endif
! 2333: }
! 2334: if (GET_CODE (XEXP (operands[0], 0)) == REG)
! 2335: #if defined(GNX_V3) || defined(GAS_SYNTAX)
1.1 root 2336: return \"jsr %1\";
2337: #else
2338: return \"jsr %a1\";
2339: #endif
2340: }
1.1.1.3 ! root 2341: #endif /* not JSR_ALWAYS */
1.1 root 2342: return \"jsr %1\";
2343: }")
2344:
2345: (define_insn "return"
2346: [(return)]
2347: "0"
2348: "ret 0")
2349:
2350: (define_insn "abssf2"
2351: [(set (match_operand:SF 0 "general_operand" "=fm<")
2352: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2353: "TARGET_32081"
2354: "absf %1,%0")
2355:
2356: (define_insn "absdf2"
2357: [(set (match_operand:DF 0 "general_operand" "=fm<")
2358: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2359: "TARGET_32081"
2360: "absl %1,%0")
2361:
2362: (define_insn "abssi2"
2363: [(set (match_operand:SI 0 "general_operand" "=g<")
2364: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2365: ""
2366: "absd %1,%0")
2367:
2368: (define_insn "abshi2"
2369: [(set (match_operand:HI 0 "general_operand" "=g<")
2370: (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2371: ""
2372: "absw %1,%0")
2373:
2374: (define_insn "absqi2"
2375: [(set (match_operand:QI 0 "general_operand" "=g<")
2376: (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2377: ""
2378: "absb %1,%0")
2379:
2380: (define_insn "nop"
2381: [(const_int 0)]
2382: ""
2383: "nop")
2384:
2385: ;;(define_insn "tablejump"
2386: ;; [(set (pc)
2387: ;; (plus:SI (match_operand:SI 0 "general_operand" "g")
2388: ;; (pc)))]
2389: ;; ""
2390: ;; "cased %0")
2391:
2392: (define_insn "tablejump"
2393: [(set (pc)
2394: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g")))
2395: (use (label_ref (match_operand 1 "" "")))]
2396: ""
2397: "*
2398: {
2399: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2400: CODE_LABEL_NUMBER (operands[1]));
2401: return \"casew %0\";
2402: }")
2403:
2404: ;;(define_insn ""
2405: ;; [(set (pc)
2406: ;; (plus:SI (match_operand:QI 0 "general_operand" "g")
2407: ;; (pc)))]
2408: ;; ""
2409: ;; "caseb %0")
2410:
2411: ;; Scondi instructions
2412: (define_insn "seq"
2413: [(set (match_operand:SI 0 "general_operand" "=g<")
2414: (eq (cc0) (const_int 0)))]
2415: ""
2416: "*
2417: { if (cc_prev_status.flags & CC_Z_IN_F)
2418: return \"sfcd %0\";
2419: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2420: return \"sfsd %0\";
2421: else return \"seqd %0\";
2422: }")
2423:
2424: (define_insn ""
2425: [(set (match_operand:HI 0 "general_operand" "=g<")
2426: (eq (cc0) (const_int 0)))]
2427: ""
2428: "*
2429: { if (cc_prev_status.flags & CC_Z_IN_F)
2430: return \"sfcw %0\";
2431: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2432: return \"sfsw %0\";
2433: else return \"seqw %0\";
2434: }")
2435:
2436: (define_insn ""
2437: [(set (match_operand:QI 0 "general_operand" "=g<")
2438: (eq (cc0) (const_int 0)))]
2439: ""
2440: "*
2441: { if (cc_prev_status.flags & CC_Z_IN_F)
2442: return \"sfcb %0\";
2443: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2444: return \"sfsb %0\";
2445: else return \"seqb %0\";
2446: }")
2447:
2448: (define_insn "sne"
2449: [(set (match_operand:SI 0 "general_operand" "=g<")
2450: (ne (cc0) (const_int 0)))]
2451: ""
2452: "*
2453: { if (cc_prev_status.flags & CC_Z_IN_F)
2454: return \"sfsd %0\";
2455: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2456: return \"sfcd %0\";
2457: else return \"sned %0\";
2458: }")
2459:
2460: (define_insn ""
2461: [(set (match_operand:HI 0 "general_operand" "=g<")
2462: (ne (cc0) (const_int 0)))]
2463: ""
2464: "*
2465: { if (cc_prev_status.flags & CC_Z_IN_F)
2466: return \"sfsw %0\";
2467: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2468: return \"sfcw %0\";
2469: else return \"snew %0\";
2470: }")
2471:
2472: (define_insn ""
2473: [(set (match_operand:QI 0 "general_operand" "=g<")
2474: (ne (cc0) (const_int 0)))]
2475: ""
2476: "*
2477: { if (cc_prev_status.flags & CC_Z_IN_F)
2478: return \"sfsb %0\";
2479: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2480: return \"sfcb %0\";
2481: else return \"sneb %0\";
2482: }")
2483:
2484: (define_insn "sgt"
2485: [(set (match_operand:SI 0 "general_operand" "=g<")
2486: (gt (cc0) (const_int 0)))]
2487: ""
2488: "sgtd %0")
2489:
2490: (define_insn ""
2491: [(set (match_operand:HI 0 "general_operand" "=g<")
2492: (gt (cc0) (const_int 0)))]
2493: ""
2494: "sgtw %0")
2495:
2496: (define_insn ""
2497: [(set (match_operand:QI 0 "general_operand" "=g<")
2498: (gt (cc0) (const_int 0)))]
2499: ""
2500: "sgtb %0")
2501:
2502: (define_insn "sgtu"
2503: [(set (match_operand:SI 0 "general_operand" "=g<")
2504: (gtu (cc0) (const_int 0)))]
2505: ""
2506: "shid %0")
2507:
2508: (define_insn ""
2509: [(set (match_operand:HI 0 "general_operand" "=g<")
2510: (gtu (cc0) (const_int 0)))]
2511: ""
2512: "shiw %0")
2513:
2514: (define_insn ""
2515: [(set (match_operand:QI 0 "general_operand" "=g<")
2516: (gtu (cc0) (const_int 0)))]
2517: ""
2518: "shib %0")
2519:
2520: (define_insn "slt"
2521: [(set (match_operand:SI 0 "general_operand" "=g<")
2522: (lt (cc0) (const_int 0)))]
2523: ""
2524: "sltd %0")
2525:
2526: (define_insn ""
2527: [(set (match_operand:HI 0 "general_operand" "=g<")
2528: (lt (cc0) (const_int 0)))]
2529: ""
2530: "sltw %0")
2531:
2532: (define_insn ""
2533: [(set (match_operand:QI 0 "general_operand" "=g<")
2534: (lt (cc0) (const_int 0)))]
2535: ""
2536: "sltb %0")
2537:
2538: (define_insn "sltu"
2539: [(set (match_operand:SI 0 "general_operand" "=g<")
2540: (ltu (cc0) (const_int 0)))]
2541: ""
2542: "slod %0")
2543:
2544: (define_insn ""
2545: [(set (match_operand:HI 0 "general_operand" "=g<")
2546: (ltu (cc0) (const_int 0)))]
2547: ""
2548: "slow %0")
2549:
2550: (define_insn ""
2551: [(set (match_operand:QI 0 "general_operand" "=g<")
2552: (ltu (cc0) (const_int 0)))]
2553: ""
2554: "slob %0")
2555:
2556: (define_insn "sge"
2557: [(set (match_operand:SI 0 "general_operand" "=g<")
2558: (ge (cc0) (const_int 0)))]
2559: ""
2560: "sged %0")
2561:
2562: (define_insn ""
2563: [(set (match_operand:HI 0 "general_operand" "=g<")
2564: (ge (cc0) (const_int 0)))]
2565: ""
2566: "sgew %0")
2567:
2568: (define_insn ""
2569: [(set (match_operand:QI 0 "general_operand" "=g<")
2570: (ge (cc0) (const_int 0)))]
2571: ""
2572: "sgeb %0")
2573:
2574: (define_insn "sgeu"
2575: [(set (match_operand:SI 0 "general_operand" "=g<")
2576: (geu (cc0) (const_int 0)))]
2577: ""
2578: "shsd %0")
2579:
2580: (define_insn ""
2581: [(set (match_operand:HI 0 "general_operand" "=g<")
2582: (geu (cc0) (const_int 0)))]
2583: ""
2584: "shsw %0")
2585:
2586: (define_insn ""
2587: [(set (match_operand:QI 0 "general_operand" "=g<")
2588: (geu (cc0) (const_int 0)))]
2589: ""
2590: "shsb %0")
2591:
2592: (define_insn "sle"
2593: [(set (match_operand:SI 0 "general_operand" "=g<")
2594: (le (cc0) (const_int 0)))]
2595: ""
2596: "sled %0")
2597:
2598: (define_insn ""
2599: [(set (match_operand:HI 0 "general_operand" "=g<")
2600: (le (cc0) (const_int 0)))]
2601: ""
2602: "slew %0")
2603:
2604: (define_insn ""
2605: [(set (match_operand:QI 0 "general_operand" "=g<")
2606: (le (cc0) (const_int 0)))]
2607: ""
2608: "sleb %0")
2609:
2610: (define_insn "sleu"
2611: [(set (match_operand:SI 0 "general_operand" "=g<")
2612: (leu (cc0) (const_int 0)))]
2613: ""
2614: "slsd %0")
2615:
2616: (define_insn ""
2617: [(set (match_operand:HI 0 "general_operand" "=g<")
2618: (leu (cc0) (const_int 0)))]
2619: ""
2620: "slsw %0")
2621:
2622: (define_insn ""
2623: [(set (match_operand:QI 0 "general_operand" "=g<")
2624: (leu (cc0) (const_int 0)))]
2625: ""
2626: "slsb %0")
2627:
2628: ;;- Local variables:
2629: ;;- mode:emacs-lisp
2630: ;;- comment-start: ";;- "
2631: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2632: ;;- eval: (modify-syntax-entry ?[ "(]")
2633: ;;- eval: (modify-syntax-entry ?] ")[")
2634: ;;- eval: (modify-syntax-entry ?{ "(}")
2635: ;;- eval: (modify-syntax-entry ?} "){")
2636: ;;- End:
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.