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1.1 root 1: ; BUGS:
2: ;; Insert no-op between an insn with memory read-write operands
3: ;; following by a scale-indexing operation.
4: ;; The Sequent assembler does not allow addresses to be used
5: ;; except in insns which explicitly compute an effective address.
6: ;; I.e., one cannot say "cmpd _p,@_x"
7: ;; Implement unsigned multiplication??
8:
1.1.1.2 root 9: ;;- Machine description for GNU compiler
1.1 root 10: ;;- ns32000 Version
11: ;; Copyright (C) 1988 Free Software Foundation, Inc.
12: ;; Contributed by Michael Tiemann ([email protected])
13:
14: ;; This file is part of GNU CC.
15:
16: ;; GNU CC is free software; you can redistribute it and/or modify
17: ;; it under the terms of the GNU General Public License as published by
18: ;; the Free Software Foundation; either version 2, or (at your option)
19: ;; any later version.
20:
21: ;; GNU CC is distributed in the hope that it will be useful,
22: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
23: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24: ;; GNU General Public License for more details.
25:
26: ;; You should have received a copy of the GNU General Public License
27: ;; along with GNU CC; see the file COPYING. If not, write to
28: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
29:
30:
31: ;;- Instruction patterns. When multiple patterns apply,
32: ;;- the first one in the file is chosen.
33: ;;-
34: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
35: ;;-
36: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
37: ;;- updates for most instructions.
38:
39: ;; We don't want to allow a constant operand for test insns because
40: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
41: ;; be folded while optimizing anyway.
42:
43: (define_insn "tstsi"
44: [(set (cc0)
45: (match_operand:SI 0 "nonimmediate_operand" "rm"))]
46: ""
47: "*
48: { cc_status.flags |= CC_REVERSED;
49: operands[1] = const0_rtx;
50: return \"cmpqd %1,%0\"; }")
51:
52: (define_insn "tsthi"
53: [(set (cc0)
54: (match_operand:HI 0 "nonimmediate_operand" "g"))]
55: ""
56: "*
57: { cc_status.flags |= CC_REVERSED;
58: operands[1] = const0_rtx;
59: return \"cmpqw %1,%0\"; }")
60:
61: (define_insn "tstqi"
62: [(set (cc0)
63: (match_operand:QI 0 "nonimmediate_operand" "g"))]
64: ""
65: "*
66: { cc_status.flags |= CC_REVERSED;
67: operands[1] = const0_rtx;
68: return \"cmpqb %1,%0\"; }")
69:
70: (define_insn "tstdf"
71: [(set (cc0)
72: (match_operand:DF 0 "general_operand" "fmF"))]
73: "TARGET_32081"
74: "*
75: { cc_status.flags |= CC_REVERSED;
76: operands[1] = CONST0_RTX (DFmode);
77: return \"cmpl %1,%0\"; }")
78:
79: (define_insn "tstsf"
80: [(set (cc0)
81: (match_operand:SF 0 "general_operand" "fmF"))]
82: "TARGET_32081"
83: "*
84: { cc_status.flags |= CC_REVERSED;
85: operands[1] = CONST0_RTX (SFmode);
86: return \"cmpf %1,%0\"; }")
87:
88: (define_insn "cmpsi"
89: [(set (cc0)
90: (compare (match_operand:SI 0 "nonimmediate_operand" "rmn")
91: (match_operand:SI 1 "general_operand" "rmn")))]
92: ""
93: "*
94: {
95: if (GET_CODE (operands[1]) == CONST_INT)
96: {
97: int i = INTVAL (operands[1]);
98: if (i <= 7 && i >= -8)
99: {
100: cc_status.flags |= CC_REVERSED;
101: return \"cmpqd %1,%0\";
102: }
103: }
104: cc_status.flags &= ~CC_REVERSED;
105: if (GET_CODE (operands[0]) == CONST_INT)
106: {
107: int i = INTVAL (operands[0]);
108: if (i <= 7 && i >= -8)
109: return \"cmpqd %0,%1\";
110: }
111: return \"cmpd %0,%1\";
112: }")
113:
114: (define_insn "cmphi"
115: [(set (cc0)
116: (compare (match_operand:HI 0 "nonimmediate_operand" "g")
117: (match_operand:HI 1 "general_operand" "g")))]
118: ""
119: "*
120: {
121: if (GET_CODE (operands[1]) == CONST_INT)
122: {
123: short i = INTVAL (operands[1]);
124: if (i <= 7 && i >= -8)
125: {
126: cc_status.flags |= CC_REVERSED;
127: if (INTVAL (operands[1]) > 7)
128: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
129: return \"cmpqw %1,%0\";
130: }
131: }
132: cc_status.flags &= ~CC_REVERSED;
133: if (GET_CODE (operands[0]) == CONST_INT)
134: {
135: short i = INTVAL (operands[0]);
136: if (i <= 7 && i >= -8)
137: {
138: if (INTVAL (operands[0]) > 7)
139: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
140: return \"cmpqw %0,%1\";
141: }
142: }
143: return \"cmpw %0,%1\";
144: }")
145:
146: (define_insn "cmpqi"
147: [(set (cc0)
148: (compare (match_operand:QI 0 "nonimmediate_operand" "g")
149: (match_operand:QI 1 "general_operand" "g")))]
150: ""
151: "*
152: {
153: if (GET_CODE (operands[1]) == CONST_INT)
154: {
155: char i = INTVAL (operands[1]);
156: if (i <= 7 && i >= -8)
157: {
158: cc_status.flags |= CC_REVERSED;
159: if (INTVAL (operands[1]) > 7)
160: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
161: return \"cmpqb %1,%0\";
162: }
163: }
164: cc_status.flags &= ~CC_REVERSED;
165: if (GET_CODE (operands[0]) == CONST_INT)
166: {
167: char i = INTVAL (operands[0]);
168: if (i <= 7 && i >= -8)
169: {
170: if (INTVAL (operands[0]) > 7)
171: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
172: return \"cmpqb %0,%1\";
173: }
174: }
175: return \"cmpb %0,%1\";
176: }")
177:
178: (define_insn "cmpdf"
179: [(set (cc0)
180: (compare (match_operand:DF 0 "general_operand" "fmF")
181: (match_operand:DF 1 "general_operand" "fmF")))]
182: "TARGET_32081"
183: "cmpl %0,%1")
184:
185: (define_insn "cmpsf"
186: [(set (cc0)
187: (compare (match_operand:SF 0 "general_operand" "fmF")
188: (match_operand:SF 1 "general_operand" "fmF")))]
189: "TARGET_32081"
190: "cmpf %0,%1")
191:
192: (define_insn "movdf"
193: [(set (match_operand:DF 0 "general_operand" "=&fg<")
194: (match_operand:DF 1 "general_operand" "fFg"))]
195: ""
196: "*
197: {
198: if (FP_REG_P (operands[0]))
199: {
200: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
201: return \"movl %1,%0\";
202: if (REG_P (operands[1]))
203: {
204: rtx xoperands[2];
205: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
206: output_asm_insn (\"movd %1,tos\", xoperands);
207: output_asm_insn (\"movd %1,tos\", operands);
208: return \"movl tos,%0\";
209: }
210: return \"movl %1,%0\";
211: }
212: else if (FP_REG_P (operands[1]))
213: {
214: if (REG_P (operands[0]))
215: {
216: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
217: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
218: return \"movd tos,%0\";
219: }
220: else
221: return \"movl %1,%0\";
222: }
223: return output_move_double (operands);
224: }")
225:
226: (define_insn "movsf"
227: [(set (match_operand:SF 0 "general_operand" "=fg<")
228: (match_operand:SF 1 "general_operand" "fFg"))]
229: ""
230: "*
231: {
232: if (FP_REG_P (operands[0]))
233: {
234: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
235: return \"movd %1,tos\;movf tos,%0\";
236: else
237: return \"movf %1,%0\";
238: }
239: else if (FP_REG_P (operands[1]))
240: {
241: if (REG_P (operands[0]))
242: return \"movf %1,tos\;movd tos,%0\";
243: return \"movf %1,%0\";
244: }
1.1.1.2 root 245: #if 0 /* Someone suggested this for the Sequent. Is it needed? */
246: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
247: return \"movf %1,%0\";
248: #endif
249: /* There was a #if 0 around this, but that was erroneous
1.1.1.3 ! root 250: for many machines -- rms. */
! 251: #ifndef MOVD_FLOAT_OK
1.1 root 252: /* GAS understands floating constants in ordinary movd instructions
253: but other assemblers might object. */
254: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
255: {
256: union {int i[2]; float f; double d;} convrt;
257: convrt.i[0] = CONST_DOUBLE_LOW (operands[1]);
258: convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]);
259: convrt.f = convrt.d;
260:
261: /* Is there a better machine-independent way to to this? */
262: operands[1] = gen_rtx (CONST_INT, VOIDmode, convrt.i[0]);
263: return \"movd %1,%0\";
264: }
265: #endif
266: else return \"movd %1,%0\";
267: }")
268:
269: (define_insn ""
270: [(set (match_operand:TI 0 "memory_operand" "=m")
271: (match_operand:TI 1 "memory_operand" "m"))]
272: ""
273: "movmd %1,%0,4")
274:
275: (define_insn "movdi"
276: [(set (match_operand:DI 0 "general_operand" "=&g<,*f,g")
277: (match_operand:DI 1 "general_operand" "gF,g,*f"))]
278: ""
279: "*
280: {
281: if (FP_REG_P (operands[0]))
282: {
283: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
284: return \"movl %1,%0\";
285: if (REG_P (operands[1]))
286: {
287: rtx xoperands[2];
288: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
289: output_asm_insn (\"movd %1,tos\", xoperands);
290: output_asm_insn (\"movd %1,tos\", operands);
291: return \"movl tos,%0\";
292: }
293: return \"movl %1,%0\";
294: }
295: else if (FP_REG_P (operands[1]))
296: {
297: if (REG_P (operands[0]))
298: {
299: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
300: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
301: return \"movd tos,%0\";
302: }
303: else
304: return \"movl %1,%0\";
305: }
306: return output_move_double (operands);
307: }")
308:
309: ;; This special case must precede movsi.
310: (define_insn ""
311: [(set (reg:SI 17)
312: (match_operand:SI 0 "general_operand" "rmn"))]
313: ""
314: "lprd sp,%0")
315:
316: (define_insn "movsi"
317: [(set (match_operand:SI 0 "general_operand" "=g<,*f,g")
318: (match_operand:SI 1 "general_operand" "gxy,g,*f"))]
319: ""
320: "*
321: {
322: if (FP_REG_P (operands[0]))
323: {
324: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
325: return \"movd %1,tos\;movf tos,%0\";
326: else
327: return \"movf %1,%0\";
328: }
329: else if (FP_REG_P (operands[1]))
330: {
331: if (REG_P (operands[0]))
332: return \"movf %1,tos\;movd tos,%0\";
333: return \"movf %1,%0\";
334: }
335: if (GET_CODE (operands[1]) == CONST_INT)
336: {
337: int i = INTVAL (operands[1]);
338: if (i <= 7 && i >= -8)
339: return \"movqd %1,%0\";
340: if (i < 0x4000 && i >= -0x4000 && ! TARGET_32532)
341: #if defined (GNX_V3) || defined (UTEK_ASM)
342: return \"addr %c1,%0\";
343: #else
344: return \"addr @%c1,%0\";
345: #endif
346: return \"movd %1,%0\";
347: }
348: else if (GET_CODE (operands[1]) == REG)
349: {
350: if (REGNO (operands[1]) < 16)
351: return \"movd %1,%0\";
352: else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM)
353: {
354: if (GET_CODE(operands[0]) == REG)
355: return \"sprd fp,%0\";
356: else
357: return \"addr 0(fp),%0\" ;
358: }
359: else if (REGNO (operands[1]) == STACK_POINTER_REGNUM)
360: {
361: if (GET_CODE(operands[0]) == REG)
362: return \"sprd sp,%0\";
363: else
364: return \"addr 0(sp),%0\" ;
365: }
366: else abort ();
367: }
368: else if (GET_CODE (operands[1]) == MEM)
369: return \"movd %1,%0\";
370: /* Check if this effective address can be
371: calculated faster by pulling it apart. */
372: if (REG_P (operands[0])
373: && GET_CODE (operands[1]) == MULT
374: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
375: && (INTVAL (XEXP (operands[1], 1)) == 2
376: || INTVAL (XEXP (operands[1], 1)) == 4))
377: {
378: rtx xoperands[3];
379: xoperands[0] = operands[0];
380: xoperands[1] = XEXP (operands[1], 0);
381: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
382: return output_shift_insn (xoperands);
383: }
384: return \"addr %a1,%0\";
385: }")
386:
387: (define_insn "movhi"
388: [(set (match_operand:HI 0 "general_operand" "=g<,*f,g")
389: (match_operand:HI 1 "general_operand" "g,g,*f"))]
390: ""
391: "*
392: {
393: if (GET_CODE (operands[1]) == CONST_INT)
394: {
395: short i = INTVAL (operands[1]);
396: if (i <= 7 && i >= -8)
397: {
398: if (INTVAL (operands[1]) > 7)
399: operands[1] =
400: gen_rtx (CONST_INT, VOIDmode, i);
401: return \"movqw %1,%0\";
402: }
403: return \"movw %1,%0\";
404: }
405: else if (FP_REG_P (operands[0]))
406: {
407: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
408: return \"movwf %1,tos\;movf tos,%0\";
409: else
410: return \"movwf %1,%0\";
411: }
412: else if (FP_REG_P (operands[1]))
413: {
414: if (REG_P (operands[0]))
415: return \"movf %1,tos\;movd tos,%0\";
416: return \"movf %1,%0\";
417: }
418: else
419: return \"movw %1,%0\";
420: }")
421:
422: (define_insn "movstricthi"
423: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
424: (match_operand:HI 1 "general_operand" "g"))]
425: ""
426: "*
427: {
428: if (GET_CODE (operands[1]) == CONST_INT
429: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
430: return \"movqw %1,%0\";
431: return \"movw %1,%0\";
432: }")
433:
434: (define_insn "movqi"
435: [(set (match_operand:QI 0 "general_operand" "=g<,*f,g")
436: (match_operand:QI 1 "general_operand" "g,g,*f"))]
437: ""
438: "*
439: { if (GET_CODE (operands[1]) == CONST_INT)
440: {
441: char char_val = (char)INTVAL (operands[1]);
442: if (char_val <= 7 && char_val >= -8)
443: {
444: if (INTVAL (operands[1]) > 7)
445: operands[1] =
446: gen_rtx (CONST_INT, VOIDmode, char_val);
447: return \"movqb %1,%0\";
448: }
449: return \"movb %1,%0\";
450: }
451: else if (FP_REG_P (operands[0]))
452: {
453: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
454: return \"movbf %1,tos\;movf tos,%0\";
455: else
456: return \"movbf %1,%0\";
457: }
458: else if (FP_REG_P (operands[1]))
459: {
460: if (REG_P (operands[0]))
461: return \"movf %1,tos\;movd tos,%0\";
462: return \"movf %1,%0\";
463: }
464: else
465: return \"movb %1,%0\";
466: }")
467:
468: (define_insn "movstrictqi"
469: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
470: (match_operand:QI 1 "general_operand" "g"))]
471: ""
472: "*
473: {
474: if (GET_CODE (operands[1]) == CONST_INT
475: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
476: return \"movqb %1,%0\";
477: return \"movb %1,%0\";
478: }")
479:
480: ;; The definition of this insn does not really explain what it does,
481: ;; but it should suffice
482: ;; that anything generated as this insn will be recognized as one
483: ;; and that it won't successfully combine with anything.
484: (define_insn "movstrsi"
485: [(set (match_operand:BLK 0 "general_operand" "=g")
486: (match_operand:BLK 1 "general_operand" "g"))
487: (use (match_operand:SI 2 "general_operand" "rmn"))
488: (clobber (reg:SI 0))
489: (clobber (reg:SI 1))
490: (clobber (reg:SI 2))]
491: ""
492: "*
493: {
494: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
495: abort ();
496: operands[0] = XEXP (operands[0], 0);
497: operands[1] = XEXP (operands[1], 0);
498: if (GET_CODE (operands[0]) == MEM)
499: if (GET_CODE (operands[1]) == MEM)
500: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
501: else
502: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
503: else if (GET_CODE (operands[1]) == MEM)
504: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
505: else
506: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
507:
508: #ifdef UTEK_ASM
509: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
510: {
511: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
512: if ((unsigned) INTVAL (operands[2]) <= 7)
513: return \"movqd %2,r0\;movsd $0\";
514: else
515: return \"movd %2,r0\;movsd $0\";
516: }
517: else
518: {
519: return \"movd %2,r0\;movsb $0\";
520: }
521: #else
522: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
523: {
524: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
525: if ((unsigned) INTVAL (operands[2]) <= 7)
526: return \"movqd %2,r0\;movsd\";
527: else
528: return \"movd %2,r0\;movsd\";
529: }
530: else
531: {
532: return \"movd %2,r0\;movsb\";
533: }
534: #endif
535: }")
536:
537: ;; Extension and truncation insns.
538: ;; Those for integer source operand
539: ;; are ordered widest source type first.
540:
541: (define_insn "truncsiqi2"
542: [(set (match_operand:QI 0 "general_operand" "=g<")
543: (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "rmn")))]
544: ""
545: "movb %1,%0")
546:
547: (define_insn "truncsihi2"
548: [(set (match_operand:HI 0 "general_operand" "=g<")
549: (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "rmn")))]
550: ""
551: "movw %1,%0")
552:
553: (define_insn "trunchiqi2"
554: [(set (match_operand:QI 0 "general_operand" "=g<")
555: (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
556: ""
557: "movb %1,%0")
558:
559: (define_insn "extendhisi2"
560: [(set (match_operand:SI 0 "general_operand" "=g<")
561: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
562: ""
563: "movxwd %1,%0")
564:
565: (define_insn "extendqihi2"
566: [(set (match_operand:HI 0 "general_operand" "=g<")
567: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
568: ""
569: "movxbw %1,%0")
570:
571: (define_insn "extendqisi2"
572: [(set (match_operand:SI 0 "general_operand" "=g<")
573: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
574: ""
575: "movxbd %1,%0")
576:
577: (define_insn "extendsfdf2"
578: [(set (match_operand:DF 0 "general_operand" "=fm<")
579: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
580: "TARGET_32081"
581: "movfl %1,%0")
582:
583: (define_insn "truncdfsf2"
584: [(set (match_operand:SF 0 "general_operand" "=fm<")
585: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
586: "TARGET_32081"
587: "movlf %1,%0")
588:
589: (define_insn "zero_extendhisi2"
590: [(set (match_operand:SI 0 "general_operand" "=g<")
591: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
592: ""
593: "movzwd %1,%0")
594:
595: (define_insn "zero_extendqihi2"
596: [(set (match_operand:HI 0 "general_operand" "=g<")
597: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
598: ""
599: "movzbw %1,%0")
600:
601: (define_insn "zero_extendqisi2"
602: [(set (match_operand:SI 0 "general_operand" "=g<")
603: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
604: ""
605: "movzbd %1,%0")
606:
607: ;; Fix-to-float conversion insns.
608: ;; Note that the ones that start with SImode come first.
609: ;; That is so that an operand that is a CONST_INT
610: ;; (and therefore lacks a specific machine mode).
611: ;; will be recognized as SImode (which is always valid)
612: ;; rather than as QImode or HImode.
613:
614: ;; Rumor has it that the National part does not correctly convert
615: ;; constant ints to floats. This conversion is therefore disabled.
616: ;; A register must be used to perform the conversion.
617:
618: (define_insn "floatsisf2"
619: [(set (match_operand:SF 0 "general_operand" "=fm<")
620: (float:SF (match_operand:SI 1 "general_operand" "rm")))]
621: "TARGET_32081"
622: "movdf %1,%0")
623:
624: (define_insn "floatsidf2"
625: [(set (match_operand:DF 0 "general_operand" "=fm<")
626: (float:DF (match_operand:SI 1 "general_operand" "rm")))]
627: "TARGET_32081"
628: "movdl %1,%0")
629:
630: (define_insn "floathisf2"
631: [(set (match_operand:SF 0 "general_operand" "=fm<")
632: (float:SF (match_operand:HI 1 "general_operand" "rm")))]
633: "TARGET_32081"
634: "movwf %1,%0")
635:
636: (define_insn "floathidf2"
637: [(set (match_operand:DF 0 "general_operand" "=fm<")
638: (float:DF (match_operand:HI 1 "general_operand" "rm")))]
639: "TARGET_32081"
640: "movwl %1,%0")
641:
642: (define_insn "floatqisf2"
643: [(set (match_operand:SF 0 "general_operand" "=fm<")
644: (float:SF (match_operand:QI 1 "general_operand" "rm")))]
645: "TARGET_32081"
646: "movbf %1,%0")
647:
648: ; Some assemblers warn that this insn doesn't work.
649: ; Maybe they know something we don't.
650: ;(define_insn "floatqidf2"
651: ; [(set (match_operand:DF 0 "general_operand" "=fm<")
652: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
653: ; "TARGET_32081"
654: ; "movbl %1,%0")
655:
656: ;; Float-to-fix conversion insns.
657: ;; The sequent compiler always generates "trunc" insns.
658:
659: (define_insn "fixsfqi2"
660: [(set (match_operand:QI 0 "general_operand" "=g<")
661: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
662: "TARGET_32081"
663: "truncfb %1,%0")
664:
665: (define_insn "fixsfhi2"
666: [(set (match_operand:HI 0 "general_operand" "=g<")
667: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
668: "TARGET_32081"
669: "truncfw %1,%0")
670:
671: (define_insn "fixsfsi2"
672: [(set (match_operand:SI 0 "general_operand" "=g<")
673: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
674: "TARGET_32081"
675: "truncfd %1,%0")
676:
677: (define_insn "fixdfqi2"
678: [(set (match_operand:QI 0 "general_operand" "=g<")
679: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
680: "TARGET_32081"
681: "trunclb %1,%0")
682:
683: (define_insn "fixdfhi2"
684: [(set (match_operand:HI 0 "general_operand" "=g<")
685: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
686: "TARGET_32081"
687: "trunclw %1,%0")
688:
689: (define_insn "fixdfsi2"
690: [(set (match_operand:SI 0 "general_operand" "=g<")
691: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
692: "TARGET_32081"
693: "truncld %1,%0")
694:
695: ;; Unsigned
696:
697: (define_insn "fixunssfqi2"
698: [(set (match_operand:QI 0 "general_operand" "=g<")
699: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
700: "TARGET_32081"
701: "truncfb %1,%0")
702:
703: (define_insn "fixunssfhi2"
704: [(set (match_operand:HI 0 "general_operand" "=g<")
705: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
706: "TARGET_32081"
707: "truncfw %1,%0")
708:
709: (define_insn "fixunssfsi2"
710: [(set (match_operand:SI 0 "general_operand" "=g<")
711: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
712: "TARGET_32081"
713: "truncfd %1,%0")
714:
715: (define_insn "fixunsdfqi2"
716: [(set (match_operand:QI 0 "general_operand" "=g<")
717: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
718: "TARGET_32081"
719: "trunclb %1,%0")
720:
721: (define_insn "fixunsdfhi2"
722: [(set (match_operand:HI 0 "general_operand" "=g<")
723: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
724: "TARGET_32081"
725: "trunclw %1,%0")
726:
727: (define_insn "fixunsdfsi2"
728: [(set (match_operand:SI 0 "general_operand" "=g<")
729: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
730: "TARGET_32081"
731: "truncld %1,%0")
732:
733: ;;; These are not yet used by GCC
734: (define_insn "fix_truncsfqi2"
735: [(set (match_operand:QI 0 "general_operand" "=g<")
736: (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
737: "TARGET_32081"
738: "truncfb %1,%0")
739:
740: (define_insn "fix_truncsfhi2"
741: [(set (match_operand:HI 0 "general_operand" "=g<")
742: (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
743: "TARGET_32081"
744: "truncfw %1,%0")
745:
746: (define_insn "fix_truncsfsi2"
747: [(set (match_operand:SI 0 "general_operand" "=g<")
748: (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
749: "TARGET_32081"
750: "truncfd %1,%0")
751:
752: (define_insn "fix_truncdfqi2"
753: [(set (match_operand:QI 0 "general_operand" "=g<")
754: (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
755: "TARGET_32081"
756: "trunclb %1,%0")
757:
758: (define_insn "fix_truncdfhi2"
759: [(set (match_operand:HI 0 "general_operand" "=g<")
760: (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
761: "TARGET_32081"
762: "trunclw %1,%0")
763:
764: (define_insn "fix_truncdfsi2"
765: [(set (match_operand:SI 0 "general_operand" "=g<")
766: (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
767: "TARGET_32081"
768: "truncld %1,%0")
769:
770: ;;- All kinds of add instructions.
771:
772: (define_insn "adddf3"
773: [(set (match_operand:DF 0 "general_operand" "=fm")
774: (plus:DF (match_operand:DF 1 "general_operand" "%0")
775: (match_operand:DF 2 "general_operand" "fmF")))]
776: "TARGET_32081"
777: "addl %2,%0")
778:
779:
780: (define_insn "addsf3"
781: [(set (match_operand:SF 0 "general_operand" "=fm")
782: (plus:SF (match_operand:SF 1 "general_operand" "%0")
783: (match_operand:SF 2 "general_operand" "fmF")))]
784: "TARGET_32081"
785: "addf %2,%0")
786:
787: (define_insn ""
788: [(set (reg:SI 17)
789: (plus:SI (reg:SI 17)
790: (match_operand:SI 0 "immediate_operand" "i")))]
791: "GET_CODE (operands[0]) == CONST_INT"
792: "*
793: {
794: #ifndef SEQUENT_ADJUST_STACK
795: if (TARGET_32532)
796: if (INTVAL (operands[0]) == 8)
797: return \"cmpd tos,tos\";
798: if (TARGET_32532 || TARGET_32332)
799: if (INTVAL (operands[0]) == 4)
800: return \"cmpqd %$0,tos\";
801: #endif
802: if (! TARGET_32532)
803: {
804: if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64)
805: return \"adjspb %$%n0\";
806: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
807: return \"adjspw %$%n0\";
808: }
809: return \"adjspd %$%n0\";
810: }")
811:
812: (define_insn ""
813: [(set (match_operand:SI 0 "general_operand" "=g<")
814: (plus:SI (reg:SI 16)
815: (match_operand:SI 1 "immediate_operand" "i")))]
816: "GET_CODE (operands[1]) == CONST_INT"
817: "addr %c1(fp),%0")
818:
819: (define_insn ""
820: [(set (match_operand:SI 0 "general_operand" "=g<")
821: (plus:SI (reg:SI 17)
822: (match_operand:SI 1 "immediate_operand" "i")))]
823: "GET_CODE (operands[1]) == CONST_INT"
824: "addr %c1(sp),%0")
825:
826: (define_insn "addsi3"
827: [(set (match_operand:SI 0 "general_operand" "=g,=g<")
828: (plus:SI (match_operand:SI 1 "general_operand" "%0,%r")
829: (match_operand:SI 2 "general_operand" "rmn,n")))]
830: ""
831: "*
832: {
833: if (which_alternative == 1)
834: {
835: int i = INTVAL (operands[2]);
1.1.1.3 ! root 836: if (NS32K_DISPLACEMENT_P (i))
! 837: return \"addr %c2(%1),%0\";
1.1 root 838: else
1.1.1.3 ! root 839: return \"movd %1,%0\;addd %2,%0\";
1.1 root 840: }
841: if (GET_CODE (operands[2]) == CONST_INT)
842: {
843: int i = INTVAL (operands[2]);
844:
845: if (i <= 7 && i >= -8)
846: return \"addqd %2,%0\";
847: else if (GET_CODE (operands[0]) == REG
848: && i < 0x4000 && i >= -0x4000 && ! TARGET_32532)
849: return \"addr %c2(%0),%0\";
850: }
851: return \"addd %2,%0\";
852: }")
853:
854: (define_insn "addhi3"
855: [(set (match_operand:HI 0 "general_operand" "=g")
856: (plus:HI (match_operand:HI 1 "general_operand" "%0")
857: (match_operand:HI 2 "general_operand" "g")))]
858: ""
859: "*
860: { if (GET_CODE (operands[2]) == CONST_INT)
861: {
862: int i = INTVAL (operands[2]);
863: if (i <= 7 && i >= -8)
864: return \"addqw %2,%0\";
865: }
866: return \"addw %2,%0\";
867: }")
868:
869: (define_insn ""
870: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
871: (plus:HI (match_operand:HI 1 "general_operand" "0")
872: (match_operand:HI 2 "general_operand" "g")))]
873: ""
874: "*
875: {
876: if (GET_CODE (operands[1]) == CONST_INT
877: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
878: return \"addqw %1,%0\";
879: return \"addw %1,%0\";
880: }")
881:
882: (define_insn "addqi3"
883: [(set (match_operand:QI 0 "general_operand" "=g")
884: (plus:QI (match_operand:QI 1 "general_operand" "%0")
885: (match_operand:QI 2 "general_operand" "g")))]
886: ""
887: "*
888: { if (GET_CODE (operands[2]) == CONST_INT)
889: {
890: int i = INTVAL (operands[2]);
891: if (i <= 7 && i >= -8)
892: return \"addqb %2,%0\";
893: }
894: return \"addb %2,%0\";
895: }")
896:
897: (define_insn ""
898: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
899: (plus:QI (match_operand:QI 1 "general_operand" "0")
900: (match_operand:QI 2 "general_operand" "g")))]
901: ""
902: "*
903: {
904: if (GET_CODE (operands[1]) == CONST_INT
905: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
906: return \"addqb %1,%0\";
907: return \"addb %1,%0\";
908: }")
909:
910: ;;- All kinds of subtract instructions.
911:
912: (define_insn "subdf3"
913: [(set (match_operand:DF 0 "general_operand" "=fm")
914: (minus:DF (match_operand:DF 1 "general_operand" "0")
915: (match_operand:DF 2 "general_operand" "fmF")))]
916: "TARGET_32081"
917: "subl %2,%0")
918:
919: (define_insn "subsf3"
920: [(set (match_operand:SF 0 "general_operand" "=fm")
921: (minus:SF (match_operand:SF 1 "general_operand" "0")
922: (match_operand:SF 2 "general_operand" "fmF")))]
923: "TARGET_32081"
924: "subf %2,%0")
925:
926: (define_insn ""
927: [(set (reg:SI 17)
928: (minus:SI (reg:SI 17)
929: (match_operand:SI 0 "immediate_operand" "i")))]
930: "GET_CODE (operands[0]) == CONST_INT"
931: "*
932: {
933: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64
934: && INTVAL(operands[0]) > -64 && ! TARGET_32532)
935: return \"adjspb %0\";
936: return \"adjspd %0\";
937: }")
938:
939: (define_insn "subsi3"
940: [(set (match_operand:SI 0 "general_operand" "=g")
941: (minus:SI (match_operand:SI 1 "general_operand" "0")
942: (match_operand:SI 2 "general_operand" "rmn")))]
943: ""
944: "*
945: { if (GET_CODE (operands[2]) == CONST_INT)
946: {
947: int i = INTVAL (operands[2]);
948:
949: if (i <= 8 && i >= -7)
950: return \"addqd %$%n2,%0\";
951: }
952: return \"subd %2,%0\";
953: }")
954:
955: (define_insn "subhi3"
956: [(set (match_operand:HI 0 "general_operand" "=g")
957: (minus:HI (match_operand:HI 1 "general_operand" "0")
958: (match_operand:HI 2 "general_operand" "g")))]
959: ""
960: "*
961: { if (GET_CODE (operands[2]) == CONST_INT)
962: {
963: int i = INTVAL (operands[2]);
964:
965: if (i <= 8 && i >= -7)
966: return \"addqw %$%n2,%0\";
967: }
968: return \"subw %2,%0\";
969: }")
970:
971: (define_insn ""
972: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
973: (minus:HI (match_operand:HI 1 "general_operand" "0")
974: (match_operand:HI 2 "general_operand" "g")))]
975: ""
976: "*
977: {
978: if (GET_CODE (operands[1]) == CONST_INT
979: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
980: return \"addqw %$%n1,%0\";
981: return \"subw %1,%0\";
982: }")
983:
984: (define_insn "subqi3"
985: [(set (match_operand:QI 0 "general_operand" "=g")
986: (minus:QI (match_operand:QI 1 "general_operand" "0")
987: (match_operand:QI 2 "general_operand" "g")))]
988: ""
989: "*
990: { if (GET_CODE (operands[2]) == CONST_INT)
991: {
992: int i = INTVAL (operands[2]);
993:
994: if (i <= 8 && i >= -7)
995: return \"addqb %$%n2,%0\";
996: }
997: return \"subb %2,%0\";
998: }")
999:
1000: (define_insn ""
1001: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
1002: (minus:QI (match_operand:QI 1 "general_operand" "0")
1003: (match_operand:QI 2 "general_operand" "g")))]
1004: ""
1005: "*
1006: {
1007: if (GET_CODE (operands[1]) == CONST_INT
1008: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1009: return \"addqb %$%n1,%0\";
1010: return \"subb %1,%0\";
1011: }")
1012:
1013: ;;- Multiply instructions.
1014:
1015: (define_insn "muldf3"
1016: [(set (match_operand:DF 0 "general_operand" "=fm")
1017: (mult:DF (match_operand:DF 1 "general_operand" "%0")
1018: (match_operand:DF 2 "general_operand" "fmF")))]
1019: "TARGET_32081"
1020: "mull %2,%0")
1021:
1022: (define_insn "mulsf3"
1023: [(set (match_operand:SF 0 "general_operand" "=fm")
1024: (mult:SF (match_operand:SF 1 "general_operand" "%0")
1025: (match_operand:SF 2 "general_operand" "fmF")))]
1026: "TARGET_32081"
1027: "mulf %2,%0")
1028:
1029: (define_insn "mulsi3"
1030: [(set (match_operand:SI 0 "general_operand" "=g")
1031: (mult:SI (match_operand:SI 1 "general_operand" "%0")
1032: (match_operand:SI 2 "general_operand" "rmn")))]
1033: ""
1034: "muld %2,%0")
1035:
1036: (define_insn "mulhi3"
1037: [(set (match_operand:HI 0 "general_operand" "=g")
1038: (mult:HI (match_operand:HI 1 "general_operand" "%0")
1039: (match_operand:HI 2 "general_operand" "g")))]
1040: ""
1041: "mulw %2,%0")
1042:
1043: (define_insn "mulqi3"
1044: [(set (match_operand:QI 0 "general_operand" "=g")
1045: (mult:QI (match_operand:QI 1 "general_operand" "%0")
1046: (match_operand:QI 2 "general_operand" "g")))]
1047: ""
1048: "mulb %2,%0")
1049:
1050: (define_insn "umulsidi3"
1051: [(set (match_operand:DI 0 "general_operand" "=g")
1052: (mult:DI (zero_extend:DI
1053: (match_operand:SI 1 "nonimmediate_operand" "0"))
1054: (zero_extend:DI
1055: (match_operand:SI 2 "nonimmediate_operand" "rmn"))))]
1056: ""
1057: "meid %2,%0")
1058:
1059: ;;- Divide instructions.
1060:
1061: (define_insn "divdf3"
1062: [(set (match_operand:DF 0 "general_operand" "=fm")
1063: (div:DF (match_operand:DF 1 "general_operand" "0")
1064: (match_operand:DF 2 "general_operand" "fmF")))]
1065: "TARGET_32081"
1066: "divl %2,%0")
1067:
1068: (define_insn "divsf3"
1069: [(set (match_operand:SF 0 "general_operand" "=fm")
1070: (div:SF (match_operand:SF 1 "general_operand" "0")
1071: (match_operand:SF 2 "general_operand" "fmF")))]
1072: "TARGET_32081"
1073: "divf %2,%0")
1074:
1075: (define_insn "divsi3"
1076: [(set (match_operand:SI 0 "general_operand" "=g")
1077: (div:SI (match_operand:SI 1 "general_operand" "0")
1078: (match_operand:SI 2 "general_operand" "rmn")))]
1079: ""
1080: "quod %2,%0")
1081:
1082: (define_insn "divhi3"
1083: [(set (match_operand:HI 0 "general_operand" "=g")
1084: (div:HI (match_operand:HI 1 "general_operand" "0")
1085: (match_operand:HI 2 "general_operand" "g")))]
1086: ""
1087: "quow %2,%0")
1088:
1089: (define_insn "divqi3"
1090: [(set (match_operand:QI 0 "general_operand" "=g")
1091: (div:QI (match_operand:QI 1 "general_operand" "0")
1092: (match_operand:QI 2 "general_operand" "g")))]
1093: ""
1094: "quob %2,%0")
1095:
1096: (define_insn "udivsi3"
1097: [(set (match_operand:SI 0 "register_operand" "=r")
1098: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1099: (match_operand:SI 2 "general_operand" "rmn")))]
1100: ""
1101: "*
1102: {
1103: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1104: return \"deid %2,%0\;movd %1,%0\";
1105: }")
1106:
1107: (define_insn "udivhi3"
1108: [(set (match_operand:HI 0 "register_operand" "=r")
1109: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1110: (match_operand:HI 2 "general_operand" "g")))]
1111: ""
1112: "*
1113: {
1114: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
1115: return \"deiw %2,%0\;movw %1,%0\";
1116: }")
1117:
1118: (define_insn "udivqi3"
1119: [(set (match_operand:QI 0 "register_operand" "=r")
1120: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1121: (match_operand:QI 2 "general_operand" "g")))]
1122: ""
1123: "*
1124: {
1125: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
1126: return \"deib %2,%0\;movb %1,%0\";
1127: }")
1128:
1129: ;; Remainder instructions.
1130:
1131: (define_insn "modsi3"
1132: [(set (match_operand:SI 0 "general_operand" "=g")
1133: (mod:SI (match_operand:SI 1 "general_operand" "0")
1134: (match_operand:SI 2 "general_operand" "rmn")))]
1135: ""
1136: "remd %2,%0")
1137:
1138: (define_insn "modhi3"
1139: [(set (match_operand:HI 0 "general_operand" "=g")
1140: (mod:HI (match_operand:HI 1 "general_operand" "0")
1141: (match_operand:HI 2 "general_operand" "g")))]
1142: ""
1143: "remw %2,%0")
1144:
1145: (define_insn "modqi3"
1146: [(set (match_operand:QI 0 "general_operand" "=g")
1147: (mod:QI (match_operand:QI 1 "general_operand" "0")
1148: (match_operand:QI 2 "general_operand" "g")))]
1149: ""
1150: "remb %2,%0")
1151:
1152: (define_insn "umodsi3"
1153: [(set (match_operand:SI 0 "register_operand" "=r")
1154: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1155: (match_operand:SI 2 "general_operand" "rmn")))]
1156: ""
1157: "deid %2,%0")
1158:
1159: (define_insn "umodhi3"
1160: [(set (match_operand:HI 0 "register_operand" "=r")
1161: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1162: (match_operand:HI 2 "general_operand" "g")))]
1163: ""
1164: "deiw %2,%0")
1165:
1166: (define_insn "umodqi3"
1167: [(set (match_operand:QI 0 "register_operand" "=r")
1168: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1169: (match_operand:QI 2 "general_operand" "g")))]
1170: ""
1171: "deib %2,%0")
1172:
1173: ; This isn't be usable in its current form.
1174: ;(define_insn "udivmoddisi4"
1175: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1176: ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1177: ; (match_operand:SI 2 "general_operand" "rmn")))
1178: ; (set (subreg:SI (match_dup 0) 0)
1179: ; (umod:SI (match_dup 1) (match_dup 2)))]
1180: ; ""
1181: ; "deid %2,%0")
1182:
1183: ;;- Logical Instructions: AND
1184:
1185: (define_insn "andsi3"
1186: [(set (match_operand:SI 0 "general_operand" "=g")
1187: (and:SI (match_operand:SI 1 "general_operand" "%0")
1188: (match_operand:SI 2 "general_operand" "rmn")))]
1189: ""
1190: "*
1191: {
1192: if (GET_CODE (operands[2]) == CONST_INT)
1193: {
1194: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1195: {
1196: if (INTVAL (operands[2]) == 0xffffff00)
1197: return \"movqb %$0,%0\";
1198: else
1199: {
1200: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1201: INTVAL (operands[2]) & 0xff);
1202: return \"andb %2,%0\";
1203: }
1204: }
1205: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1206: {
1207: if (INTVAL (operands[2]) == 0xffff0000)
1208: return \"movqw %$0,%0\";
1209: else
1210: {
1211: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1212: INTVAL (operands[2]) & 0xffff);
1213: return \"andw %2,%0\";
1214: }
1215: }
1216: }
1217: return \"andd %2,%0\";
1218: }")
1219:
1220: (define_insn "andhi3"
1221: [(set (match_operand:HI 0 "general_operand" "=g")
1222: (and:HI (match_operand:HI 1 "general_operand" "%0")
1223: (match_operand:HI 2 "general_operand" "g")))]
1224: ""
1225: "*
1226: {
1227: if (GET_CODE (operands[2]) == CONST_INT
1228: && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1229: {
1230: if (INTVAL (operands[2]) == 0xffffff00)
1231: return \"movqb %$0,%0\";
1232: else
1233: {
1234: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1235: INTVAL (operands[2]) & 0xff);
1236: return \"andb %2,%0\";
1237: }
1238: }
1239: return \"andw %2,%0\";
1240: }")
1241:
1242: (define_insn "andqi3"
1243: [(set (match_operand:QI 0 "general_operand" "=g")
1244: (and:QI (match_operand:QI 1 "general_operand" "%0")
1245: (match_operand:QI 2 "general_operand" "g")))]
1246: ""
1247: "andb %2,%0")
1248:
1249: (define_insn ""
1250: [(set (match_operand:SI 0 "general_operand" "=g")
1251: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1252: (match_operand:SI 2 "general_operand" "0")))]
1253: ""
1254: "bicd %1,%0")
1255:
1256: (define_insn ""
1257: [(set (match_operand:HI 0 "general_operand" "=g")
1258: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1259: (match_operand:HI 2 "general_operand" "0")))]
1260: ""
1261: "bicw %1,%0")
1262:
1263: (define_insn ""
1264: [(set (match_operand:QI 0 "general_operand" "=g")
1265: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1266: (match_operand:QI 2 "general_operand" "0")))]
1267: ""
1268: "bicb %1,%0")
1269:
1270: ;;- Bit set instructions.
1271:
1272: (define_insn "iorsi3"
1273: [(set (match_operand:SI 0 "general_operand" "=g")
1274: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1275: (match_operand:SI 2 "general_operand" "rmn")))]
1276: ""
1277: "*
1278: {
1279: if (GET_CODE (operands[2]) == CONST_INT) {
1280: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1281: return \"orb %2,%0\";
1282: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1283: return \"orw %2,%0\";
1284: }
1285: return \"ord %2,%0\";
1286: }")
1287:
1288: (define_insn "iorhi3"
1289: [(set (match_operand:HI 0 "general_operand" "=g")
1290: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1291: (match_operand:HI 2 "general_operand" "g")))]
1292: ""
1293: "*
1294: {
1295: if (GET_CODE(operands[2]) == CONST_INT &&
1296: (INTVAL(operands[2]) & 0xffffff00) == 0)
1297: return \"orb %2,%0\";
1298: return \"orw %2,%0\";
1299: }")
1300:
1301: (define_insn "iorqi3"
1302: [(set (match_operand:QI 0 "general_operand" "=g")
1303: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1304: (match_operand:QI 2 "general_operand" "g")))]
1305: ""
1306: "orb %2,%0")
1307:
1308: ;;- xor instructions.
1309:
1310: (define_insn "xorsi3"
1311: [(set (match_operand:SI 0 "general_operand" "=g")
1312: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1313: (match_operand:SI 2 "general_operand" "rmn")))]
1314: ""
1315: "*
1316: {
1317: if (GET_CODE (operands[2]) == CONST_INT) {
1318: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1319: return \"xorb %2,%0\";
1320: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1321: return \"xorw %2,%0\";
1322: }
1323: return \"xord %2,%0\";
1324: }")
1325:
1326: (define_insn "xorhi3"
1327: [(set (match_operand:HI 0 "general_operand" "=g")
1328: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1329: (match_operand:HI 2 "general_operand" "g")))]
1330: ""
1331: "*
1332: {
1333: if (GET_CODE(operands[2]) == CONST_INT &&
1334: (INTVAL(operands[2]) & 0xffffff00) == 0)
1335: return \"xorb %2,%0\";
1336: return \"xorw %2,%0\";
1337: }")
1338:
1339: (define_insn "xorqi3"
1340: [(set (match_operand:QI 0 "general_operand" "=g")
1341: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1342: (match_operand:QI 2 "general_operand" "g")))]
1343: ""
1344: "xorb %2,%0")
1345:
1346: (define_insn "negdf2"
1347: [(set (match_operand:DF 0 "general_operand" "=fm<")
1348: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1349: "TARGET_32081"
1350: "negl %1,%0")
1351:
1352: (define_insn "negsf2"
1353: [(set (match_operand:SF 0 "general_operand" "=fm<")
1354: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1355: "TARGET_32081"
1356: "negf %1,%0")
1357:
1358: (define_insn "negsi2"
1359: [(set (match_operand:SI 0 "general_operand" "=g<")
1360: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1361: ""
1362: "negd %1,%0")
1363:
1364: (define_insn "neghi2"
1365: [(set (match_operand:HI 0 "general_operand" "=g<")
1366: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1367: ""
1368: "negw %1,%0")
1369:
1370: (define_insn "negqi2"
1371: [(set (match_operand:QI 0 "general_operand" "=g<")
1372: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1373: ""
1374: "negb %1,%0")
1375:
1376: (define_insn "one_cmplsi2"
1377: [(set (match_operand:SI 0 "general_operand" "=g<")
1378: (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1379: ""
1380: "comd %1,%0")
1381:
1382: (define_insn "one_cmplhi2"
1383: [(set (match_operand:HI 0 "general_operand" "=g<")
1384: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1385: ""
1386: "comw %1,%0")
1387:
1388: (define_insn "one_cmplqi2"
1389: [(set (match_operand:QI 0 "general_operand" "=g<")
1390: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1391: ""
1392: "comb %1,%0")
1393:
1394: ;; arithmetic left and right shift operations
1395: ;; on the 32532 we will always use lshd for arithmetic left shifts,
1396: ;; because it is three times faster. Broken programs which
1397: ;; use negative shift counts are probably broken differently
1398: ;; than elsewhere.
1399:
1400: ;; alternative 0 never matches on the 32532
1401: (define_insn "ashlsi3"
1402: [(set (match_operand:SI 0 "general_operand" "=g,g")
1403: (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1404: (match_operand:SI 2 "general_operand" "I,rmn")))]
1405: ""
1406: "*
1407: { if (TARGET_32532)
1408: return \"lshd %2,%0\";
1409: else
1410: return output_shift_insn (operands);
1411: }")
1412:
1413: (define_insn "ashlhi3"
1414: [(set (match_operand:HI 0 "general_operand" "=g")
1415: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1416: (match_operand:SI 2 "general_operand" "rmn")))]
1417: ""
1418: "*
1419: { if (GET_CODE (operands[2]) == CONST_INT)
1420: {
1421: if (INTVAL (operands[2]) == 1)
1422: return \"addw %0,%0\";
1423: else if (INTVAL (operands[2]) == 2 && !TARGET_32532)
1424: return \"addw %0,%0\;addw %0,%0\";
1425: }
1426: if (TARGET_32532)
1427: return \"lshw %2,%0\";
1428: else
1429: return \"ashw %2,%0\";
1430: }")
1431:
1432: (define_insn "ashlqi3"
1433: [(set (match_operand:QI 0 "general_operand" "=g")
1434: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1435: (match_operand:SI 2 "general_operand" "rmn")))]
1436: ""
1437: "*
1438: { if (GET_CODE (operands[2]) == CONST_INT)
1439: {
1440: if (INTVAL (operands[2]) == 1)
1441: return \"addb %0,%0\";
1442: else if (INTVAL (operands[2]) == 2 && !TARGET_32532)
1443: return \"addb %0,%0\;addb %0,%0\";
1444: }
1445: if (TARGET_32532)
1446: return \"lshb %2,%0\";
1447: else
1448: return \"ashb %2,%0\";
1449: }")
1450:
1451: ;; Arithmetic right shift on the 32k works by negating the shift count.
1452: (define_expand "ashrsi3"
1453: [(set (match_operand:SI 0 "general_operand" "=g")
1454: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1455: (match_operand:SI 2 "general_operand" "g")))]
1456: ""
1457: "
1458: {
1459: if (GET_CODE (operands[2]) != CONST_INT)
1460: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1461: }")
1462:
1463: (define_insn ""
1464: [(set (match_operand:SI 0 "general_operand" "=g")
1465: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1466: (match_operand:SI 2 "immediate_operand" "i")))]
1467: ""
1468: "ashd %$%n2,%0")
1469:
1470: (define_insn ""
1471: [(set (match_operand:SI 0 "general_operand" "=g")
1472: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1473: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1474: ""
1475: "ashd %2,%0")
1476:
1477: (define_expand "ashrhi3"
1478: [(set (match_operand:HI 0 "general_operand" "=g")
1479: (ashiftrt:HI (match_operand:HI 1 "general_operand" "g")
1480: (match_operand:SI 2 "general_operand" "g")))]
1481: ""
1482: "
1483: {
1484: if (GET_CODE (operands[2]) != CONST_INT)
1485: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1486: }")
1487:
1488: (define_insn ""
1489: [(set (match_operand:HI 0 "general_operand" "=g")
1490: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1491: (match_operand:SI 2 "immediate_operand" "i")))]
1492: ""
1493: "ashw %$%n2,%0")
1494:
1495: (define_insn ""
1496: [(set (match_operand:HI 0 "general_operand" "=g")
1497: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1498: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1499: ""
1500: "ashw %2,%0")
1501:
1502: (define_expand "ashrqi3"
1503: [(set (match_operand:QI 0 "general_operand" "=g")
1504: (ashiftrt:QI (match_operand:QI 1 "general_operand" "g")
1505: (match_operand:SI 2 "general_operand" "g")))]
1506: ""
1507: "
1508: {
1509: if (GET_CODE (operands[2]) != CONST_INT)
1510: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1511: }")
1512:
1513: (define_insn ""
1514: [(set (match_operand:QI 0 "general_operand" "=g")
1515: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1516: (match_operand:SI 2 "immediate_operand" "i")))]
1517: ""
1518: "ashb %$%n2,%0")
1519:
1520: (define_insn ""
1521: [(set (match_operand:QI 0 "general_operand" "=g")
1522: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1523: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1524: ""
1525: "ashb %2,%0")
1526:
1527: ;; logical shift instructions
1528:
1529: (define_insn "lshlsi3"
1530: [(set (match_operand:SI 0 "general_operand" "=g")
1531: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1532: (match_operand:SI 2 "general_operand" "rmn")))]
1533: ""
1534: "lshd %2,%0")
1535:
1536: (define_insn "lshlhi3"
1537: [(set (match_operand:HI 0 "general_operand" "=g")
1538: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1539: (match_operand:SI 2 "general_operand" "rmn")))]
1540: ""
1541: "lshw %2,%0")
1542:
1543: (define_insn "lshlqi3"
1544: [(set (match_operand:QI 0 "general_operand" "=g")
1545: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1546: (match_operand:SI 2 "general_operand" "rmn")))]
1547: ""
1548: "lshb %2,%0")
1549:
1550: ;; Logical right shift on the 32k works by negating the shift count.
1551: (define_expand "lshrsi3"
1552: [(set (match_operand:SI 0 "general_operand" "=g")
1553: (lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
1554: (match_operand:SI 2 "general_operand" "g")))]
1555: ""
1556: "
1557: {
1558: if (GET_CODE (operands[2]) != CONST_INT)
1559: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1560: }")
1561:
1562: (define_insn ""
1563: [(set (match_operand:SI 0 "general_operand" "=g")
1564: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1565: (match_operand:SI 2 "immediate_operand" "i")))]
1566: ""
1567: "lshd %$%n2,%0")
1568:
1569: (define_insn ""
1570: [(set (match_operand:SI 0 "general_operand" "=g")
1571: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1572: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1573: ""
1574: "lshd %2,%0")
1575:
1576: (define_expand "lshrhi3"
1577: [(set (match_operand:HI 0 "general_operand" "=g")
1578: (lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
1579: (match_operand:SI 2 "general_operand" "g")))]
1580: ""
1581: "
1582: {
1583: if (GET_CODE (operands[2]) != CONST_INT)
1584: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1585: }")
1586:
1587: (define_insn ""
1588: [(set (match_operand:HI 0 "general_operand" "=g")
1589: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1590: (match_operand:SI 2 "immediate_operand" "i")))]
1591: ""
1592: "lshw %$%n2,%0")
1593:
1594: (define_insn ""
1595: [(set (match_operand:HI 0 "general_operand" "=g")
1596: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1597: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1598: ""
1599: "lshw %2,%0")
1600:
1601: (define_expand "lshrqi3"
1602: [(set (match_operand:QI 0 "general_operand" "=g")
1603: (lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
1604: (match_operand:SI 2 "general_operand" "g")))]
1605: ""
1606: "
1607: {
1608: if (GET_CODE (operands[2]) != CONST_INT)
1609: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1610: }")
1611:
1612: (define_insn ""
1613: [(set (match_operand:QI 0 "general_operand" "=g")
1614: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1615: (match_operand:SI 2 "immediate_operand" "i")))]
1616: ""
1617: "lshb %$%n2,%0")
1618:
1619: (define_insn ""
1620: [(set (match_operand:QI 0 "general_operand" "=g")
1621: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1622: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1623: ""
1624: "lshb %2,%0")
1625:
1626: ;; Rotate instructions
1627:
1628: (define_insn "rotlsi3"
1629: [(set (match_operand:SI 0 "general_operand" "=g")
1630: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1631: (match_operand:SI 2 "general_operand" "rmn")))]
1632: ""
1633: "rotd %2,%0")
1634:
1635: (define_insn "rotlhi3"
1636: [(set (match_operand:HI 0 "general_operand" "=g")
1637: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1638: (match_operand:SI 2 "general_operand" "rmn")))]
1639: ""
1640: "rotw %2,%0")
1641:
1642: (define_insn "rotlqi3"
1643: [(set (match_operand:QI 0 "general_operand" "=g")
1644: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1645: (match_operand:SI 2 "general_operand" "rmn")))]
1646: ""
1647: "rotb %2,%0")
1648:
1649: ;; Right rotate on the 32k works by negating the shift count.
1650: (define_expand "rotrsi3"
1651: [(set (match_operand:SI 0 "general_operand" "=g")
1652: (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1653: (match_operand:SI 2 "general_operand" "g")))]
1654: ""
1655: "
1656: {
1657: if (GET_CODE (operands[2]) != CONST_INT)
1658: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1659: }")
1660:
1661: (define_insn ""
1662: [(set (match_operand:SI 0 "general_operand" "=g")
1663: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1664: (match_operand:SI 2 "immediate_operand" "i")))]
1665: ""
1666: "rotd %$%n2,%0")
1667:
1668: (define_insn ""
1669: [(set (match_operand:SI 0 "general_operand" "=g")
1670: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1671: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1672: ""
1673: "rotd %2,%0")
1674:
1675: (define_expand "rotrhi3"
1676: [(set (match_operand:HI 0 "general_operand" "=g")
1677: (rotatert:HI (match_operand:HI 1 "general_operand" "g")
1678: (match_operand:SI 2 "general_operand" "g")))]
1679: ""
1680: "
1681: {
1682: if (GET_CODE (operands[2]) != CONST_INT)
1683: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1684: }")
1685:
1686: (define_insn ""
1687: [(set (match_operand:HI 0 "general_operand" "=g")
1688: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1689: (match_operand:SI 2 "immediate_operand" "i")))]
1690: ""
1691: "rotw %$%n2,%0")
1692:
1693: (define_insn ""
1694: [(set (match_operand:HI 0 "general_operand" "=g")
1695: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1696: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1697: ""
1698: "rotw %2,%0")
1699:
1700: (define_expand "rotrqi3"
1701: [(set (match_operand:QI 0 "general_operand" "=g")
1702: (rotatert:QI (match_operand:QI 1 "general_operand" "g")
1703: (match_operand:SI 2 "general_operand" "g")))]
1704: ""
1705: "
1706: {
1707: if (GET_CODE (operands[2]) != CONST_INT)
1708: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1709: }")
1710:
1711: (define_insn ""
1712: [(set (match_operand:QI 0 "general_operand" "=g")
1713: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1714: (match_operand:SI 2 "immediate_operand" "i")))]
1715: ""
1716: "rotb %$%n2,%0")
1717:
1718: (define_insn ""
1719: [(set (match_operand:QI 0 "general_operand" "=g")
1720: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1721: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1722: ""
1723: "rotb %2,%0")
1724:
1725: ;;- load or push effective address
1726: ;; These come after the move, add, and multiply patterns
1727: ;; because we don't want pushl $1 turned into pushad 1.
1728:
1729: (define_insn ""
1730: [(set (match_operand:SI 0 "general_operand" "=g<")
1731: (match_operand:QI 1 "address_operand" "p"))]
1732: ""
1733: "*
1734: {
1735: if (REG_P (operands[0])
1736: && GET_CODE (operands[1]) == MULT
1737: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1738: && (INTVAL (XEXP (operands[1], 1)) == 2
1739: || INTVAL (XEXP (operands[1], 1)) == 4))
1740: {
1741: rtx xoperands[3];
1742: xoperands[0] = operands[0];
1743: xoperands[1] = XEXP (operands[1], 0);
1744: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
1745: return output_shift_insn (xoperands);
1746: }
1747: return \"addr %a1,%0\";
1748: }")
1749:
1750: ;;; Index insns. These are about the same speed as multiply-add counterparts.
1751: ;;; but slower then using power-of-2 shifts if we can use them
1752: ;
1753: ;(define_insn ""
1754: ; [(set (match_operand:SI 0 "register_operand" "=r")
1755: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1756: ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1757: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1758: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1759: ; "indexd %0,%3,%1")
1760: ;
1761: ;(define_insn ""
1762: ; [(set (match_operand:SI 0 "register_operand" "=r")
1763: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1764: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1765: ; (match_operand:SI 3 "general_operand" "rmn")))]
1766: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1767: ; "indexd %0,%2,%3")
1768:
1769: ;; Set, Clear, and Invert bit
1770:
1771: (define_insn ""
1772: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
1773: (const_int 1)
1774: (match_operand:SI 1 "general_operand" "rmn"))
1775: (const_int 1))]
1776: ""
1777: "sbitd %1,%0")
1778:
1779: (define_insn ""
1780: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
1781: (const_int 1)
1782: (match_operand:SI 1 "general_operand" "rmn"))
1783: (const_int 0))]
1784: ""
1785: "cbitd %1,%0")
1786:
1787: (define_insn ""
1788: [(set (match_operand:SI 0 "general_operand" "+g")
1789: (xor:SI (ashift:SI (const_int 1)
1790: (match_operand:SI 1 "general_operand" "rmn"))
1791: (match_dup 0)))]
1792: ""
1793: "ibitd %1,%0")
1794:
1795: (define_insn ""
1796: [(set (match_operand:QI 0 "general_operand" "=g")
1797: (xor:QI (subreg:QI
1798: (ashift:SI (const_int 1)
1799: (match_operand:QI 1 "general_operand" "rmn")) 0)
1800: (match_dup 0)))]
1801: ""
1802: "ibitb %1,%0")
1803:
1804: ;; Recognize jbs and jbc instructions.
1805:
1806: (define_insn ""
1807: [(set (cc0)
1808: (zero_extract (match_operand:SI 0 "general_operand" "rm")
1809: (const_int 1)
1810: (match_operand:SI 1 "general_operand" "g")))]
1811: ""
1812: "*
1813: { cc_status.flags = CC_Z_IN_F;
1814: return \"tbitd %1,%0\";
1815: }")
1816:
1817: ;; extract(base, width, offset)
1818: ;; Signed bitfield extraction is not supported in hardware on the
1819: ;; NS 32032. It is therefore better to let GCC figure out a
1820: ;; good strategy for generating the proper instruction sequence
1821: ;; and represent it as rtl.
1822:
1823: ;; Optimize the case of extracting a byte or word from a register.
1824: ;; Otherwise we must load a register with the offset of the
1825: ;; chunk we want, and perform an extract insn (each of which
1826: ;; is very expensive). Since we use the stack to do our bit-twiddling
1827: ;; we cannot use it for a destination. Perhaps things are fast
1828: ;; enough on the 32532 that such hacks are not needed.
1829:
1830: (define_insn ""
1831: [(set (match_operand:SI 0 "general_operand" "=ro")
1832: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1833: (match_operand:SI 2 "const_int_operand" "i")
1834: (match_operand:SI 3 "const_int_operand" "i")))]
1835: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1836: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
1837: "*
1838: {
1839: output_asm_insn (\"movd %1,tos\", operands);
1840: if (INTVAL (operands[2]) == 16)
1841: {
1842: if (INTVAL (operands[3]) == 8)
1843: output_asm_insn (\"movzwd 1(sp),%0\", operands);
1844: else
1845: output_asm_insn (\"movzwd 2(sp),%0\", operands);
1846: }
1847: else
1848: {
1849: if (INTVAL (operands[3]) == 8)
1850: output_asm_insn (\"movzbd 1(sp),%0\", operands);
1851: else if (INTVAL (operands[3]) == 16)
1852: output_asm_insn (\"movzbd 2(sp),%0\", operands);
1853: else
1854: output_asm_insn (\"movzbd 3(sp),%0\", operands);
1855: }
1856: if (TARGET_32532 || TARGET_32332)
1857: return \"cmpqd %$0,tos\";
1858: else
1859: return \"adjspb %$-4\";
1860: }")
1861:
1.1.1.3 ! root 1862: (define_insn ""
! 1863: [(set (match_operand:SI 0 "general_operand" "=g<")
! 1864: (zero_extract:SI (match_operand:SI 1 "register_operand" "g")
! 1865: (match_operand:SI 2 "const_int_operand" "i")
! 1866: (match_operand:SI 3 "general_operand" "rK")))]
! 1867: ""
! 1868: "*
! 1869: { if (GET_CODE (operands[3]) == CONST_INT)
! 1870: return \"extsd %1,%0,%3,%2\";
! 1871: else return \"extd %3,%1,%0,%2\";
! 1872: }")
! 1873:
1.1 root 1874: (define_insn "extzv"
1875: [(set (match_operand:SI 0 "general_operand" "=g<")
1876: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1877: (match_operand:SI 2 "const_int_operand" "i")
1878: (match_operand:SI 3 "general_operand" "rK")))]
1879: ""
1880: "*
1881: { if (GET_CODE (operands[3]) == CONST_INT)
1882: return \"extsd %1,%0,%3,%2\";
1883: else return \"extd %3,%1,%0,%2\";
1884: }")
1885:
1886: (define_insn ""
1887: [(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o")
1888: (match_operand:SI 1 "const_int_operand" "i")
1889: (match_operand:SI 2 "general_operand" "rn"))
1890: (match_operand:SI 3 "general_operand" "rm"))]
1891: ""
1892: "*
1893: { if (GET_CODE (operands[2]) == CONST_INT)
1894: {
1895: if (INTVAL (operands[2]) >= 8)
1896: {
1897: operands[0] = adj_offsettable_operand (operands[0],
1898: INTVAL (operands[2]) / 8);
1899: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1900: }
1901: if (INTVAL (operands[1]) <= 8)
1902: return \"inssb %3,%0,%2,%1\";
1903: else if (INTVAL (operands[1]) <= 16)
1904: return \"inssw %3,%0,%2,%1\";
1905: else
1906: return \"inssd %3,%0,%2,%1\";
1907: }
1908: return \"insd %2,%3,%0,%1\";
1909: }")
1910:
1911: (define_insn ""
1912: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1913: (match_operand:SI 1 "const_int_operand" "i")
1914: (match_operand:SI 2 "general_operand" "rK"))
1915: (match_operand:SI 3 "general_operand" "rm"))]
1916: ""
1917: "*
1918: { if (GET_CODE (operands[2]) == CONST_INT)
1919: if (INTVAL (operands[1]) <= 8)
1920: return \"inssb %3,%0,%2,%1\";
1921: else if (INTVAL (operands[1]) <= 16)
1922: return \"inssw %3,%0,%2,%1\";
1923: else
1924: return \"inssd %3,%0,%2,%1\";
1925: return \"insd %2,%3,%0,%1\";
1926: }")
1927:
1928: (define_insn "insv"
1929: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1930: (match_operand:SI 1 "const_int_operand" "i")
1931: (match_operand:SI 2 "general_operand" "rK"))
1932: (match_operand:SI 3 "general_operand" "rm"))]
1933: ""
1934: "*
1935: { if (GET_CODE (operands[2]) == CONST_INT)
1936: if (INTVAL (operands[1]) <= 8)
1937: return \"inssb %3,%0,%2,%1\";
1938: else if (INTVAL (operands[1]) <= 16)
1939: return \"inssw %3,%0,%2,%1\";
1940: else
1941: return \"inssd %3,%0,%2,%1\";
1942: return \"insd %2,%3,%0,%1\";
1943: }")
1944:
1945:
1946: (define_insn "jump"
1947: [(set (pc)
1948: (label_ref (match_operand 0 "" "")))]
1949: ""
1950: "br %l0")
1951:
1952: (define_insn "beq"
1953: [(set (pc)
1954: (if_then_else (eq (cc0)
1955: (const_int 0))
1956: (label_ref (match_operand 0 "" ""))
1957: (pc)))]
1958: ""
1959: "*
1960: { if (cc_prev_status.flags & CC_Z_IN_F)
1961: return \"bfc %l0\";
1962: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1963: return \"bfs %l0\";
1964: else return \"beq %l0\";
1965: }")
1966:
1967: (define_insn "bne"
1968: [(set (pc)
1969: (if_then_else (ne (cc0)
1970: (const_int 0))
1971: (label_ref (match_operand 0 "" ""))
1972: (pc)))]
1973: ""
1974: "*
1975: { if (cc_prev_status.flags & CC_Z_IN_F)
1976: return \"bfs %l0\";
1977: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1978: return \"bfc %l0\";
1979: else return \"bne %l0\";
1980: }")
1981:
1982: (define_insn "bgt"
1983: [(set (pc)
1984: (if_then_else (gt (cc0)
1985: (const_int 0))
1986: (label_ref (match_operand 0 "" ""))
1987: (pc)))]
1988: ""
1989: "bgt %l0")
1990:
1991: (define_insn "bgtu"
1992: [(set (pc)
1993: (if_then_else (gtu (cc0)
1994: (const_int 0))
1995: (label_ref (match_operand 0 "" ""))
1996: (pc)))]
1997: ""
1998: "bhi %l0")
1999:
2000: (define_insn "blt"
2001: [(set (pc)
2002: (if_then_else (lt (cc0)
2003: (const_int 0))
2004: (label_ref (match_operand 0 "" ""))
2005: (pc)))]
2006: ""
2007: "blt %l0")
2008:
2009: (define_insn "bltu"
2010: [(set (pc)
2011: (if_then_else (ltu (cc0)
2012: (const_int 0))
2013: (label_ref (match_operand 0 "" ""))
2014: (pc)))]
2015: ""
2016: "blo %l0")
2017:
2018: (define_insn "bge"
2019: [(set (pc)
2020: (if_then_else (ge (cc0)
2021: (const_int 0))
2022: (label_ref (match_operand 0 "" ""))
2023: (pc)))]
2024: ""
2025: "bge %l0")
2026:
2027: (define_insn "bgeu"
2028: [(set (pc)
2029: (if_then_else (geu (cc0)
2030: (const_int 0))
2031: (label_ref (match_operand 0 "" ""))
2032: (pc)))]
2033: ""
2034: "bhs %l0")
2035:
2036: (define_insn "ble"
2037: [(set (pc)
2038: (if_then_else (le (cc0)
2039: (const_int 0))
2040: (label_ref (match_operand 0 "" ""))
2041: (pc)))]
2042: ""
2043: "ble %l0")
2044:
2045: (define_insn "bleu"
2046: [(set (pc)
2047: (if_then_else (leu (cc0)
2048: (const_int 0))
2049: (label_ref (match_operand 0 "" ""))
2050: (pc)))]
2051: ""
2052: "bls %l0")
2053:
2054: (define_insn ""
2055: [(set (pc)
2056: (if_then_else (eq (cc0)
2057: (const_int 0))
2058: (pc)
2059: (label_ref (match_operand 0 "" ""))))]
2060: ""
2061: "*
2062: { if (cc_prev_status.flags & CC_Z_IN_F)
2063: return \"bfs %l0\";
2064: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2065: return \"bfc %l0\";
2066: else return \"bne %l0\";
2067: }")
2068:
2069: (define_insn ""
2070: [(set (pc)
2071: (if_then_else (ne (cc0)
2072: (const_int 0))
2073: (pc)
2074: (label_ref (match_operand 0 "" ""))))]
2075: ""
2076: "*
2077: { if (cc_prev_status.flags & CC_Z_IN_F)
2078: return \"bfc %l0\";
2079: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2080: return \"bfs %l0\";
2081: else return \"beq %l0\";
2082: }")
2083:
2084: (define_insn ""
2085: [(set (pc)
2086: (if_then_else (gt (cc0)
2087: (const_int 0))
2088: (pc)
2089: (label_ref (match_operand 0 "" ""))))]
2090: ""
2091: "ble %l0")
2092:
2093: (define_insn ""
2094: [(set (pc)
2095: (if_then_else (gtu (cc0)
2096: (const_int 0))
2097: (pc)
2098: (label_ref (match_operand 0 "" ""))))]
2099: ""
2100: "bls %l0")
2101:
2102: (define_insn ""
2103: [(set (pc)
2104: (if_then_else (lt (cc0)
2105: (const_int 0))
2106: (pc)
2107: (label_ref (match_operand 0 "" ""))))]
2108: ""
2109: "bge %l0")
2110:
2111: (define_insn ""
2112: [(set (pc)
2113: (if_then_else (ltu (cc0)
2114: (const_int 0))
2115: (pc)
2116: (label_ref (match_operand 0 "" ""))))]
2117: ""
2118: "bhs %l0")
2119:
2120: (define_insn ""
2121: [(set (pc)
2122: (if_then_else (ge (cc0)
2123: (const_int 0))
2124: (pc)
2125: (label_ref (match_operand 0 "" ""))))]
2126: ""
2127: "blt %l0")
2128:
2129: (define_insn ""
2130: [(set (pc)
2131: (if_then_else (geu (cc0)
2132: (const_int 0))
2133: (pc)
2134: (label_ref (match_operand 0 "" ""))))]
2135: ""
2136: "blo %l0")
2137:
2138: (define_insn ""
2139: [(set (pc)
2140: (if_then_else (le (cc0)
2141: (const_int 0))
2142: (pc)
2143: (label_ref (match_operand 0 "" ""))))]
2144: ""
2145: "bgt %l0")
2146:
2147: (define_insn ""
2148: [(set (pc)
2149: (if_then_else (leu (cc0)
2150: (const_int 0))
2151: (pc)
2152: (label_ref (match_operand 0 "" ""))))]
2153: ""
2154: "bhi %l0")
2155:
2156: ;; Subtract-and-jump and Add-and-jump insns.
2157: ;; These can actually be used for adding numbers in the range -8 to 7
2158:
2159: (define_insn ""
2160: [(set (pc)
2161: (if_then_else
2162: (ne (match_operand:SI 0 "general_operand" "+g")
2163: (match_operand:SI 1 "const_int_operand" "i"))
2164: (label_ref (match_operand 2 "" ""))
2165: (pc)))
2166: (set (match_dup 0)
2167: (minus:SI (match_dup 0)
2168: (match_dup 1)))]
2169: "INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2170: "acbd %$%n1,%0,%l2")
2171:
2172: (define_insn ""
2173: [(set (pc)
2174: (if_then_else
2175: (ne (match_operand:SI 0 "general_operand" "+g")
2176: (match_operand:SI 1 "const_int_operand" "i"))
2177: (label_ref (match_operand 2 "" ""))
2178: (pc)))
2179: (set (match_dup 0)
2180: (plus:SI (match_dup 0)
2181: (match_operand:SI 3 "const_int_operand" "i")))]
2182: "INTVAL (operands[1]) == - INTVAL (operands[3])
2183: && INTVAL (operands[3]) >= -8 && INTVAL (operands[3]) < 8"
2184: "acbd %3,%0,%l2")
2185:
2186: (define_insn "call"
2187: [(call (match_operand:QI 0 "memory_operand" "m")
2188: (match_operand:QI 1 "general_operand" "g"))]
2189: ""
2190: "*
2191: {
2192: #ifndef JSR_ALWAYS
2193: if (GET_CODE (operands[0]) == MEM)
2194: {
2195: rtx temp = XEXP (operands[0], 0);
2196: if (CONSTANT_ADDRESS_P (temp))
2197: {
1.1.1.3 ! root 2198: #ifdef ENCORE_ASM
! 2199: return \"bsr %?%0\";
! 2200: #else
! 2201: #ifdef CALL_MEMREF_IMPLICIT
1.1 root 2202: operands[0] = temp;
2203: return \"bsr %0\";
1.1.1.2 root 2204: #else
1.1 root 2205: #ifdef GNX_V3
2206: return \"bsr %0\";
2207: #else
2208: return \"bsr %?%a0\";
2209: #endif
2210: #endif
1.1.1.3 ! root 2211: #endif
1.1 root 2212: }
2213: if (GET_CODE (XEXP (operands[0], 0)) == REG)
1.1.1.3 ! root 2214: #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
1.1 root 2215: return \"jsr %0\";
1.1.1.2 root 2216: #else
1.1 root 2217: return \"jsr %a0\";
2218: #endif
2219: }
2220: #endif /* not JSR_ALWAYS */
2221: return \"jsr %0\";
2222: }")
2223:
2224: (define_insn "call_value"
2225: [(set (match_operand 0 "" "=rf")
2226: (call (match_operand:QI 1 "memory_operand" "m")
2227: (match_operand:QI 2 "general_operand" "g")))]
2228: ""
2229: "*
2230: {
2231: #ifndef JSR_ALWAYS
2232: if (GET_CODE (operands[1]) == MEM)
2233: {
2234: rtx temp = XEXP (operands[1], 0);
2235: if (CONSTANT_ADDRESS_P (temp))
2236: {
1.1.1.3 ! root 2237: #ifdef ENCORE_ASM
! 2238: return \"bsr %?%1\";
! 2239: #else
! 2240: #ifdef CALL_MEMREF_IMPLICIT
1.1 root 2241: operands[1] = temp;
2242: return \"bsr %1\";
1.1.1.2 root 2243: #else
1.1 root 2244: #ifdef GNX_V3
2245: return \"bsr %1\";
2246: #else
2247: return \"bsr %?%a1\";
2248: #endif
2249: #endif
1.1.1.3 ! root 2250: #endif
1.1 root 2251: }
2252: if (GET_CODE (XEXP (operands[1], 0)) == REG)
1.1.1.3 ! root 2253: #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
1.1 root 2254: return \"jsr %1\";
1.1.1.2 root 2255: #else
1.1 root 2256: return \"jsr %a1\";
2257: #endif
2258: }
2259: #endif /* not JSR_ALWAYS */
2260: return \"jsr %1\";
2261: }")
2262:
2263: (define_insn "return"
2264: [(return)]
2265: "0"
2266: "ret 0")
2267:
2268: (define_insn "abssf2"
2269: [(set (match_operand:SF 0 "general_operand" "=fm<")
2270: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2271: "TARGET_32081"
2272: "absf %1,%0")
2273:
2274: (define_insn "absdf2"
2275: [(set (match_operand:DF 0 "general_operand" "=fm<")
2276: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2277: "TARGET_32081"
2278: "absl %1,%0")
2279:
2280: (define_insn "abssi2"
2281: [(set (match_operand:SI 0 "general_operand" "=g<")
2282: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2283: ""
2284: "absd %1,%0")
2285:
2286: (define_insn "abshi2"
2287: [(set (match_operand:HI 0 "general_operand" "=g<")
2288: (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2289: ""
2290: "absw %1,%0")
2291:
2292: (define_insn "absqi2"
2293: [(set (match_operand:QI 0 "general_operand" "=g<")
2294: (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2295: ""
2296: "absb %1,%0")
2297:
2298: (define_insn "nop"
2299: [(const_int 0)]
2300: ""
2301: "nop")
2302:
2303: (define_insn "indirect_jump"
2304: [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2305: ""
2306: "jump %0")
2307:
2308: ;;(define_insn "tablejump"
2309: ;; [(set (pc)
2310: ;; (plus:SI (match_operand:SI 0 "general_operand" "g")
2311: ;; (pc)))]
2312: ;; ""
2313: ;; "cased %0")
2314:
2315: (define_insn "tablejump"
2316: [(set (pc)
2317: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g")))
2318: (use (label_ref (match_operand 1 "" "")))]
2319: ""
2320: "*
2321: {
2322: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2323: CODE_LABEL_NUMBER (operands[1]));
2324: return \"casew %0\";
2325: }")
2326:
2327: ;;(define_insn ""
2328: ;; [(set (pc)
2329: ;; (plus:SI (match_operand:QI 0 "general_operand" "g")
2330: ;; (pc)))]
2331: ;; ""
2332: ;; "caseb %0")
2333:
2334: ;; Scondi instructions
2335: (define_insn "seq"
2336: [(set (match_operand:SI 0 "general_operand" "=g<")
2337: (eq:SI (cc0) (const_int 0)))]
2338: ""
2339: "*
2340: { if (cc_prev_status.flags & CC_Z_IN_F)
2341: return \"sfcd %0\";
2342: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2343: return \"sfsd %0\";
2344: else return \"seqd %0\";
2345: }")
2346:
2347: (define_insn ""
2348: [(set (match_operand:HI 0 "general_operand" "=g<")
2349: (eq:HI (cc0) (const_int 0)))]
2350: ""
2351: "*
2352: { if (cc_prev_status.flags & CC_Z_IN_F)
2353: return \"sfcw %0\";
2354: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2355: return \"sfsw %0\";
2356: else return \"seqw %0\";
2357: }")
2358:
2359: (define_insn ""
2360: [(set (match_operand:QI 0 "general_operand" "=g<")
2361: (eq:QI (cc0) (const_int 0)))]
2362: ""
2363: "*
2364: { if (cc_prev_status.flags & CC_Z_IN_F)
2365: return \"sfcb %0\";
2366: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2367: return \"sfsb %0\";
2368: else return \"seqb %0\";
2369: }")
2370:
2371: (define_insn "sne"
2372: [(set (match_operand:SI 0 "general_operand" "=g<")
2373: (ne:SI (cc0) (const_int 0)))]
2374: ""
2375: "*
2376: { if (cc_prev_status.flags & CC_Z_IN_F)
2377: return \"sfsd %0\";
2378: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2379: return \"sfcd %0\";
2380: else return \"sned %0\";
2381: }")
2382:
2383: (define_insn ""
2384: [(set (match_operand:HI 0 "general_operand" "=g<")
2385: (ne:HI (cc0) (const_int 0)))]
2386: ""
2387: "*
2388: { if (cc_prev_status.flags & CC_Z_IN_F)
2389: return \"sfsw %0\";
2390: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2391: return \"sfcw %0\";
2392: else return \"snew %0\";
2393: }")
2394:
2395: (define_insn ""
2396: [(set (match_operand:QI 0 "general_operand" "=g<")
2397: (ne:QI (cc0) (const_int 0)))]
2398: ""
2399: "*
2400: { if (cc_prev_status.flags & CC_Z_IN_F)
2401: return \"sfsb %0\";
2402: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2403: return \"sfcb %0\";
2404: else return \"sneb %0\";
2405: }")
2406:
2407: (define_insn "sgt"
2408: [(set (match_operand:SI 0 "general_operand" "=g<")
2409: (gt:SI (cc0) (const_int 0)))]
2410: ""
2411: "sgtd %0")
2412:
2413: (define_insn ""
2414: [(set (match_operand:HI 0 "general_operand" "=g<")
2415: (gt:HI (cc0) (const_int 0)))]
2416: ""
2417: "sgtw %0")
2418:
2419: (define_insn ""
2420: [(set (match_operand:QI 0 "general_operand" "=g<")
2421: (gt:QI (cc0) (const_int 0)))]
2422: ""
2423: "sgtb %0")
2424:
2425: (define_insn "sgtu"
2426: [(set (match_operand:SI 0 "general_operand" "=g<")
2427: (gtu:SI (cc0) (const_int 0)))]
2428: ""
2429: "shid %0")
2430:
2431: (define_insn ""
2432: [(set (match_operand:HI 0 "general_operand" "=g<")
2433: (gtu:HI (cc0) (const_int 0)))]
2434: ""
2435: "shiw %0")
2436:
2437: (define_insn ""
2438: [(set (match_operand:QI 0 "general_operand" "=g<")
2439: (gtu:QI (cc0) (const_int 0)))]
2440: ""
2441: "shib %0")
2442:
2443: (define_insn "slt"
2444: [(set (match_operand:SI 0 "general_operand" "=g<")
2445: (lt:SI (cc0) (const_int 0)))]
2446: ""
2447: "sltd %0")
2448:
2449: (define_insn ""
2450: [(set (match_operand:HI 0 "general_operand" "=g<")
2451: (lt:HI (cc0) (const_int 0)))]
2452: ""
2453: "sltw %0")
2454:
2455: (define_insn ""
2456: [(set (match_operand:QI 0 "general_operand" "=g<")
2457: (lt:QI (cc0) (const_int 0)))]
2458: ""
2459: "sltb %0")
2460:
2461: (define_insn "sltu"
2462: [(set (match_operand:SI 0 "general_operand" "=g<")
2463: (ltu:SI (cc0) (const_int 0)))]
2464: ""
2465: "slod %0")
2466:
2467: (define_insn ""
2468: [(set (match_operand:HI 0 "general_operand" "=g<")
2469: (ltu:HI (cc0) (const_int 0)))]
2470: ""
2471: "slow %0")
2472:
2473: (define_insn ""
2474: [(set (match_operand:QI 0 "general_operand" "=g<")
2475: (ltu:QI (cc0) (const_int 0)))]
2476: ""
2477: "slob %0")
2478:
2479: (define_insn "sge"
2480: [(set (match_operand:SI 0 "general_operand" "=g<")
2481: (ge:SI (cc0) (const_int 0)))]
2482: ""
2483: "sged %0")
2484:
2485: (define_insn ""
2486: [(set (match_operand:HI 0 "general_operand" "=g<")
2487: (ge:HI (cc0) (const_int 0)))]
2488: ""
2489: "sgew %0")
2490:
2491: (define_insn ""
2492: [(set (match_operand:QI 0 "general_operand" "=g<")
2493: (ge:QI (cc0) (const_int 0)))]
2494: ""
2495: "sgeb %0")
2496:
2497: (define_insn "sgeu"
2498: [(set (match_operand:SI 0 "general_operand" "=g<")
2499: (geu:SI (cc0) (const_int 0)))]
2500: ""
2501: "shsd %0")
2502:
2503: (define_insn ""
2504: [(set (match_operand:HI 0 "general_operand" "=g<")
2505: (geu:HI (cc0) (const_int 0)))]
2506: ""
2507: "shsw %0")
2508:
2509: (define_insn ""
2510: [(set (match_operand:QI 0 "general_operand" "=g<")
2511: (geu:QI (cc0) (const_int 0)))]
2512: ""
2513: "shsb %0")
2514:
2515: (define_insn "sle"
2516: [(set (match_operand:SI 0 "general_operand" "=g<")
2517: (le:SI (cc0) (const_int 0)))]
2518: ""
2519: "sled %0")
2520:
2521: (define_insn ""
2522: [(set (match_operand:HI 0 "general_operand" "=g<")
2523: (le:HI (cc0) (const_int 0)))]
2524: ""
2525: "slew %0")
2526:
2527: (define_insn ""
2528: [(set (match_operand:QI 0 "general_operand" "=g<")
2529: (le:QI (cc0) (const_int 0)))]
2530: ""
2531: "sleb %0")
2532:
2533: (define_insn "sleu"
2534: [(set (match_operand:SI 0 "general_operand" "=g<")
2535: (leu:SI (cc0) (const_int 0)))]
2536: ""
2537: "slsd %0")
2538:
2539: (define_insn ""
2540: [(set (match_operand:HI 0 "general_operand" "=g<")
2541: (leu:HI (cc0) (const_int 0)))]
2542: ""
2543: "slsw %0")
2544:
2545: (define_insn ""
2546: [(set (match_operand:QI 0 "general_operand" "=g<")
2547: (leu:QI (cc0) (const_int 0)))]
2548: ""
2549: "slsb %0")
2550:
2551: ;;- Local variables:
2552: ;;- mode:emacs-lisp
2553: ;;- comment-start: ";;- "
2554: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2555: ;;- eval: (modify-syntax-entry ?[ "(]")
2556: ;;- eval: (modify-syntax-entry ?] ")[")
2557: ;;- eval: (modify-syntax-entry ?{ "(}")
2558: ;;- eval: (modify-syntax-entry ?} "){")
2559: ;;- End:
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