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1.1 root 1: ; BUGS:
2: ;; Insert no-op between an insn with memory read-write operands
3: ;; following by a scale-indexing operation.
4: ;; The Sequent assembler does not allow addresses to be used
5: ;; except in insns which explicitly compute an effective address.
6: ;; I.e., one cannot say "cmpd _p,@_x"
7: ;; Implement unsigned multiplication??
8:
1.1.1.2 root 9: ;;- Machine description for GNU compiler
1.1 root 10: ;;- ns32000 Version
11: ;; Copyright (C) 1988 Free Software Foundation, Inc.
12: ;; Contributed by Michael Tiemann ([email protected])
13:
14: ;; This file is part of GNU CC.
15:
16: ;; GNU CC is free software; you can redistribute it and/or modify
17: ;; it under the terms of the GNU General Public License as published by
18: ;; the Free Software Foundation; either version 2, or (at your option)
19: ;; any later version.
20:
21: ;; GNU CC is distributed in the hope that it will be useful,
22: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
23: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24: ;; GNU General Public License for more details.
25:
26: ;; You should have received a copy of the GNU General Public License
27: ;; along with GNU CC; see the file COPYING. If not, write to
28: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
29:
30:
31: ;;- Instruction patterns. When multiple patterns apply,
32: ;;- the first one in the file is chosen.
33: ;;-
34: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
35: ;;-
36: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
37: ;;- updates for most instructions.
38:
39: ;; We don't want to allow a constant operand for test insns because
40: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
41: ;; be folded while optimizing anyway.
42:
43: (define_insn "tstsi"
44: [(set (cc0)
45: (match_operand:SI 0 "nonimmediate_operand" "rm"))]
46: ""
47: "*
48: { cc_status.flags |= CC_REVERSED;
49: operands[1] = const0_rtx;
50: return \"cmpqd %1,%0\"; }")
51:
52: (define_insn "tsthi"
53: [(set (cc0)
54: (match_operand:HI 0 "nonimmediate_operand" "g"))]
55: ""
56: "*
57: { cc_status.flags |= CC_REVERSED;
58: operands[1] = const0_rtx;
59: return \"cmpqw %1,%0\"; }")
60:
61: (define_insn "tstqi"
62: [(set (cc0)
63: (match_operand:QI 0 "nonimmediate_operand" "g"))]
64: ""
65: "*
66: { cc_status.flags |= CC_REVERSED;
67: operands[1] = const0_rtx;
68: return \"cmpqb %1,%0\"; }")
69:
70: (define_insn "tstdf"
71: [(set (cc0)
72: (match_operand:DF 0 "general_operand" "fmF"))]
73: "TARGET_32081"
74: "*
75: { cc_status.flags |= CC_REVERSED;
76: operands[1] = CONST0_RTX (DFmode);
77: return \"cmpl %1,%0\"; }")
78:
79: (define_insn "tstsf"
80: [(set (cc0)
81: (match_operand:SF 0 "general_operand" "fmF"))]
82: "TARGET_32081"
83: "*
84: { cc_status.flags |= CC_REVERSED;
85: operands[1] = CONST0_RTX (SFmode);
86: return \"cmpf %1,%0\"; }")
87:
88: (define_insn "cmpsi"
89: [(set (cc0)
90: (compare (match_operand:SI 0 "nonimmediate_operand" "rmn")
91: (match_operand:SI 1 "general_operand" "rmn")))]
92: ""
93: "*
94: {
95: if (GET_CODE (operands[1]) == CONST_INT)
96: {
97: int i = INTVAL (operands[1]);
98: if (i <= 7 && i >= -8)
99: {
100: cc_status.flags |= CC_REVERSED;
101: return \"cmpqd %1,%0\";
102: }
103: }
104: cc_status.flags &= ~CC_REVERSED;
105: if (GET_CODE (operands[0]) == CONST_INT)
106: {
107: int i = INTVAL (operands[0]);
108: if (i <= 7 && i >= -8)
109: return \"cmpqd %0,%1\";
110: }
111: return \"cmpd %0,%1\";
112: }")
113:
114: (define_insn "cmphi"
115: [(set (cc0)
116: (compare (match_operand:HI 0 "nonimmediate_operand" "g")
117: (match_operand:HI 1 "general_operand" "g")))]
118: ""
119: "*
120: {
121: if (GET_CODE (operands[1]) == CONST_INT)
122: {
123: short i = INTVAL (operands[1]);
124: if (i <= 7 && i >= -8)
125: {
126: cc_status.flags |= CC_REVERSED;
127: if (INTVAL (operands[1]) > 7)
128: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
129: return \"cmpqw %1,%0\";
130: }
131: }
132: cc_status.flags &= ~CC_REVERSED;
133: if (GET_CODE (operands[0]) == CONST_INT)
134: {
135: short i = INTVAL (operands[0]);
136: if (i <= 7 && i >= -8)
137: {
138: if (INTVAL (operands[0]) > 7)
139: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
140: return \"cmpqw %0,%1\";
141: }
142: }
143: return \"cmpw %0,%1\";
144: }")
145:
146: (define_insn "cmpqi"
147: [(set (cc0)
148: (compare (match_operand:QI 0 "nonimmediate_operand" "g")
149: (match_operand:QI 1 "general_operand" "g")))]
150: ""
151: "*
152: {
153: if (GET_CODE (operands[1]) == CONST_INT)
154: {
155: char i = INTVAL (operands[1]);
156: if (i <= 7 && i >= -8)
157: {
158: cc_status.flags |= CC_REVERSED;
159: if (INTVAL (operands[1]) > 7)
160: operands[1] = gen_rtx(CONST_INT, VOIDmode, i);
161: return \"cmpqb %1,%0\";
162: }
163: }
164: cc_status.flags &= ~CC_REVERSED;
165: if (GET_CODE (operands[0]) == CONST_INT)
166: {
167: char i = INTVAL (operands[0]);
168: if (i <= 7 && i >= -8)
169: {
170: if (INTVAL (operands[0]) > 7)
171: operands[0] = gen_rtx(CONST_INT, VOIDmode, i);
172: return \"cmpqb %0,%1\";
173: }
174: }
175: return \"cmpb %0,%1\";
176: }")
177:
178: (define_insn "cmpdf"
179: [(set (cc0)
180: (compare (match_operand:DF 0 "general_operand" "fmF")
181: (match_operand:DF 1 "general_operand" "fmF")))]
182: "TARGET_32081"
183: "cmpl %0,%1")
184:
185: (define_insn "cmpsf"
186: [(set (cc0)
187: (compare (match_operand:SF 0 "general_operand" "fmF")
188: (match_operand:SF 1 "general_operand" "fmF")))]
189: "TARGET_32081"
190: "cmpf %0,%1")
191:
192: (define_insn "movdf"
193: [(set (match_operand:DF 0 "general_operand" "=&fg<")
194: (match_operand:DF 1 "general_operand" "fFg"))]
195: ""
196: "*
197: {
198: if (FP_REG_P (operands[0]))
199: {
200: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
201: return \"movl %1,%0\";
202: if (REG_P (operands[1]))
203: {
204: rtx xoperands[2];
205: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
206: output_asm_insn (\"movd %1,tos\", xoperands);
207: output_asm_insn (\"movd %1,tos\", operands);
208: return \"movl tos,%0\";
209: }
210: return \"movl %1,%0\";
211: }
212: else if (FP_REG_P (operands[1]))
213: {
214: if (REG_P (operands[0]))
215: {
216: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
217: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
218: return \"movd tos,%0\";
219: }
220: else
221: return \"movl %1,%0\";
222: }
223: return output_move_double (operands);
224: }")
225:
226: (define_insn "movsf"
227: [(set (match_operand:SF 0 "general_operand" "=fg<")
228: (match_operand:SF 1 "general_operand" "fFg"))]
229: ""
230: "*
231: {
232: if (FP_REG_P (operands[0]))
233: {
234: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
235: return \"movd %1,tos\;movf tos,%0\";
236: else
237: return \"movf %1,%0\";
238: }
239: else if (FP_REG_P (operands[1]))
240: {
241: if (REG_P (operands[0]))
242: return \"movf %1,tos\;movd tos,%0\";
243: return \"movf %1,%0\";
244: }
1.1.1.2 root 245: #if 0 /* Someone suggested this for the Sequent. Is it needed? */
246: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
247: return \"movf %1,%0\";
248: #endif
249: /* There was a #if 0 around this, but that was erroneous
1.1.1.3 root 250: for many machines -- rms. */
251: #ifndef MOVD_FLOAT_OK
1.1 root 252: /* GAS understands floating constants in ordinary movd instructions
253: but other assemblers might object. */
254: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
255: {
256: union {int i[2]; float f; double d;} convrt;
257: convrt.i[0] = CONST_DOUBLE_LOW (operands[1]);
258: convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]);
259: convrt.f = convrt.d;
260:
261: /* Is there a better machine-independent way to to this? */
262: operands[1] = gen_rtx (CONST_INT, VOIDmode, convrt.i[0]);
263: return \"movd %1,%0\";
264: }
265: #endif
266: else return \"movd %1,%0\";
267: }")
268:
269: (define_insn ""
270: [(set (match_operand:TI 0 "memory_operand" "=m")
271: (match_operand:TI 1 "memory_operand" "m"))]
272: ""
273: "movmd %1,%0,4")
274:
275: (define_insn "movdi"
276: [(set (match_operand:DI 0 "general_operand" "=&g<,*f,g")
277: (match_operand:DI 1 "general_operand" "gF,g,*f"))]
278: ""
279: "*
280: {
281: if (FP_REG_P (operands[0]))
282: {
283: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE)
284: return \"movl %1,%0\";
285: if (REG_P (operands[1]))
286: {
287: rtx xoperands[2];
288: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
289: output_asm_insn (\"movd %1,tos\", xoperands);
290: output_asm_insn (\"movd %1,tos\", operands);
291: return \"movl tos,%0\";
292: }
293: return \"movl %1,%0\";
294: }
295: else if (FP_REG_P (operands[1]))
296: {
297: if (REG_P (operands[0]))
298: {
299: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands);
300: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
301: return \"movd tos,%0\";
302: }
303: else
304: return \"movl %1,%0\";
305: }
306: return output_move_double (operands);
307: }")
308:
309: ;; This special case must precede movsi.
310: (define_insn ""
311: [(set (reg:SI 17)
312: (match_operand:SI 0 "general_operand" "rmn"))]
313: ""
314: "lprd sp,%0")
315:
316: (define_insn "movsi"
1.1.1.4 ! root 317: [(set (match_operand:SI 0 "general_operand" "=g<,g<,*f,g")
! 318: (match_operand:SI 1 "general_operand" "g,?xy,g,*f"))]
1.1 root 319: ""
320: "*
321: {
322: if (FP_REG_P (operands[0]))
323: {
324: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
325: return \"movd %1,tos\;movf tos,%0\";
326: else
327: return \"movf %1,%0\";
328: }
329: else if (FP_REG_P (operands[1]))
330: {
331: if (REG_P (operands[0]))
332: return \"movf %1,tos\;movd tos,%0\";
333: return \"movf %1,%0\";
334: }
335: if (GET_CODE (operands[1]) == CONST_INT)
336: {
337: int i = INTVAL (operands[1]);
338: if (i <= 7 && i >= -8)
339: return \"movqd %1,%0\";
340: if (i < 0x4000 && i >= -0x4000 && ! TARGET_32532)
341: #if defined (GNX_V3) || defined (UTEK_ASM)
342: return \"addr %c1,%0\";
343: #else
344: return \"addr @%c1,%0\";
345: #endif
346: return \"movd %1,%0\";
347: }
348: else if (GET_CODE (operands[1]) == REG)
349: {
350: if (REGNO (operands[1]) < 16)
351: return \"movd %1,%0\";
352: else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM)
353: {
354: if (GET_CODE(operands[0]) == REG)
355: return \"sprd fp,%0\";
356: else
357: return \"addr 0(fp),%0\" ;
358: }
359: else if (REGNO (operands[1]) == STACK_POINTER_REGNUM)
360: {
361: if (GET_CODE(operands[0]) == REG)
362: return \"sprd sp,%0\";
363: else
364: return \"addr 0(sp),%0\" ;
365: }
366: else abort ();
367: }
368: else if (GET_CODE (operands[1]) == MEM)
369: return \"movd %1,%0\";
370: /* Check if this effective address can be
371: calculated faster by pulling it apart. */
372: if (REG_P (operands[0])
373: && GET_CODE (operands[1]) == MULT
374: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
375: && (INTVAL (XEXP (operands[1], 1)) == 2
376: || INTVAL (XEXP (operands[1], 1)) == 4))
377: {
378: rtx xoperands[3];
379: xoperands[0] = operands[0];
380: xoperands[1] = XEXP (operands[1], 0);
381: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
382: return output_shift_insn (xoperands);
383: }
384: return \"addr %a1,%0\";
385: }")
386:
387: (define_insn "movhi"
388: [(set (match_operand:HI 0 "general_operand" "=g<,*f,g")
389: (match_operand:HI 1 "general_operand" "g,g,*f"))]
390: ""
391: "*
392: {
393: if (GET_CODE (operands[1]) == CONST_INT)
394: {
395: short i = INTVAL (operands[1]);
396: if (i <= 7 && i >= -8)
397: {
398: if (INTVAL (operands[1]) > 7)
399: operands[1] =
400: gen_rtx (CONST_INT, VOIDmode, i);
401: return \"movqw %1,%0\";
402: }
403: return \"movw %1,%0\";
404: }
405: else if (FP_REG_P (operands[0]))
406: {
407: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
408: return \"movwf %1,tos\;movf tos,%0\";
409: else
410: return \"movwf %1,%0\";
411: }
412: else if (FP_REG_P (operands[1]))
413: {
414: if (REG_P (operands[0]))
415: return \"movf %1,tos\;movd tos,%0\";
416: return \"movf %1,%0\";
417: }
418: else
419: return \"movw %1,%0\";
420: }")
421:
422: (define_insn "movstricthi"
423: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r"))
424: (match_operand:HI 1 "general_operand" "g"))]
425: ""
426: "*
427: {
428: if (GET_CODE (operands[1]) == CONST_INT
429: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8)
430: return \"movqw %1,%0\";
431: return \"movw %1,%0\";
432: }")
433:
434: (define_insn "movqi"
435: [(set (match_operand:QI 0 "general_operand" "=g<,*f,g")
436: (match_operand:QI 1 "general_operand" "g,g,*f"))]
437: ""
438: "*
439: { if (GET_CODE (operands[1]) == CONST_INT)
440: {
441: char char_val = (char)INTVAL (operands[1]);
442: if (char_val <= 7 && char_val >= -8)
443: {
444: if (INTVAL (operands[1]) > 7)
445: operands[1] =
446: gen_rtx (CONST_INT, VOIDmode, char_val);
447: return \"movqb %1,%0\";
448: }
449: return \"movb %1,%0\";
450: }
451: else if (FP_REG_P (operands[0]))
452: {
453: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8)
454: return \"movbf %1,tos\;movf tos,%0\";
455: else
456: return \"movbf %1,%0\";
457: }
458: else if (FP_REG_P (operands[1]))
459: {
460: if (REG_P (operands[0]))
461: return \"movf %1,tos\;movd tos,%0\";
462: return \"movf %1,%0\";
463: }
464: else
465: return \"movb %1,%0\";
466: }")
467:
468: (define_insn "movstrictqi"
469: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r"))
470: (match_operand:QI 1 "general_operand" "g"))]
471: ""
472: "*
473: {
474: if (GET_CODE (operands[1]) == CONST_INT
475: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9)
476: return \"movqb %1,%0\";
477: return \"movb %1,%0\";
478: }")
479:
1.1.1.4 ! root 480: ;; This is here to accept 4 arguments and pass the first 3 along
! 481: ;; to the movstrsi1 pattern that really does the work.
! 482: (define_expand "movstrsi"
! 483: [(set (match_operand:BLK 0 "general_operand" "=g")
! 484: (match_operand:BLK 1 "general_operand" "g"))
! 485: (use (match_operand:SI 2 "general_operand" "rmn"))
! 486: (match_operand 3 "" "")]
! 487: ""
! 488: "
! 489: emit_insn (gen_movstrsi1 (operands[0], operands[1], operands[2]));
! 490: DONE;
! 491: ")
! 492:
1.1 root 493: ;; The definition of this insn does not really explain what it does,
494: ;; but it should suffice
495: ;; that anything generated as this insn will be recognized as one
496: ;; and that it won't successfully combine with anything.
1.1.1.4 ! root 497: (define_insn "movstrsi1"
1.1 root 498: [(set (match_operand:BLK 0 "general_operand" "=g")
499: (match_operand:BLK 1 "general_operand" "g"))
500: (use (match_operand:SI 2 "general_operand" "rmn"))
501: (clobber (reg:SI 0))
502: (clobber (reg:SI 1))
503: (clobber (reg:SI 2))]
504: ""
505: "*
506: {
507: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)
508: abort ();
509: operands[0] = XEXP (operands[0], 0);
510: operands[1] = XEXP (operands[1], 0);
511: if (GET_CODE (operands[0]) == MEM)
512: if (GET_CODE (operands[1]) == MEM)
513: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands);
514: else
515: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands);
516: else if (GET_CODE (operands[1]) == MEM)
517: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands);
518: else
519: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands);
520:
521: #ifdef UTEK_ASM
522: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
523: {
524: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
525: if ((unsigned) INTVAL (operands[2]) <= 7)
526: return \"movqd %2,r0\;movsd $0\";
527: else
528: return \"movd %2,r0\;movsd $0\";
529: }
530: else
531: {
532: return \"movd %2,r0\;movsb $0\";
533: }
534: #else
535: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0)
536: {
537: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2);
538: if ((unsigned) INTVAL (operands[2]) <= 7)
539: return \"movqd %2,r0\;movsd\";
540: else
541: return \"movd %2,r0\;movsd\";
542: }
543: else
544: {
545: return \"movd %2,r0\;movsb\";
546: }
547: #endif
548: }")
549:
550: ;; Extension and truncation insns.
551: ;; Those for integer source operand
552: ;; are ordered widest source type first.
553:
554: (define_insn "truncsiqi2"
555: [(set (match_operand:QI 0 "general_operand" "=g<")
556: (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "rmn")))]
557: ""
558: "movb %1,%0")
559:
560: (define_insn "truncsihi2"
561: [(set (match_operand:HI 0 "general_operand" "=g<")
562: (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "rmn")))]
563: ""
564: "movw %1,%0")
565:
566: (define_insn "trunchiqi2"
567: [(set (match_operand:QI 0 "general_operand" "=g<")
568: (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))]
569: ""
570: "movb %1,%0")
571:
572: (define_insn "extendhisi2"
573: [(set (match_operand:SI 0 "general_operand" "=g<")
574: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
575: ""
576: "movxwd %1,%0")
577:
578: (define_insn "extendqihi2"
579: [(set (match_operand:HI 0 "general_operand" "=g<")
580: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
581: ""
582: "movxbw %1,%0")
583:
584: (define_insn "extendqisi2"
585: [(set (match_operand:SI 0 "general_operand" "=g<")
586: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
587: ""
588: "movxbd %1,%0")
589:
590: (define_insn "extendsfdf2"
591: [(set (match_operand:DF 0 "general_operand" "=fm<")
592: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))]
593: "TARGET_32081"
594: "movfl %1,%0")
595:
596: (define_insn "truncdfsf2"
597: [(set (match_operand:SF 0 "general_operand" "=fm<")
598: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))]
599: "TARGET_32081"
600: "movlf %1,%0")
601:
602: (define_insn "zero_extendhisi2"
603: [(set (match_operand:SI 0 "general_operand" "=g<")
604: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))]
605: ""
606: "movzwd %1,%0")
607:
608: (define_insn "zero_extendqihi2"
609: [(set (match_operand:HI 0 "general_operand" "=g<")
610: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))]
611: ""
612: "movzbw %1,%0")
613:
614: (define_insn "zero_extendqisi2"
615: [(set (match_operand:SI 0 "general_operand" "=g<")
616: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))]
617: ""
618: "movzbd %1,%0")
619:
620: ;; Fix-to-float conversion insns.
621: ;; Note that the ones that start with SImode come first.
622: ;; That is so that an operand that is a CONST_INT
623: ;; (and therefore lacks a specific machine mode).
624: ;; will be recognized as SImode (which is always valid)
625: ;; rather than as QImode or HImode.
626:
627: ;; Rumor has it that the National part does not correctly convert
628: ;; constant ints to floats. This conversion is therefore disabled.
629: ;; A register must be used to perform the conversion.
630:
631: (define_insn "floatsisf2"
632: [(set (match_operand:SF 0 "general_operand" "=fm<")
633: (float:SF (match_operand:SI 1 "general_operand" "rm")))]
634: "TARGET_32081"
635: "movdf %1,%0")
636:
637: (define_insn "floatsidf2"
638: [(set (match_operand:DF 0 "general_operand" "=fm<")
639: (float:DF (match_operand:SI 1 "general_operand" "rm")))]
640: "TARGET_32081"
641: "movdl %1,%0")
642:
643: (define_insn "floathisf2"
644: [(set (match_operand:SF 0 "general_operand" "=fm<")
645: (float:SF (match_operand:HI 1 "general_operand" "rm")))]
646: "TARGET_32081"
647: "movwf %1,%0")
648:
649: (define_insn "floathidf2"
650: [(set (match_operand:DF 0 "general_operand" "=fm<")
651: (float:DF (match_operand:HI 1 "general_operand" "rm")))]
652: "TARGET_32081"
653: "movwl %1,%0")
654:
655: (define_insn "floatqisf2"
656: [(set (match_operand:SF 0 "general_operand" "=fm<")
657: (float:SF (match_operand:QI 1 "general_operand" "rm")))]
658: "TARGET_32081"
659: "movbf %1,%0")
660:
661: ; Some assemblers warn that this insn doesn't work.
662: ; Maybe they know something we don't.
663: ;(define_insn "floatqidf2"
664: ; [(set (match_operand:DF 0 "general_operand" "=fm<")
665: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))]
666: ; "TARGET_32081"
667: ; "movbl %1,%0")
668:
669: ;; Float-to-fix conversion insns.
670: ;; The sequent compiler always generates "trunc" insns.
671:
672: (define_insn "fixsfqi2"
673: [(set (match_operand:QI 0 "general_operand" "=g<")
674: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
675: "TARGET_32081"
676: "truncfb %1,%0")
677:
678: (define_insn "fixsfhi2"
679: [(set (match_operand:HI 0 "general_operand" "=g<")
680: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
681: "TARGET_32081"
682: "truncfw %1,%0")
683:
684: (define_insn "fixsfsi2"
685: [(set (match_operand:SI 0 "general_operand" "=g<")
686: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
687: "TARGET_32081"
688: "truncfd %1,%0")
689:
690: (define_insn "fixdfqi2"
691: [(set (match_operand:QI 0 "general_operand" "=g<")
692: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
693: "TARGET_32081"
694: "trunclb %1,%0")
695:
696: (define_insn "fixdfhi2"
697: [(set (match_operand:HI 0 "general_operand" "=g<")
698: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
699: "TARGET_32081"
700: "trunclw %1,%0")
701:
702: (define_insn "fixdfsi2"
703: [(set (match_operand:SI 0 "general_operand" "=g<")
704: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
705: "TARGET_32081"
706: "truncld %1,%0")
707:
708: ;; Unsigned
709:
710: (define_insn "fixunssfqi2"
711: [(set (match_operand:QI 0 "general_operand" "=g<")
712: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
713: "TARGET_32081"
714: "truncfb %1,%0")
715:
716: (define_insn "fixunssfhi2"
717: [(set (match_operand:HI 0 "general_operand" "=g<")
718: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
719: "TARGET_32081"
720: "truncfw %1,%0")
721:
722: (define_insn "fixunssfsi2"
723: [(set (match_operand:SI 0 "general_operand" "=g<")
724: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))]
725: "TARGET_32081"
726: "truncfd %1,%0")
727:
728: (define_insn "fixunsdfqi2"
729: [(set (match_operand:QI 0 "general_operand" "=g<")
730: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
731: "TARGET_32081"
732: "trunclb %1,%0")
733:
734: (define_insn "fixunsdfhi2"
735: [(set (match_operand:HI 0 "general_operand" "=g<")
736: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
737: "TARGET_32081"
738: "trunclw %1,%0")
739:
740: (define_insn "fixunsdfsi2"
741: [(set (match_operand:SI 0 "general_operand" "=g<")
742: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))]
743: "TARGET_32081"
744: "truncld %1,%0")
745:
746: ;;; These are not yet used by GCC
747: (define_insn "fix_truncsfqi2"
748: [(set (match_operand:QI 0 "general_operand" "=g<")
749: (fix:QI (match_operand:SF 1 "general_operand" "fm")))]
750: "TARGET_32081"
751: "truncfb %1,%0")
752:
753: (define_insn "fix_truncsfhi2"
754: [(set (match_operand:HI 0 "general_operand" "=g<")
755: (fix:HI (match_operand:SF 1 "general_operand" "fm")))]
756: "TARGET_32081"
757: "truncfw %1,%0")
758:
759: (define_insn "fix_truncsfsi2"
760: [(set (match_operand:SI 0 "general_operand" "=g<")
761: (fix:SI (match_operand:SF 1 "general_operand" "fm")))]
762: "TARGET_32081"
763: "truncfd %1,%0")
764:
765: (define_insn "fix_truncdfqi2"
766: [(set (match_operand:QI 0 "general_operand" "=g<")
767: (fix:QI (match_operand:DF 1 "general_operand" "fm")))]
768: "TARGET_32081"
769: "trunclb %1,%0")
770:
771: (define_insn "fix_truncdfhi2"
772: [(set (match_operand:HI 0 "general_operand" "=g<")
773: (fix:HI (match_operand:DF 1 "general_operand" "fm")))]
774: "TARGET_32081"
775: "trunclw %1,%0")
776:
777: (define_insn "fix_truncdfsi2"
778: [(set (match_operand:SI 0 "general_operand" "=g<")
779: (fix:SI (match_operand:DF 1 "general_operand" "fm")))]
780: "TARGET_32081"
781: "truncld %1,%0")
782:
783: ;;- All kinds of add instructions.
784:
785: (define_insn "adddf3"
786: [(set (match_operand:DF 0 "general_operand" "=fm")
787: (plus:DF (match_operand:DF 1 "general_operand" "%0")
788: (match_operand:DF 2 "general_operand" "fmF")))]
789: "TARGET_32081"
790: "addl %2,%0")
791:
792:
793: (define_insn "addsf3"
794: [(set (match_operand:SF 0 "general_operand" "=fm")
795: (plus:SF (match_operand:SF 1 "general_operand" "%0")
796: (match_operand:SF 2 "general_operand" "fmF")))]
797: "TARGET_32081"
798: "addf %2,%0")
799:
800: (define_insn ""
801: [(set (reg:SI 17)
802: (plus:SI (reg:SI 17)
803: (match_operand:SI 0 "immediate_operand" "i")))]
804: "GET_CODE (operands[0]) == CONST_INT"
805: "*
806: {
807: #ifndef SEQUENT_ADJUST_STACK
808: if (TARGET_32532)
809: if (INTVAL (operands[0]) == 8)
810: return \"cmpd tos,tos\";
811: if (TARGET_32532 || TARGET_32332)
812: if (INTVAL (operands[0]) == 4)
813: return \"cmpqd %$0,tos\";
814: #endif
815: if (! TARGET_32532)
816: {
817: if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64)
818: return \"adjspb %$%n0\";
819: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192)
820: return \"adjspw %$%n0\";
821: }
822: return \"adjspd %$%n0\";
823: }")
824:
825: (define_insn ""
826: [(set (match_operand:SI 0 "general_operand" "=g<")
827: (plus:SI (reg:SI 16)
828: (match_operand:SI 1 "immediate_operand" "i")))]
829: "GET_CODE (operands[1]) == CONST_INT"
830: "addr %c1(fp),%0")
831:
832: (define_insn ""
833: [(set (match_operand:SI 0 "general_operand" "=g<")
834: (plus:SI (reg:SI 17)
835: (match_operand:SI 1 "immediate_operand" "i")))]
836: "GET_CODE (operands[1]) == CONST_INT"
837: "addr %c1(sp),%0")
838:
839: (define_insn "addsi3"
1.1.1.4 ! root 840: [(set (match_operand:SI 0 "general_operand" "=g,=g&<")
! 841: (plus:SI (match_operand:SI 1 "general_operand" "%0,r")
1.1 root 842: (match_operand:SI 2 "general_operand" "rmn,n")))]
843: ""
844: "*
845: {
846: if (which_alternative == 1)
847: {
848: int i = INTVAL (operands[2]);
1.1.1.3 root 849: if (NS32K_DISPLACEMENT_P (i))
850: return \"addr %c2(%1),%0\";
1.1 root 851: else
1.1.1.3 root 852: return \"movd %1,%0\;addd %2,%0\";
1.1 root 853: }
854: if (GET_CODE (operands[2]) == CONST_INT)
855: {
856: int i = INTVAL (operands[2]);
857:
858: if (i <= 7 && i >= -8)
859: return \"addqd %2,%0\";
860: else if (GET_CODE (operands[0]) == REG
861: && i < 0x4000 && i >= -0x4000 && ! TARGET_32532)
862: return \"addr %c2(%0),%0\";
863: }
864: return \"addd %2,%0\";
865: }")
866:
867: (define_insn "addhi3"
868: [(set (match_operand:HI 0 "general_operand" "=g")
869: (plus:HI (match_operand:HI 1 "general_operand" "%0")
870: (match_operand:HI 2 "general_operand" "g")))]
871: ""
872: "*
873: { if (GET_CODE (operands[2]) == CONST_INT)
874: {
875: int i = INTVAL (operands[2]);
876: if (i <= 7 && i >= -8)
877: return \"addqw %2,%0\";
878: }
879: return \"addw %2,%0\";
880: }")
881:
882: (define_insn ""
883: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
884: (plus:HI (match_operand:HI 1 "general_operand" "0")
885: (match_operand:HI 2 "general_operand" "g")))]
886: ""
887: "*
888: {
889: if (GET_CODE (operands[1]) == CONST_INT
890: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
891: return \"addqw %1,%0\";
892: return \"addw %1,%0\";
893: }")
894:
895: (define_insn "addqi3"
896: [(set (match_operand:QI 0 "general_operand" "=g")
897: (plus:QI (match_operand:QI 1 "general_operand" "%0")
898: (match_operand:QI 2 "general_operand" "g")))]
899: ""
900: "*
901: { if (GET_CODE (operands[2]) == CONST_INT)
902: {
903: int i = INTVAL (operands[2]);
904: if (i <= 7 && i >= -8)
905: return \"addqb %2,%0\";
906: }
907: return \"addb %2,%0\";
908: }")
909:
910: (define_insn ""
911: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
912: (plus:QI (match_operand:QI 1 "general_operand" "0")
913: (match_operand:QI 2 "general_operand" "g")))]
914: ""
915: "*
916: {
917: if (GET_CODE (operands[1]) == CONST_INT
918: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8)
919: return \"addqb %1,%0\";
920: return \"addb %1,%0\";
921: }")
922:
923: ;;- All kinds of subtract instructions.
924:
925: (define_insn "subdf3"
926: [(set (match_operand:DF 0 "general_operand" "=fm")
927: (minus:DF (match_operand:DF 1 "general_operand" "0")
928: (match_operand:DF 2 "general_operand" "fmF")))]
929: "TARGET_32081"
930: "subl %2,%0")
931:
932: (define_insn "subsf3"
933: [(set (match_operand:SF 0 "general_operand" "=fm")
934: (minus:SF (match_operand:SF 1 "general_operand" "0")
935: (match_operand:SF 2 "general_operand" "fmF")))]
936: "TARGET_32081"
937: "subf %2,%0")
938:
939: (define_insn ""
940: [(set (reg:SI 17)
941: (minus:SI (reg:SI 17)
942: (match_operand:SI 0 "immediate_operand" "i")))]
943: "GET_CODE (operands[0]) == CONST_INT"
944: "*
945: {
946: if (GET_CODE(operands[0]) == CONST_INT && INTVAL(operands[0]) < 64
947: && INTVAL(operands[0]) > -64 && ! TARGET_32532)
948: return \"adjspb %0\";
949: return \"adjspd %0\";
950: }")
951:
952: (define_insn "subsi3"
953: [(set (match_operand:SI 0 "general_operand" "=g")
954: (minus:SI (match_operand:SI 1 "general_operand" "0")
955: (match_operand:SI 2 "general_operand" "rmn")))]
956: ""
957: "*
958: { if (GET_CODE (operands[2]) == CONST_INT)
959: {
960: int i = INTVAL (operands[2]);
961:
962: if (i <= 8 && i >= -7)
963: return \"addqd %$%n2,%0\";
964: }
965: return \"subd %2,%0\";
966: }")
967:
968: (define_insn "subhi3"
969: [(set (match_operand:HI 0 "general_operand" "=g")
970: (minus:HI (match_operand:HI 1 "general_operand" "0")
971: (match_operand:HI 2 "general_operand" "g")))]
972: ""
973: "*
974: { if (GET_CODE (operands[2]) == CONST_INT)
975: {
976: int i = INTVAL (operands[2]);
977:
978: if (i <= 8 && i >= -7)
979: return \"addqw %$%n2,%0\";
980: }
981: return \"subw %2,%0\";
982: }")
983:
984: (define_insn ""
985: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r"))
986: (minus:HI (match_operand:HI 1 "general_operand" "0")
987: (match_operand:HI 2 "general_operand" "g")))]
988: ""
989: "*
990: {
991: if (GET_CODE (operands[1]) == CONST_INT
992: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
993: return \"addqw %$%n1,%0\";
994: return \"subw %1,%0\";
995: }")
996:
997: (define_insn "subqi3"
998: [(set (match_operand:QI 0 "general_operand" "=g")
999: (minus:QI (match_operand:QI 1 "general_operand" "0")
1000: (match_operand:QI 2 "general_operand" "g")))]
1001: ""
1002: "*
1003: { if (GET_CODE (operands[2]) == CONST_INT)
1004: {
1005: int i = INTVAL (operands[2]);
1006:
1007: if (i <= 8 && i >= -7)
1008: return \"addqb %$%n2,%0\";
1009: }
1010: return \"subb %2,%0\";
1011: }")
1012:
1013: (define_insn ""
1014: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r"))
1015: (minus:QI (match_operand:QI 1 "general_operand" "0")
1016: (match_operand:QI 2 "general_operand" "g")))]
1017: ""
1018: "*
1019: {
1020: if (GET_CODE (operands[1]) == CONST_INT
1021: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9)
1022: return \"addqb %$%n1,%0\";
1023: return \"subb %1,%0\";
1024: }")
1025:
1026: ;;- Multiply instructions.
1027:
1028: (define_insn "muldf3"
1029: [(set (match_operand:DF 0 "general_operand" "=fm")
1030: (mult:DF (match_operand:DF 1 "general_operand" "%0")
1031: (match_operand:DF 2 "general_operand" "fmF")))]
1032: "TARGET_32081"
1033: "mull %2,%0")
1034:
1035: (define_insn "mulsf3"
1036: [(set (match_operand:SF 0 "general_operand" "=fm")
1037: (mult:SF (match_operand:SF 1 "general_operand" "%0")
1038: (match_operand:SF 2 "general_operand" "fmF")))]
1039: "TARGET_32081"
1040: "mulf %2,%0")
1041:
1042: (define_insn "mulsi3"
1043: [(set (match_operand:SI 0 "general_operand" "=g")
1044: (mult:SI (match_operand:SI 1 "general_operand" "%0")
1045: (match_operand:SI 2 "general_operand" "rmn")))]
1046: ""
1047: "muld %2,%0")
1048:
1049: (define_insn "mulhi3"
1050: [(set (match_operand:HI 0 "general_operand" "=g")
1051: (mult:HI (match_operand:HI 1 "general_operand" "%0")
1052: (match_operand:HI 2 "general_operand" "g")))]
1053: ""
1054: "mulw %2,%0")
1055:
1056: (define_insn "mulqi3"
1057: [(set (match_operand:QI 0 "general_operand" "=g")
1058: (mult:QI (match_operand:QI 1 "general_operand" "%0")
1059: (match_operand:QI 2 "general_operand" "g")))]
1060: ""
1061: "mulb %2,%0")
1062:
1063: (define_insn "umulsidi3"
1064: [(set (match_operand:DI 0 "general_operand" "=g")
1065: (mult:DI (zero_extend:DI
1066: (match_operand:SI 1 "nonimmediate_operand" "0"))
1067: (zero_extend:DI
1068: (match_operand:SI 2 "nonimmediate_operand" "rmn"))))]
1069: ""
1070: "meid %2,%0")
1071:
1072: ;;- Divide instructions.
1073:
1074: (define_insn "divdf3"
1075: [(set (match_operand:DF 0 "general_operand" "=fm")
1076: (div:DF (match_operand:DF 1 "general_operand" "0")
1077: (match_operand:DF 2 "general_operand" "fmF")))]
1078: "TARGET_32081"
1079: "divl %2,%0")
1080:
1081: (define_insn "divsf3"
1082: [(set (match_operand:SF 0 "general_operand" "=fm")
1083: (div:SF (match_operand:SF 1 "general_operand" "0")
1084: (match_operand:SF 2 "general_operand" "fmF")))]
1085: "TARGET_32081"
1086: "divf %2,%0")
1087:
1088: (define_insn "divsi3"
1089: [(set (match_operand:SI 0 "general_operand" "=g")
1090: (div:SI (match_operand:SI 1 "general_operand" "0")
1091: (match_operand:SI 2 "general_operand" "rmn")))]
1092: ""
1093: "quod %2,%0")
1094:
1095: (define_insn "divhi3"
1096: [(set (match_operand:HI 0 "general_operand" "=g")
1097: (div:HI (match_operand:HI 1 "general_operand" "0")
1098: (match_operand:HI 2 "general_operand" "g")))]
1099: ""
1100: "quow %2,%0")
1101:
1102: (define_insn "divqi3"
1103: [(set (match_operand:QI 0 "general_operand" "=g")
1104: (div:QI (match_operand:QI 1 "general_operand" "0")
1105: (match_operand:QI 2 "general_operand" "g")))]
1106: ""
1107: "quob %2,%0")
1108:
1109: (define_insn "udivsi3"
1110: [(set (match_operand:SI 0 "register_operand" "=r")
1111: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1112: (match_operand:SI 2 "general_operand" "rmn")))]
1113: ""
1114: "*
1115: {
1116: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1117: return \"deid %2,%0\;movd %1,%0\";
1118: }")
1119:
1120: (define_insn "udivhi3"
1121: [(set (match_operand:HI 0 "register_operand" "=r")
1122: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1123: (match_operand:HI 2 "general_operand" "g")))]
1124: ""
1125: "*
1126: {
1127: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1);
1128: return \"deiw %2,%0\;movw %1,%0\";
1129: }")
1130:
1131: (define_insn "udivqi3"
1132: [(set (match_operand:QI 0 "register_operand" "=r")
1133: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1134: (match_operand:QI 2 "general_operand" "g")))]
1135: ""
1136: "*
1137: {
1138: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1);
1139: return \"deib %2,%0\;movb %1,%0\";
1140: }")
1141:
1142: ;; Remainder instructions.
1143:
1144: (define_insn "modsi3"
1145: [(set (match_operand:SI 0 "general_operand" "=g")
1146: (mod:SI (match_operand:SI 1 "general_operand" "0")
1147: (match_operand:SI 2 "general_operand" "rmn")))]
1148: ""
1149: "remd %2,%0")
1150:
1151: (define_insn "modhi3"
1152: [(set (match_operand:HI 0 "general_operand" "=g")
1153: (mod:HI (match_operand:HI 1 "general_operand" "0")
1154: (match_operand:HI 2 "general_operand" "g")))]
1155: ""
1156: "remw %2,%0")
1157:
1158: (define_insn "modqi3"
1159: [(set (match_operand:QI 0 "general_operand" "=g")
1160: (mod:QI (match_operand:QI 1 "general_operand" "0")
1161: (match_operand:QI 2 "general_operand" "g")))]
1162: ""
1163: "remb %2,%0")
1164:
1165: (define_insn "umodsi3"
1166: [(set (match_operand:SI 0 "register_operand" "=r")
1167: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1168: (match_operand:SI 2 "general_operand" "rmn")))]
1169: ""
1170: "deid %2,%0")
1171:
1172: (define_insn "umodhi3"
1173: [(set (match_operand:HI 0 "register_operand" "=r")
1174: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1175: (match_operand:HI 2 "general_operand" "g")))]
1176: ""
1177: "deiw %2,%0")
1178:
1179: (define_insn "umodqi3"
1180: [(set (match_operand:QI 0 "register_operand" "=r")
1181: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0)
1182: (match_operand:QI 2 "general_operand" "g")))]
1183: ""
1184: "deib %2,%0")
1185:
1186: ; This isn't be usable in its current form.
1187: ;(define_insn "udivmoddisi4"
1188: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1)
1189: ; (udiv:SI (match_operand:DI 1 "general_operand" "0")
1190: ; (match_operand:SI 2 "general_operand" "rmn")))
1191: ; (set (subreg:SI (match_dup 0) 0)
1192: ; (umod:SI (match_dup 1) (match_dup 2)))]
1193: ; ""
1194: ; "deid %2,%0")
1195:
1196: ;;- Logical Instructions: AND
1197:
1198: (define_insn "andsi3"
1199: [(set (match_operand:SI 0 "general_operand" "=g")
1200: (and:SI (match_operand:SI 1 "general_operand" "%0")
1201: (match_operand:SI 2 "general_operand" "rmn")))]
1202: ""
1203: "*
1204: {
1205: if (GET_CODE (operands[2]) == CONST_INT)
1206: {
1207: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff)
1208: {
1209: if (INTVAL (operands[2]) == 0xffffff00)
1210: return \"movqb %$0,%0\";
1211: else
1212: {
1213: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1214: INTVAL (operands[2]) & 0xff);
1215: return \"andb %2,%0\";
1216: }
1217: }
1218: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff)
1219: {
1220: if (INTVAL (operands[2]) == 0xffff0000)
1221: return \"movqw %$0,%0\";
1222: else
1223: {
1224: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1225: INTVAL (operands[2]) & 0xffff);
1226: return \"andw %2,%0\";
1227: }
1228: }
1229: }
1230: return \"andd %2,%0\";
1231: }")
1232:
1233: (define_insn "andhi3"
1234: [(set (match_operand:HI 0 "general_operand" "=g")
1235: (and:HI (match_operand:HI 1 "general_operand" "%0")
1236: (match_operand:HI 2 "general_operand" "g")))]
1237: ""
1238: "*
1239: {
1240: if (GET_CODE (operands[2]) == CONST_INT
1241: && (INTVAL (operands[2]) | 0xff) == 0xffffffff)
1242: {
1243: if (INTVAL (operands[2]) == 0xffffff00)
1244: return \"movqb %$0,%0\";
1245: else
1246: {
1247: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1248: INTVAL (operands[2]) & 0xff);
1249: return \"andb %2,%0\";
1250: }
1251: }
1252: return \"andw %2,%0\";
1253: }")
1254:
1255: (define_insn "andqi3"
1256: [(set (match_operand:QI 0 "general_operand" "=g")
1257: (and:QI (match_operand:QI 1 "general_operand" "%0")
1258: (match_operand:QI 2 "general_operand" "g")))]
1259: ""
1260: "andb %2,%0")
1261:
1262: (define_insn ""
1263: [(set (match_operand:SI 0 "general_operand" "=g")
1264: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn"))
1265: (match_operand:SI 2 "general_operand" "0")))]
1266: ""
1267: "bicd %1,%0")
1268:
1269: (define_insn ""
1270: [(set (match_operand:HI 0 "general_operand" "=g")
1271: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
1272: (match_operand:HI 2 "general_operand" "0")))]
1273: ""
1274: "bicw %1,%0")
1275:
1276: (define_insn ""
1277: [(set (match_operand:QI 0 "general_operand" "=g")
1278: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
1279: (match_operand:QI 2 "general_operand" "0")))]
1280: ""
1281: "bicb %1,%0")
1282:
1283: ;;- Bit set instructions.
1284:
1285: (define_insn "iorsi3"
1286: [(set (match_operand:SI 0 "general_operand" "=g")
1287: (ior:SI (match_operand:SI 1 "general_operand" "%0")
1288: (match_operand:SI 2 "general_operand" "rmn")))]
1289: ""
1290: "*
1291: {
1292: if (GET_CODE (operands[2]) == CONST_INT) {
1293: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1294: return \"orb %2,%0\";
1295: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1296: return \"orw %2,%0\";
1297: }
1298: return \"ord %2,%0\";
1299: }")
1300:
1301: (define_insn "iorhi3"
1302: [(set (match_operand:HI 0 "general_operand" "=g")
1303: (ior:HI (match_operand:HI 1 "general_operand" "%0")
1304: (match_operand:HI 2 "general_operand" "g")))]
1305: ""
1306: "*
1307: {
1308: if (GET_CODE(operands[2]) == CONST_INT &&
1309: (INTVAL(operands[2]) & 0xffffff00) == 0)
1310: return \"orb %2,%0\";
1311: return \"orw %2,%0\";
1312: }")
1313:
1314: (define_insn "iorqi3"
1315: [(set (match_operand:QI 0 "general_operand" "=g")
1316: (ior:QI (match_operand:QI 1 "general_operand" "%0")
1317: (match_operand:QI 2 "general_operand" "g")))]
1318: ""
1319: "orb %2,%0")
1320:
1321: ;;- xor instructions.
1322:
1323: (define_insn "xorsi3"
1324: [(set (match_operand:SI 0 "general_operand" "=g")
1325: (xor:SI (match_operand:SI 1 "general_operand" "%0")
1326: (match_operand:SI 2 "general_operand" "rmn")))]
1327: ""
1328: "*
1329: {
1330: if (GET_CODE (operands[2]) == CONST_INT) {
1331: if ((INTVAL (operands[2]) & 0xffffff00) == 0)
1332: return \"xorb %2,%0\";
1333: if ((INTVAL (operands[2]) & 0xffff0000) == 0)
1334: return \"xorw %2,%0\";
1335: }
1336: return \"xord %2,%0\";
1337: }")
1338:
1339: (define_insn "xorhi3"
1340: [(set (match_operand:HI 0 "general_operand" "=g")
1341: (xor:HI (match_operand:HI 1 "general_operand" "%0")
1342: (match_operand:HI 2 "general_operand" "g")))]
1343: ""
1344: "*
1345: {
1346: if (GET_CODE(operands[2]) == CONST_INT &&
1347: (INTVAL(operands[2]) & 0xffffff00) == 0)
1348: return \"xorb %2,%0\";
1349: return \"xorw %2,%0\";
1350: }")
1351:
1352: (define_insn "xorqi3"
1353: [(set (match_operand:QI 0 "general_operand" "=g")
1354: (xor:QI (match_operand:QI 1 "general_operand" "%0")
1355: (match_operand:QI 2 "general_operand" "g")))]
1356: ""
1357: "xorb %2,%0")
1358:
1359: (define_insn "negdf2"
1360: [(set (match_operand:DF 0 "general_operand" "=fm<")
1361: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))]
1362: "TARGET_32081"
1363: "negl %1,%0")
1364:
1365: (define_insn "negsf2"
1366: [(set (match_operand:SF 0 "general_operand" "=fm<")
1367: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))]
1368: "TARGET_32081"
1369: "negf %1,%0")
1370:
1371: (define_insn "negsi2"
1372: [(set (match_operand:SI 0 "general_operand" "=g<")
1373: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))]
1374: ""
1375: "negd %1,%0")
1376:
1377: (define_insn "neghi2"
1378: [(set (match_operand:HI 0 "general_operand" "=g<")
1379: (neg:HI (match_operand:HI 1 "general_operand" "g")))]
1380: ""
1381: "negw %1,%0")
1382:
1383: (define_insn "negqi2"
1384: [(set (match_operand:QI 0 "general_operand" "=g<")
1385: (neg:QI (match_operand:QI 1 "general_operand" "g")))]
1386: ""
1387: "negb %1,%0")
1388:
1389: (define_insn "one_cmplsi2"
1390: [(set (match_operand:SI 0 "general_operand" "=g<")
1391: (not:SI (match_operand:SI 1 "general_operand" "rmn")))]
1392: ""
1393: "comd %1,%0")
1394:
1395: (define_insn "one_cmplhi2"
1396: [(set (match_operand:HI 0 "general_operand" "=g<")
1397: (not:HI (match_operand:HI 1 "general_operand" "g")))]
1398: ""
1399: "comw %1,%0")
1400:
1401: (define_insn "one_cmplqi2"
1402: [(set (match_operand:QI 0 "general_operand" "=g<")
1403: (not:QI (match_operand:QI 1 "general_operand" "g")))]
1404: ""
1405: "comb %1,%0")
1406:
1407: ;; arithmetic left and right shift operations
1408: ;; on the 32532 we will always use lshd for arithmetic left shifts,
1409: ;; because it is three times faster. Broken programs which
1410: ;; use negative shift counts are probably broken differently
1411: ;; than elsewhere.
1412:
1413: ;; alternative 0 never matches on the 32532
1414: (define_insn "ashlsi3"
1415: [(set (match_operand:SI 0 "general_operand" "=g,g")
1416: (ashift:SI (match_operand:SI 1 "general_operand" "r,0")
1417: (match_operand:SI 2 "general_operand" "I,rmn")))]
1418: ""
1419: "*
1420: { if (TARGET_32532)
1421: return \"lshd %2,%0\";
1422: else
1423: return output_shift_insn (operands);
1424: }")
1425:
1426: (define_insn "ashlhi3"
1427: [(set (match_operand:HI 0 "general_operand" "=g")
1428: (ashift:HI (match_operand:HI 1 "general_operand" "0")
1429: (match_operand:SI 2 "general_operand" "rmn")))]
1430: ""
1431: "*
1432: { if (GET_CODE (operands[2]) == CONST_INT)
1433: {
1434: if (INTVAL (operands[2]) == 1)
1435: return \"addw %0,%0\";
1436: else if (INTVAL (operands[2]) == 2 && !TARGET_32532)
1437: return \"addw %0,%0\;addw %0,%0\";
1438: }
1439: if (TARGET_32532)
1440: return \"lshw %2,%0\";
1441: else
1442: return \"ashw %2,%0\";
1443: }")
1444:
1445: (define_insn "ashlqi3"
1446: [(set (match_operand:QI 0 "general_operand" "=g")
1447: (ashift:QI (match_operand:QI 1 "general_operand" "0")
1448: (match_operand:SI 2 "general_operand" "rmn")))]
1449: ""
1450: "*
1451: { if (GET_CODE (operands[2]) == CONST_INT)
1452: {
1453: if (INTVAL (operands[2]) == 1)
1454: return \"addb %0,%0\";
1455: else if (INTVAL (operands[2]) == 2 && !TARGET_32532)
1456: return \"addb %0,%0\;addb %0,%0\";
1457: }
1458: if (TARGET_32532)
1459: return \"lshb %2,%0\";
1460: else
1461: return \"ashb %2,%0\";
1462: }")
1463:
1464: ;; Arithmetic right shift on the 32k works by negating the shift count.
1465: (define_expand "ashrsi3"
1466: [(set (match_operand:SI 0 "general_operand" "=g")
1467: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g")
1468: (match_operand:SI 2 "general_operand" "g")))]
1469: ""
1470: "
1471: {
1472: if (GET_CODE (operands[2]) != CONST_INT)
1473: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1474: }")
1475:
1476: (define_insn ""
1477: [(set (match_operand:SI 0 "general_operand" "=g")
1478: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1479: (match_operand:SI 2 "immediate_operand" "i")))]
1480: ""
1481: "ashd %$%n2,%0")
1482:
1483: (define_insn ""
1484: [(set (match_operand:SI 0 "general_operand" "=g")
1485: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
1486: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1487: ""
1488: "ashd %2,%0")
1489:
1490: (define_expand "ashrhi3"
1491: [(set (match_operand:HI 0 "general_operand" "=g")
1492: (ashiftrt:HI (match_operand:HI 1 "general_operand" "g")
1493: (match_operand:SI 2 "general_operand" "g")))]
1494: ""
1495: "
1496: {
1497: if (GET_CODE (operands[2]) != CONST_INT)
1498: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1499: }")
1500:
1501: (define_insn ""
1502: [(set (match_operand:HI 0 "general_operand" "=g")
1503: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1504: (match_operand:SI 2 "immediate_operand" "i")))]
1505: ""
1506: "ashw %$%n2,%0")
1507:
1508: (define_insn ""
1509: [(set (match_operand:HI 0 "general_operand" "=g")
1510: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
1511: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1512: ""
1513: "ashw %2,%0")
1514:
1515: (define_expand "ashrqi3"
1516: [(set (match_operand:QI 0 "general_operand" "=g")
1517: (ashiftrt:QI (match_operand:QI 1 "general_operand" "g")
1518: (match_operand:SI 2 "general_operand" "g")))]
1519: ""
1520: "
1521: {
1522: if (GET_CODE (operands[2]) != CONST_INT)
1523: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1524: }")
1525:
1526: (define_insn ""
1527: [(set (match_operand:QI 0 "general_operand" "=g")
1528: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1529: (match_operand:SI 2 "immediate_operand" "i")))]
1530: ""
1531: "ashb %$%n2,%0")
1532:
1533: (define_insn ""
1534: [(set (match_operand:QI 0 "general_operand" "=g")
1535: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
1536: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1537: ""
1538: "ashb %2,%0")
1539:
1540: ;; logical shift instructions
1541:
1542: (define_insn "lshlsi3"
1543: [(set (match_operand:SI 0 "general_operand" "=g")
1544: (lshift:SI (match_operand:SI 1 "general_operand" "0")
1545: (match_operand:SI 2 "general_operand" "rmn")))]
1546: ""
1547: "lshd %2,%0")
1548:
1549: (define_insn "lshlhi3"
1550: [(set (match_operand:HI 0 "general_operand" "=g")
1551: (lshift:HI (match_operand:HI 1 "general_operand" "0")
1552: (match_operand:SI 2 "general_operand" "rmn")))]
1553: ""
1554: "lshw %2,%0")
1555:
1556: (define_insn "lshlqi3"
1557: [(set (match_operand:QI 0 "general_operand" "=g")
1558: (lshift:QI (match_operand:QI 1 "general_operand" "0")
1559: (match_operand:SI 2 "general_operand" "rmn")))]
1560: ""
1561: "lshb %2,%0")
1562:
1563: ;; Logical right shift on the 32k works by negating the shift count.
1564: (define_expand "lshrsi3"
1565: [(set (match_operand:SI 0 "general_operand" "=g")
1566: (lshiftrt:SI (match_operand:SI 1 "general_operand" "g")
1567: (match_operand:SI 2 "general_operand" "g")))]
1568: ""
1569: "
1570: {
1571: if (GET_CODE (operands[2]) != CONST_INT)
1572: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1573: }")
1574:
1575: (define_insn ""
1576: [(set (match_operand:SI 0 "general_operand" "=g")
1577: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1578: (match_operand:SI 2 "immediate_operand" "i")))]
1579: ""
1580: "lshd %$%n2,%0")
1581:
1582: (define_insn ""
1583: [(set (match_operand:SI 0 "general_operand" "=g")
1584: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
1585: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1586: ""
1587: "lshd %2,%0")
1588:
1589: (define_expand "lshrhi3"
1590: [(set (match_operand:HI 0 "general_operand" "=g")
1591: (lshiftrt:HI (match_operand:HI 1 "general_operand" "g")
1592: (match_operand:SI 2 "general_operand" "g")))]
1593: ""
1594: "
1595: {
1596: if (GET_CODE (operands[2]) != CONST_INT)
1597: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1598: }")
1599:
1600: (define_insn ""
1601: [(set (match_operand:HI 0 "general_operand" "=g")
1602: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1603: (match_operand:SI 2 "immediate_operand" "i")))]
1604: ""
1605: "lshw %$%n2,%0")
1606:
1607: (define_insn ""
1608: [(set (match_operand:HI 0 "general_operand" "=g")
1609: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
1610: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1611: ""
1612: "lshw %2,%0")
1613:
1614: (define_expand "lshrqi3"
1615: [(set (match_operand:QI 0 "general_operand" "=g")
1616: (lshiftrt:QI (match_operand:QI 1 "general_operand" "g")
1617: (match_operand:SI 2 "general_operand" "g")))]
1618: ""
1619: "
1620: {
1621: if (GET_CODE (operands[2]) != CONST_INT)
1622: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1623: }")
1624:
1625: (define_insn ""
1626: [(set (match_operand:QI 0 "general_operand" "=g")
1627: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1628: (match_operand:SI 2 "immediate_operand" "i")))]
1629: ""
1630: "lshb %$%n2,%0")
1631:
1632: (define_insn ""
1633: [(set (match_operand:QI 0 "general_operand" "=g")
1634: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
1635: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1636: ""
1637: "lshb %2,%0")
1638:
1639: ;; Rotate instructions
1640:
1641: (define_insn "rotlsi3"
1642: [(set (match_operand:SI 0 "general_operand" "=g")
1643: (rotate:SI (match_operand:SI 1 "general_operand" "0")
1644: (match_operand:SI 2 "general_operand" "rmn")))]
1645: ""
1646: "rotd %2,%0")
1647:
1648: (define_insn "rotlhi3"
1649: [(set (match_operand:HI 0 "general_operand" "=g")
1650: (rotate:HI (match_operand:HI 1 "general_operand" "0")
1651: (match_operand:SI 2 "general_operand" "rmn")))]
1652: ""
1653: "rotw %2,%0")
1654:
1655: (define_insn "rotlqi3"
1656: [(set (match_operand:QI 0 "general_operand" "=g")
1657: (rotate:QI (match_operand:QI 1 "general_operand" "0")
1658: (match_operand:SI 2 "general_operand" "rmn")))]
1659: ""
1660: "rotb %2,%0")
1661:
1662: ;; Right rotate on the 32k works by negating the shift count.
1663: (define_expand "rotrsi3"
1664: [(set (match_operand:SI 0 "general_operand" "=g")
1665: (rotatert:SI (match_operand:SI 1 "general_operand" "g")
1666: (match_operand:SI 2 "general_operand" "g")))]
1667: ""
1668: "
1669: {
1670: if (GET_CODE (operands[2]) != CONST_INT)
1671: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1672: }")
1673:
1674: (define_insn ""
1675: [(set (match_operand:SI 0 "general_operand" "=g")
1676: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1677: (match_operand:SI 2 "immediate_operand" "i")))]
1678: ""
1679: "rotd %$%n2,%0")
1680:
1681: (define_insn ""
1682: [(set (match_operand:SI 0 "general_operand" "=g")
1683: (rotatert:SI (match_operand:SI 1 "general_operand" "0")
1684: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1685: ""
1686: "rotd %2,%0")
1687:
1688: (define_expand "rotrhi3"
1689: [(set (match_operand:HI 0 "general_operand" "=g")
1690: (rotatert:HI (match_operand:HI 1 "general_operand" "g")
1691: (match_operand:SI 2 "general_operand" "g")))]
1692: ""
1693: "
1694: {
1695: if (GET_CODE (operands[2]) != CONST_INT)
1696: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1697: }")
1698:
1699: (define_insn ""
1700: [(set (match_operand:HI 0 "general_operand" "=g")
1701: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1702: (match_operand:SI 2 "immediate_operand" "i")))]
1703: ""
1704: "rotw %$%n2,%0")
1705:
1706: (define_insn ""
1707: [(set (match_operand:HI 0 "general_operand" "=g")
1708: (rotatert:HI (match_operand:HI 1 "general_operand" "0")
1709: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1710: ""
1711: "rotw %2,%0")
1712:
1713: (define_expand "rotrqi3"
1714: [(set (match_operand:QI 0 "general_operand" "=g")
1715: (rotatert:QI (match_operand:QI 1 "general_operand" "g")
1716: (match_operand:SI 2 "general_operand" "g")))]
1717: ""
1718: "
1719: {
1720: if (GET_CODE (operands[2]) != CONST_INT)
1721: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2]));
1722: }")
1723:
1724: (define_insn ""
1725: [(set (match_operand:QI 0 "general_operand" "=g")
1726: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1727: (match_operand:SI 2 "immediate_operand" "i")))]
1728: ""
1729: "rotb %$%n2,%0")
1730:
1731: (define_insn ""
1732: [(set (match_operand:QI 0 "general_operand" "=g")
1733: (rotatert:QI (match_operand:QI 1 "general_operand" "0")
1734: (neg:SI (match_operand:SI 2 "general_operand" "r"))))]
1735: ""
1736: "rotb %2,%0")
1737:
1738: ;;- load or push effective address
1739: ;; These come after the move, add, and multiply patterns
1740: ;; because we don't want pushl $1 turned into pushad 1.
1741:
1742: (define_insn ""
1743: [(set (match_operand:SI 0 "general_operand" "=g<")
1744: (match_operand:QI 1 "address_operand" "p"))]
1745: ""
1746: "*
1747: {
1748: if (REG_P (operands[0])
1749: && GET_CODE (operands[1]) == MULT
1750: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT
1751: && (INTVAL (XEXP (operands[1], 1)) == 2
1752: || INTVAL (XEXP (operands[1], 1)) == 4))
1753: {
1754: rtx xoperands[3];
1755: xoperands[0] = operands[0];
1756: xoperands[1] = XEXP (operands[1], 0);
1757: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1);
1758: return output_shift_insn (xoperands);
1759: }
1760: return \"addr %a1,%0\";
1761: }")
1762:
1763: ;;; Index insns. These are about the same speed as multiply-add counterparts.
1764: ;;; but slower then using power-of-2 shifts if we can use them
1765: ;
1766: ;(define_insn ""
1767: ; [(set (match_operand:SI 0 "register_operand" "=r")
1768: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn")
1769: ; (mult:SI (match_operand:SI 2 "register_operand" "0")
1770: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))]
1771: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8"
1772: ; "indexd %0,%3,%1")
1773: ;
1774: ;(define_insn ""
1775: ; [(set (match_operand:SI 0 "register_operand" "=r")
1776: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0")
1777: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1)))
1778: ; (match_operand:SI 3 "general_operand" "rmn")))]
1779: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8"
1780: ; "indexd %0,%2,%3")
1781:
1782: ;; Set, Clear, and Invert bit
1783:
1784: (define_insn ""
1785: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
1786: (const_int 1)
1787: (match_operand:SI 1 "general_operand" "rmn"))
1788: (const_int 1))]
1789: ""
1790: "sbitd %1,%0")
1791:
1792: (define_insn ""
1793: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g")
1794: (const_int 1)
1795: (match_operand:SI 1 "general_operand" "rmn"))
1796: (const_int 0))]
1797: ""
1798: "cbitd %1,%0")
1799:
1800: (define_insn ""
1801: [(set (match_operand:SI 0 "general_operand" "+g")
1802: (xor:SI (ashift:SI (const_int 1)
1803: (match_operand:SI 1 "general_operand" "rmn"))
1804: (match_dup 0)))]
1805: ""
1806: "ibitd %1,%0")
1807:
1808: (define_insn ""
1809: [(set (match_operand:QI 0 "general_operand" "=g")
1810: (xor:QI (subreg:QI
1811: (ashift:SI (const_int 1)
1812: (match_operand:QI 1 "general_operand" "rmn")) 0)
1813: (match_dup 0)))]
1814: ""
1815: "ibitb %1,%0")
1816:
1817: ;; Recognize jbs and jbc instructions.
1818:
1819: (define_insn ""
1820: [(set (cc0)
1821: (zero_extract (match_operand:SI 0 "general_operand" "rm")
1822: (const_int 1)
1823: (match_operand:SI 1 "general_operand" "g")))]
1824: ""
1825: "*
1826: { cc_status.flags = CC_Z_IN_F;
1827: return \"tbitd %1,%0\";
1828: }")
1829:
1830: ;; extract(base, width, offset)
1831: ;; Signed bitfield extraction is not supported in hardware on the
1832: ;; NS 32032. It is therefore better to let GCC figure out a
1833: ;; good strategy for generating the proper instruction sequence
1834: ;; and represent it as rtl.
1835:
1836: ;; Optimize the case of extracting a byte or word from a register.
1837: ;; Otherwise we must load a register with the offset of the
1838: ;; chunk we want, and perform an extract insn (each of which
1839: ;; is very expensive). Since we use the stack to do our bit-twiddling
1840: ;; we cannot use it for a destination. Perhaps things are fast
1841: ;; enough on the 32532 that such hacks are not needed.
1842:
1843: (define_insn ""
1844: [(set (match_operand:SI 0 "general_operand" "=ro")
1845: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
1846: (match_operand:SI 2 "const_int_operand" "i")
1847: (match_operand:SI 3 "const_int_operand" "i")))]
1848: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
1849: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)"
1850: "*
1851: {
1852: output_asm_insn (\"movd %1,tos\", operands);
1853: if (INTVAL (operands[2]) == 16)
1854: {
1855: if (INTVAL (operands[3]) == 8)
1856: output_asm_insn (\"movzwd 1(sp),%0\", operands);
1857: else
1858: output_asm_insn (\"movzwd 2(sp),%0\", operands);
1859: }
1860: else
1861: {
1862: if (INTVAL (operands[3]) == 8)
1863: output_asm_insn (\"movzbd 1(sp),%0\", operands);
1864: else if (INTVAL (operands[3]) == 16)
1865: output_asm_insn (\"movzbd 2(sp),%0\", operands);
1866: else
1867: output_asm_insn (\"movzbd 3(sp),%0\", operands);
1868: }
1869: if (TARGET_32532 || TARGET_32332)
1870: return \"cmpqd %$0,tos\";
1871: else
1872: return \"adjspb %$-4\";
1873: }")
1874:
1.1.1.3 root 1875: (define_insn ""
1876: [(set (match_operand:SI 0 "general_operand" "=g<")
1877: (zero_extract:SI (match_operand:SI 1 "register_operand" "g")
1878: (match_operand:SI 2 "const_int_operand" "i")
1879: (match_operand:SI 3 "general_operand" "rK")))]
1880: ""
1881: "*
1882: { if (GET_CODE (operands[3]) == CONST_INT)
1883: return \"extsd %1,%0,%3,%2\";
1884: else return \"extd %3,%1,%0,%2\";
1885: }")
1886:
1.1 root 1887: (define_insn "extzv"
1888: [(set (match_operand:SI 0 "general_operand" "=g<")
1889: (zero_extract:SI (match_operand:QI 1 "general_operand" "g")
1890: (match_operand:SI 2 "const_int_operand" "i")
1891: (match_operand:SI 3 "general_operand" "rK")))]
1892: ""
1893: "*
1894: { if (GET_CODE (operands[3]) == CONST_INT)
1895: return \"extsd %1,%0,%3,%2\";
1896: else return \"extd %3,%1,%0,%2\";
1897: }")
1898:
1899: (define_insn ""
1900: [(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o")
1901: (match_operand:SI 1 "const_int_operand" "i")
1902: (match_operand:SI 2 "general_operand" "rn"))
1903: (match_operand:SI 3 "general_operand" "rm"))]
1904: ""
1905: "*
1906: { if (GET_CODE (operands[2]) == CONST_INT)
1907: {
1908: if (INTVAL (operands[2]) >= 8)
1909: {
1910: operands[0] = adj_offsettable_operand (operands[0],
1911: INTVAL (operands[2]) / 8);
1912: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8);
1913: }
1914: if (INTVAL (operands[1]) <= 8)
1915: return \"inssb %3,%0,%2,%1\";
1916: else if (INTVAL (operands[1]) <= 16)
1917: return \"inssw %3,%0,%2,%1\";
1918: else
1919: return \"inssd %3,%0,%2,%1\";
1920: }
1921: return \"insd %2,%3,%0,%1\";
1922: }")
1923:
1924: (define_insn ""
1925: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
1926: (match_operand:SI 1 "const_int_operand" "i")
1927: (match_operand:SI 2 "general_operand" "rK"))
1928: (match_operand:SI 3 "general_operand" "rm"))]
1929: ""
1930: "*
1931: { if (GET_CODE (operands[2]) == CONST_INT)
1932: if (INTVAL (operands[1]) <= 8)
1933: return \"inssb %3,%0,%2,%1\";
1934: else if (INTVAL (operands[1]) <= 16)
1935: return \"inssw %3,%0,%2,%1\";
1936: else
1937: return \"inssd %3,%0,%2,%1\";
1938: return \"insd %2,%3,%0,%1\";
1939: }")
1940:
1941: (define_insn "insv"
1942: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g")
1943: (match_operand:SI 1 "const_int_operand" "i")
1944: (match_operand:SI 2 "general_operand" "rK"))
1945: (match_operand:SI 3 "general_operand" "rm"))]
1946: ""
1947: "*
1948: { if (GET_CODE (operands[2]) == CONST_INT)
1949: if (INTVAL (operands[1]) <= 8)
1950: return \"inssb %3,%0,%2,%1\";
1951: else if (INTVAL (operands[1]) <= 16)
1952: return \"inssw %3,%0,%2,%1\";
1953: else
1954: return \"inssd %3,%0,%2,%1\";
1955: return \"insd %2,%3,%0,%1\";
1956: }")
1957:
1958:
1959: (define_insn "jump"
1960: [(set (pc)
1961: (label_ref (match_operand 0 "" "")))]
1962: ""
1963: "br %l0")
1964:
1965: (define_insn "beq"
1966: [(set (pc)
1967: (if_then_else (eq (cc0)
1968: (const_int 0))
1969: (label_ref (match_operand 0 "" ""))
1970: (pc)))]
1971: ""
1972: "*
1973: { if (cc_prev_status.flags & CC_Z_IN_F)
1974: return \"bfc %l0\";
1975: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1976: return \"bfs %l0\";
1977: else return \"beq %l0\";
1978: }")
1979:
1980: (define_insn "bne"
1981: [(set (pc)
1982: (if_then_else (ne (cc0)
1983: (const_int 0))
1984: (label_ref (match_operand 0 "" ""))
1985: (pc)))]
1986: ""
1987: "*
1988: { if (cc_prev_status.flags & CC_Z_IN_F)
1989: return \"bfs %l0\";
1990: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
1991: return \"bfc %l0\";
1992: else return \"bne %l0\";
1993: }")
1994:
1995: (define_insn "bgt"
1996: [(set (pc)
1997: (if_then_else (gt (cc0)
1998: (const_int 0))
1999: (label_ref (match_operand 0 "" ""))
2000: (pc)))]
2001: ""
2002: "bgt %l0")
2003:
2004: (define_insn "bgtu"
2005: [(set (pc)
2006: (if_then_else (gtu (cc0)
2007: (const_int 0))
2008: (label_ref (match_operand 0 "" ""))
2009: (pc)))]
2010: ""
2011: "bhi %l0")
2012:
2013: (define_insn "blt"
2014: [(set (pc)
2015: (if_then_else (lt (cc0)
2016: (const_int 0))
2017: (label_ref (match_operand 0 "" ""))
2018: (pc)))]
2019: ""
2020: "blt %l0")
2021:
2022: (define_insn "bltu"
2023: [(set (pc)
2024: (if_then_else (ltu (cc0)
2025: (const_int 0))
2026: (label_ref (match_operand 0 "" ""))
2027: (pc)))]
2028: ""
2029: "blo %l0")
2030:
2031: (define_insn "bge"
2032: [(set (pc)
2033: (if_then_else (ge (cc0)
2034: (const_int 0))
2035: (label_ref (match_operand 0 "" ""))
2036: (pc)))]
2037: ""
2038: "bge %l0")
2039:
2040: (define_insn "bgeu"
2041: [(set (pc)
2042: (if_then_else (geu (cc0)
2043: (const_int 0))
2044: (label_ref (match_operand 0 "" ""))
2045: (pc)))]
2046: ""
2047: "bhs %l0")
2048:
2049: (define_insn "ble"
2050: [(set (pc)
2051: (if_then_else (le (cc0)
2052: (const_int 0))
2053: (label_ref (match_operand 0 "" ""))
2054: (pc)))]
2055: ""
2056: "ble %l0")
2057:
2058: (define_insn "bleu"
2059: [(set (pc)
2060: (if_then_else (leu (cc0)
2061: (const_int 0))
2062: (label_ref (match_operand 0 "" ""))
2063: (pc)))]
2064: ""
2065: "bls %l0")
2066:
2067: (define_insn ""
2068: [(set (pc)
2069: (if_then_else (eq (cc0)
2070: (const_int 0))
2071: (pc)
2072: (label_ref (match_operand 0 "" ""))))]
2073: ""
2074: "*
2075: { if (cc_prev_status.flags & CC_Z_IN_F)
2076: return \"bfs %l0\";
2077: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2078: return \"bfc %l0\";
2079: else return \"bne %l0\";
2080: }")
2081:
2082: (define_insn ""
2083: [(set (pc)
2084: (if_then_else (ne (cc0)
2085: (const_int 0))
2086: (pc)
2087: (label_ref (match_operand 0 "" ""))))]
2088: ""
2089: "*
2090: { if (cc_prev_status.flags & CC_Z_IN_F)
2091: return \"bfc %l0\";
2092: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2093: return \"bfs %l0\";
2094: else return \"beq %l0\";
2095: }")
2096:
2097: (define_insn ""
2098: [(set (pc)
2099: (if_then_else (gt (cc0)
2100: (const_int 0))
2101: (pc)
2102: (label_ref (match_operand 0 "" ""))))]
2103: ""
2104: "ble %l0")
2105:
2106: (define_insn ""
2107: [(set (pc)
2108: (if_then_else (gtu (cc0)
2109: (const_int 0))
2110: (pc)
2111: (label_ref (match_operand 0 "" ""))))]
2112: ""
2113: "bls %l0")
2114:
2115: (define_insn ""
2116: [(set (pc)
2117: (if_then_else (lt (cc0)
2118: (const_int 0))
2119: (pc)
2120: (label_ref (match_operand 0 "" ""))))]
2121: ""
2122: "bge %l0")
2123:
2124: (define_insn ""
2125: [(set (pc)
2126: (if_then_else (ltu (cc0)
2127: (const_int 0))
2128: (pc)
2129: (label_ref (match_operand 0 "" ""))))]
2130: ""
2131: "bhs %l0")
2132:
2133: (define_insn ""
2134: [(set (pc)
2135: (if_then_else (ge (cc0)
2136: (const_int 0))
2137: (pc)
2138: (label_ref (match_operand 0 "" ""))))]
2139: ""
2140: "blt %l0")
2141:
2142: (define_insn ""
2143: [(set (pc)
2144: (if_then_else (geu (cc0)
2145: (const_int 0))
2146: (pc)
2147: (label_ref (match_operand 0 "" ""))))]
2148: ""
2149: "blo %l0")
2150:
2151: (define_insn ""
2152: [(set (pc)
2153: (if_then_else (le (cc0)
2154: (const_int 0))
2155: (pc)
2156: (label_ref (match_operand 0 "" ""))))]
2157: ""
2158: "bgt %l0")
2159:
2160: (define_insn ""
2161: [(set (pc)
2162: (if_then_else (leu (cc0)
2163: (const_int 0))
2164: (pc)
2165: (label_ref (match_operand 0 "" ""))))]
2166: ""
2167: "bhi %l0")
2168:
2169: ;; Subtract-and-jump and Add-and-jump insns.
2170: ;; These can actually be used for adding numbers in the range -8 to 7
2171:
2172: (define_insn ""
2173: [(set (pc)
2174: (if_then_else
2175: (ne (match_operand:SI 0 "general_operand" "+g")
2176: (match_operand:SI 1 "const_int_operand" "i"))
2177: (label_ref (match_operand 2 "" ""))
2178: (pc)))
2179: (set (match_dup 0)
2180: (minus:SI (match_dup 0)
2181: (match_dup 1)))]
2182: "INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
2183: "acbd %$%n1,%0,%l2")
2184:
2185: (define_insn ""
2186: [(set (pc)
2187: (if_then_else
2188: (ne (match_operand:SI 0 "general_operand" "+g")
2189: (match_operand:SI 1 "const_int_operand" "i"))
2190: (label_ref (match_operand 2 "" ""))
2191: (pc)))
2192: (set (match_dup 0)
2193: (plus:SI (match_dup 0)
2194: (match_operand:SI 3 "const_int_operand" "i")))]
2195: "INTVAL (operands[1]) == - INTVAL (operands[3])
2196: && INTVAL (operands[3]) >= -8 && INTVAL (operands[3]) < 8"
2197: "acbd %3,%0,%l2")
2198:
2199: (define_insn "call"
2200: [(call (match_operand:QI 0 "memory_operand" "m")
2201: (match_operand:QI 1 "general_operand" "g"))]
2202: ""
2203: "*
2204: {
2205: #ifndef JSR_ALWAYS
2206: if (GET_CODE (operands[0]) == MEM)
2207: {
2208: rtx temp = XEXP (operands[0], 0);
2209: if (CONSTANT_ADDRESS_P (temp))
2210: {
1.1.1.3 root 2211: #ifdef ENCORE_ASM
2212: return \"bsr %?%0\";
2213: #else
2214: #ifdef CALL_MEMREF_IMPLICIT
1.1 root 2215: operands[0] = temp;
2216: return \"bsr %0\";
1.1.1.2 root 2217: #else
1.1 root 2218: #ifdef GNX_V3
2219: return \"bsr %0\";
2220: #else
2221: return \"bsr %?%a0\";
2222: #endif
2223: #endif
1.1.1.3 root 2224: #endif
1.1 root 2225: }
2226: if (GET_CODE (XEXP (operands[0], 0)) == REG)
1.1.1.3 root 2227: #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
1.1 root 2228: return \"jsr %0\";
1.1.1.2 root 2229: #else
1.1 root 2230: return \"jsr %a0\";
2231: #endif
2232: }
2233: #endif /* not JSR_ALWAYS */
2234: return \"jsr %0\";
2235: }")
2236:
2237: (define_insn "call_value"
2238: [(set (match_operand 0 "" "=rf")
2239: (call (match_operand:QI 1 "memory_operand" "m")
2240: (match_operand:QI 2 "general_operand" "g")))]
2241: ""
2242: "*
2243: {
2244: #ifndef JSR_ALWAYS
2245: if (GET_CODE (operands[1]) == MEM)
2246: {
2247: rtx temp = XEXP (operands[1], 0);
2248: if (CONSTANT_ADDRESS_P (temp))
2249: {
1.1.1.3 root 2250: #ifdef ENCORE_ASM
2251: return \"bsr %?%1\";
2252: #else
2253: #ifdef CALL_MEMREF_IMPLICIT
1.1 root 2254: operands[1] = temp;
2255: return \"bsr %1\";
1.1.1.2 root 2256: #else
1.1 root 2257: #ifdef GNX_V3
2258: return \"bsr %1\";
2259: #else
2260: return \"bsr %?%a1\";
2261: #endif
2262: #endif
1.1.1.3 root 2263: #endif
1.1 root 2264: }
2265: if (GET_CODE (XEXP (operands[1], 0)) == REG)
1.1.1.3 root 2266: #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT)
1.1 root 2267: return \"jsr %1\";
1.1.1.2 root 2268: #else
1.1 root 2269: return \"jsr %a1\";
2270: #endif
2271: }
2272: #endif /* not JSR_ALWAYS */
2273: return \"jsr %1\";
2274: }")
2275:
2276: (define_insn "return"
2277: [(return)]
2278: "0"
2279: "ret 0")
2280:
2281: (define_insn "abssf2"
2282: [(set (match_operand:SF 0 "general_operand" "=fm<")
2283: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))]
2284: "TARGET_32081"
2285: "absf %1,%0")
2286:
2287: (define_insn "absdf2"
2288: [(set (match_operand:DF 0 "general_operand" "=fm<")
2289: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
2290: "TARGET_32081"
2291: "absl %1,%0")
2292:
2293: (define_insn "abssi2"
2294: [(set (match_operand:SI 0 "general_operand" "=g<")
2295: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))]
2296: ""
2297: "absd %1,%0")
2298:
2299: (define_insn "abshi2"
2300: [(set (match_operand:HI 0 "general_operand" "=g<")
2301: (abs:HI (match_operand:HI 1 "general_operand" "g")))]
2302: ""
2303: "absw %1,%0")
2304:
2305: (define_insn "absqi2"
2306: [(set (match_operand:QI 0 "general_operand" "=g<")
2307: (abs:QI (match_operand:QI 1 "general_operand" "g")))]
2308: ""
2309: "absb %1,%0")
2310:
2311: (define_insn "nop"
2312: [(const_int 0)]
2313: ""
2314: "nop")
2315:
2316: (define_insn "indirect_jump"
2317: [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2318: ""
2319: "jump %0")
2320:
2321: ;;(define_insn "tablejump"
2322: ;; [(set (pc)
2323: ;; (plus:SI (match_operand:SI 0 "general_operand" "g")
2324: ;; (pc)))]
2325: ;; ""
2326: ;; "cased %0")
2327:
2328: (define_insn "tablejump"
2329: [(set (pc)
2330: (plus:SI (pc) (match_operand:HI 0 "general_operand" "g")))
2331: (use (label_ref (match_operand 1 "" "")))]
2332: ""
2333: "*
2334: {
2335: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
2336: CODE_LABEL_NUMBER (operands[1]));
2337: return \"casew %0\";
2338: }")
2339:
2340: ;;(define_insn ""
2341: ;; [(set (pc)
2342: ;; (plus:SI (match_operand:QI 0 "general_operand" "g")
2343: ;; (pc)))]
2344: ;; ""
2345: ;; "caseb %0")
2346:
2347: ;; Scondi instructions
2348: (define_insn "seq"
2349: [(set (match_operand:SI 0 "general_operand" "=g<")
2350: (eq:SI (cc0) (const_int 0)))]
2351: ""
2352: "*
2353: { if (cc_prev_status.flags & CC_Z_IN_F)
2354: return \"sfcd %0\";
2355: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2356: return \"sfsd %0\";
2357: else return \"seqd %0\";
2358: }")
2359:
2360: (define_insn ""
2361: [(set (match_operand:HI 0 "general_operand" "=g<")
2362: (eq:HI (cc0) (const_int 0)))]
2363: ""
2364: "*
2365: { if (cc_prev_status.flags & CC_Z_IN_F)
2366: return \"sfcw %0\";
2367: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2368: return \"sfsw %0\";
2369: else return \"seqw %0\";
2370: }")
2371:
2372: (define_insn ""
2373: [(set (match_operand:QI 0 "general_operand" "=g<")
2374: (eq:QI (cc0) (const_int 0)))]
2375: ""
2376: "*
2377: { if (cc_prev_status.flags & CC_Z_IN_F)
2378: return \"sfcb %0\";
2379: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2380: return \"sfsb %0\";
2381: else return \"seqb %0\";
2382: }")
2383:
2384: (define_insn "sne"
2385: [(set (match_operand:SI 0 "general_operand" "=g<")
2386: (ne:SI (cc0) (const_int 0)))]
2387: ""
2388: "*
2389: { if (cc_prev_status.flags & CC_Z_IN_F)
2390: return \"sfsd %0\";
2391: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2392: return \"sfcd %0\";
2393: else return \"sned %0\";
2394: }")
2395:
2396: (define_insn ""
2397: [(set (match_operand:HI 0 "general_operand" "=g<")
2398: (ne:HI (cc0) (const_int 0)))]
2399: ""
2400: "*
2401: { if (cc_prev_status.flags & CC_Z_IN_F)
2402: return \"sfsw %0\";
2403: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2404: return \"sfcw %0\";
2405: else return \"snew %0\";
2406: }")
2407:
2408: (define_insn ""
2409: [(set (match_operand:QI 0 "general_operand" "=g<")
2410: (ne:QI (cc0) (const_int 0)))]
2411: ""
2412: "*
2413: { if (cc_prev_status.flags & CC_Z_IN_F)
2414: return \"sfsb %0\";
2415: else if (cc_prev_status.flags & CC_Z_IN_NOT_F)
2416: return \"sfcb %0\";
2417: else return \"sneb %0\";
2418: }")
2419:
2420: (define_insn "sgt"
2421: [(set (match_operand:SI 0 "general_operand" "=g<")
2422: (gt:SI (cc0) (const_int 0)))]
2423: ""
2424: "sgtd %0")
2425:
2426: (define_insn ""
2427: [(set (match_operand:HI 0 "general_operand" "=g<")
2428: (gt:HI (cc0) (const_int 0)))]
2429: ""
2430: "sgtw %0")
2431:
2432: (define_insn ""
2433: [(set (match_operand:QI 0 "general_operand" "=g<")
2434: (gt:QI (cc0) (const_int 0)))]
2435: ""
2436: "sgtb %0")
2437:
2438: (define_insn "sgtu"
2439: [(set (match_operand:SI 0 "general_operand" "=g<")
2440: (gtu:SI (cc0) (const_int 0)))]
2441: ""
2442: "shid %0")
2443:
2444: (define_insn ""
2445: [(set (match_operand:HI 0 "general_operand" "=g<")
2446: (gtu:HI (cc0) (const_int 0)))]
2447: ""
2448: "shiw %0")
2449:
2450: (define_insn ""
2451: [(set (match_operand:QI 0 "general_operand" "=g<")
2452: (gtu:QI (cc0) (const_int 0)))]
2453: ""
2454: "shib %0")
2455:
2456: (define_insn "slt"
2457: [(set (match_operand:SI 0 "general_operand" "=g<")
2458: (lt:SI (cc0) (const_int 0)))]
2459: ""
2460: "sltd %0")
2461:
2462: (define_insn ""
2463: [(set (match_operand:HI 0 "general_operand" "=g<")
2464: (lt:HI (cc0) (const_int 0)))]
2465: ""
2466: "sltw %0")
2467:
2468: (define_insn ""
2469: [(set (match_operand:QI 0 "general_operand" "=g<")
2470: (lt:QI (cc0) (const_int 0)))]
2471: ""
2472: "sltb %0")
2473:
2474: (define_insn "sltu"
2475: [(set (match_operand:SI 0 "general_operand" "=g<")
2476: (ltu:SI (cc0) (const_int 0)))]
2477: ""
2478: "slod %0")
2479:
2480: (define_insn ""
2481: [(set (match_operand:HI 0 "general_operand" "=g<")
2482: (ltu:HI (cc0) (const_int 0)))]
2483: ""
2484: "slow %0")
2485:
2486: (define_insn ""
2487: [(set (match_operand:QI 0 "general_operand" "=g<")
2488: (ltu:QI (cc0) (const_int 0)))]
2489: ""
2490: "slob %0")
2491:
2492: (define_insn "sge"
2493: [(set (match_operand:SI 0 "general_operand" "=g<")
2494: (ge:SI (cc0) (const_int 0)))]
2495: ""
2496: "sged %0")
2497:
2498: (define_insn ""
2499: [(set (match_operand:HI 0 "general_operand" "=g<")
2500: (ge:HI (cc0) (const_int 0)))]
2501: ""
2502: "sgew %0")
2503:
2504: (define_insn ""
2505: [(set (match_operand:QI 0 "general_operand" "=g<")
2506: (ge:QI (cc0) (const_int 0)))]
2507: ""
2508: "sgeb %0")
2509:
2510: (define_insn "sgeu"
2511: [(set (match_operand:SI 0 "general_operand" "=g<")
2512: (geu:SI (cc0) (const_int 0)))]
2513: ""
2514: "shsd %0")
2515:
2516: (define_insn ""
2517: [(set (match_operand:HI 0 "general_operand" "=g<")
2518: (geu:HI (cc0) (const_int 0)))]
2519: ""
2520: "shsw %0")
2521:
2522: (define_insn ""
2523: [(set (match_operand:QI 0 "general_operand" "=g<")
2524: (geu:QI (cc0) (const_int 0)))]
2525: ""
2526: "shsb %0")
2527:
2528: (define_insn "sle"
2529: [(set (match_operand:SI 0 "general_operand" "=g<")
2530: (le:SI (cc0) (const_int 0)))]
2531: ""
2532: "sled %0")
2533:
2534: (define_insn ""
2535: [(set (match_operand:HI 0 "general_operand" "=g<")
2536: (le:HI (cc0) (const_int 0)))]
2537: ""
2538: "slew %0")
2539:
2540: (define_insn ""
2541: [(set (match_operand:QI 0 "general_operand" "=g<")
2542: (le:QI (cc0) (const_int 0)))]
2543: ""
2544: "sleb %0")
2545:
2546: (define_insn "sleu"
2547: [(set (match_operand:SI 0 "general_operand" "=g<")
2548: (leu:SI (cc0) (const_int 0)))]
2549: ""
2550: "slsd %0")
2551:
2552: (define_insn ""
2553: [(set (match_operand:HI 0 "general_operand" "=g<")
2554: (leu:HI (cc0) (const_int 0)))]
2555: ""
2556: "slsw %0")
2557:
2558: (define_insn ""
2559: [(set (match_operand:QI 0 "general_operand" "=g<")
2560: (leu:QI (cc0) (const_int 0)))]
2561: ""
2562: "slsb %0")
2563:
2564: ;;- Local variables:
2565: ;;- mode:emacs-lisp
2566: ;;- comment-start: ";;- "
2567: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2568: ;;- eval: (modify-syntax-entry ?[ "(]")
2569: ;;- eval: (modify-syntax-entry ?] ")[")
2570: ;;- eval: (modify-syntax-entry ?{ "(}")
2571: ;;- eval: (modify-syntax-entry ?} "){")
2572: ;;- End:
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