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1.1.1.3 ! root 1: ;;- Machine description for GNU compiler, ns32000 Version ! 2: ;; Copyright (C) 1988, 1994 Free Software Foundation, Inc. ! 3: ;; Contributed by Michael Tiemann ([email protected]) 1.1 root 4: 5: ;; This file is part of GNU CC. 6: 7: ;; GNU CC is free software; you can redistribute it and/or modify 8: ;; it under the terms of the GNU General Public License as published by 9: ;; the Free Software Foundation; either version 2, or (at your option) 10: ;; any later version. 11: 12: ;; GNU CC is distributed in the hope that it will be useful, 13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15: ;; GNU General Public License for more details. 16: 17: ;; You should have received a copy of the GNU General Public License 18: ;; along with GNU CC; see the file COPYING. If not, write to 19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. 20: 21: 1.1.1.3 ! root 22: ; BUGS: ! 23: ;; Insert no-op between an insn with memory read-write operands ! 24: ;; following by a scale-indexing operation. ! 25: ;; The Sequent assembler does not allow addresses to be used ! 26: ;; except in insns which explicitly compute an effective address. ! 27: ;; I.e., one cannot say "cmpd _p,@_x" ! 28: ;; Implement unsigned multiplication?? ! 29: 1.1 root 30: ;;- Instruction patterns. When multiple patterns apply, 31: ;;- the first one in the file is chosen. 32: ;;- 33: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 34: ;;- 35: ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code 36: ;;- updates for most instructions. 37: 38: ;; We don't want to allow a constant operand for test insns because 39: ;; (set (cc0) (const_int foo)) has no mode information. Such insns will 40: ;; be folded while optimizing anyway. 41: 42: (define_insn "tstsi" 43: [(set (cc0) 44: (match_operand:SI 0 "nonimmediate_operand" "rm"))] 45: "" 46: "* 47: { cc_status.flags |= CC_REVERSED; 48: operands[1] = const0_rtx; 49: return \"cmpqd %1,%0\"; }") 50: 51: (define_insn "tsthi" 52: [(set (cc0) 53: (match_operand:HI 0 "nonimmediate_operand" "g"))] 54: "" 55: "* 56: { cc_status.flags |= CC_REVERSED; 57: operands[1] = const0_rtx; 58: return \"cmpqw %1,%0\"; }") 59: 60: (define_insn "tstqi" 61: [(set (cc0) 62: (match_operand:QI 0 "nonimmediate_operand" "g"))] 63: "" 64: "* 65: { cc_status.flags |= CC_REVERSED; 66: operands[1] = const0_rtx; 67: return \"cmpqb %1,%0\"; }") 68: 69: (define_insn "tstdf" 70: [(set (cc0) 71: (match_operand:DF 0 "general_operand" "fmF"))] 72: "TARGET_32081" 73: "* 74: { cc_status.flags |= CC_REVERSED; 75: operands[1] = CONST0_RTX (DFmode); 76: return \"cmpl %1,%0\"; }") 77: 78: (define_insn "tstsf" 79: [(set (cc0) 80: (match_operand:SF 0 "general_operand" "fmF"))] 81: "TARGET_32081" 82: "* 83: { cc_status.flags |= CC_REVERSED; 84: operands[1] = CONST0_RTX (SFmode); 85: return \"cmpf %1,%0\"; }") 86: 87: (define_insn "cmpsi" 88: [(set (cc0) 89: (compare (match_operand:SI 0 "nonimmediate_operand" "rmn") 90: (match_operand:SI 1 "general_operand" "rmn")))] 91: "" 92: "* 93: { 94: if (GET_CODE (operands[1]) == CONST_INT) 95: { 96: int i = INTVAL (operands[1]); 97: if (i <= 7 && i >= -8) 98: { 99: cc_status.flags |= CC_REVERSED; 100: return \"cmpqd %1,%0\"; 101: } 102: } 103: cc_status.flags &= ~CC_REVERSED; 104: if (GET_CODE (operands[0]) == CONST_INT) 105: { 106: int i = INTVAL (operands[0]); 107: if (i <= 7 && i >= -8) 108: return \"cmpqd %0,%1\"; 109: } 110: return \"cmpd %0,%1\"; 111: }") 112: 113: (define_insn "cmphi" 114: [(set (cc0) 115: (compare (match_operand:HI 0 "nonimmediate_operand" "g") 116: (match_operand:HI 1 "general_operand" "g")))] 117: "" 118: "* 119: { 120: if (GET_CODE (operands[1]) == CONST_INT) 121: { 122: short i = INTVAL (operands[1]); 123: if (i <= 7 && i >= -8) 124: { 125: cc_status.flags |= CC_REVERSED; 126: if (INTVAL (operands[1]) > 7) 127: operands[1] = gen_rtx(CONST_INT, VOIDmode, i); 128: return \"cmpqw %1,%0\"; 129: } 130: } 131: cc_status.flags &= ~CC_REVERSED; 132: if (GET_CODE (operands[0]) == CONST_INT) 133: { 134: short i = INTVAL (operands[0]); 135: if (i <= 7 && i >= -8) 136: { 137: if (INTVAL (operands[0]) > 7) 138: operands[0] = gen_rtx(CONST_INT, VOIDmode, i); 139: return \"cmpqw %0,%1\"; 140: } 141: } 142: return \"cmpw %0,%1\"; 143: }") 144: 145: (define_insn "cmpqi" 146: [(set (cc0) 147: (compare (match_operand:QI 0 "nonimmediate_operand" "g") 148: (match_operand:QI 1 "general_operand" "g")))] 149: "" 150: "* 151: { 152: if (GET_CODE (operands[1]) == CONST_INT) 153: { 154: char i = INTVAL (operands[1]); 155: if (i <= 7 && i >= -8) 156: { 157: cc_status.flags |= CC_REVERSED; 158: if (INTVAL (operands[1]) > 7) 159: operands[1] = gen_rtx(CONST_INT, VOIDmode, i); 160: return \"cmpqb %1,%0\"; 161: } 162: } 163: cc_status.flags &= ~CC_REVERSED; 164: if (GET_CODE (operands[0]) == CONST_INT) 165: { 166: char i = INTVAL (operands[0]); 167: if (i <= 7 && i >= -8) 168: { 169: if (INTVAL (operands[0]) > 7) 170: operands[0] = gen_rtx(CONST_INT, VOIDmode, i); 171: return \"cmpqb %0,%1\"; 172: } 173: } 174: return \"cmpb %0,%1\"; 175: }") 176: 177: (define_insn "cmpdf" 178: [(set (cc0) 179: (compare (match_operand:DF 0 "general_operand" "fmF") 180: (match_operand:DF 1 "general_operand" "fmF")))] 181: "TARGET_32081" 182: "cmpl %0,%1") 183: 184: (define_insn "cmpsf" 185: [(set (cc0) 186: (compare (match_operand:SF 0 "general_operand" "fmF") 187: (match_operand:SF 1 "general_operand" "fmF")))] 188: "TARGET_32081" 189: "cmpf %0,%1") 190: 191: (define_insn "movdf" 1.1.1.2 root 192: [(set (match_operand:DF 0 "general_operand" "=fg<") 1.1 root 193: (match_operand:DF 1 "general_operand" "fFg"))] 194: "" 195: "* 196: { 197: if (FP_REG_P (operands[0])) 198: { 199: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE) 200: return \"movl %1,%0\"; 201: if (REG_P (operands[1])) 202: { 203: rtx xoperands[2]; 204: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 205: output_asm_insn (\"movd %1,tos\", xoperands); 206: output_asm_insn (\"movd %1,tos\", operands); 207: return \"movl tos,%0\"; 208: } 209: return \"movl %1,%0\"; 210: } 211: else if (FP_REG_P (operands[1])) 212: { 213: if (REG_P (operands[0])) 214: { 215: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands); 216: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 217: return \"movd tos,%0\"; 218: } 219: else 220: return \"movl %1,%0\"; 221: } 222: return output_move_double (operands); 223: }") 224: 225: (define_insn "movsf" 226: [(set (match_operand:SF 0 "general_operand" "=fg<") 227: (match_operand:SF 1 "general_operand" "fFg"))] 228: "" 229: "* 230: { 231: if (FP_REG_P (operands[0])) 232: { 233: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) 234: return \"movd %1,tos\;movf tos,%0\"; 235: else 236: return \"movf %1,%0\"; 237: } 238: else if (FP_REG_P (operands[1])) 239: { 240: if (REG_P (operands[0])) 241: return \"movf %1,tos\;movd tos,%0\"; 242: return \"movf %1,%0\"; 243: } 244: #if 0 /* Someone suggested this for the Sequent. Is it needed? */ 245: else if (GET_CODE (operands[1]) == CONST_DOUBLE) 246: return \"movf %1,%0\"; 247: #endif 248: /* There was a #if 0 around this, but that was erroneous 249: for many machines -- rms. */ 250: #ifndef MOVD_FLOAT_OK 251: /* GAS understands floating constants in ordinary movd instructions 252: but other assemblers might object. */ 253: else if (GET_CODE (operands[1]) == CONST_DOUBLE) 254: { 255: union {int i[2]; float f; double d;} convrt; 256: convrt.i[0] = CONST_DOUBLE_LOW (operands[1]); 257: convrt.i[1] = CONST_DOUBLE_HIGH (operands[1]); 258: convrt.f = convrt.d; 259: 260: /* Is there a better machine-independent way to to this? */ 261: operands[1] = gen_rtx (CONST_INT, VOIDmode, convrt.i[0]); 262: return \"movd %1,%0\"; 263: } 264: #endif 265: else return \"movd %1,%0\"; 266: }") 267: 268: (define_insn "" 269: [(set (match_operand:TI 0 "memory_operand" "=m") 270: (match_operand:TI 1 "memory_operand" "m"))] 271: "" 272: "movmd %1,%0,4") 273: 274: (define_insn "movdi" 1.1.1.2 root 275: [(set (match_operand:DI 0 "general_operand" "=g<,*f,g") 1.1 root 276: (match_operand:DI 1 "general_operand" "gF,g,*f"))] 277: "" 278: "* 279: { 280: if (FP_REG_P (operands[0])) 281: { 282: if (FP_REG_P (operands[1]) || GET_CODE (operands[1]) == CONST_DOUBLE) 283: return \"movl %1,%0\"; 284: if (REG_P (operands[1])) 285: { 286: rtx xoperands[2]; 287: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1); 288: output_asm_insn (\"movd %1,tos\", xoperands); 289: output_asm_insn (\"movd %1,tos\", operands); 290: return \"movl tos,%0\"; 291: } 292: return \"movl %1,%0\"; 293: } 294: else if (FP_REG_P (operands[1])) 295: { 296: if (REG_P (operands[0])) 297: { 298: output_asm_insn (\"movl %1,tos\;movd tos,%0\", operands); 299: operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 300: return \"movd tos,%0\"; 301: } 302: else 303: return \"movl %1,%0\"; 304: } 305: return output_move_double (operands); 306: }") 307: 308: ;; This special case must precede movsi. 309: (define_insn "" 310: [(set (reg:SI 17) 311: (match_operand:SI 0 "general_operand" "rmn"))] 312: "" 313: "lprd sp,%0") 314: 315: (define_insn "movsi" 1.1.1.2 root 316: [(set (match_operand:SI 0 "general_operand" "=g<,g<,*f,g,x") 317: (match_operand:SI 1 "general_operand" "g,?xy,g,*f,rmn"))] 1.1 root 318: "" 319: "* 320: { 1.1.1.3 ! root 321: extern int flag_pic; \ ! 322: 1.1 root 323: if (FP_REG_P (operands[0])) 324: { 325: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) 326: return \"movd %1,tos\;movf tos,%0\"; 327: else 328: return \"movf %1,%0\"; 329: } 330: else if (FP_REG_P (operands[1])) 331: { 332: if (REG_P (operands[0])) 333: return \"movf %1,tos\;movd tos,%0\"; 334: return \"movf %1,%0\"; 335: } 1.1.1.2 root 336: if (GET_CODE (operands[0]) == REG 337: && REGNO (operands[0]) == FRAME_POINTER_REGNUM) 338: return \"lprd fp,%1\"; 339: if (GET_CODE (operands[1]) == CONST_DOUBLE) 340: operands[1] 341: = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[1])); 1.1 root 342: if (GET_CODE (operands[1]) == CONST_INT) 343: { 344: int i = INTVAL (operands[1]); 1.1.1.3 ! root 345: if (! TARGET_32532) ! 346: { ! 347: if (i <= 7 && i >= -8) ! 348: return \"movqd %1,%0\"; ! 349: if (i <= 0x1fffffff && i >= -0x20000000) 1.1 root 350: #if defined (GNX_V3) || defined (UTEK_ASM) 1.1.1.3 ! root 351: return \"addr %c1,%0\"; 1.1 root 352: #else 1.1.1.3 ! root 353: return \"addr @%c1,%0\"; 1.1 root 354: #endif 1.1.1.3 ! root 355: return \"movd %$%1,%0\"; ! 356: } ! 357: else ! 358: return output_move_dconst(i, \"%$%1,%0\"); ! 359: } ! 360: else if (GET_CODE (operands[1]) == CONST && ! flag_pic) ! 361: { ! 362: /* Must contain symbols so we don`t know how big it is. In ! 363: * that case addr might lead to overflow. For PIC symbolic ! 364: * address loads always have to be done with addr. ! 365: */ ! 366: return \"movd %$%1,%0\"; 1.1 root 367: } 368: else if (GET_CODE (operands[1]) == REG) 369: { 370: if (REGNO (operands[1]) < 16) 371: return \"movd %1,%0\"; 372: else if (REGNO (operands[1]) == FRAME_POINTER_REGNUM) 373: { 374: if (GET_CODE(operands[0]) == REG) 375: return \"sprd fp,%0\"; 376: else 377: return \"addr 0(fp),%0\" ; 378: } 379: else if (REGNO (operands[1]) == STACK_POINTER_REGNUM) 380: { 381: if (GET_CODE(operands[0]) == REG) 382: return \"sprd sp,%0\"; 383: else 384: return \"addr 0(sp),%0\" ; 385: } 386: else abort (); 387: } 388: else if (GET_CODE (operands[1]) == MEM) 389: return \"movd %1,%0\"; 1.1.1.3 ! root 390: 1.1 root 391: /* Check if this effective address can be 392: calculated faster by pulling it apart. */ 393: if (REG_P (operands[0]) 394: && GET_CODE (operands[1]) == MULT 395: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT 396: && (INTVAL (XEXP (operands[1], 1)) == 2 397: || INTVAL (XEXP (operands[1], 1)) == 4)) 398: { 399: rtx xoperands[3]; 400: xoperands[0] = operands[0]; 401: xoperands[1] = XEXP (operands[1], 0); 402: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1); 403: return output_shift_insn (xoperands); 404: } 405: return \"addr %a1,%0\"; 406: }") 407: 408: (define_insn "movhi" 409: [(set (match_operand:HI 0 "general_operand" "=g<,*f,g") 410: (match_operand:HI 1 "general_operand" "g,g,*f"))] 411: "" 412: "* 413: { 414: if (GET_CODE (operands[1]) == CONST_INT) 415: { 416: short i = INTVAL (operands[1]); 417: if (i <= 7 && i >= -8) 418: { 419: if (INTVAL (operands[1]) > 7) 420: operands[1] = 421: gen_rtx (CONST_INT, VOIDmode, i); 422: return \"movqw %1,%0\"; 423: } 424: return \"movw %1,%0\"; 425: } 426: else if (FP_REG_P (operands[0])) 427: { 428: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) 429: return \"movwf %1,tos\;movf tos,%0\"; 430: else 431: return \"movwf %1,%0\"; 432: } 433: else if (FP_REG_P (operands[1])) 434: { 435: if (REG_P (operands[0])) 436: return \"movf %1,tos\;movd tos,%0\"; 437: return \"movf %1,%0\"; 438: } 439: else 440: return \"movw %1,%0\"; 441: }") 442: 443: (define_insn "movstricthi" 444: [(set (strict_low_part (match_operand:HI 0 "general_operand" "+r")) 445: (match_operand:HI 1 "general_operand" "g"))] 446: "" 447: "* 448: { 449: if (GET_CODE (operands[1]) == CONST_INT 450: && INTVAL(operands[1]) <= 7 && INTVAL(operands[1]) >= -8) 451: return \"movqw %1,%0\"; 452: return \"movw %1,%0\"; 453: }") 454: 455: (define_insn "movqi" 456: [(set (match_operand:QI 0 "general_operand" "=g<,*f,g") 457: (match_operand:QI 1 "general_operand" "g,g,*f"))] 458: "" 459: "* 460: { if (GET_CODE (operands[1]) == CONST_INT) 461: { 462: char char_val = (char)INTVAL (operands[1]); 463: if (char_val <= 7 && char_val >= -8) 464: { 465: if (INTVAL (operands[1]) > 7) 466: operands[1] = 467: gen_rtx (CONST_INT, VOIDmode, char_val); 468: return \"movqb %1,%0\"; 469: } 470: return \"movb %1,%0\"; 471: } 472: else if (FP_REG_P (operands[0])) 473: { 474: if (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 8) 475: return \"movbf %1,tos\;movf tos,%0\"; 476: else 477: return \"movbf %1,%0\"; 478: } 479: else if (FP_REG_P (operands[1])) 480: { 481: if (REG_P (operands[0])) 482: return \"movf %1,tos\;movd tos,%0\"; 483: return \"movf %1,%0\"; 484: } 485: else 486: return \"movb %1,%0\"; 487: }") 488: 489: (define_insn "movstrictqi" 490: [(set (strict_low_part (match_operand:QI 0 "general_operand" "+r")) 491: (match_operand:QI 1 "general_operand" "g"))] 492: "" 493: "* 494: { 495: if (GET_CODE (operands[1]) == CONST_INT 496: && INTVAL(operands[1]) < 8 && INTVAL(operands[1]) > -9) 497: return \"movqb %1,%0\"; 498: return \"movb %1,%0\"; 499: }") 500: 501: ;; This is here to accept 4 arguments and pass the first 3 along 502: ;; to the movstrsi1 pattern that really does the work. 503: (define_expand "movstrsi" 504: [(set (match_operand:BLK 0 "general_operand" "=g") 505: (match_operand:BLK 1 "general_operand" "g")) 506: (use (match_operand:SI 2 "general_operand" "rmn")) 507: (match_operand 3 "" "")] 508: "" 509: " 510: emit_insn (gen_movstrsi1 (operands[0], operands[1], operands[2])); 511: DONE; 512: ") 513: 514: ;; The definition of this insn does not really explain what it does, 515: ;; but it should suffice 516: ;; that anything generated as this insn will be recognized as one 517: ;; and that it won't successfully combine with anything. 518: (define_insn "movstrsi1" 519: [(set (match_operand:BLK 0 "general_operand" "=g") 520: (match_operand:BLK 1 "general_operand" "g")) 521: (use (match_operand:SI 2 "general_operand" "rmn")) 522: (clobber (reg:SI 0)) 523: (clobber (reg:SI 1)) 524: (clobber (reg:SI 2))] 525: "" 526: "* 527: { 528: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM) 529: abort (); 530: operands[0] = XEXP (operands[0], 0); 531: operands[1] = XEXP (operands[1], 0); 532: if (GET_CODE (operands[0]) == MEM) 533: if (GET_CODE (operands[1]) == MEM) 534: output_asm_insn (\"movd %0,r2\;movd %1,r1\", operands); 535: else 536: output_asm_insn (\"movd %0,r2\;addr %a1,r1\", operands); 537: else if (GET_CODE (operands[1]) == MEM) 538: output_asm_insn (\"addr %a0,r2\;movd %1,r1\", operands); 539: else 540: output_asm_insn (\"addr %a0,r2\;addr %a1,r1\", operands); 541: 542: #ifdef UTEK_ASM 543: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0) 544: { 545: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2); 546: if ((unsigned) INTVAL (operands[2]) <= 7) 547: return \"movqd %2,r0\;movsd $0\"; 548: else 549: return \"movd %2,r0\;movsd $0\"; 550: } 551: else 552: { 553: return \"movd %2,r0\;movsb $0\"; 554: } 555: #else 556: if (GET_CODE (operands[2]) == CONST_INT && (INTVAL (operands[2]) & 0x3) == 0) 557: { 558: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) >> 2); 559: if ((unsigned) INTVAL (operands[2]) <= 7) 560: return \"movqd %2,r0\;movsd\"; 561: else 562: return \"movd %2,r0\;movsd\"; 563: } 564: else 565: { 566: return \"movd %2,r0\;movsb\"; 567: } 568: #endif 569: }") 570: 571: ;; Extension and truncation insns. 572: ;; Those for integer source operand 573: ;; are ordered widest source type first. 574: 575: (define_insn "truncsiqi2" 576: [(set (match_operand:QI 0 "general_operand" "=g<") 577: (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "rmn")))] 578: "" 579: "movb %1,%0") 580: 581: (define_insn "truncsihi2" 582: [(set (match_operand:HI 0 "general_operand" "=g<") 583: (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "rmn")))] 584: "" 585: "movw %1,%0") 586: 587: (define_insn "trunchiqi2" 588: [(set (match_operand:QI 0 "general_operand" "=g<") 589: (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))] 590: "" 591: "movb %1,%0") 592: 593: (define_insn "extendhisi2" 594: [(set (match_operand:SI 0 "general_operand" "=g<") 595: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))] 596: "" 597: "movxwd %1,%0") 598: 599: (define_insn "extendqihi2" 600: [(set (match_operand:HI 0 "general_operand" "=g<") 601: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))] 602: "" 603: "movxbw %1,%0") 604: 605: (define_insn "extendqisi2" 606: [(set (match_operand:SI 0 "general_operand" "=g<") 607: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))] 608: "" 609: "movxbd %1,%0") 610: 611: (define_insn "extendsfdf2" 612: [(set (match_operand:DF 0 "general_operand" "=fm<") 613: (float_extend:DF (match_operand:SF 1 "general_operand" "fmF")))] 614: "TARGET_32081" 615: "movfl %1,%0") 616: 617: (define_insn "truncdfsf2" 618: [(set (match_operand:SF 0 "general_operand" "=fm<") 619: (float_truncate:SF (match_operand:DF 1 "general_operand" "fmF")))] 620: "TARGET_32081" 621: "movlf %1,%0") 622: 623: (define_insn "zero_extendhisi2" 624: [(set (match_operand:SI 0 "general_operand" "=g<") 625: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))] 626: "" 627: "movzwd %1,%0") 628: 629: (define_insn "zero_extendqihi2" 630: [(set (match_operand:HI 0 "general_operand" "=g<") 631: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))] 632: "" 633: "movzbw %1,%0") 634: 635: (define_insn "zero_extendqisi2" 636: [(set (match_operand:SI 0 "general_operand" "=g<") 637: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))] 638: "" 639: "movzbd %1,%0") 640: 641: ;; Fix-to-float conversion insns. 642: ;; Note that the ones that start with SImode come first. 643: ;; That is so that an operand that is a CONST_INT 644: ;; (and therefore lacks a specific machine mode). 645: ;; will be recognized as SImode (which is always valid) 646: ;; rather than as QImode or HImode. 647: 648: ;; Rumor has it that the National part does not correctly convert 649: ;; constant ints to floats. This conversion is therefore disabled. 650: ;; A register must be used to perform the conversion. 651: 652: (define_insn "floatsisf2" 653: [(set (match_operand:SF 0 "general_operand" "=fm<") 654: (float:SF (match_operand:SI 1 "general_operand" "rm")))] 655: "TARGET_32081" 656: "movdf %1,%0") 657: 658: (define_insn "floatsidf2" 659: [(set (match_operand:DF 0 "general_operand" "=fm<") 660: (float:DF (match_operand:SI 1 "general_operand" "rm")))] 661: "TARGET_32081" 662: "movdl %1,%0") 663: 664: (define_insn "floathisf2" 665: [(set (match_operand:SF 0 "general_operand" "=fm<") 666: (float:SF (match_operand:HI 1 "general_operand" "rm")))] 667: "TARGET_32081" 668: "movwf %1,%0") 669: 670: (define_insn "floathidf2" 671: [(set (match_operand:DF 0 "general_operand" "=fm<") 672: (float:DF (match_operand:HI 1 "general_operand" "rm")))] 673: "TARGET_32081" 674: "movwl %1,%0") 675: 676: (define_insn "floatqisf2" 677: [(set (match_operand:SF 0 "general_operand" "=fm<") 678: (float:SF (match_operand:QI 1 "general_operand" "rm")))] 679: "TARGET_32081" 680: "movbf %1,%0") 681: 682: ; Some assemblers warn that this insn doesn't work. 683: ; Maybe they know something we don't. 684: ;(define_insn "floatqidf2" 685: ; [(set (match_operand:DF 0 "general_operand" "=fm<") 686: ; (float:DF (match_operand:QI 1 "general_operand" "rm")))] 687: ; "TARGET_32081" 688: ; "movbl %1,%0") 689: 690: ;; Float-to-fix conversion insns. 691: ;; The sequent compiler always generates "trunc" insns. 692: 693: (define_insn "fixsfqi2" 694: [(set (match_operand:QI 0 "general_operand" "=g<") 695: (fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] 696: "TARGET_32081" 697: "truncfb %1,%0") 698: 699: (define_insn "fixsfhi2" 700: [(set (match_operand:HI 0 "general_operand" "=g<") 701: (fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] 702: "TARGET_32081" 703: "truncfw %1,%0") 704: 705: (define_insn "fixsfsi2" 706: [(set (match_operand:SI 0 "general_operand" "=g<") 707: (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] 708: "TARGET_32081" 709: "truncfd %1,%0") 710: 711: (define_insn "fixdfqi2" 712: [(set (match_operand:QI 0 "general_operand" "=g<") 713: (fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] 714: "TARGET_32081" 715: "trunclb %1,%0") 716: 717: (define_insn "fixdfhi2" 718: [(set (match_operand:HI 0 "general_operand" "=g<") 719: (fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] 720: "TARGET_32081" 721: "trunclw %1,%0") 722: 723: (define_insn "fixdfsi2" 724: [(set (match_operand:SI 0 "general_operand" "=g<") 725: (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] 726: "TARGET_32081" 727: "truncld %1,%0") 728: 729: ;; Unsigned 730: 731: (define_insn "fixunssfqi2" 732: [(set (match_operand:QI 0 "general_operand" "=g<") 733: (unsigned_fix:QI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] 734: "TARGET_32081" 735: "truncfb %1,%0") 736: 737: (define_insn "fixunssfhi2" 738: [(set (match_operand:HI 0 "general_operand" "=g<") 739: (unsigned_fix:HI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] 740: "TARGET_32081" 741: "truncfw %1,%0") 742: 743: (define_insn "fixunssfsi2" 744: [(set (match_operand:SI 0 "general_operand" "=g<") 745: (unsigned_fix:SI (fix:SF (match_operand:SF 1 "general_operand" "fm"))))] 746: "TARGET_32081" 747: "truncfd %1,%0") 748: 749: (define_insn "fixunsdfqi2" 750: [(set (match_operand:QI 0 "general_operand" "=g<") 751: (unsigned_fix:QI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] 752: "TARGET_32081" 753: "trunclb %1,%0") 754: 755: (define_insn "fixunsdfhi2" 756: [(set (match_operand:HI 0 "general_operand" "=g<") 757: (unsigned_fix:HI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] 758: "TARGET_32081" 759: "trunclw %1,%0") 760: 761: (define_insn "fixunsdfsi2" 762: [(set (match_operand:SI 0 "general_operand" "=g<") 763: (unsigned_fix:SI (fix:DF (match_operand:DF 1 "general_operand" "fm"))))] 764: "TARGET_32081" 765: "truncld %1,%0") 766: 767: ;;; These are not yet used by GCC 768: (define_insn "fix_truncsfqi2" 769: [(set (match_operand:QI 0 "general_operand" "=g<") 770: (fix:QI (match_operand:SF 1 "general_operand" "fm")))] 771: "TARGET_32081" 772: "truncfb %1,%0") 773: 774: (define_insn "fix_truncsfhi2" 775: [(set (match_operand:HI 0 "general_operand" "=g<") 776: (fix:HI (match_operand:SF 1 "general_operand" "fm")))] 777: "TARGET_32081" 778: "truncfw %1,%0") 779: 780: (define_insn "fix_truncsfsi2" 781: [(set (match_operand:SI 0 "general_operand" "=g<") 782: (fix:SI (match_operand:SF 1 "general_operand" "fm")))] 783: "TARGET_32081" 784: "truncfd %1,%0") 785: 786: (define_insn "fix_truncdfqi2" 787: [(set (match_operand:QI 0 "general_operand" "=g<") 788: (fix:QI (match_operand:DF 1 "general_operand" "fm")))] 789: "TARGET_32081" 790: "trunclb %1,%0") 791: 792: (define_insn "fix_truncdfhi2" 793: [(set (match_operand:HI 0 "general_operand" "=g<") 794: (fix:HI (match_operand:DF 1 "general_operand" "fm")))] 795: "TARGET_32081" 796: "trunclw %1,%0") 797: 798: (define_insn "fix_truncdfsi2" 799: [(set (match_operand:SI 0 "general_operand" "=g<") 800: (fix:SI (match_operand:DF 1 "general_operand" "fm")))] 801: "TARGET_32081" 802: "truncld %1,%0") 803: 804: ;;- All kinds of add instructions. 805: 806: (define_insn "adddf3" 807: [(set (match_operand:DF 0 "general_operand" "=fm") 808: (plus:DF (match_operand:DF 1 "general_operand" "%0") 809: (match_operand:DF 2 "general_operand" "fmF")))] 810: "TARGET_32081" 811: "addl %2,%0") 812: 813: 814: (define_insn "addsf3" 815: [(set (match_operand:SF 0 "general_operand" "=fm") 816: (plus:SF (match_operand:SF 1 "general_operand" "%0") 817: (match_operand:SF 2 "general_operand" "fmF")))] 818: "TARGET_32081" 819: "addf %2,%0") 820: 821: (define_insn "" 822: [(set (reg:SI 17) 823: (plus:SI (reg:SI 17) 824: (match_operand:SI 0 "immediate_operand" "i")))] 825: "GET_CODE (operands[0]) == CONST_INT" 826: "* 827: { 828: #ifndef SEQUENT_ADJUST_STACK 829: if (TARGET_32532) 830: if (INTVAL (operands[0]) == 8) 831: return \"cmpd tos,tos\"; 832: if (TARGET_32532 || TARGET_32332) 833: if (INTVAL (operands[0]) == 4) 834: return \"cmpqd %$0,tos\"; 835: #endif 836: if (! TARGET_32532) 837: { 838: if (INTVAL (operands[0]) < 64 && INTVAL (operands[0]) > -64) 839: return \"adjspb %$%n0\"; 840: else if (INTVAL (operands[0]) < 8192 && INTVAL (operands[0]) >= -8192) 841: return \"adjspw %$%n0\"; 842: } 843: return \"adjspd %$%n0\"; 844: }") 845: 846: (define_insn "" 847: [(set (match_operand:SI 0 "general_operand" "=g<") 848: (plus:SI (reg:SI 16) 849: (match_operand:SI 1 "immediate_operand" "i")))] 850: "GET_CODE (operands[1]) == CONST_INT" 851: "addr %c1(fp),%0") 852: 853: (define_insn "" 854: [(set (match_operand:SI 0 "general_operand" "=g<") 855: (plus:SI (reg:SI 17) 856: (match_operand:SI 1 "immediate_operand" "i")))] 857: "GET_CODE (operands[1]) == CONST_INT" 858: "addr %c1(sp),%0") 859: 860: (define_insn "addsi3" 861: [(set (match_operand:SI 0 "general_operand" "=g,=g&<") 862: (plus:SI (match_operand:SI 1 "general_operand" "%0,r") 863: (match_operand:SI 2 "general_operand" "rmn,n")))] 864: "" 865: "* 866: { 867: if (which_alternative == 1) 868: { 869: int i = INTVAL (operands[2]); 870: if (NS32K_DISPLACEMENT_P (i)) 871: return \"addr %c2(%1),%0\"; 872: else 873: return \"movd %1,%0\;addd %2,%0\"; 874: } 875: if (GET_CODE (operands[2]) == CONST_INT) 876: { 877: int i = INTVAL (operands[2]); 878: 879: if (i <= 7 && i >= -8) 880: return \"addqd %2,%0\"; 1.1.1.3 ! root 881: else if (! TARGET_32532 && GET_CODE (operands[0]) == REG ! 882: && i <= 0x1fffffff && i >= -0x20000000) 1.1 root 883: return \"addr %c2(%0),%0\"; 884: } 885: return \"addd %2,%0\"; 886: }") 887: 888: (define_insn "addhi3" 889: [(set (match_operand:HI 0 "general_operand" "=g") 890: (plus:HI (match_operand:HI 1 "general_operand" "%0") 891: (match_operand:HI 2 "general_operand" "g")))] 892: "" 893: "* 894: { if (GET_CODE (operands[2]) == CONST_INT) 895: { 896: int i = INTVAL (operands[2]); 897: if (i <= 7 && i >= -8) 898: return \"addqw %2,%0\"; 899: } 900: return \"addw %2,%0\"; 901: }") 902: 903: (define_insn "" 904: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r")) 905: (plus:HI (match_operand:HI 1 "general_operand" "0") 906: (match_operand:HI 2 "general_operand" "g")))] 907: "" 908: "* 909: { 910: if (GET_CODE (operands[1]) == CONST_INT 911: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8) 1.1.1.2 root 912: return \"addqw %2,%0\"; 913: return \"addw %2,%0\"; 1.1 root 914: }") 915: 916: (define_insn "addqi3" 917: [(set (match_operand:QI 0 "general_operand" "=g") 918: (plus:QI (match_operand:QI 1 "general_operand" "%0") 919: (match_operand:QI 2 "general_operand" "g")))] 920: "" 921: "* 922: { if (GET_CODE (operands[2]) == CONST_INT) 923: { 924: int i = INTVAL (operands[2]); 925: if (i <= 7 && i >= -8) 926: return \"addqb %2,%0\"; 927: } 928: return \"addb %2,%0\"; 929: }") 930: 931: (define_insn "" 932: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r")) 933: (plus:QI (match_operand:QI 1 "general_operand" "0") 934: (match_operand:QI 2 "general_operand" "g")))] 935: "" 936: "* 937: { 938: if (GET_CODE (operands[1]) == CONST_INT 939: && INTVAL (operands[1]) >-9 && INTVAL(operands[1]) < 8) 1.1.1.2 root 940: return \"addqb %2,%0\"; 941: return \"addb %2,%0\"; 1.1 root 942: }") 943: 944: ;;- All kinds of subtract instructions. 945: 946: (define_insn "subdf3" 947: [(set (match_operand:DF 0 "general_operand" "=fm") 948: (minus:DF (match_operand:DF 1 "general_operand" "0") 949: (match_operand:DF 2 "general_operand" "fmF")))] 950: "TARGET_32081" 951: "subl %2,%0") 952: 953: (define_insn "subsf3" 954: [(set (match_operand:SF 0 "general_operand" "=fm") 955: (minus:SF (match_operand:SF 1 "general_operand" "0") 956: (match_operand:SF 2 "general_operand" "fmF")))] 957: "TARGET_32081" 958: "subf %2,%0") 959: 960: (define_insn "" 961: [(set (reg:SI 17) 962: (minus:SI (reg:SI 17) 963: (match_operand:SI 0 "immediate_operand" "i")))] 964: "GET_CODE (operands[0]) == CONST_INT" 965: "* 966: { 1.1.1.3 ! root 967: if (! TARGET_32532 && GET_CODE(operands[0]) == CONST_INT ! 968: && INTVAL(operands[0]) < 64 && INTVAL(operands[0]) > -64) 1.1.1.2 root 969: return \"adjspb %$%0\"; 970: return \"adjspd %$%0\"; 1.1 root 971: }") 972: 973: (define_insn "subsi3" 974: [(set (match_operand:SI 0 "general_operand" "=g") 975: (minus:SI (match_operand:SI 1 "general_operand" "0") 976: (match_operand:SI 2 "general_operand" "rmn")))] 977: "" 978: "* 979: { if (GET_CODE (operands[2]) == CONST_INT) 980: { 981: int i = INTVAL (operands[2]); 982: 983: if (i <= 8 && i >= -7) 984: return \"addqd %$%n2,%0\"; 985: } 986: return \"subd %2,%0\"; 987: }") 988: 989: (define_insn "subhi3" 990: [(set (match_operand:HI 0 "general_operand" "=g") 991: (minus:HI (match_operand:HI 1 "general_operand" "0") 992: (match_operand:HI 2 "general_operand" "g")))] 993: "" 994: "* 995: { if (GET_CODE (operands[2]) == CONST_INT) 996: { 997: int i = INTVAL (operands[2]); 998: 999: if (i <= 8 && i >= -7) 1000: return \"addqw %$%n2,%0\"; 1001: } 1002: return \"subw %2,%0\"; 1003: }") 1004: 1005: (define_insn "" 1006: [(set (strict_low_part (match_operand:HI 0 "general_operand" "=r")) 1007: (minus:HI (match_operand:HI 1 "general_operand" "0") 1008: (match_operand:HI 2 "general_operand" "g")))] 1009: "" 1010: "* 1011: { 1012: if (GET_CODE (operands[1]) == CONST_INT 1013: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9) 1.1.1.2 root 1014: return \"addqw %$%n2,%0\"; 1015: return \"subw %2,%0\"; 1.1 root 1016: }") 1017: 1018: (define_insn "subqi3" 1019: [(set (match_operand:QI 0 "general_operand" "=g") 1020: (minus:QI (match_operand:QI 1 "general_operand" "0") 1021: (match_operand:QI 2 "general_operand" "g")))] 1022: "" 1023: "* 1024: { if (GET_CODE (operands[2]) == CONST_INT) 1025: { 1026: int i = INTVAL (operands[2]); 1027: 1028: if (i <= 8 && i >= -7) 1029: return \"addqb %$%n2,%0\"; 1030: } 1031: return \"subb %2,%0\"; 1032: }") 1033: 1034: (define_insn "" 1035: [(set (strict_low_part (match_operand:QI 0 "general_operand" "=r")) 1036: (minus:QI (match_operand:QI 1 "general_operand" "0") 1037: (match_operand:QI 2 "general_operand" "g")))] 1038: "" 1039: "* 1040: { 1041: if (GET_CODE (operands[1]) == CONST_INT 1042: && INTVAL (operands[1]) >-8 && INTVAL(operands[1]) < 9) 1.1.1.2 root 1043: return \"addqb %$%n2,%0\"; 1044: return \"subb %2,%0\"; 1.1 root 1045: }") 1046: 1047: ;;- Multiply instructions. 1048: 1049: (define_insn "muldf3" 1050: [(set (match_operand:DF 0 "general_operand" "=fm") 1051: (mult:DF (match_operand:DF 1 "general_operand" "%0") 1052: (match_operand:DF 2 "general_operand" "fmF")))] 1053: "TARGET_32081" 1054: "mull %2,%0") 1055: 1056: (define_insn "mulsf3" 1057: [(set (match_operand:SF 0 "general_operand" "=fm") 1058: (mult:SF (match_operand:SF 1 "general_operand" "%0") 1059: (match_operand:SF 2 "general_operand" "fmF")))] 1060: "TARGET_32081" 1061: "mulf %2,%0") 1062: 1063: (define_insn "mulsi3" 1064: [(set (match_operand:SI 0 "general_operand" "=g") 1065: (mult:SI (match_operand:SI 1 "general_operand" "%0") 1066: (match_operand:SI 2 "general_operand" "rmn")))] 1067: "" 1068: "muld %2,%0") 1069: 1070: (define_insn "mulhi3" 1071: [(set (match_operand:HI 0 "general_operand" "=g") 1072: (mult:HI (match_operand:HI 1 "general_operand" "%0") 1073: (match_operand:HI 2 "general_operand" "g")))] 1074: "" 1075: "mulw %2,%0") 1076: 1077: (define_insn "mulqi3" 1078: [(set (match_operand:QI 0 "general_operand" "=g") 1079: (mult:QI (match_operand:QI 1 "general_operand" "%0") 1080: (match_operand:QI 2 "general_operand" "g")))] 1081: "" 1082: "mulb %2,%0") 1083: 1084: (define_insn "umulsidi3" 1085: [(set (match_operand:DI 0 "general_operand" "=g") 1086: (mult:DI (zero_extend:DI 1087: (match_operand:SI 1 "nonimmediate_operand" "0")) 1088: (zero_extend:DI 1089: (match_operand:SI 2 "nonimmediate_operand" "rmn"))))] 1090: "" 1091: "meid %2,%0") 1092: 1093: ;;- Divide instructions. 1094: 1095: (define_insn "divdf3" 1096: [(set (match_operand:DF 0 "general_operand" "=fm") 1097: (div:DF (match_operand:DF 1 "general_operand" "0") 1098: (match_operand:DF 2 "general_operand" "fmF")))] 1099: "TARGET_32081" 1100: "divl %2,%0") 1101: 1102: (define_insn "divsf3" 1103: [(set (match_operand:SF 0 "general_operand" "=fm") 1104: (div:SF (match_operand:SF 1 "general_operand" "0") 1105: (match_operand:SF 2 "general_operand" "fmF")))] 1106: "TARGET_32081" 1107: "divf %2,%0") 1108: 1109: (define_insn "divsi3" 1110: [(set (match_operand:SI 0 "general_operand" "=g") 1111: (div:SI (match_operand:SI 1 "general_operand" "0") 1112: (match_operand:SI 2 "general_operand" "rmn")))] 1113: "" 1114: "quod %2,%0") 1115: 1116: (define_insn "divhi3" 1117: [(set (match_operand:HI 0 "general_operand" "=g") 1118: (div:HI (match_operand:HI 1 "general_operand" "0") 1119: (match_operand:HI 2 "general_operand" "g")))] 1120: "" 1121: "quow %2,%0") 1122: 1123: (define_insn "divqi3" 1124: [(set (match_operand:QI 0 "general_operand" "=g") 1125: (div:QI (match_operand:QI 1 "general_operand" "0") 1126: (match_operand:QI 2 "general_operand" "g")))] 1127: "" 1128: "quob %2,%0") 1129: 1130: (define_insn "udivsi3" 1131: [(set (match_operand:SI 0 "register_operand" "=r") 1132: (udiv:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) 1133: (match_operand:SI 2 "general_operand" "rmn")))] 1134: "" 1135: "* 1136: { 1137: operands[1] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1); 1138: return \"deid %2,%0\;movd %1,%0\"; 1139: }") 1140: 1141: (define_insn "udivhi3" 1142: [(set (match_operand:HI 0 "register_operand" "=r") 1143: (udiv:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) 1144: (match_operand:HI 2 "general_operand" "g")))] 1145: "" 1146: "* 1147: { 1148: operands[1] = gen_rtx (REG, HImode, REGNO (operands[0]) + 1); 1149: return \"deiw %2,%0\;movw %1,%0\"; 1150: }") 1151: 1152: (define_insn "udivqi3" 1153: [(set (match_operand:QI 0 "register_operand" "=r") 1154: (udiv:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) 1155: (match_operand:QI 2 "general_operand" "g")))] 1156: "" 1157: "* 1158: { 1159: operands[1] = gen_rtx (REG, QImode, REGNO (operands[0]) + 1); 1160: return \"deib %2,%0\;movb %1,%0\"; 1161: }") 1162: 1163: ;; Remainder instructions. 1164: 1165: (define_insn "modsi3" 1166: [(set (match_operand:SI 0 "general_operand" "=g") 1167: (mod:SI (match_operand:SI 1 "general_operand" "0") 1168: (match_operand:SI 2 "general_operand" "rmn")))] 1169: "" 1170: "remd %2,%0") 1171: 1172: (define_insn "modhi3" 1173: [(set (match_operand:HI 0 "general_operand" "=g") 1174: (mod:HI (match_operand:HI 1 "general_operand" "0") 1175: (match_operand:HI 2 "general_operand" "g")))] 1176: "" 1177: "remw %2,%0") 1178: 1179: (define_insn "modqi3" 1180: [(set (match_operand:QI 0 "general_operand" "=g") 1181: (mod:QI (match_operand:QI 1 "general_operand" "0") 1182: (match_operand:QI 2 "general_operand" "g")))] 1183: "" 1184: "remb %2,%0") 1185: 1186: (define_insn "umodsi3" 1187: [(set (match_operand:SI 0 "register_operand" "=r") 1188: (umod:SI (subreg:SI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) 1189: (match_operand:SI 2 "general_operand" "rmn")))] 1190: "" 1191: "deid %2,%0") 1192: 1193: (define_insn "umodhi3" 1194: [(set (match_operand:HI 0 "register_operand" "=r") 1195: (umod:HI (subreg:HI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) 1196: (match_operand:HI 2 "general_operand" "g")))] 1197: "" 1198: "deiw %2,%0") 1199: 1200: (define_insn "umodqi3" 1201: [(set (match_operand:QI 0 "register_operand" "=r") 1202: (umod:QI (subreg:QI (match_operand:DI 1 "reg_or_mem_operand" "0") 0) 1203: (match_operand:QI 2 "general_operand" "g")))] 1204: "" 1205: "deib %2,%0") 1206: 1207: ; This isn't be usable in its current form. 1208: ;(define_insn "udivmoddisi4" 1209: ; [(set (subreg:SI (match_operand:DI 0 "general_operand" "=r") 1) 1210: ; (udiv:SI (match_operand:DI 1 "general_operand" "0") 1211: ; (match_operand:SI 2 "general_operand" "rmn"))) 1212: ; (set (subreg:SI (match_dup 0) 0) 1213: ; (umod:SI (match_dup 1) (match_dup 2)))] 1214: ; "" 1215: ; "deid %2,%0") 1216: 1217: ;;- Logical Instructions: AND 1218: 1219: (define_insn "andsi3" 1220: [(set (match_operand:SI 0 "general_operand" "=g") 1221: (and:SI (match_operand:SI 1 "general_operand" "%0") 1222: (match_operand:SI 2 "general_operand" "rmn")))] 1223: "" 1224: "* 1225: { 1226: if (GET_CODE (operands[2]) == CONST_INT) 1227: { 1228: if ((INTVAL (operands[2]) | 0xff) == 0xffffffff) 1229: { 1230: if (INTVAL (operands[2]) == 0xffffff00) 1231: return \"movqb %$0,%0\"; 1232: else 1233: { 1234: operands[2] = gen_rtx (CONST_INT, VOIDmode, 1235: INTVAL (operands[2]) & 0xff); 1236: return \"andb %2,%0\"; 1237: } 1238: } 1239: if ((INTVAL (operands[2]) | 0xffff) == 0xffffffff) 1240: { 1241: if (INTVAL (operands[2]) == 0xffff0000) 1242: return \"movqw %$0,%0\"; 1243: else 1244: { 1245: operands[2] = gen_rtx (CONST_INT, VOIDmode, 1246: INTVAL (operands[2]) & 0xffff); 1247: return \"andw %2,%0\"; 1248: } 1249: } 1250: } 1251: return \"andd %2,%0\"; 1252: }") 1253: 1254: (define_insn "andhi3" 1255: [(set (match_operand:HI 0 "general_operand" "=g") 1256: (and:HI (match_operand:HI 1 "general_operand" "%0") 1257: (match_operand:HI 2 "general_operand" "g")))] 1258: "" 1259: "* 1260: { 1261: if (GET_CODE (operands[2]) == CONST_INT 1262: && (INTVAL (operands[2]) | 0xff) == 0xffffffff) 1263: { 1264: if (INTVAL (operands[2]) == 0xffffff00) 1265: return \"movqb %$0,%0\"; 1266: else 1267: { 1268: operands[2] = gen_rtx (CONST_INT, VOIDmode, 1269: INTVAL (operands[2]) & 0xff); 1270: return \"andb %2,%0\"; 1271: } 1272: } 1273: return \"andw %2,%0\"; 1274: }") 1275: 1276: (define_insn "andqi3" 1277: [(set (match_operand:QI 0 "general_operand" "=g") 1278: (and:QI (match_operand:QI 1 "general_operand" "%0") 1279: (match_operand:QI 2 "general_operand" "g")))] 1280: "" 1281: "andb %2,%0") 1282: 1283: (define_insn "" 1284: [(set (match_operand:SI 0 "general_operand" "=g") 1285: (and:SI (not:SI (match_operand:SI 1 "general_operand" "rmn")) 1286: (match_operand:SI 2 "general_operand" "0")))] 1287: "" 1288: "bicd %1,%0") 1289: 1290: (define_insn "" 1291: [(set (match_operand:HI 0 "general_operand" "=g") 1292: (and:HI (not:HI (match_operand:HI 1 "general_operand" "g")) 1293: (match_operand:HI 2 "general_operand" "0")))] 1294: "" 1295: "bicw %1,%0") 1296: 1297: (define_insn "" 1298: [(set (match_operand:QI 0 "general_operand" "=g") 1299: (and:QI (not:QI (match_operand:QI 1 "general_operand" "g")) 1300: (match_operand:QI 2 "general_operand" "0")))] 1301: "" 1302: "bicb %1,%0") 1303: 1304: ;;- Bit set instructions. 1305: 1306: (define_insn "iorsi3" 1307: [(set (match_operand:SI 0 "general_operand" "=g") 1308: (ior:SI (match_operand:SI 1 "general_operand" "%0") 1309: (match_operand:SI 2 "general_operand" "rmn")))] 1310: "" 1311: "* 1312: { 1313: if (GET_CODE (operands[2]) == CONST_INT) { 1314: if ((INTVAL (operands[2]) & 0xffffff00) == 0) 1315: return \"orb %2,%0\"; 1316: if ((INTVAL (operands[2]) & 0xffff0000) == 0) 1317: return \"orw %2,%0\"; 1318: } 1319: return \"ord %2,%0\"; 1320: }") 1321: 1322: (define_insn "iorhi3" 1323: [(set (match_operand:HI 0 "general_operand" "=g") 1324: (ior:HI (match_operand:HI 1 "general_operand" "%0") 1325: (match_operand:HI 2 "general_operand" "g")))] 1326: "" 1327: "* 1328: { 1329: if (GET_CODE(operands[2]) == CONST_INT && 1330: (INTVAL(operands[2]) & 0xffffff00) == 0) 1331: return \"orb %2,%0\"; 1332: return \"orw %2,%0\"; 1333: }") 1334: 1335: (define_insn "iorqi3" 1336: [(set (match_operand:QI 0 "general_operand" "=g") 1337: (ior:QI (match_operand:QI 1 "general_operand" "%0") 1338: (match_operand:QI 2 "general_operand" "g")))] 1339: "" 1340: "orb %2,%0") 1341: 1342: ;;- xor instructions. 1343: 1344: (define_insn "xorsi3" 1345: [(set (match_operand:SI 0 "general_operand" "=g") 1346: (xor:SI (match_operand:SI 1 "general_operand" "%0") 1347: (match_operand:SI 2 "general_operand" "rmn")))] 1348: "" 1349: "* 1350: { 1351: if (GET_CODE (operands[2]) == CONST_INT) { 1352: if ((INTVAL (operands[2]) & 0xffffff00) == 0) 1353: return \"xorb %2,%0\"; 1354: if ((INTVAL (operands[2]) & 0xffff0000) == 0) 1355: return \"xorw %2,%0\"; 1356: } 1357: return \"xord %2,%0\"; 1358: }") 1359: 1360: (define_insn "xorhi3" 1361: [(set (match_operand:HI 0 "general_operand" "=g") 1362: (xor:HI (match_operand:HI 1 "general_operand" "%0") 1363: (match_operand:HI 2 "general_operand" "g")))] 1364: "" 1365: "* 1366: { 1367: if (GET_CODE(operands[2]) == CONST_INT && 1368: (INTVAL(operands[2]) & 0xffffff00) == 0) 1369: return \"xorb %2,%0\"; 1370: return \"xorw %2,%0\"; 1371: }") 1372: 1373: (define_insn "xorqi3" 1374: [(set (match_operand:QI 0 "general_operand" "=g") 1375: (xor:QI (match_operand:QI 1 "general_operand" "%0") 1376: (match_operand:QI 2 "general_operand" "g")))] 1377: "" 1378: "xorb %2,%0") 1379: 1380: (define_insn "negdf2" 1381: [(set (match_operand:DF 0 "general_operand" "=fm<") 1382: (neg:DF (match_operand:DF 1 "general_operand" "fmF")))] 1383: "TARGET_32081" 1384: "negl %1,%0") 1385: 1386: (define_insn "negsf2" 1387: [(set (match_operand:SF 0 "general_operand" "=fm<") 1388: (neg:SF (match_operand:SF 1 "general_operand" "fmF")))] 1389: "TARGET_32081" 1390: "negf %1,%0") 1391: 1392: (define_insn "negsi2" 1393: [(set (match_operand:SI 0 "general_operand" "=g<") 1394: (neg:SI (match_operand:SI 1 "general_operand" "rmn")))] 1395: "" 1396: "negd %1,%0") 1397: 1398: (define_insn "neghi2" 1399: [(set (match_operand:HI 0 "general_operand" "=g<") 1400: (neg:HI (match_operand:HI 1 "general_operand" "g")))] 1401: "" 1402: "negw %1,%0") 1403: 1404: (define_insn "negqi2" 1405: [(set (match_operand:QI 0 "general_operand" "=g<") 1406: (neg:QI (match_operand:QI 1 "general_operand" "g")))] 1407: "" 1408: "negb %1,%0") 1409: 1410: (define_insn "one_cmplsi2" 1411: [(set (match_operand:SI 0 "general_operand" "=g<") 1412: (not:SI (match_operand:SI 1 "general_operand" "rmn")))] 1413: "" 1414: "comd %1,%0") 1415: 1416: (define_insn "one_cmplhi2" 1417: [(set (match_operand:HI 0 "general_operand" "=g<") 1418: (not:HI (match_operand:HI 1 "general_operand" "g")))] 1419: "" 1420: "comw %1,%0") 1421: 1422: (define_insn "one_cmplqi2" 1423: [(set (match_operand:QI 0 "general_operand" "=g<") 1424: (not:QI (match_operand:QI 1 "general_operand" "g")))] 1425: "" 1426: "comb %1,%0") 1427: 1428: ;; arithmetic left and right shift operations 1429: ;; on the 32532 we will always use lshd for arithmetic left shifts, 1430: ;; because it is three times faster. Broken programs which 1431: ;; use negative shift counts are probably broken differently 1432: ;; than elsewhere. 1433: 1434: ;; alternative 0 never matches on the 32532 1435: (define_insn "ashlsi3" 1436: [(set (match_operand:SI 0 "general_operand" "=g,g") 1437: (ashift:SI (match_operand:SI 1 "general_operand" "r,0") 1438: (match_operand:SI 2 "general_operand" "I,rmn")))] 1439: "" 1440: "* 1441: { if (TARGET_32532) 1442: return \"lshd %2,%0\"; 1443: else 1444: return output_shift_insn (operands); 1445: }") 1446: 1447: (define_insn "ashlhi3" 1448: [(set (match_operand:HI 0 "general_operand" "=g") 1449: (ashift:HI (match_operand:HI 1 "general_operand" "0") 1450: (match_operand:SI 2 "general_operand" "rmn")))] 1451: "" 1452: "* 1453: { if (GET_CODE (operands[2]) == CONST_INT) 1454: { 1455: if (INTVAL (operands[2]) == 1) 1456: return \"addw %0,%0\"; 1.1.1.3 ! root 1457: else if (! TARGET_32532 && INTVAL (operands[2]) == 2) 1.1 root 1458: return \"addw %0,%0\;addw %0,%0\"; 1459: } 1460: if (TARGET_32532) 1461: return \"lshw %2,%0\"; 1462: else 1463: return \"ashw %2,%0\"; 1464: }") 1465: 1466: (define_insn "ashlqi3" 1467: [(set (match_operand:QI 0 "general_operand" "=g") 1468: (ashift:QI (match_operand:QI 1 "general_operand" "0") 1469: (match_operand:SI 2 "general_operand" "rmn")))] 1470: "" 1471: "* 1472: { if (GET_CODE (operands[2]) == CONST_INT) 1473: { 1474: if (INTVAL (operands[2]) == 1) 1475: return \"addb %0,%0\"; 1.1.1.3 ! root 1476: else if (! TARGET_32532 && INTVAL (operands[2]) == 2) 1.1 root 1477: return \"addb %0,%0\;addb %0,%0\"; 1478: } 1479: if (TARGET_32532) 1480: return \"lshb %2,%0\"; 1481: else 1482: return \"ashb %2,%0\"; 1483: }") 1484: 1485: ;; Arithmetic right shift on the 32k works by negating the shift count. 1486: (define_expand "ashrsi3" 1487: [(set (match_operand:SI 0 "general_operand" "=g") 1488: (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") 1489: (match_operand:SI 2 "general_operand" "g")))] 1490: "" 1491: " 1492: { 1493: if (GET_CODE (operands[2]) != CONST_INT) 1494: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1495: }") 1496: 1497: (define_insn "" 1498: [(set (match_operand:SI 0 "general_operand" "=g") 1499: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") 1500: (match_operand:SI 2 "immediate_operand" "i")))] 1501: "" 1502: "ashd %$%n2,%0") 1503: 1504: (define_insn "" 1505: [(set (match_operand:SI 0 "general_operand" "=g") 1506: (ashiftrt:SI (match_operand:SI 1 "general_operand" "0") 1507: (neg:SI (match_operand:SI 2 "general_operand" "r"))))] 1508: "" 1509: "ashd %2,%0") 1510: 1511: (define_expand "ashrhi3" 1512: [(set (match_operand:HI 0 "general_operand" "=g") 1513: (ashiftrt:HI (match_operand:HI 1 "general_operand" "g") 1514: (match_operand:SI 2 "general_operand" "g")))] 1515: "" 1516: " 1517: { 1518: if (GET_CODE (operands[2]) != CONST_INT) 1519: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1520: }") 1521: 1522: (define_insn "" 1523: [(set (match_operand:HI 0 "general_operand" "=g") 1524: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") 1525: (match_operand:SI 2 "immediate_operand" "i")))] 1526: "" 1527: "ashw %$%n2,%0") 1528: 1529: (define_insn "" 1530: [(set (match_operand:HI 0 "general_operand" "=g") 1531: (ashiftrt:HI (match_operand:HI 1 "general_operand" "0") 1532: (neg:SI (match_operand:SI 2 "general_operand" "r"))))] 1533: "" 1534: "ashw %2,%0") 1535: 1536: (define_expand "ashrqi3" 1537: [(set (match_operand:QI 0 "general_operand" "=g") 1538: (ashiftrt:QI (match_operand:QI 1 "general_operand" "g") 1539: (match_operand:SI 2 "general_operand" "g")))] 1540: "" 1541: " 1542: { 1543: if (GET_CODE (operands[2]) != CONST_INT) 1544: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1545: }") 1546: 1547: (define_insn "" 1548: [(set (match_operand:QI 0 "general_operand" "=g") 1549: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") 1550: (match_operand:SI 2 "immediate_operand" "i")))] 1551: "" 1552: "ashb %$%n2,%0") 1553: 1554: (define_insn "" 1555: [(set (match_operand:QI 0 "general_operand" "=g") 1556: (ashiftrt:QI (match_operand:QI 1 "general_operand" "0") 1557: (neg:SI (match_operand:SI 2 "general_operand" "r"))))] 1558: "" 1559: "ashb %2,%0") 1560: 1561: ;; logical shift instructions 1562: 1563: ;; Logical right shift on the 32k works by negating the shift count. 1564: (define_expand "lshrsi3" 1565: [(set (match_operand:SI 0 "general_operand" "=g") 1566: (lshiftrt:SI (match_operand:SI 1 "general_operand" "g") 1567: (match_operand:SI 2 "general_operand" "g")))] 1568: "" 1569: " 1570: { 1571: if (GET_CODE (operands[2]) != CONST_INT) 1572: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1573: }") 1574: 1575: (define_insn "" 1576: [(set (match_operand:SI 0 "general_operand" "=g") 1577: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") 1578: (match_operand:SI 2 "immediate_operand" "i")))] 1579: "" 1580: "lshd %$%n2,%0") 1581: 1582: (define_insn "" 1583: [(set (match_operand:SI 0 "general_operand" "=g") 1584: (lshiftrt:SI (match_operand:SI 1 "general_operand" "0") 1585: (neg:SI (match_operand:SI 2 "general_operand" "r"))))] 1586: "" 1587: "lshd %2,%0") 1588: 1589: (define_expand "lshrhi3" 1590: [(set (match_operand:HI 0 "general_operand" "=g") 1591: (lshiftrt:HI (match_operand:HI 1 "general_operand" "g") 1592: (match_operand:SI 2 "general_operand" "g")))] 1593: "" 1594: " 1595: { 1596: if (GET_CODE (operands[2]) != CONST_INT) 1597: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1598: }") 1599: 1600: (define_insn "" 1601: [(set (match_operand:HI 0 "general_operand" "=g") 1602: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") 1603: (match_operand:SI 2 "immediate_operand" "i")))] 1604: "" 1605: "lshw %$%n2,%0") 1606: 1607: (define_insn "" 1608: [(set (match_operand:HI 0 "general_operand" "=g") 1609: (lshiftrt:HI (match_operand:HI 1 "general_operand" "0") 1610: (neg:SI (match_operand:SI 2 "general_operand" "r"))))] 1611: "" 1612: "lshw %2,%0") 1613: 1614: (define_expand "lshrqi3" 1615: [(set (match_operand:QI 0 "general_operand" "=g") 1616: (lshiftrt:QI (match_operand:QI 1 "general_operand" "g") 1617: (match_operand:SI 2 "general_operand" "g")))] 1618: "" 1619: " 1620: { 1621: if (GET_CODE (operands[2]) != CONST_INT) 1622: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1623: }") 1624: 1625: (define_insn "" 1626: [(set (match_operand:QI 0 "general_operand" "=g") 1627: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") 1628: (match_operand:SI 2 "immediate_operand" "i")))] 1629: "" 1630: "lshb %$%n2,%0") 1631: 1632: (define_insn "" 1633: [(set (match_operand:QI 0 "general_operand" "=g") 1634: (lshiftrt:QI (match_operand:QI 1 "general_operand" "0") 1635: (neg:SI (match_operand:SI 2 "general_operand" "r"))))] 1636: "" 1637: "lshb %2,%0") 1638: 1639: ;; Rotate instructions 1640: 1641: (define_insn "rotlsi3" 1642: [(set (match_operand:SI 0 "general_operand" "=g") 1643: (rotate:SI (match_operand:SI 1 "general_operand" "0") 1644: (match_operand:SI 2 "general_operand" "rmn")))] 1645: "" 1646: "rotd %2,%0") 1647: 1648: (define_insn "rotlhi3" 1649: [(set (match_operand:HI 0 "general_operand" "=g") 1650: (rotate:HI (match_operand:HI 1 "general_operand" "0") 1651: (match_operand:SI 2 "general_operand" "rmn")))] 1652: "" 1653: "rotw %2,%0") 1654: 1655: (define_insn "rotlqi3" 1656: [(set (match_operand:QI 0 "general_operand" "=g") 1657: (rotate:QI (match_operand:QI 1 "general_operand" "0") 1658: (match_operand:SI 2 "general_operand" "rmn")))] 1659: "" 1660: "rotb %2,%0") 1661: 1662: ;; Right rotate on the 32k works by negating the shift count. 1663: (define_expand "rotrsi3" 1664: [(set (match_operand:SI 0 "general_operand" "=g") 1665: (rotatert:SI (match_operand:SI 1 "general_operand" "g") 1666: (match_operand:SI 2 "general_operand" "g")))] 1667: "" 1668: " 1669: { 1670: if (GET_CODE (operands[2]) != CONST_INT) 1671: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1672: }") 1673: 1674: (define_insn "" 1675: [(set (match_operand:SI 0 "general_operand" "=g") 1676: (rotatert:SI (match_operand:SI 1 "general_operand" "0") 1677: (match_operand:SI 2 "immediate_operand" "i")))] 1678: "" 1679: "rotd %$%n2,%0") 1680: 1681: (define_insn "" 1682: [(set (match_operand:SI 0 "general_operand" "=g") 1683: (rotatert:SI (match_operand:SI 1 "general_operand" "0") 1684: (neg:SI (match_operand:SI 2 "general_operand" "r"))))] 1685: "" 1686: "rotd %2,%0") 1687: 1688: (define_expand "rotrhi3" 1689: [(set (match_operand:HI 0 "general_operand" "=g") 1690: (rotatert:HI (match_operand:HI 1 "general_operand" "g") 1691: (match_operand:SI 2 "general_operand" "g")))] 1692: "" 1693: " 1694: { 1695: if (GET_CODE (operands[2]) != CONST_INT) 1696: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1697: }") 1698: 1699: (define_insn "" 1700: [(set (match_operand:HI 0 "general_operand" "=g") 1701: (rotatert:HI (match_operand:HI 1 "general_operand" "0") 1702: (match_operand:SI 2 "immediate_operand" "i")))] 1703: "" 1704: "rotw %$%n2,%0") 1705: 1706: (define_insn "" 1707: [(set (match_operand:HI 0 "general_operand" "=g") 1708: (rotatert:HI (match_operand:HI 1 "general_operand" "0") 1709: (neg:SI (match_operand:SI 2 "general_operand" "r"))))] 1710: "" 1711: "rotw %2,%0") 1712: 1713: (define_expand "rotrqi3" 1714: [(set (match_operand:QI 0 "general_operand" "=g") 1715: (rotatert:QI (match_operand:QI 1 "general_operand" "g") 1716: (match_operand:SI 2 "general_operand" "g")))] 1717: "" 1718: " 1719: { 1720: if (GET_CODE (operands[2]) != CONST_INT) 1721: operands[2] = gen_rtx (NEG, SImode, negate_rtx (SImode, operands[2])); 1722: }") 1723: 1724: (define_insn "" 1725: [(set (match_operand:QI 0 "general_operand" "=g") 1726: (rotatert:QI (match_operand:QI 1 "general_operand" "0") 1727: (match_operand:SI 2 "immediate_operand" "i")))] 1728: "" 1729: "rotb %$%n2,%0") 1730: 1731: (define_insn "" 1732: [(set (match_operand:QI 0 "general_operand" "=g") 1733: (rotatert:QI (match_operand:QI 1 "general_operand" "0") 1734: (neg:SI (match_operand:SI 2 "general_operand" "r"))))] 1735: "" 1736: "rotb %2,%0") 1737: 1738: ;;- load or push effective address 1739: ;; These come after the move, add, and multiply patterns 1740: ;; because we don't want pushl $1 turned into pushad 1. 1741: 1742: (define_insn "" 1743: [(set (match_operand:SI 0 "general_operand" "=g<") 1744: (match_operand:QI 1 "address_operand" "p"))] 1745: "" 1746: "* 1747: { 1748: if (REG_P (operands[0]) 1749: && GET_CODE (operands[1]) == MULT 1750: && GET_CODE (XEXP (operands[1], 1)) == CONST_INT 1751: && (INTVAL (XEXP (operands[1], 1)) == 2 1752: || INTVAL (XEXP (operands[1], 1)) == 4)) 1753: { 1754: rtx xoperands[3]; 1755: xoperands[0] = operands[0]; 1756: xoperands[1] = XEXP (operands[1], 0); 1757: xoperands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (XEXP (operands[1], 1)) >> 1); 1758: return output_shift_insn (xoperands); 1759: } 1760: return \"addr %a1,%0\"; 1761: }") 1762: 1763: ;;; Index insns. These are about the same speed as multiply-add counterparts. 1764: ;;; but slower then using power-of-2 shifts if we can use them 1765: ; 1766: ;(define_insn "" 1767: ; [(set (match_operand:SI 0 "register_operand" "=r") 1768: ; (plus:SI (match_operand:SI 1 "general_operand" "rmn") 1769: ; (mult:SI (match_operand:SI 2 "register_operand" "0") 1770: ; (plus:SI (match_operand:SI 3 "general_operand" "rmn") (const_int 1)))))] 1771: ; "GET_CODE (operands[3]) != CONST_INT || INTVAL (operands[3]) > 8" 1772: ; "indexd %0,%3,%1") 1773: ; 1774: ;(define_insn "" 1775: ; [(set (match_operand:SI 0 "register_operand" "=r") 1776: ; (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "0") 1777: ; (plus:SI (match_operand:SI 2 "general_operand" "rmn") (const_int 1))) 1778: ; (match_operand:SI 3 "general_operand" "rmn")))] 1779: ; "GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) > 8" 1780: ; "indexd %0,%2,%3") 1781: 1782: ;; Set, Clear, and Invert bit 1783: 1784: (define_insn "" 1785: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g") 1786: (const_int 1) 1787: (match_operand:SI 1 "general_operand" "rmn")) 1788: (const_int 1))] 1789: "" 1790: "sbitd %1,%0") 1791: 1792: (define_insn "" 1793: [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "+g") 1794: (const_int 1) 1795: (match_operand:SI 1 "general_operand" "rmn")) 1796: (const_int 0))] 1797: "" 1798: "cbitd %1,%0") 1799: 1800: (define_insn "" 1801: [(set (match_operand:SI 0 "general_operand" "+g") 1802: (xor:SI (ashift:SI (const_int 1) 1803: (match_operand:SI 1 "general_operand" "rmn")) 1804: (match_dup 0)))] 1805: "" 1806: "ibitd %1,%0") 1807: 1808: (define_insn "" 1809: [(set (match_operand:QI 0 "general_operand" "=g") 1810: (xor:QI (subreg:QI 1811: (ashift:SI (const_int 1) 1812: (match_operand:QI 1 "general_operand" "rmn")) 0) 1813: (match_dup 0)))] 1814: "" 1815: "ibitb %1,%0") 1816: 1817: ;; Recognize jbs and jbc instructions. 1818: 1819: (define_insn "" 1820: [(set (cc0) 1821: (zero_extract (match_operand:SI 0 "general_operand" "rm") 1822: (const_int 1) 1823: (match_operand:SI 1 "general_operand" "g")))] 1824: "" 1825: "* 1826: { cc_status.flags = CC_Z_IN_F; 1827: return \"tbitd %1,%0\"; 1828: }") 1829: 1830: ;; extract(base, width, offset) 1831: ;; Signed bitfield extraction is not supported in hardware on the 1832: ;; NS 32032. It is therefore better to let GCC figure out a 1833: ;; good strategy for generating the proper instruction sequence 1834: ;; and represent it as rtl. 1835: 1836: ;; Optimize the case of extracting a byte or word from a register. 1837: ;; Otherwise we must load a register with the offset of the 1838: ;; chunk we want, and perform an extract insn (each of which 1839: ;; is very expensive). Since we use the stack to do our bit-twiddling 1840: ;; we cannot use it for a destination. Perhaps things are fast 1841: ;; enough on the 32532 that such hacks are not needed. 1842: 1843: (define_insn "" 1844: [(set (match_operand:SI 0 "general_operand" "=ro") 1845: (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 1846: (match_operand:SI 2 "const_int_operand" "i") 1847: (match_operand:SI 3 "const_int_operand" "i")))] 1848: "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 1849: && (INTVAL (operands[3]) == 8 || INTVAL (operands[3]) == 16 || INTVAL (operands[3]) == 24)" 1850: "* 1851: { 1852: output_asm_insn (\"movd %1,tos\", operands); 1853: if (INTVAL (operands[2]) == 16) 1854: { 1855: if (INTVAL (operands[3]) == 8) 1856: output_asm_insn (\"movzwd 1(sp),%0\", operands); 1857: else 1858: output_asm_insn (\"movzwd 2(sp),%0\", operands); 1859: } 1860: else 1861: { 1862: if (INTVAL (operands[3]) == 8) 1863: output_asm_insn (\"movzbd 1(sp),%0\", operands); 1864: else if (INTVAL (operands[3]) == 16) 1865: output_asm_insn (\"movzbd 2(sp),%0\", operands); 1866: else 1867: output_asm_insn (\"movzbd 3(sp),%0\", operands); 1868: } 1869: if (TARGET_32532 || TARGET_32332) 1870: return \"cmpqd %$0,tos\"; 1871: else 1872: return \"adjspb %$-4\"; 1873: }") 1874: 1.1.1.3 ! root 1875: ;; The exts/ext instructions have the problem that they always access ! 1876: ;; 32 bits even if the bitfield is smaller. For example the instruction ! 1877: ;; extsd 7(r1),r0,2,5 ! 1878: ;; would read not only at address 7(r1) but also at 8(r1) to 10(r1). ! 1879: ;; If these addresses are in a different (unmapped) page a memory fault ! 1880: ;; is the result. ! 1881: ;; ! 1882: ;; Timing considerations: ! 1883: ;; movd 0(r1),r0 3 bytes ! 1884: ;; lshd -26,r0 4 ! 1885: ;; andd 0x1f,r0 5 ! 1886: ;; takes about 13 cycles on the 532 while ! 1887: ;; extsd 7(r1),r0,2,5 5 bytes ! 1888: ;; takes about 21 cycles. ! 1889: ;; ! 1890: ;; The inss/ins instructions suffer from the same problem. ! 1891: ;; ! 1892: ;; A machine specific option (-mbitfield/-mnobitfield) is used ! 1893: ;; to allow/disallow the use of these instructions. ! 1894: 1.1 root 1895: (define_insn "" 1896: [(set (match_operand:SI 0 "general_operand" "=g<") 1897: (zero_extract:SI (match_operand:SI 1 "register_operand" "g") 1898: (match_operand:SI 2 "const_int_operand" "i") 1899: (match_operand:SI 3 "general_operand" "rK")))] 1.1.1.3 ! root 1900: "TARGET_BITFIELD" 1.1 root 1901: "* 1902: { if (GET_CODE (operands[3]) == CONST_INT) 1903: return \"extsd %1,%0,%3,%2\"; 1904: else return \"extd %3,%1,%0,%2\"; 1905: }") 1906: 1907: (define_insn "extzv" 1908: [(set (match_operand:SI 0 "general_operand" "=g<") 1909: (zero_extract:SI (match_operand:QI 1 "general_operand" "g") 1910: (match_operand:SI 2 "const_int_operand" "i") 1911: (match_operand:SI 3 "general_operand" "rK")))] 1.1.1.3 ! root 1912: "TARGET_BITFIELD" 1.1 root 1913: "* 1914: { if (GET_CODE (operands[3]) == CONST_INT) 1915: return \"extsd %1,%0,%3,%2\"; 1916: else return \"extd %3,%1,%0,%2\"; 1917: }") 1918: 1919: (define_insn "" 1920: [(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o") 1921: (match_operand:SI 1 "const_int_operand" "i") 1922: (match_operand:SI 2 "general_operand" "rn")) 1923: (match_operand:SI 3 "general_operand" "rm"))] 1.1.1.3 ! root 1924: "TARGET_BITFIELD" 1.1 root 1925: "* 1926: { if (GET_CODE (operands[2]) == CONST_INT) 1927: { 1928: if (INTVAL (operands[2]) >= 8) 1929: { 1930: operands[0] = adj_offsettable_operand (operands[0], 1931: INTVAL (operands[2]) / 8); 1932: operands[2] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) % 8); 1933: } 1934: if (INTVAL (operands[1]) <= 8) 1935: return \"inssb %3,%0,%2,%1\"; 1936: else if (INTVAL (operands[1]) <= 16) 1937: return \"inssw %3,%0,%2,%1\"; 1938: else 1939: return \"inssd %3,%0,%2,%1\"; 1940: } 1941: return \"insd %2,%3,%0,%1\"; 1942: }") 1943: 1944: (define_insn "" 1945: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 1946: (match_operand:SI 1 "const_int_operand" "i") 1947: (match_operand:SI 2 "general_operand" "rK")) 1948: (match_operand:SI 3 "general_operand" "rm"))] 1.1.1.3 ! root 1949: "TARGET_BITFIELD" 1.1 root 1950: "* 1951: { if (GET_CODE (operands[2]) == CONST_INT) 1952: if (INTVAL (operands[1]) <= 8) 1953: return \"inssb %3,%0,%2,%1\"; 1954: else if (INTVAL (operands[1]) <= 16) 1955: return \"inssw %3,%0,%2,%1\"; 1956: else 1957: return \"inssd %3,%0,%2,%1\"; 1958: return \"insd %2,%3,%0,%1\"; 1959: }") 1960: 1961: (define_insn "insv" 1962: [(set (zero_extract:SI (match_operand:QI 0 "general_operand" "+g") 1963: (match_operand:SI 1 "const_int_operand" "i") 1964: (match_operand:SI 2 "general_operand" "rK")) 1965: (match_operand:SI 3 "general_operand" "rm"))] 1.1.1.3 ! root 1966: "TARGET_BITFIELD" 1.1 root 1967: "* 1968: { if (GET_CODE (operands[2]) == CONST_INT) 1969: if (INTVAL (operands[1]) <= 8) 1970: return \"inssb %3,%0,%2,%1\"; 1971: else if (INTVAL (operands[1]) <= 16) 1972: return \"inssw %3,%0,%2,%1\"; 1973: else 1974: return \"inssd %3,%0,%2,%1\"; 1975: return \"insd %2,%3,%0,%1\"; 1976: }") 1977: 1978: 1979: (define_insn "jump" 1980: [(set (pc) 1981: (label_ref (match_operand 0 "" "")))] 1982: "" 1983: "br %l0") 1984: 1985: (define_insn "beq" 1986: [(set (pc) 1987: (if_then_else (eq (cc0) 1988: (const_int 0)) 1989: (label_ref (match_operand 0 "" "")) 1990: (pc)))] 1991: "" 1992: "* 1993: { if (cc_prev_status.flags & CC_Z_IN_F) 1994: return \"bfc %l0\"; 1995: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) 1996: return \"bfs %l0\"; 1997: else return \"beq %l0\"; 1998: }") 1999: 2000: (define_insn "bne" 2001: [(set (pc) 2002: (if_then_else (ne (cc0) 2003: (const_int 0)) 2004: (label_ref (match_operand 0 "" "")) 2005: (pc)))] 2006: "" 2007: "* 2008: { if (cc_prev_status.flags & CC_Z_IN_F) 2009: return \"bfs %l0\"; 2010: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) 2011: return \"bfc %l0\"; 2012: else return \"bne %l0\"; 2013: }") 2014: 2015: (define_insn "bgt" 2016: [(set (pc) 2017: (if_then_else (gt (cc0) 2018: (const_int 0)) 2019: (label_ref (match_operand 0 "" "")) 2020: (pc)))] 2021: "" 2022: "bgt %l0") 2023: 2024: (define_insn "bgtu" 2025: [(set (pc) 2026: (if_then_else (gtu (cc0) 2027: (const_int 0)) 2028: (label_ref (match_operand 0 "" "")) 2029: (pc)))] 2030: "" 2031: "bhi %l0") 2032: 2033: (define_insn "blt" 2034: [(set (pc) 2035: (if_then_else (lt (cc0) 2036: (const_int 0)) 2037: (label_ref (match_operand 0 "" "")) 2038: (pc)))] 2039: "" 2040: "blt %l0") 2041: 2042: (define_insn "bltu" 2043: [(set (pc) 2044: (if_then_else (ltu (cc0) 2045: (const_int 0)) 2046: (label_ref (match_operand 0 "" "")) 2047: (pc)))] 2048: "" 2049: "blo %l0") 2050: 2051: (define_insn "bge" 2052: [(set (pc) 2053: (if_then_else (ge (cc0) 2054: (const_int 0)) 2055: (label_ref (match_operand 0 "" "")) 2056: (pc)))] 2057: "" 2058: "bge %l0") 2059: 2060: (define_insn "bgeu" 2061: [(set (pc) 2062: (if_then_else (geu (cc0) 2063: (const_int 0)) 2064: (label_ref (match_operand 0 "" "")) 2065: (pc)))] 2066: "" 2067: "bhs %l0") 2068: 2069: (define_insn "ble" 2070: [(set (pc) 2071: (if_then_else (le (cc0) 2072: (const_int 0)) 2073: (label_ref (match_operand 0 "" "")) 2074: (pc)))] 2075: "" 2076: "ble %l0") 2077: 2078: (define_insn "bleu" 2079: [(set (pc) 2080: (if_then_else (leu (cc0) 2081: (const_int 0)) 2082: (label_ref (match_operand 0 "" "")) 2083: (pc)))] 2084: "" 2085: "bls %l0") 2086: 2087: (define_insn "" 2088: [(set (pc) 2089: (if_then_else (eq (cc0) 2090: (const_int 0)) 2091: (pc) 2092: (label_ref (match_operand 0 "" ""))))] 2093: "" 2094: "* 2095: { if (cc_prev_status.flags & CC_Z_IN_F) 2096: return \"bfs %l0\"; 2097: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) 2098: return \"bfc %l0\"; 2099: else return \"bne %l0\"; 2100: }") 2101: 2102: (define_insn "" 2103: [(set (pc) 2104: (if_then_else (ne (cc0) 2105: (const_int 0)) 2106: (pc) 2107: (label_ref (match_operand 0 "" ""))))] 2108: "" 2109: "* 2110: { if (cc_prev_status.flags & CC_Z_IN_F) 2111: return \"bfc %l0\"; 2112: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) 2113: return \"bfs %l0\"; 2114: else return \"beq %l0\"; 2115: }") 2116: 2117: (define_insn "" 2118: [(set (pc) 2119: (if_then_else (gt (cc0) 2120: (const_int 0)) 2121: (pc) 2122: (label_ref (match_operand 0 "" ""))))] 2123: "" 2124: "ble %l0") 2125: 2126: (define_insn "" 2127: [(set (pc) 2128: (if_then_else (gtu (cc0) 2129: (const_int 0)) 2130: (pc) 2131: (label_ref (match_operand 0 "" ""))))] 2132: "" 2133: "bls %l0") 2134: 2135: (define_insn "" 2136: [(set (pc) 2137: (if_then_else (lt (cc0) 2138: (const_int 0)) 2139: (pc) 2140: (label_ref (match_operand 0 "" ""))))] 2141: "" 2142: "bge %l0") 2143: 2144: (define_insn "" 2145: [(set (pc) 2146: (if_then_else (ltu (cc0) 2147: (const_int 0)) 2148: (pc) 2149: (label_ref (match_operand 0 "" ""))))] 2150: "" 2151: "bhs %l0") 2152: 2153: (define_insn "" 2154: [(set (pc) 2155: (if_then_else (ge (cc0) 2156: (const_int 0)) 2157: (pc) 2158: (label_ref (match_operand 0 "" ""))))] 2159: "" 2160: "blt %l0") 2161: 2162: (define_insn "" 2163: [(set (pc) 2164: (if_then_else (geu (cc0) 2165: (const_int 0)) 2166: (pc) 2167: (label_ref (match_operand 0 "" ""))))] 2168: "" 2169: "blo %l0") 2170: 2171: (define_insn "" 2172: [(set (pc) 2173: (if_then_else (le (cc0) 2174: (const_int 0)) 2175: (pc) 2176: (label_ref (match_operand 0 "" ""))))] 2177: "" 2178: "bgt %l0") 2179: 2180: (define_insn "" 2181: [(set (pc) 2182: (if_then_else (leu (cc0) 2183: (const_int 0)) 2184: (pc) 2185: (label_ref (match_operand 0 "" ""))))] 2186: "" 2187: "bhi %l0") 2188: 2189: ;; Subtract-and-jump and Add-and-jump insns. 2190: ;; These can actually be used for adding numbers in the range -8 to 7 2191: 2192: (define_insn "" 2193: [(set (pc) 2194: (if_then_else 2195: (ne (match_operand:SI 0 "general_operand" "+g") 2196: (match_operand:SI 1 "const_int_operand" "i")) 2197: (label_ref (match_operand 2 "" "")) 2198: (pc))) 2199: (set (match_dup 0) 2200: (minus:SI (match_dup 0) 2201: (match_dup 1)))] 2202: "INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8" 2203: "acbd %$%n1,%0,%l2") 2204: 2205: (define_insn "" 2206: [(set (pc) 2207: (if_then_else 2208: (ne (match_operand:SI 0 "general_operand" "+g") 2209: (match_operand:SI 1 "const_int_operand" "i")) 2210: (label_ref (match_operand 2 "" "")) 2211: (pc))) 2212: (set (match_dup 0) 2213: (plus:SI (match_dup 0) 2214: (match_operand:SI 3 "const_int_operand" "i")))] 2215: "INTVAL (operands[1]) == - INTVAL (operands[3]) 2216: && INTVAL (operands[3]) >= -8 && INTVAL (operands[3]) < 8" 2217: "acbd %3,%0,%l2") 2218: 2219: (define_insn "call" 2220: [(call (match_operand:QI 0 "memory_operand" "m") 2221: (match_operand:QI 1 "general_operand" "g"))] 2222: "" 2223: "* 2224: { 2225: #ifndef JSR_ALWAYS 2226: if (GET_CODE (operands[0]) == MEM) 2227: { 2228: rtx temp = XEXP (operands[0], 0); 2229: if (CONSTANT_ADDRESS_P (temp)) 2230: { 2231: #ifdef ENCORE_ASM 2232: return \"bsr %?%0\"; 2233: #else 2234: #ifdef CALL_MEMREF_IMPLICIT 2235: operands[0] = temp; 2236: return \"bsr %0\"; 2237: #else 2238: #ifdef GNX_V3 2239: return \"bsr %0\"; 2240: #else 2241: return \"bsr %?%a0\"; 2242: #endif 2243: #endif 2244: #endif 2245: } 2246: if (GET_CODE (XEXP (operands[0], 0)) == REG) 2247: #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT) 2248: return \"jsr %0\"; 2249: #else 2250: return \"jsr %a0\"; 2251: #endif 2252: } 2253: #endif /* not JSR_ALWAYS */ 2254: return \"jsr %0\"; 2255: }") 2256: 2257: (define_insn "call_value" 2258: [(set (match_operand 0 "" "=rf") 2259: (call (match_operand:QI 1 "memory_operand" "m") 2260: (match_operand:QI 2 "general_operand" "g")))] 2261: "" 2262: "* 2263: { 2264: #ifndef JSR_ALWAYS 2265: if (GET_CODE (operands[1]) == MEM) 2266: { 2267: rtx temp = XEXP (operands[1], 0); 2268: if (CONSTANT_ADDRESS_P (temp)) 2269: { 2270: #ifdef ENCORE_ASM 2271: return \"bsr %?%1\"; 2272: #else 2273: #ifdef CALL_MEMREF_IMPLICIT 2274: operands[1] = temp; 2275: return \"bsr %1\"; 2276: #else 2277: #ifdef GNX_V3 2278: return \"bsr %1\"; 2279: #else 2280: return \"bsr %?%a1\"; 2281: #endif 2282: #endif 2283: #endif 2284: } 2285: if (GET_CODE (XEXP (operands[1], 0)) == REG) 2286: #if defined (GNX_V3) || defined (CALL_MEMREF_IMPLICIT) 2287: return \"jsr %1\"; 2288: #else 2289: return \"jsr %a1\"; 2290: #endif 2291: } 2292: #endif /* not JSR_ALWAYS */ 2293: return \"jsr %1\"; 2294: }") 2295: 2296: ;; Call subroutine returning any type. 2297: 2298: (define_expand "untyped_call" 2299: [(parallel [(call (match_operand 0 "" "") 2300: (const_int 0)) 2301: (match_operand 1 "" "") 2302: (match_operand 2 "" "")])] 2303: "" 2304: " 2305: { 2306: int i; 2307: 2308: emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx)); 2309: 2310: for (i = 0; i < XVECLEN (operands[2], 0); i++) 2311: { 2312: rtx set = XVECEXP (operands[2], 0, i); 2313: emit_move_insn (SET_DEST (set), SET_SRC (set)); 2314: } 2315: 2316: /* The optimizer does not know that the call sets the function value 2317: registers we stored in the result block. We avoid problems by 2318: claiming that all hard registers are used and clobbered at this 2319: point. */ 2320: emit_insn (gen_blockage ()); 2321: 2322: DONE; 2323: }") 2324: 2325: ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 2326: ;; all of memory. This blocks insns from being moved across this point. 2327: 2328: (define_insn "blockage" 2329: [(unspec_volatile [(const_int 0)] 0)] 2330: "" 2331: "") 2332: 2333: (define_insn "return" 2334: [(return)] 2335: "0" 2336: "ret 0") 2337: 2338: (define_insn "abssf2" 2339: [(set (match_operand:SF 0 "general_operand" "=fm<") 2340: (abs:SF (match_operand:SF 1 "general_operand" "fmF")))] 2341: "TARGET_32081" 2342: "absf %1,%0") 2343: 2344: (define_insn "absdf2" 2345: [(set (match_operand:DF 0 "general_operand" "=fm<") 2346: (abs:DF (match_operand:DF 1 "general_operand" "fmF")))] 2347: "TARGET_32081" 2348: "absl %1,%0") 2349: 2350: (define_insn "abssi2" 2351: [(set (match_operand:SI 0 "general_operand" "=g<") 2352: (abs:SI (match_operand:SI 1 "general_operand" "rmn")))] 2353: "" 2354: "absd %1,%0") 2355: 2356: (define_insn "abshi2" 2357: [(set (match_operand:HI 0 "general_operand" "=g<") 2358: (abs:HI (match_operand:HI 1 "general_operand" "g")))] 2359: "" 2360: "absw %1,%0") 2361: 2362: (define_insn "absqi2" 2363: [(set (match_operand:QI 0 "general_operand" "=g<") 2364: (abs:QI (match_operand:QI 1 "general_operand" "g")))] 2365: "" 2366: "absb %1,%0") 2367: 2368: (define_insn "nop" 2369: [(const_int 0)] 2370: "" 2371: "nop") 2372: 2373: (define_insn "indirect_jump" 2374: [(set (pc) (match_operand:SI 0 "register_operand" "r"))] 2375: "" 2376: "jump %0") 2377: 2378: (define_insn "tablejump" 2379: [(set (pc) 1.1.1.2 root 2380: (plus:SI (pc) (match_operand:SI 0 "general_operand" "g"))) 1.1 root 2381: (use (label_ref (match_operand 1 "" "")))] 2382: "" 2383: "* 2384: { 2385: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\", 2386: CODE_LABEL_NUMBER (operands[1])); 1.1.1.2 root 2387: return \"cased %0\"; 1.1 root 2388: }") 2389: 2390: ;; Scondi instructions 2391: (define_insn "seq" 2392: [(set (match_operand:SI 0 "general_operand" "=g<") 2393: (eq:SI (cc0) (const_int 0)))] 2394: "" 2395: "* 2396: { if (cc_prev_status.flags & CC_Z_IN_F) 2397: return \"sfcd %0\"; 2398: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) 2399: return \"sfsd %0\"; 2400: else return \"seqd %0\"; 2401: }") 2402: 2403: (define_insn "" 2404: [(set (match_operand:HI 0 "general_operand" "=g<") 2405: (eq:HI (cc0) (const_int 0)))] 2406: "" 2407: "* 2408: { if (cc_prev_status.flags & CC_Z_IN_F) 2409: return \"sfcw %0\"; 2410: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) 2411: return \"sfsw %0\"; 2412: else return \"seqw %0\"; 2413: }") 2414: 2415: (define_insn "" 2416: [(set (match_operand:QI 0 "general_operand" "=g<") 2417: (eq:QI (cc0) (const_int 0)))] 2418: "" 2419: "* 2420: { if (cc_prev_status.flags & CC_Z_IN_F) 2421: return \"sfcb %0\"; 2422: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) 2423: return \"sfsb %0\"; 2424: else return \"seqb %0\"; 2425: }") 2426: 2427: (define_insn "sne" 2428: [(set (match_operand:SI 0 "general_operand" "=g<") 2429: (ne:SI (cc0) (const_int 0)))] 2430: "" 2431: "* 2432: { if (cc_prev_status.flags & CC_Z_IN_F) 2433: return \"sfsd %0\"; 2434: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) 2435: return \"sfcd %0\"; 2436: else return \"sned %0\"; 2437: }") 2438: 2439: (define_insn "" 2440: [(set (match_operand:HI 0 "general_operand" "=g<") 2441: (ne:HI (cc0) (const_int 0)))] 2442: "" 2443: "* 2444: { if (cc_prev_status.flags & CC_Z_IN_F) 2445: return \"sfsw %0\"; 2446: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) 2447: return \"sfcw %0\"; 2448: else return \"snew %0\"; 2449: }") 2450: 2451: (define_insn "" 2452: [(set (match_operand:QI 0 "general_operand" "=g<") 2453: (ne:QI (cc0) (const_int 0)))] 2454: "" 2455: "* 2456: { if (cc_prev_status.flags & CC_Z_IN_F) 2457: return \"sfsb %0\"; 2458: else if (cc_prev_status.flags & CC_Z_IN_NOT_F) 2459: return \"sfcb %0\"; 2460: else return \"sneb %0\"; 2461: }") 2462: 2463: (define_insn "sgt" 2464: [(set (match_operand:SI 0 "general_operand" "=g<") 2465: (gt:SI (cc0) (const_int 0)))] 2466: "" 2467: "sgtd %0") 2468: 2469: (define_insn "" 2470: [(set (match_operand:HI 0 "general_operand" "=g<") 2471: (gt:HI (cc0) (const_int 0)))] 2472: "" 2473: "sgtw %0") 2474: 2475: (define_insn "" 2476: [(set (match_operand:QI 0 "general_operand" "=g<") 2477: (gt:QI (cc0) (const_int 0)))] 2478: "" 2479: "sgtb %0") 2480: 2481: (define_insn "sgtu" 2482: [(set (match_operand:SI 0 "general_operand" "=g<") 2483: (gtu:SI (cc0) (const_int 0)))] 2484: "" 2485: "shid %0") 2486: 2487: (define_insn "" 2488: [(set (match_operand:HI 0 "general_operand" "=g<") 2489: (gtu:HI (cc0) (const_int 0)))] 2490: "" 2491: "shiw %0") 2492: 2493: (define_insn "" 2494: [(set (match_operand:QI 0 "general_operand" "=g<") 2495: (gtu:QI (cc0) (const_int 0)))] 2496: "" 2497: "shib %0") 2498: 2499: (define_insn "slt" 2500: [(set (match_operand:SI 0 "general_operand" "=g<") 2501: (lt:SI (cc0) (const_int 0)))] 2502: "" 2503: "sltd %0") 2504: 2505: (define_insn "" 2506: [(set (match_operand:HI 0 "general_operand" "=g<") 2507: (lt:HI (cc0) (const_int 0)))] 2508: "" 2509: "sltw %0") 2510: 2511: (define_insn "" 2512: [(set (match_operand:QI 0 "general_operand" "=g<") 2513: (lt:QI (cc0) (const_int 0)))] 2514: "" 2515: "sltb %0") 2516: 2517: (define_insn "sltu" 2518: [(set (match_operand:SI 0 "general_operand" "=g<") 2519: (ltu:SI (cc0) (const_int 0)))] 2520: "" 2521: "slod %0") 2522: 2523: (define_insn "" 2524: [(set (match_operand:HI 0 "general_operand" "=g<") 2525: (ltu:HI (cc0) (const_int 0)))] 2526: "" 2527: "slow %0") 2528: 2529: (define_insn "" 2530: [(set (match_operand:QI 0 "general_operand" "=g<") 2531: (ltu:QI (cc0) (const_int 0)))] 2532: "" 2533: "slob %0") 2534: 2535: (define_insn "sge" 2536: [(set (match_operand:SI 0 "general_operand" "=g<") 2537: (ge:SI (cc0) (const_int 0)))] 2538: "" 2539: "sged %0") 2540: 2541: (define_insn "" 2542: [(set (match_operand:HI 0 "general_operand" "=g<") 2543: (ge:HI (cc0) (const_int 0)))] 2544: "" 2545: "sgew %0") 2546: 2547: (define_insn "" 2548: [(set (match_operand:QI 0 "general_operand" "=g<") 2549: (ge:QI (cc0) (const_int 0)))] 2550: "" 2551: "sgeb %0") 2552: 2553: (define_insn "sgeu" 2554: [(set (match_operand:SI 0 "general_operand" "=g<") 2555: (geu:SI (cc0) (const_int 0)))] 2556: "" 2557: "shsd %0") 2558: 2559: (define_insn "" 2560: [(set (match_operand:HI 0 "general_operand" "=g<") 2561: (geu:HI (cc0) (const_int 0)))] 2562: "" 2563: "shsw %0") 2564: 2565: (define_insn "" 2566: [(set (match_operand:QI 0 "general_operand" "=g<") 2567: (geu:QI (cc0) (const_int 0)))] 2568: "" 2569: "shsb %0") 2570: 2571: (define_insn "sle" 2572: [(set (match_operand:SI 0 "general_operand" "=g<") 2573: (le:SI (cc0) (const_int 0)))] 2574: "" 2575: "sled %0") 2576: 2577: (define_insn "" 2578: [(set (match_operand:HI 0 "general_operand" "=g<") 2579: (le:HI (cc0) (const_int 0)))] 2580: "" 2581: "slew %0") 2582: 2583: (define_insn "" 2584: [(set (match_operand:QI 0 "general_operand" "=g<") 2585: (le:QI (cc0) (const_int 0)))] 2586: "" 2587: "sleb %0") 2588: 2589: (define_insn "sleu" 2590: [(set (match_operand:SI 0 "general_operand" "=g<") 2591: (leu:SI (cc0) (const_int 0)))] 2592: "" 2593: "slsd %0") 2594: 2595: (define_insn "" 2596: [(set (match_operand:HI 0 "general_operand" "=g<") 2597: (leu:HI (cc0) (const_int 0)))] 2598: "" 2599: "slsw %0") 2600: 2601: (define_insn "" 2602: [(set (match_operand:QI 0 "general_operand" "=g<") 2603: (leu:QI (cc0) (const_int 0)))] 2604: "" 2605: "slsb %0") 1.1.1.2 root 2606: 1.1.1.3 ! root 2607: ;; ffs instructions ! 2608: ! 2609: (define_insn "ffsqi2" ! 2610: [(set (match_operand:QI 0 "general_operand" "=g") ! 2611: (ffs:QI (match_operand:SI 1 "general_operand" "g")))] ! 2612: "" ! 2613: "* ! 2614: { ! 2615: return \"movqb 0,%0; ffsd %1,%0; bfs 1f; addqb 1,%0; 1:\"; ! 2616: }") ! 2617: ! 2618: (define_insn "ffshi2" ! 2619: [(set (match_operand:HI 0 "general_operand" "=g") ! 2620: (ffs:HI (match_operand:SI 1 "general_operand" "g")))] ! 2621: "" ! 2622: "* ! 2623: { ! 2624: return \"movqw 0,%0; ffsd %1,%0; bfs 1f; addqw 1,%0; 1:\"; ! 2625: }") ! 2626: ! 2627: (define_insn "ffssi2" ! 2628: [(set (match_operand:SI 0 "general_operand" "=g") ! 2629: (ffs:SI (match_operand:SI 1 "general_operand" "g")))] ! 2630: "" ! 2631: "* ! 2632: { ! 2633: return \"movqd 0,%0; ffsd %1,%0; bfs 1f; addqd 1,%0; 1:\"; ! 2634: }") ! 2635: ! 2636: ;; Speed up stack adjust followed by a HI fixedpoint push. ! 2637: ! 2638: (define_peephole ! 2639: [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int -2))) ! 2640: (set (match_operand:HI 0 "push_operand" "=m") ! 2641: (match_operand:HI 1 "general_operand" "g"))] ! 2642: "! reg_mentioned_p (stack_pointer_rtx, operands[1])" ! 2643: "* ! 2644: { ! 2645: if (GET_CODE (operands[1]) == CONST_INT) ! 2646: output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,tos\"), ! 2647: operands); ! 2648: else ! 2649: output_asm_insn (\"movzwd %1,tos\", operands); ! 2650: return \"\"; ! 2651: }") ! 2652: ! 2653: ;; Speed up stack adjust followed by a zero_extend:HI(QI) fixedpoint push. ! 2654: ! 2655: (define_peephole ! 2656: [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int -2))) ! 2657: (set (match_operand:HI 0 "push_operand" "=m") ! 2658: (zero_extend:HI (match_operand:QI 1 "general_operand" "g")))] ! 2659: "! reg_mentioned_p (stack_pointer_rtx, operands[1])" ! 2660: "* ! 2661: { ! 2662: if (GET_CODE (operands[1]) == CONST_INT) ! 2663: output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,tos\"), ! 2664: operands); ! 2665: else ! 2666: output_asm_insn (\"movzbd %1,tos\", operands); ! 2667: return \"\"; ! 2668: }") ! 2669: ! 2670: ;; Speed up stack adjust followed by a sign_extend:HI(QI) fixedpoint push. ! 2671: ! 2672: (define_peephole ! 2673: [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int -2))) ! 2674: (set (match_operand:HI 0 "push_operand" "=m") ! 2675: (sign_extend:HI (match_operand:QI 1 "general_operand" "g")))] ! 2676: "! reg_mentioned_p (stack_pointer_rtx, operands[1])" ! 2677: "* ! 2678: { ! 2679: if (GET_CODE (operands[1]) == CONST_INT) ! 2680: output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,tos\"), ! 2681: operands); ! 2682: else ! 2683: output_asm_insn (\"movxbd %1,tos\", operands); ! 2684: return \"\"; ! 2685: }") ! 2686: ! 2687: ;; Speed up stack adjust followed by a QI fixedpoint push. ! 2688: ! 2689: (define_peephole ! 2690: [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int -3))) ! 2691: (set (match_operand:QI 0 "push_operand" "=m") ! 2692: (match_operand:QI 1 "general_operand" "g"))] ! 2693: "! reg_mentioned_p (stack_pointer_rtx, operands[1])" ! 2694: "* ! 2695: { ! 2696: if (GET_CODE (operands[1]) == CONST_INT) ! 2697: output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,tos\"), ! 2698: operands); ! 2699: else ! 2700: output_asm_insn (\"movzbd %1,tos\", operands); ! 2701: return \"\"; ! 2702: }") ! 2703: ! 2704: ;; Speed up stack adjust followed by a SI fixedpoint push. 1.1.1.2 root 2705: 2706: (define_peephole 2707: [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int 4))) 2708: (set (match_operand:SI 0 "push_operand" "=m") 2709: (match_operand:SI 1 "general_operand" "g"))] 2710: "! reg_mentioned_p (stack_pointer_rtx, operands[1])" 2711: "* 2712: { 1.1.1.3 ! root 2713: if (GET_CODE (operands[1]) == CONST_INT) ! 2714: output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,0(sp)\"), ! 2715: operands); ! 2716: else if (GET_CODE (operands[1]) != REG ! 2717: && GET_CODE (operands[1]) != MEM ! 2718: && address_operand (operands[1], SImode)) ! 2719: output_asm_insn (\"addr %a1,0(sp)\", operands); ! 2720: else ! 2721: output_asm_insn (\"movd %1,0(sp)\", operands); ! 2722: return \"\"; 1.1.1.2 root 2723: }") 2724: 2725: ;; Speed up stack adjust followed by two fullword fixedpoint pushes. 2726: 2727: (define_peephole 2728: [(set (reg:SI 17) (plus:SI (reg:SI 17) (const_int 8))) 2729: (set (match_operand:SI 0 "push_operand" "=m") 2730: (match_operand:SI 1 "general_operand" "g")) 2731: (set (match_operand:SI 2 "push_operand" "=m") 2732: (match_operand:SI 3 "general_operand" "g"))] 2733: "! reg_mentioned_p (stack_pointer_rtx, operands[1]) 2734: && ! reg_mentioned_p (stack_pointer_rtx, operands[3])" 2735: "* 2736: { 1.1.1.3 ! root 2737: if (GET_CODE (operands[1]) == CONST_INT) ! 2738: output_asm_insn (output_move_dconst (INTVAL (operands[1]), \"%$%1,4(sp)\"), ! 2739: operands); ! 2740: else if (GET_CODE (operands[1]) != REG ! 2741: && GET_CODE (operands[1]) != MEM ! 2742: && address_operand (operands[1], SImode)) ! 2743: output_asm_insn (\"addr %a1,4(sp)\", operands); ! 2744: else ! 2745: output_asm_insn (\"movd %1,4(sp)\", operands); 1.1.1.2 root 2746: 1.1.1.3 ! root 2747: if (GET_CODE (operands[3]) == CONST_INT) ! 2748: output_asm_insn (output_move_dconst (INTVAL (operands[3]), \"%$%3,0(sp)\"), ! 2749: operands); ! 2750: else if (GET_CODE (operands[3]) != REG ! 2751: && GET_CODE (operands[3]) != MEM ! 2752: && address_operand (operands[3], SImode)) ! 2753: output_asm_insn (\"addr %a3,0(sp)\", operands); ! 2754: else ! 2755: output_asm_insn (\"movd %3,0(sp)\", operands); ! 2756: return \"\"; ! 2757: }")
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