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1.1 root 1: /* Subroutines for insn-output.c for Motorola 68000 family.
2: Copyright (C) 1987 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 1, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: /* Some output-actions in m68k.md need these. */
22: #include <stdio.h>
23: extern FILE *asm_out_file;
24:
25: /* Index into this array by (register number >> 3) to find the
26: smallest class which contains that register. */
27: enum reg_class regno_reg_class[]
28: = { DATA_REGS, ADDR_REGS, FP_REGS,
29: LO_FPA_REGS, LO_FPA_REGS, FPA_REGS, FPA_REGS };
30:
31: static rtx find_addr_reg ();
32:
33: char *
34: output_btst (operands, countop, dataop, insn, signpos)
35: rtx *operands;
36: rtx countop, dataop;
37: rtx insn;
38: int signpos;
39: {
40: operands[0] = countop;
41: operands[1] = dataop;
42:
43: if (GET_CODE (countop) == CONST_INT)
44: {
45: register int count = INTVAL (countop);
46: /* If COUNT is bigger than size of storage unit in use,
47: advance to the containing unit of same size. */
48: if (count > signpos)
49: {
50: int offset = (count & ~signpos) / 8;
51: count = count & signpos;
52: operands[1] = dataop = adj_offsettable_operand (dataop, offset);
53: }
54: if (count == signpos)
55: cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
56: else
57: cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
58:
59: if (count == 31
60: && next_insns_test_no_inequality (insn))
61: return "tst%.l %1";
62: if (count == 15
63: && next_insns_test_no_inequality (insn))
64: return "tst%.w %1";
65: if (count == 7
66: && next_insns_test_no_inequality (insn))
67: return "tst%.b %1";
68:
69: cc_status.flags = CC_NOT_NEGATIVE;
70: }
71: return "btst %0,%1";
72: }
73:
74: /* Return the best assembler insn template
75: for moving operands[1] into operands[0] as a fullword. */
76:
77: static char *
78: singlemove_string (operands)
79: rtx *operands;
80: {
81: if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
82: return "fpmoves %1,%0";
83: if (operands[1] != const0_rtx)
84: return "move%.l %1,%0";
85: if (! ADDRESS_REG_P (operands[0]))
86: return "clr%.l %0";
87: return "sub%.l %0,%0";
88: }
89:
90: /* Output assembler code to perform a doubleword move insn
91: with operands OPERANDS. */
92:
93: char *
94: output_move_double (operands)
95: rtx *operands;
96: {
97: enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
98: rtx latehalf[2];
99: rtx addreg0 = 0, addreg1 = 0;
100:
101: /* First classify both operands. */
102:
103: if (REG_P (operands[0]))
104: optype0 = REGOP;
105: else if (offsettable_memref_p (operands[0]))
106: optype0 = OFFSOP;
107: else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
108: optype0 = POPOP;
109: else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
110: optype0 = PUSHOP;
111: else if (GET_CODE (operands[0]) == MEM)
112: optype0 = MEMOP;
113: else
114: optype0 = RNDOP;
115:
116: if (REG_P (operands[1]))
117: optype1 = REGOP;
118: else if (CONSTANT_P (operands[1])
119: || GET_CODE (operands[1]) == CONST_DOUBLE)
120: optype1 = CNSTOP;
121: else if (offsettable_memref_p (operands[1]))
122: optype1 = OFFSOP;
123: else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
124: optype1 = POPOP;
125: else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
126: optype1 = PUSHOP;
127: else if (GET_CODE (operands[1]) == MEM)
128: optype1 = MEMOP;
129: else
130: optype1 = RNDOP;
131:
132: /* Check for the cases that the operand constraints are not
133: supposed to allow to happen. Abort if we get one,
134: because generating code for these cases is painful. */
135:
136: if (optype0 == RNDOP || optype1 == RNDOP)
137: abort ();
138:
139: /* If one operand is decrementing and one is incrementing
140: decrement the former register explicitly
141: and change that operand into ordinary indexing. */
142:
143: if (optype0 == PUSHOP && optype1 == POPOP)
144: {
145: operands[0] = XEXP (XEXP (operands[0], 0), 0);
146: output_asm_insn ("subq%.l %#8,%0", operands);
147: operands[0] = gen_rtx (MEM, DImode, operands[0]);
148: optype0 = OFFSOP;
149: }
150: if (optype0 == POPOP && optype1 == PUSHOP)
151: {
152: operands[1] = XEXP (XEXP (operands[1], 0), 0);
153: output_asm_insn ("subq%.l %#8,%1", operands);
154: operands[1] = gen_rtx (MEM, DImode, operands[1]);
155: optype1 = OFFSOP;
156: }
157:
158: /* If an operand is an unoffsettable memory ref, find a register
159: we can increment temporarily to make it refer to the second word. */
160:
161: if (optype0 == MEMOP)
162: addreg0 = find_addr_reg (XEXP (operands[0], 0));
163:
164: if (optype1 == MEMOP)
165: addreg1 = find_addr_reg (XEXP (operands[1], 0));
166:
167: /* Ok, we can do one word at a time.
168: Normally we do the low-numbered word first,
169: but if either operand is autodecrementing then we
170: do the high-numbered word first.
171:
172: In either case, set up in LATEHALF the operands to use
173: for the high-numbered word and in some cases alter the
174: operands in OPERANDS to be suitable for the low-numbered word. */
175:
176: if (optype0 == REGOP)
177: latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
178: else if (optype0 == OFFSOP)
179: latehalf[0] = adj_offsettable_operand (operands[0], 4);
180: else
181: latehalf[0] = operands[0];
182:
183: if (optype1 == REGOP)
184: latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
185: else if (optype1 == OFFSOP)
186: latehalf[1] = adj_offsettable_operand (operands[1], 4);
187: else if (optype1 == CNSTOP)
188: {
189: if (CONSTANT_P (operands[1]))
190: latehalf[1] = const0_rtx;
191: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
192: {
193: latehalf[1] = gen_rtx (CONST_INT, VOIDmode,
194: CONST_DOUBLE_HIGH (operands[1]));
195: operands[1] = gen_rtx (CONST_INT, VOIDmode,
196: CONST_DOUBLE_LOW (operands[1]));
1.1.1.2 ! root 197: #if 0 /* not HOST_WORDS_BIG_ENDIAN */
! 198: latehalf[1] = gen_rtx (CONST_INT, VOIDmode,
! 199: CONST_DOUBLE_LOW (operands[1]));
! 200: operands[1] = gen_rtx (CONST_INT, VOIDmode,
! 201: CONST_DOUBLE_HIGH (operands[1]));
! 202: #endif /* not HOST_WORDS_BIG_ENDIAN */
1.1 root 203: }
204: }
205: else
206: latehalf[1] = operands[1];
207:
208: /* If insn is effectively movd N(sp),-(sp) then we will do the
209: high word first. We should use the adjusted operand 1 (which is N+4(sp))
210: for the low word as well, to compensate for the first decrement of sp. */
211: if (optype0 == PUSHOP
212: && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
213: && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
214: operands[1] = latehalf[1];
215:
216: /* If one or both operands autodecrementing,
217: do the two words, high-numbered first. */
218:
219: /* Likewise, the first move would clobber the source of the second one,
220: do them in the other order. This happens only for registers;
221: such overlap can't happen in memory unless the user explicitly
222: sets it up, and that is an undefined circumstance. */
223:
224: if (optype0 == PUSHOP || optype1 == PUSHOP
225: || (optype0 == REGOP && optype1 == REGOP
226: && REGNO (operands[0]) == REGNO (latehalf[1])))
227: {
228: /* Make any unoffsettable addresses point at high-numbered word. */
229: if (addreg0)
230: output_asm_insn ("addql %#4,%0", &addreg0);
231: if (addreg1)
232: output_asm_insn ("addql %#4,%0", &addreg1);
233:
234: /* Do that word. */
235: output_asm_insn (singlemove_string (latehalf), latehalf);
236:
237: /* Undo the adds we just did. */
238: if (addreg0)
239: output_asm_insn ("subql %#4,%0", &addreg0);
240: if (addreg1)
241: output_asm_insn ("subql %#4,%0", &addreg1);
242:
243: /* Do low-numbered word. */
244: return singlemove_string (operands);
245: }
246:
247: /* Normal case: do the two words, low-numbered first. */
248:
249: output_asm_insn (singlemove_string (operands), operands);
250:
251: /* Make any unoffsettable addresses point at high-numbered word. */
252: if (addreg0)
253: output_asm_insn ("addql %#4,%0", &addreg0);
254: if (addreg1)
255: output_asm_insn ("addql %#4,%0", &addreg1);
256:
257: /* Do that word. */
258: output_asm_insn (singlemove_string (latehalf), latehalf);
259:
260: /* Undo the adds we just did. */
261: if (addreg0)
262: output_asm_insn ("subql %#4,%0", &addreg0);
263: if (addreg1)
264: output_asm_insn ("subql %#4,%0", &addreg1);
265:
266: return "";
267: }
268:
269: /* Return a REG that occurs in ADDR with coefficient 1.
270: ADDR can be effectively incremented by incrementing REG. */
271:
272: static rtx
273: find_addr_reg (addr)
274: rtx addr;
275: {
276: while (GET_CODE (addr) == PLUS)
277: {
278: if (GET_CODE (XEXP (addr, 0)) == REG)
279: addr = XEXP (addr, 0);
280: else if (GET_CODE (XEXP (addr, 1)) == REG)
281: addr = XEXP (addr, 1);
282: else if (CONSTANT_P (XEXP (addr, 0)))
283: addr = XEXP (addr, 1);
284: else if (CONSTANT_P (XEXP (addr, 1)))
285: addr = XEXP (addr, 0);
286: else
287: abort ();
288: }
289: if (GET_CODE (addr) == REG)
290: return addr;
291: abort ();
292: }
293:
1.1.1.2 ! root 294: /* Test for -0.0. */
! 295:
! 296: int
! 297: double_is_minus_zero (arg)
! 298: double arg;
! 299: {
! 300: union { double d; int i[2];} u;
! 301:
! 302: u.d = arg;
! 303: return (u.i[1] == 0 && u.i[0] == 0x80000000);
! 304: }
! 305:
1.1 root 306: char *
307: output_move_const_double (operands)
308: rtx *operands;
309: {
310: if (TARGET_FPA && FPA_REG_P(operands[0]))
311: {
312: int code = standard_sun_fpa_constant_p (operands[1]);
313:
314: if (code != 0)
315: {
316: static char buf[40];
317:
318: sprintf (buf, "fpmove%%.d %%%%%d,%%0", code & 0x1ff);
319: return buf;
320: }
321: return "fpmove%.d %1,%0";
322: }
323: else
324: {
325: int code = standard_68881_constant_p (operands[1]);
326:
327: if (code != 0)
328: {
329: static char buf[40];
330:
331: sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
332: return buf;
333: }
334: return "fmove%.d %1,%0";
335: }
336: }
337:
338: char *
339: output_move_const_single (operands)
340: rtx *operands;
341: {
342: if (TARGET_FPA)
343: {
344: int code = standard_sun_fpa_constant_p (operands[1]);
345:
346: if (code != 0)
347: {
348: static char buf[40];
349:
350: sprintf (buf, "fpmove%%.s %%%%%d,%%0", code & 0x1ff);
351: return buf;
352: }
353: return "fpmove%.s %1,%0";
354: }
355: else
356: {
357: int code = standard_68881_constant_p (operands[1]);
358:
359: if (code != 0)
360: {
361: static char buf[40];
362:
363: sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
364: return buf;
365: }
366: return "fmove%.s %f1,%0";
367: }
368: }
369:
370: /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
371: from the "fmovecr" instruction.
372: The value, anded with 0xff, gives the code to use in fmovecr
373: to get the desired constant. */
374:
375: int
376: standard_68881_constant_p (x)
377: rtx x;
378: {
379: union {double d; int i[2];} u;
380: register double d;
1.1.1.2 ! root 381:
! 382: #ifdef HOST_WORDS_BIG_ENDIAN
1.1 root 383: u.i[0] = CONST_DOUBLE_LOW (x);
384: u.i[1] = CONST_DOUBLE_HIGH (x);
1.1.1.2 ! root 385: #else
! 386: u.i[0] = CONST_DOUBLE_HIGH (x);
! 387: u.i[1] = CONST_DOUBLE_LOW (x);
! 388: #endif
1.1 root 389: d = u.d;
390:
391: if (d == 0)
392: return 0x0f;
393: /* Note: there are various other constants available
394: but it is a nuisance to put in their values here. */
395: if (d == 1)
396: return 0x32;
397: if (d == 10)
398: return 0x33;
399: if (d == 100)
400: return 0x34;
401: if (d == 10000)
402: return 0x35;
403: if (d == 1e8)
404: return 0x36;
405: if (GET_MODE (x) == SFmode)
406: return 0;
407: if (d == 1e16)
408: return 0x37;
409: /* larger powers of ten in the constants ram are not used
410: because they are not equal to a `double' C constant. */
411: return 0;
412: }
413:
414: /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
415: from the Sun FPA's constant RAM.
416: The value returned, anded with 0x1ff, gives the code to use in fpmove
417: to get the desired constant. */
418: #define S_E (2.718281745910644531)
419: #define D_E (2.718281828459045091)
420: #define S_PI (3.141592741012573242)
421: #define D_PI (3.141592653589793116)
422: #define S_SQRT2 (1.414213538169860840)
423: #define D_SQRT2 (1.414213562373095145)
424: #define S_LOG2ofE (1.442695021629333496)
425: #define D_LOG2ofE (1.442695040888963387)
426: #define S_LOG2of10 (3.321928024291992188)
427: #define D_LOG2of10 (3.321928024887362182)
428: #define S_LOGEof2 (0.6931471824645996094)
429: #define D_LOGEof2 (0.6931471805599452862)
430: #define S_LOGEof10 (2.302585124969482442)
431: #define D_LOGEof10 (2.302585092994045901)
432: #define S_LOG10of2 (0.3010300099849700928)
433: #define D_LOG10of2 (0.3010299956639811980)
434: #define S_LOG10ofE (0.4342944920063018799)
435: #define D_LOG10ofE (0.4342944819032518167)
436:
437: int
438: standard_sun_fpa_constant_p (x)
439: rtx x;
440: {
441: union {double d; int i[2];} u;
442: register double d;
443: u.i[0] = CONST_DOUBLE_LOW (x);
444: u.i[1] = CONST_DOUBLE_HIGH (x);
445: d = u.d;
446:
447: if (d == 0.0)
448: return 0x200; /* 0 once 0x1ff is anded with it */
449: if (d == 1.0)
450: return 0xe;
451: if (d == 0.5)
452: return 0xf;
453: if (d == -1.0)
454: return 0x10;
455: if (d == 2.0)
456: return 0x11;
457: if (d == 3.0)
458: return 0xB1;
459: if (d == 4.0)
460: return 0x12;
461: if (d == 8.0)
462: return 0x13;
463: if (d == 0.25)
464: return 0x15;
465: if (d == 0.125)
466: return 0x16;
467: if (d == 10.0)
468: return 0x17;
469: if (d == -(1.0/2.0))
470: return 0x2E;
471:
472: /*
473: * Stuff that looks different if it's single or double
474: */
475: if (GET_MODE(x) == SFmode)
476: {
477: if (d == S_E)
478: return 0x8;
479: if (d == (2*S_PI))
480: return 0x9;
481: if (d == S_PI)
482: return 0xA;
483: if (d == (S_PI / 2.0))
484: return 0xB;
485: if (d == S_SQRT2)
486: return 0xC;
487: if (d == (1.0 / S_SQRT2))
488: return 0xD;
489: /* Large powers of 10 in the constant
490: ram are not used because they are
491: not equal to a C double constant */
492: if (d == -(S_PI / 2.0))
493: return 0x27;
494: if (d == S_LOG2ofE)
495: return 0x28;
496: if (d == S_LOG2of10)
497: return 0x29;
498: if (d == S_LOGEof2)
499: return 0x2A;
500: if (d == S_LOGEof10)
501: return 0x2B;
502: if (d == S_LOG10of2)
503: return 0x2C;
504: if (d == S_LOG10ofE)
505: return 0x2D;
506: }
507: else
508: {
509: if (d == D_E)
510: return 0x8;
511: if (d == (2*D_PI))
512: return 0x9;
513: if (d == D_PI)
514: return 0xA;
515: if (d == (D_PI / 2.0))
516: return 0xB;
517: if (d == D_SQRT2)
518: return 0xC;
519: if (d == (1.0 / D_SQRT2))
520: return 0xD;
521: /* Large powers of 10 in the constant
522: ram are not used because they are
523: not equal to a C double constant */
524: if (d == -(D_PI / 2.0))
525: return 0x27;
526: if (d == D_LOG2ofE)
527: return 0x28;
528: if (d == D_LOG2of10)
529: return 0x29;
530: if (d == D_LOGEof2)
531: return 0x2A;
532: if (d == D_LOGEof10)
533: return 0x2B;
534: if (d == D_LOG10of2)
535: return 0x2C;
536: if (d == D_LOG10ofE)
537: return 0x2D;
538: }
539: return 0x0;
540: }
541:
542: #undef S_E
543: #undef D_E
544: #undef S_PI
545: #undef D_PI
546: #undef S_SQRT2
547: #undef D_SQRT2
548: #undef S_LOG2ofE
549: #undef D_LOG2ofE
550: #undef S_LOG2of10
551: #undef D_LOG2of10
552: #undef S_LOGEof2
553: #undef D_LOGEof2
554: #undef S_LOGEof10
555: #undef D_LOGEof10
556: #undef S_LOG10of2
557: #undef D_LOG10of2
558: #undef S_LOG10ofE
559: #undef D_LOG10ofE
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