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1.1 root 1: /* Subroutines for insn-output.c for Motorola 68000 family.
2: Copyright (C) 1987 Free Software Foundation, Inc.
3:
4: This file is part of GNU CC.
5:
6: GNU CC is free software; you can redistribute it and/or modify
7: it under the terms of the GNU General Public License as published by
8: the Free Software Foundation; either version 1, or (at your option)
9: any later version.
10:
11: GNU CC is distributed in the hope that it will be useful,
12: but WITHOUT ANY WARRANTY; without even the implied warranty of
13: MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: GNU General Public License for more details.
15:
16: You should have received a copy of the GNU General Public License
17: along with GNU CC; see the file COPYING. If not, write to
18: the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */
19:
20:
21: /* Some output-actions in m68k.md need these. */
22: #include <stdio.h>
23: extern FILE *asm_out_file;
24:
25: /* Index into this array by (register number >> 3) to find the
26: smallest class which contains that register. */
27: enum reg_class regno_reg_class[]
28: = { DATA_REGS, ADDR_REGS, FP_REGS,
29: LO_FPA_REGS, LO_FPA_REGS, FPA_REGS, FPA_REGS };
30:
31: static rtx find_addr_reg ();
32:
33: char *
34: output_btst (operands, countop, dataop, insn, signpos)
35: rtx *operands;
36: rtx countop, dataop;
37: rtx insn;
38: int signpos;
39: {
40: operands[0] = countop;
41: operands[1] = dataop;
42:
43: if (GET_CODE (countop) == CONST_INT)
44: {
45: register int count = INTVAL (countop);
46: /* If COUNT is bigger than size of storage unit in use,
47: advance to the containing unit of same size. */
48: if (count > signpos)
49: {
50: int offset = (count & ~signpos) / 8;
51: count = count & signpos;
52: operands[1] = dataop = adj_offsettable_operand (dataop, offset);
53: }
54: if (count == signpos)
55: cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N;
56: else
57: cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N;
58:
59: if (count == 31
60: && next_insns_test_no_inequality (insn))
61: return "tst%.l %1";
62: if (count == 15
63: && next_insns_test_no_inequality (insn))
64: return "tst%.w %1";
65: if (count == 7
66: && next_insns_test_no_inequality (insn))
67: return "tst%.b %1";
68:
69: cc_status.flags = CC_NOT_NEGATIVE;
70: }
71: return "btst %0,%1";
72: }
73:
74: /* Return the best assembler insn template
75: for moving operands[1] into operands[0] as a fullword. */
76:
77: static char *
78: singlemove_string (operands)
79: rtx *operands;
80: {
81: if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
82: return "fpmoves %1,%0";
83: if (operands[1] != const0_rtx)
84: return "move%.l %1,%0";
85: if (! ADDRESS_REG_P (operands[0]))
86: return "clr%.l %0";
87: return "sub%.l %0,%0";
88: }
89:
90: /* Output assembler code to perform a doubleword move insn
91: with operands OPERANDS. */
92:
93: char *
94: output_move_double (operands)
95: rtx *operands;
96: {
97: enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype0, optype1;
98: rtx latehalf[2];
99: rtx addreg0 = 0, addreg1 = 0;
100:
101: /* First classify both operands. */
102:
103: if (REG_P (operands[0]))
104: optype0 = REGOP;
105: else if (offsettable_memref_p (operands[0]))
106: optype0 = OFFSOP;
107: else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
108: optype0 = POPOP;
109: else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
110: optype0 = PUSHOP;
111: else if (GET_CODE (operands[0]) == MEM)
112: optype0 = MEMOP;
113: else
114: optype0 = RNDOP;
115:
116: if (REG_P (operands[1]))
117: optype1 = REGOP;
118: else if (CONSTANT_P (operands[1])
119: || GET_CODE (operands[1]) == CONST_DOUBLE)
120: optype1 = CNSTOP;
121: else if (offsettable_memref_p (operands[1]))
122: optype1 = OFFSOP;
123: else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC)
124: optype1 = POPOP;
125: else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
126: optype1 = PUSHOP;
127: else if (GET_CODE (operands[1]) == MEM)
128: optype1 = MEMOP;
129: else
130: optype1 = RNDOP;
131:
132: /* Check for the cases that the operand constraints are not
133: supposed to allow to happen. Abort if we get one,
134: because generating code for these cases is painful. */
135:
136: if (optype0 == RNDOP || optype1 == RNDOP)
137: abort ();
138:
139: /* If one operand is decrementing and one is incrementing
140: decrement the former register explicitly
141: and change that operand into ordinary indexing. */
142:
143: if (optype0 == PUSHOP && optype1 == POPOP)
144: {
145: operands[0] = XEXP (XEXP (operands[0], 0), 0);
146: output_asm_insn ("subq%.l %#8,%0", operands);
147: operands[0] = gen_rtx (MEM, DImode, operands[0]);
148: optype0 = OFFSOP;
149: }
150: if (optype0 == POPOP && optype1 == PUSHOP)
151: {
152: operands[1] = XEXP (XEXP (operands[1], 0), 0);
153: output_asm_insn ("subq%.l %#8,%1", operands);
154: operands[1] = gen_rtx (MEM, DImode, operands[1]);
155: optype1 = OFFSOP;
156: }
157:
158: /* If an operand is an unoffsettable memory ref, find a register
159: we can increment temporarily to make it refer to the second word. */
160:
161: if (optype0 == MEMOP)
162: addreg0 = find_addr_reg (XEXP (operands[0], 0));
163:
164: if (optype1 == MEMOP)
165: addreg1 = find_addr_reg (XEXP (operands[1], 0));
166:
167: /* Ok, we can do one word at a time.
168: Normally we do the low-numbered word first,
169: but if either operand is autodecrementing then we
170: do the high-numbered word first.
171:
172: In either case, set up in LATEHALF the operands to use
173: for the high-numbered word and in some cases alter the
174: operands in OPERANDS to be suitable for the low-numbered word. */
175:
176: if (optype0 == REGOP)
177: latehalf[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
178: else if (optype0 == OFFSOP)
179: latehalf[0] = adj_offsettable_operand (operands[0], 4);
180: else
181: latehalf[0] = operands[0];
182:
183: if (optype1 == REGOP)
184: latehalf[1] = gen_rtx (REG, SImode, REGNO (operands[1]) + 1);
185: else if (optype1 == OFFSOP)
186: latehalf[1] = adj_offsettable_operand (operands[1], 4);
187: else if (optype1 == CNSTOP)
188: {
189: if (CONSTANT_P (operands[1]))
190: latehalf[1] = const0_rtx;
191: else if (GET_CODE (operands[1]) == CONST_DOUBLE)
192: {
1.1.1.3 ! root 193: #ifndef HOST_WORDS_BIG_ENDIAN
1.1.1.2 root 194: latehalf[1] = gen_rtx (CONST_INT, VOIDmode,
195: CONST_DOUBLE_LOW (operands[1]));
196: operands[1] = gen_rtx (CONST_INT, VOIDmode,
197: CONST_DOUBLE_HIGH (operands[1]));
1.1.1.3 ! root 198: #else /* HOST_WORDS_BIG_ENDIAN */
! 199: latehalf[1] = gen_rtx (CONST_INT, VOIDmode,
! 200: CONST_DOUBLE_HIGH (operands[1]));
! 201: operands[1] = gen_rtx (CONST_INT, VOIDmode,
! 202: CONST_DOUBLE_LOW (operands[1]));
! 203: #endif /* HOST_WORDS_BIG_ENDIAN */
1.1 root 204: }
205: }
206: else
207: latehalf[1] = operands[1];
208:
209: /* If insn is effectively movd N(sp),-(sp) then we will do the
210: high word first. We should use the adjusted operand 1 (which is N+4(sp))
211: for the low word as well, to compensate for the first decrement of sp. */
212: if (optype0 == PUSHOP
213: && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
214: && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1]))
215: operands[1] = latehalf[1];
216:
217: /* If one or both operands autodecrementing,
218: do the two words, high-numbered first. */
219:
220: /* Likewise, the first move would clobber the source of the second one,
221: do them in the other order. This happens only for registers;
222: such overlap can't happen in memory unless the user explicitly
223: sets it up, and that is an undefined circumstance. */
224:
225: if (optype0 == PUSHOP || optype1 == PUSHOP
226: || (optype0 == REGOP && optype1 == REGOP
227: && REGNO (operands[0]) == REGNO (latehalf[1])))
228: {
229: /* Make any unoffsettable addresses point at high-numbered word. */
230: if (addreg0)
231: output_asm_insn ("addql %#4,%0", &addreg0);
232: if (addreg1)
233: output_asm_insn ("addql %#4,%0", &addreg1);
234:
235: /* Do that word. */
236: output_asm_insn (singlemove_string (latehalf), latehalf);
237:
238: /* Undo the adds we just did. */
239: if (addreg0)
240: output_asm_insn ("subql %#4,%0", &addreg0);
241: if (addreg1)
242: output_asm_insn ("subql %#4,%0", &addreg1);
243:
244: /* Do low-numbered word. */
245: return singlemove_string (operands);
246: }
247:
248: /* Normal case: do the two words, low-numbered first. */
249:
250: output_asm_insn (singlemove_string (operands), operands);
251:
252: /* Make any unoffsettable addresses point at high-numbered word. */
253: if (addreg0)
254: output_asm_insn ("addql %#4,%0", &addreg0);
255: if (addreg1)
256: output_asm_insn ("addql %#4,%0", &addreg1);
257:
258: /* Do that word. */
259: output_asm_insn (singlemove_string (latehalf), latehalf);
260:
261: /* Undo the adds we just did. */
262: if (addreg0)
263: output_asm_insn ("subql %#4,%0", &addreg0);
264: if (addreg1)
265: output_asm_insn ("subql %#4,%0", &addreg1);
266:
267: return "";
268: }
269:
270: /* Return a REG that occurs in ADDR with coefficient 1.
271: ADDR can be effectively incremented by incrementing REG. */
272:
273: static rtx
274: find_addr_reg (addr)
275: rtx addr;
276: {
277: while (GET_CODE (addr) == PLUS)
278: {
279: if (GET_CODE (XEXP (addr, 0)) == REG)
280: addr = XEXP (addr, 0);
281: else if (GET_CODE (XEXP (addr, 1)) == REG)
282: addr = XEXP (addr, 1);
283: else if (CONSTANT_P (XEXP (addr, 0)))
284: addr = XEXP (addr, 1);
285: else if (CONSTANT_P (XEXP (addr, 1)))
286: addr = XEXP (addr, 0);
287: else
288: abort ();
289: }
290: if (GET_CODE (addr) == REG)
291: return addr;
292: abort ();
293: }
294:
1.1.1.2 root 295: /* Test for -0.0. */
296:
297: int
298: double_is_minus_zero (arg)
299: double arg;
300: {
301: union { double d; int i[2];} u;
302:
303: u.d = arg;
304: return (u.i[1] == 0 && u.i[0] == 0x80000000);
305: }
306:
1.1 root 307: char *
308: output_move_const_double (operands)
309: rtx *operands;
310: {
311: if (TARGET_FPA && FPA_REG_P(operands[0]))
312: {
313: int code = standard_sun_fpa_constant_p (operands[1]);
314:
315: if (code != 0)
316: {
317: static char buf[40];
318:
319: sprintf (buf, "fpmove%%.d %%%%%d,%%0", code & 0x1ff);
320: return buf;
321: }
322: return "fpmove%.d %1,%0";
323: }
324: else
325: {
326: int code = standard_68881_constant_p (operands[1]);
327:
328: if (code != 0)
329: {
330: static char buf[40];
331:
332: sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
333: return buf;
334: }
335: return "fmove%.d %1,%0";
336: }
337: }
338:
339: char *
340: output_move_const_single (operands)
341: rtx *operands;
342: {
343: if (TARGET_FPA)
344: {
345: int code = standard_sun_fpa_constant_p (operands[1]);
346:
347: if (code != 0)
348: {
349: static char buf[40];
350:
351: sprintf (buf, "fpmove%%.s %%%%%d,%%0", code & 0x1ff);
352: return buf;
353: }
354: return "fpmove%.s %1,%0";
355: }
356: else
357: {
358: int code = standard_68881_constant_p (operands[1]);
359:
360: if (code != 0)
361: {
362: static char buf[40];
363:
364: sprintf (buf, "fmovecr %%#0x%x,%%0", code & 0xff);
365: return buf;
366: }
367: return "fmove%.s %f1,%0";
368: }
369: }
370:
371: /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
372: from the "fmovecr" instruction.
373: The value, anded with 0xff, gives the code to use in fmovecr
374: to get the desired constant. */
375:
376: int
377: standard_68881_constant_p (x)
378: rtx x;
379: {
380: union {double d; int i[2];} u;
381: register double d;
1.1.1.2 root 382:
383: #ifdef HOST_WORDS_BIG_ENDIAN
1.1 root 384: u.i[0] = CONST_DOUBLE_LOW (x);
385: u.i[1] = CONST_DOUBLE_HIGH (x);
1.1.1.2 root 386: #else
387: u.i[0] = CONST_DOUBLE_HIGH (x);
388: u.i[1] = CONST_DOUBLE_LOW (x);
389: #endif
1.1 root 390: d = u.d;
391:
392: if (d == 0)
393: return 0x0f;
394: /* Note: there are various other constants available
395: but it is a nuisance to put in their values here. */
396: if (d == 1)
397: return 0x32;
398: if (d == 10)
399: return 0x33;
400: if (d == 100)
401: return 0x34;
402: if (d == 10000)
403: return 0x35;
404: if (d == 1e8)
405: return 0x36;
406: if (GET_MODE (x) == SFmode)
407: return 0;
408: if (d == 1e16)
409: return 0x37;
410: /* larger powers of ten in the constants ram are not used
411: because they are not equal to a `double' C constant. */
412: return 0;
413: }
414:
415: /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get
416: from the Sun FPA's constant RAM.
417: The value returned, anded with 0x1ff, gives the code to use in fpmove
418: to get the desired constant. */
419: #define S_E (2.718281745910644531)
420: #define D_E (2.718281828459045091)
421: #define S_PI (3.141592741012573242)
422: #define D_PI (3.141592653589793116)
423: #define S_SQRT2 (1.414213538169860840)
424: #define D_SQRT2 (1.414213562373095145)
425: #define S_LOG2ofE (1.442695021629333496)
426: #define D_LOG2ofE (1.442695040888963387)
427: #define S_LOG2of10 (3.321928024291992188)
428: #define D_LOG2of10 (3.321928024887362182)
429: #define S_LOGEof2 (0.6931471824645996094)
430: #define D_LOGEof2 (0.6931471805599452862)
431: #define S_LOGEof10 (2.302585124969482442)
432: #define D_LOGEof10 (2.302585092994045901)
433: #define S_LOG10of2 (0.3010300099849700928)
434: #define D_LOG10of2 (0.3010299956639811980)
435: #define S_LOG10ofE (0.4342944920063018799)
436: #define D_LOG10ofE (0.4342944819032518167)
437:
438: int
439: standard_sun_fpa_constant_p (x)
440: rtx x;
441: {
442: union {double d; int i[2];} u;
443: register double d;
444: u.i[0] = CONST_DOUBLE_LOW (x);
445: u.i[1] = CONST_DOUBLE_HIGH (x);
446: d = u.d;
447:
448: if (d == 0.0)
449: return 0x200; /* 0 once 0x1ff is anded with it */
450: if (d == 1.0)
451: return 0xe;
452: if (d == 0.5)
453: return 0xf;
454: if (d == -1.0)
455: return 0x10;
456: if (d == 2.0)
457: return 0x11;
458: if (d == 3.0)
459: return 0xB1;
460: if (d == 4.0)
461: return 0x12;
462: if (d == 8.0)
463: return 0x13;
464: if (d == 0.25)
465: return 0x15;
466: if (d == 0.125)
467: return 0x16;
468: if (d == 10.0)
469: return 0x17;
470: if (d == -(1.0/2.0))
471: return 0x2E;
472:
473: /*
474: * Stuff that looks different if it's single or double
475: */
476: if (GET_MODE(x) == SFmode)
477: {
478: if (d == S_E)
479: return 0x8;
480: if (d == (2*S_PI))
481: return 0x9;
482: if (d == S_PI)
483: return 0xA;
484: if (d == (S_PI / 2.0))
485: return 0xB;
486: if (d == S_SQRT2)
487: return 0xC;
488: if (d == (1.0 / S_SQRT2))
489: return 0xD;
490: /* Large powers of 10 in the constant
491: ram are not used because they are
492: not equal to a C double constant */
493: if (d == -(S_PI / 2.0))
494: return 0x27;
495: if (d == S_LOG2ofE)
496: return 0x28;
497: if (d == S_LOG2of10)
498: return 0x29;
499: if (d == S_LOGEof2)
500: return 0x2A;
501: if (d == S_LOGEof10)
502: return 0x2B;
503: if (d == S_LOG10of2)
504: return 0x2C;
505: if (d == S_LOG10ofE)
506: return 0x2D;
507: }
508: else
509: {
510: if (d == D_E)
511: return 0x8;
512: if (d == (2*D_PI))
513: return 0x9;
514: if (d == D_PI)
515: return 0xA;
516: if (d == (D_PI / 2.0))
517: return 0xB;
518: if (d == D_SQRT2)
519: return 0xC;
520: if (d == (1.0 / D_SQRT2))
521: return 0xD;
522: /* Large powers of 10 in the constant
523: ram are not used because they are
524: not equal to a C double constant */
525: if (d == -(D_PI / 2.0))
526: return 0x27;
527: if (d == D_LOG2ofE)
528: return 0x28;
529: if (d == D_LOG2of10)
530: return 0x29;
531: if (d == D_LOGEof2)
532: return 0x2A;
533: if (d == D_LOGEof10)
534: return 0x2B;
535: if (d == D_LOG10of2)
536: return 0x2C;
537: if (d == D_LOG10ofE)
538: return 0x2D;
539: }
540: return 0x0;
541: }
542:
543: #undef S_E
544: #undef D_E
545: #undef S_PI
546: #undef D_PI
547: #undef S_SQRT2
548: #undef D_SQRT2
549: #undef S_LOG2ofE
550: #undef D_LOG2ofE
551: #undef S_LOG2of10
552: #undef D_LOG2of10
553: #undef S_LOGEof2
554: #undef D_LOGEof2
555: #undef S_LOGEof10
556: #undef D_LOGEof10
557: #undef S_LOG10of2
558: #undef D_LOG10of2
559: #undef S_LOG10ofE
560: #undef D_LOG10ofE
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