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1.1 root 1: ;;- Machine description for HP PA-RISC architecture for GNU C compiler
2: ;; Copyright (C) 1992 Free Software Foundation, Inc.
3: ;; Contributed by the Center for Software Science at the University
4: ;; of Utah.
5:
6: ;; This file is part of GNU CC.
7:
8: ;; GNU CC is free software; you can redistribute it and/or modify
9: ;; it under the terms of the GNU General Public License as published by
10: ;; the Free Software Foundation; either version 2, or (at your option)
11: ;; any later version.
12:
13: ;; GNU CC is distributed in the hope that it will be useful,
14: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: ;; GNU General Public License for more details.
17:
18: ;; You should have received a copy of the GNU General Public License
19: ;; along with GNU CC; see the file COPYING. If not, write to
20: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21:
22: ;; This gcc Version 2 machine description is inspired by sparc.md and
23: ;; mips.md.
24:
25: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26:
27: ;; Insn type. Used to default other attribute values.
28:
29: ;; type "unary" insns have one input operand (1) and one output operand (0)
30: ;; type "binary" insns have two input operands (1,2) and one output (0)
31:
32: (define_attr "type"
33: "move,unary,binary,compare,load,store,branch,cbranch,call,dyncall,address,fpload,fpstore,fpalu,fpcc,fpmul,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,misc,milli"
34: (const_string "binary"))
35:
36: ;; Set true if insn uses call-clobbered intermediate register.
37: (define_attr "use_clobbered" "false,true"
38: (if_then_else (and (eq_attr "type" "address")
39: (match_operand 0 "clobbered_register" ""))
40: (const_string "true")
41: (const_string "false")))
42:
43: ;; Length (in # of insns).
44: (define_attr "length" ""
45: (cond [(eq_attr "type" "load,fpload")
46: (if_then_else (match_operand 1 "symbolic_memory_operand" "")
47: (const_int 2) (const_int 1))
48:
49: (eq_attr "type" "store,fpstore")
50: (if_then_else (match_operand 0 "symbolic_memory_operand" "")
51: (const_int 2) (const_int 1))
52:
53: (eq_attr "type" "address") (const_int 2)
54:
55: (eq_attr "type" "binary")
56: (if_then_else (match_operand 2 "arith_operand" "")
57: (const_int 1) (const_int 3))
58:
59: (eq_attr "type" "move,unary")
60: (if_then_else (match_operand 1 "arith_operand" "")
61: (const_int 1) (const_int 2))]
62:
63: (const_int 1)))
64:
65: (define_asm_attributes
66: [(set_attr "length" "1")
67: (set_attr "type" "multi")])
68:
69: ;; Attributes for instruction and branch scheduling
70:
71: (define_attr "in_call_delay" "false,true"
72: (cond [(eq_attr "type" "branch,cbranch,call,dyncall,multi,milli")
73: (const_string "false")
74:
75: (eq_attr "type" "load,fpload,store,fpstore")
76: (if_then_else (eq_attr "length" "1")
77: (const_string "true")
78: (const_string "false"))
79:
80: (eq_attr "type" "address")
81: (if_then_else (eq_attr "use_clobbered" "false")
82: (const_string "true")
83: (const_string "false"))]
84:
85: (if_then_else (eq_attr "length" "1")
86: (const_string "true")
87: (const_string "false"))))
88:
89: (define_attr "in_milli_delay" "false,true"
90: (cond [(eq_attr "length" "!1")
91: (const_string "false")
92:
93: (eq_attr "type" "branch,cbranch,call,dyncall,milli")
94: (const_string "false")
95:
96: (ne (symbol_ref "use_milli_regs (insn)") (const_int 0))
97: (const_string "false")]
98: (const_string "true")))
99:
100: (define_delay (eq_attr "type" "call")
101: [(eq_attr "in_call_delay" "true") (nil) (nil)])
102:
103: (define_attr "in_branch_delay" "false,true"
104: (if_then_else (and (eq_attr "type" "!branch,cbranch,call,multi,milli")
105: (eq_attr "length" "1"))
106: (const_string "true")
107: (const_string "false")))
108:
109: (define_delay (eq_attr "type" "branch")
110: [(eq_attr "in_branch_delay" "true")
111: (eq_attr "in_branch_delay" "true") (nil)])
112:
113: (define_delay (eq_attr "type" "cbranch")
114: [(eq_attr "in_branch_delay" "true") (nil) (nil)])
115:
116: (define_delay (eq_attr "type" "milli")
117: [(eq_attr "in_milli_delay" "true") (nil) (nil)])
118:
119: ;; Function units of the HPPA. The following data is for the "Snake"
120: ;; (Mustang CPU + Timex FPU) because that's what I have the docs for.
121: ;; Scheduling instructions for PA-83 machines according to the Snake
122: ;; constraints shouldn't hurt.
123:
124: ;; (define_function_unit {name} {num-units} {n-users} {test}
125: ;; {ready-delay} {busy-delay} [{conflict-list}])
126:
127: ;; The integer ALU.
128: ;; (Noted only for documentation; units that take one cycle do not need to
129: ;; be specified.)
130:
131: ;; (define_function_unit "alu" 1 0
132: ;; (eq_attr "type" "unary,binary,move,address") 1 0)
133:
134:
135: ;; Memory. Disregarding Cache misses, the Mustang memory times are:
136: ;; load: 1
137: ;; store, fpstore: 3, no D-cache operations should be scheduled.
138: ;; fpload: 3 (really 2 for flops, but I don't think we can specify that).
139:
140: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 1 0)
141: (define_function_unit "memory" 1 1 (eq_attr "type" "store,fpstore") 3 0)
142: (define_function_unit "memory" 1 1 (eq_attr "type" "fpload") 3 0)
143:
144: ;; The Timex has two floating-point units: ALU, and MUL/DIV/SQRT unit.
145: ;; Timings:
146: ;; Instruction Time Unit Minimum Distance (unit contention)
147: ;; fcpy 3 ALU 2
148: ;; fabs 3 ALU 2
149: ;; fadd 3 ALU 2
150: ;; fsub 3 ALU 2
151: ;; fcmp 3 ALU 2
152: ;; fcnv 3 ALU 2
153: ;; fmpyadd 3 ALU,MPY 2
154: ;; fmpysub 3 ALU,MPY 2
155: ;; fmpycfxt 3 ALU,MPY 2
156: ;; fmpy 3 MPY 2
157: ;; fmpyi 3 MPY 2
158: ;; fdiv,sgl 10 MPY 10
159: ;; fdiv,dbl 12 MPY 12
160: ;; fsqrt,sgl 14 MPY 14
161: ;; fsqrt,dbl 18 MPY 18
162:
163: (define_function_unit "fp_alu" 1 0 (eq_attr "type" "fpalu") 3 2)
164: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpmul") 3 2)
165: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpdivsgl") 10 10)
166: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpdivdbl") 12 12)
167: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpsqrtsgl") 14 14)
168: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpsqrtdbl") 18 18)
169:
170: ;; Compare instructions.
171: ;; This controls RTL generation and register allocation.
172:
173: ;; We generate RTL for comparisons and branches by having the cmpxx
174: ;; patterns store away the operands. Then, the scc and bcc patterns
175: ;; emit RTL for both the compare and the branch.
176: ;;
177:
178: (define_expand "cmpsi"
179: [(set (reg:CC 0)
180: (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
181: (match_operand:SI 1 "arith5_operand" "")))]
182: ""
183: "
184: {
185: hppa_compare_op0 = operands[0];
186: hppa_compare_op1 = operands[1];
187: hppa_branch_type = CMP_SI;
188: DONE;
189: }")
190:
191: (define_expand "cmpsf"
192: [(set (reg:CCFP 0)
193: (compare:CCFP (match_operand:SF 0 "register_operand" "")
194: (match_operand:SF 1 "register_operand" "")))]
195: ""
196: "
197: {
198: hppa_compare_op0 = operands[0];
199: hppa_compare_op1 = operands[1];
200: hppa_branch_type = CMP_SF;
201: DONE;
202: }")
203:
204: (define_expand "cmpdf"
205: [(set (reg:CCFP 0)
206: (compare:CCFP (match_operand:DF 0 "register_operand" "")
207: (match_operand:DF 1 "register_operand" "")))]
208: ""
209: "
210: {
211: hppa_compare_op0 = operands[0];
212: hppa_compare_op1 = operands[1];
213: hppa_branch_type = CMP_DF;
214: DONE;
215: }")
216:
217: (define_insn ""
218: [(set (reg:CCFP 0)
219: (match_operator:CCFP 2 "comparison_operator"
220: [(match_operand:SF 0 "register_operand" "fx")
221: (match_operand:SF 1 "register_operand" "fx")]))]
222: ""
223: "fcmp,sgl,%Y2 %0,%1"
224: [(set_attr "type" "fpcc")])
225:
226: (define_insn ""
227: [(set (reg:CCFP 0)
228: (match_operator:CCFP 2 "comparison_operator"
229: [(match_operand:DF 0 "register_operand" "fx")
230: (match_operand:DF 1 "register_operand" "fx")]))]
231: ""
232: "fcmp,dbl,%Y2 %0,%1"
233: [(set_attr "type" "fpcc")])
234:
235: ;; scc insns.
236:
237: (define_insn ""
238: [(set (match_operand:SI 0 "register_operand" "=r")
239: (match_operator:CCFP 1 "comparison_operator" [(reg:CCFP 0)
240: (const_int 0)]))]
241: ""
242: "copy 0,%0\;ftest\;ldi 1,%0"
243: [(set_attr "type" "unary")
244: (set_attr "length" "3")])
245:
246: (define_expand "seq"
247: [(set (match_operand:SI 0 "register_operand" "")
248: (eq:CC (match_dup 1)
249: (match_dup 2)))]
250: ""
251: "
252: {
253: if (hppa_branch_type != CMP_SI)
254: {
255: emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
256: emit_insn (gen_scond_fp (EQ, operands[0]));
257: DONE;
258: }
259: /* set up operands from compare. */
260: operands[1] = hppa_compare_op0;
261: operands[2] = hppa_compare_op1;
262: /* fall through and generate default code */
263: }")
264:
265: (define_expand "sne"
266: [(set (match_operand:SI 0 "register_operand" "=r")
267: (ne:CC (match_dup 1)
268: (match_dup 2)))]
269: ""
270: "
271: {
272: if (hppa_branch_type != CMP_SI)
273: {
274: emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
275: emit_insn (gen_scond_fp (NE, operands[0]));
276: DONE;
277: }
278: operands[1] = hppa_compare_op0;
279: operands[2] = hppa_compare_op1;
280: }")
281:
282: (define_expand "slt"
283: [(set (match_operand:SI 0 "register_operand" "=r")
284: (lt:CC (match_dup 1)
285: (match_dup 2)))]
286: ""
287: "
288: {
289: if (hppa_branch_type != CMP_SI)
290: {
291: emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
292: emit_insn (gen_scond_fp (LT, operands[0]));
293: DONE;
294: }
295: operands[1] = hppa_compare_op0;
296: operands[2] = hppa_compare_op1;
297: }")
298:
299: (define_expand "sgt"
300: [(set (match_operand:SI 0 "register_operand" "=r")
301: (gt:CC (match_dup 1)
302: (match_dup 2)))]
303: ""
304: "
305: {
306: if (hppa_branch_type != CMP_SI)
307: {
308: emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
309: emit_insn (gen_scond_fp (GT, operands[0]));
310: DONE;
311: }
312: operands[1] = hppa_compare_op0;
313: operands[2] = hppa_compare_op1;
314: }")
315:
316: (define_expand "sle"
317: [(set (match_operand:SI 0 "register_operand" "=r")
318: (le:CC (match_dup 1)
319: (match_dup 2)))]
320: ""
321: "
322: {
323: if (hppa_branch_type != CMP_SI)
324: {
325: emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
326: emit_insn (gen_scond_fp (LE, operands[0]));
327: DONE;
328: }
329: operands[1] = hppa_compare_op0;
330: operands[2] = hppa_compare_op1;
331: }")
332:
333: (define_expand "sge"
334: [(set (match_operand:SI 0 "register_operand" "=r")
335: (ge:CC (match_dup 1)
336: (match_dup 2)))]
337: ""
338: "
339: {
340: if (hppa_branch_type != CMP_SI)
341: {
342: emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
343: emit_insn (gen_scond_fp (GE, operands[0]));
344: DONE;
345: }
346: operands[1] = hppa_compare_op0;
347: operands[2] = hppa_compare_op1;
348: }")
349:
350: (define_expand "sltu"
351: [(set (match_operand:SI 0 "register_operand" "=r")
352: (ltu:CC (match_dup 1)
353: (match_dup 2)))]
354: ""
355: "
356: {
357: if (hppa_branch_type != CMP_SI)
358: FAIL;
359: operands[1] = hppa_compare_op0;
360: operands[2] = hppa_compare_op1;
361: }")
362:
363: (define_expand "sgtu"
364: [(set (match_operand:SI 0 "register_operand" "=r")
365: (gtu:CC (match_dup 1)
366: (match_dup 2)))]
367: ""
368: "
369: {
370: if (hppa_branch_type != CMP_SI)
371: FAIL;
372: operands[1] = hppa_compare_op0;
373: operands[2] = hppa_compare_op1;
374: }")
375:
376: (define_expand "sleu"
377: [(set (match_operand:SI 0 "register_operand" "=r")
378: (leu:CC (match_dup 1)
379: (match_dup 2)))]
380: ""
381: "
382: {
383: if (hppa_branch_type != CMP_SI)
384: FAIL;
385: operands[1] = hppa_compare_op0;
386: operands[2] = hppa_compare_op1;
387: }")
388:
389: (define_expand "sgeu"
390: [(set (match_operand:SI 0 "register_operand" "=r")
391: (geu:CC (match_dup 1)
392: (match_dup 2)))]
393: ""
394: "
395: {
396: if (hppa_branch_type != CMP_SI)
397: FAIL;
398: operands[1] = hppa_compare_op0;
399: operands[2] = hppa_compare_op1;
400: }")
401:
402: ;; Instruction canonicalization puts immediate operands second, which
403: ;; is the reverse of what we want.
404:
405: (define_insn ""
406: [(set (match_operand:SI 0 "register_operand" "=r,r")
407: (match_operator:CC 3 "comparison_operator"
408: [(match_operand:SI 1 "register_operand" "r,r")
409: (match_operand:SI 2 "arith11_operand" "r,I")]))]
410: ""
411: "*
412: {
413: if (which_alternative == 0)
414: return \"comclr,%N3 %1,%2,%0\;ldi 1,%0\";
415: else
416: {
417: if (!(GET_CODE (operands[3]) == EQ || GET_CODE (operands[3]) == NE))
418: PUT_CODE (operands[3], reverse_relop (GET_CODE (operands[3])));
419: output_asm_insn (\"comiclr,%N3 %2,%1,%0\;ldi 1,%0\", operands);
420: return \"\";
421: }
422: }"
423: [(set_attr "type" "binary")
424: (set_attr "length" "2")])
425:
426: ;; Conditionals
427:
428: (define_expand "beq"
429: [(set (pc)
430: (if_then_else (eq (match_dup 1) (match_dup 2))
431: (label_ref (match_operand 0 "" ""))
432: (pc)))]
433: ""
434: "
435: {
436: if (hppa_branch_type != CMP_SI)
437: {
438: emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
439: emit_bcond_fp (NE, operands[0]);
440: DONE;
441: }
442: /* set up operands from compare. */
443: operands[1] = hppa_compare_op0;
444: operands[2] = hppa_compare_op1;
445: /* fall through and generate default code */
446: }")
447:
448: (define_expand "bne"
449: [(set (pc)
450: (if_then_else (ne (match_dup 1) (match_dup 2))
451: (label_ref (match_operand 0 "" ""))
452: (pc)))]
453: ""
454: "
455: {
456: if (hppa_branch_type != CMP_SI)
457: {
458: emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
459: emit_bcond_fp (NE, operands[0]);
460: DONE;
461: }
462: operands[1] = hppa_compare_op0;
463: operands[2] = hppa_compare_op1;
464: }")
465:
466: (define_expand "bgt"
467: [(set (pc)
468: (if_then_else (gt (match_dup 1) (match_dup 2))
469: (label_ref (match_operand 0 "" ""))
470: (pc)))]
471: ""
472: "
473: {
474: if (hppa_branch_type != CMP_SI)
475: {
476: emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
477: emit_bcond_fp (NE, operands[0]);
478: DONE;
479: }
480: operands[1] = hppa_compare_op0;
481: operands[2] = hppa_compare_op1;
482: }")
483:
484: (define_expand "blt"
485: [(set (pc)
486: (if_then_else (lt (match_dup 1) (match_dup 2))
487: (label_ref (match_operand 0 "" ""))
488: (pc)))]
489: ""
490: "
491: {
492: if (hppa_branch_type != CMP_SI)
493: {
494: emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
495: emit_bcond_fp (NE, operands[0]);
496: DONE;
497: }
498: operands[1] = hppa_compare_op0;
499: operands[2] = hppa_compare_op1;
500: }")
501:
502: (define_expand "bge"
503: [(set (pc)
504: (if_then_else (ge (match_dup 1) (match_dup 2))
505: (label_ref (match_operand 0 "" ""))
506: (pc)))]
507: ""
508: "
509: {
510: if (hppa_branch_type != CMP_SI)
511: {
512: emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
513: emit_bcond_fp (NE, operands[0]);
514: DONE;
515: }
516: operands[1] = hppa_compare_op0;
517: operands[2] = hppa_compare_op1;
518: }")
519:
520: (define_expand "ble"
521: [(set (pc)
522: (if_then_else (le (match_dup 1) (match_dup 2))
523: (label_ref (match_operand 0 "" ""))
524: (pc)))]
525: ""
526: "
527: {
528: if (hppa_branch_type != CMP_SI)
529: {
530: emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
531: emit_bcond_fp (NE, operands[0]);
532: DONE;
533: }
534: operands[1] = hppa_compare_op0;
535: operands[2] = hppa_compare_op1;
536: }")
537:
538: (define_expand "bgtu"
539: [(set (pc)
540: (if_then_else (gtu (match_dup 1) (match_dup 2))
541: (label_ref (match_operand 0 "" ""))
542: (pc)))]
543: ""
544: "
545: {
546: if (hppa_branch_type != CMP_SI)
547: FAIL;
548: operands[1] = hppa_compare_op0;
549: operands[2] = hppa_compare_op1;
550: }")
551:
552: (define_expand "bltu"
553: [(set (pc)
554: (if_then_else (ltu (match_dup 1) (match_dup 2))
555: (label_ref (match_operand 0 "" ""))
556: (pc)))]
557: ""
558: "
559: {
560: if (hppa_branch_type != CMP_SI)
561: FAIL;
562: operands[1] = hppa_compare_op0;
563: operands[2] = hppa_compare_op1;
564: }")
565:
566: (define_expand "bgeu"
567: [(set (pc)
568: (if_then_else (geu (match_dup 1) (match_dup 2))
569: (label_ref (match_operand 0 "" ""))
570: (pc)))]
571: ""
572: "
573: {
574: if (hppa_branch_type != CMP_SI)
575: FAIL;
576: operands[1] = hppa_compare_op0;
577: operands[2] = hppa_compare_op1;
578: }")
579:
580: (define_expand "bleu"
581: [(set (pc)
582: (if_then_else (leu (match_dup 1) (match_dup 2))
583: (label_ref (match_operand 0 "" ""))
584: (pc)))]
585: ""
586: "
587: {
588: if (hppa_branch_type != CMP_SI)
589: FAIL;
590: operands[1] = hppa_compare_op0;
591: operands[2] = hppa_compare_op1;
592: }")
593:
594: ;; Match the branch patterns.
595:
596: (define_insn ""
597: [(set (pc)
598: (if_then_else
599: (match_operator 3 "comparison_operator"
600: [(match_operand:SI 1 "register_operand" "r,r")
601: (match_operand:SI 2 "arith5_operand" "r,L")])
602: (label_ref (match_operand 0 "" ""))
603: (pc)))]
604: ""
605: "*
606: {
607: if (which_alternative == 0)
608: return (get_attr_length (insn) == 1
609: ? \"comb,%C3 %1,%2,%0%#\" : \"comclr,%N3 %1,%2,0\;bl %0,0%#\");
610: {
611: enum rtx_code comp_code = GET_CODE (operands[3]);
612: if (!(comp_code == EQ || comp_code == NE))
613: PUT_CODE (operands[3], reverse_relop (comp_code));
614: if (get_attr_length (insn) == 1)
615: output_asm_insn (\"comib,%C3 %2,%1,%0%#\", operands);
616: else
617: output_asm_insn (\"comiclr,%N3 %2,%1,0\;bl %0,0%#\", operands);
618: return \"\";
619: }
620: }"
621: [(set_attr "type" "cbranch")
622: (set (attr "length") (if_then_else (lt (abs (minus (match_dup 0)
623: (plus (pc) (const_int 2))))
624: (const_int 1023))
625: (const_int 1)
626: (const_int 2)))])
627:
628: ;; Match the negated branch.
629:
630: (define_insn ""
631: [(set (pc)
632: (if_then_else
633: (match_operator 3 "comparison_operator"
634: [(match_operand:SI 1 "register_operand" "r,r")
635: (match_operand:SI 2 "arith5_operand" "r,L")])
636: (pc)
637: (label_ref (match_operand 0 "" ""))))]
638: ""
639: "*
640: {
641: if (which_alternative == 0)
642: return (get_attr_length (insn) == 1
643: ? \"comb,%N3 %1,%2,%0%#\" : \"comclr,%C3 %1,%2,0\;bl %0,0%#\");
644: {
645: enum rtx_code comp_code = GET_CODE (operands[3]);
646: if (!(comp_code == EQ || comp_code == NE))
647: PUT_CODE (operands[3], reverse_relop (comp_code));
648: if (get_attr_length (insn) == 1)
649: output_asm_insn (\"comib,%N3 %2,%1,%0%#\", operands);
650: else
651: output_asm_insn (\"comiclr,%C3 %2,%1,0%#\;bl %0,0%#\", operands);
652: return \"\";
653: }
654: }"
655: [(set_attr "type" "cbranch")
656: (set (attr "length") (if_then_else (lt (abs (minus (match_dup 0)
657: (plus (pc) (const_int 2))))
658: (const_int 1023))
659: (const_int 1)
660: (const_int 2)))])
661:
662: ;; Floating point branches
663:
664: (define_insn ""
665: [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
666: (label_ref (match_operand 0 "" ""))
667: (pc)))]
668: ""
669: "ftest\;bl%* %0,0"
670: [(set_attr "type" "cbranch")
671: (set_attr "length" "2")])
672:
673: (define_insn ""
674: [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
675: (pc)
676: (label_ref (match_operand 0 "" ""))))]
677: ""
678: "ftest\;add,tr 0,0,0\;bl%* %0,0"
679: [(set_attr "type" "cbranch")
680: (set_attr "length" "3")])
681:
682: ;; Move instructions
683:
684: (define_expand "movsi"
685: [(set (match_operand:SI 0 "general_operand" "")
686: (match_operand:SI 1 "general_operand" ""))]
687: ""
688: "
689: {
690: if (emit_move_sequence (operands, SImode))
691: DONE;
692: }")
693:
694: ;; Moves to and from the shift register.
695:
696: (define_insn ""
697: [(set (reg:SI 112)
698: (match_operand:SI 0 "register_operand" "r"))]
699: ""
700: "mtsar %0"
701: [(set_attr "type" "move")])
702:
703: (define_insn ""
704: [(set (match_operand:SI 0 "register_operand" "=r")
705: (reg:SI 112))]
706: ""
707: "mfctl 11,%0"
708: [(set_attr "type" "move")])
709:
710: (define_insn ""
711: [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
712: "=r,r,Q,!r,!*f*x,!*f*x")
713: (match_operand:SI 1 "move_operand" "rM,Q,rM,!*f*x*y,!r,!*f*x"))]
714: ""
715: "@
716: copy %r1,%0
717: ldw%M1 %1,%0
718: stw%M0 %r1,%0
719: fstws %1,-16(30)\;ldw -16(30),%0
720: stw %1,-16(30)\;fldws -16(30),%0
721: fcpy,sgl %1,%0"
722: [(set_attr "type" "move,load,store,move,move,fpalu")
723: (set_attr "length" "1,1,1,2,2,1")])
724:
725: ;; For pic
726: (define_insn ""
727: [(set (match_operand:SI 0 "register_operand" "=r")
728: (match_operand:SI 1 "pic_operand" "i"))
729: (clobber (match_scratch:SI 2 "=a"))]
730: ""
731: "*
732: {
733: rtx label_rtx = gen_label_rtx ();
734: rtx xoperands[3];
735: extern FILE *asm_out_file;
736:
737: xoperands[0] = operands[0];
738: xoperands[1] = operands[1];
739: xoperands[2] = label_rtx;
740: output_asm_insn (\"bl .+8,%0\;addil L'%1-%2,%0\", xoperands);
741: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (label_rtx));
742: output_asm_insn (\"ldo R'%1(1),%0\", xoperands);
743: return \"\";
744: }
745: "
746: [(set_attr "type" "multi")
747: (set_attr "length" "3")])
748:
749: (define_insn ""
750: [(set (match_operand:SI 0 "register_operand" "=r")
751: (match_operand:SI 1 "immediate_operand" "n"))]
752: "(GET_CODE (operands[1]) == CONST_INT) &&
753: (INT_14_BITS (operands[1]) || !(INTVAL (operands[1]) & 0x7ff))"
754: "*
755: {
756: if (INT_14_BITS (operands[1]))
757: return \"ldo %1(0),%0\";
758: else
759: return \"ldil L'%1,%0\";
760: }"
761: [(set_attr "type" "move")
762: (set_attr "length" "1")])
763:
764: (define_insn ""
765: [(set (match_operand:SI 0 "register_operand" "=a,?*r")
766: (plus:SI (match_operand:SI 1 "register_operand" "r,r")
767: (high:SI (match_operand 2 "" ""))))]
768: ""
769: "@
770: addil L'%G2,%1
771: ldil L'%G2,%0\;add %0,%1,%0"
772: [(set_attr "type" "binary")
773: (set_attr "length" "1,2")])
774:
775: (define_split
776: [(set (match_operand:SI 0 "register_operand" "")
777: (plus:SI (match_operand:SI 1 "register_operand" "")
778: (high:SI (match_operand 2 "" ""))))]
779: "reload_completed && REGNO (operands[0]) != 1"
780: [(set (match_dup 0) (high:SI (match_dup 2)))
781: (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 1)))]
782: "")
783:
784: (define_insn ""
785: [(set (match_operand:SI 0 "register_operand" "=r")
786: (high:SI (match_operand 1 "" "")))]
787: "check_pic (1)"
788: "ldil L'%G1,%0"
789: [(set_attr "type" "move")
790: (set_attr "length" "1")])
791:
792: (define_insn ""
793: [(set (match_operand:HI 0 "register_operand" "=r")
794: (high:HI (match_operand 1 "" "")))]
795: "check_pic (1)"
796: "ldil L'%G1,%0"
797: [(set_attr "type" "move")
798: (set_attr "length" "1")])
799:
800: (define_insn ""
801: [(set (match_operand:SI 0 "register_operand" "=r")
802: (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
803: (match_operand:SI 2 "immediate_operand" "in")))]
804: ""
805: "ldo R'%G2(%1),%0"
806: ;; Need to set length for this arith insn because operand2
807: ;; is not an "arith_operand".
808: [(set_attr "length" "1")])
809:
810: ;;; Experimental
811:
812: (define_insn ""
813: [(set (match_operand:SI 0 "fp_reg_operand" "*f*x")
814: (match_operand:SI 1 "short_memory_operand" "T"))]
815: ""
816: "fldws%F1 %1,%0"
817: [(set_attr "type" "fpload")
818: (set_attr "length" "1")])
819:
820: (define_insn ""
821: [(set (match_operand:SI 0 "short_memory_operand" "T")
822: (match_operand:SI 1 "fp_reg_operand" "*f*x"))]
823: ""
824: "fstws%F0 %1,%0"
825: [(set_attr "type" "fpstore")
826: (set_attr "length" "1")])
827:
828: (define_expand "movhi"
829: [(set (match_operand:HI 0 "general_operand" "")
830: (match_operand:HI 1 "general_operand" ""))]
831: ""
832: "
833: {
834: if (emit_move_sequence (operands, HImode))
835: DONE;
836: }")
837:
838: (define_insn ""
839: [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,Q")
840: (match_operand:HI 1 "move_operand" "rM,Q,rM"))]
841: ""
842: "@
843: copy %r1,%0
844: ldh%M1 %1,%0
845: sth%M0 %r1,%0"
846: [(set_attr "type" "move,load,store")
847: (set_attr "length" "1,1,1")])
848:
849: (define_insn ""
850: [(set (match_operand:HI 0 "register_operand" "=r")
851: (match_operand:HI 1 "immediate_operand" "n"))]
852: "(GET_CODE (operands[1]) == CONST_INT) &&
853: (INT_14_BITS (operands[1]) || !(INTVAL (operands[1]) & 0x7ff))"
854: "*
855: {
856: if (INT_14_BITS (operands[1]))
857: return \"ldo %1(0),%0\";
858: else
859: return \"ldil L'%1,%0\";
860: }"
861: [(set_attr "type" "move")
862: (set_attr "length" "1")])
863:
864: (define_insn ""
865: [(set (match_operand:HI 0 "register_operand" "=r")
866: (lo_sum:HI (match_operand:HI 1 "register_operand" "r")
867: (match_operand 2 "immediate_operand" "in")))]
868: ""
869: "ldo R'%G2(%1),%0"
870: [(set_attr "length" "1")])
871:
872: (define_expand "movqi"
873: [(set (match_operand:QI 0 "general_operand" "")
874: (match_operand:QI 1 "general_operand" ""))]
875: ""
876: "
877: {
878: if (emit_move_sequence (operands, QImode))
879: DONE;
880: }")
881:
882: (define_insn ""
883: [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,Q")
884: (match_operand:QI 1 "move_operand" "rM,Q,rM"))]
885: ""
886: "@
887: copy %r1,%0
888: ldb%M1 %1,%0
889: stb%M0 %r1,%0"
890: [(set_attr "type" "move,load,store")
891: (set_attr "length" "1,1,1")])
892:
893: (define_insn ""
894: [(set (match_operand:QI 0 "register_operand" "=r")
895: (match_operand:QI 1 "immediate_operand" "J"))]
896: ""
897: "ldo %1(0),%0"
898: [(set_attr "type" "move")
899: (set_attr "length" "1")])
900:
901: (define_insn ""
902: [(set (match_operand:QI 0 "register_operand" "=r")
903: (subreg:QI (lo_sum:SI (match_operand:QI 1 "register_operand" "r")
904: (match_operand 2 "immediate_operand" "in")) 0))]
905: ""
906: "ldo R'%G2(%1),%0"
907: [(set_attr "length" "1")])
908:
909: ;; The definition of this insn does not really explain what it does,
910: ;; but it should suffice
911: ;; that anything generated as this insn will be recognized as one
912: ;; and that it will not successfully combine with anything.
913: (define_expand "movstrsi"
914: [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
915: (mem:BLK (match_operand:BLK 1 "general_operand" "")))
916: (clobber (match_dup 0))
917: (clobber (match_dup 1))
918: (clobber (match_scratch:SI 4 ""))
919: (clobber (match_scratch:SI 5 ""))
920: (use (match_operand:SI 2 "arith_operand" ""))
921: (use (match_operand:SI 3 "const_int_operand" ""))])]
922: ""
923: "
924: {
925: /* If the blocks are not word-aligned and rather big (>16 items),
926: or the size is indeterminate, don't inline the copy code. A
927: procedure call is better since it can check the alignment at
928: runtime and make the optimal decisions. */
929: if (INTVAL (operands[3]) != 4
930: && (GET_CODE (operands[2]) != CONST_INT
931: || (INTVAL (operands[2]) / INTVAL (operands[3]) > 16)))
932: FAIL;
933:
934: operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
935: operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
936: operands[2] = force_not_mem (operands[2]);
937: }")
938:
939: ;; The operand constraints are written like this to support both compile-time
940: ;; and run-time determined byte count. If the count is run-time determined,
941: ;; the register with the byte count is clobbered by the copying code, and
942: ;; therefore it is forced to operand 2. If the count is compile-time
943: ;; determined, we need two scratch registers for the unrolled code.
944: (define_insn ""
945: [(set (mem:BLK (match_operand:SI 0 "register_operand" "r,r"))
946: (mem:BLK (match_operand:SI 1 "register_operand" "r,r")))
947: (clobber (match_dup 0))
948: (clobber (match_dup 1))
949: (clobber (match_scratch:SI 2 "=r,r")) ;loop cnt/item tmp
950: (clobber (match_scratch:SI 3 "=r,r")) ;item tmp
951: (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
952: (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
953: ""
954: "* return output_block_move (operands, !which_alternative);"
955: [(set_attr "type" "multi")])
956:
957: ;; Floating point move insns
958:
959: ;; This pattern forces (set (reg:DF ...) (const_double ...))
960: ;; to be reloaded by putting the constant into memory.
961: ;; It must come before the more general movdf pattern.
962: (define_insn ""
963: [(set (match_operand:DF 0 "general_operand" "=?r,r,fx")
964: (match_operand:DF 1 "" "?E,G,m"))]
965: "GET_CODE (operands[1]) == CONST_DOUBLE"
966: "*
967: {
968: switch (which_alternative)
969: {
970: case 0:
971: return output_move_double (operands);
972: case 1:
973: return \"copy 0,%0\;copy 0,%R0\";
974: case 2:
975: return output_fp_move_double (operands);
976: }
977: }"
978: [(set_attr "type" "load,move,fpload")
979: (set_attr "length" "3,2,3")])
980:
981: (define_expand "movdf"
982: [(set (match_operand:DF 0 "general_operand" "")
983: (match_operand:DF 1 "general_operand" ""))]
984: ""
985: "
986: {
987: if (emit_move_sequence (operands, DFmode))
988: DONE;
989: }")
990:
991: (define_insn ""
992: [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
993: "=fx,r,Q,Q,fx,&r,?fx,?r")
994: (match_operand:DF 1 "reg_or_nonsymb_mem_operand"
995: "fx,r,fx,r,Q,Q,r,fx"))]
996: ""
997: "*
998: {
999: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1000: return output_fp_move_double (operands);
1001: return output_move_double (operands);
1002: }"
1003: [(set_attr "type" "fpalu,move,fpstore,store,fpload,load,multi,multi")
1004: (set_attr "length" "1,2,1,2,1,2,3,3")])
1005:
1006: (define_expand "movdi"
1007: [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
1008: (match_operand:DI 1 "general_operand" ""))]
1009: ""
1010: "
1011: {
1012: if (emit_move_sequence (operands, DImode))
1013: DONE;
1014: }")
1015:
1016: (define_insn ""
1017: [(set (match_operand:DI 0 "register_operand" "=r")
1018: (high:DI (match_operand 1 "" "")))]
1019: "check_pic (1)"
1020: "*
1021: {
1022: rtx op0 = operands[0];
1023: rtx op1 = operands[1];
1024:
1025: if (GET_CODE (op1) == CONST_INT)
1026: {
1027: operands[0] = operand_subword (op0, 1, 0, DImode);
1028: output_asm_insn (\"ldil L'%1,%0\", operands);
1029:
1030: operands[0] = operand_subword (op0, 0, 0, DImode);
1031: if (INTVAL (op1) < 0)
1032: output_asm_insn (\"ldo -1(0),%0\", operands);
1033: else
1034: output_asm_insn (\"ldo 0(0),%0\", operands);
1035: }
1036: else if (GET_CODE (op1) == CONST_DOUBLE)
1037: {
1038: operands[0] = operand_subword (op0, 1, 0, DImode);
1039: operands[1] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (op1));
1040: output_asm_insn (\"ldil L'%1,%0\", operands);
1041:
1042: operands[0] = operand_subword (op0, 0, 0, DImode);
1043: operands[1] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_HIGH (op1));
1044: output_asm_insn (singlemove_string (operands), operands);
1045: }
1046: else
1047: abort ();
1048: }"
1049: [(set_attr "type" "move")
1050: (set_attr "length" "2")])
1051:
1052: (define_insn ""
1053: [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
1054: "=r,Q,&r,&r,*f*x,*f*x,*f*x,r,Q")
1055: (match_operand:DI 1 "general_operand"
1056: "r,r,Q,i,r,*f*x,Q,*f*x,*f*x"))]
1057: ""
1058: "*
1059: {
1060: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1061: return output_fp_move_double (operands);
1062: return output_move_double (operands);
1063: }"
1064: [(set_attr "type" "move,store,load,misc,multi,fpalu,fpload,multi,fpstore")
1065: (set_attr "length" "2,3,3,3,3,2,3,3,3")])
1066:
1067: (define_insn ""
1068: [(set (match_operand:DI 0 "register_operand" "=r,r")
1069: (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
1070: (match_operand:DI 2 "immediate_operand" "in,in")))]
1071: ""
1072: "*
1073: {
1074: /* Don't output a 64 bit constant, since we can't trust the assembler to
1075: handle it correctly. */
1076: if (GET_CODE (operands[2]) == CONST_DOUBLE)
1077: operands[2] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[2]));
1078: if (which_alternative == 1)
1079: output_asm_insn (\"copy %1,%0\", operands);
1080: return \"ldo R'%G2(%R1),%R0\";
1081: }"
1082: ;; Need to set length for this arith insn because operand2
1083: ;; is not an "arith_operand".
1084: [(set_attr "length" "1,2")])
1085:
1086: (define_expand "movsf"
1087: [(set (match_operand:SF 0 "general_operand" "")
1088: (match_operand:SF 1 "general_operand" ""))]
1089: ""
1090: "
1091: {
1092: if (emit_move_sequence (operands, SFmode))
1093: DONE;
1094: }")
1095:
1096: (define_insn ""
1097: [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
1098: "=fx,r,r,fx,fx,r,Q,Q")
1099: (match_operand:SF 1 "reg_or_nonsymb_mem_operand"
1100: "fx,r,!fx,!r,Q,Q,fx,r"))]
1101: ""
1102: "@
1103: fcpy %1,%0
1104: copy %1,%0
1105: fstws %1,-16(0,30)\;ldw -16(0,30),%0
1106: stw %r1,-16(0,30)\;fldws -16(0,30),%0
1107: fldws%F1 %1,%0
1108: ldw%M1 %1,%0
1109: fstws%F0 %r1,%0
1110: stw%M0 %r1,%0"
1111: [(set_attr "type" "fpalu,move,multi,multi,fpload,load,fpstore,store")
1112: (set_attr "length" "1,1,2,2,1,1,1,1")])
1113:
1114:
1115: ;;- zero extension instructions
1116:
1117: ;; Note that the one starting from HImode comes before those for QImode
1118: ;; so that a constant operand will match HImode, not QImode.
1119:
1120: (define_expand "zero_extendhisi2"
1121: [(set (match_operand:SI 0 "register_operand" "")
1122: (zero_extend:SI
1123: (match_operand:HI 1 "general_operand" "")))]
1124: ""
1125: "
1126: {
1127: if (GET_CODE (operand1) == MEM
1128: && symbolic_operand (XEXP (operand1, 0), Pmode))
1129: {
1130: rtx temp = copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode,
1131: XEXP (operand1, 0)));
1132: operands[1] = gen_rtx (MEM, HImode,
1133: gen_rtx (LO_SUM, Pmode,
1134: temp, XEXP (operand1, 0)));
1135: }
1136: }")
1137:
1138: (define_insn ""
1139: [(set (match_operand:SI 0 "register_operand" "=r,r")
1140: (zero_extend:SI
1141: (match_operand:HI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
1142: ""
1143: "@
1144: extru %1,31,16,%0
1145: ldh%M1 %1,%0"
1146: [(set_attr "type" "unary,load")])
1147:
1148: (define_expand "zero_extendqihi2"
1149: [(set (match_operand:HI 0 "register_operand" "")
1150: (zero_extend:HI
1151: (match_operand:QI 1 "general_operand" "")))]
1152: ""
1153: "
1154: {
1155: if (GET_CODE (operand1) == MEM
1156: && symbolic_operand (XEXP (operand1, 0), Pmode))
1157: {
1158: rtx temp = copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode,
1159: XEXP (operand1, 0)));
1160: operands[1] = gen_rtx (MEM, QImode,
1161: gen_rtx (LO_SUM, Pmode,
1162: temp, XEXP (operand1, 0)));
1163: }
1164: }")
1165:
1166: (define_insn ""
1167: [(set (match_operand:HI 0 "register_operand" "=r,r")
1168: (zero_extend:HI
1169: (match_operand:QI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
1170: ""
1171: "@
1172: extru %1,31,8,%0
1173: ldb%M1 %1,%0"
1174: [(set_attr "type" "unary,load")
1175: (set_attr "length" "1")])
1176:
1177: (define_expand "zero_extendqisi2"
1178: [(set (match_operand:SI 0 "register_operand" "")
1179: (zero_extend:SI
1180: (match_operand:QI 1 "general_operand" "")))]
1181: ""
1182: "
1183: {
1184: if (GET_CODE (operand1) == MEM
1185: && symbolic_operand (XEXP (operand1, 0), Pmode))
1186: {
1187: rtx temp = copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode,
1188: XEXP (operand1, 0)));
1189: operand1 = gen_rtx (MEM, QImode,
1190: gen_rtx (LO_SUM, Pmode,
1191: temp, XEXP (operand1, 0)));
1192: emit_insn (gen_rtx (SET, VOIDmode, operand0,
1193: gen_rtx (ZERO_EXTEND, SImode, operand1)));
1194: DONE;
1195: }
1196: }")
1197:
1198: (define_insn ""
1199: [(set (match_operand:SI 0 "register_operand" "=r,r")
1200: (zero_extend:SI
1201: (match_operand:QI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
1202: ""
1203: "@
1204: extru %1,31,8,%0
1205: ldb%M1 %1,%0"
1206: [(set_attr "type" "unary,load")
1207: (set_attr "length" "1")])
1208:
1209: ;;- sign extension instructions
1210: ;; Note that the one starting from HImode comes before those for QImode
1211: ;; so that a constant operand will match HImode, not QImode.
1212:
1213: (define_insn "extendhisi2"
1214: [(set (match_operand:SI 0 "register_operand" "=r")
1215: (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1216: ""
1217: "extrs %1,31,16,%0"
1218: [(set_attr "type" "unary")])
1219:
1220: (define_insn "extendqihi2"
1221: [(set (match_operand:HI 0 "register_operand" "=r")
1222: (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1223: ""
1224: "extrs %1,31,8,%0"
1225: [(set_attr "type" "unary")])
1226:
1227: (define_insn "extendqisi2"
1228: [(set (match_operand:SI 0 "register_operand" "=r")
1229: (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1230: ""
1231: "extrs %1,31,8,%0"
1232: [(set_attr "type" "unary")])
1233:
1234: ;; Conversions between float and double.
1235:
1236: (define_insn "extendsfdf2"
1237: [(set (match_operand:DF 0 "register_operand" "=fx")
1238: (float_extend:DF
1239: (match_operand:SF 1 "register_operand" "fx")))]
1240: ""
1241: "fcnvff,sgl,dbl %1,%0"
1242: [(set_attr "type" "fpalu")])
1243:
1244: (define_insn "truncdfsf2"
1245: [(set (match_operand:SF 0 "register_operand" "=fx")
1246: (float_truncate:SF
1247: (match_operand:DF 1 "register_operand" "fx")))]
1248: ""
1249: "fcnvff,dbl,sgl %1,%0"
1250: [(set_attr "type" "fpalu")])
1251:
1252: ;; Conversion between fixed point and floating point.
1253: ;; Note that among the fix-to-float insns
1254: ;; the ones that start with SImode come first.
1255: ;; That is so that an operand that is a CONST_INT
1256: ;; (and therefore lacks a specific machine mode).
1257: ;; will be recognized as SImode (which is always valid)
1258: ;; rather than as QImode or HImode.
1259:
1260: ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
1261: ;; to be reloaded by putting the constant into memory.
1262: ;; It must come before the more general floatsisf2 pattern.
1263: (define_insn ""
1264: [(set (match_operand:SF 0 "general_operand" "=fx")
1265: (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
1266: ""
1267: "* return output_floatsisf2 (operands);"
1268: [(set_attr "type" "fpalu")
1269: (set_attr "length" "3")])
1270:
1271: (define_insn "floatsisf2"
1272: [(set (match_operand:SF 0 "general_operand" "=fx")
1273: (float:SF (match_operand:SI 1 "register_operand" "fxr")))]
1274: ""
1275: "* return output_floatsisf2 (operands);"
1276: [(set_attr "type" "fpalu")
1277: (set_attr "length" "3")])
1278:
1279: ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
1280: ;; to be reloaded by putting the constant into memory.
1281: ;; It must come before the more general floatsidf2 pattern.
1282: (define_insn ""
1283: [(set (match_operand:DF 0 "general_operand" "=fx")
1284: (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
1285: ""
1286: "* return output_floatsidf2 (operands);"
1287: [(set_attr "type" "fpalu")
1288: (set_attr "length" "3")])
1289:
1290: (define_insn "floatsidf2"
1291: [(set (match_operand:DF 0 "general_operand" "=fx")
1292: (float:DF (match_operand:SI 1 "register_operand" "fxr")))]
1293: ""
1294: "* return output_floatsidf2 (operands);"
1295: [(set_attr "type" "fpalu")
1296: (set_attr "length" "3")])
1297:
1298: ;; Convert a float to an actual integer.
1299: ;; Truncation is performed as part of the conversion.
1300:
1301: (define_insn "fix_truncsfsi2"
1302: [(set (match_operand:SI 0 "register_operand" "=r,fx")
1303: (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "fx,fx"))))
1304: (clobber (match_scratch:SI 2 "=&fx,X"))]
1305: ""
1306: "@
1307: fcnvfxt,sgl,sgl %1,%2\;fstws %2,-16(30)\;ldw -16(30),%0
1308: fcnvfxt,sgl,sgl %1,%0"
1309: [(set_attr "type" "fpalu,fpalu")
1310: (set_attr "length" "3,1")])
1311:
1312: (define_insn "fix_truncdfsi2"
1313: [(set (match_operand:SI 0 "register_operand" "=r,fx")
1314: (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "fx,fx"))))
1315: (clobber (match_scratch:SI 2 "=&fx,X"))]
1316: ""
1317: "@
1318: fcnvfxt,dbl,sgl %1,%2\;fstws %2,-16(30)\;ldw -16(30),%0
1319: fcnvfxt,dbl,sgl %1,%0"
1320: [(set_attr "type" "fpalu,fpalu")
1321: (set_attr "length" "3,1")])
1322:
1323:
1324: ;;- arithmetic instructions
1325:
1326: (define_insn "adddi3"
1327: [(set (match_operand:DI 0 "register_operand" "=r")
1328: (plus:DI (match_operand:DI 1 "register_operand" "%r")
1329: (match_operand:DI 2 "register_operand" "r")))]
1330: ""
1331: "add %R1,%R2,%R0\;addc %1,%2,%0"
1332: [(set_attr "type" "binary")
1333: (set_attr "length" "2")])
1334:
1335: (define_insn "addsi3"
1336: [(set (match_operand:SI 0 "register_operand" "=r,r")
1337: (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
1338: (match_operand:SI 2 "arith_operand" "r,J")))]
1339: ""
1340: "@
1341: add %1,%2,%0
1342: ldo %2(%1),%0")
1343:
1344: (define_insn "subdi3"
1345: [(set (match_operand:DI 0 "register_operand" "=r")
1346: (minus:DI (match_operand:DI 1 "register_operand" "r")
1347: (match_operand:DI 2 "register_operand" "r")))]
1348: ""
1349: "sub %R1,%R2,%R0\;subb %1,%2,%0"
1350: [(set_attr "length" "2")])
1351:
1352: (define_insn "subsi3"
1353: [(set (match_operand:SI 0 "register_operand" "=r,r")
1354: (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
1355: (match_operand:SI 2 "register_operand" "r,r")))]
1356: ""
1357: "@
1358: sub %1,%2,%0
1359: subi %1,%2,%0")
1360:
1361: ;; The mulsi3 insns set up registers for the millicode call.
1362:
1363: (define_expand "mulsi3"
1364: [(set (reg:SI 26) (match_operand:SI 1 "srcsi_operand" ""))
1365: (set (reg:SI 25) (match_operand:SI 2 "srcsi_operand" ""))
1366: (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
1367: (clobber (match_scratch:SI 3 ""))
1368: (clobber (reg:SI 26))
1369: (clobber (reg:SI 25))
1370: (clobber (reg:SI 31))])
1371: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1372: ""
1373: "")
1374:
1375: (define_insn ""
1376: [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
1377: (clobber (match_scratch:SI 0 "=a"))
1378: (clobber (reg:SI 26))
1379: (clobber (reg:SI 25))
1380: (clobber (reg:SI 31))]
1381: ""
1382: "* return output_mul_insn (0);"
1383: [(set_attr "type" "milli")])
1384:
1385: ;;; Division and mod.
1386:
1387: (define_expand "divsi3"
1388: [(set (reg:SI 26) (match_operand:SI 1 "srcsi_operand" ""))
1389: (set (reg:SI 25) (match_operand:SI 2 "srcsi_operand" ""))
1390: (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
1391: (clobber (match_scratch:SI 3 ""))
1392: (clobber (reg:SI 26))
1393: (clobber (reg:SI 25))
1394: (clobber (reg:SI 31))])
1395: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1396: ""
1397: "
1398: {
1399: if (!(GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const(operands, 0)))
1400: {
1401: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1402: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1403: emit
1404: (gen_rtx
1405: (PARALLEL, VOIDmode,
1406: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1407: gen_rtx (DIV, SImode,
1408: gen_rtx (REG, SImode, 26),
1409: gen_rtx (REG, SImode, 25))),
1410: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1411: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1412: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1413: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1414: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1415: }
1416: DONE;
1417: }")
1418:
1419: (define_insn ""
1420: [(set (reg:SI 29)
1421: (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
1422: (clobber (match_scratch:SI 1 "=a"))
1423: (clobber (reg:SI 26))
1424: (clobber (reg:SI 25))
1425: (clobber (reg:SI 31))]
1426: ""
1427: "*
1428: return output_div_insn (operands, 0);"
1429: [(set_attr "type" "milli")])
1430:
1431: (define_expand "udivsi3"
1432: [(set (reg:SI 26) (match_operand:SI 1 "srcsi_operand" ""))
1433: (set (reg:SI 25) (match_operand:SI 2 "srcsi_operand" ""))
1434: (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
1435: (clobber (match_scratch:SI 3 ""))
1436: (clobber (reg:SI 26))
1437: (clobber (reg:SI 25))
1438: (clobber (reg:SI 31))])
1439: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1440: ""
1441: "
1442: {
1443: if (!(GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const(operands, 1)))
1444: {
1445: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1446: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1447: emit
1448: (gen_rtx
1449: (PARALLEL, VOIDmode,
1450: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1451: gen_rtx (UDIV, SImode,
1452: gen_rtx (REG, SImode, 26),
1453: gen_rtx (REG, SImode, 25))),
1454: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1455: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1456: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1457: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1458: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1459: }
1460: DONE;
1461: }")
1462:
1463: (define_insn ""
1464: [(set (reg:SI 29)
1465: (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
1466: (clobber (match_scratch:SI 1 "=a"))
1467: (clobber (reg:SI 26))
1468: (clobber (reg:SI 25))
1469: (clobber (reg:SI 31))]
1470: ""
1471: "*
1472: return output_div_insn (operands, 1);"
1473: [(set_attr "type" "milli")])
1474:
1475: (define_expand "modsi3"
1476: [(set (reg:SI 26) (match_operand:SI 1 "srcsi_operand" ""))
1477: (set (reg:SI 25) (match_operand:SI 2 "srcsi_operand" ""))
1478: (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
1479: (clobber (match_scratch:SI 3 ""))
1480: (clobber (reg:SI 26))
1481: (clobber (reg:SI 25))
1482: (clobber (reg:SI 31))])
1483: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1484: ""
1485: "
1486: {
1487: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1488: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1489: emit
1490: (gen_rtx
1491: (PARALLEL, VOIDmode,
1492: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1493: gen_rtx (MOD, SImode,
1494: gen_rtx (REG, SImode, 26),
1495: gen_rtx (REG, SImode, 25))),
1496: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1497: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1498: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1499: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1500: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1501: DONE;
1502: }")
1503:
1504: (define_insn ""
1505: [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
1506: (clobber (match_scratch:SI 0 "=a"))
1507: (clobber (reg:SI 26))
1508: (clobber (reg:SI 25))
1509: (clobber (reg:SI 31))]
1510: ""
1511: "*
1512: return output_mod_insn (0);"
1513: [(set_attr "type" "milli")])
1514:
1515: (define_expand "umodsi3"
1516: [(set (reg:SI 26) (match_operand:SI 1 "srcsi_operand" ""))
1517: (set (reg:SI 25) (match_operand:SI 2 "srcsi_operand" ""))
1518: (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
1519: (clobber (match_scratch:SI 3 ""))
1520: (clobber (reg:SI 26))
1521: (clobber (reg:SI 25))
1522: (clobber (reg:SI 31))])
1523: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1524: ""
1525: "
1526: {
1527: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1528: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1529: emit
1530: (gen_rtx
1531: (PARALLEL, VOIDmode,
1532: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1533: gen_rtx (UMOD, SImode,
1534: gen_rtx (REG, SImode, 26),
1535: gen_rtx (REG, SImode, 25))),
1536: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1537: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1538: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1539: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1540: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1541: DONE;
1542: }")
1543:
1544: (define_insn ""
1545: [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
1546: (clobber (match_scratch:SI 0 "=a"))
1547: (clobber (reg:SI 26))
1548: (clobber (reg:SI 25))
1549: (clobber (reg:SI 31))]
1550: ""
1551: "*
1552: return output_mod_insn (1);"
1553: [(set_attr "type" "milli")])
1554:
1555: ;;- and instructions
1556: ;; We define DImode `and` so with DImode `not` we can get
1557: ;; DImode `andn`. Other combinations are possible.
1558:
1559: (define_expand "anddi3"
1560: [(set (match_operand:DI 0 "register_operand" "")
1561: (and:DI (match_operand:DI 1 "arith_double_operand" "")
1562: (match_operand:DI 2 "arith_double_operand" "")))]
1563: ""
1564: "
1565: {
1566: if (! register_operand (operands[1], DImode)
1567: || ! register_operand (operands[2], DImode))
1568: /* Let GCC break this into word-at-a-time operations. */
1569: FAIL;
1570: }")
1571:
1572: (define_insn ""
1573: [(set (match_operand:DI 0 "register_operand" "=r")
1574: (and:DI (match_operand:DI 1 "register_operand" "%r")
1575: (match_operand:DI 2 "register_operand" "r")))]
1576: ""
1577: "and %1,%2,%0\;and %R1,%R2,%R0"
1578: [(set_attr "length" "2")])
1579:
1580: (define_insn "andsi3"
1581: [(set (match_operand:SI 0 "register_operand" "=r")
1582: (and:SI (match_operand:SI 1 "register_operand" "%r")
1583: (match_operand:SI 2 "register_operand" "r")))]
1584: ""
1585: "and %1,%2,%0")
1586:
1587: (define_insn ""
1588: [(set (match_operand:DI 0 "register_operand" "=r")
1589: (and:DI (match_operand:DI 1 "register_operand" "r")
1590: (not:DI (match_operand:DI 2 "register_operand" "r"))))]
1591: ""
1592: "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
1593: [(set_attr "length" "2")])
1594:
1595: (define_insn ""
1596: [(set (match_operand:SI 0 "register_operand" "=r")
1597: (and:SI (match_operand:SI 1 "register_operand" "%r")
1598: (not:SI (match_operand:SI 2 "register_operand" "r"))))]
1599: ""
1600: "andcm %1,%2,%0")
1601:
1602:
1603: (define_expand "iordi3"
1604: [(set (match_operand:DI 0 "register_operand" "")
1605: (ior:DI (match_operand:DI 1 "arith_double_operand" "")
1606: (match_operand:DI 2 "arith_double_operand" "")))]
1607: ""
1608: "
1609: {
1610: if (! register_operand (operands[1], DImode)
1611: || ! register_operand (operands[2], DImode))
1612: /* Let GCC break this into word-at-a-time operations. */
1613: FAIL;
1614: }")
1615:
1616: (define_insn ""
1617: [(set (match_operand:DI 0 "register_operand" "=r")
1618: (ior:DI (match_operand:DI 1 "register_operand" "%r")
1619: (match_operand:DI 2 "register_operand" "r")))]
1620: ""
1621: "or %1,%2,%0\;or %R1,%R2,%R0"
1622: [(set_attr "length" "2")])
1623:
1624: (define_insn "iorsi3"
1625: [(set (match_operand:SI 0 "register_operand" "=r")
1626: (ior:SI (match_operand:SI 1 "register_operand" "%r")
1627: (match_operand:SI 2 "register_operand" "r")))]
1628: ""
1629: "or %1,%2,%0")
1630:
1631: (define_expand "xordi3"
1632: [(set (match_operand:DI 0 "register_operand" "")
1633: (xor:DI (match_operand:DI 1 "arith_double_operand" "")
1634: (match_operand:DI 2 "arith_double_operand" "")))]
1635: ""
1636: "
1637: {
1638: if (! register_operand (operands[1], DImode)
1639: || ! register_operand (operands[2], DImode))
1640: /* Let GCC break this into word-at-a-time operations. */
1641: FAIL;
1642: }")
1643:
1644: (define_insn ""
1645: [(set (match_operand:DI 0 "register_operand" "=r")
1646: (xor:DI (match_operand:DI 1 "register_operand" "%r")
1647: (match_operand:DI 2 "register_operand" "r")))]
1648: ""
1649: "xor %1,%2,%0\;xor %R1,%R2,%R0"
1650: [(set_attr "length" "2")])
1651:
1652: (define_insn "xorsi3"
1653: [(set (match_operand:SI 0 "register_operand" "=r")
1654: (xor:SI (match_operand:SI 1 "register_operand" "%r")
1655: (match_operand:SI 2 "register_operand" "r")))]
1656: ""
1657: "xor %r1,%2,%0")
1658:
1659: (define_insn "negdi2"
1660: [(set (match_operand:DI 0 "register_operand" "=r")
1661: (neg:DI (match_operand:DI 1 "register_operand" "r")))]
1662: ""
1663: "sub 0,%R1,%R0\;subb 0,%1,%0"
1664: [(set_attr "type" "unary")
1665: (set_attr "length" "2")])
1666:
1667: (define_insn "negsi2"
1668: [(set (match_operand:SI 0 "register_operand" "=r")
1669: (neg:SI (match_operand:SI 1 "register_operand" "r")))]
1670: ""
1671: "@
1672: sub 0,%1,%0"
1673: [(set_attr "type" "unary")])
1674:
1675: (define_expand "one_cmpldi2"
1676: [(set (match_operand:DI 0 "register_operand" "")
1677: (not:DI (match_operand:DI 1 "arith_double_operand" "")))]
1678: ""
1679: "
1680: {
1681: if (! register_operand (operands[1], DImode))
1682: FAIL;
1683: }")
1684:
1685: (define_insn ""
1686: [(set (match_operand:DI 0 "register_operand" "=r")
1687: (not:DI (match_operand:DI 1 "arith_double_operand" "r")))]
1688: ""
1689: "uaddcm 0,%1,%0\;uaddcm 0,%R1,%R0"
1690: [(set_attr "type" "unary")
1691: (set_attr "length" "2")])
1692:
1693: (define_insn "one_cmplsi2"
1694: [(set (match_operand:SI 0 "register_operand" "=r")
1695: (not:SI (match_operand:SI 1 "register_operand" "r")))]
1696: ""
1697: "uaddcm 0,%1,%0"
1698: [(set_attr "type" "unary")])
1699:
1700: ;; Floating point arithmetic instructions.
1701:
1702: (define_insn "adddf3"
1703: [(set (match_operand:DF 0 "register_operand" "=fx")
1704: (plus:DF (match_operand:DF 1 "register_operand" "fx")
1705: (match_operand:DF 2 "register_operand" "fx")))]
1706: ""
1707: "fadd,dbl %1,%2,%0"
1708: [(set_attr "type" "fpalu")])
1709:
1710: (define_insn "addsf3"
1711: [(set (match_operand:SF 0 "register_operand" "=fx")
1712: (plus:SF (match_operand:SF 1 "register_operand" "fx")
1713: (match_operand:SF 2 "register_operand" "fx")))]
1714: ""
1715: "fadd,sgl %1,%2,%0"
1716: [(set_attr "type" "fpalu")])
1717:
1718: (define_insn "subdf3"
1719: [(set (match_operand:DF 0 "register_operand" "=fx")
1720: (minus:DF (match_operand:DF 1 "register_operand" "fx")
1721: (match_operand:DF 2 "register_operand" "fx")))]
1722: ""
1723: "fsub,dbl %1,%2,%0"
1724: [(set_attr "type" "fpalu")])
1725:
1726: (define_insn "subsf3"
1727: [(set (match_operand:SF 0 "register_operand" "=fx")
1728: (minus:SF (match_operand:SF 1 "register_operand" "fx")
1729: (match_operand:SF 2 "register_operand" "fx")))]
1730: ""
1731: "fsub,sgl %1,%2,%0"
1732: [(set_attr "type" "fpalu")])
1733:
1734: (define_insn "muldf3"
1735: [(set (match_operand:DF 0 "register_operand" "=fx")
1736: (mult:DF (match_operand:DF 1 "register_operand" "fx")
1737: (match_operand:DF 2 "register_operand" "fx")))]
1738: ""
1739: "fmpy,dbl %1,%2,%0"
1740: [(set_attr "type" "fpmul")])
1741:
1742: (define_insn "mulsf3"
1743: [(set (match_operand:SF 0 "register_operand" "=fx")
1744: (mult:SF (match_operand:SF 1 "register_operand" "fx")
1745: (match_operand:SF 2 "register_operand" "fx")))]
1746: ""
1747: "fmpy,sgl %1,%2,%0"
1748: [(set_attr "type" "fpmul")])
1749:
1750: (define_insn "divdf3"
1751: [(set (match_operand:DF 0 "register_operand" "=fx")
1752: (div:DF (match_operand:DF 1 "register_operand" "fx")
1753: (match_operand:DF 2 "register_operand" "fx")))]
1754: ""
1755: "fdiv,dbl %1,%2,%0"
1756: [(set_attr "type" "fpdivdbl")])
1757:
1758: (define_insn "divsf3"
1759: [(set (match_operand:SF 0 "register_operand" "=fx")
1760: (div:SF (match_operand:SF 1 "register_operand" "fx")
1761: (match_operand:SF 2 "register_operand" "fx")))]
1762: ""
1763: "fdiv,sgl %1,%2,%0"
1764: [(set_attr "type" "fpdivsgl")])
1765:
1766: (define_insn "negdf2"
1767: [(set (match_operand:DF 0 "register_operand" "=fx")
1768: (neg:DF (match_operand:DF 1 "register_operand" "fx")))]
1769: ""
1770: "fsub,dbl 0,%1,%0"
1771: [(set_attr "type" "fpalu")])
1772:
1773: (define_insn "negsf2"
1774: [(set (match_operand:SF 0 "register_operand" "=fx")
1775: (neg:SF (match_operand:SF 1 "register_operand" "fx")))]
1776: ""
1777: "fsub,sgl 0, %1,%0"
1778: [(set_attr "type" "fpalu")])
1779:
1780: (define_insn "absdf2"
1781: [(set (match_operand:DF 0 "register_operand" "=fx")
1782: (abs:DF (match_operand:DF 1 "register_operand" "fx")))]
1783: ""
1784: "fabs,dbl %1,%0"
1785: [(set_attr "type" "fpalu")])
1786:
1787: (define_insn "abssf2"
1788: [(set (match_operand:SF 0 "register_operand" "=fx")
1789: (abs:SF (match_operand:SF 1 "register_operand" "fx")))]
1790: ""
1791: "fabs,sgl %1,%0"
1792: [(set_attr "type" "fpalu")])
1793:
1794: (define_insn "sqrtdf2"
1795: [(set (match_operand:DF 0 "register_operand" "=fx")
1796: (sqrt:DF (match_operand:DF 1 "register_operand" "fx")))]
1797: ""
1798: "fsqrt,dbl %1,%0"
1799: [(set_attr "type" "fpsqrtdbl")])
1800:
1801: (define_insn "sqrtsf2"
1802: [(set (match_operand:SF 0 "register_operand" "=fx")
1803: (sqrt:SF (match_operand:SF 1 "register_operand" "fx")))]
1804: ""
1805: "fsqrt,sgl %1,%0"
1806: [(set_attr "type" "fpsqrtsgl")])
1807:
1808: ;;- Shift instructions
1809:
1810: ;; Optimized special case of shifting.
1811:
1812: (define_insn ""
1813: [(set (match_operand:SI 0 "register_operand" "=r")
1814: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
1815: (const_int 24)))]
1816: ""
1817: "ldb%M1 %1,%0")
1818:
1819: (define_insn ""
1820: [(set (match_operand:SI 0 "register_operand" "=r")
1821: (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
1822: (const_int 2))
1823: (match_operand:SI 1 "register_operand" "r")))]
1824: ""
1825: "sh1add %2,%1,%0")
1826:
1827: (define_insn ""
1828: [(set (match_operand:SI 0 "register_operand" "=r")
1829: (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
1830: (const_int 4))
1831: (match_operand:SI 1 "register_operand" "r")))]
1832: ""
1833: "sh2add %2,%1,%0")
1834:
1835: (define_insn ""
1836: [(set (match_operand:SI 0 "register_operand" "=r")
1837: (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
1838: (const_int 8))
1839: (match_operand:SI 1 "register_operand" "r")))]
1840: ""
1841: "sh3add %2,%1,%0")
1842:
1843: (define_insn "sar_sub"
1844: [(set (match_operand:SI 0 "register_operand" "=r")
1845: (if_then_else (gtu:SI (match_operand:SI 2 "register_operand" "r")
1846: (match_operand:SI 1 "int11_operand" "I"))
1847: (const_int 0)
1848: (minus:SI (match_dup 1) (match_dup 2))))]
1849: ""
1850: "subi,>>= %1,%2,%0\;copy 0,%0"
1851: [(set_attr "length" "2" )])
1852:
1853: (define_expand "ashlsi3"
1854: [(set (match_operand:SI 0 "register_operand" "")
1855: (ashift:SI (match_operand:SI 1 "register_operand" "")
1856: (match_operand:SI 2 "arith5_operand" "")))]
1857: ""
1858: "
1859: {
1860: if (GET_CODE (operands[2]) != CONST_INT)
1861: {
1862: rtx temp = gen_reg_rtx (SImode);
1863: emit_insn (gen_sar_sub (temp,
1864: gen_rtx (CONST_INT, VOIDmode, 31),
1865: operands[2]));
1866: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 112), temp));
1867: emit_insn (gen_rtx (SET, VOIDmode,
1868: operands[0],
1869: gen_rtx (ASHIFT, SImode,
1870: operands[1],
1871: gen_rtx (MINUS, SImode,
1872: gen_rtx (CONST_INT, VOIDmode, 31),
1873: gen_rtx (REG, SImode, 112)))));
1874: DONE;
1875: }
1876: }")
1877:
1878: (define_insn ""
1879: [(set (match_operand:SI 0 "register_operand" "=r")
1880: (ashift:SI (match_operand:SI 1 "register_operand" "r")
1881: (match_operand:SI 2 "int5_operand" "L")))]
1882: ""
1883: "*
1884: {
1885: rtx xoperands[4];
1886: xoperands[0] = operands[0]; xoperands[1] = operands[1];
1887: xoperands[2] = gen_rtx (CONST_INT, VOIDmode,
1888: 31 - INTVAL (operands[2]));
1889: xoperands[3] = gen_rtx (CONST_INT, VOIDmode,
1890: 32 - INTVAL (operands[2]));
1891: output_asm_insn (\"zdep %1,%2,%3,%0\", xoperands);
1892: return \"\";
1893: }")
1894:
1895: (define_insn ""
1896: [(set (match_operand:SI 0 "register_operand" "=r")
1897: (ashift:SI (match_operand:SI 1 "register_operand" "r")
1898: (minus:SI (const_int 31)
1899: (reg:SI 112))))]
1900: ""
1901: "zvdep %1,32,%0")
1902:
1903: (define_expand "ashrsi3"
1904: [(set (match_operand:SI 0 "register_operand" "")
1905: (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
1906: (match_operand:SI 2 "arith5_operand" "")))]
1907: ""
1908: "
1909: {
1910: if (GET_CODE (operands[2]) != CONST_INT)
1911: {
1912: rtx temp = gen_reg_rtx (SImode);
1913: emit_insn (gen_sar_sub (temp,
1914: gen_rtx (CONST_INT, VOIDmode, 31),
1915: operands[2]));
1916: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 112), temp));
1917: emit_insn (gen_rtx (SET, VOIDmode,
1918: operands[0],
1919: gen_rtx (ASHIFTRT, SImode,
1920: operands[1],
1921: gen_rtx (MINUS, SImode,
1922: gen_rtx (CONST_INT, VOIDmode, 31),
1923: gen_rtx (REG, SImode, 112)))));
1924: DONE;
1925: }
1926: }")
1927:
1928: (define_insn ""
1929: [(set (match_operand:SI 0 "register_operand" "=r")
1930: (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
1931: (match_operand:SI 2 "int5_operand" "L")))]
1932: ""
1933: "*
1934: {
1935: rtx xoperands[4];
1936: xoperands[0] = operands[0]; xoperands[1] = operands[1];
1937: xoperands[2] = gen_rtx (CONST_INT, VOIDmode,
1938: 31 - INTVAL (operands[2]));
1939: xoperands[3] = gen_rtx (CONST_INT, VOIDmode,
1940: 32 - INTVAL (operands[2]));
1941: output_asm_insn (\"extrs %1,%2,%3,%0\", xoperands);
1942: return \"\";
1943: }")
1944:
1945:
1946: (define_insn ""
1947: [(set (match_operand:SI 0 "register_operand" "=r")
1948: (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
1949: (minus:SI (const_int 31)
1950: (reg:SI 112))))]
1951: ""
1952: "vextrs %1,32,%0")
1953:
1954: (define_expand "lshrsi3"
1955: [(set (match_operand:SI 0 "register_operand" "")
1956: (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
1957: (match_operand:SI 2 "arith5_operand" "")))]
1958: ""
1959: "
1960: {
1961: if (GET_CODE (operands[2]) != CONST_INT)
1962: {
1963: rtx temp = gen_reg_rtx (SImode);
1964: emit_insn (gen_sar_sub (temp,
1965: gen_rtx (CONST_INT, VOIDmode, 31),
1966: operands[2]));
1967: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 112), temp));
1968: emit_insn (gen_rtx (SET, VOIDmode,
1969: operands[0],
1970: gen_rtx (LSHIFTRT, SImode,
1971: operands[1],
1972: gen_rtx (MINUS, SImode,
1973: gen_rtx (CONST_INT, VOIDmode, 31),
1974: gen_rtx (REG, SImode, 112)))));
1975: DONE;
1976: }
1977: }")
1978:
1979: (define_insn ""
1980: [(set (match_operand:SI 0 "register_operand" "=r")
1981: (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
1982: (match_operand:SI 2 "uint5_operand" "K")))]
1983: ""
1984: "*
1985: {
1986: rtx xoperands[4];
1987: xoperands[0] = operands[0]; xoperands[1] = operands[1];
1988: xoperands[2] = gen_rtx (CONST_INT, VOIDmode,
1989: 31 - INTVAL (operands[2]));
1990: xoperands[3] = gen_rtx (CONST_INT, VOIDmode,
1991: 32 - INTVAL (operands[2]));
1992: output_asm_insn (\"extru %1,%2,%3,%0\", xoperands);
1993: return \"\";
1994: }")
1995:
1996: (define_insn ""
1997: [(set (match_operand:SI 0 "register_operand" "=r")
1998: (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
1999: (minus:SI (const_int 31)
2000: (reg:SI 112))))]
2001: ""
2002: "vextru %1,32,%0")
2003:
2004: ;; Unconditional and other jump instructions.
2005:
2006: (define_insn "jump"
2007: [(set (pc) (label_ref (match_operand 0 "" "")))]
2008: ""
2009: "bl%* %l0,0"
2010: [(set_attr "type" "branch")])
2011:
2012: (define_insn "casesi"
2013: [(set (pc)
2014: (if_then_else (leu (minus:SI
2015: (match_operand:SI 0 "general_operand" "r")
2016: (match_operand:SI 1 "general_operand" "rI"))
2017: (match_operand:SI 2 "general_operand" "rI"))
2018: (plus:SI (mem:SI (plus:SI (pc)
2019: (minus:SI (match_dup 0)
2020: (match_dup 1))))
2021: (label_ref (match_operand 3 "" "")))
2022: (pc)))
2023: (use (label_ref (match_operand 4 "" "")))
2024: (clobber (match_scratch:SI 5 "=r"))]
2025: ""
2026: "*
2027: {
2028: if (GET_CODE (operands[1]) == CONST_INT)
2029: {
2030: if (GET_CODE (operands[2]) == CONST_INT)
2031: {
2032: operands[2] = gen_rtx (CONST_INT, VOIDmode,
2033: INTVAL (operands[1]) + INTVAL (operands[2]));
2034: if (!INT_11_BITS (operands[2]))
2035: {
2036: output_asm_insn (\"ldo %2(0),%5\", operands);
2037: operands[2] = operands[5];
2038: }
2039: }
2040: else
2041: output_asm_insn (\"ldo %1(%2),%2\", operands);
2042: output_asm_insn (\"addi,< %n1,%0,0\", operands);
2043: }
2044: else
2045: {
2046: if (GET_CODE (operands[2]) == CONST_INT)
2047: {
2048: output_asm_insn (\"ldo %2(%1),%5\", operands);
2049: operands[2] = operands[5];
2050: }
2051: output_asm_insn (\"sub,< %0,%1,0\", operands);
2052: }
2053: if (GET_CODE (operands[2]) == CONST_INT)
2054: output_asm_insn (\"addi,<= %n2,%0,0\", operands);
2055: else
2056: output_asm_insn (\"sub,<= %0,%2,0\", operands);
2057: output_asm_insn (\"b,n %l4\", operands);
2058: if (GET_CODE (operands[1]) == CONST_INT)
2059: output_asm_insn (\"ldo %n1(%0),%5\", operands);
2060: else output_asm_insn (\"sub %0,%1,%5\", operands);
2061: return \"blr %5,0\;nop\";
2062: }"
2063: [(set_attr "length" "7")])
2064:
2065: ;; Need nops for the calls because execution is supposed to continue
2066: ;; past; we don't want to nullify an instruction that we need.
2067: ;;- jump to subroutine
2068:
2069: (define_expand "call"
2070: [(parallel [(call (match_operand:SI 0 "" "")
2071: (match_operand 1 "" ""))
2072: (clobber (reg:SI 31))
2073: (clobber (reg:SI 2))])]
2074: ""
2075: "
2076: {
2077: operands[0] = gen_rtx (MEM, SImode, XEXP (operands[0], 0));
2078: }")
2079:
2080: (define_insn ""
2081: [(call (mem:SI (match_operand:SI 0 "call_operand_address" "r,S"))
2082: (match_operand 1 "" "i,i"))
2083: (clobber (reg:SI 31))
2084: (clobber (reg:SI 2))]
2085: ""
2086: "*
2087: {
2088: if (which_alternative == 0)
2089: return \"copy %0,22\;.CALL\\tARGW0=GR\;bl $$dyncall,31\;copy 31,2\";
2090: else
2091: {
2092: output_arg_descriptor (insn);
2093: return \"bl %0,2%#\";
2094: }
2095: }"
2096: [(set_attr "type" "dyncall,call")
2097: (set_attr "length" "3,1")])
2098:
2099: (define_expand "call_value"
2100: [(parallel [(set (match_operand 0 "" "")
2101: (call (match_operand:SI 1 "" "")
2102: (match_operand 2 "" "")))
2103: (clobber (reg:SI 31))
2104: (clobber (reg:SI 2))])]
2105: ;;- Don't use operand 1 for most machines.
2106: ""
2107: "
2108: {
2109: operands[1] = gen_rtx (MEM, SImode, XEXP (operands[1], 0));
2110: }")
2111:
2112: (define_insn ""
2113: [(set (match_operand 0 "" "=rfx,rfx")
2114: (call (mem:SI (match_operand:SI 1 "call_operand_address" "r,S"))
2115: (match_operand 2 "" "i,i")))
2116: (clobber (reg:SI 31))
2117: (clobber (reg:SI 2))]
2118: ;;- Don't use operand 1 for most machines.
2119: ""
2120: "*
2121: {
2122: if (which_alternative == 0)
2123: return \"copy %1,22\;.CALL\\tARGW0=GR\;bl $$dyncall,31\;copy 31,2\";
2124: else
2125: {
2126: output_arg_descriptor (insn);
2127: return \"bl %1,2\;nop\";
2128: }
2129: }"
2130: [(set_attr "type" "dyncall")
2131: (set_attr "length" "3,2")])
2132:
2133: (define_insn "nop"
2134: [(const_int 0)]
2135: ""
2136: "nop")
2137:
2138: ;;; Hope this is only within a function...
2139: (define_insn "indirect_jump"
2140: [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2141: ""
2142: "bv 0(%0)%#"
2143: [(set_attr "type" "branch")])
2144:
2145: (define_insn "extzv"
2146: [(set (match_operand:SI 0 "register_operand" "=r")
2147: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2148: (match_operand:SI 2 "uint5_operand" "")
2149: (match_operand:SI 3 "uint5_operand" "")))]
2150: ""
2151: "extru %1,%3+%2-1,%2,%0")
2152:
2153: (define_insn "extv"
2154: [(set (match_operand:SI 0 "register_operand" "=r")
2155: (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
2156: (match_operand:SI 2 "uint5_operand" "")
2157: (match_operand:SI 3 "uint5_operand" "")))]
2158: ""
2159: "extrs %1,%3+%2-1,%2,%0")
2160:
2161: (define_insn "insv"
2162: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "=r")
2163: (match_operand:SI 1 "uint5_operand" "")
2164: (match_operand:SI 2 "uint5_operand" ""))
2165: (match_operand:SI 3 "register_operand" "r"))]
2166: ""
2167: "dep %3,%2+%1-1,%1,%0")
2168:
2169: ;; This insn is used for some loop tests, typically loops reversed when
2170: ;; strength reduction is used. It is actually created when the instruction
2171: ;; combination phase combines the special loop test. Since this insn
2172: ;; is both a jump insn and has an output, it must deal with it's own
2173: ;; reloads, hence the `m' constraints. The `!' constraints direct reload
2174: ;; to not choose the register alternatives in the event a reload is needed.
2175:
2176: (define_insn "decrement_and_branch_until_zero"
2177: [(set (pc)
2178: (if_then_else
2179: (ge (plus:SI (match_operand:SI 0 "register_operand" "+!r,m")
2180: (const_int -1))
2181: (const_int 0))
2182: (label_ref (match_operand 1 "" ""))
2183: (pc)))
2184: (set (match_dup 0)
2185: (plus:SI (match_dup 0)
2186: (const_int -1)))
2187: (clobber (match_scratch:SI 2 "=X,r"))]
2188: "find_reg_note (insn, REG_NONNEG, 0)"
2189: "*
2190: {
2191: if (which_alternative == 0)
2192: if (get_attr_length (insn) == 1)
2193: return \"addib,>= -1,%0,%1%#\";
2194: else
2195: return \"addi,< -1,%0,%0\;bl %1,0%#\";
2196: else
2197: {
2198: output_asm_insn (\"ldw %0,%2\;ldo -1(%2),%2\;stw %2,%0\", operands);
2199: if (get_attr_length (insn) == 4)
2200: return \"comb,> 0,%2,%1%#\";
2201: else
2202: return \"comclr,<= 0,%2,0\;bl %1,0%#\";
2203: }
2204: }"
2205: [(set_attr "type" "cbranch")
2206: (set (attr "length")
2207: (if_then_else (eq (symbol_ref "which_alternative") (const_int 0))
2208: (if_then_else (lt (abs (minus (match_dup 1)
2209: (plus (pc) (const_int 2))))
2210: (const_int 1023))
2211: (const_int 1)
2212: (const_int 2))
2213: (if_then_else (lt (match_dup 1)
2214: (pc))
2215: (if_then_else
2216: (lt (abs (minus (match_dup 1)
2217: (plus (pc)
2218: (const_int 5))))
2219: (const_int 1023))
2220: (const_int 4)
2221: (const_int 5))
2222: (if_then_else
2223: (lt (abs (minus (match_dup 1)
2224: (plus (pc)
2225: (const_int 2))))
2226: (const_int 1023))
2227: (const_int 4)
2228: (const_int 5)))))])
2229:
2230:
2231:
2232: ;;- Local variables:
2233: ;;- mode:emacs-lisp
2234: ;;- comment-start: ";;- "
2235: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2236: ;;- eval: (modify-syntax-entry ?[ "(]")
2237: ;;- eval: (modify-syntax-entry ?] ")[")
2238: ;;- eval: (modify-syntax-entry ?{ "(}")
2239: ;;- eval: (modify-syntax-entry ?} "){")
2240: ;;- End:
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