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1.1 root 1: ;;- Machine description for HP PA-RISC architecture for GNU C compiler
2: ;; Copyright (C) 1992 Free Software Foundation, Inc.
3: ;; Contributed by the Center for Software Science at the University
1.1.1.2 ! root 4: ;; of Utah.
1.1 root 5:
6: ;; This file is part of GNU CC.
7:
8: ;; GNU CC is free software; you can redistribute it and/or modify
9: ;; it under the terms of the GNU General Public License as published by
10: ;; the Free Software Foundation; either version 2, or (at your option)
11: ;; any later version.
12:
13: ;; GNU CC is distributed in the hope that it will be useful,
14: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
15: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16: ;; GNU General Public License for more details.
17:
18: ;; You should have received a copy of the GNU General Public License
19: ;; along with GNU CC; see the file COPYING. If not, write to
20: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21:
22: ;; This gcc Version 2 machine description is inspired by sparc.md and
23: ;; mips.md.
24:
25: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
26:
27: ;; Insn type. Used to default other attribute values.
28:
29: ;; type "unary" insns have one input operand (1) and one output operand (0)
30: ;; type "binary" insns have two input operands (1,2) and one output (0)
31:
32: (define_attr "type"
1.1.1.2 ! root 33: "move,unary,binary,compare,load,store,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmul,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,misc,milli"
1.1 root 34: (const_string "binary"))
35:
36: ;; Length (in # of insns).
37: (define_attr "length" ""
38: (cond [(eq_attr "type" "load,fpload")
39: (if_then_else (match_operand 1 "symbolic_memory_operand" "")
40: (const_int 2) (const_int 1))
41:
42: (eq_attr "type" "store,fpstore")
43: (if_then_else (match_operand 0 "symbolic_memory_operand" "")
44: (const_int 2) (const_int 1))
45:
46: (eq_attr "type" "binary")
47: (if_then_else (match_operand 2 "arith_operand" "")
48: (const_int 1) (const_int 3))
49:
50: (eq_attr "type" "move,unary")
51: (if_then_else (match_operand 1 "arith_operand" "")
52: (const_int 1) (const_int 2))]
53:
54: (const_int 1)))
55:
56: (define_asm_attributes
57: [(set_attr "length" "1")
58: (set_attr "type" "multi")])
59:
60: ;; Attributes for instruction and branch scheduling
61:
62: (define_attr "in_branch_delay" "false,true"
1.1.1.2 ! root 63: (if_then_else (and (eq_attr "type" "!branch,cbranch,fbranch,call,dyncall,multi,milli")
1.1 root 64: (eq_attr "length" "1"))
65: (const_string "true")
66: (const_string "false")))
67:
1.1.1.2 ! root 68: ;; Unconditional branch, call, and millicode call delay slot description.
! 69: (define_delay (eq_attr "type" "branch,call,milli")
! 70: [(eq_attr "in_branch_delay" "true") (nil) (nil)])
! 71:
! 72: ;; Floating point conditional branch delay slot description.
! 73: (define_delay (eq_attr "type" "fbranch")
1.1 root 74: [(eq_attr "in_branch_delay" "true")
1.1.1.2 ! root 75: (eq_attr "in_branch_delay" "true")
! 76: (nil)])
1.1 root 77:
1.1.1.2 ! root 78: ;; Integer conditional branch delay slot description.
1.1 root 79: (define_delay (eq_attr "type" "cbranch")
80: [(eq_attr "in_branch_delay" "true") (nil) (nil)])
81:
82: ;; Function units of the HPPA. The following data is for the "Snake"
83: ;; (Mustang CPU + Timex FPU) because that's what I have the docs for.
84: ;; Scheduling instructions for PA-83 machines according to the Snake
85: ;; constraints shouldn't hurt.
86:
87: ;; (define_function_unit {name} {num-units} {n-users} {test}
1.1.1.2 ! root 88: ;; {ready-delay} {issue-delay} [{conflict-list}])
1.1 root 89:
90: ;; The integer ALU.
91: ;; (Noted only for documentation; units that take one cycle do not need to
92: ;; be specified.)
93:
94: ;; (define_function_unit "alu" 1 0
95: ;; (eq_attr "type" "unary,binary,move,address") 1 0)
96:
97:
98: ;; Memory. Disregarding Cache misses, the Mustang memory times are:
1.1.1.2 ! root 99: ;; load: 2
1.1 root 100: ;; store, fpstore: 3, no D-cache operations should be scheduled.
101: ;; fpload: 3 (really 2 for flops, but I don't think we can specify that).
102:
1.1.1.2 ! root 103: (define_function_unit "memory" 1 1 (eq_attr "type" "load") 2 0)
1.1 root 104: (define_function_unit "memory" 1 1 (eq_attr "type" "store,fpstore") 3 0)
105: (define_function_unit "memory" 1 1 (eq_attr "type" "fpload") 3 0)
106:
107: ;; The Timex has two floating-point units: ALU, and MUL/DIV/SQRT unit.
108: ;; Timings:
109: ;; Instruction Time Unit Minimum Distance (unit contention)
110: ;; fcpy 3 ALU 2
111: ;; fabs 3 ALU 2
112: ;; fadd 3 ALU 2
113: ;; fsub 3 ALU 2
114: ;; fcmp 3 ALU 2
115: ;; fcnv 3 ALU 2
116: ;; fmpyadd 3 ALU,MPY 2
117: ;; fmpysub 3 ALU,MPY 2
118: ;; fmpycfxt 3 ALU,MPY 2
119: ;; fmpy 3 MPY 2
120: ;; fmpyi 3 MPY 2
121: ;; fdiv,sgl 10 MPY 10
122: ;; fdiv,dbl 12 MPY 12
123: ;; fsqrt,sgl 14 MPY 14
124: ;; fsqrt,dbl 18 MPY 18
125:
1.1.1.2 ! root 126: (define_function_unit "fp_alu" 1 0 (eq_attr "type" "fpcc") 4 2)
1.1 root 127: (define_function_unit "fp_alu" 1 0 (eq_attr "type" "fpalu") 3 2)
128: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpmul") 3 2)
129: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpdivsgl") 10 10)
130: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpdivdbl") 12 12)
131: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpsqrtsgl") 14 14)
132: (define_function_unit "fp_mpy" 1 0 (eq_attr "type" "fpsqrtdbl") 18 18)
133:
134: ;; Compare instructions.
135: ;; This controls RTL generation and register allocation.
136:
1.1.1.2 ! root 137: ;; We generate RTL for comparisons and branches by having the cmpxx
1.1 root 138: ;; patterns store away the operands. Then, the scc and bcc patterns
139: ;; emit RTL for both the compare and the branch.
140: ;;
141:
142: (define_expand "cmpsi"
143: [(set (reg:CC 0)
144: (compare:CC (match_operand:SI 0 "reg_or_0_operand" "")
145: (match_operand:SI 1 "arith5_operand" "")))]
146: ""
147: "
148: {
149: hppa_compare_op0 = operands[0];
150: hppa_compare_op1 = operands[1];
151: hppa_branch_type = CMP_SI;
152: DONE;
153: }")
154:
155: (define_expand "cmpsf"
156: [(set (reg:CCFP 0)
157: (compare:CCFP (match_operand:SF 0 "register_operand" "")
158: (match_operand:SF 1 "register_operand" "")))]
159: ""
160: "
161: {
162: hppa_compare_op0 = operands[0];
163: hppa_compare_op1 = operands[1];
164: hppa_branch_type = CMP_SF;
165: DONE;
166: }")
167:
168: (define_expand "cmpdf"
169: [(set (reg:CCFP 0)
170: (compare:CCFP (match_operand:DF 0 "register_operand" "")
171: (match_operand:DF 1 "register_operand" "")))]
172: ""
173: "
174: {
175: hppa_compare_op0 = operands[0];
176: hppa_compare_op1 = operands[1];
177: hppa_branch_type = CMP_DF;
178: DONE;
179: }")
180:
181: (define_insn ""
182: [(set (reg:CCFP 0)
183: (match_operator:CCFP 2 "comparison_operator"
184: [(match_operand:SF 0 "register_operand" "fx")
185: (match_operand:SF 1 "register_operand" "fx")]))]
186: ""
187: "fcmp,sgl,%Y2 %0,%1"
188: [(set_attr "type" "fpcc")])
189:
190: (define_insn ""
191: [(set (reg:CCFP 0)
192: (match_operator:CCFP 2 "comparison_operator"
193: [(match_operand:DF 0 "register_operand" "fx")
194: (match_operand:DF 1 "register_operand" "fx")]))]
195: ""
196: "fcmp,dbl,%Y2 %0,%1"
197: [(set_attr "type" "fpcc")])
198:
199: ;; scc insns.
200:
201: (define_insn ""
202: [(set (match_operand:SI 0 "register_operand" "=r")
203: (match_operator:CCFP 1 "comparison_operator" [(reg:CCFP 0)
204: (const_int 0)]))]
205: ""
206: "copy 0,%0\;ftest\;ldi 1,%0"
207: [(set_attr "type" "unary")
208: (set_attr "length" "3")])
209:
210: (define_expand "seq"
211: [(set (match_operand:SI 0 "register_operand" "")
1.1.1.2 ! root 212: (eq:SI (match_dup 1)
1.1 root 213: (match_dup 2)))]
214: ""
215: "
216: {
217: if (hppa_branch_type != CMP_SI)
218: {
219: emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
220: emit_insn (gen_scond_fp (EQ, operands[0]));
221: DONE;
222: }
223: /* set up operands from compare. */
224: operands[1] = hppa_compare_op0;
225: operands[2] = hppa_compare_op1;
226: /* fall through and generate default code */
227: }")
228:
229: (define_expand "sne"
1.1.1.2 ! root 230: [(set (match_operand:SI 0 "register_operand" "")
! 231: (ne:SI (match_dup 1)
1.1 root 232: (match_dup 2)))]
233: ""
234: "
235: {
236: if (hppa_branch_type != CMP_SI)
237: {
238: emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
239: emit_insn (gen_scond_fp (NE, operands[0]));
240: DONE;
241: }
242: operands[1] = hppa_compare_op0;
243: operands[2] = hppa_compare_op1;
244: }")
245:
246: (define_expand "slt"
1.1.1.2 ! root 247: [(set (match_operand:SI 0 "register_operand" "")
! 248: (lt:SI (match_dup 1)
1.1 root 249: (match_dup 2)))]
250: ""
251: "
252: {
253: if (hppa_branch_type != CMP_SI)
254: {
255: emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
256: emit_insn (gen_scond_fp (LT, operands[0]));
257: DONE;
258: }
259: operands[1] = hppa_compare_op0;
260: operands[2] = hppa_compare_op1;
261: }")
262:
263: (define_expand "sgt"
1.1.1.2 ! root 264: [(set (match_operand:SI 0 "register_operand" "")
! 265: (gt:SI (match_dup 1)
1.1 root 266: (match_dup 2)))]
267: ""
268: "
269: {
270: if (hppa_branch_type != CMP_SI)
271: {
272: emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
273: emit_insn (gen_scond_fp (GT, operands[0]));
274: DONE;
275: }
276: operands[1] = hppa_compare_op0;
277: operands[2] = hppa_compare_op1;
278: }")
279:
280: (define_expand "sle"
1.1.1.2 ! root 281: [(set (match_operand:SI 0 "register_operand" "")
! 282: (le:SI (match_dup 1)
1.1 root 283: (match_dup 2)))]
284: ""
285: "
286: {
287: if (hppa_branch_type != CMP_SI)
288: {
289: emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
290: emit_insn (gen_scond_fp (LE, operands[0]));
291: DONE;
292: }
293: operands[1] = hppa_compare_op0;
294: operands[2] = hppa_compare_op1;
295: }")
296:
297: (define_expand "sge"
1.1.1.2 ! root 298: [(set (match_operand:SI 0 "register_operand" "")
! 299: (ge:SI (match_dup 1)
1.1 root 300: (match_dup 2)))]
301: ""
302: "
303: {
304: if (hppa_branch_type != CMP_SI)
305: {
306: emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
307: emit_insn (gen_scond_fp (GE, operands[0]));
308: DONE;
309: }
310: operands[1] = hppa_compare_op0;
311: operands[2] = hppa_compare_op1;
312: }")
313:
314: (define_expand "sltu"
1.1.1.2 ! root 315: [(set (match_operand:SI 0 "register_operand" "")
! 316: (ltu:SI (match_dup 1)
1.1 root 317: (match_dup 2)))]
318: ""
319: "
320: {
321: if (hppa_branch_type != CMP_SI)
322: FAIL;
323: operands[1] = hppa_compare_op0;
324: operands[2] = hppa_compare_op1;
325: }")
326:
327: (define_expand "sgtu"
1.1.1.2 ! root 328: [(set (match_operand:SI 0 "register_operand" "")
! 329: (gtu:SI (match_dup 1)
1.1 root 330: (match_dup 2)))]
331: ""
332: "
333: {
334: if (hppa_branch_type != CMP_SI)
335: FAIL;
336: operands[1] = hppa_compare_op0;
337: operands[2] = hppa_compare_op1;
338: }")
339:
340: (define_expand "sleu"
1.1.1.2 ! root 341: [(set (match_operand:SI 0 "register_operand" "")
! 342: (leu:SI (match_dup 1)
1.1 root 343: (match_dup 2)))]
344: ""
345: "
346: {
347: if (hppa_branch_type != CMP_SI)
348: FAIL;
349: operands[1] = hppa_compare_op0;
350: operands[2] = hppa_compare_op1;
351: }")
352:
353: (define_expand "sgeu"
1.1.1.2 ! root 354: [(set (match_operand:SI 0 "register_operand" "")
! 355: (geu:SI (match_dup 1)
1.1 root 356: (match_dup 2)))]
357: ""
358: "
359: {
360: if (hppa_branch_type != CMP_SI)
361: FAIL;
362: operands[1] = hppa_compare_op0;
363: operands[2] = hppa_compare_op1;
364: }")
365:
366: ;; Instruction canonicalization puts immediate operands second, which
367: ;; is the reverse of what we want.
368:
369: (define_insn ""
370: [(set (match_operand:SI 0 "register_operand" "=r,r")
1.1.1.2 ! root 371: (match_operator:SI 3 "comparison_operator"
1.1 root 372: [(match_operand:SI 1 "register_operand" "r,r")
373: (match_operand:SI 2 "arith11_operand" "r,I")]))]
374: ""
375: "*
376: {
377: if (which_alternative == 0)
378: return \"comclr,%N3 %1,%2,%0\;ldi 1,%0\";
379: else
380: {
381: if (!(GET_CODE (operands[3]) == EQ || GET_CODE (operands[3]) == NE))
382: PUT_CODE (operands[3], reverse_relop (GET_CODE (operands[3])));
1.1.1.2 ! root 383: return \"comiclr,%N3 %2,%1,%0\;ldi 1,%0\";
1.1 root 384: }
385: }"
1.1.1.2 ! root 386: [(set_attr "type" "binary,binary")
! 387: (set_attr "length" "2,2")])
1.1 root 388:
389: ;; Conditionals
390:
391: (define_expand "beq"
392: [(set (pc)
393: (if_then_else (eq (match_dup 1) (match_dup 2))
394: (label_ref (match_operand 0 "" ""))
395: (pc)))]
396: ""
397: "
398: {
399: if (hppa_branch_type != CMP_SI)
400: {
401: emit_insn (gen_cmp_fp (EQ, hppa_compare_op0, hppa_compare_op1));
402: emit_bcond_fp (NE, operands[0]);
403: DONE;
404: }
405: /* set up operands from compare. */
406: operands[1] = hppa_compare_op0;
407: operands[2] = hppa_compare_op1;
408: /* fall through and generate default code */
409: }")
410:
411: (define_expand "bne"
412: [(set (pc)
413: (if_then_else (ne (match_dup 1) (match_dup 2))
414: (label_ref (match_operand 0 "" ""))
415: (pc)))]
416: ""
417: "
418: {
419: if (hppa_branch_type != CMP_SI)
420: {
421: emit_insn (gen_cmp_fp (NE, hppa_compare_op0, hppa_compare_op1));
422: emit_bcond_fp (NE, operands[0]);
423: DONE;
424: }
425: operands[1] = hppa_compare_op0;
426: operands[2] = hppa_compare_op1;
427: }")
428:
429: (define_expand "bgt"
430: [(set (pc)
431: (if_then_else (gt (match_dup 1) (match_dup 2))
432: (label_ref (match_operand 0 "" ""))
433: (pc)))]
434: ""
435: "
436: {
437: if (hppa_branch_type != CMP_SI)
438: {
439: emit_insn (gen_cmp_fp (GT, hppa_compare_op0, hppa_compare_op1));
440: emit_bcond_fp (NE, operands[0]);
441: DONE;
442: }
443: operands[1] = hppa_compare_op0;
444: operands[2] = hppa_compare_op1;
445: }")
446:
447: (define_expand "blt"
448: [(set (pc)
449: (if_then_else (lt (match_dup 1) (match_dup 2))
450: (label_ref (match_operand 0 "" ""))
451: (pc)))]
452: ""
453: "
454: {
455: if (hppa_branch_type != CMP_SI)
456: {
457: emit_insn (gen_cmp_fp (LT, hppa_compare_op0, hppa_compare_op1));
458: emit_bcond_fp (NE, operands[0]);
459: DONE;
460: }
461: operands[1] = hppa_compare_op0;
462: operands[2] = hppa_compare_op1;
463: }")
464:
465: (define_expand "bge"
466: [(set (pc)
467: (if_then_else (ge (match_dup 1) (match_dup 2))
468: (label_ref (match_operand 0 "" ""))
469: (pc)))]
470: ""
471: "
472: {
473: if (hppa_branch_type != CMP_SI)
474: {
475: emit_insn (gen_cmp_fp (GE, hppa_compare_op0, hppa_compare_op1));
476: emit_bcond_fp (NE, operands[0]);
477: DONE;
478: }
479: operands[1] = hppa_compare_op0;
480: operands[2] = hppa_compare_op1;
481: }")
482:
483: (define_expand "ble"
484: [(set (pc)
485: (if_then_else (le (match_dup 1) (match_dup 2))
486: (label_ref (match_operand 0 "" ""))
487: (pc)))]
488: ""
489: "
490: {
491: if (hppa_branch_type != CMP_SI)
492: {
493: emit_insn (gen_cmp_fp (LE, hppa_compare_op0, hppa_compare_op1));
494: emit_bcond_fp (NE, operands[0]);
495: DONE;
496: }
497: operands[1] = hppa_compare_op0;
498: operands[2] = hppa_compare_op1;
499: }")
500:
501: (define_expand "bgtu"
502: [(set (pc)
503: (if_then_else (gtu (match_dup 1) (match_dup 2))
504: (label_ref (match_operand 0 "" ""))
505: (pc)))]
506: ""
507: "
508: {
509: if (hppa_branch_type != CMP_SI)
510: FAIL;
511: operands[1] = hppa_compare_op0;
512: operands[2] = hppa_compare_op1;
513: }")
514:
515: (define_expand "bltu"
516: [(set (pc)
517: (if_then_else (ltu (match_dup 1) (match_dup 2))
518: (label_ref (match_operand 0 "" ""))
519: (pc)))]
520: ""
521: "
522: {
523: if (hppa_branch_type != CMP_SI)
524: FAIL;
525: operands[1] = hppa_compare_op0;
526: operands[2] = hppa_compare_op1;
527: }")
528:
529: (define_expand "bgeu"
530: [(set (pc)
531: (if_then_else (geu (match_dup 1) (match_dup 2))
532: (label_ref (match_operand 0 "" ""))
533: (pc)))]
534: ""
535: "
536: {
537: if (hppa_branch_type != CMP_SI)
538: FAIL;
539: operands[1] = hppa_compare_op0;
540: operands[2] = hppa_compare_op1;
541: }")
542:
543: (define_expand "bleu"
544: [(set (pc)
545: (if_then_else (leu (match_dup 1) (match_dup 2))
546: (label_ref (match_operand 0 "" ""))
547: (pc)))]
548: ""
549: "
550: {
551: if (hppa_branch_type != CMP_SI)
552: FAIL;
553: operands[1] = hppa_compare_op0;
554: operands[2] = hppa_compare_op1;
555: }")
556:
557: ;; Match the branch patterns.
558:
559: (define_insn ""
560: [(set (pc)
561: (if_then_else
562: (match_operator 3 "comparison_operator"
563: [(match_operand:SI 1 "register_operand" "r,r")
564: (match_operand:SI 2 "arith5_operand" "r,L")])
565: (label_ref (match_operand 0 "" ""))
566: (pc)))]
567: ""
568: "*
569: {
570: if (which_alternative == 0)
571: return (get_attr_length (insn) == 1
572: ? \"comb,%C3 %1,%2,%0%#\" : \"comclr,%N3 %1,%2,0\;bl %0,0%#\");
573: {
574: enum rtx_code comp_code = GET_CODE (operands[3]);
575: if (!(comp_code == EQ || comp_code == NE))
576: PUT_CODE (operands[3], reverse_relop (comp_code));
577: if (get_attr_length (insn) == 1)
1.1.1.2 ! root 578: return \"comib,%C3 %2,%1,%0%#\";
1.1 root 579: else
1.1.1.2 ! root 580: return \"comiclr,%N3 %2,%1,0\;bl %0,0%#\";
1.1 root 581: }
582: }"
583: [(set_attr "type" "cbranch")
584: (set (attr "length") (if_then_else (lt (abs (minus (match_dup 0)
585: (plus (pc) (const_int 2))))
586: (const_int 1023))
587: (const_int 1)
588: (const_int 2)))])
589:
590: ;; Match the negated branch.
591:
592: (define_insn ""
593: [(set (pc)
594: (if_then_else
595: (match_operator 3 "comparison_operator"
596: [(match_operand:SI 1 "register_operand" "r,r")
597: (match_operand:SI 2 "arith5_operand" "r,L")])
598: (pc)
599: (label_ref (match_operand 0 "" ""))))]
600: ""
601: "*
602: {
603: if (which_alternative == 0)
604: return (get_attr_length (insn) == 1
605: ? \"comb,%N3 %1,%2,%0%#\" : \"comclr,%C3 %1,%2,0\;bl %0,0%#\");
606: {
607: enum rtx_code comp_code = GET_CODE (operands[3]);
608: if (!(comp_code == EQ || comp_code == NE))
609: PUT_CODE (operands[3], reverse_relop (comp_code));
610: if (get_attr_length (insn) == 1)
1.1.1.2 ! root 611: return \"comib,%N3 %2,%1,%0%#\";
1.1 root 612: else
1.1.1.2 ! root 613: return \"comiclr,%C3 %2,%1,0%#\;bl %0,0%#\";
1.1 root 614: }
615: }"
616: [(set_attr "type" "cbranch")
617: (set (attr "length") (if_then_else (lt (abs (minus (match_dup 0)
618: (plus (pc) (const_int 2))))
619: (const_int 1023))
620: (const_int 1)
621: (const_int 2)))])
622:
623: ;; Floating point branches
624:
625: (define_insn ""
626: [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
627: (label_ref (match_operand 0 "" ""))
628: (pc)))]
629: ""
1.1.1.2 ! root 630: "*
! 631: {
! 632: if (INSN_ANNULLED_BRANCH_P (insn))
! 633: return \"ftest\;bl,n %0,0\";
! 634: else
! 635: return \"ftest\;bl%* %0,0\";
! 636: }"
! 637: [(set_attr "type" "fbranch")
1.1 root 638: (set_attr "length" "2")])
639:
640: (define_insn ""
641: [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
642: (pc)
643: (label_ref (match_operand 0 "" ""))))]
644: ""
1.1.1.2 ! root 645: "*
! 646: {
! 647: if (INSN_ANNULLED_BRANCH_P (insn))
! 648: return \"ftest\;add,tr 0,0,0\;bl,n %0,0\";
! 649: else
! 650: return \"ftest\;add,tr 0,0,0\;bl%* %0,0\";
! 651: }"
! 652: [(set_attr "type" "fbranch")
1.1 root 653: (set_attr "length" "3")])
654:
655: ;; Move instructions
656:
657: (define_expand "movsi"
658: [(set (match_operand:SI 0 "general_operand" "")
659: (match_operand:SI 1 "general_operand" ""))]
660: ""
661: "
662: {
1.1.1.2 ! root 663: if (emit_move_sequence (operands, SImode, 0))
! 664: DONE;
! 665: }")
! 666:
! 667: ;; Reloading an SImode or DImode value requires a scratch register if
! 668: ;; going in to or out of float point registers.
! 669:
! 670: (define_expand "reload_insi"
! 671: [(set (match_operand:SI 0 "register_operand" "=z")
! 672: (match_operand:SI 1 "general_operand" ""))
! 673: (clobber (match_operand:SI 2 "register_operand" "=&r"))]
! 674: ""
! 675: "
! 676: {
! 677: if (emit_move_sequence (operands, SImode, operands[2]))
1.1 root 678: DONE;
1.1.1.2 ! root 679:
! 680: /* We don't want the clobber emitted, so handle this ourselves. */
! 681: emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
! 682: DONE;
! 683: }")
! 684:
! 685: (define_expand "reload_outsi"
! 686: [(set (match_operand:SI 0 "general_operand" "")
! 687: (match_operand:SI 1 "register_operand""z"))
! 688: (clobber (match_operand:SI 2 "register_operand" "=&r"))]
! 689: ""
! 690: "
! 691: {
! 692: if (emit_move_sequence (operands, SImode, operands[2]))
! 693: DONE;
! 694:
! 695: /* We don't want the clobber emitted, so handle this ourselves. */
! 696: emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
! 697: DONE;
1.1 root 698: }")
699:
700: ;; Moves to and from the shift register.
701:
702: (define_insn ""
703: [(set (reg:SI 112)
704: (match_operand:SI 0 "register_operand" "r"))]
705: ""
706: "mtsar %0"
707: [(set_attr "type" "move")])
708:
709: (define_insn ""
710: [(set (match_operand:SI 0 "register_operand" "=r")
711: (reg:SI 112))]
712: ""
713: "mfctl 11,%0"
714: [(set_attr "type" "move")])
715:
1.1.1.2 ! root 716: ;;; Experimental
! 717:
! 718: (define_insn ""
! 719: [(set (match_operand:SI 0 "fp_reg_operand" "=fx")
! 720: (match_operand:SI 1 "short_memory_operand" "T"))]
! 721: ""
! 722: "fldws%F1 %1,%0"
! 723: [(set_attr "type" "fpload")
! 724: (set_attr "length" "1")])
! 725:
! 726: (define_insn ""
! 727: [(set (match_operand:SI 0 "short_memory_operand" "=T")
! 728: (match_operand:SI 1 "fp_reg_operand" "fx"))]
! 729: ""
! 730: "fstws%F0 %1,%0"
! 731: [(set_attr "type" "fpstore")
! 732: (set_attr "length" "1")])
! 733:
! 734: ;;; pic symbol refrences
! 735:
! 736: (define_insn ""
! 737: [(set (match_operand:SI 0 "register_operand" "=r")
! 738: (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "r")
! 739: (match_operand:SI 2 "symbolic_operand" ""))))]
! 740: "flag_pic && operands[1] == pic_offset_table_rtx"
! 741: "ldw T'%2(%1),%0"
! 742: [(set_attr "type" "load")
! 743: (set_attr "length" "1")])
! 744:
1.1 root 745: (define_insn ""
746: [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand"
1.1.1.2 ! root 747: "=r,r,Q,!r,!fx,!fx")
! 748: (match_operand:SI 1 "move_operand" "rM,Q,rM,!fxy,!r,!fx"))]
1.1 root 749: ""
750: "@
751: copy %r1,%0
752: ldw%M1 %1,%0
753: stw%M0 %r1,%0
754: fstws %1,-16(30)\;ldw -16(30),%0
755: stw %1,-16(30)\;fldws -16(30),%0
756: fcpy,sgl %1,%0"
757: [(set_attr "type" "move,load,store,move,move,fpalu")
758: (set_attr "length" "1,1,1,2,2,1")])
759:
760: ;; For pic
761: (define_insn ""
762: [(set (match_operand:SI 0 "register_operand" "=r")
763: (match_operand:SI 1 "pic_operand" "i"))
764: (clobber (match_scratch:SI 2 "=a"))]
765: ""
766: "*
767: {
768: rtx label_rtx = gen_label_rtx ();
769: rtx xoperands[3];
770: extern FILE *asm_out_file;
771:
772: xoperands[0] = operands[0];
773: xoperands[1] = operands[1];
774: xoperands[2] = label_rtx;
775: output_asm_insn (\"bl .+8,%0\;addil L'%1-%2,%0\", xoperands);
776: ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\", CODE_LABEL_NUMBER (label_rtx));
1.1.1.2 ! root 777: output_asm_insn (\"ldo R'%1-%2(1),%0\", xoperands);
1.1 root 778: return \"\";
779: }
780: "
781: [(set_attr "type" "multi")
782: (set_attr "length" "3")])
783:
784: (define_insn ""
785: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 ! root 786: (match_operand:SI 1 "const_int_operand" ""))]
! 787: "INT_14_BITS (operands[1]) || (INTVAL (operands[1]) & 0x7ff) == 0"
1.1 root 788: "*
789: {
790: if (INT_14_BITS (operands[1]))
791: return \"ldo %1(0),%0\";
792: else
793: return \"ldil L'%1,%0\";
794: }"
795: [(set_attr "type" "move")
796: (set_attr "length" "1")])
797:
798: (define_insn ""
1.1.1.2 ! root 799: [(set (match_operand:SI 0 "register_operand" "=r")
! 800: (match_operand:SI 1 "depi_cint_operand" ""))]
! 801: ""
! 802: "*
! 803: {
! 804: rtx xoperands[4];
! 805: xoperands[0] = operands[0];
! 806: compute_xdepi_operands_from_integer (INTVAL (operands[1]), xoperands);
! 807: output_asm_insn (\"zdepi %1,%2,%3,%0\", xoperands);
! 808: return \"\";
! 809: }"
! 810: [(set_attr "type" "move")
! 811: (set_attr "length" "1")])
! 812:
! 813: (define_insn ""
! 814: [(set (match_operand:SI 0 "register_operand" "=a,&?*r")
1.1 root 815: (plus:SI (match_operand:SI 1 "register_operand" "r,r")
816: (high:SI (match_operand 2 "" ""))))]
1.1.1.2 ! root 817: "!TARGET_KERNEL"
1.1 root 818: "@
819: addil L'%G2,%1
820: ldil L'%G2,%0\;add %0,%1,%0"
1.1.1.2 ! root 821: [(set_attr "type" "binary,binary")
1.1 root 822: (set_attr "length" "1,2")])
823:
1.1.1.2 ! root 824: (define_insn ""
! 825: [(set (match_operand:SI 0 "register_operand" "=a")
! 826: (plus:SI (match_operand:SI 1 "register_operand" "r")
! 827: (high:SI (match_operand 2 "" ""))))]
! 828: "TARGET_KERNEL"
! 829: "@
! 830: addil L'%G2,%1"
! 831: [(set_attr "type" "binary")
! 832: (set_attr "length" "1")])
! 833:
1.1 root 834: (define_split
835: [(set (match_operand:SI 0 "register_operand" "")
836: (plus:SI (match_operand:SI 1 "register_operand" "")
1.1.1.2 ! root 837: (high:SI (match_operand 2 "" ""))))
! 838: (clobber (match_scratch:SI 3 ""))]
1.1 root 839: "reload_completed && REGNO (operands[0]) != 1"
1.1.1.2 ! root 840: [(set (match_dup 3) (high:SI (match_dup 2)))
! 841: (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
1.1 root 842: "")
843:
844: (define_insn ""
845: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 ! root 846: (high:SI (match_operand:SI 1 "function_label_operand" "")))]
! 847: "TARGET_SHARED_LIBS"
! 848: "ldil LP'%G1,%0"
! 849: [(set_attr "type" "move")
! 850: (set_attr "length" "1")])
! 851:
! 852: (define_insn ""
! 853: [(set (match_operand:SI 0 "register_operand" "=r")
1.1 root 854: (high:SI (match_operand 1 "" "")))]
855: "check_pic (1)"
856: "ldil L'%G1,%0"
857: [(set_attr "type" "move")
858: (set_attr "length" "1")])
859:
860: (define_insn ""
861: [(set (match_operand:HI 0 "register_operand" "=r")
862: (high:HI (match_operand 1 "" "")))]
863: "check_pic (1)"
864: "ldil L'%G1,%0"
865: [(set_attr "type" "move")
866: (set_attr "length" "1")])
867:
868: (define_insn ""
869: [(set (match_operand:SI 0 "register_operand" "=r")
870: (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
1.1.1.2 ! root 871: (match_operand:SI 2 "function_label_operand" "")))
! 872: (clobber (match_operand:SI 3 "register_operand" "=r"))]
! 873: "TARGET_SHARED_LIBS"
! 874: "ldo RP'%G2(%1),%0\;extru,= %0,31,1,%3\;ldw -4(%%r27),%3\;add %0,%3,%0"
! 875: [(set_attr "type" "multi")
! 876: (set_attr "length" "4")])
! 877:
! 878: (define_insn ""
! 879: [(set (match_operand:SI 0 "register_operand" "=r")
! 880: (lo_sum:SI (match_operand:SI 1 "register_operand" "r")
! 881: (match_operand:SI 2 "immediate_operand" "i")))]
1.1 root 882: ""
883: "ldo R'%G2(%1),%0"
884: ;; Need to set length for this arith insn because operand2
885: ;; is not an "arith_operand".
886: [(set_attr "length" "1")])
887:
888: (define_expand "movhi"
889: [(set (match_operand:HI 0 "general_operand" "")
890: (match_operand:HI 1 "general_operand" ""))]
891: ""
892: "
893: {
1.1.1.2 ! root 894: if (emit_move_sequence (operands, HImode, 0))
1.1 root 895: DONE;
896: }")
897:
898: (define_insn ""
1.1.1.2 ! root 899: [(set (match_operand:HI 0 "reg_or_nonsymb_mem_operand" "=r,r,Q,!r,!*fx,!*fx")
! 900: (match_operand:HI 1 "move_operand" "rM,Q,rM,*fx,r,!*fx"))]
1.1 root 901: ""
902: "@
903: copy %r1,%0
904: ldh%M1 %1,%0
1.1.1.2 ! root 905: sth%M0 %r1,%0
! 906: fstws %1,-16(30)\;ldw -16(30),%0
! 907: stw %1,-16(30)\;fldws -16(30),%0
! 908: fcpy,sgl %1,%0"
! 909: [(set_attr "type" "move,load,store,move,move,fpalu")
! 910: (set_attr "length" "1,1,1,2,2,1")])
1.1 root 911:
912: (define_insn ""
913: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 ! root 914: (match_operand:HI 1 "const_int_operand" ""))]
! 915: "INT_14_BITS (operands[1]) || (INTVAL (operands[1]) & 0x7ff) == 0"
1.1 root 916: "*
917: {
918: if (INT_14_BITS (operands[1]))
919: return \"ldo %1(0),%0\";
920: else
921: return \"ldil L'%1,%0\";
922: }"
923: [(set_attr "type" "move")
924: (set_attr "length" "1")])
925:
926: (define_insn ""
927: [(set (match_operand:HI 0 "register_operand" "=r")
1.1.1.2 ! root 928: (match_operand:HI 1 "depi_cint_operand" ""))]
! 929: ""
! 930: "*
! 931: {
! 932: rtx xoperands[4];
! 933: xoperands[0] = operands[0];
! 934: compute_xdepi_operands_from_integer (INTVAL (operands[1]), xoperands);
! 935: output_asm_insn (\"zdepi %1,%2,%3,%0\", xoperands);
! 936: return \"\";
! 937: }"
! 938: [(set_attr "type" "move")
! 939: (set_attr "length" "1")])
! 940:
! 941: (define_insn ""
! 942: [(set (match_operand:HI 0 "register_operand" "=r")
1.1 root 943: (lo_sum:HI (match_operand:HI 1 "register_operand" "r")
1.1.1.2 ! root 944: (match_operand 2 "immediate_operand" "i")))]
1.1 root 945: ""
946: "ldo R'%G2(%1),%0"
947: [(set_attr "length" "1")])
948:
949: (define_expand "movqi"
950: [(set (match_operand:QI 0 "general_operand" "")
951: (match_operand:QI 1 "general_operand" ""))]
952: ""
953: "
954: {
1.1.1.2 ! root 955: if (emit_move_sequence (operands, QImode, 0))
1.1 root 956: DONE;
957: }")
958:
959: (define_insn ""
1.1.1.2 ! root 960: [(set (match_operand:QI 0 "reg_or_nonsymb_mem_operand" "=r,r,Q,!r,!*fx,!*fx")
! 961: (match_operand:QI 1 "move_operand" "rM,Q,rM,*fx,r,*fx"))]
1.1 root 962: ""
963: "@
964: copy %r1,%0
965: ldb%M1 %1,%0
1.1.1.2 ! root 966: stb%M0 %r1,%0
! 967: fstws %1,-16(30)\;ldw -16(30),%0
! 968: stw %1,-16(30)\;fldws -16(30),%0
! 969: fcpy,sgl %1,%0"
! 970: [(set_attr "type" "move,load,store,move,move,fpalu")
! 971: (set_attr "length" "1,1,1,2,2,1")])
1.1 root 972:
973: (define_insn ""
974: [(set (match_operand:QI 0 "register_operand" "=r")
975: (match_operand:QI 1 "immediate_operand" "J"))]
976: ""
977: "ldo %1(0),%0"
978: [(set_attr "type" "move")
979: (set_attr "length" "1")])
980:
981: (define_insn ""
982: [(set (match_operand:QI 0 "register_operand" "=r")
983: (subreg:QI (lo_sum:SI (match_operand:QI 1 "register_operand" "r")
1.1.1.2 ! root 984: (match_operand 2 "immediate_operand" "i")) 0))]
1.1 root 985: ""
986: "ldo R'%G2(%1),%0"
987: [(set_attr "length" "1")])
988:
1.1.1.2 ! root 989: ;; Sneaky ways of using index modes
! 990: ;; We don't use unscaled modes since they can't be used unless we can tell
! 991: ;; which of the registers is the base and which is the index, due to PA's
! 992: ;; idea of segment selection using the top bits of the base register.
! 993:
! 994: (define_insn ""
! 995: [(set (match_operand:SI 0 "register_operand" "=r")
! 996: (mem:SI (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
! 997: (const_int 4))
! 998: (match_operand:SI 2 "register_operand" "r"))))]
! 999: ""
! 1000: "ldwx,s %1(0,%2),%0"
! 1001: [(set_attr "type" "move")
! 1002: (set_attr "length" "1")])
! 1003:
! 1004: ; this will never match
! 1005: ;(define_insn ""
! 1006: ; [(set (match_operand:SI 0 "register_operand" "=r")
! 1007: ; (mem:SI (match_operand:SI 1 "register_operand" "+r")))
! 1008: ; (set (match_dup 1)
! 1009: ; (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
! 1010: ; (const_int 4))
! 1011: ; (match_dup 1)))]
! 1012: ; ""
! 1013: ; "ldwx,sm %2(0,%1),%0"
! 1014: ; [(set_attr "type" "move")
! 1015: ; (set_attr "length" "1")])
! 1016:
! 1017: (define_insn ""
! 1018: [(set (match_operand:HI 0 "register_operand" "=r")
! 1019: (mem:HI (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
! 1020: (const_int 2))
! 1021: (match_operand:SI 1 "register_operand" "r"))))]
! 1022: ""
! 1023: "ldhx,s %2(0,%1),%0"
! 1024: [(set_attr "type" "move")
! 1025: (set_attr "length" "1")])
! 1026:
! 1027: ; this will never match
! 1028: ;(define_insn ""
! 1029: ; [(set (match_operand:HI 0 "register_operand" "=r")
! 1030: ; (mem:HI (match_operand:SI 1 "register_operand" "+r")))
! 1031: ; (set (match_dup 1)
! 1032: ; (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
! 1033: ; (const_int 2))
! 1034: ; (match_dup 1)))]
! 1035: ; ""
! 1036: ; "ldhx,sm %2(0,%1),%0"
! 1037: ; [(set_attr "type" "move")
! 1038: ; (set_attr "length" "1")])
! 1039:
1.1 root 1040: ;; The definition of this insn does not really explain what it does,
1041: ;; but it should suffice
1042: ;; that anything generated as this insn will be recognized as one
1043: ;; and that it will not successfully combine with anything.
1044: (define_expand "movstrsi"
1045: [(parallel [(set (mem:BLK (match_operand:BLK 0 "general_operand" ""))
1046: (mem:BLK (match_operand:BLK 1 "general_operand" "")))
1047: (clobber (match_dup 0))
1048: (clobber (match_dup 1))
1.1.1.2 ! root 1049: (clobber (match_dup 4))
! 1050: (clobber (match_dup 5))
1.1 root 1051: (use (match_operand:SI 2 "arith_operand" ""))
1052: (use (match_operand:SI 3 "const_int_operand" ""))])]
1053: ""
1054: "
1055: {
1.1.1.2 ! root 1056: /* If the blocks are not at least word-aligned and rather big (>16 items),
1.1 root 1057: or the size is indeterminate, don't inline the copy code. A
1058: procedure call is better since it can check the alignment at
1059: runtime and make the optimal decisions. */
1.1.1.2 ! root 1060: if (INTVAL (operands[3]) < 4
1.1 root 1061: && (GET_CODE (operands[2]) != CONST_INT
1062: || (INTVAL (operands[2]) / INTVAL (operands[3]) > 16)))
1063: FAIL;
1064:
1065: operands[0] = copy_to_mode_reg (SImode, XEXP (operands[0], 0));
1066: operands[1] = copy_to_mode_reg (SImode, XEXP (operands[1], 0));
1.1.1.2 ! root 1067: operands[4] = gen_reg_rtx (SImode);
! 1068: operands[5] = gen_reg_rtx (SImode);
1.1 root 1069: }")
1070:
1071: ;; The operand constraints are written like this to support both compile-time
1072: ;; and run-time determined byte count. If the count is run-time determined,
1073: ;; the register with the byte count is clobbered by the copying code, and
1074: ;; therefore it is forced to operand 2. If the count is compile-time
1075: ;; determined, we need two scratch registers for the unrolled code.
1076: (define_insn ""
1.1.1.2 ! root 1077: [(set (mem:BLK (match_operand:SI 0 "register_operand" "+r,r"))
! 1078: (mem:BLK (match_operand:SI 1 "register_operand" "+r,r")))
1.1 root 1079: (clobber (match_dup 0))
1080: (clobber (match_dup 1))
1.1.1.2 ! root 1081: (clobber (match_operand:SI 2 "register_operand" "=r,r")) ;loop cnt/tmp
! 1082: (clobber (match_operand:SI 3 "register_operand" "=&r,&r")) ;item tmp
1.1 root 1083: (use (match_operand:SI 4 "arith_operand" "J,2")) ;byte count
1084: (use (match_operand:SI 5 "const_int_operand" "n,n"))] ;alignment
1085: ""
1086: "* return output_block_move (operands, !which_alternative);"
1.1.1.2 ! root 1087: [(set_attr "type" "multi,multi")])
1.1 root 1088:
1089: ;; Floating point move insns
1090:
1091: ;; This pattern forces (set (reg:DF ...) (const_double ...))
1092: ;; to be reloaded by putting the constant into memory.
1093: ;; It must come before the more general movdf pattern.
1094: (define_insn ""
1095: [(set (match_operand:DF 0 "general_operand" "=?r,r,fx")
1096: (match_operand:DF 1 "" "?E,G,m"))]
1097: "GET_CODE (operands[1]) == CONST_DOUBLE"
1098: "*
1099: {
1100: switch (which_alternative)
1101: {
1102: case 0:
1103: return output_move_double (operands);
1104: case 1:
1105: return \"copy 0,%0\;copy 0,%R0\";
1106: case 2:
1107: return output_fp_move_double (operands);
1108: }
1109: }"
1110: [(set_attr "type" "load,move,fpload")
1111: (set_attr "length" "3,2,3")])
1112:
1113: (define_expand "movdf"
1114: [(set (match_operand:DF 0 "general_operand" "")
1115: (match_operand:DF 1 "general_operand" ""))]
1116: ""
1117: "
1118: {
1.1.1.2 ! root 1119: if (emit_move_sequence (operands, DFmode, 0))
1.1 root 1120: DONE;
1121: }")
1122:
1123: (define_insn ""
1124: [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
1.1.1.2 ! root 1125: "=fx,*r,Q,?Q,fx,*&r,?fx,?r")
1.1 root 1126: (match_operand:DF 1 "reg_or_nonsymb_mem_operand"
1.1.1.2 ! root 1127: "fx,*r,fx,*r,Q,Q,*r,fx"))]
! 1128: "register_operand (operands[0], DFmode)
! 1129: || register_operand (operands[1], DFmode)"
1.1 root 1130: "*
1131: {
1132: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1133: return output_fp_move_double (operands);
1134: return output_move_double (operands);
1135: }"
1136: [(set_attr "type" "fpalu,move,fpstore,store,fpload,load,multi,multi")
1137: (set_attr "length" "1,2,1,2,1,2,3,3")])
1138:
1139: (define_expand "movdi"
1140: [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
1141: (match_operand:DI 1 "general_operand" ""))]
1142: ""
1143: "
1144: {
1.1.1.2 ! root 1145: if (emit_move_sequence (operands, DImode, 0))
1.1 root 1146: DONE;
1147: }")
1148:
1.1.1.2 ! root 1149: (define_expand "reload_indi"
! 1150: [(set (match_operand:DI 0 "register_operand" "=z")
! 1151: (match_operand:DI 1 "general_operand" ""))
! 1152: (clobber (match_operand:SI 2 "register_operand" "=&r"))]
! 1153: ""
! 1154: "
! 1155: {
! 1156: if (emit_move_sequence (operands, DImode, operands[2]))
! 1157: DONE;
! 1158:
! 1159: /* We don't want the clobber emitted, so handle this ourselves. */
! 1160: emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
! 1161: DONE;
! 1162: }")
! 1163:
! 1164: (define_expand "reload_outdi"
! 1165: [(set (match_operand:DI 0 "general_operand" "")
! 1166: (match_operand:DI 1 "register_operand" "z"))
! 1167: (clobber (match_operand:SI 2 "register_operand" "=&r"))]
! 1168: ""
! 1169: "
! 1170: {
! 1171: if (emit_move_sequence (operands, DImode, operands[2]))
! 1172: DONE;
! 1173:
! 1174: /* We don't want the clobber emitted, so handle this ourselves. */
! 1175: emit_insn (gen_rtx (SET, VOIDmode, operands[0], operands[1]));
! 1176: DONE;
! 1177: }")
! 1178:
1.1 root 1179: (define_insn ""
1180: [(set (match_operand:DI 0 "register_operand" "=r")
1181: (high:DI (match_operand 1 "" "")))]
1182: "check_pic (1)"
1183: "*
1184: {
1185: rtx op0 = operands[0];
1186: rtx op1 = operands[1];
1187:
1188: if (GET_CODE (op1) == CONST_INT)
1189: {
1190: operands[0] = operand_subword (op0, 1, 0, DImode);
1191: output_asm_insn (\"ldil L'%1,%0\", operands);
1192:
1193: operands[0] = operand_subword (op0, 0, 0, DImode);
1194: if (INTVAL (op1) < 0)
1195: output_asm_insn (\"ldo -1(0),%0\", operands);
1196: else
1197: output_asm_insn (\"ldo 0(0),%0\", operands);
1.1.1.2 ! root 1198: return \"\";
1.1 root 1199: }
1200: else if (GET_CODE (op1) == CONST_DOUBLE)
1201: {
1202: operands[0] = operand_subword (op0, 1, 0, DImode);
1203: operands[1] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (op1));
1204: output_asm_insn (\"ldil L'%1,%0\", operands);
1205:
1206: operands[0] = operand_subword (op0, 0, 0, DImode);
1207: operands[1] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_HIGH (op1));
1208: output_asm_insn (singlemove_string (operands), operands);
1.1.1.2 ! root 1209: return \"\";
1.1 root 1210: }
1211: else
1212: abort ();
1213: }"
1214: [(set_attr "type" "move")
1215: (set_attr "length" "2")])
1216:
1.1.1.2 ! root 1217: ;;; Experimental
! 1218:
! 1219: (define_insn ""
! 1220: [(set (match_operand:DI 0 "fp_reg_operand" "=fx")
! 1221: (match_operand:DI 1 "short_memory_operand" "T"))]
! 1222: ""
! 1223: "fldds%F1 %1,%0"
! 1224: [(set_attr "type" "fpload")
! 1225: (set_attr "length" "1")])
! 1226:
! 1227: (define_insn ""
! 1228: [(set (match_operand:DI 0 "short_memory_operand" "=T")
! 1229: (match_operand:DI 1 "fp_reg_operand" "fx"))]
! 1230: ""
! 1231: "fstds%F0 %1,%0"
! 1232: [(set_attr "type" "fpstore")
! 1233: (set_attr "length" "1")])
! 1234:
1.1 root 1235: (define_insn ""
1236: [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
1.1.1.2 ! root 1237: "=r,Q,&r,&r,fx,fx,r")
1.1 root 1238: (match_operand:DI 1 "general_operand"
1.1.1.2 ! root 1239: "r,r,Q,i,r,fx,fx"))]
1.1 root 1240: ""
1241: "*
1242: {
1243: if (FP_REG_P (operands[0]) || FP_REG_P (operands[1]))
1244: return output_fp_move_double (operands);
1245: return output_move_double (operands);
1246: }"
1.1.1.2 ! root 1247: [(set_attr "type" "move,store,load,misc,multi,fpalu,multi")
! 1248: (set_attr "length" "2,3,3,3,3,2,3")])
1.1 root 1249:
1250: (define_insn ""
1251: [(set (match_operand:DI 0 "register_operand" "=r,r")
1252: (lo_sum:DI (match_operand:DI 1 "register_operand" "0,r")
1.1.1.2 ! root 1253: (match_operand:DI 2 "immediate_operand" "i,i")))]
1.1 root 1254: ""
1255: "*
1256: {
1257: /* Don't output a 64 bit constant, since we can't trust the assembler to
1258: handle it correctly. */
1259: if (GET_CODE (operands[2]) == CONST_DOUBLE)
1260: operands[2] = gen_rtx (CONST_INT, VOIDmode, CONST_DOUBLE_LOW (operands[2]));
1261: if (which_alternative == 1)
1262: output_asm_insn (\"copy %1,%0\", operands);
1263: return \"ldo R'%G2(%R1),%R0\";
1264: }"
1265: ;; Need to set length for this arith insn because operand2
1266: ;; is not an "arith_operand".
1267: [(set_attr "length" "1,2")])
1268:
1269: (define_expand "movsf"
1270: [(set (match_operand:SF 0 "general_operand" "")
1271: (match_operand:SF 1 "general_operand" ""))]
1272: ""
1273: "
1274: {
1.1.1.2 ! root 1275: if (emit_move_sequence (operands, SFmode, 0))
1.1 root 1276: DONE;
1277: }")
1278:
1279: (define_insn ""
1280: [(set (match_operand:SF 0 "reg_or_nonsymb_mem_operand"
1281: "=fx,r,r,fx,fx,r,Q,Q")
1282: (match_operand:SF 1 "reg_or_nonsymb_mem_operand"
1283: "fx,r,!fx,!r,Q,Q,fx,r"))]
1284: ""
1285: "@
1.1.1.2 ! root 1286: fcpy,sgl %1,%0
1.1 root 1287: copy %1,%0
1288: fstws %1,-16(0,30)\;ldw -16(0,30),%0
1289: stw %r1,-16(0,30)\;fldws -16(0,30),%0
1290: fldws%F1 %1,%0
1291: ldw%M1 %1,%0
1292: fstws%F0 %r1,%0
1293: stw%M0 %r1,%0"
1294: [(set_attr "type" "fpalu,move,multi,multi,fpload,load,fpstore,store")
1295: (set_attr "length" "1,1,2,2,1,1,1,1")])
1296:
1297:
1298: ;;- zero extension instructions
1299:
1300: ;; Note that the one starting from HImode comes before those for QImode
1301: ;; so that a constant operand will match HImode, not QImode.
1302:
1303: (define_expand "zero_extendhisi2"
1304: [(set (match_operand:SI 0 "register_operand" "")
1305: (zero_extend:SI
1306: (match_operand:HI 1 "general_operand" "")))]
1307: ""
1308: "
1309: {
1310: if (GET_CODE (operand1) == MEM
1311: && symbolic_operand (XEXP (operand1, 0), Pmode))
1312: {
1313: rtx temp = copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode,
1314: XEXP (operand1, 0)));
1315: operands[1] = gen_rtx (MEM, HImode,
1316: gen_rtx (LO_SUM, Pmode,
1317: temp, XEXP (operand1, 0)));
1318: }
1319: }")
1320:
1321: (define_insn ""
1322: [(set (match_operand:SI 0 "register_operand" "=r,r")
1323: (zero_extend:SI
1324: (match_operand:HI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
1325: ""
1326: "@
1327: extru %1,31,16,%0
1328: ldh%M1 %1,%0"
1329: [(set_attr "type" "unary,load")])
1330:
1331: (define_expand "zero_extendqihi2"
1332: [(set (match_operand:HI 0 "register_operand" "")
1333: (zero_extend:HI
1334: (match_operand:QI 1 "general_operand" "")))]
1335: ""
1336: "
1337: {
1338: if (GET_CODE (operand1) == MEM
1339: && symbolic_operand (XEXP (operand1, 0), Pmode))
1340: {
1341: rtx temp = copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode,
1342: XEXP (operand1, 0)));
1343: operands[1] = gen_rtx (MEM, QImode,
1344: gen_rtx (LO_SUM, Pmode,
1345: temp, XEXP (operand1, 0)));
1346: }
1347: }")
1348:
1349: (define_insn ""
1350: [(set (match_operand:HI 0 "register_operand" "=r,r")
1351: (zero_extend:HI
1352: (match_operand:QI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
1353: ""
1354: "@
1355: extru %1,31,8,%0
1356: ldb%M1 %1,%0"
1357: [(set_attr "type" "unary,load")
1.1.1.2 ! root 1358: (set_attr "length" "1,1")])
1.1 root 1359:
1360: (define_expand "zero_extendqisi2"
1361: [(set (match_operand:SI 0 "register_operand" "")
1362: (zero_extend:SI
1363: (match_operand:QI 1 "general_operand" "")))]
1364: ""
1365: "
1366: {
1367: if (GET_CODE (operand1) == MEM
1368: && symbolic_operand (XEXP (operand1, 0), Pmode))
1369: {
1370: rtx temp = copy_to_mode_reg (Pmode, gen_rtx (HIGH, Pmode,
1371: XEXP (operand1, 0)));
1372: operand1 = gen_rtx (MEM, QImode,
1373: gen_rtx (LO_SUM, Pmode,
1374: temp, XEXP (operand1, 0)));
1375: emit_insn (gen_rtx (SET, VOIDmode, operand0,
1376: gen_rtx (ZERO_EXTEND, SImode, operand1)));
1377: DONE;
1378: }
1379: }")
1380:
1381: (define_insn ""
1382: [(set (match_operand:SI 0 "register_operand" "=r,r")
1383: (zero_extend:SI
1384: (match_operand:QI 1 "reg_or_nonsymb_mem_operand" "r,Q")))]
1385: ""
1386: "@
1387: extru %1,31,8,%0
1388: ldb%M1 %1,%0"
1389: [(set_attr "type" "unary,load")
1.1.1.2 ! root 1390: (set_attr "length" "1,1")])
1.1 root 1391:
1392: ;;- sign extension instructions
1393: ;; Note that the one starting from HImode comes before those for QImode
1394: ;; so that a constant operand will match HImode, not QImode.
1395:
1396: (define_insn "extendhisi2"
1397: [(set (match_operand:SI 0 "register_operand" "=r")
1398: (sign_extend:SI (match_operand:HI 1 "register_operand" "r")))]
1399: ""
1400: "extrs %1,31,16,%0"
1401: [(set_attr "type" "unary")])
1402:
1403: (define_insn "extendqihi2"
1404: [(set (match_operand:HI 0 "register_operand" "=r")
1405: (sign_extend:HI (match_operand:QI 1 "register_operand" "r")))]
1406: ""
1407: "extrs %1,31,8,%0"
1408: [(set_attr "type" "unary")])
1409:
1410: (define_insn "extendqisi2"
1411: [(set (match_operand:SI 0 "register_operand" "=r")
1412: (sign_extend:SI (match_operand:QI 1 "register_operand" "r")))]
1413: ""
1414: "extrs %1,31,8,%0"
1415: [(set_attr "type" "unary")])
1416:
1417: ;; Conversions between float and double.
1418:
1419: (define_insn "extendsfdf2"
1420: [(set (match_operand:DF 0 "register_operand" "=fx")
1421: (float_extend:DF
1422: (match_operand:SF 1 "register_operand" "fx")))]
1423: ""
1424: "fcnvff,sgl,dbl %1,%0"
1425: [(set_attr "type" "fpalu")])
1426:
1427: (define_insn "truncdfsf2"
1428: [(set (match_operand:SF 0 "register_operand" "=fx")
1429: (float_truncate:SF
1430: (match_operand:DF 1 "register_operand" "fx")))]
1431: ""
1432: "fcnvff,dbl,sgl %1,%0"
1433: [(set_attr "type" "fpalu")])
1434:
1435: ;; Conversion between fixed point and floating point.
1436: ;; Note that among the fix-to-float insns
1437: ;; the ones that start with SImode come first.
1438: ;; That is so that an operand that is a CONST_INT
1439: ;; (and therefore lacks a specific machine mode).
1440: ;; will be recognized as SImode (which is always valid)
1441: ;; rather than as QImode or HImode.
1442:
1443: ;; This pattern forces (set (reg:SF ...) (float:SF (const_int ...)))
1444: ;; to be reloaded by putting the constant into memory.
1445: ;; It must come before the more general floatsisf2 pattern.
1446: (define_insn ""
1447: [(set (match_operand:SF 0 "general_operand" "=fx")
1448: (float:SF (match_operand:SI 1 "const_int_operand" "m")))]
1449: ""
1450: "* return output_floatsisf2 (operands);"
1451: [(set_attr "type" "fpalu")
1452: (set_attr "length" "3")])
1453:
1454: (define_insn "floatsisf2"
1455: [(set (match_operand:SF 0 "general_operand" "=fx")
1.1.1.2 ! root 1456: (float:SF (match_operand:SI 1 "register_operand" "fx")))]
1.1 root 1457: ""
1458: "* return output_floatsisf2 (operands);"
1459: [(set_attr "type" "fpalu")
1460: (set_attr "length" "3")])
1461:
1462: ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
1463: ;; to be reloaded by putting the constant into memory.
1464: ;; It must come before the more general floatsidf2 pattern.
1465: (define_insn ""
1466: [(set (match_operand:DF 0 "general_operand" "=fx")
1467: (float:DF (match_operand:SI 1 "const_int_operand" "m")))]
1468: ""
1469: "* return output_floatsidf2 (operands);"
1470: [(set_attr "type" "fpalu")
1471: (set_attr "length" "3")])
1472:
1473: (define_insn "floatsidf2"
1474: [(set (match_operand:DF 0 "general_operand" "=fx")
1.1.1.2 ! root 1475: (float:DF (match_operand:SI 1 "register_operand" "fx")))]
1.1 root 1476: ""
1477: "* return output_floatsidf2 (operands);"
1478: [(set_attr "type" "fpalu")
1479: (set_attr "length" "3")])
1480:
1481: ;; Convert a float to an actual integer.
1482: ;; Truncation is performed as part of the conversion.
1483:
1484: (define_insn "fix_truncsfsi2"
1485: [(set (match_operand:SI 0 "register_operand" "=r,fx")
1486: (fix:SI (fix:SF (match_operand:SF 1 "register_operand" "fx,fx"))))
1487: (clobber (match_scratch:SI 2 "=&fx,X"))]
1488: ""
1489: "@
1490: fcnvfxt,sgl,sgl %1,%2\;fstws %2,-16(30)\;ldw -16(30),%0
1491: fcnvfxt,sgl,sgl %1,%0"
1492: [(set_attr "type" "fpalu,fpalu")
1493: (set_attr "length" "3,1")])
1494:
1495: (define_insn "fix_truncdfsi2"
1496: [(set (match_operand:SI 0 "register_operand" "=r,fx")
1497: (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "fx,fx"))))
1498: (clobber (match_scratch:SI 2 "=&fx,X"))]
1499: ""
1500: "@
1501: fcnvfxt,dbl,sgl %1,%2\;fstws %2,-16(30)\;ldw -16(30),%0
1502: fcnvfxt,dbl,sgl %1,%0"
1503: [(set_attr "type" "fpalu,fpalu")
1504: (set_attr "length" "3,1")])
1505:
1506:
1507: ;;- arithmetic instructions
1508:
1509: (define_insn "adddi3"
1510: [(set (match_operand:DI 0 "register_operand" "=r")
1511: (plus:DI (match_operand:DI 1 "register_operand" "%r")
1.1.1.2 ! root 1512: (match_operand:DI 2 "arith11_operand" "rI")))]
1.1 root 1513: ""
1.1.1.2 ! root 1514: "*
! 1515: {
! 1516: if (GET_CODE (operands[2]) == CONST_INT)
! 1517: {
! 1518: if (INTVAL (operands[2]) >= 0)
! 1519: return \"addi %2,%R1,%R0\;addc %1,0,%0\";
! 1520: else
! 1521: return \"addi %2,%R1,%R0\;subb %1,0,%0\";
! 1522: }
! 1523: else
! 1524: return \"add %R2,%R1,%R0\;addc %2,%1,%0\";
! 1525: }"
! 1526: [(set_attr "length" "2")])
1.1 root 1527:
1528: (define_insn "addsi3"
1529: [(set (match_operand:SI 0 "register_operand" "=r,r")
1530: (plus:SI (match_operand:SI 1 "register_operand" "%r,r")
1531: (match_operand:SI 2 "arith_operand" "r,J")))]
1532: ""
1533: "@
1534: add %1,%2,%0
1535: ldo %2(%1),%0")
1536:
1537: (define_insn "subdi3"
1538: [(set (match_operand:DI 0 "register_operand" "=r")
1539: (minus:DI (match_operand:DI 1 "register_operand" "r")
1540: (match_operand:DI 2 "register_operand" "r")))]
1541: ""
1542: "sub %R1,%R2,%R0\;subb %1,%2,%0"
1543: [(set_attr "length" "2")])
1544:
1545: (define_insn "subsi3"
1546: [(set (match_operand:SI 0 "register_operand" "=r,r")
1547: (minus:SI (match_operand:SI 1 "arith11_operand" "r,I")
1548: (match_operand:SI 2 "register_operand" "r,r")))]
1549: ""
1550: "@
1551: sub %1,%2,%0
1552: subi %1,%2,%0")
1553:
1554: ;; The mulsi3 insns set up registers for the millicode call.
1555:
1556: (define_expand "mulsi3"
1557: [(set (reg:SI 26) (match_operand:SI 1 "srcsi_operand" ""))
1558: (set (reg:SI 25) (match_operand:SI 2 "srcsi_operand" ""))
1559: (parallel [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
1560: (clobber (match_scratch:SI 3 ""))
1561: (clobber (reg:SI 26))
1562: (clobber (reg:SI 25))
1563: (clobber (reg:SI 31))])
1564: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1565: ""
1.1.1.2 ! root 1566: "
! 1567: {
! 1568: if (TARGET_SNAKE)
! 1569: {
! 1570: rtx scratch = gen_reg_rtx (DImode);
! 1571: operands[1] = force_reg (SImode, operands[1]);
! 1572: operands[2] = force_reg (SImode, operands[2]);
! 1573: emit_insn (gen_umulsidi3 (scratch, operands[1], operands[2]));
! 1574: emit_insn (gen_rtx (SET, VOIDmode,
! 1575: operands[0],
! 1576: gen_rtx (SUBREG, SImode, scratch, 1)));
! 1577: DONE;
! 1578: }
! 1579: }")
! 1580:
! 1581: (define_insn "umulsidi3"
! 1582: [(set (match_operand:DI 0 "register_operand" "=x")
! 1583: (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "x"))
! 1584: (zero_extend:DI (match_operand:SI 2 "register_operand" "x"))))]
! 1585: "TARGET_SNAKE"
! 1586: "xmpyu %1,%2,%0"
! 1587: [(set_attr "type" "fpmul")])
1.1 root 1588:
1589: (define_insn ""
1590: [(set (reg:SI 29) (mult:SI (reg:SI 26) (reg:SI 25)))
1591: (clobber (match_scratch:SI 0 "=a"))
1592: (clobber (reg:SI 26))
1593: (clobber (reg:SI 25))
1594: (clobber (reg:SI 31))]
1595: ""
1596: "* return output_mul_insn (0);"
1597: [(set_attr "type" "milli")])
1598:
1599: ;;; Division and mod.
1600:
1601: (define_expand "divsi3"
1602: [(set (reg:SI 26) (match_operand:SI 1 "srcsi_operand" ""))
1603: (set (reg:SI 25) (match_operand:SI 2 "srcsi_operand" ""))
1604: (parallel [(set (reg:SI 29) (div:SI (reg:SI 26) (reg:SI 25)))
1605: (clobber (match_scratch:SI 3 ""))
1606: (clobber (reg:SI 26))
1607: (clobber (reg:SI 25))
1608: (clobber (reg:SI 31))])
1609: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1610: ""
1611: "
1612: {
1613: if (!(GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const(operands, 0)))
1614: {
1615: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1616: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1617: emit
1618: (gen_rtx
1619: (PARALLEL, VOIDmode,
1620: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1621: gen_rtx (DIV, SImode,
1622: gen_rtx (REG, SImode, 26),
1623: gen_rtx (REG, SImode, 25))),
1624: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1625: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1626: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1627: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1628: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1629: }
1630: DONE;
1631: }")
1632:
1633: (define_insn ""
1634: [(set (reg:SI 29)
1635: (div:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
1636: (clobber (match_scratch:SI 1 "=a"))
1637: (clobber (reg:SI 26))
1638: (clobber (reg:SI 25))
1639: (clobber (reg:SI 31))]
1640: ""
1641: "*
1642: return output_div_insn (operands, 0);"
1643: [(set_attr "type" "milli")])
1644:
1645: (define_expand "udivsi3"
1646: [(set (reg:SI 26) (match_operand:SI 1 "srcsi_operand" ""))
1647: (set (reg:SI 25) (match_operand:SI 2 "srcsi_operand" ""))
1648: (parallel [(set (reg:SI 29) (udiv:SI (reg:SI 26) (reg:SI 25)))
1649: (clobber (match_scratch:SI 3 ""))
1650: (clobber (reg:SI 26))
1651: (clobber (reg:SI 25))
1652: (clobber (reg:SI 31))])
1653: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1654: ""
1655: "
1656: {
1657: if (!(GET_CODE (operands[2]) == CONST_INT && emit_hpdiv_const(operands, 1)))
1658: {
1659: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1660: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1661: emit
1662: (gen_rtx
1663: (PARALLEL, VOIDmode,
1664: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1665: gen_rtx (UDIV, SImode,
1666: gen_rtx (REG, SImode, 26),
1667: gen_rtx (REG, SImode, 25))),
1668: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1669: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1670: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1671: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1672: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1673: }
1674: DONE;
1675: }")
1676:
1677: (define_insn ""
1678: [(set (reg:SI 29)
1679: (udiv:SI (reg:SI 26) (match_operand:SI 0 "div_operand" "")))
1680: (clobber (match_scratch:SI 1 "=a"))
1681: (clobber (reg:SI 26))
1682: (clobber (reg:SI 25))
1683: (clobber (reg:SI 31))]
1684: ""
1685: "*
1686: return output_div_insn (operands, 1);"
1687: [(set_attr "type" "milli")])
1688:
1689: (define_expand "modsi3"
1690: [(set (reg:SI 26) (match_operand:SI 1 "srcsi_operand" ""))
1691: (set (reg:SI 25) (match_operand:SI 2 "srcsi_operand" ""))
1692: (parallel [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
1693: (clobber (match_scratch:SI 3 ""))
1694: (clobber (reg:SI 26))
1695: (clobber (reg:SI 25))
1696: (clobber (reg:SI 31))])
1697: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1698: ""
1699: "
1700: {
1701: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1702: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1703: emit
1704: (gen_rtx
1705: (PARALLEL, VOIDmode,
1706: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1707: gen_rtx (MOD, SImode,
1708: gen_rtx (REG, SImode, 26),
1709: gen_rtx (REG, SImode, 25))),
1710: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1711: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1712: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1713: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1714: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1715: DONE;
1716: }")
1.1.1.2 ! root 1717:
1.1 root 1718: (define_insn ""
1719: [(set (reg:SI 29) (mod:SI (reg:SI 26) (reg:SI 25)))
1720: (clobber (match_scratch:SI 0 "=a"))
1721: (clobber (reg:SI 26))
1722: (clobber (reg:SI 25))
1723: (clobber (reg:SI 31))]
1724: ""
1725: "*
1726: return output_mod_insn (0);"
1727: [(set_attr "type" "milli")])
1728:
1729: (define_expand "umodsi3"
1730: [(set (reg:SI 26) (match_operand:SI 1 "srcsi_operand" ""))
1731: (set (reg:SI 25) (match_operand:SI 2 "srcsi_operand" ""))
1732: (parallel [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
1733: (clobber (match_scratch:SI 3 ""))
1734: (clobber (reg:SI 26))
1735: (clobber (reg:SI 25))
1736: (clobber (reg:SI 31))])
1737: (set (match_operand:SI 0 "general_operand" "") (reg:SI 29))]
1738: ""
1739: "
1740: {
1741: emit_move_insn (gen_rtx (REG, SImode, 26), operands[1]);
1742: emit_move_insn (gen_rtx (REG, SImode, 25), operands[2]);
1743: emit
1744: (gen_rtx
1745: (PARALLEL, VOIDmode,
1746: gen_rtvec (5, gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 29),
1747: gen_rtx (UMOD, SImode,
1748: gen_rtx (REG, SImode, 26),
1749: gen_rtx (REG, SImode, 25))),
1750: gen_rtx (CLOBBER, VOIDmode, gen_rtx (SCRATCH, SImode, 0)),
1751: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 26)),
1752: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 25)),
1753: gen_rtx (CLOBBER, VOIDmode, gen_rtx (REG, SImode, 31)))));
1754: emit_move_insn (operands[0], gen_rtx (REG, SImode, 29));
1755: DONE;
1756: }")
1757:
1758: (define_insn ""
1759: [(set (reg:SI 29) (umod:SI (reg:SI 26) (reg:SI 25)))
1760: (clobber (match_scratch:SI 0 "=a"))
1761: (clobber (reg:SI 26))
1762: (clobber (reg:SI 25))
1763: (clobber (reg:SI 31))]
1764: ""
1765: "*
1766: return output_mod_insn (1);"
1767: [(set_attr "type" "milli")])
1768:
1769: ;;- and instructions
1770: ;; We define DImode `and` so with DImode `not` we can get
1771: ;; DImode `andn`. Other combinations are possible.
1772:
1773: (define_expand "anddi3"
1774: [(set (match_operand:DI 0 "register_operand" "")
1775: (and:DI (match_operand:DI 1 "arith_double_operand" "")
1776: (match_operand:DI 2 "arith_double_operand" "")))]
1777: ""
1778: "
1779: {
1780: if (! register_operand (operands[1], DImode)
1781: || ! register_operand (operands[2], DImode))
1782: /* Let GCC break this into word-at-a-time operations. */
1783: FAIL;
1784: }")
1785:
1786: (define_insn ""
1787: [(set (match_operand:DI 0 "register_operand" "=r")
1788: (and:DI (match_operand:DI 1 "register_operand" "%r")
1789: (match_operand:DI 2 "register_operand" "r")))]
1790: ""
1791: "and %1,%2,%0\;and %R1,%R2,%R0"
1792: [(set_attr "length" "2")])
1793:
1794: (define_insn "andsi3"
1.1.1.2 ! root 1795: [(set (match_operand:SI 0 "register_operand" "=r,r")
! 1796: (and:SI (match_operand:SI 1 "register_operand" "%r,0")
! 1797: (match_operand:SI 2 "and_operand" "rO,P")))]
1.1 root 1798: ""
1.1.1.2 ! root 1799: "* return output_and (operands); ")
1.1 root 1800:
1801: (define_insn ""
1802: [(set (match_operand:DI 0 "register_operand" "=r")
1.1.1.2 ! root 1803: (and:DI (not:DI (match_operand:DI 1 "register_operand" "r"))
! 1804: (match_operand:DI 2 "register_operand" "r")))]
1.1 root 1805: ""
1806: "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
1807: [(set_attr "length" "2")])
1808:
1809: (define_insn ""
1810: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 ! root 1811: (and:SI (not:SI (match_operand:SI 1 "register_operand" "r"))
! 1812: (match_operand:SI 2 "register_operand" "r")))]
1.1 root 1813: ""
1.1.1.2 ! root 1814: "andcm %2,%1,%0")
1.1 root 1815:
1816: (define_expand "iordi3"
1817: [(set (match_operand:DI 0 "register_operand" "")
1818: (ior:DI (match_operand:DI 1 "arith_double_operand" "")
1819: (match_operand:DI 2 "arith_double_operand" "")))]
1820: ""
1821: "
1822: {
1823: if (! register_operand (operands[1], DImode)
1824: || ! register_operand (operands[2], DImode))
1825: /* Let GCC break this into word-at-a-time operations. */
1826: FAIL;
1827: }")
1828:
1829: (define_insn ""
1830: [(set (match_operand:DI 0 "register_operand" "=r")
1831: (ior:DI (match_operand:DI 1 "register_operand" "%r")
1832: (match_operand:DI 2 "register_operand" "r")))]
1833: ""
1834: "or %1,%2,%0\;or %R1,%R2,%R0"
1835: [(set_attr "length" "2")])
1836:
1837: (define_insn "iorsi3"
1.1.1.2 ! root 1838: [(set (match_operand:SI 0 "register_operand" "=r,r")
! 1839: (ior:SI (match_operand:SI 1 "register_operand" "%r,0")
! 1840: (match_operand:SI 2 "ior_operand" "r,n")))]
1.1 root 1841: ""
1.1.1.2 ! root 1842: "* return output_ior (operands); ")
1.1 root 1843:
1844: (define_expand "xordi3"
1845: [(set (match_operand:DI 0 "register_operand" "")
1846: (xor:DI (match_operand:DI 1 "arith_double_operand" "")
1847: (match_operand:DI 2 "arith_double_operand" "")))]
1848: ""
1849: "
1850: {
1851: if (! register_operand (operands[1], DImode)
1852: || ! register_operand (operands[2], DImode))
1853: /* Let GCC break this into word-at-a-time operations. */
1854: FAIL;
1855: }")
1856:
1857: (define_insn ""
1858: [(set (match_operand:DI 0 "register_operand" "=r")
1859: (xor:DI (match_operand:DI 1 "register_operand" "%r")
1860: (match_operand:DI 2 "register_operand" "r")))]
1861: ""
1862: "xor %1,%2,%0\;xor %R1,%R2,%R0"
1863: [(set_attr "length" "2")])
1864:
1865: (define_insn "xorsi3"
1866: [(set (match_operand:SI 0 "register_operand" "=r")
1867: (xor:SI (match_operand:SI 1 "register_operand" "%r")
1868: (match_operand:SI 2 "register_operand" "r")))]
1869: ""
1.1.1.2 ! root 1870: "xor %1,%2,%0")
1.1 root 1871:
1872: (define_insn "negdi2"
1873: [(set (match_operand:DI 0 "register_operand" "=r")
1874: (neg:DI (match_operand:DI 1 "register_operand" "r")))]
1875: ""
1876: "sub 0,%R1,%R0\;subb 0,%1,%0"
1877: [(set_attr "type" "unary")
1878: (set_attr "length" "2")])
1879:
1880: (define_insn "negsi2"
1881: [(set (match_operand:SI 0 "register_operand" "=r")
1882: (neg:SI (match_operand:SI 1 "register_operand" "r")))]
1883: ""
1.1.1.2 ! root 1884: "sub 0,%1,%0"
1.1 root 1885: [(set_attr "type" "unary")])
1886:
1887: (define_expand "one_cmpldi2"
1888: [(set (match_operand:DI 0 "register_operand" "")
1889: (not:DI (match_operand:DI 1 "arith_double_operand" "")))]
1890: ""
1891: "
1892: {
1893: if (! register_operand (operands[1], DImode))
1894: FAIL;
1895: }")
1896:
1897: (define_insn ""
1898: [(set (match_operand:DI 0 "register_operand" "=r")
1.1.1.2 ! root 1899: (not:DI (match_operand:DI 1 "register_operand" "r")))]
1.1 root 1900: ""
1901: "uaddcm 0,%1,%0\;uaddcm 0,%R1,%R0"
1902: [(set_attr "type" "unary")
1903: (set_attr "length" "2")])
1904:
1905: (define_insn "one_cmplsi2"
1906: [(set (match_operand:SI 0 "register_operand" "=r")
1907: (not:SI (match_operand:SI 1 "register_operand" "r")))]
1908: ""
1909: "uaddcm 0,%1,%0"
1910: [(set_attr "type" "unary")])
1911:
1912: ;; Floating point arithmetic instructions.
1913:
1914: (define_insn "adddf3"
1915: [(set (match_operand:DF 0 "register_operand" "=fx")
1916: (plus:DF (match_operand:DF 1 "register_operand" "fx")
1917: (match_operand:DF 2 "register_operand" "fx")))]
1918: ""
1919: "fadd,dbl %1,%2,%0"
1920: [(set_attr "type" "fpalu")])
1921:
1922: (define_insn "addsf3"
1923: [(set (match_operand:SF 0 "register_operand" "=fx")
1924: (plus:SF (match_operand:SF 1 "register_operand" "fx")
1925: (match_operand:SF 2 "register_operand" "fx")))]
1926: ""
1927: "fadd,sgl %1,%2,%0"
1928: [(set_attr "type" "fpalu")])
1929:
1930: (define_insn "subdf3"
1931: [(set (match_operand:DF 0 "register_operand" "=fx")
1932: (minus:DF (match_operand:DF 1 "register_operand" "fx")
1933: (match_operand:DF 2 "register_operand" "fx")))]
1934: ""
1935: "fsub,dbl %1,%2,%0"
1936: [(set_attr "type" "fpalu")])
1937:
1938: (define_insn "subsf3"
1939: [(set (match_operand:SF 0 "register_operand" "=fx")
1940: (minus:SF (match_operand:SF 1 "register_operand" "fx")
1941: (match_operand:SF 2 "register_operand" "fx")))]
1942: ""
1943: "fsub,sgl %1,%2,%0"
1944: [(set_attr "type" "fpalu")])
1945:
1946: (define_insn "muldf3"
1947: [(set (match_operand:DF 0 "register_operand" "=fx")
1948: (mult:DF (match_operand:DF 1 "register_operand" "fx")
1949: (match_operand:DF 2 "register_operand" "fx")))]
1950: ""
1951: "fmpy,dbl %1,%2,%0"
1952: [(set_attr "type" "fpmul")])
1953:
1954: (define_insn "mulsf3"
1955: [(set (match_operand:SF 0 "register_operand" "=fx")
1956: (mult:SF (match_operand:SF 1 "register_operand" "fx")
1957: (match_operand:SF 2 "register_operand" "fx")))]
1958: ""
1959: "fmpy,sgl %1,%2,%0"
1960: [(set_attr "type" "fpmul")])
1961:
1962: (define_insn "divdf3"
1963: [(set (match_operand:DF 0 "register_operand" "=fx")
1964: (div:DF (match_operand:DF 1 "register_operand" "fx")
1965: (match_operand:DF 2 "register_operand" "fx")))]
1966: ""
1967: "fdiv,dbl %1,%2,%0"
1968: [(set_attr "type" "fpdivdbl")])
1969:
1970: (define_insn "divsf3"
1971: [(set (match_operand:SF 0 "register_operand" "=fx")
1972: (div:SF (match_operand:SF 1 "register_operand" "fx")
1973: (match_operand:SF 2 "register_operand" "fx")))]
1974: ""
1975: "fdiv,sgl %1,%2,%0"
1976: [(set_attr "type" "fpdivsgl")])
1977:
1978: (define_insn "negdf2"
1979: [(set (match_operand:DF 0 "register_operand" "=fx")
1980: (neg:DF (match_operand:DF 1 "register_operand" "fx")))]
1981: ""
1982: "fsub,dbl 0,%1,%0"
1983: [(set_attr "type" "fpalu")])
1984:
1985: (define_insn "negsf2"
1986: [(set (match_operand:SF 0 "register_operand" "=fx")
1987: (neg:SF (match_operand:SF 1 "register_operand" "fx")))]
1988: ""
1989: "fsub,sgl 0, %1,%0"
1990: [(set_attr "type" "fpalu")])
1991:
1992: (define_insn "absdf2"
1993: [(set (match_operand:DF 0 "register_operand" "=fx")
1994: (abs:DF (match_operand:DF 1 "register_operand" "fx")))]
1995: ""
1996: "fabs,dbl %1,%0"
1997: [(set_attr "type" "fpalu")])
1998:
1999: (define_insn "abssf2"
2000: [(set (match_operand:SF 0 "register_operand" "=fx")
2001: (abs:SF (match_operand:SF 1 "register_operand" "fx")))]
2002: ""
2003: "fabs,sgl %1,%0"
2004: [(set_attr "type" "fpalu")])
2005:
2006: (define_insn "sqrtdf2"
2007: [(set (match_operand:DF 0 "register_operand" "=fx")
2008: (sqrt:DF (match_operand:DF 1 "register_operand" "fx")))]
2009: ""
2010: "fsqrt,dbl %1,%0"
2011: [(set_attr "type" "fpsqrtdbl")])
2012:
2013: (define_insn "sqrtsf2"
2014: [(set (match_operand:SF 0 "register_operand" "=fx")
2015: (sqrt:SF (match_operand:SF 1 "register_operand" "fx")))]
2016: ""
2017: "fsqrt,sgl %1,%0"
2018: [(set_attr "type" "fpsqrtsgl")])
2019:
2020: ;;- Shift instructions
2021:
2022: ;; Optimized special case of shifting.
2023:
2024: (define_insn ""
2025: [(set (match_operand:SI 0 "register_operand" "=r")
2026: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
2027: (const_int 24)))]
2028: ""
1.1.1.2 ! root 2029: "ldb%M1 %1,%0"
! 2030: [(set_attr "type" "load")
! 2031: (set_attr "length" "1")])
1.1 root 2032:
2033: (define_insn ""
2034: [(set (match_operand:SI 0 "register_operand" "=r")
1.1.1.2 ! root 2035: (lshiftrt:SI (match_operand:SI 1 "memory_operand" "m")
! 2036: (const_int 16)))]
! 2037: ""
! 2038: "ldh%M1 %1,%0"
! 2039: [(set_attr "type" "load")
! 2040: (set_attr "length" "1")])
! 2041:
! 2042: ;; Using shadd_operand works around a bug in reload. For 2.4 fix
! 2043: ;; reload and use register_operand instead.
! 2044: (define_insn ""
! 2045: [(set (match_operand:SI 0 "register_operand" "=r")
1.1 root 2046: (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
2047: (const_int 2))
1.1.1.2 ! root 2048: (match_operand:SI 1 "shadd_operand" "r")))]
1.1 root 2049: ""
2050: "sh1add %2,%1,%0")
2051:
2052: (define_insn ""
2053: [(set (match_operand:SI 0 "register_operand" "=r")
2054: (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
2055: (const_int 4))
1.1.1.2 ! root 2056: (match_operand:SI 1 "shadd_operand" "r")))]
1.1 root 2057: ""
2058: "sh2add %2,%1,%0")
2059:
2060: (define_insn ""
2061: [(set (match_operand:SI 0 "register_operand" "=r")
2062: (plus:SI (mult:SI (match_operand:SI 2 "register_operand" "r")
2063: (const_int 8))
1.1.1.2 ! root 2064: (match_operand:SI 1 "shadd_operand" "r")))]
1.1 root 2065: ""
2066: "sh3add %2,%1,%0")
2067:
2068: (define_insn "sar_sub"
2069: [(set (match_operand:SI 0 "register_operand" "=r")
2070: (if_then_else (gtu:SI (match_operand:SI 2 "register_operand" "r")
2071: (match_operand:SI 1 "int11_operand" "I"))
2072: (const_int 0)
2073: (minus:SI (match_dup 1) (match_dup 2))))]
2074: ""
2075: "subi,>>= %1,%2,%0\;copy 0,%0"
2076: [(set_attr "length" "2" )])
2077:
2078: (define_expand "ashlsi3"
2079: [(set (match_operand:SI 0 "register_operand" "")
2080: (ashift:SI (match_operand:SI 1 "register_operand" "")
1.1.1.2 ! root 2081: (match_operand:SI 2 "arith32_operand" "")))]
1.1 root 2082: ""
2083: "
2084: {
2085: if (GET_CODE (operands[2]) != CONST_INT)
2086: {
2087: rtx temp = gen_reg_rtx (SImode);
2088: emit_insn (gen_sar_sub (temp,
2089: gen_rtx (CONST_INT, VOIDmode, 31),
2090: operands[2]));
2091: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 112), temp));
2092: emit_insn (gen_rtx (SET, VOIDmode,
2093: operands[0],
2094: gen_rtx (ASHIFT, SImode,
2095: operands[1],
2096: gen_rtx (MINUS, SImode,
2097: gen_rtx (CONST_INT, VOIDmode, 31),
2098: gen_rtx (REG, SImode, 112)))));
2099: DONE;
2100: }
2101: }")
2102:
2103: (define_insn ""
2104: [(set (match_operand:SI 0 "register_operand" "=r")
2105: (ashift:SI (match_operand:SI 1 "register_operand" "r")
1.1.1.2 ! root 2106: (match_operand:SI 2 "const_int_operand" "n")))]
1.1 root 2107: ""
2108: "*
2109: {
2110: rtx xoperands[4];
1.1.1.2 ! root 2111: xoperands[0] = operands[0];
! 2112: xoperands[1] = operands[1];
1.1 root 2113: xoperands[2] = gen_rtx (CONST_INT, VOIDmode,
1.1.1.2 ! root 2114: 31 - (INTVAL (operands[2]) & 31));
1.1 root 2115: xoperands[3] = gen_rtx (CONST_INT, VOIDmode,
1.1.1.2 ! root 2116: 32 - (INTVAL (operands[2]) & 31));
1.1 root 2117: output_asm_insn (\"zdep %1,%2,%3,%0\", xoperands);
2118: return \"\";
2119: }")
2120:
2121: (define_insn ""
2122: [(set (match_operand:SI 0 "register_operand" "=r")
2123: (ashift:SI (match_operand:SI 1 "register_operand" "r")
2124: (minus:SI (const_int 31)
2125: (reg:SI 112))))]
2126: ""
2127: "zvdep %1,32,%0")
2128:
2129: (define_expand "ashrsi3"
2130: [(set (match_operand:SI 0 "register_operand" "")
2131: (ashiftrt:SI (match_operand:SI 1 "register_operand" "")
1.1.1.2 ! root 2132: (match_operand:SI 2 "arith32_operand" "")))]
1.1 root 2133: ""
2134: "
2135: {
2136: if (GET_CODE (operands[2]) != CONST_INT)
2137: {
2138: rtx temp = gen_reg_rtx (SImode);
2139: emit_insn (gen_sar_sub (temp,
2140: gen_rtx (CONST_INT, VOIDmode, 31),
2141: operands[2]));
2142: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 112), temp));
2143: emit_insn (gen_rtx (SET, VOIDmode,
2144: operands[0],
2145: gen_rtx (ASHIFTRT, SImode,
2146: operands[1],
2147: gen_rtx (MINUS, SImode,
2148: gen_rtx (CONST_INT, VOIDmode, 31),
2149: gen_rtx (REG, SImode, 112)))));
2150: DONE;
2151: }
2152: }")
2153:
2154: (define_insn ""
2155: [(set (match_operand:SI 0 "register_operand" "=r")
2156: (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
1.1.1.2 ! root 2157: (match_operand:SI 2 "const_int_operand" "n")))]
1.1 root 2158: ""
2159: "*
2160: {
2161: rtx xoperands[4];
1.1.1.2 ! root 2162: xoperands[0] = operands[0];
! 2163: xoperands[1] = operands[1];
1.1 root 2164: xoperands[2] = gen_rtx (CONST_INT, VOIDmode,
1.1.1.2 ! root 2165: 31 - (INTVAL (operands[2]) & 31));
1.1 root 2166: xoperands[3] = gen_rtx (CONST_INT, VOIDmode,
1.1.1.2 ! root 2167: 32 - (INTVAL (operands[2]) & 31));
1.1 root 2168: output_asm_insn (\"extrs %1,%2,%3,%0\", xoperands);
2169: return \"\";
2170: }")
2171:
2172: (define_insn ""
2173: [(set (match_operand:SI 0 "register_operand" "=r")
2174: (ashiftrt:SI (match_operand:SI 1 "register_operand" "r")
1.1.1.2 ! root 2175: (minus:SI (const_int 31)
! 2176: (reg:SI 112))))]
1.1 root 2177: ""
2178: "vextrs %1,32,%0")
2179:
2180: (define_expand "lshrsi3"
2181: [(set (match_operand:SI 0 "register_operand" "")
2182: (lshiftrt:SI (match_operand:SI 1 "register_operand" "")
1.1.1.2 ! root 2183: (match_operand:SI 2 "arith32_operand" "")))]
1.1 root 2184: ""
2185: "
2186: {
2187: if (GET_CODE (operands[2]) != CONST_INT)
2188: {
2189: rtx temp = gen_reg_rtx (SImode);
2190: emit_insn (gen_sar_sub (temp,
2191: gen_rtx (CONST_INT, VOIDmode, 31),
2192: operands[2]));
2193: emit_insn (gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, 112), temp));
2194: emit_insn (gen_rtx (SET, VOIDmode,
2195: operands[0],
2196: gen_rtx (LSHIFTRT, SImode,
2197: operands[1],
2198: gen_rtx (MINUS, SImode,
2199: gen_rtx (CONST_INT, VOIDmode, 31),
2200: gen_rtx (REG, SImode, 112)))));
2201: DONE;
2202: }
2203: }")
2204:
2205: (define_insn ""
2206: [(set (match_operand:SI 0 "register_operand" "=r")
2207: (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
1.1.1.2 ! root 2208: (match_operand:SI 2 "const_int_operand" "n")))]
1.1 root 2209: ""
2210: "*
2211: {
2212: rtx xoperands[4];
1.1.1.2 ! root 2213: xoperands[0] = operands[0];
! 2214: xoperands[1] = operands[1];
1.1 root 2215: xoperands[2] = gen_rtx (CONST_INT, VOIDmode,
1.1.1.2 ! root 2216: 31 - (INTVAL (operands[2]) & 31));
1.1 root 2217: xoperands[3] = gen_rtx (CONST_INT, VOIDmode,
1.1.1.2 ! root 2218: 32 - (INTVAL (operands[2]) & 31));
1.1 root 2219: output_asm_insn (\"extru %1,%2,%3,%0\", xoperands);
2220: return \"\";
2221: }")
2222:
2223: (define_insn ""
2224: [(set (match_operand:SI 0 "register_operand" "=r")
2225: (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")
1.1.1.2 ! root 2226: (minus:SI (const_int 31)
! 2227: (reg:SI 112))))]
1.1 root 2228: ""
2229: "vextru %1,32,%0")
2230:
2231: ;; Unconditional and other jump instructions.
2232:
2233: (define_insn "jump"
2234: [(set (pc) (label_ref (match_operand 0 "" "")))]
2235: ""
2236: "bl%* %l0,0"
2237: [(set_attr "type" "branch")])
2238:
1.1.1.2 ! root 2239: ;; Subroutines of "casesi".
! 2240: ;; operand 0 is index
! 2241: ;; operand 1 is the minimum bound
! 2242: ;; operand 2 is the maximum bound - minimum bound + 1
! 2243: ;; operand 3 is CODE_LABEL for the table;
! 2244: ;; operand 4 is the CODE_LABEL to go to if index out of range.
! 2245:
! 2246: (define_expand "casesi"
! 2247: [(match_operand:SI 0 "general_operand" "")
! 2248: (match_operand:SI 1 "const_int_operand" "")
! 2249: (match_operand:SI 2 "const_int_operand" "")
! 2250: (match_operand 3 "" "")
! 2251: (match_operand 4 "" "")]
! 2252: ""
! 2253: "
! 2254: {
! 2255: if (GET_CODE (operands[0]) != REG)
! 2256: operands[0] = force_reg (SImode, operands[0]);
! 2257:
! 2258: if (operands[1] != const0_rtx)
! 2259: {
! 2260: rtx reg = gen_reg_rtx (SImode);
! 2261:
! 2262: operands[1] = gen_rtx (CONST_INT, VOIDmode, -INTVAL (operands[1]));
! 2263: if (!INT_14_BITS (operands[1]))
! 2264: operands[1] = force_reg (SImode, operands[1]);
! 2265: emit_insn (gen_addsi3 (reg, operands[0], operands[1]));
! 2266:
! 2267: operands[0] = reg;
! 2268: }
! 2269:
! 2270: if (!INT_11_BITS (operands[2]))
! 2271: operands[2] = force_reg (SImode, operands[2]);
! 2272:
! 2273: emit_jump_insn (gen_casesi0 (operands[0], operands[2],
! 2274: operands[3], operands[4]));
! 2275: DONE;
! 2276: }")
! 2277:
! 2278: (define_insn "casesi0"
1.1 root 2279: [(set (pc)
1.1.1.2 ! root 2280: (if_then_else (leu (match_operand:SI 0 "register_operand" "r")
! 2281: (match_operand:SI 1 "arith11_operand" "rI"))
! 2282: (plus:SI (mem:SI (plus:SI (pc) (match_dup 0)))
! 2283: (label_ref (match_operand 2 "" "")))
1.1 root 2284: (pc)))
1.1.1.2 ! root 2285: (use (label_ref (match_operand 3 "" "")))]
1.1 root 2286: ""
2287: "*
2288: {
2289: if (GET_CODE (operands[1]) == CONST_INT)
2290: {
1.1.1.2 ! root 2291: operands[1] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[1]));
! 2292: return \"addi,uv %1,%0,0\;blr,n %0,0\;b,n %l3\";
1.1 root 2293: }
2294: else
2295: {
1.1.1.2 ! root 2296: return \"sub,>> %0,%1,0\;blr,n %0,0\;b,n %l3\";
1.1 root 2297: }
2298: }"
1.1.1.2 ! root 2299: [(set_attr "length" "3")])
! 2300:
! 2301:
1.1 root 2302: ;; Need nops for the calls because execution is supposed to continue
2303: ;; past; we don't want to nullify an instruction that we need.
2304: ;;- jump to subroutine
2305:
2306: (define_expand "call"
2307: [(parallel [(call (match_operand:SI 0 "" "")
2308: (match_operand 1 "" ""))
2309: (clobber (reg:SI 31))
2310: (clobber (reg:SI 2))])]
2311: ""
2312: "
2313: {
1.1.1.2 ! root 2314: if (TARGET_LONG_CALLS)
! 2315: operands[0] = gen_rtx (MEM, SImode,
! 2316: force_reg (SImode, XEXP (operands[0], 0)));
! 2317: else
! 2318: operands[0] = gen_rtx (MEM, SImode, XEXP (operands[0], 0));
1.1 root 2319: }")
2320:
2321: (define_insn ""
2322: [(call (mem:SI (match_operand:SI 0 "call_operand_address" "r,S"))
2323: (match_operand 1 "" "i,i"))
2324: (clobber (reg:SI 31))
2325: (clobber (reg:SI 2))]
2326: ""
2327: "*
2328: {
2329: if (which_alternative == 0)
2330: return \"copy %0,22\;.CALL\\tARGW0=GR\;bl $$dyncall,31\;copy 31,2\";
2331: else
2332: {
2333: output_arg_descriptor (insn);
2334: return \"bl %0,2%#\";
2335: }
2336: }"
2337: [(set_attr "type" "dyncall,call")
2338: (set_attr "length" "3,1")])
2339:
2340: (define_expand "call_value"
2341: [(parallel [(set (match_operand 0 "" "")
2342: (call (match_operand:SI 1 "" "")
2343: (match_operand 2 "" "")))
2344: (clobber (reg:SI 31))
2345: (clobber (reg:SI 2))])]
2346: ;;- Don't use operand 1 for most machines.
2347: ""
2348: "
2349: {
1.1.1.2 ! root 2350: if (TARGET_LONG_CALLS)
! 2351: operands[1] = gen_rtx (MEM, SImode,
! 2352: force_reg (SImode, XEXP (operands[1], 0)));
! 2353: else
! 2354: operands[1] = gen_rtx (MEM, SImode, XEXP (operands[1], 0));
1.1 root 2355: }")
2356:
2357: (define_insn ""
2358: [(set (match_operand 0 "" "=rfx,rfx")
2359: (call (mem:SI (match_operand:SI 1 "call_operand_address" "r,S"))
2360: (match_operand 2 "" "i,i")))
2361: (clobber (reg:SI 31))
2362: (clobber (reg:SI 2))]
2363: ;;- Don't use operand 1 for most machines.
2364: ""
2365: "*
2366: {
2367: if (which_alternative == 0)
2368: return \"copy %1,22\;.CALL\\tARGW0=GR\;bl $$dyncall,31\;copy 31,2\";
2369: else
2370: {
2371: output_arg_descriptor (insn);
1.1.1.2 ! root 2372: return \"bl %1,2%#\";
1.1 root 2373: }
2374: }"
1.1.1.2 ! root 2375: [(set_attr "type" "dyncall,call")
! 2376: (set_attr "length" "3,1")])
1.1 root 2377:
2378: (define_insn "nop"
2379: [(const_int 0)]
2380: ""
2381: "nop")
2382:
2383: ;;; Hope this is only within a function...
2384: (define_insn "indirect_jump"
2385: [(set (pc) (match_operand:SI 0 "register_operand" "r"))]
2386: ""
1.1.1.2 ! root 2387: "bv%* 0(%0)"
1.1 root 2388: [(set_attr "type" "branch")])
2389:
2390: (define_insn "extzv"
2391: [(set (match_operand:SI 0 "register_operand" "=r")
2392: (zero_extract:SI (match_operand:SI 1 "register_operand" "r")
2393: (match_operand:SI 2 "uint5_operand" "")
2394: (match_operand:SI 3 "uint5_operand" "")))]
2395: ""
2396: "extru %1,%3+%2-1,%2,%0")
2397:
2398: (define_insn "extv"
2399: [(set (match_operand:SI 0 "register_operand" "=r")
2400: (sign_extract:SI (match_operand:SI 1 "register_operand" "r")
2401: (match_operand:SI 2 "uint5_operand" "")
2402: (match_operand:SI 3 "uint5_operand" "")))]
2403: ""
2404: "extrs %1,%3+%2-1,%2,%0")
2405:
2406: (define_insn "insv"
1.1.1.2 ! root 2407: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r,r")
1.1 root 2408: (match_operand:SI 1 "uint5_operand" "")
2409: (match_operand:SI 2 "uint5_operand" ""))
1.1.1.2 ! root 2410: (match_operand:SI 3 "arith5_operand" "r,L"))]
1.1 root 2411: ""
1.1.1.2 ! root 2412: "@
! 2413: dep %3,%2+%1-1,%1,%0
! 2414: depi %3,%2+%1-1,%1,%0")
! 2415:
! 2416: ;; Optimize insertion of const_int values of type 1...1xxxx.
! 2417: (define_insn ""
! 2418: [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
! 2419: (match_operand:SI 1 "uint5_operand" "")
! 2420: (match_operand:SI 2 "uint5_operand" ""))
! 2421: (match_operand:SI 3 "const_int_operand" ""))]
! 2422: "(INTVAL (operands[3]) & 0x10) != 0 &&
! 2423: (~INTVAL (operands[3]) & (1L << INTVAL (operands[1])) - 1 & ~0xf) == 0"
! 2424: "*
! 2425: {
! 2426: operands[3] = gen_rtx (CONST_INT, VOIDmode, (INTVAL (operands[3]) & 0xf) - 0x10);
! 2427: return \"depi %3,%2+%1-1,%1,%0\";
! 2428: }")
1.1 root 2429:
2430: ;; This insn is used for some loop tests, typically loops reversed when
2431: ;; strength reduction is used. It is actually created when the instruction
2432: ;; combination phase combines the special loop test. Since this insn
2433: ;; is both a jump insn and has an output, it must deal with it's own
2434: ;; reloads, hence the `m' constraints. The `!' constraints direct reload
2435: ;; to not choose the register alternatives in the event a reload is needed.
2436:
2437: (define_insn "decrement_and_branch_until_zero"
2438: [(set (pc)
2439: (if_then_else
2440: (ge (plus:SI (match_operand:SI 0 "register_operand" "+!r,m")
2441: (const_int -1))
2442: (const_int 0))
2443: (label_ref (match_operand 1 "" ""))
2444: (pc)))
2445: (set (match_dup 0)
2446: (plus:SI (match_dup 0)
2447: (const_int -1)))
2448: (clobber (match_scratch:SI 2 "=X,r"))]
2449: "find_reg_note (insn, REG_NONNEG, 0)"
2450: "*
2451: {
2452: if (which_alternative == 0)
2453: if (get_attr_length (insn) == 1)
2454: return \"addib,>= -1,%0,%1%#\";
2455: else
2456: return \"addi,< -1,%0,%0\;bl %1,0%#\";
2457: else
2458: {
2459: output_asm_insn (\"ldw %0,%2\;ldo -1(%2),%2\;stw %2,%0\", operands);
2460: if (get_attr_length (insn) == 4)
2461: return \"comb,> 0,%2,%1%#\";
2462: else
2463: return \"comclr,<= 0,%2,0\;bl %1,0%#\";
2464: }
2465: }"
2466: [(set_attr "type" "cbranch")
2467: (set (attr "length")
2468: (if_then_else (eq (symbol_ref "which_alternative") (const_int 0))
2469: (if_then_else (lt (abs (minus (match_dup 1)
2470: (plus (pc) (const_int 2))))
2471: (const_int 1023))
2472: (const_int 1)
2473: (const_int 2))
2474: (if_then_else (lt (match_dup 1)
2475: (pc))
2476: (if_then_else
2477: (lt (abs (minus (match_dup 1)
2478: (plus (pc)
2479: (const_int 5))))
2480: (const_int 1023))
2481: (const_int 4)
2482: (const_int 5))
2483: (if_then_else
2484: (lt (abs (minus (match_dup 1)
2485: (plus (pc)
2486: (const_int 2))))
2487: (const_int 1023))
2488: (const_int 4)
2489: (const_int 5)))))])
2490:
2491:
2492:
2493: ;;- Local variables:
2494: ;;- mode:emacs-lisp
2495: ;;- comment-start: ";;- "
2496: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
2497: ;;- eval: (modify-syntax-entry ?[ "(]")
2498: ;;- eval: (modify-syntax-entry ?] ")[")
2499: ;;- eval: (modify-syntax-entry ?{ "(}")
2500: ;;- eval: (modify-syntax-entry ?} "){")
2501: ;;- End:
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