--- gcc/config/pa/pa.h 2018/04/24 18:10:27 1.1.1.1 +++ gcc/config/pa/pa.h 2018/04/24 18:36:29 1.1.1.5 @@ -1,6 +1,6 @@ /* Definitions of target machine for GNU compiler, for the HP Spectrum. - Copyright (C) 1992, 1993 Free Software Foundation, Inc. - Contributed by Michael Tiemann (tiemann@mcc.com) + Copyright (C) 1992, 1993, 1994, 1995 Free Software Foundation, Inc. + Contributed by Michael Tiemann (tiemann@cygnus.com) of Cygnus Support and Tim Moore (moore@defmacro.cs.utah.edu) of the Center for Software Science at the University of Utah. @@ -18,7 +18,8 @@ GNU General Public License for more deta You should have received a copy of the GNU General Public License along with GNU CC; see the file COPYING. If not, write to -the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. */ +the Free Software Foundation, 59 Temple Place - Suite 330, +Boston, MA 02111-1307, USA. */ enum cmp_type /* comparison type */ { @@ -28,6 +29,24 @@ enum cmp_type /* comparison type */ CMP_MAX /* max comparison type */ }; +/* For long call handling. */ +extern unsigned int total_code_bytes; + +/* Which processor to schedule for. */ + +enum processor_type +{ + PROCESSOR_700, + PROCESSOR_7100, + PROCESSOR_7100LC, +}; + +#define pa_cpu_attr ((enum attr_cpu)pa_cpu) + +/* For -mschedule= option. */ +extern char *pa_cpu_string; +extern enum processor_type pa_cpu; + /* Print subsidiary information on the compiler version in use. */ #define TARGET_VERSION fprintf (stderr, " (hppa)"); @@ -42,42 +61,56 @@ extern int target_flags; /* Disable all FP registers (they all become fixed). This may be necessary for compiling kernels which perform lazy context switching of FP regs. - Note if you use this option and try to perform floating point operations + Note if you use this option and try to perform floating point operations the compiler will abort! */ #define TARGET_DISABLE_FPREGS (target_flags & 2) -/* Force gcc to only use instructions which are safe when compiling kernels. - Specifically, avoid using add instructions with dp (r27) as an argument. - Use addil instructions instead. Doing so avoids a nasty bug in the - HPUX linker. When HP fixes their linker take this option out. */ +/* Generate code which assumes that calls through function pointers will + never cross a space boundary. Such assumptions are generally safe for + building kernels and statically linked executables. Code compiled with + this option will fail miserably if the executable is dynamically linked + or uses nested functions! */ +#define TARGET_FAST_INDIRECT_CALLS (target_flags & 4) + +/* Allow unconditional jumps in the delay slots of call instructions. */ +#define TARGET_JUMP_IN_DELAY (target_flags & 8) + +/* In rare cases, a millicode call via "bl" can not be turned into + a millicode call using "ble" (when SHLIB_INFO subspace is very large). + + This option forces just millicode calls to use inline long-calls + This is far more efficient than the old long-call option which forced + every function to be called indirectly (as is still the case for + TARGET_PORTABLE_RUNTIME). -#define TARGET_KERNEL (target_flags & 4) + ??? What about simple jumps, they can suffer from the same problem. + Would require significant surgery in pa.md. */ -/* Generate code that will link against HPUX 8.0 shared libraries. - Older linkers and assemblers might not support this. */ +#define TARGET_MILLICODE_LONG_CALLS (target_flags & 16) -#define TARGET_SHARED_LIBS 1 /* was (target_flags & 8) */ +/* Disable indexed addressing modes. */ -/* Force all function calls to indirect addressing via a register. This - avoids lossage when the function is very far away from the current PC. +#define TARGET_DISABLE_INDEXING (target_flags & 32) - ??? What about simple jumps, they can suffer from the same problem. - Would require significant surgery in pa.md. */ +/* Emit code which follows the new portable runtime calling conventions + HP wants everyone to use for ELF objects. If at all possible you want + to avoid this since it's a performance loss for non-prototyped code. -#define TARGET_LONG_CALLS (target_flags & 16) + Note TARGET_PORTABLE_RUNTIME also forces all calls to use inline + long-call stubs which is quite expensive. */ -/* Disable indexed addressing modes. Necessary under MACH. +#define TARGET_PORTABLE_RUNTIME (target_flags & 64) - ??? Some problem with a high bit being set in an address having - special meaning to the PA MACH ports. */ +/* Emit directives only understood by GAS. This allows parameter + relocations to work for static functions. There is no way + to make them work the HP assembler at this time. */ -#define TARGET_DISABLE_INDEXING (target_flags & 32) +#define TARGET_GAS (target_flags & 128) -/* Force a colon to be tacked onto the end of local and global - labels. An option because the HP assembler croaks on them. */ +/* Emit code for processors which do not have an FPU. */ -#define TARGET_TRAILING_COLON (target_flags & 64) +#define TARGET_SOFT_FLOAT (target_flags & 256) /* Macro to define tables used to set the flags. This is a list in braces of pairs in braces, @@ -86,60 +119,172 @@ extern int target_flags; An empty string NAME is used to identify the default VALUE. */ #define TARGET_SWITCHES \ - {{"snake", 1}, \ - {"nosnake", -1}, \ - {"pa-risc-1-0", -1}, \ - {"pa-risc-1-1", 1}, \ - {"disable-fpregs", 2},\ - {"kernel", 4}, \ - {"shared-libs", 8}, \ - {"no-shared-libs", -8},\ - {"long-calls", 16}, \ - {"disable-indexing", 32},\ - {"trailing-colon", 64},\ + {{"snake", 1}, \ + {"nosnake", -1}, \ + {"pa-risc-1-0", -1}, \ + {"pa-risc-1-1", 1}, \ + {"disable-fpregs", 2}, \ + {"no-disable-fpregs", -2}, \ + {"fast-indirect-calls", 4}, \ + {"no-fast-indirect-calls", -4},\ + {"jump-in-delay", 8}, \ + {"no-jump-in-delay", -8}, \ + {"millicode-long-calls", 16},\ + {"no-millicode-long-calls", -16},\ + {"disable-indexing", 32}, \ + {"no-disable-indexing", -32},\ + {"portable-runtime", 64+16},\ + {"no-portable-runtime", -(64+16)},\ + {"gas", 128}, \ + {"no-gas", -128}, \ + {"soft-float", 256}, \ + {"no-soft-float", -256}, \ { "", TARGET_DEFAULT}} #ifndef TARGET_DEFAULT -#define TARGET_DEFAULT 0 +#define TARGET_DEFAULT 0x88 /* TARGET_GAS + TARGET_JUMP_IN_DELAY */ #endif +#define TARGET_OPTIONS \ +{ \ + { "schedule=", &pa_cpu_string }\ +} + +#define OVERRIDE_OPTIONS override_options () + #define DBX_DEBUGGING_INFO -#define DEFAULT_GDB_EXTENSIONS 0 +#define DEFAULT_GDB_EXTENSIONS 1 + +/* This is the way other stabs-in-XXX tools do things. We will be + compatible. */ +#define DBX_BLOCKS_FUNCTION_RELATIVE 1 + +/* Likewise for linenos. + + We make the first line stab special to avoid adding several + gross hacks to GAS. */ +#undef ASM_OUTPUT_SOURCE_LINE +#define ASM_OUTPUT_SOURCE_LINE(file, line) \ + { static int sym_lineno = 1; \ + static tree last_function_decl = NULL; \ + if (current_function_decl == last_function_decl) \ + fprintf (file, "\t.stabn 68,0,%d,L$M%d-%s\nL$M%d:\n", \ + line, sym_lineno, \ + XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0) + 1, \ + sym_lineno); \ + else \ + fprintf (file, "\t.stabn 68,0,%d,0\n", line); \ + last_function_decl = current_function_decl; \ + sym_lineno += 1; } + +/* But, to make this work, we have to output the stabs for the function + name *first*... */ +#define DBX_FUNCTION_FIRST + +/* Only labels should ever begin in column zero. */ +#define ASM_STABS_OP "\t.stabs" +#define ASM_STABN_OP "\t.stabn" + +/* GDB always assumes the current function's frame begins at the value + of the stack pointer upon entry to the current function. Accessing + local variables and parameters passed on the stack is done using the + base of the frame + an offset provided by GCC. + + For functions which have frame pointers this method works fine; + the (frame pointer) == (stack pointer at function entry) and GCC provides + an offset relative to the frame pointer. + + This loses for functions without a frame pointer; GCC provides an offset + which is relative to the stack pointer after adjusting for the function's + frame size. GDB would prefer the offset to be relative to the value of + the stack pointer at the function's entry. Yuk! */ +#define DEBUGGER_AUTO_OFFSET(X) \ + ((GET_CODE (X) == PLUS ? INTVAL (XEXP (X, 1)) : 0) \ + + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0))) + +#define DEBUGGER_ARG_OFFSET(OFFSET, X) \ + ((GET_CODE (X) == PLUS ? OFFSET : 0) \ + + (frame_pointer_needed ? 0 : compute_frame_size (get_frame_size (), 0))) + +/* gdb needs a null N_SO at the end of each file for scattered loading. */ + +#undef DBX_OUTPUT_MAIN_SOURCE_FILE_END +#define DBX_OUTPUT_MAIN_SOURCE_FILE_END(FILE, FILENAME) \ + fprintf (FILE, \ + "%s\n\t.stabs \"%s\",%d,0,0,L$text_end\nL$text_end:\n",\ + TEXT_SECTION_ASM_OP, "" , N_SO) #if (TARGET_DEFAULT & 1) == 0 #define CPP_SPEC "%{msnake:-D__hp9000s700 -D_PA_RISC1_1}\ %{mpa-risc-1-1:-D__hp9000s700 -D_PA_RISC1_1}" #else -#define CPP_SPEC "%{!mpa-risc-1-0:%{!mnosnake:-D__hp9000s700 -D_PA_RISC1_1}}" +#define CPP_SPEC "%{!mpa-risc-1-0:%{!mnosnake:%{!msoft-float:-D__hp9000s700 -D_PA_RISC1_1}}}" #endif /* Defines for a K&R CC */ #define CC1_SPEC "%{pg:} %{p:}" - -#define LINK_SPEC "-u main" + +#define LINK_SPEC "%{!shared:-u main} %{shared:-b}" + +/* We don't want -lg. */ +#ifndef LIB_SPEC +#define LIB_SPEC "%{!p:%{!pg:-lc}}%{p:-lc_p}%{pg:-lc_p}" +#endif + +/* Allow $ in identifiers. */ +#define DOLLARS_IN_IDENTIFIERS 2 /* Make gcc agree with */ #define SIZE_TYPE "unsigned int" #define PTRDIFF_TYPE "int" -#define WCHAR_TYPE "short unsigned int" -#define WCHAR_TYPE_SIZE 16 +#define WCHAR_TYPE "unsigned int" +#define WCHAR_TYPE_SIZE 32 -/* Omit frame pointer at high optimization levels. */ - -#define OPTIMIZATION_OPTIONS(OPTIMIZE) \ -{ \ - if (OPTIMIZE >= 2) \ - flag_omit_frame_pointer = 1; \ -} +/* Show we can debug even without a frame pointer. */ +#define CAN_DEBUG_WITHOUT_FP + +/* Machine dependent reorg pass. */ +#define MACHINE_DEPENDENT_REORG(X) pa_reorg(X) /* Names to predefine in the preprocessor for this target machine. */ -#define CPP_PREDEFINES "-Dhppa -Dhp9000s800 -D__hp9000s800 -Dhp9k8 -Dunix -D_HPUX_SOURCE -Dhp9000 -Dhp800 -Dspectrum -DREVARGV" +#define CPP_PREDEFINES "-Dhppa -Dhp9000s800 -D__hp9000s800 -Dhp9k8 -Dunix -D_HPUX_SOURCE -Dhp9000 -Dhp800 -Dspectrum -DREVARGV -Asystem(unix) -Asystem(bsd) -Acpu(hppa) -Amachine(hppa)" + +/* HPUX has a program 'chatr' to list the dependencies of dynamically + linked executables and shared libraries. */ +#define LDD_SUFFIX "chatr" +/* look for lines like "dynamic /usr/lib/X11R5/libX11.sl". */ +#define PARSE_LDD_OUTPUT(PTR) \ +do { \ + while (*PTR == ' ') PTR++; \ + if (strncmp (PTR, "dynamic", sizeof ("dynamic") - 1) == 0) \ + { \ + PTR += sizeof ("dynamic") - 1; \ + while (*p == ' ') PTR++; \ + } \ + else \ + PTR = 0; \ +} while (0) /* target machine storage layout */ +/* Define for cross-compilation from a host with a different float format + or endianness (e.g. VAX, x86). */ +#define REAL_ARITHMETIC + +/* Define this macro if it is advisable to hold scalars in registers + in a wider mode than that declared by the program. In such cases, + the value is constrained to be within the bounds of the declared + type, but kept valid in the wider mode. The signedness of the + extension may differ from that of the type. */ + +#define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ + if (GET_MODE_CLASS (MODE) == MODE_INT \ + && GET_MODE_SIZE (MODE) < 4) \ + (MODE) = SImode; + /* Define this if most significant bit is lowest numbered in instructions that operate on numbered bit-fields. */ #define BITS_BIG_ENDIAN 1 @@ -150,8 +295,6 @@ extern int target_flags; /* Define this if most significant word of a multiword number is lowest numbered. */ -/* For the HP-PA we can decide arbitrarily - since there are no machine instructions for them. */ #define WORDS_BIG_ENDIAN 1 /* number of bits in an addressable storage unit */ @@ -178,7 +321,7 @@ extern int target_flags; #define MAX_PARM_BOUNDARY 64 /* Boundary (in *bits*) on which stack pointer should be aligned. */ -#define STACK_BOUNDARY (TARGET_SNAKE ? 512 : 64) +#define STACK_BOUNDARY 512 /* Allocation boundary (in *bits*) for the code of a function. */ #define FUNCTION_BOUNDARY 32 @@ -195,6 +338,9 @@ extern int target_flags; /* No data type wants to be aligned rounder than this. */ #define BIGGEST_ALIGNMENT 64 +/* The .align directive in the HP assembler allows up to a 32 alignment. */ +#define MAX_OFILE_ALIGNMENT 32768 + /* Get around hp-ux assembler bug, and make strcpy of constants fast. */ #define CONSTANT_ALIGNMENT(CODE, TYPEALIGN) \ ((TYPEALIGN) < 32 ? 32 : (TYPEALIGN)) @@ -224,9 +370,9 @@ extern int target_flags; HP-PA 1.0 has 32 fullword registers and 16 floating point registers. The floating point registers hold either word or double word values. - + 16 additional registers are reserved. - + HP-PA 1.1 has 32 fullword registers and 32 floating point registers. However, the floating point registers behave differently: the left and right halves of registers are addressable @@ -234,8 +380,8 @@ extern int target_flags; has different fp units: define separate register sets for the 1.0 and 1.1 fp units. */ -#define FIRST_PSEUDO_REGISTER 101 /* 32 + 12 1.0 regs + 56 1.1 regs + */ - /* 1 shift reg */ +#define FIRST_PSEUDO_REGISTER 89 /* 32 general regs + 56 fp regs + + + 1 shift reg */ /* 1 for registers that have pervasive standard uses and are not available for the register allocator. @@ -245,15 +391,15 @@ extern int target_flags; so is not fixed. Reg 1 = ADDIL target/Temporary (hardware). Reg 2 = Return Pointer - Reg 3 = Preserved Register (Gnu). Frame Pointer (> 8k frames HP.) - Reg 4 = Frame Pointer (Gnu) - Reg 5-18 = Preserved Registers + Reg 3 = Frame Pointer + Reg 4 = Frame Pointer (>8k varying frame with HP compilers only) + Reg 4-18 = Preserved Registers Reg 19 = Linkage Table Register in HPUX 8.0 shared library scheme. Reg 20-22 = Temporary Registers Reg 23-26 = Temporary/Parameter Registers Reg 27 = Global Data Pointer (hp) Reg 28 = Temporary/???/Return Value register - Reg 29 = Temporary/Static Chain/Return Value register + Reg 29 = Temporary/Static Chain/Return Value register #2 Reg 30 = stack pointer Reg 31 = Temporary/Millicode Return Pointer (hp) @@ -271,7 +417,6 @@ extern int target_flags; Freg 8L-11R = Temporary Registers Freg 12L-21R = Preserved Registers Freg 22L-31R = Temporary Registers - */ @@ -280,10 +425,7 @@ extern int target_flags; 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 1, 0, 0, 1, 0, \ - /* 1.0 fp registers */ \ - 0, 0, 0, 0, \ - 0, 0, 0, 0, 0, 0, 0, 0, \ - /* 1.1 fp registers */ \ + /* fp registers */ \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -304,10 +446,7 @@ extern int target_flags; 0, 0, 0, 0, 0, 0, 0, 0, \ 0, 0, 0, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ - /* 1.0 fp registers */ \ - 1, 1, 1, 1, \ - 1, 1, 1, 1, 0, 0, 0, 0, \ - /* 1.1 fp registers */ \ + /* fp registers */ \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 0, 0, 0, 0, 0, 0, 0, 0, \ @@ -315,47 +454,30 @@ extern int target_flags; 0, 0, 0, 0, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ 1, 1, 1, 1, 1, 1, 1, 1, \ - 1} - -/* Make sure everything's fine if we *don't* have a given processor. - This assumes that putting a register in fixed_regs will keep the - compiler's mitts completely off it. We don't bother to zero it out - of register classes. */ + 1} #define CONDITIONAL_REGISTER_USAGE \ { \ - int i; \ - HARD_REG_SET x; \ if (!TARGET_SNAKE) \ { \ - COPY_HARD_REG_SET (x, reg_class_contents[(int)SNAKE_FP_REGS]);\ - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ - if (TEST_HARD_REG_BIT (x, i)) \ + for (i = 56; i < 88; i++) \ + fixed_regs[i] = call_used_regs[i] = 1; \ + for (i = 33; i < 88; i += 2) \ fixed_regs[i] = call_used_regs[i] = 1; \ } \ - else if (TARGET_DISABLE_FPREGS) \ + if (TARGET_DISABLE_FPREGS || TARGET_SOFT_FLOAT)\ { \ - COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]);\ - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ - if (TEST_HARD_REG_BIT (x, i)) \ - fixed_regs[i] = call_used_regs[i] = 1; \ - COPY_HARD_REG_SET (x, reg_class_contents[(int)SNAKE_FP_REGS]);\ - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ - if (TEST_HARD_REG_BIT (x, i)) \ + for (i = 32; i < 88; i++) \ fixed_regs[i] = call_used_regs[i] = 1; \ } \ - else \ - { \ - COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ - for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) \ - if (TEST_HARD_REG_BIT (x, i)) \ - fixed_regs[i] = call_used_regs[i] = 1; \ - } \ if (flag_pic) \ - fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ + { \ + fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ + fixed_regs[PIC_OFFSET_TABLE_REGNUM_SAVED] = 1;\ + } \ } -/* Allocated the call used registers first. This should minimize +/* Allocate the call used registers first. This should minimize the number of registers that need to be saved (as call used registers will generally not be allocated across a call). @@ -363,30 +485,30 @@ extern int target_flags; FP registers first. */ #define REG_ALLOC_ORDER \ - /* 1.0 caller-saved fp regs. */ \ - {36, 37, 38, 39, 32, 33, 34, 35, \ - /* 1.1 caller-saved fp regs. */ \ - 52, 53, 54, 55, 56, 57, 58, 59, \ - 80, 81, 82, 83, 84, 85, 86, 87, \ - 88, 89, 90, 91, 92, 93, 94, 95, \ - 96, 97, 98, 99, \ - 44, 45, 46, 47, 48, 49, 50, 51, \ + { \ + /* caller-saved fp regs. */ \ + 40, 41, 42, 43, 44, 45, 46, 47, \ + 68, 69, 70, 71, 72, 73, 74, 75, \ + 76, 77, 78, 79, 80, 81, 82, 83, \ + 84, 85, 86, 87, \ + 32, 33, 34, 35, 36, 37, 38, 39, \ /* caller-saved general regs. */ \ 19, 20, 21, 22, 23, 24, 25, 26, \ 27, 28, 29, 31, 2, \ - /* 1.0 callee-saved fp regs. */ \ - 40, 41, 42, 43, \ - /* 1.1 callee-saved fp regs. */ \ - 60, 61, 62, 63, 64, 65, 66, 67, \ - 68, 69, 70, 71, 72, 73, 74, 75, \ - 76, 77, 78, 79, \ + /* callee-saved fp regs. */ \ + 48, 49, 50, 51, 52, 53, 54, 55, \ + 56, 57, 58, 59, 60, 61, 62, 63, \ + 64, 65, 66, 67, \ /* callee-saved general regs. */ \ 3, 4, 5, 6, 7, 8, 9, 10, \ 11, 12, 13, 14, 15, 16, 17, 18, \ /* special registers. */ \ - 1, 30, 0, 100} + 1, 30, 0, 88} +/* True if register is floating-point. */ +#define FP_REGNO_P(N) ((N) >= 32 && (N) <= 87) + /* Return number of consecutive hard regs needed starting at reg REGNO to hold something of mode MODE. This is ordinarily the length in words of a value of mode MODE @@ -395,21 +517,20 @@ extern int target_flags; On the HP-PA, ordinary registers hold 32 bits worth; The floating point registers are 64 bits wide. Snake fp regs are 32 bits wide */ -#define HARD_REGNO_NREGS(REGNO, MODE) \ - (((REGNO) < 32 || (REGNO) >= 44) \ - ? ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) : 1) +#define HARD_REGNO_NREGS(REGNO, MODE) \ + (!TARGET_SNAKE && FP_REGNO_P (REGNO) ? 1 \ + : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. On the HP-PA, the cpu registers can hold any mode. We force this to be an even register is it cannot hold the full mode. */ #define HARD_REGNO_MODE_OK(REGNO, MODE) \ ((REGNO) == 0 ? (MODE) == CCmode || (MODE) == CCFPmode \ - : (REGNO) < 32 ? ((GET_MODE_SIZE (MODE) <= 4) ? 1 : ((REGNO) & 1) == 0)\ - : (REGNO) < 44 ? (GET_MODE_SIZE (MODE) <= 4 \ - || (GET_MODE_SIZE (MODE) > 4 \ - && GET_MODE_CLASS (MODE) == MODE_FLOAT)) \ - : (GET_MODE_SIZE (MODE) > 4 ? ((REGNO) & 1) == 0 \ - : 1)) + /* On 1.0 machines, don't allow wide non-fp modes in fp regs. */ \ + : !TARGET_SNAKE && FP_REGNO_P (REGNO) \ + ? GET_MODE_SIZE (MODE) <= 4 || GET_MODE_CLASS (MODE) == MODE_FLOAT \ + /* Make wide modes be in aligned registers. */ \ + : GET_MODE_SIZE (MODE) <= 4 || ((REGNO) & 1) == 0) /* Value is 1 if it is a good idea to tie two pseudo registers when one has mode MODE1 and one has mode MODE2. @@ -428,11 +549,11 @@ extern int target_flags; #define STACK_POINTER_REGNUM 30 /* Base register for access to local variables of the function. */ -#define FRAME_POINTER_REGNUM 4 +#define FRAME_POINTER_REGNUM 3 /* Value should be nonzero if functions must have frame pointers. */ #define FRAME_POINTER_REQUIRED (current_function_calls_alloca) - + /* C statement to store the difference between the frame pointer and the stack pointer values immediately after the function prologue. @@ -444,7 +565,7 @@ extern int target_flags; do {(VAR) = - compute_frame_size (get_frame_size (), 0);} while (0) /* Base register for access to arguments of the function. */ -#define ARG_POINTER_REGNUM 4 +#define ARG_POINTER_REGNUM 3 /* Register in which static-chain is passed to a function. */ /* ??? */ @@ -454,9 +575,16 @@ extern int target_flags; data references. */ #define PIC_OFFSET_TABLE_REGNUM 19 +#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1 -#define INITIALIZE_PIC initialize_pic () -#define FINALIZE_PIC finalize_pic () +/* Register into which we save the PIC_OFFEST_TABLE_REGNUM so that it + can be restore across function calls. */ +#define PIC_OFFSET_TABLE_REGNUM_SAVED 4 + +/* SOM ABI says that objects larger than 64 bits are returned in memory. */ +#define DEFAULT_PCC_STRUCT_RETURN 0 +#define RETURN_IN_MEMORY(TYPE) \ + (int_size_in_bytes (TYPE) > 8 || TREE_ADDRESSABLE (TYPE)) /* Register in which address to store a structure value is passed to a function. */ @@ -484,23 +612,18 @@ extern int target_flags; /* The HP-PA has four kinds of registers: general regs, 1.0 fp regs, 1.1 fp regs, and the high 1.1 fp regs, to which the operands of - fmpyadd and fmpysub are restricted. - - FP_OR_SNAKE_FP_REGS is for reload_{in,out}di only and isn't used - anywhere else. */ + fmpyadd and fmpysub are restricted. */ enum reg_class { NO_REGS, R1_REGS, GENERAL_REGS, FP_REGS, GENERAL_OR_FP_REGS, - HI_SNAKE_FP_REGS, SNAKE_FP_REGS, GENERAL_OR_SNAKE_FP_REGS, - FP_OR_SNAKE_FP_REGS, NON_SHIFT_REGS, SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES}; + SHIFT_REGS, ALL_REGS, LIM_REG_CLASSES}; #define N_REG_CLASSES (int) LIM_REG_CLASSES /* Give names of register classes as strings for dump file. */ #define REG_CLASS_NAMES \ - { "NO_REGS", "R1_REGS", "GENERAL_REGS", "FP_REGS", "GENERAL_OR_FP_REGS",\ - "HI_SNAKE_FP_REGS", "SNAKE_FP_REGS", "GENERAL_OR_SNAKE_FP_REGS",\ - "FP_OR_SNAKE_FP_REGS", "NON_SHIFT_REGS", "SHIFT_REGS", "ALL_REGS"} + {"NO_REGS", "R1_REGS", "GENERAL_REGS", "FP_REGS", \ + "GENERAL_OR_FP_REGS", "SHIFT_REGS", "ALL_REGS"} /* Define which registers fit in which classes. This is an initializer for a vector of HARD_REG_SET @@ -508,31 +631,24 @@ enum reg_class { NO_REGS, R1_REGS, GENER is in no class. */ #define REG_CLASS_CONTENTS \ -{ {0, 0, 0, 0}, /* NO_REGS */ \ - {0x2, 0, 0, 0}, /* R1_REGS */ \ - {-2, 0, 0, 0}, /* GENERAL_REGS */ \ - {0, 0xfff, 0, 0}, /* FP_REGS */ \ - {-2, 0xfff, 0, 0}, /* GENERAL_OR_FP_REGS */\ - {0, 0, 0xfffffff0, 0xf}, /* HI_SNAKE_FP_REGS */ \ - {0, 0xfffff000, ~0, 0xf}, /* SNAKE_FP_REGS */ \ - {-2, 0xfffff000, ~0, 0xf}, /* GENERAL_OR_SNAKE_FP_REGS */\ - {0, ~0, ~0, 0xf}, /* FP_OR_SNAKE_FP_REGS */\ - {-2, ~0, ~0, ~0x10}, /* NON_SHIFT_REGS */ \ - {0, 0, 0, 0x10}, /* SHIFT_REGS */ \ - {-2, ~0, ~0, 0x1f}} /* ALL_REGS */ + {{0x00000000, 0x00000000, 0x00000000}, /* NO_REGS */ \ + {0x00000002, 0x00000000, 0x00000000}, /* R1_REGS */ \ + {0xfffffffe, 0x00000000, 0x00000000}, /* GENERAL_REGS */ \ + {0x00000000, 0xffffffff, 0x00ffffff}, /* FP_REGS */ \ + {0xfffffffe, 0xffffffff, 0x00ffffff}, /* GENERAL_OR_FP_REGS */ \ + {0x00000000, 0x00000000, 0x01000000}, /* SHIFT_REGS */ \ + {0xfffffffe, 0xffffffff, 0x01ffffff}} /* ALL_REGS */ /* The same information, inverted: Return the class number of the smallest class containing reg number REGNO. This could be a conditional expression or could index an array. */ -#define REGNO_REG_CLASS(REGNO) \ - ((REGNO) == 0 ? NO_REGS \ - : (REGNO) == 1 ? R1_REGS \ - : (REGNO) < 32 ? GENERAL_REGS \ - : (REGNO) < 44 ? FP_REGS \ - : (REGNO) < 68 ? SNAKE_FP_REGS \ - : (REGNO) < 100 ? HI_SNAKE_FP_REGS \ +#define REGNO_REG_CLASS(REGNO) \ + ((REGNO) == 0 ? NO_REGS \ + : (REGNO) == 1 ? R1_REGS \ + : (REGNO) < 32 ? GENERAL_REGS \ + : (REGNO) < 88 ? FP_REGS \ : SHIFT_REGS) /* The class value for index registers, and the one for base regs. */ @@ -540,20 +656,16 @@ enum reg_class { NO_REGS, R1_REGS, GENER #define BASE_REG_CLASS GENERAL_REGS #define FP_REG_CLASS_P(CLASS) \ - (CLASS == FP_REGS || CLASS == SNAKE_FP_REGS || CLASS == HI_SNAKE_FP_REGS) - -/* Get reg_class from a letter such as appears in the machine description. - Note 'Z' is not the same as 'r' since SHIFT_REGS is not part of - GENERAL_REGS. */ + ((CLASS) == FP_REGS) +/* Get reg_class from a letter such as appears in the machine description. */ +/* Keep 'x' for backward compatibility with user asm. */ #define REG_CLASS_FROM_LETTER(C) \ - ((C) == 'f' ? (!TARGET_SNAKE ? FP_REGS : NO_REGS) : \ - ((C) == 'x' ? (TARGET_SNAKE ? SNAKE_FP_REGS : NO_REGS) : \ - ((C) == 'y' ? (TARGET_SNAKE ? HI_SNAKE_FP_REGS : NO_REGS) : \ - ((C) == 'q' ? SHIFT_REGS : \ - ((C) == 'a' ? R1_REGS : \ - ((C) == 'z' ? FP_OR_SNAKE_FP_REGS : \ - ((C) == 'Z' ? ALL_REGS : NO_REGS))))))) + ((C) == 'f' ? FP_REGS : \ + (C) == 'x' ? FP_REGS : \ + (C) == 'q' ? SHIFT_REGS : \ + (C) == 'a' ? R1_REGS : \ + (C) == 'Z' ? ALL_REGS : NO_REGS) /* The letters I, J, K, L and M in a register constraint string can be used to stand for particular ranges of immediate operands. @@ -604,11 +716,10 @@ enum reg_class { NO_REGS, R1_REGS, GENER #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ secondary_reload_class (CLASS, MODE, IN) -/* On the PA it is not possible to directly move data between +/* On the PA it is not possible to directly move data between GENERAL_REGS and FP_REGS. */ #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ - ((FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2)) \ - || (! FP_REG_CLASS_P (CLASS1) && FP_REG_CLASS_P (CLASS2))) + (FP_REG_CLASS_P (CLASS1) != FP_REG_CLASS_P (CLASS2)) /* Return the stack location to use for secondary memory needed reloads. */ #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ @@ -616,8 +727,9 @@ enum reg_class { NO_REGS, R1_REGS, GENER /* Return the maximum number of consecutive registers needed to represent mode MODE in a register of class CLASS. */ -#define CLASS_MAX_NREGS(CLASS, MODE) \ - ((CLASS) == FP_REGS ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) +#define CLASS_MAX_NREGS(CLASS, MODE) \ + (!TARGET_SNAKE && (CLASS) == FP_REGS ? 1 : \ + ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) /* Stack layout; function entry, exit and calling. */ @@ -654,12 +766,12 @@ enum reg_class { NO_REGS, R1_REGS, GENER ??? Have to check on this.*/ -#define FIRST_PARM_OFFSET(FNDECL) -32 +#define FIRST_PARM_OFFSET(FNDECL) -32 /* Absolute value of offset from top-of-stack address to location to store the function parameter if it can't go in a register. Addresses for following parameters are computed relative to this one. */ -#define FIRST_PARM_CALLER_OFFSET(FNDECL) -32 +#define FIRST_PARM_CALLER_OFFSET(FNDECL) -32 /* When a parameter is passed in a register, stack space is still @@ -675,11 +787,11 @@ enum reg_class { NO_REGS, R1_REGS, GENER doesn't behave itself when the stack pointer moves within the function! */ #define ACCUMULATE_OUTGOING_ARGS - -/* The weird HPPA calling conventions require a minimum of 48 bytes on + +/* The weird HPPA calling conventions require a minimum of 48 bytes on the stack: 16 bytes for register saves, and 32 bytes for magic. This is the difference between the logical top of stack and the - actual sp. */ + actual sp. */ #define STACK_POINTER_OFFSET -32 #define STACK_DYNAMIC_OFFSET(FNDECL) \ @@ -687,10 +799,11 @@ enum reg_class { NO_REGS, R1_REGS, GENER /* Value is 1 if returning from a function call automatically pops the arguments described by the number-of-args field in the call. + FUNDECL is the declaration node of the function (as a tree), FUNTYPE is the data type of the function (as a tree), or for a library call it is an identifier node for the subroutine name. */ -#define RETURN_POPS_ARGS(FUNTYPE,SIZE) 0 +#define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 /* Define how to find the value returned by a function. VALTYPE is the data type of the value (as a tree). @@ -702,28 +815,29 @@ enum reg_class { NO_REGS, R1_REGS, GENER #define FUNCTION_VALUE(VALTYPE, FUNC) \ - gen_rtx (REG, TYPE_MODE (VALTYPE), ((TYPE_MODE (VALTYPE) == SFmode ||\ - TYPE_MODE (VALTYPE) == DFmode) ? \ - (TARGET_SNAKE ? 44 : 32) : 28)) + gen_rtx (REG, TYPE_MODE (VALTYPE), ((! TARGET_SOFT_FLOAT \ + && (TYPE_MODE (VALTYPE) == SFmode || \ + TYPE_MODE (VALTYPE) == DFmode)) ? \ + 32 : 28)) /* Define how to find the value returned by a library function assuming the value has mode MODE. */ -#define LIBCALL_VALUE(MODE) \ - gen_rtx (REG, MODE, (MODE == SFmode || MODE == DFmode ?\ - (TARGET_SNAKE ? 44 : 32) : 28)) +#define LIBCALL_VALUE(MODE) \ + gen_rtx (REG, MODE, \ + (! TARGET_SOFT_FLOAT \ + && ((MODE) == SFmode || (MODE) == DFmode) ? 32 : 28)) /* 1 if N is a possible register number for a function value as seen by the caller. */ -#define FUNCTION_VALUE_REGNO_P(N) ((N) == 28 || (N) == (TARGET_SNAKE ? 44 : 32)) +#define FUNCTION_VALUE_REGNO_P(N) \ + ((N) == 28 || (! TARGET_SOFT_FLOAT && (N) == 32)) /* 1 if N is a possible register number for function argument passing. */ -#define FUNCTION_ARG_REGNO_P(N) \ - (((N) >= 23 && (N) <= 26) \ - || ((N) >= 32 && (N) <= 35 && ! TARGET_SNAKE) \ - || ((N) >= 44 && (N) <= 51 && TARGET_SNAKE)) +#define FUNCTION_ARG_REGNO_P(N) \ + (((N) >= 23 && (N) <= 26) || (! TARGET_SOFT_FLOAT && (N) >= 32 && (N) <= 39)) /* Define a data type for recording info about an argument list during the scan of that argument list. This data type should @@ -736,14 +850,30 @@ enum reg_class { NO_REGS, R1_REGS, GENER if any, which holds the structure-value-address). Thus 4 or more means all following args should go on the stack. */ -#define CUMULATIVE_ARGS int +struct hppa_args {int words, nargs_prototype; }; + +#define CUMULATIVE_ARGS struct hppa_args /* Initialize a variable CUM of type CUMULATIVE_ARGS for a call to a function whose data type is FNTYPE. - For a library call, FNTYPE is 0. -*/ + For a library call, FNTYPE is 0. */ + +#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) \ + (CUM).words = 0, \ + (CUM).nargs_prototype = (FNTYPE && TYPE_ARG_TYPES (FNTYPE) \ + ? (list_length (TYPE_ARG_TYPES (FNTYPE)) - 1 \ + + (TYPE_MODE (TREE_TYPE (FNTYPE)) == BLKmode \ + || RETURN_IN_MEMORY (TREE_TYPE (FNTYPE)))) \ + : 0) + -#define INIT_CUMULATIVE_ARGS(CUM,FNTYPE,LIBNAME) ((CUM) = 0) + +/* Similar, but when scanning the definition of a procedure. We always + set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ + +#define INIT_CUMULATIVE_INCOMING_ARGS(CUM,FNTYPE,IGNORE) \ + (CUM).words = 0, \ + (CUM).nargs_prototype = 1000 /* Figure out the size in words of the function argument. */ @@ -755,8 +885,12 @@ enum reg_class { NO_REGS, R1_REGS, GENER (TYPE is null for libcalls where that information may not be available.) */ #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ - (((((CUM) & 01) && (TYPE) != 0 && FUNCTION_ARG_SIZE(MODE, TYPE) > 1)\ - && (CUM)++), (CUM) += FUNCTION_ARG_SIZE(MODE, TYPE)) +{ (CUM).nargs_prototype--; \ + ((((CUM).words & 01) && (TYPE) != 0 \ + && FUNCTION_ARG_SIZE(MODE, TYPE) > 1) \ + && (CUM).words++), \ + (CUM).words += FUNCTION_ARG_SIZE(MODE, TYPE); \ +} /* Determine where to put an argument to a function. Value is zero to push the argument on the stack, @@ -769,9 +903,9 @@ enum reg_class { NO_REGS, R1_REGS, GENER CUM is a variable of type CUMULATIVE_ARGS which gives info about the preceding args and about the function being called. NAMED is nonzero if this argument is a named parameter - (otherwise it is an extra parameter matching an ellipsis). */ + (otherwise it is an extra parameter matching an ellipsis). -/* On the HP-PA the first four words of args are normally in registers + On the HP-PA the first four words of args are normally in registers and the rest are pushed. But any arg that won't entirely fit in regs is pushed. @@ -780,30 +914,69 @@ enum reg_class { NO_REGS, R1_REGS, GENER The caller must make a distinction between calls to explicitly named functions and calls through pointers to functions -- the conventions are different! Calls through pointers to functions only use general - registers for the first four argument words. */ + registers for the first four argument words. -#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE)) + Of course all this is different for the portable runtime model + HP wants everyone to use for ELF. Ugh. Here's a quick description + of how it's supposed to work. -#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ - (4 >= ((CUM) + FUNCTION_ARG_SIZE ((MODE), (TYPE))) \ - ? gen_rtx (REG, (MODE), \ - (FUNCTION_ARG_SIZE ((MODE), (TYPE)) > 1 \ - ? ((! (TARGET_SHARED_LIBS && current_call_is_indirect) \ - && (MODE) == DFmode) \ - ? ((CUM) ? (TARGET_SNAKE ? 50 : 35) \ - : (TARGET_SNAKE ? 46 : 33)) \ - : ((CUM) ? 23 : 25)) \ - : ((! (TARGET_SHARED_LIBS && current_call_is_indirect) \ - && (MODE) == SFmode) \ - ? (TARGET_SNAKE ? 44 + 2 * (CUM) : 32 + (CUM)) \ - : (27 - (CUM) - FUNCTION_ARG_SIZE ((MODE), (TYPE))))))\ - : 0) + 1) callee side remains unchanged. It expects integer args to be + in the integer registers, float args in the float registers and + unnamed args in integer registers. + + 2) caller side now depends on if the function being called has + a prototype in scope (rather than if it's being called indirectly). -/* Define where a function finds its arguments. - This would be different from FUNCTION_ARG if we had register windows. */ + 2a) If there is a prototype in scope, then arguments are passed + according to their type (ints in integer registers, floats in float + registers, unnamed args in integer registers. -#define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ - FUNCTION_ARG (CUM, MODE, TYPE, NAMED) + 2b) If there is no prototype in scope, then floating point arguments + are passed in both integer and float registers. egad. + + FYI: The portable parameter passing conventions are almost exactly like + the standard parameter passing conventions on the RS6000. That's why + you'll see lots of similar code in rs6000.h. */ + +#define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding ((MODE), (TYPE)) + +/* Do not expect to understand this without reading it several times. I'm + tempted to try and simply it, but I worry about breaking something. */ + +#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ + (4 >= ((CUM).words + FUNCTION_ARG_SIZE ((MODE), (TYPE))) \ + ? (!TARGET_PORTABLE_RUNTIME || (TYPE) == 0 \ + || !FLOAT_MODE_P (MODE) || TARGET_SOFT_FLOAT \ + || (CUM).nargs_prototype > 0) \ + ? gen_rtx (REG, (MODE), \ + (FUNCTION_ARG_SIZE ((MODE), (TYPE)) > 1 \ + ? (((!current_call_is_indirect \ + || TARGET_PORTABLE_RUNTIME) \ + && (MODE) == DFmode \ + && ! TARGET_SOFT_FLOAT) \ + ? ((CUM).words ? 38 : 34) \ + : ((CUM).words ? 23 : 25)) \ + : (((!current_call_is_indirect \ + || TARGET_PORTABLE_RUNTIME) \ + && (MODE) == SFmode \ + && ! TARGET_SOFT_FLOAT) \ + ? (32 + 2 * (CUM).words) \ + : (27 - (CUM).words - FUNCTION_ARG_SIZE ((MODE), \ + (TYPE))))))\ + /* We are calling a non-prototyped function with floating point \ + arguments using the portable conventions. */ \ + : gen_rtx (EXPR_LIST, VOIDmode, \ + gen_rtx (REG, (MODE), \ + (FUNCTION_ARG_SIZE ((MODE), (TYPE)) > 1 \ + ? ((CUM).words ? 38 : 34) \ + : (32 + 2 * (CUM).words))), \ + gen_rtx (REG, (MODE), \ + (FUNCTION_ARG_SIZE ((MODE), (TYPE)) > 1 \ + ? ((CUM).words ? 23 : 25) \ + : (27 - (CUM).words - FUNCTION_ARG_SIZE ((MODE),\ + (TYPE)))))) \ + /* Pass this parameter in the stack. */ \ + : 0) /* For an arg passed partly in registers and partly in memory, this is the number of registers used. @@ -817,9 +990,7 @@ enum reg_class { NO_REGS, R1_REGS, GENER #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ (((TYPE) != 0) \ - ? ((TYPE_ALIGN(TYPE) <= PARM_BOUNDARY) \ - ? PARM_BOUNDARY \ - : TYPE_ALIGN(TYPE)) \ + ? (((int_size_in_bytes (TYPE)) + 3) / 4) * BITS_PER_WORD \ : ((GET_MODE_ALIGNMENT(MODE) <= PARM_BOUNDARY) \ ? PARM_BOUNDARY \ : GET_MODE_ALIGNMENT(MODE))) @@ -828,12 +999,16 @@ enum reg_class { NO_REGS, R1_REGS, GENER #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ ((TYPE) && int_size_in_bytes (TYPE) > 8) + +#define FUNCTION_ARG_CALLEE_COPIES(CUM, MODE, TYPE, NAMED) \ + ((TYPE) && int_size_in_bytes (TYPE) > 8) + extern struct rtx_def *hppa_compare_op0, *hppa_compare_op1; extern enum cmp_type hppa_branch_type; /* Output the label for a function definition. */ -#ifdef HP_FP_ARG_DESCRIPTOR_REVERSED +#ifndef HP_FP_ARG_DESCRIPTOR_REVERSED #define ASM_DOUBLE_ARG_DESCRIPTORS(FILE, ARG0, ARG1) \ do { fprintf (FILE, ",ARGW%d=FR", (ARG0)); \ fprintf (FILE, ",ARGW%d=FU", (ARG1));} while (0) @@ -848,16 +1023,33 @@ extern enum cmp_type hppa_branch_type; tree tree_type = TREE_TYPE (DECL); \ tree parm; \ int i; \ - if (TREE_PUBLIC (DECL)) \ + if (TREE_PUBLIC (DECL) || TARGET_GAS) \ { extern int current_function_varargs; \ - fputs ("\t.EXPORT ", FILE); assemble_name (FILE, NAME); \ - fputs (",ENTRY,PRIV_LEV=3", FILE); \ + if (TREE_PUBLIC (DECL)) \ + { \ + fputs ("\t.EXPORT ", FILE); \ + assemble_name (FILE, NAME); \ + fputs (",ENTRY,PRIV_LEV=3", FILE); \ + } \ + else \ + { \ + fputs ("\t.PARAM ", FILE); \ + assemble_name (FILE, NAME); \ + } \ + if (TARGET_PORTABLE_RUNTIME) \ + { \ + fputs (",ARGW0=NO,ARGW1=NO,ARGW2=NO,ARGW3=NO,", FILE); \ + fputs ("RTNVAL=NO\n", FILE); \ + break; \ + } \ for (parm = DECL_ARGUMENTS (DECL), i = 0; parm && i < 4; \ parm = TREE_CHAIN (parm)) \ { \ - if (TYPE_MODE (DECL_ARG_TYPE (parm)) == SFmode) \ + if (TYPE_MODE (DECL_ARG_TYPE (parm)) == SFmode \ + && ! TARGET_SOFT_FLOAT) \ fprintf (FILE, ",ARGW%d=FR", i++); \ - else if (TYPE_MODE (DECL_ARG_TYPE (parm)) == DFmode) \ + else if (TYPE_MODE (DECL_ARG_TYPE (parm)) == DFmode \ + && ! TARGET_SOFT_FLOAT) \ { \ if (i <= 2) \ { \ @@ -872,6 +1064,11 @@ extern enum cmp_type hppa_branch_type; int arg_size = \ FUNCTION_ARG_SIZE (TYPE_MODE (DECL_ARG_TYPE (parm)),\ DECL_ARG_TYPE (parm)); \ + /* Passing structs by invisible reference uses \ + one general register. */ \ + if (arg_size > 2 \ + || TREE_ADDRESSABLE (DECL_ARG_TYPE (parm)))\ + arg_size = 1; \ if (arg_size == 2 && i <= 2) \ { \ if (i == 1) i++; \ @@ -893,15 +1090,14 @@ extern enum cmp_type hppa_branch_type; for (; i < 4; i++) \ fprintf (FILE, ",ARGW%d=GR", i); \ } \ - if (TYPE_MODE (fntype) == DFmode) \ + if (TYPE_MODE (fntype) == DFmode && ! TARGET_SOFT_FLOAT) \ fprintf (FILE, ",RTNVAL=FR"); \ - else if (TYPE_MODE (fntype) == SFmode) \ + else if (TYPE_MODE (fntype) == SFmode && ! TARGET_SOFT_FLOAT) \ fprintf (FILE, ",RTNVAL=FU"); \ else if (fntype != void_type_node) \ fprintf (FILE, ",RTNVAL=GR"); \ fputs ("\n", FILE); \ - } \ - ASM_OUTPUT_LABEL (FILE, NAME);} while (0) + }} while (0) /* This macro generates the assembly code for function entry. FILE is a stdio stream to output the code to. @@ -972,30 +1168,36 @@ extern union tree_node *current_function This code template is copied from text segment to stack location and then patched with INITIALIZE_TRAMPOLINE to contain - valid values, and then entered as a subroutine. + valid values, and then entered as a subroutine. - It is best to keep this as small as possible to avoid having to + It is best to keep this as small as possible to avoid having to flush multiple lines in the cache. */ #define TRAMPOLINE_TEMPLATE(FILE) \ -{ \ - fprintf (FILE, "\tldw 12(0,%%r22),%%r21\n"); \ - fprintf (FILE, "\tbe 0(4,%%r21)\n"); \ - fprintf (FILE, "\tldw 16(0,%%r22),%%r29\n"); \ - fprintf (FILE, "\t.word 0\n"); \ - fprintf (FILE, "\t.word 0\n"); \ -} + { \ + fprintf (FILE, "\tldw 36(0,%%r22),%%r21\n"); \ + fprintf (FILE, "\tbb,>=,n %%r21,30,.+16\n"); \ + fprintf (FILE, "\tdepi 0,31,2,%%r21\n"); \ + fprintf (FILE, "\tldw 4(0,%%r21),%%r19\n"); \ + fprintf (FILE, "\tldw 0(0,%%r21),%%r21\n"); \ + fprintf (FILE, "\tldsid (0,%%r21),%%r1\n"); \ + fprintf (FILE, "\tmtsp %%r1,%%sr0\n"); \ + fprintf (FILE, "\tbe 0(%%sr0,%%r21)\n"); \ + fprintf (FILE, "\tldw 40(0,%%r22),%%r29\n"); \ + fprintf (FILE, "\t.word 0\n"); \ + fprintf (FILE, "\t.word 0\n"); \ + } /* Length in units of the trampoline for entering a nested function. Flush the cache entries corresponding to the first and last addresses of the trampoline. This is necessary as the trampoline may cross two - cache lines. + cache lines. - If the trampoline ever grows to > 32 bytes, then it will become - necessary to hack on the cacheflush pattern in pa.md. */ + If the code part of the trampoline ever grows to > 32 bytes, then it + will become necessary to hack on the cacheflush pattern in pa.md. */ -#define TRAMPOLINE_SIZE (5 * 4) +#define TRAMPOLINE_SIZE (11 * 4) /* Emit RTL insns to initialize the variable parts of a trampoline. FNADDR is an RTX for the address of the function's pure code. @@ -1005,18 +1207,21 @@ extern union tree_node *current_function Move the static chain value to trampoline template at offset 16. */ #define INITIALIZE_TRAMPOLINE(TRAMP, FNADDR, CXT) \ -{ \ - rtx start_addr, end_addr, mem; \ - \ - start_addr = memory_address (Pmode, plus_constant ((TRAMP), 12));\ - emit_move_insn (gen_rtx (MEM, Pmode, start_addr), (FNADDR)); \ - start_addr = memory_address (Pmode, plus_constant ((TRAMP), 16));\ - emit_move_insn (gen_rtx (MEM, Pmode, start_addr), (CXT)); \ - /* fdc and fic only use registers for the address to flush, \ - they do not accept integer displacements. */ \ - start_addr = force_reg (SImode, (TRAMP)); \ - end_addr = force_reg (SImode, plus_constant ((TRAMP), 8)); \ - emit_insn (gen_cacheflush (start_addr, end_addr)); \ +{ \ + rtx start_addr, end_addr; \ + \ + start_addr = memory_address (Pmode, plus_constant ((TRAMP), 36)); \ + emit_move_insn (gen_rtx (MEM, Pmode, start_addr), (FNADDR)); \ + start_addr = memory_address (Pmode, plus_constant ((TRAMP), 40)); \ + emit_move_insn (gen_rtx (MEM, Pmode, start_addr), (CXT)); \ + /* fdc and fic only use registers for the address to flush, \ + they do not accept integer displacements. */ \ + start_addr = force_reg (SImode, (TRAMP)); \ + end_addr = force_reg (SImode, plus_constant ((TRAMP), 32)); \ + emit_insn (gen_dcacheflush (start_addr, end_addr)); \ + end_addr = force_reg (SImode, plus_constant (start_addr, 32)); \ + emit_insn (gen_icacheflush (start_addr, end_addr, start_addr, \ + gen_reg_rtx (SImode), gen_reg_rtx (SImode)));\ } /* Emit code for a call to builtin_saveregs. We must emit USE insns which @@ -1024,7 +1229,8 @@ extern union tree_node *current_function Ordinarily they are not call used registers, but they are for _builtin_saveregs, so we must make this explicit. */ -#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) (rtx)hppa_builtin_saveregs (ARGLIST) +extern struct rtx_def *hppa_builtin_saveregs (); +#define EXPAND_BUILTIN_SAVEREGS(ARGLIST) hppa_builtin_saveregs (ARGLIST) /* Addressing modes, and classification of registers for them. */ @@ -1048,8 +1254,7 @@ extern union tree_node *current_function #define REGNO_OK_FOR_BASE_P(REGNO) \ ((REGNO) && ((REGNO) < 32 || (unsigned) reg_renumber[REGNO] < 32)) #define REGNO_OK_FOR_FP_P(REGNO) \ - (((REGNO) >= 32 && (REGNO) <= 99)\ - || (reg_renumber[REGNO] >= 32 && reg_renumber[REGNO] <= 99)) + (FP_REGNO_P (REGNO) || FP_REGNO_P (reg_renumber[REGNO])) /* Now macros that check whether X is a register and also, strictly, whether it is in a specified class. @@ -1078,16 +1283,14 @@ extern union tree_node *current_function && (reload_in_progress || reload_completed || ! symbolic_expression_p (X))) /* Include all constant integers and constant doubles, but not - floating-point, except for floating-point zero. + floating-point, except for floating-point zero. */ - Also reject function labels as reload can not handle them correctly - right now. (Fix this for 2.5). */ #define LEGITIMATE_CONSTANT_P(X) \ ((GET_MODE_CLASS (GET_MODE (X)) != MODE_FLOAT \ || (X) == CONST0_RTX (GET_MODE (X))) \ - && ! function_label_operand (X, VOIDmode)) + && !(flag_pic && function_label_operand (X, VOIDmode))) -/* Subroutine for EXTRA_CONSTRAINT. +/* Subroutine for EXTRA_CONSTRAINT. Return 1 iff OP is a pseudo which did not get a hard register and we are running the reload pass. */ @@ -1107,12 +1310,12 @@ extern union tree_node *current_function constrain_operands to fail. Also note `Q' accepts any memory operand during the reload pass. - This includes out-of-range displacements in reg+d addressing. + This includes out-of-range displacements in reg+d addressing. This makes for better code. (??? For 2.5 address this issue). `R' is unused. - `S' handles constraints for calls. + `S' is unused. `T' is for fp loads and stores. */ #define EXTRA_CONSTRAINT(OP, C) \ @@ -1127,15 +1330,7 @@ extern union tree_node *current_function (GET_CODE (OP) == MEM \ /* Using DFmode forces only short displacements \ to be recognized as valid in reg+d addresses. */\ - && memory_address_p (DFmode, XEXP (OP, 0))) \ - : ((C) == 'S' ? \ - ((CONSTANT_P (OP) && ! TARGET_LONG_CALLS) \ - || (reload_in_progress \ - ? strict_memory_address_p (Pmode, OP) \ - : memory_address_p (Pmode, OP)) \ - || (reload_in_progress \ - && GET_CODE (OP) == REG \ - && reg_renumber[REGNO (OP)] > 0)) : 0))) + && memory_address_p (DFmode, XEXP (OP, 0))) : 0)) /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx and check its validity for a certain class. @@ -1179,7 +1374,11 @@ extern union tree_node *current_function REG+REG, REG+(REG*SCALE) or REG+SMALLINT. But we can treat a SYMBOL_REF as legitimate if it is part of this function's constant-pool, because such addresses can actually - be output as REG+SMALLINT. */ + be output as REG+SMALLINT. + + Note we only allow 5 bit immediates for access to a constant address; + doing so avoids losing for loading/storing a FP register at an address + which will not fit in 5 bits. */ #define VAL_5_BITS_P(X) ((unsigned)(X) + 0x10 < 0x20) #define INT_5_BITS(X) VAL_5_BITS_P (INTVAL (X)) @@ -1210,9 +1409,7 @@ extern union tree_node *current_function && REG_OK_FOR_BASE_P (XEXP (X, 1))) \ goto ADDR; \ else if (flag_pic == 1 \ - && GET_CODE (XEXP (X, 1)) != REG \ - && GET_CODE (XEXP (X, 1)) != LO_SUM \ - && GET_CODE (XEXP (X, 1)) != MEM) \ + && GET_CODE (XEXP (X, 1)) == SYMBOL_REF)\ goto ADDR; \ } \ else if (REG_P (XEXP (X, 0)) \ @@ -1223,7 +1420,9 @@ extern union tree_node *current_function base = XEXP (X, 1), index = XEXP (X, 0); \ if (base != 0) \ if (GET_CODE (index) == CONST_INT \ - && ((INT_14_BITS (index) && (MODE) != SFmode && (MODE) != DFmode) \ + && ((INT_14_BITS (index) \ + && (TARGET_SOFT_FLOAT \ + || ((MODE) != SFmode && (MODE) != DFmode))) \ || INT_5_BITS (index))) \ goto ADDR; \ } \ @@ -1231,20 +1430,28 @@ extern union tree_node *current_function && GET_CODE (XEXP (X, 0)) == REG \ && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ && CONSTANT_P (XEXP (X, 1)) \ - && (MODE) != SFmode \ - && (MODE) != DFmode) \ + && (TARGET_SOFT_FLOAT \ + || ((MODE) != SFmode \ + && (MODE) != DFmode))) \ goto ADDR; \ else if (GET_CODE (X) == LO_SUM \ && GET_CODE (XEXP (X, 0)) == SUBREG \ && GET_CODE (SUBREG_REG (XEXP (X, 0))) == REG\ && REG_OK_FOR_BASE_P (SUBREG_REG (XEXP (X, 0)))\ && CONSTANT_P (XEXP (X, 1)) \ - && (MODE) != SFmode \ - && (MODE) != DFmode) \ + && (TARGET_SOFT_FLOAT \ + || ((MODE) != SFmode \ + && (MODE) != DFmode))) \ goto ADDR; \ else if (GET_CODE (X) == LABEL_REF \ || (GET_CODE (X) == CONST_INT \ - && INT_14_BITS (X))) \ + && INT_5_BITS (X))) \ + goto ADDR; \ + /* Needed for -fPIC */ \ + else if (GET_CODE (X) == LO_SUM \ + && GET_CODE (XEXP (X, 0)) == REG \ + && REG_OK_FOR_BASE_P (XEXP (X, 0)) \ + && GET_CODE (XEXP (X, 1)) == UNSPEC) \ goto ADDR; \ } @@ -1317,11 +1524,11 @@ do \ _rtl = TREE_CST_RTL (DECL); \ SYMBOL_REF_FLAG (XEXP (_rtl, 0)) = 1; \ if (TREE_CODE (DECL) == FUNCTION_DECL) \ - hppa_encode_label (XEXP (DECL_RTL (DECL), 0));\ + hppa_encode_label (XEXP (DECL_RTL (DECL), 0), 0);\ } \ } \ while (0) - + /* Store the user-specified part of SYMBOL_NAME in VAR. This is sort of inverse to ENCODE_SECTION_INFO. */ @@ -1330,9 +1537,20 @@ while (0) 1 + (SYMBOL_NAME)[1] == '@'\ : (SYMBOL_NAME)[0] == '@')) +/* Arghh. This is used for stuff in the constant pool; this may include + function addresses on the PA, which during PIC code generation must + reside in the data space. Unfortunately, there's no way to determine + if a particular label in the constant pool refers to a function address. + So just force everything into the data space during PIC generation. */ +#define SELECT_RTX_SECTION(RTX,MODE) \ + if (flag_pic) \ + data_section (); \ + else \ + readonly_data_section (); + /* Specify the machine mode that this machine uses for the index in the tablejump instruction. */ -#define CASE_VECTOR_MODE SImode +#define CASE_VECTOR_MODE DImode /* Define this if the tablejump instruction expects the table to contain offsets from the address of the table. @@ -1353,9 +1571,15 @@ while (0) in one reasonably fast instruction. */ #define MOVE_MAX 8 -/* Define if normal loads of shorter-than-word items from memory clears - the rest of the bigs in the register. */ -#define BYTE_LOADS_ZERO_EXTEND +/* Define if operations between registers always perform the operation + on the full register even if a narrower mode is specified. */ +#define WORD_REGISTER_OPERATIONS + +/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD + will either zero-extend or sign-extend. The value of this macro should + be the code that says which one of the two operations is implicitly + done, NIL if none. */ +#define LOAD_EXTEND_OP(MODE) ZERO_EXTEND /* Nonzero if access to memory by bytes is slow and undesirable. */ #define SLOW_BYTE_ACCESS 1 @@ -1400,16 +1624,16 @@ while (0) is a byte address (for indexing purposes) so give the MEM rtx a byte's mode. */ #define FUNCTION_MODE SImode - + /* Define this if addresses of constant functions shouldn't be put through pseudo regs where they can be cse'd. Desirable on machines where ordinary constants are expensive but a CALL with constant address is cheap. */ #define NO_FUNCTION_CSE -/* Define this if shift instructions ignore all but the low-order +/* Define this to be nonzero if shift instructions ignore all but the low-order few bits. */ -#define SHIFT_COUNT_TRUNCATED +#define SHIFT_COUNT_TRUNCATED 1 /* Use atexit for static constructors/destructors, instead of defining our own exit function. */ @@ -1443,14 +1667,15 @@ while (0) /* Compute extra cost of moving data between one register class and another. - Make moves from SAR so expensive they should never happen. + Make moves from SAR so expensive they should never happen. We used to + have 0xffff here, but that generates overflow in rare cases. - Copies involving a FP register and a non-FP register are relatively + Copies involving a FP register and a non-FP register are relatively expensive because they must go through memory. Other copies are reasonably cheap. */ #define REGISTER_MOVE_COST(CLASS1, CLASS2) \ - (CLASS1 == SHIFT_REGS ? 0xffff \ + (CLASS1 == SHIFT_REGS ? 0x100 \ : FP_REG_CLASS_P (CLASS1) && ! FP_REG_CLASS_P (CLASS2) ? 16 \ : FP_REG_CLASS_P (CLASS2) && ! FP_REG_CLASS_P (CLASS1) ? 16 \ : 2) @@ -1460,17 +1685,22 @@ while (0) switch on CODE. The purpose for the cost of MULT is to encourage `synth_mult' to find a synthetic multiply when reasonable. */ -#define RTX_COSTS(X,CODE,OUTER_CODE) \ - case MULT: \ - return TARGET_SNAKE && ! TARGET_DISABLE_FPREGS \ - ? COSTS_N_INSNS (8) : COSTS_N_INSNS (20); \ - case DIV: \ - case UDIV: \ - case MOD: \ - case UMOD: \ - return COSTS_N_INSNS (60); \ - case PLUS: /* this includes shNadd insns */ \ - return COSTS_N_INSNS (1) + 2; +#define RTX_COSTS(X,CODE,OUTER_CODE) \ + case MULT: \ + return (TARGET_SNAKE && ! TARGET_DISABLE_FPREGS \ + && ! TARGET_SOFT_FLOAT \ + ? COSTS_N_INSNS (8) : COSTS_N_INSNS (20)); \ + case DIV: \ + case UDIV: \ + case MOD: \ + case UMOD: \ + return COSTS_N_INSNS (60); \ + case PLUS: \ + if (GET_CODE (XEXP (X, 0)) == MULT \ + && shadd_operand (XEXP (XEXP (X, 0), 1), VOIDmode)) \ + return (2 + rtx_cost (XEXP (XEXP (X, 0), 0), OUTER_CODE) \ + + rtx_cost (XEXP (X, 1), OUTER_CODE)); \ + break; /* Adjust the cost of dependencies. */ @@ -1493,8 +1723,8 @@ while (0) are expected to clobber their arguments, %r1, %r29, and %r31 and nothing else. - These macros tell reorg that the references to arguments and - register clobbers for millicode calls do not appear to happen + These macros tell reorg that the references to arguments and + register clobbers for millicode calls do not appear to happen until after the millicode call. This allows reorg to put insns which set the argument registers into the delay slot of the millicode call -- thus they act more like traditional CALL_INSNs. @@ -1514,7 +1744,7 @@ while (0) && GET_CODE (PATTERN (X)) != SEQUENCE \ && GET_CODE (PATTERN (X)) != USE \ && GET_CODE (PATTERN (X)) != CLOBBER \ - && get_attr_type (X) == TYPE_MILLI)) + && get_attr_type (X) == TYPE_MILLI)) /* Control the assembler format that we output. */ @@ -1532,6 +1762,8 @@ do { fprintf (FILE, "\t.SPACE $PRIVATE$\ \t.IMPORT $$dyncall,MILLICODE\n");\ if (profile_flag)\ fprintf (FILE, "\t.IMPORT _mcount, CODE\n");\ + if (write_symbols != NO_DEBUG) \ + output_file_directive ((FILE), main_input_filename); \ } while (0) /* Output to assembler file text saying following lines @@ -1552,6 +1784,13 @@ do { fprintf (FILE, "\t.SPACE $PRIVATE$\ /* Supposedly the assembler rejects the command if there is no tab! */ #define TEXT_SECTION_ASM_OP "\t.SPACE $TEXT$\n\t.SUBSPA $CODE$\n" +/* Output before read-only data. */ + +/* Supposedly the assembler rejects the command if there is no tab! */ +#define READONLY_DATA_ASM_OP "\t.SPACE $TEXT$\n\t.SUBSPA $LIT$\n" + +#define READONLY_DATA_SECTION readonly_data + /* Output before writable data. */ /* Supposedly the assembler rejects the command if there is no tab! */ @@ -1563,7 +1802,20 @@ do { fprintf (FILE, "\t.SPACE $PRIVATE$\ /* Define the .bss section for ASM_OUTPUT_LOCAL to use. */ -#define EXTRA_SECTIONS in_bss +#define EXTRA_SECTIONS in_bss, in_readonly_data + +/* FIXME: HPUX ld generates incorrect GOT entries for "T" fixups + which reference data within the $TEXT$ space (for example constant + strings in the $LIT$ subspace). + + The assemblers (GAS and HP as) both have problems with handling + the difference of two symbols which is the other correct way to + reference constant data during PIC code generation. + + So, there's no way to reference constant data which is in the + $TEXT$ space during PIC generation. Instead place all constant + data into the $PRIVATE$ subspace (this reduces sharing, but it + works correctly). */ #define EXTRA_SECTION_FUNCTIONS \ void \ @@ -1574,6 +1826,18 @@ bss_section () \ fprintf (asm_out_file, "%s\n", BSS_SECTION_ASM_OP); \ in_section = in_bss; \ } \ +} \ +void \ +readonly_data () \ +{ \ + if (in_section != in_readonly_data) \ + { \ + if (flag_pic) \ + fprintf (asm_out_file, "%s\n", DATA_SECTION_ASM_OP); \ + else \ + fprintf (asm_out_file, "%s\n", READONLY_DATA_ASM_OP); \ + in_section = in_readonly_data; \ + } \ } @@ -1581,32 +1845,46 @@ bss_section () \ This sequence is indexed by compiler's hard-register-number (see above). */ #define REGISTER_NAMES \ -{"0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ - "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ - "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \ - "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \ - "%fr4", "%fr5", "%fr6", "%fr7", \ - "%fr8", "%fr9", "%fr10", "%fr11", "%fr12", "%fr13", "%fr14", "%fr15", \ - "%fr4", "%fr4R", "%fr5", "%fr5R", "%fr6", "%fr6R", "%fr7", "%fr7R", \ - "%fr8", "%fr8R", "%fr9", "%fr9R", "%fr10", "%fr10R", "%fr11", "%fr11R",\ - "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R",\ - "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R",\ - "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R",\ - "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R",\ - "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R",\ +{"%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ + "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ + "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23", \ + "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31", \ + "%fr4", "%fr4R", "%fr5", "%fr5R", "%fr6", "%fr6R", "%fr7", "%fr7R", \ + "%fr8", "%fr8R", "%fr9", "%fr9R", "%fr10", "%fr10R", "%fr11", "%fr11R", \ + "%fr12", "%fr12R", "%fr13", "%fr13R", "%fr14", "%fr14R", "%fr15", "%fr15R", \ + "%fr16", "%fr16R", "%fr17", "%fr17R", "%fr18", "%fr18R", "%fr19", "%fr19R", \ + "%fr20", "%fr20R", "%fr21", "%fr21R", "%fr22", "%fr22R", "%fr23", "%fr23R", \ + "%fr24", "%fr24R", "%fr25", "%fr25R", "%fr26", "%fr26R", "%fr27", "%fr27R", \ + "%fr28", "%fr28R", "%fr29", "%fr29R", "%fr30", "%fr30R", "%fr31", "%fr31R", \ "SAR"} -/* How to renumber registers for dbx and gdb. */ - -#define DBX_REGISTER_NUMBER(REGNO) (REGNO) +#define ADDITIONAL_REGISTER_NAMES \ +{{"%fr4L",32}, {"%fr5L",34}, {"%fr6L",36}, {"%fr7L",38}, \ + {"%fr8L",40}, {"%fr9L",42}, {"%fr10L",44}, {"%fr11L",46}, \ + {"%fr12L",48}, {"%fr13L",50}, {"%fr14L",52}, {"%fr15L",54}, \ + {"%fr16L",56}, {"%fr17L",58}, {"%fr18L",60}, {"%fr19L",62}, \ + {"%fr20L",64}, {"%fr21L",66}, {"%fr22L",68}, {"%fr23L",70}, \ + {"%fr24L",72}, {"%fr25L",74}, {"%fr26L",76}, {"%fr27L",78}, \ + {"%fr28L",80}, {"%fr29L",82}, {"%fr30L",84}, {"%fr31R",86}, \ + {"%cr11",88}} + +/* How to renumber registers for dbx and gdb. + + Registers 0 - 31 remain unchanged. + + Registers 32 - 87 are mapped to 72 - 127 + + Register 88 is mapped to 32. */ + +#define DBX_REGISTER_NUMBER(REGNO) \ + ((REGNO) <= 31 ? (REGNO) : \ + ((REGNO) > 31 && (REGNO) <= 87 ? (REGNO) + 40 : 32)) /* This is how to output the definition of a user-level label named NAME, such as the label on a static function or variable NAME. */ #define ASM_OUTPUT_LABEL(FILE, NAME) \ do { assemble_name (FILE, NAME); \ - if (TARGET_TRAILING_COLON) \ - fputc (':', FILE); \ fputc ('\n', FILE); } while (0) /* This is how to output a command to make the user-level label named NAME @@ -1621,35 +1899,33 @@ bss_section () \ fputs (",DATA\n", FILE); \ } while (0) -/* hpux ld doesn't output the object file name, or anything useful at - all, to indicate the start of an object file's symbols. This screws - up gdb, so we'll output this magic cookie at the end of an object - file with debugging symbols */ - -#define ASM_FILE_END(FILE) \ - do { if (write_symbols == DBX_DEBUG)\ - { fputs (TEXT_SECTION_ASM_OP, FILE);\ - fputs (".stabs \"end_file.\",4,0,0,Ltext_end\nLtext_end:\n",\ - (FILE));\ - }\ - } while (0) - -/* The bogus HP assembler requires ALL external references to be +/* The bogus HP assembler requires ALL external references to be "imported", even library calls. They look a bit different, so - here's this macro. */ + here's this macro. + + Also note not all libcall names are passed to ENCODE_SECTION_INFO + (__main for example). To make sure all libcall names have section + info recorded in them, we do it here. */ #define ASM_OUTPUT_EXTERNAL_LIBCALL(FILE, RTL) \ do { fputs ("\t.IMPORT ", FILE); \ + if (!function_label_operand (RTL, VOIDmode)) \ + hppa_encode_label (RTL, 1); \ assemble_name (FILE, XSTR ((RTL), 0)); \ fputs (",CODE\n", FILE); \ } while (0) #define ASM_GLOBALIZE_LABEL(FILE, NAME) \ - do { fputs ("\t.EXPORT ", FILE); assemble_name (FILE, NAME); \ - if (FUNCTION_NAME_P (NAME)) \ - fputs (",CODE\n", FILE); \ - else \ - fputs (",DATA\n", FILE);} while (0) + do { \ + /* We only handle DATA objects here, functions are globalized in \ + ASM_DECLARE_FUNCTION_NAME. */ \ + if (! FUNCTION_NAME_P (NAME)) \ + { \ + fputs ("\t.EXPORT ", FILE); \ + assemble_name (FILE, NAME); \ + fputs (",DATA\n", FILE); \ + } \ + } while (0) /* This is how to output a reference to a user-level label named NAME. `assemble_name' uses this. */ @@ -1661,11 +1937,7 @@ bss_section () \ PREFIX is the class of label and NUM is the number within the class. */ #define ASM_OUTPUT_INTERNAL_LABEL(FILE,PREFIX,NUM) \ - {fprintf (FILE, "%s$%04d", PREFIX, NUM); \ - if (TARGET_TRAILING_COLON) \ - fputs (":\n", FILE); \ - else \ - fputs ("\n", FILE);} + {fprintf (FILE, "%c$%s%04d\n", (PREFIX)[0], (PREFIX) + 1, NUM);} /* This is how to store into the string LABEL the symbol_ref name of an internal numbered label where @@ -1673,31 +1945,30 @@ bss_section () \ This is suitable for output with `assemble_name'. */ #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ - sprintf (LABEL, "*%s$%04d", PREFIX, NUM) + sprintf (LABEL, "*%c$%s%04d", (PREFIX)[0], (PREFIX) + 1, NUM) /* This is how to output an assembler line defining a `double' constant. */ #define ASM_OUTPUT_DOUBLE(FILE,VALUE) \ - do { union { double d; int i[2];} __u; \ - __u.d = (VALUE); \ - fprintf (FILE, "\t; .double %.20e\n\t.word %d ; = 0x%x\n\t.word %d ; = 0x%x\n", \ - __u.d, __u.i[0], __u.i[0], __u.i[1], __u.i[1]); \ - } while (0) + do { long l[2]; \ + REAL_VALUE_TO_TARGET_DOUBLE (VALUE, l); \ + fprintf (FILE, "\t.word 0x%lx\n\t.word 0x%lx\n", l[0], l[1]); \ + } while (0) /* This is how to output an assembler line defining a `float' constant. */ #define ASM_OUTPUT_FLOAT(FILE,VALUE) \ - do { union { float f; int i;} __u; \ - __u.f = (VALUE); \ - fprintf (FILE, "\t; .float %.12e\n\t.word %d ; = 0x%x\n", __u.f, __u.i, __u.i); \ - } while (0) + do { long l; \ + REAL_VALUE_TO_TARGET_SINGLE (VALUE, l); \ + fprintf (FILE, "\t.word 0x%lx\n", l); \ + } while (0) /* This is how to output an assembler line defining an `int' constant. */ #define ASM_OUTPUT_INT(FILE,VALUE) \ { fprintf (FILE, "\t.word "); \ - if (TARGET_SHARED_LIBS \ - && function_label_operand (VALUE, VOIDmode))\ + if (function_label_operand (VALUE, VOIDmode) \ + && !TARGET_PORTABLE_RUNTIME) \ fprintf (FILE, "P%%"); \ output_addr_const (FILE, (VALUE)); \ fprintf (FILE, "\n");} @@ -1723,7 +1994,7 @@ bss_section () \ output_ascii ((FILE), (P), (SIZE)) #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) -#define ASM_OUTPUT_REG_POP(FILE,REGNO) +#define ASM_OUTPUT_REG_POP(FILE,REGNO) /* This is how to output an element of a case-vector that is absolute. Note that this method makes filling these branch delay slots impossible. */ @@ -1735,11 +2006,14 @@ bss_section () \ #define JUMP_TABLES_IN_TEXT_SECTION /* This is how to output an element of a case-vector that is relative. - (The HP-PA does not use such vectors, - but we must define this macro anyway.) */ + This must be defined correctly as it is used when generating PIC code. + + I believe it safe to use the same definition as ASM_OUTPUT_ADDR_VEC_ELT + on the PA since ASM_OUTPUT_ADDR_VEC_ELT uses pc-relative jump instructions + rather than a table of absolute addresses. */ #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, VALUE, REL) \ - fprintf (FILE, "\tword L%d-L%d\n", VALUE, REL) + fprintf (FILE, "\tb L$%04d\n\tnop\n", VALUE) /* This is how to output an assembler line that says to advance the location counter @@ -1751,31 +2025,24 @@ bss_section () \ #define ASM_OUTPUT_SKIP(FILE,SIZE) \ fprintf (FILE, "\t.blockz %d\n", (SIZE)) -/* This says how to output an assembler line - to define a global common symbol. */ - -/* Supposedly the assembler rejects the command if there is no tab! */ - +/* This says how to output an assembler line to define a global common symbol + with size SIZE (in bytes) and alignment ALIGN (in bits). */ -#define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ -{ bss_section (); \ - assemble_name ((FILE), (NAME)); \ - if (TARGET_TRAILING_COLON) \ - fputc (':', (FILE)); \ - fputs ("\t.comm ", (FILE)); \ - fprintf ((FILE), "%d\n", (ROUNDED));} - -/* This says how to output an assembler line - to define a local common symbol. */ - -#define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ -{ bss_section (); \ - fprintf ((FILE), "\t.align %d\n", (SIZE) <= 4 ? 4 : 8); \ +#define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGNED) \ +{ bss_section (); \ + assemble_name ((FILE), (NAME)); \ + fputs ("\t.comm ", (FILE)); \ + fprintf ((FILE), "%d\n", MAX ((SIZE), ((ALIGNED) / BITS_PER_UNIT)));} + +/* This says how to output an assembler line to define a local common symbol + with size SIZE (in bytes) and alignment ALIGN (in bits). */ + +#define ASM_OUTPUT_ALIGNED_LOCAL(FILE, NAME, SIZE, ALIGNED) \ +{ bss_section (); \ + fprintf ((FILE), "\t.align %d\n", ((ALIGNED) / BITS_PER_UNIT)); \ assemble_name ((FILE), (NAME)); \ - if (TARGET_TRAILING_COLON) \ - fputc (':', (FILE)); \ - fprintf ((FILE), "\n\t.block %d\n", (ROUNDED));} - + fprintf ((FILE), "\n\t.block %d\n", (SIZE));} + /* Store in OUTPUT a string (made with alloca) containing an assembler-name for a local static variable named NAME. LABELNO is an integer which is different for each call. */ @@ -1790,6 +2057,9 @@ bss_section () \ #define ASM_OPEN_PAREN "(" #define ASM_CLOSE_PAREN ")" +/* All HP assemblers use "!" to separate logical lines. */ +#define IS_ASM_LOGICAL_LINE_SEPARATOR(C) ((C) == '!') + /* Define results of standard character escape sequences. */ #define TARGET_BELL 007 #define TARGET_BS 010 @@ -1840,7 +2110,14 @@ bss_section () \ fprintf (FILE, "%d(0,%s)", offset, reg_names [REGNO (base)]); \ break; \ case LO_SUM: \ - fputs ("R'", FILE); \ + if (!symbolic_operand (XEXP (addr, 1))) \ + fputs ("R'", FILE); \ + else if (flag_pic == 0) \ + fputs ("RR'", FILE); \ + else if (flag_pic == 1) \ + abort (); \ + else if (flag_pic == 2) \ + fputs ("RT'", FILE); \ output_global_address (FILE, XEXP (addr, 1)); \ fputs ("(", FILE); \ output_operand (XEXP (addr, 0), 0); \ @@ -1861,12 +2138,12 @@ extern char *output_ior (); extern char *output_move_double (); extern char *output_fp_move_double (); extern char *output_block_move (); -extern char *output_scc_insn (); extern char *output_cbranch (); extern char *output_bb (); +extern char *output_dbra (); +extern char *output_movb (); extern char *output_return (); -extern char *output_floatsisf2 (); -extern char *output_floatsidf2 (); +extern char *output_call (); extern char *output_mul_insn (); extern char *output_div_insn (); extern char *output_mod_insn (); @@ -1877,4 +2154,53 @@ extern struct rtx_def *legitimize_pic_ad extern struct rtx_def *gen_cmp_fp (); extern void hppa_encode_label (); -extern struct rtx_def *hppa_save_pic_table_rtx; +#if 0 +#define PREDICATE_CODES \ + {"reg_or_0_operand", {SUBREG, REG, CONST_INT, CONST_DOUBLE}}, \ + {"reg_or_cint_move_operand", {SUBREG, REG, CONST_INT}}, \ + {"arith_operand", {SUBREG, REG, CONST_INT}}, \ + {"arith32_operand", {SUBREG, REG, CONST_INT}}, \ + {"arith11_operand", {SUBREG, REG, CONST_INT}}, \ + {"arith5_operand", {SUBREG, REG, CONST_INT}}, \ + {"pre_cint_operand", {CONST_INT}}, \ + {"post_cint_operand", {CONST_INT}}, \ + {"int5_operand", {CONST_INT}}, \ + {"uint5_operand", {CONST_INT}}, \ + {"uint32_operand", {CONST_INT}}, \ + {"int11_operand", {CONST_INT}}, \ + {"and_operand", {SUBREG, REG, CONST_INT}}, \ + {"ior_operand", {CONST_INT}}, \ + {"lhs_lshift_operand", {SUBREG, REG, CONST_INT}}, \ + {"lhs_lshift_cint_operand", {CONST_INT}}, \ + {"plus_xor_ior_operator", {PLUS, XOR, IOR}}, \ + {"shadd_operand", {CONST_INT}}, \ + {"eq_neq_comparison_operator", {EQ, NE}}, \ + {"movb_comparison_operator", {EQ, NE, LT, GE}}, \ + {"pc_or_label_operand", {LABEL_REF, PC}}, \ + {"symbolic_operand", {SYMBOL_REF, LABEL_REF, CONST}}, \ + {"reg_or_nonsymb_mem_operand", {SUBREG, REG, MEM}}, \ + {"move_operand", {SUBREG, REG, CONST_INT, MEM}}, \ + {"pic_label_operand", {LABEL_REF, CONST}}, \ + {"function_label_operand", {SYMBOL_REF}}, \ + {"reg_or_0_or_nonsymb_mem_operand", {SUBREG, REG, CONST_INT, \ + CONST_DOUBLE, MEM}}, \ + {"div_operand", {REG, CONST_INT}}, \ + {"call_operand_address", {SYMBOL_REF, LABEL_REF, CONST_INT, \ + CONST_DOUBLE, CONST, HIGH}}, +#endif + +/* We want __gcc_plt_call to appear in every program built by + gcc, so we make a reference to it out of __main. + We use the asm statement to fool the optimizer into not + removing the dead (but important) initialization of + REFERENCE. */ + +#define DO_GLOBAL_DTORS_BODY \ +do { \ + extern void __gcc_plt_call (); \ + void (*reference)() = &__gcc_plt_call; \ + func_ptr *p; \ + __asm__ ("" : : "r" (reference)); \ + for (p = __DTOR_LIST__ + 1; *p; ) \ + (*p++) (); \ +} while (0)