--- gcc/config/pa/pa.md	2018/04/24 18:10:27	1.1
+++ gcc/config/pa/pa.md	2018/04/24 18:17:21	1.1.1.2
@@ -30,51 +30,71 @@
 ;; type "binary" insns have two input operands (1,2) and one output (0)
 
 (define_attr "type"
-  "move,unary,binary,compare,load,store,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmul,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,misc,milli"
+  "move,unary,binary,compare,load,store,uncond_branch,branch,cbranch,fbranch,call,dyncall,fpload,fpstore,fpalu,fpcc,fpmul,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl,multi,misc,milli"
   (const_string "binary"))
 
 ;; Length (in # of insns).
 (define_attr "length" ""
   (cond [(eq_attr "type" "load,fpload")
 	 (if_then_else (match_operand 1 "symbolic_memory_operand" "")
-		       (const_int 2) (const_int 1))
+		       (const_int 8) (const_int 4))
 
 	 (eq_attr "type" "store,fpstore")
 	 (if_then_else (match_operand 0 "symbolic_memory_operand" "")
-		       (const_int 2) (const_int 1))
+		       (const_int 8) (const_int 4))
 
 	 (eq_attr "type" "binary")
 	 (if_then_else (match_operand 2 "arith_operand" "")
-		       (const_int 1) (const_int 3))
+		       (const_int 4) (const_int 12))
 
 	 (eq_attr "type" "move,unary")
 	 (if_then_else (match_operand 1 "arith_operand" "")
-		       (const_int 1) (const_int 2))]
+		       (const_int 4) (const_int 8))]
 
-	(const_int 1)))
+	(const_int 4)))
 
 (define_asm_attributes
-  [(set_attr "length" "1")
+  [(set_attr "length" "4")
    (set_attr "type" "multi")])
 
 ;; Attributes for instruction and branch scheduling
 
+;; For conditional branches.
 (define_attr "in_branch_delay" "false,true"
-  (if_then_else (and (eq_attr "type" "!branch,cbranch,fbranch,call,dyncall,multi,milli")
-		     (eq_attr "length" "1"))
+  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli")
+		     (eq_attr "length" "4"))
 		(const_string "true")
 		(const_string "false")))
 
 ;; Disallow instructions which use the FPU since they will tie up the FPU
 ;; even if the instruction is nullified.
 (define_attr "in_nullified_branch_delay" "false,true"
-  (if_then_else (and (eq_attr "type" "!branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmul,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl")
-		     (eq_attr "length" "1"))
+  (if_then_else (and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli,fpcc,fpalu,fpmul,fpdivsgl,fpdivdbl,fpsqrtsgl,fpsqrtdbl")
+		     (eq_attr "length" "4"))
 		(const_string "true")
 		(const_string "false")))
 
+;; For calls and millicode calls.  Allow unconditional branches in the 
+;; delay slot.
+(define_attr "in_call_delay" "false,true"
+  (cond [(and (eq_attr "type" "!uncond_branch,branch,cbranch,fbranch,call,dyncall,multi,milli")
+	      (eq_attr "length" "4"))
+	   (const_string "true")
+	 (eq_attr "type" "uncond_branch")
+	   (if_then_else (ne (symbol_ref "TARGET_JUMP_IN_DELAY")
+			     (const_int 0))
+			 (const_string "true")
+			 (const_string "false"))]
+	(const_string "false")))
+	
+
+
 ;; Unconditional branch, call, and millicode call delay slot description.
-(define_delay (eq_attr "type" "branch,call,milli")
+(define_delay (eq_attr "type" "uncond_branch,branch,call,milli")
+  [(eq_attr "in_call_delay" "true") (nil) (nil)])
+
+;; Unconditional branch, return and other similar instructions.
+(define_delay (eq_attr "type" "uncond_branch,branch")
   [(eq_attr "in_branch_delay" "true") (nil) (nil)])
 
 ;; Floating point conditional branch delay slot description and
@@ -85,10 +105,9 @@
 
 ;; Integer conditional branch delay slot description.
 ;; Nullification of conditional branches on the PA is dependent on the
-;; direction of the branch.  Forward branches nullify true (direction > 0),
-;; and backward branches nullify false (direction < 0).
-;; If direction == 0, then the direction is unknown and we do not allow
-;; any nullification.
+;; direction of the branch.  Forward branches nullify true and
+;; backward branches nullify false.  If the direction is unknown
+;; then nullification is not allowed.
 (define_delay (eq_attr "type" "cbranch")
   [(eq_attr "in_branch_delay" "true") 
    (and (eq_attr "in_nullified_branch_delay" "true") 
@@ -364,19 +383,19 @@
   ""
   "com%I2clr,%B3 %2,%1,%0\;ldi 1,%0"
   [(set_attr "type" "binary")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 ;; Combiner patterns for common operations performed with the output
 ;; from an scc insn (negscc and incscc).  
 (define_insn "negscc"
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(neg (match_operator:SI 3 "comparison_operator"
+	(neg:SI (match_operator:SI 3 "comparison_operator"
 	       [(match_operand:SI 1 "register_operand" "r")
 		(match_operand:SI 2  "arith11_operand" "rI")])))]
   ""
   "com%I2clr,%B3 %2,%1,%0\;ldi -1,%0"
   [(set_attr "type" "binary")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 ;; Patterns for adding/subtracting the result of a boolean expression from
 ;; a register.  First we have special patterns that make use of the carry
@@ -392,7 +411,7 @@
   ""
   "sub%I3 %3,%2,0\;addc 0,%1,%0"
   [(set_attr "type" "binary")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 ; This need only accept registers for op3, since canonicalization
 ; replaces geu with gtu when op3 is an integer.
@@ -404,7 +423,7 @@
   ""
   "sub %2,%3,0\;addc 0,%1,%0"
   [(set_attr "type" "binary")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 ; Match only integers for op3 here.  This is used as canonical form of the
 ; geu pattern when op3 is an integer.  Don't match registers since we can't
@@ -417,7 +436,7 @@
   ""
   "addi %k3,%2,0\;addc 0,%1,%0"
   [(set_attr "type" "binary")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 (define_insn "incscc"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -430,7 +449,7 @@
    com%I3clr,%B4 %3,%2,0\;addi 1,%0,%0
    com%I3clr,%B4 %3,%2,0\;addi,tr 1,%1,%0\;copy %1,%0"
   [(set_attr "type" "binary,binary")
-   (set_attr "length" "2,3")])
+   (set_attr "length" "8,12")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -440,7 +459,7 @@
   ""
   "sub%I3 %3,%2,0\;subb %1,0,%0"
   [(set_attr "type" "binary")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 ; This need only accept registers for op3, since canonicalization
 ; replaces ltu with leu when op3 is an integer.
@@ -452,7 +471,7 @@
   ""
   "sub %2,%3,0\;subb %1,0,%0"
   [(set_attr "type" "binary")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 ; Match only integers for op3 here.  This is used as canonical form of the
 ; ltu pattern when op3 is an integer.  Don't match registers since we can't
@@ -465,7 +484,7 @@
   ""
   "addi %k3,%2,0\;subb %1,0,%0"
   [(set_attr "type" "binary")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 (define_insn "decscc"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -478,7 +497,7 @@
    com%I3clr,%B4 %3,%2,0\;addi -1,%0,%0
    com%I3clr,%B4 %3,%2,0\;addi,tr -1,%1,%0\;copy %1,%0"
   [(set_attr "type" "binary,binary")
-   (set_attr "length" "2,3")])
+   (set_attr "length" "8,12")])
 
 ; Patterns for max and min.  (There is no need for an earlyclobber in the
 ; last alternative since the middle alternative will match if op0 == op1.)
@@ -493,7 +512,7 @@
   comiclr,> %2,%0,0\;ldi %2,%0
   comclr,> %1,%2,%0\;copy %1,%0"
 [(set_attr "type" "multi,multi,multi")
- (set_attr "length" "2,2,2")])
+ (set_attr "length" "8,8,8")])
 
 (define_insn "uminsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -504,7 +523,7 @@
   comclr,>> %2,%0,0\;copy %2,%0
   comiclr,>> %2,%0,0\;ldi %2,%0"
 [(set_attr "type" "multi,multi")
- (set_attr "length" "2,2")])
+ (set_attr "length" "8,8")])
 
 (define_insn "smaxsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,r,r")
@@ -516,7 +535,7 @@
   comiclr,< %2,%0,0\;ldi %2,%0
   comclr,< %1,%2,%0\;copy %1,%0"
 [(set_attr "type" "multi,multi,multi")
- (set_attr "length" "2,2,2")])
+ (set_attr "length" "8,8,8")])
 
 (define_insn "umaxsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -527,7 +546,7 @@
   comclr,<< %2,%0,0\;copy %2,%0
   comiclr,<< %2,%0,0\;ldi %2,%0"
 [(set_attr "type" "multi,multi")
- (set_attr "length" "2,2")])
+ (set_attr "length" "8,8")])
 ;;; Experimental conditional move patterns
 
 ; We need the first constraint alternative in order to avoid
@@ -548,7 +567,7 @@
    com%I4clr,%B5 %4,%3,%0\;ldil L'%1,%0
    com%I4clr,%B5 %4,%3,%0\;zdepi %Z1,%0"
   [(set_attr "type" "multi,multi,multi,multi,multi")
-   (set_attr "length" "2,2,2,2,2")])
+   (set_attr "length" "8,8,8,8,8")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
@@ -569,7 +588,7 @@
    com%I4clr,%B5 %4,%3,0\;ldil L'%1,%0
    com%I4clr,%B5 %4,%3,0\;zdepi %Z1,%0"
   [(set_attr "type" "multi,multi,multi,multi,multi,multi,multi,multi")
-   (set_attr "length" "2,2,2,2,2,2,2,2")])
+   (set_attr "length" "8,8,8,8,8,8,8,8")])
 
 ;; Conditional Branches
 
@@ -743,7 +762,7 @@
 
 
 ;; Note a long backward conditional branch with an annulled delay slot
-;; has a length of 3.  
+;; has a length of 12.  
 (define_insn ""
   [(set (pc)
 	(if_then_else
@@ -760,14 +779,10 @@
 }"
 [(set_attr "type" "cbranch")
  (set (attr "length") 
-    (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 2))))
-		      (const_int 1023))
-           (const_int 1)
-	   (and (lt (match_dup 0) (pc))
-		(eq (symbol_ref "INSN_ANNULLED_BRANCH_P (insn)")
-		    (const_int 1)))
-	   (const_int 3)]
-	  (const_int 2)))])
+    (if_then_else (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
+		      (const_int 8188))
+           (const_int 4)
+	   (const_int 8)))])
 
 ;; Match the negated branch.
 
@@ -787,14 +802,10 @@
 }"
 [(set_attr "type" "cbranch")
  (set (attr "length") 
-    (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 2))))
-		      (const_int 1023))
-           (const_int 1)
-	   (and (lt (match_dup 0) (pc))
-		(eq (symbol_ref "INSN_ANNULLED_BRANCH_P (insn)")
-		    (const_int 1)))
-	   (const_int 3)]
-	  (const_int 2)))])
+    (if_then_else (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
+		      (const_int 8188))
+           (const_int 4)
+	   (const_int 8)))])
 
 ;; Branch on Bit patterns.
 (define_insn ""
@@ -816,14 +827,10 @@
 }"
 [(set_attr "type" "cbranch")
  (set (attr "length") 
-    (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 2))))
-		      (const_int 1023))
-           (const_int 1)
-	   (and (lt (match_dup 0) (pc))
-		(eq (symbol_ref "INSN_ANNULLED_BRANCH_P (insn)")
-		    (const_int 1)))
-	   (const_int 3)]
-	  (const_int 2)))])
+    (if_then_else (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
+		      (const_int 8188))
+           (const_int 4)
+	   (const_int 8)))])
 
 (define_insn ""
   [(set (pc)
@@ -844,17 +851,12 @@
 }"
 [(set_attr "type" "cbranch")
  (set (attr "length") 
-    (cond [(lt (abs (minus (match_dup 0) (plus (pc) (const_int 2))))
-		      (const_int 1023))
-           (const_int 1)
-	   (and (lt (match_dup 0) (pc))
-		(eq (symbol_ref "INSN_ANNULLED_BRANCH_P (insn)")
-		    (const_int 1)))
-	   (const_int 3)]
-	  (const_int 2)))])
+    (if_then_else (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
+		      (const_int 8188))
+           (const_int 4)
+	   (const_int 8)))])
 
 ;; Floating point branches
-
 (define_insn ""
   [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
 			   (label_ref (match_operand 0 "" ""))
@@ -868,7 +870,7 @@
     return \"ftest\;bl%* %0,0\";
 }"
   [(set_attr "type" "fbranch")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (pc) (if_then_else (ne (reg:CCFP 0) (const_int 0))
@@ -883,7 +885,7 @@
     return \"ftest\;add,tr 0,0,0\;bl%* %0,0\";
 }"
   [(set_attr "type" "fbranch")
-   (set_attr "length" "3")])
+   (set_attr "length" "12")])
 
 ;; Move instructions
 
@@ -939,7 +941,7 @@
   "flag_pic && operands[1] == pic_offset_table_rtx"
   "ldw T'%2(%1),%0"
   [(set_attr "type" "load")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "reg_or_nonsymb_mem_operand" 
@@ -960,7 +962,7 @@
    fldws%F1 %1,%0
    fstws%F0 %1,%0"
   [(set_attr "type" "move,move,move,move,load,store,move,fpalu,fpload,fpstore")
-   (set_attr "length" "1,1,1,1,1,1,1,1,1,1")])
+   (set_attr "length" "4,4,4,4,4,4,4,4,4,4")])
 
 ;; Load indexed.  We don't use unscaled modes since they can't be used
 ;; unless we can tell which of the registers is the base and which is
@@ -975,7 +977,28 @@
   "! TARGET_DISABLE_INDEXING"
   "ldwx,s %1(0,%2),%0"
   [(set_attr "type" "load")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
+
+;; This variant of the above insn can occur if the second operand
+;; is the frame pointer.  This is a kludge, but there doesn't
+;; seem to be a way around it.  Only recognize it while reloading.
+(define_insn ""
+  [(set (match_operand:SI 0 "register_operand" "&=r")
+	(mem:SI (plus:SI (plus:SI 
+			    (mult:SI (match_operand:SI 1 "register_operand" "r")
+				     (const_int 4))
+			    (match_operand:SI 2 "register_operand" "r"))
+			 (match_operand:SI 3 "const_int_operand" "rI"))))]
+  "! TARGET_DISABLE_INDEXING && reload_in_progress"
+  "*
+{
+  if (GET_CODE (operands[3]) == CONST_INT)
+    return \"sh2add %1,%2,%0\;ldw %3(0,%0),%0\";
+  else
+    return \"sh2add %1,%2,%0\;ldwx %3(0,%0),%0\";
+}"
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
 ;; Load or store with base-register modification.
 
@@ -993,7 +1016,7 @@
   return \"ldws,mb %2(0,%0),%3\";
 }"
   [(set_attr "type" "load")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn "pre_stwm"
   [(set (mem:SI (plus:SI (match_operand:SI 1 "register_operand" "0")
@@ -1009,7 +1032,7 @@
   return \"stws,mb %r3,%2(0,%0)\";
 }"
   [(set_attr "type" "store")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn "post_ldwm"
   [(set (match_operand:SI 3 "register_operand" "r")
@@ -1025,7 +1048,7 @@
   return \"ldws,ma %2(0,%0),%3\";
 }"
   [(set_attr "type" "load")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn "post_stwm"
   [(set (mem:SI (match_operand:SI 1 "register_operand" "0"))
@@ -1041,7 +1064,7 @@
   return \"stws,ma %r3,%2(0,%0)\";
 }"
   [(set_attr "type" "store")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 ;; For pic
 (define_insn ""
@@ -1065,46 +1088,21 @@
   }
 "
   [(set_attr "type" "multi")
-   (set_attr "length" "3")])
+   (set_attr "length" "12")])
 
-;; For kernel code always use addil; else we can lose due to a linker
-;; bug involving absolute symbols and "ldil;add" style relocations
+;; Always use addil rather than ldil;add sequences.  This allows the
+;; HP linker to eliminate the dp relocation if the symbolic operand
+;; lives in the TEXT space.
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=a")
 	(high:SI (match_operand 1 "" "")))]
-  "TARGET_KERNEL && symbolic_operand(operands[1], Pmode)
+  "symbolic_operand(operands[1], Pmode)
    && ! function_label_operand (operands[1])
    && ! read_only_operand (operands[1])"
   "@
    addil L'%G1,%%r27"
   [(set_attr "type" "binary")
-   (set_attr "length" "1")])
-
-;; For all symbolic operands *except* function addresses and read-only
-;; operands (which live in TEXT space and do not require relocation).  
-;;
-;; The constraints are a little strange.  
-;; The basic idea is to prefer %r1 as much as possible for register 
-;; allocation (hence we do not allow regclass to know about the general
-;; register case (via *r).
-;; We also want to avoid spilling %r1 as that will cause every use
-;; of %r1 to be reloaded, so we make the %r1 case very expensive
-;; as far as reload is concerned (via !a).
-;;
-;; The real solution is to not spill all pseudos allocated to %r1
-;; when %r1 is needed as a spill register, but that is considerably
-;; more difficult than coercing decent behavior via constraints.
-(define_insn ""
-  [(set (match_operand:SI 0 "register_operand" "=!a,*r")
-	(high:SI (match_operand 1 "" "")))]
-  "! TARGET_KERNEL && symbolic_operand(operands[1], Pmode)
-   && ! function_label_operand (operands[1])
-   && ! read_only_operand (operands[1])"
-  "@
-   addil L'%G1,%%r27
-   ldil L'%G1,%0\;add %0,%%r27,%0"
-  [(set_attr "type" "binary,binary")
-   (set_attr "length" "1,2")])
+   (set_attr "length" "4")])
 
 ;; This is for use in the prologue/epilogue code.  We need it 
 ;; to add large constants to a stack pointer or frame pointer.
@@ -1120,16 +1118,16 @@
    addil L'%G2,%1
    ldil L'%G2,%0\;add %0,%1,%0"
   [(set_attr "type" "binary,binary")
-   (set_attr "length" "1,2")])
+   (set_attr "length" "4,8")])
 
-;; For function addresses when TARGET_SHARED_LIBS
+;; For function addresses.
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(high:SI (match_operand:SI 1 "function_label_operand" "")))]
-  "TARGET_SHARED_LIBS"
+  ""
   "ldil LP'%G1,%0"
   [(set_attr "type" "move")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1137,18 +1135,18 @@
   "check_pic (1)"
   "ldil L'%G1,%0"
   [(set_attr "type" "move")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
-;; lo_sum of a function address when TARGET_SHARED_LIBS
+;; lo_sum of a function address.
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
 	(lo_sum:SI (match_operand:SI 1 "register_operand" "r")
 		   (match_operand:SI 2 "function_label_operand" "")))
    (clobber (match_operand:SI 3 "register_operand" "=r"))]
-  "TARGET_SHARED_LIBS"
+  ""
   "ldo RP'%G2(%1),%0\;extru,= %0,31,1,%3\;ldw -4(0,%%r27),%3\;add %0,%3,%0"
   [(set_attr "type" "multi")
-   (set_attr "length" "4")])
+   (set_attr "length" "16")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1156,7 +1154,7 @@
 		   (match_operand:SI 2 "immediate_operand" "i")))]
   ""
   "ldo R'%G2(%1),%0"
-  [(set_attr "length" "1")])
+  [(set_attr "length" "4")])
 
 ;; Now that a symbolic_address plus a constant is broken up early
 ;; in the compilation phase (for better CSE) we need a special
@@ -1197,7 +1195,7 @@
    mtsar %r1
    fcpy,sgl %r1,%0"
   [(set_attr "type" "move,move,move,move,load,store,move,fpalu")
-   (set_attr "length" "1,1,1,1,1,1,1,1")])
+   (set_attr "length" "4,4,4,4,4,4,4,4")])
 
 (define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=r")
@@ -1207,7 +1205,28 @@
   "! TARGET_DISABLE_INDEXING"
   "ldhx,s %2(0,%1),%0"
   [(set_attr "type" "load")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
+
+;; This variant of the above insn can occur if the second operand
+;; is the frame pointer.  This is a kludge, but there doesn't
+;; seem to be a way around it.  Only recognize it while reloading.
+(define_insn ""
+  [(set (match_operand:HI 0 "register_operand" "=&r")
+	(mem:HI (plus:SI (plus:SI 
+			    (mult:SI (match_operand:SI 2 "register_operand" "r")
+				     (const_int 2))
+			    (match_operand:SI 1 "register_operand" "r"))
+			 (match_operand:SI 3 "const_int_operand" "rI"))))]
+  "! TARGET_DISABLE_INDEXING && reload_in_progress"
+  "*
+{
+  if (GET_CODE (operands[3]) == CONST_INT)
+    return \"sh1add %2,%1,%0\;ldh %3(0,%0),%0\";
+  else
+    return \"sh1add %2,%1,%0\;ldhx %3(0,%0),%0\";
+}"
+  [(set_attr "type" "load")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:HI 3 "register_operand" "=r")
@@ -1218,7 +1237,7 @@
   ""
   "ldhs,mb %2(0,%0),%3"
   [(set_attr "type" "load")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn ""
   [(set (mem:HI (plus:SI (match_operand:SI 1 "register_operand" "0")
@@ -1229,7 +1248,7 @@
   ""
   "sths,mb %r3,%2(0,%0)"
   [(set_attr "type" "store")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=r")
@@ -1237,7 +1256,7 @@
   "check_pic (1)"
   "ldil L'%G1,%0"
   [(set_attr "type" "move")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn ""
   [(set (match_operand:HI 0 "register_operand" "=r")
@@ -1245,7 +1264,7 @@
 		   (match_operand 2 "immediate_operand" "i")))]
   ""
   "ldo R'%G2(%1),%0"
-  [(set_attr "length" "1")])
+  [(set_attr "length" "4")])
 
 (define_expand "movqi"
   [(set (match_operand:QI 0 "general_operand" "")
@@ -1272,7 +1291,7 @@
    mtsar %r1
    fcpy,sgl %r1,%0"
   [(set_attr "type" "move,move,move,move,load,store,move,fpalu")
-   (set_attr "length" "1,1,1,1,1,1,1,1")])
+   (set_attr "length" "4,4,4,4,4,4,4,4")])
 
 (define_insn ""
   [(set (match_operand:QI 3 "register_operand" "=r")
@@ -1283,7 +1302,7 @@
   ""
   "ldbs,mb %2(0,%0),%3"
   [(set_attr "type" "load")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn ""
   [(set (mem:QI (plus:SI (match_operand:SI 1 "register_operand" "0")
@@ -1294,7 +1313,7 @@
   ""
   "stbs,mb %r3,%2(0,%0)"
   [(set_attr "type" "store")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 ;; The definition of this insn does not really explain what it does,
 ;; but it should suffice
@@ -1364,7 +1383,7 @@
   "* return (which_alternative == 0 ? output_move_double (operands)
 				    : \" fldds%F1 %1,%0\");"
   [(set_attr "type" "move,fpload")
-   (set_attr "length" "4,1")])
+   (set_attr "length" "16,4")])
 
 (define_expand "movdf"
   [(set (match_operand:DF 0 "general_operand" "")
@@ -1378,9 +1397,9 @@
 
 (define_insn ""
   [(set (match_operand:DF 0 "reg_or_nonsymb_mem_operand"
-			  "=fx,*r,Q,?Q,fx,*&r")
+			  "=fx,*r,Q,?o,?Q,fx,*&r,*&r")
 	(match_operand:DF 1 "reg_or_0_or_nonsymb_mem_operand"
-			  "fxG,*rG,fx,*r,Q,Q"))]
+			  "fxG,*rG,fx,*r,*r,Q,o,Q"))]
   "register_operand (operands[0], DFmode)
    || reg_or_0_operand (operands[1], DFmode)"
   "*
@@ -1390,8 +1409,8 @@
     return output_fp_move_double (operands);
   return output_move_double (operands);
 }"
-  [(set_attr "type" "fpalu,move,fpstore,store,fpload,load")
-   (set_attr "length" "1,2,1,2,1,2")])
+  [(set_attr "type" "fpalu,move,fpstore,store,store,fpload,load,load")
+   (set_attr "length" "4,8,4,8,16,4,8,16")])
 
 (define_insn ""
   [(set (match_operand:DF 0 "register_operand" "=fx")
@@ -1401,7 +1420,31 @@
   "! TARGET_DISABLE_INDEXING"
   "flddx,s %1(0,%2),%0"
   [(set_attr "type" "fpload")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
+
+;; This variant of the above insn can occur if the second operand
+;; is the frame pointer.  This is a kludge, but there doesn't
+;; seem to be a way around it.  Only recognize it while reloading.
+;; Ugh. Output is a FP register; so we need to earlyclobber something
+;; else as a temporary. 
+(define_insn ""
+  [(set (match_operand:DF 0 "register_operand" "=fx")
+	(mem:DF (plus:SI 
+		  (plus:SI 
+		    (mult:SI (match_operand:SI 1 "register_operand" "+&r")
+			     (const_int 8))
+		    (match_operand:SI 2 "register_operand" "r"))
+		  (match_operand:SI 3 "const_int_operand" "rL"))))]
+  "! TARGET_DISABLE_INDEXING && reload_in_progress"
+  "*
+{
+  if (GET_CODE (operands[3]) == CONST_INT)
+    return \"sh3add %1,%2,%1\;fldds %3(0,%1),%0\";
+  else
+    return \"sh3add %1,%2,%1\;flddx %3(0,%1),%0\";
+}"
+  [(set_attr "type" "fpload")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (mem:DF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
@@ -1411,7 +1454,31 @@
   "! TARGET_DISABLE_INDEXING"
   "fstdx,s %0,%1(0,%2)"
   [(set_attr "type" "fpstore")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
+
+;; This variant of the above insn can occur if the second operand
+;; is the frame pointer.  This is a kludge, but there doesn't
+;; seem to be a way around it.  Only recognize it while reloading.
+;; Ugh. Output is a FP register; so we need to earlyclobber something
+;; else as a temporary. 
+(define_insn ""
+  [(set (mem:DF (plus:SI 
+		  (plus:SI 
+		     (mult:SI (match_operand:SI 1 "register_operand" "+&r")
+			      (const_int 8))
+		     (match_operand:SI 2 "register_operand" "r"))
+		  (match_operand:SI 3 "const_int_operand" "rL")))
+	(match_operand:DF 0 "register_operand" "=fx"))]
+  "! TARGET_DISABLE_INDEXING && reload_in_progress"
+  "*
+{
+  if (GET_CODE (operands[3]) == CONST_INT)
+    return \"sh3add %1,%2,%1\;fstds %3(0,%1),%0\";
+  else
+    return \"sh3add %1,%2,%1\;fstdx %3(0,%1),%0\";
+}"
+  [(set_attr "type" "fpstore")
+   (set_attr "length" "8")])
 
 (define_expand "movdi"
   [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand" "")
@@ -1489,15 +1556,15 @@
     abort ();
 }"
   [(set_attr "type" "move")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 ;;; Experimental
 
 (define_insn ""
   [(set (match_operand:DI 0 "reg_or_nonsymb_mem_operand"
-			  "=r,Q,&r,&r,x,x,*T")
+			  "=r,o,Q,&r,&r,&r,x,x,*T")
 	(match_operand:DI 1 "general_operand"
-			  "rM,r,Q,i,xM,*T,x"))]
+			  "rM,r,r,o,Q,i,xM,*T,x"))]
   "register_operand (operands[0], DImode)
    || reg_or_0_operand (operands[1], DImode)"
   "*
@@ -1507,8 +1574,8 @@
     return output_fp_move_double (operands);
   return output_move_double (operands);
 }"
-  [(set_attr "type" "move,store,load,misc,fpalu,fpload,fpstore")
-   (set_attr "length" "2,3,3,3,1,1,1")])
+  [(set_attr "type" "move,store,store,load,load,misc,fpalu,fpload,fpstore")
+   (set_attr "length" "8,8,16,8,16,16,4,4,4")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r,r")
@@ -1527,7 +1594,7 @@
 }"
   ;; Need to set length for this arith insn because operand2
   ;; is not an "arith_operand".
-  [(set_attr "length" "1,2")])
+  [(set_attr "length" "4,8")])
 
 ;; This pattern forces (set (reg:SF ...) (const_double ...))
 ;; to be reloaded by putting the constant into memory when
@@ -1546,7 +1613,7 @@
   "* return (which_alternative == 0 ? singlemove_string (operands)
 				    : \" fldws%F1 %1,%0\");"
   [(set_attr "type" "move,fpload")
-   (set_attr "length" "2,1")])
+   (set_attr "length" "8,4")])
 
 (define_expand "movsf"
   [(set (match_operand:SF 0 "general_operand" "")
@@ -1573,7 +1640,7 @@
    fstws%F0 %r1,%0
    stw%M0 %r1,%0"
   [(set_attr "type" "fpalu,move,fpload,load,fpstore,store")
-   (set_attr "length" "1,1,1,1,1,1")])
+   (set_attr "length" "4,4,4,4,4,4")])
 
 (define_insn ""
   [(set (match_operand:SF 0 "register_operand" "=fx")
@@ -1583,7 +1650,31 @@
   "! TARGET_DISABLE_INDEXING"
   "fldwx,s %1(0,%2),%0"
   [(set_attr "type" "fpload")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
+
+;; This variant of the above insn can occur if the second operand
+;; is the frame pointer.  This is a kludge, but there doesn't
+;; seem to be a way around it.  Only recognize it while reloading.
+;; Ugh. Output is a FP register; so we need to earlyclobber something
+;; else as a temporary. 
+(define_insn ""
+  [(set (match_operand:SF 0 "register_operand" "=fx")
+	(mem:SF (plus:SI 
+		  (plus:SI 
+		    (mult:SI (match_operand:SI 1 "register_operand" "+&r")
+			     (const_int 4))
+		    (match_operand:SI 2 "register_operand" "r"))
+		  (match_operand:SI 3 "const_int_operand" "rL"))))]
+  "! TARGET_DISABLE_INDEXING && reload_in_progress"
+  "*
+{
+  if (GET_CODE (operands[3]) == CONST_INT)
+    return \"sh2add %1,%2,%1\;fldws %3(0,%1),%0\";
+  else
+    return \"sh2add %1,%2,%1\;fldwx %3(0,%1),%0\";
+}"
+  [(set_attr "type" "fpload")
+   (set_attr "length" "8")])
 
 (define_insn ""
   [(set (mem:SF (plus:SI (mult:SI (match_operand:SI 1 "register_operand" "r")
@@ -1593,7 +1684,31 @@
   "! TARGET_DISABLE_INDEXING"
   "fstwx,s %0,%1(0,%2)"
   [(set_attr "type" "fpstore")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
+
+;; This variant of the above insn can occur if the second operand
+;; is the frame pointer.  This is a kludge, but there doesn't
+;; seem to be a way around it.  Only recognize it while reloading.
+;; Ugh. Output is a FP register; so we need to earlyclobber something
+;; else as a temporary. 
+(define_insn ""
+  [(set (mem:SF (plus:SI 
+		  (plus:SI 
+		     (mult:SI (match_operand:SI 1 "register_operand" "+&r")
+			      (const_int 4))
+		     (match_operand:SI 2 "register_operand" "r"))
+		  (match_operand:SI 3 "const_int_operand" "rL")))
+	(match_operand:SF 0 "register_operand" "=fx"))]
+  "! TARGET_DISABLE_INDEXING && reload_in_progress"
+  "*
+{
+  if (GET_CODE (operands[3]) == CONST_INT)
+    return \"sh2add %1,%2,%1\;fstds %3(0,%1),%0\";
+  else
+    return \"sh2add %1,%2,%1\;fstdx %3(0,%1),%0\";
+}"
+  [(set_attr "type" "fpstore")
+   (set_attr "length" "8")])
 
 ;;- zero extension instructions
 
@@ -1615,8 +1730,7 @@
   "@
    extru %1,31,8,%0
    ldb%M1 %1,%0"
-  [(set_attr "type" "unary,load")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "unary,load")])
 
 (define_insn "zero_extendqisi2"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -1626,8 +1740,7 @@
   "@
    extru %1,31,8,%0
    ldb%M1 %1,%0"
-  [(set_attr "type" "unary,load")
-   (set_attr "length" "1,1")])
+  [(set_attr "type" "unary,load")])
 
 ;;- sign extension instructions
 
@@ -1687,15 +1800,14 @@
   ""
   "fldws %1,%0\;fcnvxf,sgl,sgl %0,%0"
   [(set_attr "type" "fpalu")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 (define_insn "floatsisf2"
   [(set (match_operand:SF 0 "general_operand" "=fx")
 	(float:SF (match_operand:SI 1 "register_operand" "fx")))]
   ""
   "fcnvxf,sgl,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpalu")])
 
 ;; This pattern forces (set (reg:DF ...) (float:DF (const_int ...)))
 ;; to be reloaded by putting the constant into memory.
@@ -1706,15 +1818,14 @@
   ""
   "fldws %1,%0\;fcnvxf,sgl,dbl %0,%0"
   [(set_attr "type" "fpalu")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 (define_insn "floatsidf2"
   [(set (match_operand:DF 0 "general_operand" "=fx")
 	(float:DF (match_operand:SI 1 "register_operand" "fx")))]
   ""
   "fcnvxf,sgl,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpalu")])
 
 (define_expand "floatunssisf2"
   [(set (subreg:SI (match_dup 2) 1)
@@ -1741,16 +1852,14 @@
 	(float:SF (match_operand:DI 1 "register_operand" "x")))]
   "TARGET_SNAKE"
   "fcnvxf,dbl,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpalu")])
 
 (define_insn "floatdidf2"
   [(set (match_operand:DF 0 "general_operand" "=x")
 	(float:DF (match_operand:DI 1 "register_operand" "x")))]
   "TARGET_SNAKE"
   "fcnvxf,dbl,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpalu")])
 
 ;; Convert a float to an actual integer.
 ;; Truncation is performed as part of the conversion.
@@ -1760,32 +1869,28 @@
 	(fix:SI (fix:SF (match_operand:SF 1 "register_operand" "fx"))))]
   ""
   "fcnvfxt,sgl,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpalu")])
 
 (define_insn "fix_truncdfsi2"
   [(set (match_operand:SI 0 "register_operand" "=fx")
 	(fix:SI (fix:DF (match_operand:DF 1 "register_operand" "fx"))))]
   ""
   "fcnvfxt,dbl,sgl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpalu")])
 
 (define_insn "fix_truncsfdi2"
   [(set (match_operand:DI 0 "register_operand" "=x")
 	(fix:DI (fix:SF (match_operand:SF 1 "register_operand" "x"))))]
   "TARGET_SNAKE"
   "fcnvfxt,sgl,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpalu")])
 
 (define_insn "fix_truncdfdi2"
   [(set (match_operand:DI 0 "register_operand" "=x")
 	(fix:DI (fix:DF (match_operand:DF 1 "register_operand" "x"))))]
   "TARGET_SNAKE"
   "fcnvfxt,dbl,dbl %1,%0"
-  [(set_attr "type" "fpalu")
-   (set_attr "length" "1")])
+  [(set_attr "type" "fpalu")])
 
 ;;- arithmetic instructions
 
@@ -1806,7 +1911,7 @@
   else
     return \"add %R2,%R1,%R0\;addc %2,%1,%0\";
 }"
-  [(set_attr "length" "2")])
+  [(set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -1886,7 +1991,7 @@
 		  (match_operand:DI 2 "register_operand" "r")))]
   ""
   "sub %R1,%R2,%R0\;subb %1,%2,%0"
-  [(set_attr "length" "2")])
+  [(set_attr "length" "8")])
 
 (define_insn "subsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -1943,7 +2048,7 @@
    (clobber (reg:SI 25))
    (clobber (reg:SI 31))]
   ""
-  "* return output_mul_insn (0);"
+  "* return output_mul_insn (0, insn);"
   [(set_attr "type" "milli")])
 
 ;;; Division and mod.
@@ -1989,7 +2094,7 @@
    (clobber (reg:SI 31))]
  ""
  "*
- return output_div_insn (operands, 0);"
+ return output_div_insn (operands, 0, insn);"
  [(set_attr "type" "milli")])
 
 (define_expand "udivsi3"
@@ -2034,7 +2139,7 @@
    (clobber (reg:SI 31))]
  ""
  "*
- return output_div_insn (operands, 1);"
+ return output_div_insn (operands, 1, insn);"
  [(set_attr "type" "milli")])
 
 (define_expand "modsi3"
@@ -2075,7 +2180,7 @@
    (clobber (reg:SI 31))]
   ""
   "*
-  return output_mod_insn (0);"
+  return output_mod_insn (0, insn);"
   [(set_attr "type" "milli")])
 
 (define_expand "umodsi3"
@@ -2116,7 +2221,7 @@
    (clobber (reg:SI 31))]
   ""
   "*
-  return output_mod_insn (1);"
+  return output_mod_insn (1, insn);"
   [(set_attr "type" "milli")])
 
 ;;- and instructions
@@ -2142,7 +2247,7 @@
 		(match_operand:DI 2 "register_operand" "r")))]
   ""
   "and %1,%2,%0\;and %R1,%R2,%R0"
-  [(set_attr "length" "2")])
+  [(set_attr "length" "8")])
 
 (define_insn "andsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -2151,7 +2256,7 @@
   ""
   "* return output_and (operands); "
   [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn ""
   [(set (match_operand:DI 0 "register_operand" "=r")
@@ -2159,7 +2264,7 @@
 		(match_operand:DI 2 "register_operand" "r")))]
   ""
   "andcm %2,%1,%0\;andcm %R2,%R1,%R0"
-  [(set_attr "length" "2")])
+  [(set_attr "length" "8")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2187,7 +2292,7 @@
 		(match_operand:DI 2 "register_operand" "r")))]
   ""
   "or %1,%2,%0\;or %R1,%R2,%R0"
-  [(set_attr "length" "2")])
+  [(set_attr "length" "8")])
 
 ;; Need a define_expand because we've run out of CONST_OK... characters.
 (define_expand "iorsi3"
@@ -2208,7 +2313,7 @@
   ""
   "* return output_ior (operands); "
   [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2236,7 +2341,7 @@
 		(match_operand:DI 2 "register_operand" "r")))]
   ""
   "xor %1,%2,%0\;xor %R1,%R2,%R0"
-  [(set_attr "length" "2")])
+  [(set_attr "length" "8")])
 
 (define_insn "xorsi3"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2251,7 +2356,7 @@
   ""
   "sub 0,%R1,%R0\;subb 0,%1,%0"
   [(set_attr "type" "unary")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 (define_insn "negsi2"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2276,7 +2381,7 @@
   ""
   "uaddcm 0,%1,%0\;uaddcm 0,%R1,%R0"
   [(set_attr "type" "unary")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 (define_insn "one_cmplsi2"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2404,7 +2509,7 @@
   ""
   "ldb%M1 %1,%0"
   [(set_attr "type" "load")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2413,7 +2518,7 @@
   ""
   "ldh%M1 %1,%0"
   [(set_attr "type" "load")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2425,7 +2530,7 @@
 
 ;; This variant of the above insn can occur if the first operand
 ;; is the frame pointer.  This is a kludge, but there doesn't
-;; seem to be a way around it.  Only recognize them while reloading.
+;; seem to be a way around it.  Only recognize it while reloading.
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=&r")
@@ -2436,7 +2541,7 @@
   "reload_in_progress"
   "sh%O4add %2,%1,%0\;add%I3 %3,%0,%0"
   [(set_attr "type" "multi")
-   (set_attr "length" "2")])
+   (set_attr "length" "8")])
 
 (define_expand "ashlsi3"
   [(set (match_operand:SI 0 "register_operand" "")
@@ -2467,7 +2572,7 @@
   ""
   "zdep %1,%P2,%L2,%0"
   [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 ; Match cases of op1 a CONST_INT here that zvdep_imm doesn't handle.
 ; Doing it like this makes slightly better code since reload can
@@ -2522,7 +2627,7 @@
   ""
   "extrs %1,%P2,%L2,%0"
   [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn "vextrs32"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2541,7 +2646,7 @@
    vshd 0,%1,%0
    extru %1,%P2,%L2,%0"
   [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn "rotrsi3"
   [(set (match_operand:SI 0 "register_operand" "=r,r")
@@ -2559,7 +2664,7 @@
     return \"vshd %1,%1,%0\";
 }"
   [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn "rotlsi3"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2572,7 +2677,7 @@
   return \"shd %1,%1,%2,%0\";
 }"
   [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2584,7 +2689,7 @@
   "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
   "shd %1,%2,%4,%0"
   [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2596,7 +2701,7 @@
   "INTVAL (operands[3]) + INTVAL (operands[4]) == 32"
   "shd %1,%2,%4,%0"
   [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -2612,7 +2717,7 @@
   return \"zdep %1,%2,%3,%0\";
 }"
   [(set_attr "type" "binary")
-   (set_attr "length" "1")])
+   (set_attr "length" "4")])
 
 ;; Unconditional and other jump instructions.
 
@@ -2661,7 +2766,7 @@
    (use (match_operand:SI 0 "const_int_operand" ""))]
   ""
   "bl _mcount,%%r2\;ldo %0(%%r2),%%r25"
-  [(set_attr "length" "2")])
+  [(set_attr "length" "8")])
 
 (define_insn "blockage"
   [(unspec_volatile [(const_int 2)] 0)]
@@ -2673,7 +2778,17 @@
   [(set (pc) (label_ref (match_operand 0 "" "")))]
   ""
   "bl%* %l0,0"
-  [(set_attr "type" "branch")])
+  [(set_attr "type" "uncond_branch")
+   (set (attr "length")
+    (cond [(eq (symbol_ref "jump_in_call_delay (insn)") (const_int 0))
+	   (const_int 4)
+;; If the jump is in the delay slot of a call, then its length depends 
+;; on whether or not we can add the proper offset to %r2 with an ldo
+;; instruction.
+	   (lt (abs (minus (match_dup 0) (plus (pc) (const_int 8))))
+		    (const_int 8188))
+           (const_int 4)]
+	  (const_int 8)))])
 
 ;; Subroutines of "casesi".
 ;; operand 0 is index
@@ -2735,7 +2850,7 @@
       return \"sub,>> %0,%1,0\;blr,n %0,0\;b,n %l3\";
     }
 }"
- [(set_attr "length" "3")])
+ [(set_attr "length" "12")])
 
 ;; Need nops for the calls because execution is supposed to continue
 ;; past; we don't want to nullify an instruction that we need.
@@ -2754,7 +2869,17 @@
     op = force_reg (SImode, XEXP (operands[0], 0));
   else
     op = XEXP (operands[0], 0);
-  emit_call_insn (gen_call_internal (op, operands[1]));
+
+  /* Use two different patterns for calls to explicitly named functions
+     and calls through function pointers.  This is necessary as these two
+     types of calls use different calling conventions, and CSE might try
+     to change the named call into an indirect call in some cases (using
+     two patterns keeps CSE from performing this optimization).  */
+  if (GET_CODE (op) == SYMBOL_REF)
+    emit_call_insn (gen_call_internal_symref (op, operands[1]));
+  else
+    emit_call_insn (gen_call_internal_reg (op, operands[1]));
+
   if (flag_pic)
     {
       if (!hppa_save_pic_table_rtx)
@@ -2765,23 +2890,29 @@
   DONE;
 }")
 
-(define_insn "call_internal"
- [(call (mem:SI (match_operand:SI 0 "call_operand_address" "r,S"))
-	(match_operand 1 "" "i,i"))
-  (clobber (reg:SI 2))]
- ""
+(define_insn "call_internal_symref"
+ [(call (mem:SI (match_operand:SI 0 "call_operand_address" ""))
+	(match_operand 1 "" "i"))
+  (clobber (reg:SI 2))
+  (use (const_int 0))]
+ "! TARGET_LONG_CALLS"
  "*
 {
-  if (which_alternative == 0)
-    return \"copy %0,22\;.CALL\\tARGW0=GR\;bl $$dyncall,31\;copy 31,2\";
-  else
-    {
-      output_arg_descriptor (insn);
-      return \"bl %0,2%#\";
-    }
+  output_arg_descriptor (insn);
+  return output_call (insn, operands[0], gen_rtx (REG, SImode, 2));
 }"
- [(set_attr "type" "dyncall,call")
-  (set_attr "length" "3,1")])
+ [(set_attr "type" "call")
+  (set_attr "length" "4")])
+
+(define_insn "call_internal_reg"
+ [(call (mem:SI (match_operand:SI 0 "register_operand" "r"))
+	(match_operand 1 "" "i"))
+  (clobber (reg:SI 2))
+  (use (const_int 1))]
+ ""
+ "copy %r0,%%r22\;.CALL\\tARGW0=GR\;bl $$dyncall,%%r31\;copy %%r31,%%r2"
+ [(set_attr "type" "dyncall")
+  (set_attr "length" "12")])
 
 (define_expand "call_value"
   [(parallel [(set (match_operand 0 "" "")
@@ -2798,7 +2929,18 @@
     op = force_reg (SImode, XEXP (operands[1], 0));
   else
     op = XEXP (operands[1], 0);
-  emit_call_insn (gen_call_value_internal (operands[0], op, operands[2]));
+
+  /* Use two different patterns for calls to explicitly named functions
+     and calls through function pointers.  This is necessary as these two
+     types of calls use different calling conventions, and CSE might try
+     to change the named call into an indirect call in some cases (using
+     two patterns keeps CSE from performing this optimization).  */
+  if (GET_CODE (op) == SYMBOL_REF)
+    emit_call_insn (gen_call_value_internal_symref (operands[0], op,
+						    operands[2]));
+  else
+    emit_call_insn (gen_call_value_internal_reg (operands[0], op, operands[2]));
+
   if (flag_pic)
     {
       if (!hppa_save_pic_table_rtx)
@@ -2809,26 +2951,62 @@
   DONE;
 }")
 
-(define_insn "call_value_internal"
-  [(set (match_operand 0 "" "=rfx,rfx")
-	(call (mem:SI (match_operand:SI 1 "call_operand_address" "r,S"))
-	      (match_operand 2 "" "i,i")))
-   (clobber (reg:SI 2))]
+(define_insn "call_value_internal_symref"
+  [(set (match_operand 0 "" "=rfx")
+	(call (mem:SI (match_operand:SI 1 "call_operand_address" ""))
+	      (match_operand 2 "" "i")))
+   (clobber (reg:SI 2))
+   (use (const_int 0))]
   ;;- Don't use operand 1 for most machines.
-  ""
+  "! TARGET_LONG_CALLS"
   "*
 {
-  if (which_alternative == 0)
-    return \"copy %1,22\;.CALL\\tARGW0=GR\;bl $$dyncall,31\;copy 31,2\";
-  else
+  output_arg_descriptor (insn);
+  return output_call (insn, operands[1], gen_rtx (REG, SImode, 2));
+}"
+ [(set_attr "type" "call")
+  (set_attr "length" "4")])
+
+(define_insn "call_value_internal_reg"
+  [(set (match_operand 0 "" "=rfx")
+	(call (mem:SI (match_operand:SI 1 "register_operand" "r"))
+	      (match_operand 2 "" "i")))
+   (clobber (reg:SI 2))
+   (use (const_int 1))]
+  ;;- Don't use operand 1 for most machines.
+  ""
+  "copy %r1,%%r22\;.CALL\\tARGW0=GR\;bl $$dyncall,%%r31\;copy %%r31,%%r2"
+ [(set_attr "type" "dyncall")
+  (set_attr "length" "12")])
+
+;; Call subroutine returning any type.
+
+(define_expand "untyped_call"
+  [(parallel [(call (match_operand 0 "" "")
+		    (const_int 0))
+	      (match_operand 1 "" "")
+	      (match_operand 2 "" "")])]
+  ""
+  "
+{
+  int i;
+
+  emit_call_insn (gen_call (operands[0], const0_rtx));
+
+  for (i = 0; i < XVECLEN (operands[2], 0); i++)
     {
-      output_arg_descriptor (insn);
-      return \"bl %1,2%#\";
+      rtx set = XVECEXP (operands[2], 0, i);
+      emit_move_insn (SET_DEST (set), SET_SRC (set));
     }
-}"
- [(set_attr "type" "dyncall,call")
-  (set_attr "length" "3,1")])
 
+  /* The optimizer does not know that the call sets the function value
+     registers we stored in the result block.  We avoid problems by
+     claiming that all hard registers are used and clobbered at this
+     point.  */
+  emit_insn (gen_blockage ());
+
+  DONE;
+}")
 (define_insn "nop"
   [(const_int 0)]
   ""
@@ -2881,7 +3059,6 @@
   return \"depi %3,%2+%1-1,%1,%0\";
 }")
 
-;; The dbra pattern from hell.  
 ;; This insn is used for some loop tests, typically loops reversed when
 ;; strength reduction is used.  It is actually created when the instruction
 ;; combination phase combines the special loop test.  Since this insn
@@ -2892,113 +3069,202 @@
   [(set (pc)
 	(if_then_else
 	  (match_operator 2 "comparison_operator"
-	   [(plus:SI (match_operand:SI 0 "register_operand" "+!r,m")
-		     (match_operand:SI 1 "int5_operand" "L,L"))
+	   [(plus:SI (match_operand:SI 0 "register_operand" "+!r,!*f*x,!*m")
+		     (match_operand:SI 1 "int5_operand" "L,L,L"))
 	    (const_int 0)])
 	  (label_ref (match_operand 3 "" ""))
 	  (pc)))
    (set (match_dup 0)
 	(plus:SI (match_dup 0) (match_dup 1)))
-   (clobber (match_scratch:SI 4 "=X,r"))]
-  "0"
-"*
-{
-  if (INSN_ANNULLED_BRANCH_P (insn))
-    {
-      /* Loop counter is in a register.  */
-      if (which_alternative == 0)
-	/* Short branch.  Normal handling of nullification.  */
-        if (get_attr_length (insn) == 1)
-          return \"addib,%C2,n %1,%0,%3\";
-	/* Long Conditional branch forward with delay slot nullified if
-	   branch is taken.  */
-        else if (get_attr_length (insn) == 2)
-          return \"addi,%N2 %1,%0,%0\;bl,n %3,0\";
-	/* Long Conditional branch backwards with delay slot nullified
-	   if branch is not taken.  */
-        else
-          return \"addib,%N2 %1,%0,.+16\;nop\;bl %3,0\";
-      else
-        {
-	  /* Must reload loop counter from memory.  Ugly.  */
-          output_asm_insn (\"ldw %0,%4\;ldo %1(%4),%4\;stw %4,%0\", operands);
-	  /* Short branch.  Normal handling of nullification.  */
-          if (get_attr_length (insn) == 4)
-	    return \"comb,%S2,n 0,%4,%3\";
-	  /* Long Conditional branch forward with delay slot nullified if
-	     branch is taken.  */
-          else if (get_attr_length (insn) == 5)
-	    return \"comclr,%B2 0,%4,0\;bl,n %3,0\";
-	  else 
-	  /* Long Conditional branch backwards with delay slot nullified
-	     if branch is not taken.  */
-	    return \"comb,%B2 0,%4,.+16\;nop\;bl %3,0\";
-        }
-    }
-  else
-    {
-      /* We are not nullifying the delay slot.  Much simpler.  */
-      if (which_alternative == 0)
-        if (get_attr_length (insn) == 1)
-	  /* Short form.  */
-          return \"addib,%C2 %1,%0,%3%#\";
-        else
-	  /* Long form.  */
-          return \"addi,%N2 %1,%0,%0\;bl%* %3,0\";
-      else
-        {
-	  /* Reload loop counter from memory.  */
-          output_asm_insn (\"ldw %0,%4\;ldo %1(%4),%4\;stw %4,%0\", operands);
-	  /* Short form.  */
-          if (get_attr_length (insn) == 4)
-	    return \"comb,%S2 0,%4,%3%#\";
-	  /* Long form.  */
-          else
-	    return \"comclr,%B2 0,%4,0\;bl%* %3,0\";
-        }
-    }
-}"
+   (clobber (match_scratch:SI 4 "=X,r,r"))]
+  ""
+  "* return output_dbra (operands, insn, which_alternative); "
 ;; Do not expect to understand this the first time through.  
-[(set_attr "type" "cbranch")
+[(set_attr "type" "cbranch,multi,multi")
  (set (attr "length")
-      (if_then_else 
-	(eq_attr "alternative" "0")
-;; Loop counter in register case.
-	(cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 2))))
-		   (const_int 1023))
-;; Short branch has a length of 1.
-	       (const_int 1)
-;; Long backward branch with nullified delay slot has length of 3.
-	       (and (lt (match_dup 1) (pc))
-		    (eq (symbol_ref "INSN_ANNULLED_BRANCH_P (insn)")
-			(const_int 1)))
-	       (const_int 3)]
-;; Default others to 2.
-;; Long branches with unfilled delay slots  --or--
-;; Long forward with nullified delay slot.
-	      (const_int 2))
-;; Loop counter in memory case.   Similar to above except we pay
-;; 3 extra insns in each case for reloading the counter into a register.
-	(if_then_else (lt (match_dup 1) (pc))
-	  (cond [(lt (abs (minus (match_dup 1) (plus (pc) (const_int 5))))
-		     (const_int 1023))
-;; Short branch has length of 4 (the reloading costs 3 insns)
-		 (const_int 4)
-		 (and (lt (match_dup 1) (pc))
-		      (eq (symbol_ref "INSN_ANNULLED_BRANCH_P (insn)")
-			  (const_int 1)))
-;; Long backward branch with nullified delay slot has length of 6.
-		 (const_int 6)]
-;; Default others to 5.
-;; Long branches with unfilled delay slots  --or--
-;; Long forward with nullified delay slot.
-		(const_int 5))
-	  (if_then_else (lt (abs (minus (match_dup 1) 
-					(plus (pc) (const_int 2))))
-			    (const_int 1023))
-			(const_int 4)
-			(const_int 5)))))])
+      (if_then_else (eq_attr "alternative" "0")
+;; Loop counter in register case
+;; Short branch has length of 4
+;; Long branch has length of 8
+	(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
+		      (const_int 8188))
+           (const_int 4)
+	   (const_int 8))
+
+;; Loop counter in FP reg case.
+;; Extra goo to deal with additional reload insns.
+	(if_then_else (eq_attr "alternative" "1")
+	  (if_then_else (lt (match_dup 3) (pc))
+	    (if_then_else 
+	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
+		  (const_int 8188))
+	      (const_int 24)
+	      (const_int 28))
+	    (if_then_else 
+	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
+		  (const_int 8188))
+	      (const_int 24)
+	      (const_int 28)))
+;; Loop counter in memory case.
+;; Extra goo to deal with additional reload insns.
+	(if_then_else (lt (match_dup 3) (pc))
+	  (if_then_else 
+	    (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
+		(const_int 8188))
+	    (const_int 12)
+	    (const_int 16))
+	  (if_then_else 
+	    (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
+		(const_int 8188))
+	    (const_int 12)
+	    (const_int 16))))))])
+
+;; Simply another variant of the dbra pattern.  More restrictive 
+;; in testing the comparison operator as it must worry about overflow
+;; problems.
+(define_insn ""
+  [(set (pc)
+	(if_then_else
+	  (match_operator 2 "eq_neq_comparison_operator"
+	   [(match_operand:SI 0 "register_operand" "+!r,!*f*x,!*m")
+	    (match_operand:SI 5 "const_int_operand" "")])
+	  (label_ref (match_operand 3 "" ""))
+	  (pc)))
+   (set (match_dup 0)
+	(plus:SI (match_dup 0) (match_operand:SI 1 "int5_operand" "L,L,L")))
+   (clobber (match_scratch:SI 4 "=X,r,r"))]
+  "INTVAL (operands[5]) == - INTVAL (operands[1])"
+"* return output_dbra (operands, insn, which_alternative);"
+;; Do not expect to understand this the first time through.  
+[(set_attr "type" "cbranch,multi,multi")
+ (set (attr "length")
+      (if_then_else (eq_attr "alternative" "0")
+;; Loop counter in register case
+;; Short branch has length of 4
+;; Long branch has length of 8
+	(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
+		      (const_int 8188))
+           (const_int 4)
+	   (const_int 8))
+
+;; Loop counter in FP reg case.
+;; Extra goo to deal with additional reload insns.
+	(if_then_else (eq_attr "alternative" "1")
+	  (if_then_else (lt (match_dup 3) (pc))
+	    (if_then_else 
+	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 24))))
+		  (const_int 8188))
+	      (const_int 24)
+	      (const_int 28))
+	    (if_then_else 
+	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
+		  (const_int 8188))
+	      (const_int 24)
+	      (const_int 28)))
+;; Loop counter in memory case.
+;; Extra goo to deal with additional reload insns.
+	(if_then_else (lt (match_dup 3) (pc))
+	  (if_then_else 
+	    (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
+		(const_int 8188))
+	    (const_int 12)
+	    (const_int 16))
+	  (if_then_else 
+	    (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
+		(const_int 8188))
+	    (const_int 12)
+	    (const_int 16))))))])
+
+(define_insn ""
+  [(set (pc)
+	(if_then_else
+	  (match_operator 2 "movb_comparison_operator"
+	   [(match_operand:SI 1 "register_operand" "r,r,r") (const_int 0)])
+	  (label_ref (match_operand 3 "" ""))
+	  (pc)))
+   (set (match_operand:SI 0 "register_operand" "=!r,!*f*x,!*m")
+	(match_dup 1))]
+  ""
+"* return output_movb (operands, insn, which_alternative, 0); "
+;; Do not expect to understand this the first time through.  
+[(set_attr "type" "cbranch,multi,multi")
+ (set (attr "length")
+      (if_then_else (eq_attr "alternative" "0")
+;; Loop counter in register case
+;; Short branch has length of 4
+;; Long branch has length of 8
+	(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
+		      (const_int 8188))
+           (const_int 4)
+	   (const_int 8))
+
+;; Loop counter in FP reg case.
+;; Extra goo to deal with additional reload insns.
+	(if_then_else (eq_attr "alternative" "1")
+	  (if_then_else (lt (match_dup 3) (pc))
+	    (if_then_else 
+	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
+		  (const_int 8188))
+	      (const_int 12)
+	      (const_int 16))
+	    (if_then_else 
+	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
+		  (const_int 8188))
+	      (const_int 12)
+	      (const_int 16)))
+;; Loop counter in memory case.
+;; Extra goo to deal with additional reload insns.
+	(if_then_else 
+	  (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
+	      (const_int 8188))
+	  (const_int 8)
+	  (const_int 12)))))])
 
+;; Handle negated branch.
+(define_insn ""
+  [(set (pc)
+	(if_then_else
+	  (match_operator 2 "movb_comparison_operator"
+	   [(match_operand:SI 1 "register_operand" "r,r,r") (const_int 0)])
+	  (pc)
+	  (label_ref (match_operand 3 "" ""))))
+   (set (match_operand:SI 0 "register_operand" "=!r,!*f*x,!*m")
+	(match_dup 1))]
+  ""
+"* return output_movb (operands, insn, which_alternative, 1); "
+;; Do not expect to understand this the first time through.  
+[(set_attr "type" "cbranch,multi,multi")
+ (set (attr "length")
+      (if_then_else (eq_attr "alternative" "0")
+;; Loop counter in register case
+;; Short branch has length of 4
+;; Long branch has length of 8
+	(if_then_else (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
+		      (const_int 8188))
+           (const_int 4)
+	   (const_int 8))
+
+;; Loop counter in FP reg case.
+;; Extra goo to deal with additional reload insns.
+	(if_then_else (eq_attr "alternative" "1")
+	  (if_then_else (lt (match_dup 3) (pc))
+	    (if_then_else 
+	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 12))))
+		  (const_int 8188))
+	      (const_int 12)
+	      (const_int 16))
+	    (if_then_else 
+	      (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
+		  (const_int 8188))
+	      (const_int 12)
+	      (const_int 16)))
+;; Loop counter in memory case.
+;; Extra goo to deal with additional reload insns.
+	(if_then_else 
+	  (lt (abs (minus (match_dup 3) (plus (pc) (const_int 8))))
+	      (const_int 8188))
+	  (const_int 8)
+	  (const_int 12)))))])
 
 ;; The next four peepholes take advantage of the new 5 operand 
 ;; fmpy{add,sub} instructions available on 1.1 CPUS.  Basically
@@ -3096,10 +3362,22 @@
 ;; This is used by the trampoline code for nested functions.
 ;; So long as the trampoline itself is less than 32 bytes this
 ;; is sufficient.
-(define_insn "cacheflush"
+
+(define_insn "dcacheflush"
   [(unspec_volatile [(const_int 1)] 0)
    (use (mem:SI (match_operand:SI 0 "register_operand" "r")))
    (use (mem:SI (match_operand:SI 1 "register_operand" "r")))]
   ""
-  "fdc 0(0,%0)\;sync\;fic 0(0,%0)\;sync\;fdc 0(0,%1)\;sync\;fic 0(0,%1)\;sync\;nop\;nop\;nop\;nop\;nop\;nop\;nop"
-  [(set_attr "length" "15")])
+  "fdc 0(0,%0)\;fdc 0(0,%1)\;sync"
+  [(set_attr "length" "12")])
+
+(define_insn "icacheflush"
+  [(unspec_volatile [(const_int 2)] 0)
+   (use (mem:SI (match_operand:SI 0 "register_operand" "r")))
+   (use (mem:SI (match_operand:SI 1 "register_operand" "r")))
+   (use (match_operand:SI 2 "register_operand" "r"))
+   (clobber (match_operand:SI 3 "register_operand" "=&r"))
+   (clobber (match_operand:SI 4 "register_operand" "=&r"))]
+  ""
+  "mfsp %%sr0,%4\;ldsid (0,%2),%3\;mtsp %3,%%sr0\;fic 0(%%sr0,%0)\;fic 0(%%sr0,%1)\;sync\;mtsp %4,%%sr0\;nop\;nop\;nop\;nop\;nop\;nop"
+  [(set_attr "length" "52")])