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1.1 root 1: ;; Machine description for Pyramid 90 Series for GNU C compiler
2: ;; Copyright (C) 1989 Free Software Foundation, Inc.
3:
4: ;; This file is part of GNU CC.
5:
6: ;; GNU CC is free software; you can redistribute it and/or modify
7: ;; it under the terms of the GNU General Public License as published by
8: ;; the Free Software Foundation; either version 1, or (at your option)
9: ;; any later version.
10:
11: ;; GNU CC is distributed in the hope that it will be useful,
12: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14: ;; GNU General Public License for more details.
15:
16: ;; You should have received a copy of the GNU General Public License
17: ;; along with GNU CC; see the file COPYING. If not, write to
18: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
19:
20: ;; Instruction patterns. When multiple patterns apply,
21: ;; the first one in the file is chosen.
22: ;;
23: ;; See file "rtl.def" for documentation on define_insn, match_*, et. al.
24: ;;
25: ;; cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
26: ;; updates for most instructions.
27:
28: ;; * Should we check for SUBREG as well as REG, in some places???
29: ;; * Make the jump tables contain branches, not addresses! This would
30: ;; save us one instruction.
31: ;; * Could the compilcated scheme for compares be simplyfied, if we had
32: ;; no named cmpqi or cmphi patterns, and instead anonymous patterns for
33: ;; the less-than-word compare cases pyr can handle???
34: ;; * The jump insn seems to accept more than just IR addressing. Would
35: ;; we win by telling GCC?
36: ;; * More DImode patterns.
37: ;; * Expansion of "cmpsi" is not necessary. Also, some define_insn could
38: ;; be taken away if constraints were used.
39: ;; * Scan backwards in "zero_extendhisi2", "zero_extendqisi2" to find out
40: ;; if the extension can be omitted. Also improve the scan (now in the sign
41: ;; extenstion patterns), to handle more cases than extension regx->regx.
42: ;; * Enhance NOTICE_UPDATE_CC. 1) Should not be reset by insn that don't
43: ;; modify cc. 2) cc is preserved by CALL.
44: ;; * "divmodsi" with Pyramid "ediv" insn. Is it possible in rtl??
45: ;; * Would "rcsp tmpreg; u?cmp[bh] op1_regdispl(tmpreg),op2" win in
46: ;; comparison with the two extensions and single test generated now?
47: ;; The rcsp insn could be expanded, and moved out of loops by the
48: ;; optimizer, making 1 (64 bit) insn of 3 (32 bit) insns in loops.
49: ;; The rcsp insn could be followed by an add insn, making non-displacement
50: ;; IR addressing sufficient.
51:
52: ;______________________________________________________________________
53: ;
54: ; Test and Compare Patterns.
55: ;______________________________________________________________________
56:
57: (define_expand "cmpsi"
58: [(set (cc0)
59: (compare (match_operand:SI 0 "general_operand" "")
60: (match_operand:SI 1 "general_operand" "")))]
61: ""
62: "
63: {
64: extern rtx test_op0, test_op1;
65: test_op0 = copy_rtx (operands[0]);
66: test_op1 = copy_rtx (operands[1]);
67: DONE;
68: }")
69:
70: (define_expand "tstsi"
71: [(set (cc0)
72: (match_operand:SI 0 "general_operand" ""))]
73: ""
74: "
75: {
76: extern rtx test_op0, test_op1;
77: test_op0 = copy_rtx (operands[0]);
78: DONE;
79: }")
80:
81: (define_insn ""
82: [(set (cc0)
83: (compare (match_operand:SI 0 "memory_operand" "m")
84: (match_operand:SI 1 "memory_operand" "m")))]
85: "weird_memory_memory (operands[0], operands[1])"
86: "*
87: {
88: rtx br_insn = NEXT_INSN (insn);
89: RTX_CODE br_code;
90:
91: if (GET_CODE (br_insn) != JUMP_INSN)
92: abort();
93: br_code = GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));
94:
95: weird_memory_memory (operands[0], operands[1]);
96:
97: if (swap_operands == 0)
98: return (br_code >= GEU && br_code <= LTU
99: ? \"ucmpw %1,%0\" : \"cmpw %1,%0\");
100: else
101: {
102: cc_status.flags |= CC_REVERSED;
103: return (br_code >= GEU && br_code <= LTU
104: ? \"ucmpw %0,%1\" : \"cmpw %0,%1\");
105: }
106: }")
107:
108: (define_insn ""
109: [(set (cc0)
110: (compare (match_operand:SI 0 "general_operand" "r,g")
111: (match_operand:SI 1 "general_operand" "g,r")))]
112: ""
113: "*
114: {
115: rtx br_insn = NEXT_INSN (insn);
116: RTX_CODE br_code;
117:
118: if (GET_CODE (br_insn) != JUMP_INSN)
119: abort();
120: br_code = GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));
121:
122: if (which_alternative == 0)
123: return (br_code >= GEU && br_code <= LTU)
124: ? \"ucmpw %1,%0\" : \"cmpw %1,%0\";
125: else
126: {
127: cc_status.flags |= CC_REVERSED;
128: return (br_code >= GEU && br_code <= LTU)
129: ? \"ucmpw %0,%1\" : \"cmpw %0,%1\";
130: }
131: }")
132:
133: (define_insn ""
134: [(set (cc0)
135: (match_operand:SI 0 "register_operand" "r"))]
136: ""
137: "mtstw %0,%0")
138:
139: (define_expand "cmphi"
140: [(set (cc0)
141: (compare (match_operand:HI 0 "general_operand" "")
142: (match_operand:HI 1 "general_operand" "")))]
143: ""
144: "
145: {
146: extern rtx test_op0, test_op1;
147: test_op0 = copy_rtx (operands[0]);
148: test_op1 = copy_rtx (operands[1]);
149: DONE;
150: }")
151:
152: (define_expand "tsthi"
153: [(set (cc0)
154: (match_operand:HI 0 "general_operand" ""))]
155: ""
156: "
157: {
158: extern rtx test_op0, test_op1;
159: test_op0 = copy_rtx (operands[0]);
160: DONE;
161: }")
162:
163: (define_insn ""
164: [(set (cc0)
165: (compare (match_operand:HI 0 "memory_operand" "m")
166: (match_operand:HI 1 "memory_operand" "m")))]
167: "weird_memory_memory (operands[0], operands[1])"
168: "*
169: {
170: rtx br_insn = NEXT_INSN (insn);
171:
172: if (GET_CODE (br_insn) != JUMP_INSN)
173: abort();
174:
175: weird_memory_memory (operands[0], operands[1]);
176:
177: if (swap_operands == 0)
178: return \"cmph %1,%0\";
179: else
180: {
181: cc_status.flags |= CC_REVERSED;
182: return \"cmph %0,%1\";
183: }
184: }")
185:
186: (define_insn ""
187: [(set (cc0)
188: (compare (match_operand:HI 0 "nonimmediate_operand" "r,m")
189: (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
190: ""
191: "*
192: {
193: rtx br_insn = NEXT_INSN (insn);
194:
195: if (GET_CODE (br_insn) != JUMP_INSN)
196: abort();
197:
198: if (which_alternative == 0)
199: return \"cmph %1,%0\";
200: else
201: {
202: cc_status.flags |= CC_REVERSED;
203: return \"cmph %0,%1\";
204: }
205: }")
206:
207: (define_expand "cmpqi"
208: [(set (cc0)
209: (compare (match_operand:QI 0 "general_operand" "")
210: (match_operand:QI 1 "general_operand" "")))]
211: ""
212: "
213: {
214: extern rtx test_op0, test_op1;
215: test_op0 = copy_rtx (operands[0]);
216: test_op1 = copy_rtx (operands[1]);
217: DONE;
218: }")
219:
220: (define_expand "tstqi"
221: [(set (cc0)
222: (match_operand:QI 0 "general_operand" ""))]
223: ""
224: "
225: {
226: extern rtx test_op0, test_op1;
227: test_op0 = copy_rtx (operands[0]);
228: DONE;
229: }")
230:
231: (define_insn ""
232: [(set (cc0)
233: (compare (match_operand:QI 0 "memory_operand" "m")
234: (match_operand:QI 1 "memory_operand" "m")))]
235: "weird_memory_memory (operands[0], operands[1])"
236: "*
237: {
238: rtx br_insn = NEXT_INSN (insn);
239: RTX_CODE br_code;
240:
241: if (GET_CODE (br_insn) != JUMP_INSN)
242: abort();
243: br_code = GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));
244:
245: weird_memory_memory (operands[0], operands[1]);
246:
247: if (swap_operands == 0)
248: return (br_code >= GEU && br_code <= LTU
249: ? \"ucmpb %1,%0\" : \"cmpb %1,%0\");
250: else
251: {
252: cc_status.flags |= CC_REVERSED;
253: return (br_code >= GEU && br_code <= LTU
254: ? \"ucmpb %0,%1\" : \"cmpb %0,%1\");
255: }
256: }")
257:
258: (define_insn ""
259: [(set (cc0)
260: (compare (match_operand:QI 0 "nonimmediate_operand" "r,m")
261: (match_operand:QI 1 "nonimmediate_operand" "m,r")))]
262: ""
263: "*
264: {
265: rtx br_insn = NEXT_INSN (insn);
266: RTX_CODE br_code;
267:
268: if (GET_CODE (br_insn) != JUMP_INSN)
269: abort();
270: br_code = GET_CODE (XEXP (XEXP (PATTERN (br_insn), 1), 0));
271:
272: if (which_alternative == 0)
273: return (br_code >= GEU && br_code <= LTU)
274: ? \"ucmpb %1,%0\" : \"cmpb %1,%0\";
275: else
276: {
277: cc_status.flags |= CC_REVERSED;
278: return (br_code >= GEU && br_code <= LTU)
279: ? \"ucmpb %0,%1\" : \"cmpb %0,%1\";
280: }
281: }")
282:
283: (define_expand "bgt"
284: [(set (pc) (if_then_else (gt (cc0) (const_int 0))
285: (label_ref (match_operand 0 "" "")) (pc)))]
286: "" "extend_and_branch (SIGN_EXTEND);")
287:
288: (define_expand "blt"
289: [(set (pc) (if_then_else (lt (cc0) (const_int 0))
290: (label_ref (match_operand 0 "" "")) (pc)))]
291: "" "extend_and_branch (SIGN_EXTEND);")
292:
293: (define_expand "bge"
294: [(set (pc) (if_then_else (ge (cc0) (const_int 0))
295: (label_ref (match_operand 0 "" "")) (pc)))]
296: "" "extend_and_branch (SIGN_EXTEND);")
297:
298: (define_expand "ble"
299: [(set (pc) (if_then_else (le (cc0) (const_int 0))
300: (label_ref (match_operand 0 "" "")) (pc)))]
301: "" "extend_and_branch (SIGN_EXTEND);")
302:
303: (define_expand "beq"
304: [(set (pc) (if_then_else (eq (cc0) (const_int 0))
305: (label_ref (match_operand 0 "" "")) (pc)))]
306: "" "extend_and_branch (SIGN_EXTEND);")
307:
308: (define_expand "bne"
309: [(set (pc) (if_then_else (ne (cc0) (const_int 0))
310: (label_ref (match_operand 0 "" "")) (pc)))]
311: "" "extend_and_branch (SIGN_EXTEND);")
312:
313: (define_expand "bgtu"
314: [(set (pc) (if_then_else (gtu (cc0) (const_int 0))
315: (label_ref (match_operand 0 "" "")) (pc)))]
316: "" "extend_and_branch (ZERO_EXTEND);")
317:
318: (define_expand "bltu"
319: [(set (pc) (if_then_else (ltu (cc0) (const_int 0))
320: (label_ref (match_operand 0 "" "")) (pc)))]
321: "" "extend_and_branch (ZERO_EXTEND);")
322:
323: (define_expand "bgeu"
324: [(set (pc) (if_then_else (geu (cc0) (const_int 0))
325: (label_ref (match_operand 0 "" "")) (pc)))]
326: "" "extend_and_branch (ZERO_EXTEND);")
327:
328: (define_expand "bleu"
329: [(set (pc) (if_then_else (leu (cc0) (const_int 0))
330: (label_ref (match_operand 0 "" "")) (pc)))]
331: "" "extend_and_branch (ZERO_EXTEND);")
332:
333: (define_insn "cmpdf"
334: [(set (cc0)
335: (compare (match_operand:DF 0 "register_operand" "r")
336: (match_operand:DF 1 "register_operand" "r")))]
337: ""
338: "cmpd %1,%0")
339:
340: (define_insn "cmpsf"
341: [(set (cc0)
342: (compare (match_operand:SF 0 "register_operand" "r")
343: (match_operand:SF 1 "register_operand" "r")))]
344: ""
345: "cmpf %1,%0")
346:
347: (define_insn "tstdf"
348: [(set (cc0)
349: (match_operand:DF 0 "register_operand" "r"))]
350: ""
351: "mtstd %0,%0")
352:
353: (define_insn "tstsf"
354: [(set (cc0)
355: (match_operand:SF 0 "register_operand" "r"))]
356: ""
357: "mtstf %0,%0")
358:
359: ;______________________________________________________________________
360: ;
361: ; Fixed-point Arithmetic.
362: ;______________________________________________________________________
363:
364: (define_insn "addsi3"
365: [(set (match_operand:SI 0 "register_operand" "=r,!r")
366: (plus:SI (match_operand:SI 1 "register_operand" "%0,r")
367: (match_operand:SI 2 "general_operand" "g,rJ")))]
368: ""
369: "*
370: {
371: if (which_alternative == 0)
372: return \"addw %2,%0\";
373: else
374: {
375: CC_STATUS_INIT;
376: if (REG_P (operands[2]))
377: return \"mova (%2)[%1*1],%0\";
378: else
379: return \"mova %a2[%1*1],%0\";
380: }
381: }")
382:
383: (define_insn "subsi3"
384: [(set (match_operand:SI 0 "register_operand" "=r,r")
385: (minus:SI (match_operand:SI 1 "general_operand" "0,g")
386: (match_operand:SI 2 "general_operand" "g,0")))]
387: ""
388: "*
389: {
390: if (which_alternative == 0)
391: return \"subw %2,%0\";
392: else
393: return \"rsubw %1,%0\";
394: }")
395:
396: (define_insn "mulsi3"
397: [(set (match_operand:SI 0 "register_operand" "=r")
398: (mult:SI (match_operand:SI 1 "register_operand" "%0")
399: (match_operand:SI 2 "general_operand" "g")))]
400: ""
401: "mulw %2,%0")
402:
403: (define_insn "umulsi3"
404: [(set (match_operand:SI 0 "register_operand" "=r")
405: (umult:SI (match_operand:SI 1 "register_operand" "%0")
406: (match_operand:SI 2 "general_operand" "g")))]
407: ""
408: "umulw %2,%0")
409:
410: (define_insn "divsi3"
411: [(set (match_operand:SI 0 "register_operand" "=r,r")
412: (div:SI (match_operand:SI 1 "general_operand" "0,g")
413: (match_operand:SI 2 "general_operand" "g,0")))]
414: ""
415: "*
416: {
417: if (which_alternative == 0)
418: return \"divw %2,%0\";
419: else
420: return \"rdivw %1,%0\";
421: }")
422:
423: (define_insn "udivsi3"
424: [(set (match_operand:SI 0 "register_operand" "=r")
425: (udiv:SI (match_operand:SI 1 "register_operand" "0")
426: (match_operand:SI 2 "general_operand" "g")))]
427: ""
428: "*
429: {
430: CC_STATUS_INIT;
431: return \"udivw %2,%0\";
432: }")
433:
434: (define_insn "modsi3"
435: [(set (match_operand:SI 0 "register_operand" "=r")
436: (mod:SI (match_operand:SI 1 "register_operand" "0")
437: (match_operand:SI 2 "general_operand" "g")))]
438: ""
439: "modw %2,%0")
440:
441: (define_insn "umodsi3"
442: [(set (match_operand:SI 0 "register_operand" "=r")
443: (umod:SI (match_operand:SI 1 "register_operand" "0")
444: (match_operand:SI 2 "general_operand" "g")))]
445: ""
446: "*
447: {
448: CC_STATUS_INIT;
449: return \"umodw %2,%0\";
450: }")
451:
452: (define_insn "negsi2"
453: [(set (match_operand:SI 0 "register_operand" "=r")
454: (neg:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
455: ""
456: "mnegw %1,%0")
457:
458: (define_insn "one_cmplsi2"
459: [(set (match_operand:SI 0 "register_operand" "=r")
460: (not:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
461: ""
462: "mcomw %1,%0")
463:
464: (define_insn "abssi2"
465: [(set (match_operand:SI 0 "register_operand" "=r")
466: (abs:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))]
467: ""
468: "mabsw %1,%0")
469:
470: ;______________________________________________________________________
471: ;
472: ; Floating-point Arithmetic.
473: ;______________________________________________________________________
474:
475: (define_insn "adddf3"
476: [(set (match_operand:DF 0 "register_operand" "=r")
477: (plus:DF (match_operand:DF 1 "register_operand" "%0")
478: (match_operand:DF 2 "register_operand" "r")))]
479: ""
480: "addd %2,%0")
481:
482: (define_insn "addsf3"
483: [(set (match_operand:SF 0 "register_operand" "=r")
484: (plus:SF (match_operand:SF 1 "register_operand" "%0")
485: (match_operand:SF 2 "register_operand" "r")))]
486: ""
487: "addf %2,%0")
488:
489: (define_insn "subdf3"
490: [(set (match_operand:DF 0 "register_operand" "=r")
491: (minus:DF (match_operand:DF 1 "register_operand" "0")
492: (match_operand:DF 2 "register_operand" "r")))]
493: ""
494: "subd %2,%0")
495:
496: (define_insn "subsf3"
497: [(set (match_operand:SF 0 "register_operand" "=r")
498: (minus:SF (match_operand:SF 1 "register_operand" "0")
499: (match_operand:SF 2 "register_operand" "r")))]
500: ""
501: "subf %2,%0")
502:
503: (define_insn "muldf3"
504: [(set (match_operand:DF 0 "register_operand" "=r")
505: (mult:DF (match_operand:DF 1 "register_operand" "%0")
506: (match_operand:DF 2 "register_operand" "r")))]
507: ""
508: "muld %2,%0")
509:
510: (define_insn "mulsf3"
511: [(set (match_operand:SF 0 "register_operand" "=r")
512: (mult:SF (match_operand:SF 1 "register_operand" "%0")
513: (match_operand:SF 2 "register_operand" "r")))]
514: ""
515: "mulf %2,%0")
516:
517: (define_insn "divdf3"
518: [(set (match_operand:DF 0 "register_operand" "=r")
519: (div:DF (match_operand:DF 1 "register_operand" "0")
520: (match_operand:DF 2 "register_operand" "r")))]
521: ""
522: "divd %2,%0")
523:
524: (define_insn "divsf3"
525: [(set (match_operand:SF 0 "register_operand" "=r")
526: (div:SF (match_operand:SF 1 "register_operand" "0")
527: (match_operand:SF 2 "register_operand" "r")))]
528: ""
529: "divf %2,%0")
530:
531: (define_insn "negdf2"
532: [(set (match_operand:DF 0 "register_operand" "=r")
533: (neg:DF (match_operand:DF 1 "register_operand" "r")))]
534: ""
535: "mnegd %1,%0")
536:
537: (define_insn "negsf2"
538: [(set (match_operand:SF 0 "register_operand" "=r")
539: (neg:SF (match_operand:SF 1 "register_operand" "r")))]
540: ""
541: "mnegf %1,%0")
542:
543: (define_insn "absdf2"
544: [(set (match_operand:DF 0 "register_operand" "=r")
545: (abs:DF (match_operand:DF 1 "register_operand" "r")))]
546: ""
547: "mabsd %1,%0")
548:
549: (define_insn "abssf2"
550: [(set (match_operand:SF 0 "register_operand" "=r")
551: (abs:SF (match_operand:SF 1 "register_operand" "r")))]
552: ""
553: "mabsf %1,%0")
554:
555: ;______________________________________________________________________
556: ;
557: ; Logical and Shift Instructions.
558: ;______________________________________________________________________
559:
560: (define_insn ""
561: [(set (cc0)
562: (and:SI (match_operand:SI 0 "register_operand" "%r")
563: (match_operand:SI 1 "general_operand" "g")))]
564: ""
565: "bitw %1,%0");
566:
567: (define_insn "andsi3"
568: [(set (match_operand:SI 0 "register_operand" "=r,r")
569: (and:SI (match_operand:SI 1 "register_operand" "%0,r")
570: (match_operand:SI 2 "general_operand" "g,K")))]
571: ""
572: "*
573: {
574: if (which_alternative == 0)
575: return \"andw %2,%0\";
576: else
577: {
578: CC_STATUS_INIT;
579: return (INTVAL (operands[2]) == 255
580: ? \"movzbw %1,%0\" : \"movzhw %1,%0\");
581: }
582: }")
583:
584: (define_insn "andcbsi3"
585: [(set (match_operand:SI 0 "register_operand" "=r")
586: (and:SI (match_operand:SI 1 "register_operand" "0")
587: (not:SI (match_operand:SI 2 "general_operand" "g"))))]
588: ""
589: "bicw %2,%0")
590:
591: (define_insn ""
592: [(set (match_operand:SI 0 "register_operand" "=r")
593: (and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
594: (match_operand:SI 2 "register_operand" "0")))]
595: ""
596: "bicw %1,%0")
597:
598: (define_insn "iorsi3"
599: [(set (match_operand:SI 0 "register_operand" "=r")
600: (ior:SI (match_operand:SI 1 "register_operand" "%0")
601: (match_operand:SI 2 "general_operand" "g")))]
602: ""
603: "orw %2,%0")
604:
605: (define_insn "xorsi3"
606: [(set (match_operand:SI 0 "register_operand" "=r")
607: (xor:SI (match_operand:SI 1 "register_operand" "%0")
608: (match_operand:SI 2 "general_operand" "g")))]
609: ""
610: "xorw %2,%0")
611:
612: ; Some patterns using De Morgan law.
613: ;
614: ;(define_insn ""
615: ; [(set (match_operand:SI 0 "register_operand" "=r")
616: ; (not:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "%0"))
617: ; (not:SI (match_operand:SI 2 "general_operand" "g")))))]
618: ; ""
619: ; "orw %2,%0")
620: ;
621: ;(define_insn ""
622: ; [(set (match_operand:SI 0 "register_operand" "=r")
623: ; (not:SI (ior:SI (not:SI (match_operand:SI 1 "register_operand" "%0"))
624: ; (not:SI (match_operand:SI 2 "general_operand" "g")))))]
625: ; ""
626: ; "andw %2,%0")
627: ;
628: ;(define_insn ""
629: ; [(set (match_operand:SI 0 "register_operand" "=r")
630: ; (not:SI (and:SI (not:SI (match_operand:SI 1 "register_operand" "0"))
631: ; (match_operand:SI 2 "immediate_operand" "n"))))]
632: ; ""
633: ; "*
634: ; operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
635: ; return \"orw %2,%0\";
636: ;")
637: ;
638: ;(define_insn ""
639: ; [(set (match_operand:SI 0 "register_operand" "=r")
640: ; (not:SI (ior:SI (not:SI (match_operand:SI 1 "register_operand" "0"))
641: ; (match_operand:SI 2 "immediate_operand" "n"))))]
642: ; ""
643: ; "*
644: ; operands[2] = gen_rtx (CONST_INT, VOIDmode, ~INTVAL (operands[2]));
645: ; return \"andw %2,%0\";
646: ;")
647:
648: (define_insn "ashlsi3"
649: [(set (match_operand:SI 0 "register_operand" "=r")
650: (ashift:SI (match_operand:SI 1 "register_operand" "0")
651: (match_operand:SI 2 "general_operand" "rnm")))]
652: ""
653: "*
654: {
655: if (GET_CODE (operands[2]) == CONST_INT)
656: {
657: int cnt = INTVAL (operands[2]) % 32;
658: if (cnt == 0)
659: return \"\";
660: operands[2] = gen_rtx (CONST_INT, VOIDmode, cnt);
661: }
662: /* Use lshlw, not ashlw, since arithmetic shifts work strangely on pyr. */
663: return \"lshlw %2,%0\";
664: }")
665:
666: ; The arithmetic left shift instructions work strange on pyramids.
667: ; They fail to modify the sign bit.
668: ;(define_insn "ashldi3"
669: ; [(set (match_operand:DI 0 "register_operand" "=r")
670: ; (ashift:DI (match_operand:DI 1 "register_operand" "0")
671: ; (match_operand:SI 2 "general_operand" "rnm")))]
672: ; ""
673: ; "*
674: ;{
675: ; if (GET_CODE (operands[2]) == CONST_INT)
676: ; {
677: ; int cnt = INTVAL (operands[2]) % 64;
678: ; if (cnt == 0)
679: ; return \"\";
680: ; operands[2] = gen_rtx (CONST_INT, VOIDmode, cnt);
681: ; }
682: ; return \"ashll %2,%0\";
683: ;}")
684:
685: (define_insn "ashrsi3"
686: [(set (match_operand:SI 0 "register_operand" "=r")
687: (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
688: (match_operand:SI 2 "general_operand" "rnm")))]
689: ""
690: "*
691: {
692: if (GET_CODE (operands[2]) == CONST_INT)
693: {
694: int cnt = INTVAL (operands[2]) % 32;
695: if (cnt == 0)
696: return \"\";
697: operands[2] = gen_rtx (CONST_INT, VOIDmode, cnt);
698: }
699: return \"ashrw %2,%0\";
700: }")
701:
702: (define_insn "ashrdi3"
703: [(set (match_operand:DI 0 "register_operand" "=r")
704: (ashiftrt:DI (match_operand:DI 1 "register_operand" "0")
705: (match_operand:SI 2 "general_operand" "rnm")))]
706: ""
707: "*
708: {
709: if (GET_CODE (operands[2]) == CONST_INT)
710: {
711: int cnt = INTVAL (operands[2]) % 64;
712: if (cnt == 0)
713: return \"\";
714: operands[2] = gen_rtx (CONST_INT, VOIDmode, cnt);
715: }
716: return \"ashrl %2,%0\";
717: }")
718:
719: (define_insn "lshrsi3"
720: [(set (match_operand:SI 0 "register_operand" "=r")
721: (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
722: (match_operand:SI 2 "general_operand" "rnm")))]
723: ""
724: "*
725: {
726: if (GET_CODE (operands[2]) == CONST_INT)
727: {
728: int cnt = INTVAL (operands[2]) % 32;
729: if (cnt == 0)
730: return \"\";
731: operands[2] = gen_rtx (CONST_INT, VOIDmode, cnt);
732: }
733: return \"lshrw %2,%0\";
734: }")
735:
736: (define_insn "rotlsi3"
737: [(set (match_operand:SI 0 "register_operand" "=r")
738: (rotate:SI (match_operand:SI 1 "register_operand" "0")
739: (match_operand:SI 2 "general_operand" "rnm")))]
740: ""
741: "*
742: {
743: if (GET_CODE (operands[2]) == CONST_INT)
744: {
745: int cnt = INTVAL (operands[2]) % 32;
746: if (cnt == 0)
747: return \"\";
748: operands[2] = gen_rtx (CONST_INT, VOIDmode, cnt);
749: }
750: return \"rotlw %2,%0\";
751: }")
752:
753: (define_insn "rotrsi3"
754: [(set (match_operand:SI 0 "register_operand" "=r")
755: (rotatert:SI (match_operand:SI 1 "register_operand" "0")
756: (match_operand:SI 2 "general_operand" "rnm")))]
757: ""
758: "*
759: {
760: if (GET_CODE (operands[2]) == CONST_INT)
761: {
762: int cnt = INTVAL (operands[2]) % 32;
763: if (cnt == 0)
764: return \"\";
765: operands[2] = gen_rtx (CONST_INT, VOIDmode, cnt);
766: }
767: return \"rotrw %2,%0\";
768: }")
769:
770: ;______________________________________________________________________
771: ;
772: ; Fixed and Floating Moves.
773: ;______________________________________________________________________
774:
775: ;; If the destination is a memory address, indexed source operands are
776: ;; disallowed. Big DImode constants are always loaded into a reg pair,
777: ;; although offsetable memory addresses really could be dealt with.
778:
779: (define_insn ""
780: [(set (match_operand:DI 0 "memory_operand" "=m")
781: (match_operand:DI 1 "nonindexed_operand" "gF"))]
782: "(GET_CODE (operands[1]) == CONST_DOUBLE
783: ? CONST_DOUBLE_HIGH (operands[1]) == 0
784: : 1)"
785: "*
786: {
787: CC_STATUS_INIT;
788: if (GET_CODE (operands[1]) == CONST_DOUBLE)
789: operands[1] = gen_rtx (CONST_INT, VOIDmode,
790: CONST_DOUBLE_LOW (operands[1]));
791: return \"movl %1,%0\";
792: }")
793:
794: ;; Force the destination to a register, so all source operands are allowed.
795:
796: (define_insn "movdi"
797: [(set (match_operand:DI 0 "general_operand" "=r")
798: (match_operand:DI 1 "general_operand" "gF"))]
799: ""
800: "* return output_move_double (operands); ")
801:
802: ;; If the destination is a memory address, indexed operands are disallowed.
803:
804: (define_insn ""
805: [(set (match_operand:SI 0 "memory_operand" "=m")
806: (match_operand:SI 1 "nonindexed_operand" "g"))]
807: ""
808: "*
809: {
810: CC_STATUS_INIT;
811: return \"movw %1,%0\";
812: }")
813:
814: ;; Force the destination to a register, so all source operands are allowed.
815:
816: (define_insn "movsi"
817: [(set (match_operand:SI 0 "general_operand" "=r")
818: (match_operand:SI 1 "general_operand" "g"))]
819: ""
820: "*
821: {
822: CC_STATUS_INIT;
823: return \"movw %1,%0\";
824: }")
825:
826: ;; If the destination is a memory address, indexed operands are disallowed.
827:
828: (define_insn ""
829: [(set (match_operand:HI 0 "memory_operand" "=m")
830: (match_operand:HI 1 "nonindexed_operand" "g"))]
831: ""
832: "*
833: {
834: if (REG_P (operands[1]))
835: return \"cvtwh %1,%0\"; /* reg -> mem */
836: else
837: {
838: CC_STATUS_INIT;
839: return \"movh %1,%0\"; /* mem imm -> mem */
840: }
841: }")
842:
843: ;; Force the destination to a register, so all source operands are allowed.
844:
845: (define_insn "movhi"
846: [(set (match_operand:HI 0 "general_operand" "=r")
847: (match_operand:HI 1 "general_operand" "g"))]
848: ""
849: "*
850: {
851: if (GET_CODE (operands[1]) != MEM)
852: {
853: CC_STATUS_INIT;
854: return \"movw %1,%0\";
855: }
856: return \"cvthw %1,%0\";
857: }")
858:
859: ;; If the destination is a memory address, indexed operands are disallowed.
860:
861: (define_insn ""
862: [(set (match_operand:QI 0 "memory_operand" "=m")
863: (match_operand:QI 1 "nonindexed_operand" "g"))]
864: ""
865: "*
866: {
867: if (REG_P (operands[1]))
868: return \"cvtwb %1,%0\"; /* reg -> mem */
869: else
870: {
871: CC_STATUS_INIT;
872: return \"movb %1,%0\"; /* mem imm -> mem */
873: }
874: }")
875:
876: ;; Force the destination to a register, so all source operands are allowed.
877:
878: (define_insn "movqi"
879: [(set (match_operand:QI 0 "general_operand" "=r")
880: (match_operand:QI 1 "general_operand" "g"))]
881: ""
882: "*
883: {
884: if (GET_CODE (operands[1]) != MEM)
885: {
886: CC_STATUS_INIT;
887: return \"movw %1,%0\";
888: }
889: return \"cvtbw %1,%0\";
890: }")
891:
892: ;; If the destination is a memory address, indexed operands are disallowed, and
893: ;; so are immediate operands. (Constants are always loaded into a reg pair,
894: ;; although offsetable memory addresses really doesn't need that.)
895:
896: (define_insn ""
897: [(set (match_operand:DF 0 "memory_operand" "=m")
898: (match_operand:DF 1 "nonindexed_operand" "g"))]
899: "GET_CODE (operands[1]) != CONST_DOUBLE"
900: "*
901: {
902: CC_STATUS_INIT;
903: return \"movl %1,%0\";
904: }")
905:
906: ;; Force the destination to a register, so all source operands are allowed.
907:
908: (define_insn "movdf"
909: [(set (match_operand:DF 0 "general_operand" "=r")
910: (match_operand:DF 1 "general_operand" "gF"))]
911: ""
912: "* return output_move_double (operands); ")
913:
914: ;; If the destination is a memory address, indexed operands are disallowed.
915:
916: (define_insn ""
917: [(set (match_operand:SF 0 "memory_operand" "=m")
918: (match_operand:SF 1 "nonindexed_operand" "g"))]
919: ""
920: "*
921: {
922: CC_STATUS_INIT;
923: return \"movw %1,%0\";
924: }")
925:
926: ;; Force the destination to a register, so all source operands are allowed.
927:
928: (define_insn "movsf"
929: [(set (match_operand:SF 0 "general_operand" "=r")
930: (match_operand:SF 1 "general_operand" "g"))]
931: ""
932: "*
933: {
934: CC_STATUS_INIT;
935: return \"movw %1,%0\";
936: }")
937:
938: (define_insn ""
939: [(set (match_operand:SI 0 "register_operand" "=r")
940: (match_operand:QI 1 "address_operand" "p"))]
941: ""
942: "*
943: CC_STATUS_INIT;
944: return \"mova %a1,%0\";
945: ")
946:
947: ;______________________________________________________________________
948: ;
949: ; Conversion patterns.
950: ;______________________________________________________________________
951:
952: ;; The trunc patterns are used only when non compile-time constants are used.
953:
954: (define_insn "truncsiqi2"
955: [(set (match_operand:QI 0 "general_operand" "=r,m")
956: (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "rm,r")))]
957: ""
958: "*
959: {
960: CC_STATUS_INIT;
961: if (REGNO (operands[0]) == REGNO (operands[1]))
962: return \"\";
963: else
964: return \"movw %1,%0\";
965: }")
966:
967: (define_insn "truncsihi2"
968: [(set (match_operand:HI 0 "general_operand" "=r,m")
969: (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "rm,r")))]
970: ""
971: "*
972: {
973: CC_STATUS_INIT;
974: if (REGNO (operands[0]) == REGNO (operands[1]))
975: return \"\";
976: else
977: return \"movw %1,%0\";
978: }")
979:
980: (define_insn "extendhisi2"
981: [(set (match_operand:SI 0 "general_operand" "=r,m")
982: (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm,r")))]
983: ""
984: "*
985: {
986: extern int optimize;
987: if (optimize && REG_P (operands[0]) && REG_P (operands[1])
988: && REGNO (operands[0]) == REGNO (operands[1])
989: && already_sign_extended (insn, HImode, operands[0]))
990: {
991: CC_STATUS_INIT;
992: return \"\";
993: }
994: return \"cvthw %1,%0\";
995: }")
996:
997: (define_insn "extendqisi2"
998: [(set (match_operand:SI 0 "general_operand" "=r,m")
999: (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm,r")))]
1000: ""
1001: "*
1002: {
1003: extern int optimize;
1004: if (optimize && REG_P (operands[0]) && REG_P (operands[1])
1005: && REGNO (operands[0]) == REGNO (operands[1])
1006: && already_sign_extended (insn, QImode, operands[0]))
1007: {
1008: CC_STATUS_INIT;
1009: return \"\";
1010: }
1011: return \"cvtbw %1,%0\";
1012: }")
1013:
1014: ; Pyramid doesn't have insns *called* "cvtbh" or "movzbh".
1015: ; But we can cvtbw/movzbw into a register, where there is no distinction
1016: ; between words and halfwords.
1017: (define_insn "extendqihi2"
1018: [(set (match_operand:HI 0 "register_operand" "=r")
1019: (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
1020: ""
1021: "cvtbw %1,%0")
1022:
1023: (define_insn "zero_extendhisi2"
1024: [(set (match_operand:SI 0 "register_operand" "=r")
1025: (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "rm")))]
1026: ""
1027: "*
1028: {
1029: CC_STATUS_INIT;
1030: return \"movzhw %1,%0\";
1031: }")
1032:
1033: (define_insn "zero_extendqisi2"
1034: [(set (match_operand:SI 0 "register_operand" "=r")
1035: (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
1036: ""
1037: "*
1038: {
1039: CC_STATUS_INIT;
1040: return \"movzbw %1,%0\";
1041: }")
1042:
1043: (define_insn "zero_extendqihi2"
1044: [(set (match_operand:HI 0 "register_operand" "=r")
1045: (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "rm")))]
1046: ""
1047: "*
1048: {
1049: CC_STATUS_INIT;
1050: return \"movzbw %1,%0\";
1051: }")
1052:
1053: (define_insn "extendsfdf2"
1054: [(set (match_operand:DF 0 "general_operand" "=r,m")
1055: (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "rm,r")))]
1056: ""
1057: "cvtfd %1,%0")
1058:
1059: (define_insn "truncdfsf2"
1060: [(set (match_operand:SF 0 "general_operand" "=r,m")
1061: (float_truncate:SF (match_operand:DF 1 "nonimmediate_operand" "rm,r")))]
1062: ""
1063: "cvtdf %1,%0")
1064:
1065: ;;----------------------------------------------------------------------------
1066: ;;
1067: ;; Fix-to-Float and Float-to-Fix Conversion Patterns.
1068: ;;
1069: ;; Note that the ones that start with SImode come first.
1070: ;; That is so that an operand that is a CONST_INT
1071: ;; (and therefore lacks a specific machine mode).
1072: ;; will be recognized as SImode (which is always valid)
1073: ;; rather than as QImode or HImode.
1074: ;;
1075: ;;----------------------------------------------------------------------------
1076:
1077: (define_insn "floatsisf2"
1078: [(set (match_operand:SF 0 "general_operand" "=r,m")
1079: (float:SF (match_operand:SI 1 "nonimmediate_operand" "rm,r")))]
1080: ""
1081: "cvtwf %1,%0")
1082:
1083: (define_insn "floatsidf2"
1084: [(set (match_operand:DF 0 "general_operand" "=r,m")
1085: (float:DF (match_operand:SI 1 "nonimmediate_operand" "rm,r")))]
1086: ""
1087: "cvtwd %1,%0")
1088:
1089: (define_insn "fix_truncsfsi2"
1090: [(set (match_operand:SI 0 "general_operand" "=r,m")
1091: (fix:SI (fix:SF (match_operand:SF 1 "nonimmediate_operand" "rm,r"))))]
1092: ""
1093: "cvtfw %1,%0")
1094:
1095: (define_insn "fix_truncdfsi2"
1096: [(set (match_operand:SI 0 "general_operand" "=r,m")
1097: (fix:SI (fix:DF (match_operand:DF 1 "nonimmediate_operand" "rm,r"))))]
1098: ""
1099: "cvtdw %1,%0")
1100:
1101: ;______________________________________________________________________
1102: ;
1103: ; Flow Control Patterns.
1104: ;______________________________________________________________________
1105:
1106: ;; Prefer "br" to "jump" for unconditional jumps, since it's faster.
1107: ;; (The assembler can manage with out-of-range branches.)
1108:
1109: (define_insn "jump"
1110: [(set (pc)
1111: (label_ref (match_operand 0 "" "")))]
1112: ""
1113: "br %l0")
1114:
1115: (define_insn ""
1116: [(set (pc)
1117: (if_then_else (match_operator 0 "relop" [(cc0) (const_int 0)])
1118: (label_ref (match_operand 1 "" ""))
1119: (pc)))]
1120: ""
1121: "b%N0 %l1")
1122:
1123: (define_insn ""
1124: [(set (pc)
1125: (if_then_else (match_operator 0 "relop" [(cc0) (const_int 0)])
1126: (pc)
1127: (label_ref (match_operand 1 "" ""))))]
1128: ""
1129: "b%C0 %l1")
1130:
1131: (define_insn "call"
1132: [(call (match_operand:QI 0 "memory_operand" "m")
1133: (match_operand:QI 1 "immediate_operand" "n"))]
1134: ""
1135: "call %0")
1136:
1137: (define_insn "call_value"
1138: [(set (match_operand 0 "" "=r")
1139: (call (match_operand:QI 1 "memory_operand" "m")
1140: (match_operand:SI 2 "immediate_operand" "n")))]
1141: ;; Operand 2 not really used on Pyramid architecture.
1142: ""
1143: "call %1")
1144:
1145: (define_insn ""
1146: [(return)]
1147: ""
1148: "ret")
1149:
1150: (define_insn "tablejump"
1151: [(set (pc) (match_operand:SI 0 "register_operand" "r"))
1152: (use (label_ref (match_operand 1 "" "")))]
1153: ""
1154: "jump (%0)")
1155:
1156: ;______________________________________________________________________
1157: ;
1158: ; Peep-hole Optimization Patterns.
1159: ;______________________________________________________________________
1160:
1161: ;; Optimize fullword move followed by a test of the moved value.
1162:
1163: ;(define_peephole
1164: ; [(set (match_operand:SI 0 "register_operand" "=r")
1165: ; (match_operand:SI 1 "nonimmediate_operand" "rm"))
1166: ; (set (cc0) (match_operand:SI 2 "nonimmediate_operand" "rm"))]
1167: ; "rtx_equal_p (operands[2], operands[0])
1168: ; || rtx_equal_p (operands[2], operands[1])"
1169: ; "mtstw %1,%0")
1170: ;
1171: ;;; Optimize loops with a incremented/decremented variable.
1172: ;
1173: ;(define_peephole
1174: ; [(set (match_operand:SI 0 "register_operand" "=r")
1175: ; (plus:SI (match_dup 0)
1176: ; (const_int -1)))
1177: ; (set (cc0)
1178: ; (compare (match_operand:SI 1 "register_operand" "r")
1179: ; (match_operand:SI 2 "nonmemory_operand" "ri")))
1180: ; (set (pc)
1181: ; (if_then_else (match_operator:SI 3 "signed_comparison"
1182: ; [(cc0) (const_int 0)])
1183: ; (label_ref (match_operand 4 "" ""))
1184: ; (pc)))]
1185: ; "rtx_equal_p (operands[0], operands[1])
1186: ; || rtx_equal_p (operands[0], operands[2])"
1187: ; "*
1188: ; if (rtx_equal_p (operands[0], operands[1]))
1189: ; {
1190: ; output_asm_insn (\"dcmpw %2,%0\", operands);
1191: ; return output_branch (GET_CODE (operands[3]));
1192: ; }
1193: ; else
1194: ; {
1195: ; output_asm_insn (\"dcmpw %1,%0\", operands);
1196: ; return output_inv_branch (GET_CODE (operands[3]));
1197: ; }
1198: ;")
1199: ;
1200: ;(define_peephole
1201: ; [(set (match_operand:SI 0 "register_operand" "=r")
1202: ; (plus:SI (match_dup 0)
1203: ; (const_int 1)))
1204: ; (set (cc0)
1205: ; (compare (match_operand:SI 1 "register_operand" "r")
1206: ; (match_operand:SI 2 "nonmemory_operand" "ri")))
1207: ; (set (pc)
1208: ; (if_then_else (match_operator:SI 3 "signed_comparison"
1209: ; [(cc0) (const_int 0)])
1210: ; (label_ref (match_operand 4 "" ""))
1211: ; (pc)))]
1212: ; "rtx_equal_p (operands[0], operands[1])
1213: ; || rtx_equal_p (operands[0], operands[2])"
1214: ; "*
1215: ; if (rtx_equal_p (operands[0], operands[1]))
1216: ; {
1217: ; output_asm_insn (\"icmpw %2,%0\", operands);
1218: ; return output_branch (GET_CODE (operands[3]));
1219: ; }
1220: ; else
1221: ; {
1222: ; output_asm_insn (\"icmpw %1,%0\", operands);
1223: ; return output_inv_branch (GET_CODE (operands[3]));
1224: ; }
1225: ;")
1226: ;
1227: ;(define_peephole
1228: ; [(set (match_operand:SI 0 "register_operand" "=r")
1229: ; (plus:SI (match_dup 0) (const_int -1)))
1230: ; (set (cc0) (match_dup 0))
1231: ; (set (pc) (if_then_else (match_operator:SI 1 "signed_comparison"
1232: ; [(cc0) (const_int 0)])
1233: ; (label_ref (match_operand 4 "" ""))
1234: ; (pc)))]
1235: ; ""
1236: ; "*
1237: ; output_asm_insn (\"dcmpw $0,%0\", operands);
1238: ; return output_branch (GET_CODE (operands[1]));
1239: ;")
1240: ;
1241: ;(define_peephole
1242: ; [(set (match_operand:SI 0 "register_operand" "=r")
1243: ; (plus:SI (match_dup 0) (const_int 1)))
1244: ; (set (cc0) (match_dup 0))
1245: ; (set (pc) (if_then_else (match_operator:SI 1 "signed_comparison"
1246: ; [(cc0) (const_int 0)])
1247: ; (label_ref (match_operand 4 "" ""))
1248: ; (pc)))]
1249: ; ""
1250: ; "*
1251: ; output_asm_insn (\"icmpw $0,%0\", operands);
1252: ; return output_branch (GET_CODE (operands[1]));
1253: ;")
1254: ;
1255: ;;; Combine word moves with consequtive operands into a long move.
1256: ;;; Also combines immediate moves, if the high-order destination operand
1257: ;;; is loaded with zero.
1258: ;
1259: ;(define_peephole
1260: ; [(set (match_operand:SI 0 "general_operand" "=g")
1261: ; (match_operand:SI 1 "general_operand" "g"))
1262: ; (set (match_operand:SI 2 "general_operand" "=g")
1263: ; (match_operand:SI 3 "general_operand" "g"))]
1264: ; "movdi_possible (operands)"
1265: ; "*
1266: ; CC_STATUS_INIT;
1267: ; movdi_possible (operands);
1268: ; if (CONSTANT_P (operands[1]))
1269: ; /* Also operand 3 is guarranteed to be CONSTANT by movdi_possible. */
1270: ; return (swap_operands) ? \"movl %3,%0\" : \"movl %1,%2\";
1271: ;
1272: ; return (swap_operands) ? \"movl %1,%0\" : \"movl %3,%2\";
1273: ;")
1274: ;
1275: ;;; Optimize certain tests after memory stores.
1276: ;
1277: ;(define_peephole
1278: ; [(set (match_operand 0 "memory_operand" "=m")
1279: ; (match_operand 1 "register_operand" "r"))
1280: ; (set (match_operand:SI 2 "register_operand" "=r")
1281: ; (sign_extend:SI (match_dup 1)))
1282: ; (set (cc0)
1283: ; (match_dup 2))]
1284: ; "dead_or_set_p (insn, operands[2])"
1285: ; "*
1286: ; if (GET_MODE (operands[0]) == QImode)
1287: ; return \"cvtwb %1,%0\";
1288: ; else
1289: ; return \"cvtwh %1,%0\";
1290: ;")
1291:
1292: ;______________________________________________________________________
1293: ;
1294: ; DImode Patterns.
1295: ;______________________________________________________________________
1296:
1297: (define_expand "extendsidi2"
1298: [(set (subreg:SI (match_operand:DI 0 "register_operand" "=r") 1)
1299: (match_operand:SI 1 "register_operand" "r"))
1300: (set (subreg:SI (match_dup 0) 0)
1301: (subreg:SI (match_dup 0) 1))
1302: (set (subreg:SI (match_dup 0) 0)
1303: (ashiftrt:SI (subreg:SI (match_dup 0) 0)
1304: (const_int 31)))]
1305: ""
1306: "")
1307:
1308: ;; I need to debug these.
1309:
1310: ;(define_expand "cmpdi"
1311: ; [(set (cc0)
1312: ; (compare (subreg:SI (match_operand:DI 0 "register_operand" "r") 0)
1313: ; (subreg:SI (match_operand:DI 1 "register_operand" "r") 0)))
1314: ; (set (pc) (if_then_else (ne (cc0) (const_int 0))
1315: ; (label_ref (match_dup 2))
1316: ; (pc)))
1317: ; (set (cc0)
1318: ; (compare (subreg:SI (match_dup 0) 1)
1319: ; (subreg:SI (match_dup 1) 1)))
1320: ; (match_dup 2)]
1321: ; ""
1322: ; "operands[2] = gen_label_rtx ();")
1323: ;
1324: ;(define_expand "tstdi"
1325: ; [(set (cc0) (subreg:SI (match_operand:DI 0 "register_operand" "r") 0))
1326: ; (set (pc) (if_then_else (ne (cc0) (const_int 0))
1327: ; (label_ref (match_dup 1))
1328: ; (pc)))
1329: ; (set (cc0) (subreg:SI (match_dup 0) 1))
1330: ; (match_dup 1)]
1331: ; ""
1332: ; "operands[1] = gen_label_rtx ();")
1333:
1334: (define_insn "adddi3"
1335: [(set (match_operand:DI 0 "register_operand" "=r")
1336: (plus:DI (match_operand:DI 1 "register_operand" "%0")
1337: (match_operand:DI 2 "nonmemory_operand" "rF")))]
1338: ""
1339: "*
1340: {
1341: rtx xoperands[2];
1342: CC_STATUS_INIT;
1343: xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1344: if (REG_P (operands[2]))
1345: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
1346: else
1347: {
1348: xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
1349: CONST_DOUBLE_LOW (operands[2]));
1350: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1351: CONST_DOUBLE_HIGH (operands[2]));
1352: }
1353: output_asm_insn (\"addw %1,%0\", xoperands);
1354: return \"addwc %2,%0\";
1355: }")
1356:
1357: (define_insn "subdi3"
1358: [(set (match_operand:DI 0 "register_operand" "=r")
1359: (minus:DI (match_operand:DI 1 "register_operand" "0")
1360: (match_operand:DI 2 "nonmemory_operand" "rF")))]
1361: ""
1362: "*
1363: {
1364: rtx xoperands[2];
1365: CC_STATUS_INIT;
1366: xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1367: if (REG_P (operands[2]))
1368: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
1369: else
1370: {
1371: xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
1372: CONST_DOUBLE_LOW (operands[2]));
1373: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1374: CONST_DOUBLE_HIGH (operands[2]));
1375: }
1376: output_asm_insn (\"subw %1,%0\", xoperands);
1377: return \"subwb %2,%0\";
1378: }")
1379:
1380: (define_insn "iordi3"
1381: [(set (match_operand:DI 0 "register_operand" "=r")
1382: (ior:DI (match_operand:DI 1 "register_operand" "%0")
1383: (match_operand:DI 2 "nonmemory_operand" "rF")))]
1384: ""
1385: "*
1386: {
1387: rtx xoperands[2];
1388: CC_STATUS_INIT;
1389: xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1390: if (REG_P (operands[2]))
1391: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
1392: else
1393: {
1394: xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
1395: CONST_DOUBLE_LOW (operands[2]));
1396: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1397: CONST_DOUBLE_HIGH (operands[2]));
1398: }
1399: output_asm_insn (\"orw %1,%0\", xoperands);
1400: return \"orw %2,%0\";
1401: }")
1402:
1403: (define_insn "anddi3"
1404: [(set (match_operand:DI 0 "register_operand" "=r")
1405: (and:DI (match_operand:DI 1 "register_operand" "%0")
1406: (match_operand:DI 2 "nonmemory_operand" "rF")))]
1407: ""
1408: "*
1409: {
1410: rtx xoperands[2];
1411: CC_STATUS_INIT;
1412: xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1413: if (REG_P (operands[2]))
1414: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
1415: else
1416: {
1417: xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
1418: CONST_DOUBLE_LOW (operands[2]));
1419: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1420: CONST_DOUBLE_HIGH (operands[2]));
1421: }
1422: output_asm_insn (\"andw %1,%0\", xoperands);
1423: return \"andw %2,%0\";
1424: }")
1425:
1426: (define_insn "xordi3"
1427: [(set (match_operand:DI 0 "register_operand" "=r")
1428: (xor:DI (match_operand:DI 1 "register_operand" "%0")
1429: (match_operand:DI 2 "nonmemory_operand" "rF")))]
1430: ""
1431: "*
1432: {
1433: rtx xoperands[2];
1434: CC_STATUS_INIT;
1435: xoperands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1436: if (REG_P (operands[2]))
1437: xoperands[1] = gen_rtx (REG, SImode, REGNO (operands[2]) + 1);
1438: else
1439: {
1440: xoperands[1] = gen_rtx (CONST_INT, VOIDmode,
1441: CONST_DOUBLE_LOW (operands[2]));
1442: operands[2] = gen_rtx (CONST_INT, VOIDmode,
1443: CONST_DOUBLE_HIGH (operands[2]));
1444: }
1445: output_asm_insn (\"xorw %1,%0\", xoperands);
1446: return \"xorw %2,%0\";
1447: }")
1448:
1449: (define_insn "nop"
1450: [(const_int 0)]
1451: ""
1452: "movw gr0,gr0 # nop")
1453:
1454: ;;- Local variables:
1455: ;;- mode:emacs-lisp
1456: ;;- comment-start: ";;- "
1457: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
1458: ;;- eval: (modify-syntax-entry ?] ")[")
1459: ;;- eval: (modify-syntax-entry ?{ "(}")
1460: ;;- eval: (modify-syntax-entry ?} "){")
1461: ;;- End:
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