--- gcc/config/rs6000.md 2018/04/24 17:51:37 1.1 +++ gcc/config/rs6000.md 2018/04/24 18:05:59 1.1.1.4 @@ -22,7 +22,7 @@ ;; Define an insn type attribute. This is used in function unit delay ;; computations. -(define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare" +(define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare,mtlr" (const_string "integer")) ;; Memory delivers its result in two cycles. @@ -40,18 +40,21 @@ ;; Floating-point comparisons take eight cycles. (define_function_unit "compare" 1 0 (eq_attr "type" "fpcompare") 8 0) + +;; Branches on LR cannot be done until five cycles after LR is set. +(define_function_unit "branch" 1 0 (eq_attr "type" "mtlr") 5 0) ;; Start with fixed-point load and store insns. Here we put only the more ;; complex forms. Basic data transfer is done later. (define_expand "zero_extendqisi2" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] "" "") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] "" "@ @@ -61,7 +64,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r")) + (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 2 "=r"))] "" @@ -70,22 +73,22 @@ (define_insn "" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r")) + (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (match_dup 1)))] "" "andil. %0,%1,255" [(set_attr "type" "compare")]) (define_expand "zero_extendqihi2" - [(set (match_operand:HI 0 "gen_reg_operand" "") - (zero_extend:HI (match_operand:QI 1 "gen_reg_operand" "")))] + [(set (match_operand:HI 0 "gpc_reg_operand" "") + (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))] "" "") (define_insn "" - [(set (match_operand:HI 0 "gen_reg_operand" "=r,r") + [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] "" "@ @@ -94,13 +97,13 @@ [(set_attr "type" "load,*")]) (define_expand "zero_extendhisi2" - [(set (match_operand:SI 0 "gen_reg_operand" "r") - (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] "" "") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] "" "@ @@ -110,7 +113,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r")) + (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 2 "=r"))] "" @@ -119,22 +122,22 @@ (define_insn "" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r")) + (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (match_dup 1)))] "" "andil. %0,%1,65535" [(set_attr "type" "compare")]) (define_expand "extendhisi2" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] "" "") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] "" "@ @@ -144,7 +147,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r")) + (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 2 "=r"))] "" @@ -153,18 +156,18 @@ (define_insn "" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r")) + (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (sign_extend:SI (match_dup 1)))] "" "exts. %0,%1" [(set_attr "type" "compare")]) ;; Fixed-point arithmetic insns. -(define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (plus:SI (match_operand:SI 1 "gen_reg_operand" "%r,b") +(define_insn "addsi3" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b") (match_operand:SI 2 "add_operand" "rI,J")))] "" "@ @@ -173,7 +176,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] @@ -183,49 +186,48 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (match_dup 1) (match_dup 2)))] "" "a%I2. %0,%1,%2" [(set_attr "type" "compare")]) -(define_expand "addsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (plus:SI (match_operand:SI 1 "gen_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")))] - "" - " +;; Split an add that we can't do in one insn into two insns, each of which +;; does one 16-bit part. This is used by combine. Note that the low-order +;; add should be last in case the result gets used in an address. + +(define_split + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (plus:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "non_add_cint_operand" "")))] + "" + [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3))) + (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))] +" { - if (GET_CODE (operands[2]) == CONST_INT - && (unsigned) (INTVAL (operands[2]) + 0x8000) >= 0x10000 - && (INTVAL (operands[2]) & 0xffff) != 0) - { - int low = INTVAL (operands[2]) & 0xffff; - int high = (unsigned) INTVAL (operands[2]) >> 16; + int low = INTVAL (operands[2]) & 0xffff; + int high = (unsigned) INTVAL (operands[2]) >> 16; - if (low & 0x8000) - high++, low |= 0xffff0000; + if (low & 0x8000) + high++, low |= 0xffff0000; - emit_insn (gen_addsi3 (operands[0], operands[1], - gen_rtx (CONST_INT, VOIDmode, high << 16))); - operands[1] = operands[0]; - operands[2] = gen_rtx (CONST_INT, VOIDmode, low); - } + operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16); + operands[4] = gen_rtx (CONST_INT, VOIDmode, low); }") (define_insn "one_cmplsi2" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (not:SI (match_operand:SI 1 "gen_reg_operand" "r")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "sfi %0,%1,-1") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I") - (match_operand:SI 2 "gen_reg_operand" "r,r")))] + (match_operand:SI 2 "gpc_reg_operand" "r,r")))] "" "@ sf %0,%2,%1 @@ -233,8 +235,8 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -243,17 +245,17 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (minus:SI (match_dup 1) (match_dup 2)))] "" "sf. %0,%2,%1" [(set_attr "type" "compare")]) (define_expand "subsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand" "") (minus:SI (match_operand:SI 1 "reg_or_short_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")))] "" @@ -265,70 +267,95 @@ negate_rtx (SImode, operands[2]))); DONE; } - else - operands[2] = force_reg (SImode, operands[2]); }") ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i] ;; instruction and some auxiliary computations. Then we just have a single -;; DEFINE_INSN for doz[i]. +;; DEFINE_INSN for doz[i] and the define_splits to make them if made by +;; combine. (define_expand "sminsi3" [(set (match_dup 3) - (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "") + (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (const_int 0) (minus:SI (match_dup 2) (match_dup 1)))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (minus:SI (match_dup 2) (match_dup 3)))] "" " { operands[3] = gen_reg_rtx (SImode); }") +(define_split + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (smin:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "reg_or_short_operand" ""))) + (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] + "" + [(set (match_dup 3) + (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) + (const_int 0) + (minus:SI (match_dup 2) (match_dup 1)))) + (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))] + "") + (define_expand "smaxsi3" [(set (match_dup 3) - (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "") + (if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_short_operand" "")) (const_int 0) (minus:SI (match_dup 2) (match_dup 1)))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (plus:SI (match_dup 3) (match_dup 1)))] "" " { operands[3] = gen_reg_rtx (SImode); }") +(define_split + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (smax:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "reg_or_short_operand" ""))) + (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] + "" + [(set (match_dup 3) + (if_then_else:SI (gt:SI (match_dup 1) (match_dup 2)) + (const_int 0) + (minus:SI (match_dup 2) (match_dup 1)))) + (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))] + "") + (define_expand "uminsi3" - [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "") + [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") (const_int -2147483648))) - (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "") + (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") (const_int -2147483648))) (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) (const_int 0) (minus:SI (match_dup 4) (match_dup 3)))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (minus:SI (match_dup 2) (match_dup 3)))] "" " { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") (define_expand "umaxsi3" - [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "") + [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") (const_int -2147483648))) - (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "") + (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "") (const_int -2147483648))) (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4)) (const_int 0) (minus:SI (match_dup 4) (match_dup 3)))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (plus:SI (match_dup 3) (match_dup 1)))] "" " { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "reg_or_short_operand" "r")) + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0) (minus:SI (match_dup 2) (match_dup 1))))] "" @@ -337,8 +364,8 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "reg_or_short_operand" "r")) + (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0) (minus:SI (match_dup 2) (match_dup 1))) (const_int 0))) @@ -350,12 +377,12 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC - (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "reg_or_short_operand" "r")) + (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0) (minus:SI (match_dup 2) (match_dup 1))) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (if_then_else:SI (gt (match_dup 1) (match_dup 2)) (const_int 0) (minus:SI (match_dup 2) (match_dup 1))))] @@ -366,26 +393,26 @@ ;; We don't need abs with condition code because such comparisons should ;; never be done. (define_insn "abssi2" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "abs %0,%1") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))] "" "nabs %0,%1") (define_insn "negsi2" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (match_operand:SI 1 "gen_reg_operand" "r")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))] "" "neg %0,%1") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r")) + (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 2 "=r"))] "" @@ -394,9 +421,9 @@ (define_insn "" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r")) + (compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (neg:SI (match_dup 1)))] "" "neg. %0,%1" @@ -423,8 +450,8 @@ [(set_attr "type" "compare")]) (define_insn "mulsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (mult:SI (match_operand:SI 1 "gen_reg_operand" "%r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") (match_operand:SI 2 "reg_or_short_operand" "r,I"))) (clobber (match_scratch:SI 3 "=q,q"))] "" @@ -434,8 +461,8 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r")) (clobber (match_scratch:SI 4 "=q"))] @@ -445,10 +472,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (mult:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 4 "=q"))] "" @@ -460,10 +487,10 @@ ;; ??? At some point, see what, if anything, we can do about if (x % y == 0). (define_insn "divmodsi4" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (div:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r"))) - (set (match_operand:SI 3 "gen_reg_operand" "=q") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r"))) + (set (match_operand:SI 3 "gpc_reg_operand" "=q") (mod:SI (match_dup 1) (match_dup 2)))] "" "divs %0,%1,%2") @@ -471,8 +498,8 @@ ;; For powers of two we can do srai/aze for divide and then adjust for ;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used. (define_expand "divsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (div:SI (match_operand:SI 1 "gen_reg_operand" "") + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" "")))] "" " @@ -484,11 +511,11 @@ (define_expand "modsi3" [(set (match_dup 3) - (div:SI (match_operand:SI 1 "gen_reg_operand" "") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" ""))) (parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5))) (clobber (scratch:SI))]) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (minus:SI (match_dup 1) (match_dup 4)))] "" " @@ -504,15 +531,15 @@ }") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (div:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "N")))] "exact_log2 (INTVAL (operands[2])) >= 0" "srai %0,%1,%p2\;aze %0,%0") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (div:SI (match_operand:SI 1 "gen_reg_operand" "r") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "N"))) (clobber (match_scratch:SI 3 "=r"))] "exact_log2 (INTVAL (operands[2])) >= 0" @@ -521,27 +548,27 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (div:SI (match_operand:SI 1 "gen_reg_operand" "r") + (div:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "N"))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (div:SI (match_dup 1) (match_dup 2)))] "exact_log2 (INTVAL (operands[2])) >= 0" "srai %0,%1,%p2\;aze. %0,%0" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (udiv:SI (plus:DI (lshift:DI - (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r")) + (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 32)) - (zero_extend:DI (match_operand:SI 2 "register_operand" "*q"))) - (match_operand:SI 3 "gen_reg_operand" "r"))) - (set (match_operand:SI 4 "register_operand" "=*q") + (zero_extend:DI (match_operand:SI 4 "register_operand" "2"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) + (set (match_operand:SI 2 "register_operand" "=*q") (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 1)) (const_int 32)) - (zero_extend:DI (match_dup 2))) + (zero_extend:DI (match_dup 4))) (match_dup 3)))] "" @@ -587,10 +614,10 @@ }") (define_expand "udivmodsi4" - [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "") - (udiv:SI (match_operand:SI 1 "gen_reg_operand" "") + [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") + (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "reg_or_cint_operand" ""))) - (set (match_operand:SI 3 "gen_reg_operand" "") + (set (match_operand:SI 3 "gpc_reg_operand" "") (umod:SI (match_dup 1) (match_dup 2)))])] "" " @@ -616,8 +643,8 @@ }") (define_insn "andsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r") - (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") (match_operand:SI 2 "and_operand" "?r,L,K,J"))) (clobber (match_scratch:CC 3 "=X,X,x,x"))] "" @@ -629,7 +656,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") - (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") (match_operand:SI 2 "and_operand" "r,K,J,L")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r,r,r"))] @@ -643,10 +670,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x") - (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r") + (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") (match_operand:SI 2 "and_operand" "r,K,J,L")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") (and:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -656,9 +683,49 @@ rlinm. %0,%1,0,%m2,%M2" [(set_attr "type" "compare,compare,compare,delayed_compare")]) -(define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r") - (ior:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r") +;; Take a AND with a constant that cannot be done in a single insn and try to +;; split it into two insns. This does not verify that the insns are valid +;; since this need not be done as combine will do it. + +(define_split + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (and:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "non_and_cint_operand" "")))] + "" + [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3))) + (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))] + " +{ + int maskval = INTVAL (operands[2]); + int i, transitions, last_bit_value; + int orig = maskval, first_c = maskval, second_c; + + /* We know that MASKVAL must have more than 2 bit-transitions. Start at + the low-order bit and count for the third transition. When we get there, + make a first mask that has everything to the left of that position + a one. Then make the second mask to turn off whatever else is needed. */ + + for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++) + { + if (((maskval >>= 1) & 1) != last_bit_value) + last_bit_value ^= 1, transitions++; + + if (transitions > 2) + { + first_c |= (~0) << i; + break; + } + } + + second_c = orig | ~ first_c; + + operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c); + operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c); +}") + +(define_insn "iorsi3" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") + (ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") (match_operand:SI 2 "logical_operand" "r,K,J")))] "" "@ @@ -668,8 +735,8 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -678,37 +745,35 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (match_dup 1) (match_dup 2)))] "" "or. %0,%1,%2" [(set_attr "type" "compare")]) -(define_expand "iorsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (ior:SI (match_operand:SI 1 "gen_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")))] - "" - " +;; Split an IOR that we can't do in one insn into two insns, each of which +;; does one 16-bit part. This is used by combine. + +(define_split + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "non_logical_cint_operand" "")))] + "" + [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3))) + (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))] +" { - if (GET_CODE (operands[2]) == CONST_INT - && ! logical_operand (operands[2], SImode)) - { - emit_insn (gen_iorsi3 (operands[0], operands[1], - gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]) & 0xffff0000))); - operands[1] = operands[0]; - operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]) & 0xffff); - } + operands[3] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) & 0xffff0000); + operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); }") -(define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r") - (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r") +(define_insn "xorsi3" + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") + (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r") (match_operand:SI 2 "logical_operand" "r,K,J")))] "" "@ @@ -718,8 +783,8 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -728,45 +793,43 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r") - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (xor:SI (match_dup 1) (match_dup 2)))] "" "xor. %0,%1,%2" [(set_attr "type" "compare")]) -(define_expand "xorsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (xor:SI (match_operand:SI 1 "gen_reg_operand" "") - (match_operand:SI 2 "reg_or_cint_operand" "")))] - "" - " +;; Split an XOR that we can't do in one insn into two insns, each of which +;; does one 16-bit part. This is used by combine. + +(define_split + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "non_logical_cint_operand" "")))] + "" + [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3))) + (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))] +" { - if (GET_CODE (operands[2]) == CONST_INT - && ! logical_operand (operands[2], SImode)) - { - emit_insn (gen_xorsi3 (operands[0], operands[1], - gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]) & 0xffff0000))); - operands[1] = operands[0]; - operands[2] = gen_rtx (CONST_INT, VOIDmode, - INTVAL (operands[2]) & 0xffff); - } + operands[3] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[2]) & 0xffff0000); + operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff); }") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r") - (match_operand:SI 2 "gen_reg_operand" "r"))))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "eqv %0,%1,%2") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r") - (match_operand:SI 2 "gen_reg_operand" "r"))) + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -775,26 +838,26 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r") - (match_operand:SI 2 "gen_reg_operand" "r"))) + (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") + (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (not:SI (xor:SI (match_dup 1) (match_dup 2))))] "" "eqv. %0,%1,%2" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "r")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")))] "" "andc %0,%2,%1") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -803,26 +866,26 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (not:SI (match_dup 1)) (match_dup 2)))] "" "andc. %0,%2,%1" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "r")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")))] "" "orc %0,%2,%1") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -831,26 +894,26 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "r")) + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (not:SI (match_dup 1)) (match_dup 2)))] "" "orc. %0,%2,%1" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "nand %0,%1,%2") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))) + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -859,26 +922,26 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))) + (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] "" "nand. %0,%1,%2" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))] "" "nor %0,%1,%2") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))) + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -887,10 +950,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))) + (compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) + (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))] "" "nor. %0,%1,%2" @@ -901,108 +964,108 @@ ;; would modify an input register. (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0")) - (and:SI (match_dup 1) - (match_operand:SI 3 "gen_reg_operand" "r"))))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) + (match_operand:SI 1 "gpc_reg_operand" "0")) + (and:SI (match_dup 2) + (match_operand:SI 3 "gpc_reg_operand" "r"))))] "" - "maskir %0,%3,%1") + "maskir %0,%3,%2") (define_insn "" [(set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0")) - (and:SI (match_operand:SI 3 "gen_reg_operand" "r") - (match_dup 1))))] + (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) + (match_operand:SI 1 "gpc_reg_operand" "0")) + (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") + (match_dup 2))))] "" - "maskir %0,%3,%1") + "maskir %0,%3,%2") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (ior:SI (and:SI (match_dup 1) - (match_operand:SI 3 "gen_reg_operand" "r")) - (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0"))))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") + (match_operand:SI 3 "gpc_reg_operand" "r")) + (and:SI (not:SI (match_dup 2)) + (match_operand:SI 1 "gpc_reg_operand" "0"))))] "" - "maskir %0,%3,%1") + "maskir %0,%3,%2") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r") - (match_dup 1)) - (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0"))))] + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) + (and:SI (not:SI (match_dup 2)) + (match_operand:SI 1 "gpc_reg_operand" "0"))))] "" - "maskir %0,%3,%1") + "maskir %0,%3,%2") (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0")) - (and:SI (match_dup 1) - (match_operand:SI 3 "gen_reg_operand" "r"))) - (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") - (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2)) - (and:SI (match_dup 1) (match_dup 3))))] + (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) + (match_operand:SI 1 "gpc_reg_operand" "0")) + (and:SI (match_dup 2) + (match_operand:SI 3 "gpc_reg_operand" "r"))) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) + (and:SI (match_dup 2) (match_dup 3))))] "" - "maskir. %0,%3,%1" + "maskir. %0,%3,%2" [(set_attr "type" "compare")]) (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0")) - (and:SI (match_operand:SI 3 "gen_reg_operand" "r") - (match_dup 1))) + (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")) + (match_operand:SI 1 "gpc_reg_operand" "0")) + (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") + (match_dup 2))) (const_int 0))) (set (match_operand:SI 0 "register_operand" "=r") - (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2)) - (and:SI (match_dup 3) (match_dup 1))))] + (ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1)) + (and:SI (match_dup 3) (match_dup 2))))] "" - "maskir. %0,%3,%1" + "maskir. %0,%3,%2" [(set_attr "type" "compare")]) (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (match_dup 1) - (match_operand:SI 3 "gen_reg_operand" "r")) - (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0"))) - (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") - (ior:SI (and:SI (match_dup 1) (match_dup 3)) - (and:SI (not:SI (match_dup 1)) (match_dup 2))))] + (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r") + (match_operand:SI 3 "gpc_reg_operand" "r")) + (and:SI (not:SI (match_dup 2)) + (match_operand:SI 1 "gpc_reg_operand" "0"))) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (and:SI (match_dup 2) (match_dup 3)) + (and:SI (not:SI (match_dup 2)) (match_dup 1))))] "" - "maskir. %0,%3,%1" + "maskir. %0,%3,%2" [(set_attr "type" "compare")]) (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r") - (match_dup 1)) - (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) - (match_operand:SI 2 "gen_reg_operand" "0"))) - (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") - (ior:SI (and:SI (match_dup 3) (match_dup 1)) - (and:SI (not:SI (match_dup 1)) (match_dup 2))))] + (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r") + (match_operand:SI 2 "gpc_reg_operand" "r")) + (and:SI (not:SI (match_dup 2)) + (match_operand:SI 1 "gpc_reg_operand" "0"))) + (const_int 0))) + (set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ior:SI (and:SI (match_dup 3) (match_dup 2)) + (and:SI (not:SI (match_dup 2)) (match_dup 1))))] "" - "maskir. %0,%3,%1" + "maskir. %0,%3,%2" [(set_attr "type" "compare")]) ;; Rotate and shift insns, in all their variants. These support shifts, ;; field inserts and extracts, and various combinations thereof. (define_insn "insv" - [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") + [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (match_operand:SI 1 "const_int_operand" "i") (match_operand:SI 2 "const_int_operand" "i")) - (match_operand:SI 3 "gen_reg_operand" "r"))] + (match_operand:SI 3 "gpc_reg_operand" "r"))] "" "* { @@ -1015,8 +1078,8 @@ }") (define_insn "extzv" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i") (match_operand:SI 3 "const_int_operand" "i")))] "" @@ -1034,7 +1097,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i") (match_operand:SI 3 "const_int_operand" "i")) (const_int 0))) @@ -1045,6 +1108,23 @@ int start = INTVAL (operands[3]) & 31; int size = INTVAL (operands[2]) & 31; + /* If the bitfield being tested fits in the upper or lower half of a + word, it is possible to use andiu. or andil. to test it. This is + useful because the condition register set-use delay is smaller for + andi[ul]. than for rlinm. This doesn't work when the starting bit + position is 0 because the LT and GT bits may be set wrong. */ + + if ((start > 0 && start + size <= 16) || start >= 16) + { + operands[3] = gen_rtx (CONST_INT, VOIDmode, + ((1 << (16 - (start & 15))) + - (1 << (16 - (start & 15) - size)))); + if (start < 16) + return \"andiu. %4,%1,%3\"; + else + return \"andil. %4,%1,%3\"; + } + if (start + size >= 32) operands[3] = const0_rtx; else @@ -1055,11 +1135,11 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") - (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i") (match_operand:SI 3 "const_int_operand" "i")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] "" "* @@ -1067,6 +1147,12 @@ int start = INTVAL (operands[3]) & 31; int size = INTVAL (operands[2]) & 31; + if (start >= 16 && start + size == 32) + { + operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1); + return \"andil. %0,%1,%3\"; + } + if (start + size >= 32) operands[3] = const0_rtx; else @@ -1076,15 +1162,15 @@ [(set_attr "type" "delayed_compare")]) (define_insn "rotlsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")))] "" "rl%I2nm %0,%1,%h2,0,31") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") - (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] @@ -1094,18 +1180,18 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") - (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (rotate:SI (match_dup 1) (match_dup 2)))] "" "rl%I2nm. %0,%1,%h2,0,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (and:SI (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) (match_operand:SI 3 "mask_operand" "L")))] "" @@ -1114,7 +1200,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) @@ -1126,21 +1212,21 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (and:SI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "" "rl%I2nm. %0,%1,%h2,%m3,%M3" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] "" "rl%I2nm %0,%1,%h2,24,31") @@ -1149,7 +1235,7 @@ [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] @@ -1161,20 +1247,20 @@ [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:QI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] "" "rl%I2nm. %0,%1,%h2,24,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] "" "rl%I2nm %0,%1,%h2,16,31") @@ -1183,7 +1269,7 @@ [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] @@ -1195,10 +1281,10 @@ [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC (zero_extend:SI (subreg:HI - (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r") + (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] "" "rl%I2nm. %0,%1,%h2,16,31" @@ -1208,8 +1294,8 @@ ;; SHIFT_COUNT_TRUNCATED. (define_insn "ashlsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) (clobber (match_scratch:SI 3 "=q,X"))] "" @@ -1219,7 +1305,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") - (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r")) @@ -1232,10 +1318,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") - (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ashift:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 4 "=q,X"))] "" @@ -1245,8 +1331,8 @@ [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "L")))] "includes_lshift_p (operands[2], operands[3])" @@ -1255,7 +1341,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r") + (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) @@ -1267,29 +1353,31 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r") + (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "includes_lshift_p (operands[2], operands[3])" "rlinm. %0,%h1,%h2,%m3,%M3" [(set_attr "type" "delayed_compare")]) +;; The RS/6000 assembler mis-handles "sri x,x,0", so write that case as +;; "sli x,x,0". (define_insn "lshrsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) (clobber (match_scratch:SI 3 "=q,X"))] "" "@ sre %0,%1,%2 - sri %0,%1,%h2") + s%A2i %0,%1,%h2") (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r")) @@ -1297,26 +1385,26 @@ "" "@ sre. %3,%1,%2 - sri. %3,%1,%h2" + s%A2i. %3,%1,%h2" [(set_attr "type" "delayed_compare")]) (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") - (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (lshiftrt:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 4 "=q,X"))] "" "@ sre. %0,%1,%2 - sri. %0,%1,%h2" + s%A2i. %0,%1,%h2" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "L")))] "includes_rshift_p (operands[2], operands[3])" @@ -1325,7 +1413,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) @@ -1337,21 +1425,21 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) (match_operand:SI 3 "mask_operand" "L")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] "includes_rshift_p (operands[2], operands[3])" "rlinm. %0,%1,%s2,%m3,%M3" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:QI - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)))] "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" "rlinm %0,%1,%s2,24,31") @@ -1361,7 +1449,7 @@ (compare:CC (zero_extend:SI (subreg:QI - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] @@ -1374,20 +1462,20 @@ (compare:CC (zero_extend:SI (subreg:QI - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))" "rlinm. %0,%1,%s2,24,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)))] "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" "rlinm %0,%1,%s2,16,31") @@ -1397,7 +1485,7 @@ (compare:CC (zero_extend:SI (subreg:HI - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)) (const_int 0))) (clobber (match_scratch:SI 3 "=r"))] @@ -1410,46 +1498,46 @@ (compare:CC (zero_extend:SI (subreg:HI - (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "const_int_operand" "i")) 0)) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))" "rlinm. %0,%1,%s2,16,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") + [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 1) - (match_operand:SI 1 "gen_reg_operand" "r")) - (ashiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r") + (match_operand:SI 1 "gpc_reg_operand" "r")) + (ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 31)))] "" "rrib %0,%1,%2") (define_insn "" - [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") + [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 1) - (match_operand:SI 1 "gen_reg_operand" "r")) - (lshiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r") + (match_operand:SI 1 "gpc_reg_operand" "r")) + (lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 31)))] "" "rrib %0,%1,%2") (define_insn "" - [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r") + [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") (const_int 1) - (match_operand:SI 1 "gen_reg_operand" "r")) - (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r") + (match_operand:SI 1 "gpc_reg_operand" "r")) + (zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r") (const_int 1) (const_int 0)))] "" "rrib %0,%1,%2") (define_insn "ashrsi3" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i"))) (clobber (match_scratch:SI 3 "=q,X"))] "" @@ -1459,7 +1547,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) (clobber (match_scratch:SI 3 "=r,r")) @@ -1472,10 +1560,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") - (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,i")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ashiftrt:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 4 "=q,X"))] "" @@ -1486,10 +1574,10 @@ (define_expand "extendqisi2" [(parallel [(set (match_dup 2) - (ashift:SI (match_operand:QI 1 "gen_reg_operand" "") + (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") (const_int 24))) (clobber (scratch:SI))]) - (parallel [(set (match_operand:SI 0 "gen_reg_operand" "") + (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") (ashiftrt:SI (match_dup 2) (const_int 24))) (clobber (scratch:SI))])] @@ -1500,10 +1588,10 @@ (define_expand "extendqihi2" [(parallel [(set (match_dup 2) - (ashift:SI (match_operand:QI 1 "gen_reg_operand" "") + (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "") (const_int 24))) (clobber (scratch:SI))]) - (parallel [(set (match_operand:HI 0 "gen_reg_operand" "") + (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "") (ashiftrt:SI (match_dup 2) (const_int 24))) (clobber (scratch:SI))])] @@ -1528,8 +1616,8 @@ ;; is not guaranteed. Perhaps this should be tightened up at some point. (define_insn "extendsfdf2" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (float_extend:DF (match_operand:SF 1 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))] "" "* { @@ -1541,8 +1629,8 @@ [(set_attr "type" "fp")]) (define_insn "truncdfsf2" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (float_truncate:SF (match_operand:DF 1 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))] "" "* { @@ -1554,179 +1642,179 @@ [(set_attr "type" "fp")]) (define_insn "negsf2" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (neg:SF (match_operand:SF 1 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] "" "fneg %0,%1" [(set_attr "type" "fp")]) (define_insn "abssf2" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (abs:SF (match_operand:SF 1 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))] "" "fabs %0,%1" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (neg:SF (abs:SF (match_operand:SF 1 "gen_reg_operand" "f"))))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))] "" "fnabs %0,%1" [(set_attr "type" "fp")]) (define_insn "addsf3" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (plus:SF (match_operand:SF 1 "gen_reg_operand" "%f") - (match_operand:SF 2 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f")))] "" "fa %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "subsf3" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (minus:SF (match_operand:SF 1 "gen_reg_operand" "f") - (match_operand:SF 2 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (minus:SF (match_operand:SF 1 "gpc_reg_operand" "f") + (match_operand:SF 2 "gpc_reg_operand" "f")))] "" "fs %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "mulsf3" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f") - (match_operand:SF 2 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f")))] "" "fm %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "divsf3" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (div:SF (match_operand:SF 1 "gen_reg_operand" "f") - (match_operand:SF 2 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (div:SF (match_operand:SF 1 "gpc_reg_operand" "f") + (match_operand:SF 2 "gpc_reg_operand" "f")))] "" "fd %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f") - (match_operand:SF 2 "gen_reg_operand" "f")) - (match_operand:SF 3 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f")) + (match_operand:SF 3 "gpc_reg_operand" "f")))] "" "fma %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f") - (match_operand:SF 2 "gen_reg_operand" "f")) - (match_operand:SF 3 "gen_reg_operand" "f")))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f")) + (match_operand:SF 3 "gpc_reg_operand" "f")))] "" "fms %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f") - (match_operand:SF 2 "gen_reg_operand" "f")) - (match_operand:SF 3 "gen_reg_operand" "f"))))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f")) + (match_operand:SF 3 "gpc_reg_operand" "f"))))] "" "fnma %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:SF 0 "gen_reg_operand" "=f") - (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f") - (match_operand:SF 2 "gen_reg_operand" "f")) - (match_operand:SF 3 "gen_reg_operand" "f"))))] + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f") + (match_operand:SF 2 "gpc_reg_operand" "f")) + (match_operand:SF 3 "gpc_reg_operand" "f"))))] "" "fnms %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "negdf2" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (neg:DF (match_operand:DF 1 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] "" "fneg %0,%1" [(set_attr "type" "fp")]) (define_insn "absdf2" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (abs:DF (match_operand:DF 1 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))] "" "fabs %0,%1" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (neg:DF (abs:DF (match_operand:DF 1 "gen_reg_operand" "f"))))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))] "" "fnabs %0,%1" [(set_attr "type" "fp")]) (define_insn "adddf3" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (plus:DF (match_operand:DF 1 "gen_reg_operand" "%f") - (match_operand:DF 2 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f") + (match_operand:DF 2 "gpc_reg_operand" "f")))] "" "fa %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "subdf3" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (minus:DF (match_operand:DF 1 "gen_reg_operand" "f") - (match_operand:DF 2 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (minus:DF (match_operand:DF 1 "gpc_reg_operand" "f") + (match_operand:DF 2 "gpc_reg_operand" "f")))] "" "fs %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "muldf3" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f") - (match_operand:DF 2 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") + (match_operand:DF 2 "gpc_reg_operand" "f")))] "" "fm %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "divdf3" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (div:DF (match_operand:DF 1 "gen_reg_operand" "f") - (match_operand:DF 2 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (div:DF (match_operand:DF 1 "gpc_reg_operand" "f") + (match_operand:DF 2 "gpc_reg_operand" "f")))] "" "fd %0,%1,%2" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f") - (match_operand:DF 2 "gen_reg_operand" "f")) - (match_operand:DF 3 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") + (match_operand:DF 2 "gpc_reg_operand" "f")) + (match_operand:DF 3 "gpc_reg_operand" "f")))] "" "fma %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f") - (match_operand:DF 2 "gen_reg_operand" "f")) - (match_operand:DF 3 "gen_reg_operand" "f")))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") + (match_operand:DF 2 "gpc_reg_operand" "f")) + (match_operand:DF 3 "gpc_reg_operand" "f")))] "" "fms %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f") - (match_operand:DF 2 "gen_reg_operand" "f")) - (match_operand:DF 3 "gen_reg_operand" "f"))))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") + (match_operand:DF 2 "gpc_reg_operand" "f")) + (match_operand:DF 3 "gpc_reg_operand" "f"))))] "" "fnma %0,%1,%2,%3" [(set_attr "type" "fp")]) (define_insn "" - [(set (match_operand:DF 0 "gen_reg_operand" "=f") - (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f") - (match_operand:DF 2 "gen_reg_operand" "f")) - (match_operand:DF 3 "gen_reg_operand" "f"))))] + [(set (match_operand:DF 0 "gpc_reg_operand" "=f") + (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f") + (match_operand:DF 2 "gpc_reg_operand" "f")) + (match_operand:DF 3 "gpc_reg_operand" "f"))))] "" "fnms %0,%1,%2,%3" [(set_attr "type" "fp")]) @@ -1735,10 +1823,10 @@ (define_expand "floatsidf2" [(set (match_dup 2) (plus:DI (zero_extend:DI - (xor:SI (match_operand:SI 1 "gen_reg_operand" "") + (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_dup 3))) (match_dup 4))) - (set (match_operand:DF 0 "gen_reg_operand" "") + (set (match_operand:DF 0 "gpc_reg_operand" "") (minus:DF (subreg:DF (match_dup 2) 0) (match_dup 5)))] "" @@ -1759,9 +1847,9 @@ (define_expand "floatunssidf2" [(set (match_dup 2) - (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "")) + (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) (match_dup 3))) - (set (match_operand:DF 0 "gen_reg_operand" "") + (set (match_operand:DF 0 "gpc_reg_operand" "") (minus:DF (subreg:DF (match_dup 2) 0) (match_dup 4)))] "" @@ -1780,9 +1868,9 @@ ;; For the above two cases, we always split. (define_split - [(set (match_operand:DI 0 "gen_reg_operand" "") + [(set (match_operand:DI 0 "gpc_reg_operand" "") (plus:DI (zero_extend:DI - (xor:SI (match_operand:SI 1 "gen_reg_operand" "") + (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "logical_operand" ""))) (match_operand:DI 3 "immediate_operand" "")))] "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD @@ -1797,9 +1885,9 @@ }") (define_insn "" - [(set (match_operand:DI 0 "gen_reg_operand" "=r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") (plus:DI (zero_extend:DI - (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r") + (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r") (match_operand:SI 2 "logical_operand" "rKJ"))) (match_operand:DI 3 "immediate_operand" "n")))] "HOST_BITS_PER_INT == BITS_PER_WORD @@ -1808,8 +1896,8 @@ "#") (define_split - [(set (match_operand:DI 0 "gen_reg_operand" "=") - (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "")) + [(set (match_operand:DI 0 "gpc_reg_operand" "=") + (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) (match_operand:DI 2 "immediate_operand" "")))] "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD && GET_CODE (operands[2]) == CONST_DOUBLE @@ -1826,11 +1914,19 @@ emit_move_insn (operands[3], operands[4]); DONE; } + + if (rtx_equal_p (operands[1], operands[3])) + { + rtx temp; + + temp = operands[3]; operands[3] = operands[5]; operands[5] = temp; + temp = operands[4]; operands[4] = operands[1]; operands[1] = temp; + } }") (define_insn "" - [(set (match_operand:DI 0 "gen_reg_operand" "=r") - (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r")) + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) (match_operand:DI 2 "immediate_operand" "n")))] "HOST_BITS_PER_INT == BITS_PER_WORD && GET_CODE (operands[2]) == CONST_DOUBLE @@ -1838,8 +1934,8 @@ "#") (define_expand "fix_truncdfsi2" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (fix:DF (match_operand:DF 1 "gen_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))] "" " { @@ -1849,8 +1945,8 @@ }") (define_expand "fixuns_truncdfsi2" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (unsigned_fix:DF (match_operand:DF 1 "gen_reg_operand" "")))] + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (unsigned_fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))] "" " { @@ -1880,12 +1976,12 @@ }") (define_expand "trunc_call_rtl" - [(set (reg:DF 33) (match_operand:DF 1 "gen_reg_operand" "")) + [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" "")) (use (reg:DF 33)) (parallel [(set (reg:SI 3) (call (mem:SI (match_operand 2 "" "")) (const_int 0))) (clobber (scratch:SI))]) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (reg:SI 3))] "" " @@ -1896,29 +1992,29 @@ ;; Define the DImode operations that can be done in a small number ;; of instructions. (define_insn "adddi3" - [(set (match_operand:DI 0 "gen_reg_operand" "=r") - (plus:DI (match_operand:DI 1 "gen_reg_operand" "%r") - (match_operand:DI 2 "gen_reg_operand" "r")))] + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r") + (match_operand:DI 2 "gpc_reg_operand" "r")))] "" "a %L0,%L1,%L2\;ae %0,%1,%2") (define_insn "subdi3" - [(set (match_operand:DI 0 "gen_reg_operand" "=r") - (minus:DI (match_operand:DI 1 "gen_reg_operand" "r") - (match_operand:DI 2 "gen_reg_operand" "r")))] + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (minus:DI (match_operand:DI 1 "gpc_reg_operand" "r") + (match_operand:DI 2 "gpc_reg_operand" "r")))] "" "sf %L0,%L2,%L1\;sfe %0,%2,%1") -(define_insn "negdi3" - [(set (match_operand:DI 0 "gen_reg_operand" "=r") - (neg:DI (match_operand:DI 1 "gen_reg_operand" "r")))] +(define_insn "negdi2" + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))] "" "sfi %L0,%L1,0\;sfze %0,%1") (define_insn "mulsidi3" - [(set (match_operand:DI 0 "gen_reg_operand" "=r") - (mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "r")) - (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r")))) + [(set (match_operand:DI 0 "gpc_reg_operand" "=r") + (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")) + (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r")))) (clobber (match_scratch:SI 3 "=q"))] "" "mul %0,%1,%2\;mfmq %L0") @@ -1927,8 +2023,8 @@ ;; operands 0 and 1 (the usual case) can be in the same register. That's ;; why we have the strange constraints below. (define_insn "ashldi3" - [(set (match_operand:DI 0 "gen_reg_operand" "=r,r,r,&r") - (ashift:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r") + (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) (clobber (match_scratch:SI 3 "=X,q,q,q"))] "" @@ -1936,26 +2032,26 @@ sli %0,%L1,%h2\;cal %L0,0(0) sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 - sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 ") + sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2") (define_insn "lshrdi3" - [(set (match_operand:DI 0 "gen_reg_operand" "=r,r,r,&r") - (lshiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r") + (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r") (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r"))) (clobber (match_scratch:SI 3 "=X,q,q,q"))] "" "@ - cal %0,0(0)\;sri %L0,%1,%h2 - sr%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2 - sr%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2 - sr%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2 ") + cal %0,0(0)\;s%A2i %L0,%1,%h2 + sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 + sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2 + sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2") ;; Shift by a variable amount is too complex to be worth open-coding. We ;; just handle shifts by constants. (define_expand "ashrdi3" - [(parallel [(set (match_operand:DI 0 "gen_reg_operand" "=") - (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "") + [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=") + (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") (match_operand:SI 2 "general_operand" ""))) (clobber (match_scratch:SI 3 ""))])] "" @@ -1965,14 +2061,14 @@ }") (define_insn "" - [(set (match_operand:DI 0 "gen_reg_operand" "=r,r") - (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r") + [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") + (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "const_int_operand" "M,i"))) (clobber (match_scratch:SI 3 "=X,q"))] "" "@ srai %0,%1,31\;srai %L0,%1,%h2 - sraiq %L0,%L1,%2\;srlq %0,%1,%2") + sraiq %0,%1,%h2\;srliq %L0,%L1,%h2") ;; Now define ways of moving data around. ;; @@ -2007,10 +2103,10 @@ }") (define_insn "" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*h") - (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r"))] - "gen_reg_operand (operands[0], SImode) - || gen_reg_operand (operands[1], SImode)" + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l") + (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r"))] + "gpc_reg_operand (operands[0], SImode) + || gpc_reg_operand (operands[1], SImode)" "@ ai %0,%1,0 l%U1%X1 %0,%1 @@ -2018,14 +2114,35 @@ cal %0,%1(0) cau %0,0,%u1 mf%1 %0 + mt%0 %1 mt%0 %1" - [(set_attr "type" "*,load,*,*,*,*,*")]) + [(set_attr "type" "*,load,*,*,*,*,*,mtlr")]) + +;; Split a load of a large constant into the appropriate two-insn +;; sequence. + +(define_split + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (match_operand:SI 1 "const_int_operand" ""))] + "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000 + && (INTVAL (operands[1]) & 0xffff) != 0" + [(set (match_dup 0) + (match_dup 2)) + (set (match_dup 0) + (ior:SI (match_dup 0) + (match_dup 3)))] + " +{ + operands[2] = gen_rtx (CONST_INT, VOIDmode, + INTVAL (operands[1]) & 0xffff0000); + operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff); +}") (define_insn "" [(set (match_operand:CC 2 "cc_reg_operand" "=x") - (compare:CC (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") (match_dup 1))] + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))] "" "ai. %0,%1,0" [(set_attr "type" "compare")]) @@ -2046,8 +2163,8 @@ (define_insn "" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h") (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))] - "gen_reg_operand (operands[0], HImode) - || gen_reg_operand (operands[1], HImode)" + "gpc_reg_operand (operands[0], HImode) + || gpc_reg_operand (operands[1], HImode)" "@ oril %0,%1,0 lhz%U1%X1 %0,%1 @@ -2073,8 +2190,8 @@ (define_insn "" [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h") (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))] - "gen_reg_operand (operands[0], QImode) - || gen_reg_operand (operands[1], QImode)" + "gpc_reg_operand (operands[0], QImode) + || gpc_reg_operand (operands[1], QImode)" "@ oril %0,%1,0 lbz%U1%X1 %0,%1 @@ -2198,7 +2315,7 @@ }") (define_insn "" - [(set (match_operand:SF 0 "gen_reg_operand" "=r,r") + [(set (match_operand:SF 0 "gpc_reg_operand" "=r,r") (match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))] "REGNO (operands[0]) <= 31" "@ @@ -2207,7 +2324,7 @@ [(set_attr "type" "*,load")]) (define_split - [(set (match_operand:SF 0 "gen_reg_operand" "") + [(set (match_operand:SF 0 "gpc_reg_operand" "") (match_operand:SF 1 "easy_fp_constant" ""))] "reload_completed && REGNO (operands[0]) <= 31" [(set (match_dup 2) (match_dup 3))] @@ -2218,8 +2335,8 @@ (define_insn "" [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m") (match_operand:SF 1 "input_operand" "f,m,f"))] - "gen_reg_operand (operands[0], SFmode) - || gen_reg_operand (operands[1], SFmode)" + "gpc_reg_operand (operands[0], SFmode) + || gpc_reg_operand (operands[1], SFmode)" "@ fmr %0,%1 lfs%U1%X1 %0,%1 @@ -2324,7 +2441,7 @@ }") (define_insn "" - [(set (match_operand:DF 0 "gen_reg_operand" "=r,r") + [(set (match_operand:DF 0 "gpc_reg_operand" "=r,r") (match_operand:DF 1 "mem_or_easy_const_operand" "G,m"))] "REGNO (operands[0]) <= 31" "@ @@ -2333,7 +2450,7 @@ [(set_attr "type" "*,load")]) (define_split - [(set (match_operand:DF 0 "gen_reg_operand" "") + [(set (match_operand:DF 0 "gpc_reg_operand" "") (match_operand:DF 1 "easy_fp_constant" ""))] "reload_completed && REGNO (operands[0]) <= 31" [(set (match_dup 2) (match_dup 3)) @@ -2347,8 +2464,8 @@ (define_insn "" [(set (match_operand:DF 0 "fp_reg_or_mem_operand" "=f,f,m") (match_operand:DF 1 "fp_reg_or_mem_operand" "f,m,f"))] - "gen_reg_operand (operands[0], DFmode) - || gen_reg_operand (operands[1], DFmode)" + "gpc_reg_operand (operands[0], DFmode) + || gpc_reg_operand (operands[1], DFmode)" "@ fmr %0,%1 lfd%U1%X1 %0,%1 @@ -2363,11 +2480,8 @@ "" " { - if (GET_CODE (operands[0]) == MEM) - operands[1] = force_reg (DImode, operands[1]); - - else if (GET_CODE (operands[1]) == CONST_DOUBLE - || GET_CODE (operands[1]) == CONST_INT) + if (GET_CODE (operands[1]) == CONST_DOUBLE + || GET_CODE (operands[1]) == CONST_INT) { emit_move_insn (operand_subword (operands[0], 0, 0, DImode), operand_subword (operands[1], 0, 0, DImode)); @@ -2375,13 +2489,16 @@ operand_subword (operands[1], 1, 0, DImode)); DONE; } + + if (GET_CODE (operands[0]) == MEM) + operands[1] = force_reg (DImode, operands[1]); }") (define_insn "" [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m") (match_operand:DI 1 "input_operand" "r,m,r"))] - "gen_reg_operand (operands[0], DImode) - || gen_reg_operand (operands[1], DImode)" + "gpc_reg_operand (operands[0], DImode) + || gpc_reg_operand (operands[1], DImode)" "* { switch (which_alternative) @@ -2445,8 +2562,8 @@ [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r") (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m")) (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))] - "gen_reg_operand (operands[0], TImode) - || gen_reg_operand (operands[1], TImode)" + "gpc_reg_operand (operands[0], TImode) + || gpc_reg_operand (operands[1], TImode)" "* { switch (which_alternative) @@ -2492,9 +2609,9 @@ [(set_attr "type" "*,load,load,*,*")]) (define_expand "load_multiple" - [(match_parallel 3 "" [(set (match_operand:SI 0 "" "") - (match_operand:SI 1 "" "")) - (use (match_operand:SI 2 "" ""))])] + [(match_par_dup 3 [(set (match_operand:SI 0 "" "") + (match_operand:SI 1 "" "")) + (use (match_operand:SI 2 "" ""))])] "" " { @@ -2528,7 +2645,7 @@ (define_insn "" [(match_parallel 0 "load_multiple_operation" - [(set (match_operand:SI 1 "gen_reg_operand" "=r") + [(set (match_operand:SI 1 "gpc_reg_operand" "=r") (match_operand:SI 2 "indirect_operand" "Q"))])] "" "* @@ -2557,10 +2674,10 @@ [(set_attr "type" "load")]) (define_expand "store_multiple" - [(match_parallel 3 "" [(set (match_operand:SI 0 "" "") - (match_operand:SI 1 "" "")) - (clobber (scratch:SI)) - (use (match_operand:SI 2 "" ""))])] + [(match_par_dup 3 [(set (match_operand:SI 0 "" "") + (match_operand:SI 1 "" "")) + (clobber (scratch:SI)) + (use (match_operand:SI 2 "" ""))])] "" " { @@ -2601,7 +2718,7 @@ (define_insn "" [(match_parallel 0 "store_multiple_operation" [(set (match_operand:SI 1 "indirect_operand" "=Q") - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (clobber (match_scratch:SI 3 "=q"))])] "" "stsi %2,%P1,%O0") @@ -2616,170 +2733,168 @@ ;; that will benefit the most). (define_insn "" - [(set (match_operand:SI 3 "gen_reg_operand" "=r,r") - (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") + (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - lux %3,%1,%2 - lu %3,%2(%1)" + lux %3,%0,%2 + lu %3,%2(%0)" [(set_attr "type" "load,load")]) (define_insn "" - [(set (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))) - (match_operand:SI 3 "gen_reg_operand" "r,r")) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (match_operand:SI 3 "gpc_reg_operand" "r,r")) + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - stux %3,%1,%2 - stu %3,%2(%1)") + stux %3,%0,%2 + stu %3,%2(%0)") (define_insn "" - [(set (match_operand:HI 3 "gen_reg_operand" "=r,r") - (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") + (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - lhzux %3,%1,%2 - lhzu %3,%2(%1)" + lhzux %3,%0,%2 + lhzu %3,%2(%0)" [(set_attr "type" "load,load")]) (define_insn "" - [(set (match_operand:SI 3 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") (zero_extend:SI - (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - lhzux %3,%1,%2 - lhzu %3,%2(%1)" + lhzux %3,%0,%2 + lhzu %3,%2(%0)" [(set_attr "type" "load,load")]) (define_insn "" - [(set (match_operand:SI 3 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") (sign_extend:SI - (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - lhaux %3,%1,%2 - lhau %3,%2(%1)" + lhaux %3,%0,%2 + lhau %3,%2(%0)" [(set_attr "type" "load,load")]) (define_insn "" - [(set (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))) - (match_operand:HI 3 "gen_reg_operand" "r,r")) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (match_operand:HI 3 "gpc_reg_operand" "r,r")) + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - sthux %3,%1,%2 - sthu %3,%2(%1)" + sthux %3,%0,%2 + sthu %3,%2(%0)" [(set_attr "type" "load,load")]) (define_insn "" - [(set (match_operand:QI 3 "gen_reg_operand" "=r,r") - (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") + (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - lbzux %3,%1,%2 - lbzu %3,%2(%1)" + lbzux %3,%0,%2 + lbzu %3,%2(%0)" [(set_attr "type" "load,load")]) (define_insn "" - [(set (match_operand:SI 3 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") (zero_extend:SI - (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - lbzux %3,%1,%2 - lbzu %3,%2(%1)" + lbzux %3,%0,%2 + lbzu %3,%2(%0)" [(set_attr "type" "load,load")]) (define_insn "" - [(set (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))) - (match_operand:QI 3 "gen_reg_operand" "r,r")) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (match_operand:QI 3 "gpc_reg_operand" "r,r")) + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - stbux %3,%1,%2 - stbu %3,%2(%1)") + stbux %3,%0,%2 + stbu %3,%2(%0)") (define_insn "" - [(set (match_operand:SF 3 "gen_reg_operand" "=f,f") - (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") + (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - lfsux %3,%1,%2 - lfsu %3,%2(%1)" + lfsux %3,%0,%2 + lfsu %3,%2(%0)" [(set_attr "type" "load,load")]) (define_insn "" - [(set (mem:SF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))) - (match_operand:SF 3 "gen_reg_operand" "f,f")) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (match_operand:SF 3 "gpc_reg_operand" "f,f")) + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - frsp %3,%3\;stfsux %3,%1,%2 - frsp %3,%3\;stfsu %3,%2(%1)") + frsp %3,%3\;stfsux %3,%0,%2 + frsp %3,%3\;stfsu %3,%2(%0)") (define_insn "" - [(set (match_operand:DF 3 "gen_reg_operand" "=f,f") - (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f") + (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I")))) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - lfdux %3,%1,%2 - lfdu %3,%2(%1)" + lfdux %3,%0,%2 + lfdu %3,%2(%0)" [(set_attr "type" "load,load")]) (define_insn "" - [(set (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0") + [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") (match_operand:SI 2 "reg_or_short_operand" "r,I"))) - (match_operand:DF 3 "gen_reg_operand" "f,f")) - (set (match_operand:SI 0 "gen_reg_operand" "=b,b") + (match_operand:DF 3 "gpc_reg_operand" "f,f")) + (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") (plus:SI (match_dup 1) (match_dup 2)))] "" "@ - stfdux %3,%1,%2 - stfdu %3,%2(%1)") + stfdux %3,%0,%2 + stfdu %3,%2(%0)") ;; Next come insns related to the calling sequence. ;; ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). -;; We move the back-chain and decremement the stack pointer. This is slightly -;; less efficient than it needs to be for long constants, but that case -;; should be rare. +;; We move the back-chain and decrement the stack pointer. (define_expand "allocate_stack" [(set (reg:SI 1) - (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_cint_operand" "")))] + (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))] "" " { rtx chain = gen_reg_rtx (SImode); @@ -2790,6 +2905,63 @@ emit_move_insn (stack_bot, chain); DONE; }") + +;; These patterns say how to save and restore the stack pointer. We need not +;; save the stack pointer at function level since we are careful to +;; preserve the backchain. At block level, we have to restore the backchain +;; when we restore the stack pointer. +;; +;; For nonlocal gotos, we must save both the stack pointer and its +;; backchain and restore both. Note that in the nonlocal case, the +;; save area is a memory location. + +(define_expand "save_stack_function" + [(use (const_int 0))] + "" + "") + +(define_expand "restore_stack_function" + [(use (const_int 0))] + "" + "") + +(define_expand "restore_stack_block" + [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" ""))) + (set (match_dup 0) (match_operand:SI 1 "register_operand" "")) + (set (mem:SI (match_dup 0)) (match_dup 2))] + "" + " +{ operands[2] = gen_reg_rtx (SImode); }") + +(define_expand "save_stack_nonlocal" + [(match_operand:DI 0 "memory_operand" "") + (match_operand:SI 1 "register_operand" "")] + "" + " +{ + rtx temp = gen_reg_rtx (SImode); + + /* Copy the backchain to the first word, sp to the second. */ + emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1])); + emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp); + emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]); + DONE; +}") + +(define_expand "restore_stack_nonlocal" + [(match_operand:SI 0 "register_operand" "") + (match_operand:DI 1 "memory_operand" "")] + "" + " +{ + rtx temp = gen_reg_rtx (SImode); + + /* Restore the backchain from the first word, sp from the second. */ + emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode)); + emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode)); + emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp); + DONE; +}") ;; A function pointer is a pointer to a data area whose first word contains ;; the actual address of the function, whose second word contains a pointer @@ -2802,8 +2974,8 @@ ;; operands[1] is the address of data area of the function to call (define_expand "call_via_ptr" - [(set (match_operand:SI 0 "gen_reg_operand" "") - (mem:SI (match_operand:SI 1 "gen_reg_operand" ""))) + [(set (match_operand:SI 0 "gpc_reg_operand" "") + (mem:SI (match_operand:SI 1 "gpc_reg_operand" ""))) (set (mem:SI (plus:SI (reg:SI 1) (const_int 20))) (reg:SI 2)) (set (reg:SI 2) @@ -2861,14 +3033,14 @@ (define_insn "" [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s")) (match_operand 1 "" "fg,fg")) - (clobber (match_scratch:SI 3 "=l,l"))] + (clobber (match_scratch:SI 2 "=l,l"))] "" "@ brl\;l 2,20(1) bl %z0\;cror 15,15,15") (define_insn "" - [(set (match_operand 0 "" "fg,fg") + [(set (match_operand 0 "" "=fg,fg") (call (mem:SI (match_operand:SI 1 "call_operand" "l,s")) (match_operand 2 "" "fg,fg"))) (clobber (match_scratch:SI 3 "=l,l"))] @@ -2885,7 +3057,7 @@ ;; how it is used. (define_expand "cmpsi" [(set (cc0) - (compare (match_operand:SI 0 "gen_reg_operand" "") + (compare (match_operand:SI 0 "gpc_reg_operand" "") (match_operand:SI 1 "reg_or_short_operand" "")))] "" " @@ -2903,8 +3075,8 @@ }") (define_expand "cmpsf" - [(set (cc0) (compare (match_operand:SF 0 "gen_reg_operand" "") - (match_operand:SF 1 "gen_reg_operand" "")))] + [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "") + (match_operand:SF 1 "gpc_reg_operand" "")))] "" " { @@ -2915,8 +3087,8 @@ }") (define_expand "cmpdf" - [(set (cc0) (compare (match_operand:DF 0 "gen_reg_operand" "") - (match_operand:DF 1 "gen_reg_operand" "")))] + [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "") + (match_operand:DF 1 "gpc_reg_operand" "")))] "" " { @@ -3079,7 +3251,7 @@ ;; the cases we don't want to handle. (define_expand "seq" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (eq:SI (match_dup 2) (const_int 0)))] "" " @@ -3091,7 +3263,7 @@ (define_expand "sne" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (ne:SI (match_dup 2) (const_int 0)))] "" " @@ -3106,7 +3278,7 @@ ;; A > 0 is best done using the portable sequence, so fail in that case. (define_expand "sgt" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (gt:SI (match_dup 2) (const_int 0)))] "" " @@ -3123,7 +3295,7 @@ ;; A < 0 is best done in the portable way for A an integer. (define_expand "slt" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (lt:SI (match_dup 2) (const_int 0)))] "" " @@ -3139,7 +3311,7 @@ (define_expand "sge" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (ge:SI (match_dup 2) (const_int 0)))] "" " @@ -3152,7 +3324,7 @@ ;; A <= 0 is best done the portable way for A an integer. (define_expand "sle" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (le:SI (match_dup 2) (const_int 0)))] "" " @@ -3168,7 +3340,7 @@ (define_expand "sgtu" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (gtu:SI (match_dup 2) (const_int 0)))] "" " @@ -3179,7 +3351,7 @@ (define_expand "sltu" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (ltu:SI (match_dup 2) (const_int 0)))] "" " @@ -3190,7 +3362,7 @@ (define_expand "sgeu" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (geu:SI (match_dup 2) (const_int 0)))] "" " @@ -3201,7 +3373,7 @@ (define_expand "sleu" [(set (match_dup 2) (match_dup 1)) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (leu:SI (match_dup 2) (const_int 0)))] "" " @@ -3213,15 +3385,43 @@ ;; Here are the actual compare insns. (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=y") - (compare:CC (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")))] "" "cmp%I2 %0,%1,%2" [(set_attr "type" "compare")]) +;; If we are comparing a register for equality with a large constant, +;; we can do this with an XOR followed by a compare. But we need a scratch +;; register for the result of the XOR. + +(define_split + [(set (match_operand:CC 0 "cc_reg_operand" "") + (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") + (match_operand:SI 2 "non_short_cint_operand" ""))) + (clobber (match_operand:SI 3 "gpc_reg_operand" ""))] + "find_single_use (operands[0], insn, 0) + && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ + || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)" + [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4))) + (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))] + " +{ + /* Get the constant we are comparing against, C, and see what it looks like + sign-extended to 16 bits. Then see what constant could be XOR'ed + with C to get the sign-extended value. */ + + int c = INTVAL (operands[2]); + int sextc = (c << 16) >> 16; + int xorv = c ^ sextc; + + operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv); + operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc); +}") + (define_insn "" [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") - (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_u_short_operand" "rI")))] "" "cmpl%I2 %0,%1,%W2" @@ -3234,27 +3434,27 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=y") - (compare:CC (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "short_cint_operand" "i"))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] "" "#") (define_insn "" [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") - (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r") + (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "u_short_cint_operand" "i"))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] "" "#") (define_split [(set (match_operand:CC 3 "cc_reg_operand" "") - (compare:CC (match_operand:SI 1 "gen_reg_operand" "") + (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "short_cint_operand" ""))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] "" [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) @@ -3262,9 +3462,9 @@ (define_split [(set (match_operand:CCUNS 3 "cc_reg_operand" "") - (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "") + (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") (match_operand:SI 2 "u_short_cint_operand" ""))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] "" [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) @@ -3272,16 +3472,16 @@ (define_insn "" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") - (compare:CCFP (match_operand:SF 1 "gen_reg_operand" "f") - (match_operand:SF 2 "gen_reg_operand" "f")))] + (compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f") + (match_operand:SF 2 "gpc_reg_operand" "f")))] "" "fcmpu %0,%1,%2" [(set_attr "type" "fpcompare")]) (define_insn "" [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") - (compare:CCFP (match_operand:DF 1 "gen_reg_operand" "f") - (match_operand:DF 2 "gen_reg_operand" "f")))] + (compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f") + (match_operand:DF 2 "gpc_reg_operand" "f")))] "" "fcmpu %0,%1,%2" [(set_attr "type" "fpcompare")]) @@ -3290,9 +3490,11 @@ ;; way the machine works. ;; ;; Note that this is probably faster if we can put an insn between the -;; mfcr and rlinm, but this is tricky. Let's leave it for now. +;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most +;; cases the insns below which don't use an intermediate CR field will +;; be used instead. (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_operator:SI 1 "scc_comparison_operator" [(match_operand 2 "cc_reg_operand" "y") (const_int 0)]))] @@ -3305,14 +3507,14 @@ [(match_operand 2 "cc_reg_operand" "y") (const_int 0)]) (const_int 0))) - (set (match_operand:SI 3 "gen_reg_operand" "=r") + (set (match_operand:SI 3 "gpc_reg_operand" "=r") (match_op_dup 1 [(match_dup 2) (const_int 0)]))] "" "%D1mfcr %3\;rlinm. %3,%3,%J1,30,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (ashift:SI (match_operator:SI 1 "scc_comparison_operator" [(match_operand 2 "cc_reg_operand" "y") (const_int 0)]) @@ -3343,7 +3545,7 @@ (const_int 0)]) (match_operand:SI 3 "const_int_operand" "n")) (const_int 0))) - (set (match_operand:SI 4 "gen_reg_operand" "=r") + (set (match_operand:SI 4 "gpc_reg_operand" "=r") (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) (match_dup 3)))] "" @@ -3365,6 +3567,52 @@ }" [(set_attr "type" "delayed_compare")]) +;; If we are comparing the result of two comparisons, this can be done +;; using creqv or crxor. + +(define_insn "" + [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") + (compare:CCEQ (match_operator 1 "scc_comparison_operator" + [(match_operand 2 "cc_reg_operand" "y") + (const_int 0)]) + (match_operator 3 "scc_comparison_operator" + [(match_operand 4 "cc_reg_operand" "y") + (const_int 0)])))] + "REGNO (operands[2]) != REGNO (operands[4])" + "* +{ + enum rtx_code code1, code2; + + code1 = GET_CODE (operands[1]); + code2 = GET_CODE (operands[3]); + + if ((code1 == EQ || code1 == LT || code1 == GT + || code1 == LTU || code1 == GTU + || (code1 != NE && GET_MODE (operands[2]) == CCFPmode)) + != + (code2 == EQ || code2 == LT || code2 == GT + || code2 == LTU || code2 == GTU + || (code2 != NE && GET_MODE (operands[4]) == CCFPmode))) + return \"%C1%C3crxor %E0,%j1,%j3\"; + else + return \"%C1%C3creqv %E0,%j1,%j3\"; +}") + +;; There is a 3 cycle delay between consecutive mfcr instructions +;; so it is useful to combine 2 scc instructions to use only one mfcr. + +(define_peephole + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (match_operator:SI 1 "scc_comparison_operator" + [(match_operand 2 "cc_reg_operand" "y") + (const_int 0)])) + (set (match_operand:SI 3 "gpc_reg_operand" "=r") + (match_operator:SI 4 "scc_comparison_operator" + [(match_operand 5 "cc_reg_operand" "y") + (const_int 0)]))] + "REGNO (operands[2]) != REGNO (operands[5])" + "%D1%D4mfcr %3\;rlinm %0,%3,%J1,31,31\;rlinm %3,%3,%J4,31,31") + ;; There are some scc insns that can be done directly, without a compare. ;; These are faster because they don't involve the communications between ;; the FXU and branch units. In fact, we will be replacing all of the @@ -3380,8 +3628,8 @@ ;; the cmp/mfcr sequence we would otherwise generate. (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r") - (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") + (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))) (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] "" @@ -3395,10 +3643,10 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x") (compare:CC - (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r") + (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") (eq:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))] "" @@ -3411,10 +3659,10 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r") - (plus:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") + (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) - (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))) + (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))) (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] "" "@ @@ -3428,9 +3676,9 @@ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x") (compare:CC (plus:SI - (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r") + (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) - (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] "" @@ -3446,11 +3694,11 @@ [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x") (compare:CC (plus:SI - (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r") + (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")) - (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))] "" @@ -3463,8 +3711,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r") - (neg:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r") + (neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r") (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))] "" "@ @@ -3476,11 +3724,11 @@ ;; This is what (plus (ne X (const_int 0)) Y) looks like. (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (lshiftrt:SI - (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))) + (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) (const_int 31)) - (match_operand:SI 2 "gen_reg_operand" "r"))) + (match_operand:SI 2 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 3 "=&r"))] "" "ai %3,%1,-1\;aze %0,%2") @@ -3489,9 +3737,9 @@ [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (plus:SI (lshiftrt:SI - (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))) + (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) (const_int 31)) - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=&r"))] "" @@ -3502,11 +3750,11 @@ [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC (plus:SI (lshiftrt:SI - (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))) + (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))) (const_int 31)) - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31)) (match_dup 2))) (clobber (match_scratch:SI 3 "=&r"))] @@ -3515,8 +3763,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O"))) (clobber (match_scratch:SI 3 "=r,X"))] "" @@ -3527,10 +3775,10 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x,x") (compare:CC - (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (le:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 3 "=r,X"))] "" @@ -3540,10 +3788,10 @@ [(set_attr "type" "delayed_compare,compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O")) - (match_operand:SI 3 "gen_reg_operand" "r,r"))) + (match_operand:SI 3 "gpc_reg_operand" "r,r"))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ @@ -3553,9 +3801,9 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O")) - (match_operand:SI 3 "gen_reg_operand" "r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -3567,11 +3815,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O")) - (match_operand:SI 3 "gen_reg_operand" "r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -3581,8 +3829,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (neg:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,O"))))] "" "@ @@ -3590,8 +3838,8 @@ ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")))] "" "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0") @@ -3599,20 +3847,20 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC - (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (leu:SI (match_dup 1) (match_dup 2)))] "" "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 4 "=&r"))] "" "sf%I2 %4,%1,%2\;aze %0,%3") @@ -3620,9 +3868,9 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3632,11 +3880,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x") (compare:CC - (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3644,18 +3892,18 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))))] "" "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (neg:SI - (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))) - (match_operand:SI 3 "gen_reg_operand" "r"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 4 "=&r"))] "" "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4") @@ -3664,9 +3912,9 @@ [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC (and:SI (neg:SI - (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3677,11 +3925,11 @@ [(set (match_operand:CC 5 "cc_reg_operand" "=x") (compare:CC (and:SI (neg:SI - (leu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3689,8 +3937,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (lt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")))] "" "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31") @@ -3698,20 +3946,20 @@ (define_insn "" [(set (match_operand:SI 3 "cc_reg_operand" "=x") (compare:CC - (lt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (lt:SI (match_dup 1) (match_dup 2)))] "" "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 4 "=&r"))] "" "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3") @@ -3719,9 +3967,9 @@ (define_insn "" [(set (match_operand:SI 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3731,11 +3979,11 @@ (define_insn "" [(set (match_operand:SI 5 "cc_reg_operand" "=x") (compare:CC - (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3743,15 +3991,15 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))))] "" "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] "" "@ @@ -3761,10 +4009,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") (compare:CC - (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (ltu:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -3773,8 +4021,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r") - (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") + (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))) (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] @@ -3788,7 +4036,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x") (compare:CC - (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r") + (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")) (const_int 0))) @@ -3804,11 +4052,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x") (compare:CC - (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r") + (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P")) (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r,r,&r,r"))] "" @@ -3820,8 +4068,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (neg:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))] "" "@ @@ -3829,8 +4077,8 @@ ai %0,%1,%n2\;sfe %0,%0,%0") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (ge:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -3839,10 +4087,10 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (ge:SI (match_operand:SI 1 "gen_reg_operand" "r") + (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (ge:SI (match_dup 1) (match_dup 2))) (clobber (match_scratch:SI 3 "=r"))] "" @@ -3850,10 +4098,10 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 4 "=&r"))] "" "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3") @@ -3861,9 +4109,9 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3873,11 +4121,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x") (compare:CC - (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -3885,20 +4133,20 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))))] "" "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0") ;; This is (and (neg (ge X (const_int 0))) Y). (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (neg:SI (lshiftrt:SI - (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) + (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 31))) - (match_operand:SI 2 "gen_reg_operand" "r"))) + (match_operand:SI 2 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 3 "=&r"))] "" "srai %3,%1,31\;andc %0,%2,%3") @@ -3908,9 +4156,9 @@ (compare:CC (and:SI (neg:SI (lshiftrt:SI - (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) + (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 31))) - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=&r"))] "" @@ -3922,11 +4170,11 @@ (compare:CC (and:SI (neg:SI (lshiftrt:SI - (not:SI (match_operand:SI 1 "gen_reg_operand" "r")) + (not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) (const_int 31))) - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1)) (const_int 31))) (match_dup 2))) @@ -3936,8 +4184,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))] "" "@ @@ -3947,10 +4195,10 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x,x") (compare:CC - (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (geu:SI (match_dup 1) (match_dup 2)))] "" "@ @@ -3959,10 +4207,10 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) - (match_operand:SI 3 "gen_reg_operand" "r,r"))) + (match_operand:SI 3 "gpc_reg_operand" "r,r"))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ @@ -3972,9 +4220,9 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) - (match_operand:SI 3 "gen_reg_operand" "r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -3986,11 +4234,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")) - (match_operand:SI 3 "gen_reg_operand" "r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -4000,8 +4248,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (neg:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "r,I"))))] "" "@ @@ -4009,11 +4257,11 @@ sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (and:SI (neg:SI - (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) - (match_operand:SI 3 "gen_reg_operand" "r,r"))) + (match_operand:SI 3 "gpc_reg_operand" "r,r"))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" "@ @@ -4024,9 +4272,9 @@ [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC (and:SI (neg:SI - (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) - (match_operand:SI 3 "gen_reg_operand" "r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -4039,11 +4287,11 @@ [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") (compare:CC (and:SI (neg:SI - (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))) - (match_operand:SI 3 "gen_reg_operand" "r,r")) + (match_operand:SI 3 "gpc_reg_operand" "r,r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -4053,8 +4301,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)))] "" "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31") @@ -4062,18 +4310,18 @@ (define_insn "" [(set (match_operand:CC 2 "cc_reg_operand" "=x") (compare:CC - (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (gt:SI (match_dup 1) (const_int 0)))] "" "sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r")))] "" "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31") @@ -4081,20 +4329,20 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC - (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (gt:SI (match_dup 1) (match_dup 2)))] "" "doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31" [(set_attr "type" "delayed_compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)) - (match_operand:SI 2 "gen_reg_operand" "r"))) + (match_operand:SI 2 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 3 "=&r"))] "" "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2") @@ -4102,9 +4350,9 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)) - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 3 "=&r"))] "" @@ -4114,11 +4362,11 @@ (define_insn "" [(set (match_operand:CC 4 "cc_reg_operand" "=x") (compare:CC - (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0)) - (match_operand:SI 2 "gen_reg_operand" "r")) + (match_operand:SI 2 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) (clobber (match_scratch:SI 3 "=&r"))] "" @@ -4126,10 +4374,10 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r")) - (match_operand:SI 3 "gen_reg_operand" "r"))) + (match_operand:SI 3 "gpc_reg_operand" "r"))) (clobber (match_scratch:SI 4 "=&r"))] "" "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3") @@ -4137,9 +4385,9 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x") (compare:CC - (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -4149,11 +4397,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x") (compare:CC - (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r")) - (match_operand:SI 3 "gen_reg_operand" "r")) + (match_operand:SI 3 "gpc_reg_operand" "r")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r"))] "" @@ -4161,22 +4409,22 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (const_int 0))))] "" "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "r"))))] "" "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31") (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")))] "" "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0") @@ -4184,18 +4432,18 @@ (define_insn "" [(set (match_operand:CC 3 "cc_reg_operand" "=x") (compare:CC - (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r") + (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r") (gtu:SI (match_dup 1) (match_dup 2)))] "" "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0" [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r,r") - (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") + (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "reg_or_short_operand" "r,I"))) (clobber (match_scratch:SI 4 "=&r,&r"))] @@ -4205,7 +4453,7 @@ (define_insn "" [(set (match_operand:CC 0 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "reg_or_short_operand" "r,I")) (const_int 0))) @@ -4217,11 +4465,11 @@ (define_insn "" [(set (match_operand:CC 5 "cc_reg_operand" "=x,x") (compare:CC - (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r") + (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) (match_operand:SI 3 "reg_or_short_operand" "r,I")) (const_int 0))) - (set (match_operand:SI 0 "gen_reg_operand" "=r,r") + (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) (clobber (match_scratch:SI 4 "=&r,&r"))] "" @@ -4229,8 +4477,8 @@ [(set_attr "type" "compare")]) (define_insn "" - [(set (match_operand:SI 0 "gen_reg_operand" "=r") - (neg:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r") + [(set (match_operand:SI 0 "gpc_reg_operand" "=r") + (neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r") (match_operand:SI 2 "reg_or_short_operand" "rI"))))] "" "sf%I2 %0,%1,%2\;sfe %0,%0,%0") @@ -4319,7 +4567,7 @@ (define_insn "" [(set (pc) - (match_operand:SI 0 "register_operand" "c,r")) + (match_operand:SI 0 "register_operand" "c,l")) (use (label_ref (match_operand 1 "" "")))] "" "@ @@ -4387,11 +4635,11 @@ (define_split [(set (pc) (if_then_else (match_operator 2 "comparison_operator" - [(match_operand:SI 1 "gen_reg_operand" "") + [(match_operand:SI 1 "gpc_reg_operand" "") (const_int 1)]) (match_operand 5 "" "") (match_operand 6 "" ""))) - (set (match_operand:SI 0 "gen_reg_operand" "") + (set (match_operand:SI 0 "gpc_reg_operand" "") (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "")) (clobber (match_scratch:SI 4 ""))] @@ -4408,7 +4656,7 @@ (define_split [(set (pc) (if_then_else (match_operator 2 "comparison_operator" - [(match_operand:SI 1 "gen_reg_operand" "") + [(match_operand:SI 1 "gpc_reg_operand" "") (const_int 1)]) (match_operand 5 "" "") (match_operand 6 "" ""))) @@ -4416,7 +4664,7 @@ (plus:SI (match_dup 1) (const_int -1))) (clobber (match_scratch:CC 3 "")) (clobber (match_scratch:SI 4 ""))] - "reload_completed && ! gen_reg_operand (operands[0], SImode)" + "reload_completed && ! gpc_reg_operand (operands[0], SImode)" [(parallel [(set (match_dup 3) (compare:CC (plus:SI (match_dup 1) (const_int -1)) (const_int 0)))