--- gcc/config/rs6000.md	2018/04/24 17:55:07	1.1.1.2
+++ gcc/config/rs6000.md	2018/04/24 18:00:04	1.1.1.3
@@ -48,13 +48,13 @@
 ;; complex forms.  Basic data transfer is done later.
 
 (define_expand "zero_extendqisi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
-	(zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))]
   ""
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
   ""
   "@
@@ -64,7 +64,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r"))
+	(compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 2 "=r"))]
   ""
@@ -73,22 +73,22 @@
 
 (define_insn ""
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
-	(compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r"))
+	(compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(zero_extend:SI (match_dup 1)))]
   ""
   "andil. %0,%1,255"
   [(set_attr "type" "compare")])
 
 (define_expand "zero_extendqihi2"
-  [(set (match_operand:HI 0 "gen_reg_operand" "")
-	(zero_extend:HI (match_operand:QI 1 "gen_reg_operand" "")))]
+  [(set (match_operand:HI 0 "gpc_reg_operand" "")
+	(zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")))]
   ""
   "")
 
 (define_insn ""
-  [(set (match_operand:HI 0 "gen_reg_operand" "=r,r")
+  [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r")
 	(zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
   ""
   "@
@@ -97,13 +97,13 @@
   [(set_attr "type" "load,*")])
 
 (define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "r")
-	(zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "r")
+	(zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
   ""
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
   ""
   "@
@@ -113,7 +113,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
+	(compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 2 "=r"))]
   ""
@@ -122,22 +122,22 @@
 
 (define_insn ""
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
-	(compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
+	(compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(zero_extend:SI (match_dup 1)))]
   ""
   "andil. %0,%1,65535"
   [(set_attr "type" "compare")])
 
 (define_expand "extendhisi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
-	(sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
   ""
   "")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
   ""
   "@
@@ -147,7 +147,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
+	(compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 2 "=r"))]
   ""
@@ -156,18 +156,18 @@
 
 (define_insn ""
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
-	(compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
+	(compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(sign_extend:SI (match_dup 1)))]
   ""
   "exts. %0,%1"
   [(set_attr "type" "compare")])
 
 ;; Fixed-point arithmetic insns.
-(define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(plus:SI (match_operand:SI 1 "gen_reg_operand" "%r,b")
+(define_insn "addsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "%r,b")
 		 (match_operand:SI 2 "add_operand" "rI,J")))]
   ""
   "@
@@ -176,7 +176,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			     (match_operand:SI 2 "reg_or_short_operand" "rI"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
@@ -186,49 +186,48 @@
    
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	(compare:CC (plus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			     (match_operand:SI 2 "reg_or_short_operand" "rI"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "a%I2. %0,%1,%2"
   [(set_attr "type" "compare")])
    
-(define_expand "addsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
-	(plus:SI (match_operand:SI 1 "gen_reg_operand" "")
-		 (match_operand:SI 2 "reg_or_cint_operand" "")))]
-  ""
-  "
+;; Split an add that we can't do in one insn into two insns, each of which
+;; does one 16-bit part.  This is used by combine.  Note that the low-order
+;; add should be last in case the result gets used in an address.
+
+(define_split
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(plus:SI (match_operand:SI 1 "gpc_reg_operand" "")
+		 (match_operand:SI 2 "non_add_cint_operand" "")))]
+  ""
+  [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 3)))
+   (set (match_dup 0) (plus:SI (match_dup 0) (match_dup 4)))]
+"
 {
-  if (GET_CODE (operands[2]) == CONST_INT
-      && (unsigned) (INTVAL (operands[2]) + 0x8000) >= 0x10000
-      && (INTVAL (operands[2]) & 0xffff) != 0)
-    {
-      int low = INTVAL (operands[2]) & 0xffff;
-      int high = (unsigned) INTVAL (operands[2]) >> 16;
+  int low = INTVAL (operands[2]) & 0xffff;
+  int high = (unsigned) INTVAL (operands[2]) >> 16;
 
-      if (low & 0x8000)
-	high++, low |= 0xffff0000;
+  if (low & 0x8000)
+    high++, low |= 0xffff0000;
 
-      emit_insn (gen_addsi3 (operands[0], operands[1],
-			     gen_rtx (CONST_INT, VOIDmode, high << 16)));
-      operands[1] = operands[0];
-      operands[2] = gen_rtx (CONST_INT, VOIDmode, low);
-    }
+  operands[3] = gen_rtx (CONST_INT, VOIDmode, high << 16);
+  operands[4] = gen_rtx (CONST_INT, VOIDmode, low);
 }")
 
 (define_insn "one_cmplsi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(not:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
   ""
   "sfi %0,%1,-1")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
-		  (match_operand:SI 2 "gen_reg_operand" "r,r")))]
+		  (match_operand:SI 2 "gpc_reg_operand" "r,r")))]
   ""
   "@
    sf %0,%2,%1
@@ -236,8 +235,8 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r")
-			      (match_operand:SI 2 "gen_reg_operand" "r"))
+	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			      (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
   ""
@@ -246,17 +245,17 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r")
-			      (match_operand:SI 2 "gen_reg_operand" "r"))
+	(compare:CC (minus:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			      (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(minus:SI (match_dup 1) (match_dup 2)))]
   ""
   "sf. %0,%2,%1"
   [(set_attr "type" "compare")])
 
 (define_expand "subsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
 		  (match_operand:SI 2 "reg_or_cint_operand" "")))]
   ""
@@ -276,11 +275,11 @@
 
 (define_expand "sminsi3"
   [(set (match_dup 3)
-	(if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "")
+	(if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
 				(match_operand:SI 2 "reg_or_short_operand" ""))
 			 (const_int 0)
 			 (minus:SI (match_dup 2) (match_dup 1))))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(minus:SI (match_dup 2) (match_dup 3)))]
   ""
   "
@@ -288,47 +287,47 @@
 
 (define_expand "smaxsi3"
   [(set (match_dup 3)
-	(if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "")
+	(if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
 				(match_operand:SI 2 "reg_or_short_operand" ""))
 			 (const_int 0)
 			 (minus:SI (match_dup 2) (match_dup 1))))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(plus:SI (match_dup 3) (match_dup 1)))]
   ""
   "
 { operands[3] = gen_reg_rtx (SImode); }")
 
 (define_expand "uminsi3"
-  [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
+  [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			      (const_int -2147483648)))
-   (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "")
+   (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
 			      (const_int -2147483648)))
    (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
 				       (const_int 0)
 				       (minus:SI (match_dup 4) (match_dup 3))))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(minus:SI (match_dup 2) (match_dup 3)))]
   ""
   "
 { operands[3] = gen_reg_rtx (SImode);  operands[4] = gen_reg_rtx (SImode); }")
 
 (define_expand "umaxsi3"
-  [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
+  [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			      (const_int -2147483648)))
-   (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "")
+   (set (match_dup 4) (xor:SI (match_operand:SI 2 "gpc_reg_operand" "")
 			      (const_int -2147483648)))
    (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
 				       (const_int 0)
 				       (minus:SI (match_dup 4) (match_dup 3))))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(plus:SI (match_dup 3) (match_dup 1)))]
   ""
   "
 { operands[3] = gen_reg_rtx (SImode);  operands[4] = gen_reg_rtx (SImode); }")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
 			     (match_operand:SI 2 "reg_or_short_operand" "rI"))
 			 (const_int 0)
 			 (minus:SI (match_dup 2) (match_dup 1))))]
@@ -338,7 +337,7 @@
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC
-	 (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
+	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
 			      (match_operand:SI 2 "reg_or_short_operand" "rI"))
 			  (const_int 0)
 			  (minus:SI (match_dup 2) (match_dup 1)))
@@ -351,12 +350,12 @@
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
 	(compare:CC
-	 (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
+	 (if_then_else:SI (gt (match_operand:SI 1 "gpc_reg_operand" "r")
 			      (match_operand:SI 2 "reg_or_short_operand" "rI"))
 			  (const_int 0)
 			  (minus:SI (match_dup 2) (match_dup 1)))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(if_then_else:SI (gt (match_dup 1) (match_dup 2))
 			 (const_int 0)
 			 (minus:SI (match_dup 2) (match_dup 1))))]
@@ -367,26 +366,26 @@
 ;; We don't need abs with condition code because such comparisons should
 ;; never be done.
 (define_insn "abssi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
   ""
   "abs %0,%1")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r"))))]
   ""
   "nabs %0,%1")
 
 (define_insn "negsi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(neg:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(neg:SI (match_operand:SI 1 "gpc_reg_operand" "r")))]
   ""
   "neg %0,%1")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r"))
+	(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 2 "=r"))]
   ""
@@ -395,9 +394,9 @@
 
 (define_insn ""
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
-	(compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r"))
+	(compare:CC (neg:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(neg:SI (match_dup 1)))]
   ""
   "neg. %0,%1"
@@ -424,8 +423,8 @@
   [(set_attr "type" "compare")])
 
 (define_insn "mulsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(mult:SI (match_operand:SI 1 "gen_reg_operand" "%r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")
 		 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
    (clobber (match_scratch:SI 3 "=q,q"))]
   ""
@@ -435,8 +434,8 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r")
-			     (match_operand:SI 2 "gen_reg_operand" "r"))
+	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			     (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))
    (clobber (match_scratch:SI 4 "=q"))]
@@ -446,10 +445,10 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r")
-			     (match_operand:SI 2 "gen_reg_operand" "r"))
+	(compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			     (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(mult:SI (match_dup 1) (match_dup 2)))
    (clobber (match_scratch:SI 4 "=q"))]
   ""
@@ -461,10 +460,10 @@
 ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
 
 (define_insn "divmodsi4"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(div:SI (match_operand:SI 1 "gen_reg_operand" "r")
-		(match_operand:SI 2 "gen_reg_operand" "r")))
-   (set (match_operand:SI 3 "gen_reg_operand" "=q")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+		(match_operand:SI 2 "gpc_reg_operand" "r")))
+   (set (match_operand:SI 3 "gpc_reg_operand" "=q")
 	(mod:SI (match_dup 1) (match_dup 2)))]
   ""
   "divs %0,%1,%2")
@@ -472,8 +471,8 @@
 ;; For powers of two we can do srai/aze for divide and then adjust for
 ;; modulus.  If it isn't a power of two, FAIL so divmodsi4 will be used.
 (define_expand "divsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
-	(div:SI (match_operand:SI 1 "gen_reg_operand" "")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(div:SI (match_operand:SI 1 "gpc_reg_operand" "")
 		(match_operand:SI 2 "reg_or_cint_operand" "")))]
   ""
   "
@@ -485,11 +484,11 @@
 
 (define_expand "modsi3"
   [(set (match_dup 3)
-	(div:SI (match_operand:SI 1 "gen_reg_operand" "")
+	(div:SI (match_operand:SI 1 "gpc_reg_operand" "")
 		(match_operand:SI 2 "reg_or_cint_operand" "")))
    (parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5)))
 	      (clobber (scratch:SI))])
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(minus:SI (match_dup 1) (match_dup 4)))]
   ""
   "
@@ -505,15 +504,15 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(div:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "const_int_operand" "N")))]
   "exact_log2 (INTVAL (operands[2])) >= 0"
   "srai %0,%1,%p2\;aze %0,%0")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(div:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "const_int_operand" "N")))
    (clobber (match_scratch:SI 3 "=r"))]
   "exact_log2 (INTVAL (operands[2])) >= 0"
@@ -522,22 +521,22 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(div:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	(div:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "const_int_operand" "N")))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(div:SI (match_dup 1) (match_dup 2)))]
   "exact_log2 (INTVAL (operands[2])) >= 0"
   "srai %0,%1,%p2\;aze. %0,%0"
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(udiv:SI
 	 (plus:DI (lshift:DI
-		   (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
+		   (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		   (const_int 32))
 		  (zero_extend:DI (match_operand:SI 2 "register_operand" "*q")))
-	 (match_operand:SI 3 "gen_reg_operand" "r")))
+	 (match_operand:SI 3 "gpc_reg_operand" "r")))
    (set (match_operand:SI 4 "register_operand" "=*q")
 	(umod:SI
 	 (plus:DI (lshift:DI
@@ -588,10 +587,10 @@
 }")
 
 (define_expand "udivmodsi4"
-  [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
-		   (udiv:SI (match_operand:SI 1 "gen_reg_operand" "")
+  [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
+		   (udiv:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			    (match_operand:SI 2 "reg_or_cint_operand" "")))
-	      (set (match_operand:SI 3 "gen_reg_operand" "")
+	      (set (match_operand:SI 3 "gpc_reg_operand" "")
 		   (umod:SI (match_dup 1) (match_dup 2)))])]
   ""
   "
@@ -617,8 +616,8 @@
 }")
     
 (define_insn "andsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
-	(and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
+	(and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
 		(match_operand:SI 2 "and_operand" "?r,L,K,J")))
    (clobber (match_scratch:CC 3 "=X,X,x,x"))]
   ""
@@ -630,7 +629,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
-	(compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
+	(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
 			    (match_operand:SI 2 "and_operand" "r,K,J,L"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r,r,r"))]
@@ -644,10 +643,10 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
-	(compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
+	(compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r")
 			    (match_operand:SI 2 "and_operand" "r,K,J,L"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
 	(and:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -657,9 +656,49 @@
    rlinm. %0,%1,0,%m2,%M2"
   [(set_attr "type" "compare,compare,compare,delayed_compare")]) 
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r")
-	(ior:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r")
+;; Take a AND with a constant that cannot be done in a single insn and try to
+;; split it into two insns.  This does not verify that the insns are valid
+;; since this need not be done as combine will do it.
+
+(define_split
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(and:SI (match_operand:SI 1 "gpc_reg_operand" "")
+		(match_operand:SI 2 "non_and_cint_operand" "")))]
+  ""
+  [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 3)))
+   (set (match_dup 0) (and:SI (match_dup 0) (match_dup 4)))]
+  "
+{
+  int maskval = INTVAL (operands[2]);
+  int i, transitions, last_bit_value;
+  int orig = maskval, first_c = maskval, second_c;
+
+  /* We know that MASKVAL must have more than 2 bit-transitions.  Start at
+     the low-order bit and count for the third transition.  When we get there,
+     make a first mask that has everything to the left of that position
+     a one.  Then make the second mask to turn off whatever else is needed.  */
+
+  for (i = 1, transitions = 0, last_bit_value = maskval & 1; i < 32; i++)
+    {
+      if (((maskval >>= 1) & 1) != last_bit_value)
+	last_bit_value ^= 1, transitions++;
+
+      if (transitions > 2)
+	{
+	  first_c |= (~0) << i;
+	  break;
+	}
+    }
+
+  second_c = orig | ~ first_c;
+
+  operands[3] = gen_rtx (CONST_INT, VOIDmode, first_c);
+  operands[4] = gen_rtx (CONST_INT, VOIDmode, second_c);
+}")
+
+(define_insn "iorsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
+	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
 		(match_operand:SI 2 "logical_operand" "r,K,J")))]
   ""
   "@
@@ -669,8 +708,8 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r")
-			    (match_operand:SI 2 "gen_reg_operand" "r"))
+	(compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			    (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
   ""
@@ -679,37 +718,35 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r")
-			    (match_operand:SI 2 "gen_reg_operand" "r"))
+	(compare:CC (ior:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			    (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (match_dup 1) (match_dup 2)))]
   ""
   "or. %0,%1,%2"
   [(set_attr "type" "compare")])
 
-(define_expand "iorsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
-	(ior:SI (match_operand:SI 1 "gen_reg_operand" "")
-		(match_operand:SI 2 "reg_or_cint_operand" "")))]
-  ""
-  "
+;; Split an IOR that we can't do in one insn into two insns, each of which
+;; does one 16-bit part.  This is used by combine.
+
+(define_split
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(ior:SI (match_operand:SI 1 "gpc_reg_operand" "")
+		(match_operand:SI 2 "non_logical_cint_operand" "")))]
+  ""
+  [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 3)))
+   (set (match_dup 0) (ior:SI (match_dup 0) (match_dup 4)))]
+"
 {
-  if (GET_CODE (operands[2]) == CONST_INT
-      && ! logical_operand (operands[2], SImode))
-    {
-      emit_insn (gen_iorsi3 (operands[0], operands[1],
-			     gen_rtx (CONST_INT, VOIDmode,
-				      INTVAL (operands[2]) & 0xffff0000)));
-      operands[1] = operands[0];
-      operands[2] = gen_rtx (CONST_INT, VOIDmode,
-			     INTVAL (operands[2]) & 0xffff);
-    }
+  operands[3] = gen_rtx (CONST_INT, VOIDmode,
+			 INTVAL (operands[2]) & 0xffff0000);
+  operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
 }")
 
-(define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r")
-	(xor:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r")
+(define_insn "xorsi3"
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
+	(xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r")
 		(match_operand:SI 2 "logical_operand" "r,K,J")))]
   ""
   "@
@@ -719,8 +756,8 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r")
-			    (match_operand:SI 2 "gen_reg_operand" "r"))
+	(compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			    (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
   ""
@@ -729,45 +766,43 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r")
-			    (match_operand:SI 2 "gen_reg_operand" "r"))
+	(compare:CC (xor:SI (match_operand:SI 1 "gpc_reg_operand" "r")
+			    (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(xor:SI (match_dup 1) (match_dup 2)))]
   ""
   "xor. %0,%1,%2"
   [(set_attr "type" "compare")])
 
-(define_expand "xorsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
-	(xor:SI (match_operand:SI 1 "gen_reg_operand" "")
-		(match_operand:SI 2 "reg_or_cint_operand" "")))]
-  ""
-  "
+;; Split an XOR that we can't do in one insn into two insns, each of which
+;; does one 16-bit part.  This is used by combine.
+
+(define_split
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
+		(match_operand:SI 2 "non_logical_cint_operand" "")))]
+  ""
+  [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 3)))
+   (set (match_dup 0) (xor:SI (match_dup 0) (match_dup 4)))]
+"
 {
-  if (GET_CODE (operands[2]) == CONST_INT
-      && ! logical_operand (operands[2], SImode))
-    {
-      emit_insn (gen_xorsi3 (operands[0], operands[1],
-			     gen_rtx (CONST_INT, VOIDmode,
-				      INTVAL (operands[2]) & 0xffff0000)));
-      operands[1] = operands[0];
-      operands[2] = gen_rtx (CONST_INT, VOIDmode,
-			     INTVAL (operands[2]) & 0xffff);
-    }
+  operands[3] = gen_rtx (CONST_INT, VOIDmode,
+			 INTVAL (operands[2]) & 0xffff0000);
+  operands[4] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[2]) & 0xffff);
 }")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
-			(match_operand:SI 2 "gen_reg_operand" "r"))))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
+			(match_operand:SI 2 "gpc_reg_operand" "r"))))]
    ""
    "eqv %0,%1,%2")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
-				    (match_operand:SI 2 "gen_reg_operand" "r")))
+	(compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
+				    (match_operand:SI 2 "gpc_reg_operand" "r")))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
    ""
@@ -776,26 +811,26 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
-				    (match_operand:SI 2 "gen_reg_operand" "r")))
+	(compare:CC (not:SI (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
+				    (match_operand:SI 2 "gpc_reg_operand" "r")))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(not:SI (xor:SI (match_dup 1) (match_dup 2))))]
    ""
    "eqv. %0,%1,%2"
    [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-		(match_operand:SI 2 "gen_reg_operand" "r")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		(match_operand:SI 2 "gpc_reg_operand" "r")))]
   ""
   "andc %0,%2,%1")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			    (match_operand:SI 2 "gen_reg_operand" "r"))
+	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			    (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
   ""
@@ -804,26 +839,26 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			    (match_operand:SI 2 "gen_reg_operand" "r"))
+	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			    (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (not:SI (match_dup 1)) (match_dup 2)))]
   ""
   "andc. %0,%2,%1"
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-		(match_operand:SI 2 "gen_reg_operand" "r")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		(match_operand:SI 2 "gpc_reg_operand" "r")))]
   ""
   "orc %0,%2,%1")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			    (match_operand:SI 2 "gen_reg_operand" "r"))
+	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			    (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
   ""
@@ -832,26 +867,26 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			    (match_operand:SI 2 "gen_reg_operand" "r"))
+	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			    (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
   ""
   "orc. %0,%2,%1"
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-		(not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
   ""
   "nand %0,%1,%2")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			    (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
+	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
   ""
@@ -860,26 +895,26 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			    (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
+	(compare:CC (ior:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
   ""
   "nand. %0,%1,%2"
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-		(not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		(not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))))]
   ""
   "nor %0,%1,%2")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			    (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
+	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
   ""
@@ -888,10 +923,10 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			    (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
+	(compare:CC (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			    (not:SI (match_operand:SI 2 "gpc_reg_operand" "r")))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
   ""
   "nor. %0,%1,%2"
@@ -902,50 +937,50 @@
 ;; would modify an input register.
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			(match_operand:SI 2 "gen_reg_operand" "0"))
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			(match_operand:SI 2 "gpc_reg_operand" "0"))
 		(and:SI (match_dup 1)
-			(match_operand:SI 3 "gen_reg_operand" "r"))))]
+			(match_operand:SI 3 "gpc_reg_operand" "r"))))]
   ""
   "maskir %0,%3,%1")
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			(match_operand:SI 2 "gen_reg_operand" "0"))
-		(and:SI (match_operand:SI 3 "gen_reg_operand" "r")
+	(ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			(match_operand:SI 2 "gpc_reg_operand" "0"))
+		(and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
 			(match_dup 1))))]
   ""
   "maskir %0,%3,%1")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (and:SI (match_dup 1)
-			(match_operand:SI 3 "gen_reg_operand" "r"))
-		(and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			(match_operand:SI 2 "gen_reg_operand" "0"))))]
+			(match_operand:SI 3 "gpc_reg_operand" "r"))
+		(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			(match_operand:SI 2 "gpc_reg_operand" "0"))))]
   ""
   "maskir %0,%3,%1")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
 			(match_dup 1))
-		(and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			(match_operand:SI 2 "gen_reg_operand" "0"))))]
+		(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			(match_operand:SI 2 "gpc_reg_operand" "0"))))]
   ""
   "maskir %0,%3,%1")
 
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
-	 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			 (match_operand:SI 2 "gen_reg_operand" "0"))
+	 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			 (match_operand:SI 2 "gpc_reg_operand" "0"))
 		 (and:SI (match_dup 1)
-			 (match_operand:SI 3 "gen_reg_operand" "r")))
+			 (match_operand:SI 3 "gpc_reg_operand" "r")))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
 		(and:SI (match_dup 1) (match_dup 3))))]
   ""
@@ -955,9 +990,9 @@
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
-	 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			 (match_operand:SI 2 "gen_reg_operand" "0"))
-		 (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
+	 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			 (match_operand:SI 2 "gpc_reg_operand" "0"))
+		 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
 			 (match_dup 1)))
 	 (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "=r")
@@ -971,11 +1006,11 @@
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
 	 (ior:SI (and:SI (match_dup 1)
-			 (match_operand:SI 3 "gen_reg_operand" "r"))
-		 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			 (match_operand:SI 2 "gen_reg_operand" "0")))
+			 (match_operand:SI 3 "gpc_reg_operand" "r"))
+		 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			 (match_operand:SI 2 "gpc_reg_operand" "0")))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (and:SI (match_dup 1) (match_dup 3))
 		(and:SI (not:SI (match_dup 1)) (match_dup 2))))]
   ""
@@ -985,12 +1020,12 @@
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
-	 (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
+	 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
 			 (match_dup 1))
-		 (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
-			 (match_operand:SI 2 "gen_reg_operand" "0")))
+		 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
+			 (match_operand:SI 2 "gpc_reg_operand" "0")))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (and:SI (match_dup 3) (match_dup 1))
 		(and:SI (not:SI (match_dup 1)) (match_dup 2))))]
   ""
@@ -1000,10 +1035,10 @@
 ;; Rotate and shift insns, in all their variants.  These support shifts,
 ;; field inserts and extracts, and various combinations thereof.
 (define_insn "insv"
-  [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
 			 (match_operand:SI 1 "const_int_operand" "i")
 			 (match_operand:SI 2 "const_int_operand" "i"))
-	(match_operand:SI 3 "gen_reg_operand" "r"))]
+	(match_operand:SI 3 "gpc_reg_operand" "r"))]
   ""
   "*
 {
@@ -1016,8 +1051,8 @@
 }")
 
 (define_insn "extzv"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "const_int_operand" "i")
 			 (match_operand:SI 3 "const_int_operand" "i")))]
   ""
@@ -1035,7 +1070,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	(compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "const_int_operand" "i")
 			 (match_operand:SI 3 "const_int_operand" "i"))
 		    (const_int 0)))
@@ -1046,6 +1081,23 @@
   int start = INTVAL (operands[3]) & 31;
   int size = INTVAL (operands[2]) & 31;
 
+  /* If the bitfield being tested fits in the upper or lower half of a
+     word, it is possible to use andiu. or andil. to test it.  This is
+     useful because the condition register set-use delay is smaller for
+     andi[ul]. than for rlinm.  This doesn't work when the starting bit
+     position is 0 because the LT and GT bits may be set wrong.  */
+
+  if ((start > 0 && start + size <= 16) || start >= 16)
+    {
+      operands[3] = gen_rtx (CONST_INT, VOIDmode,
+			     ((1 << (16 - (start & 15)))
+			      - (1 << (16 - (start & 15) - size))));
+      if (start < 16)
+	return \"andiu. %4,%1,%3\";
+      else
+	return \"andil. %4,%1,%3\";
+    }
+  
   if (start + size >= 32)
     operands[3] = const0_rtx;
   else
@@ -1056,11 +1108,11 @@
 
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
-	(compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	(compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "const_int_operand" "i")
 			 (match_operand:SI 3 "const_int_operand" "i"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
   ""
   "*
@@ -1068,6 +1120,12 @@
   int start = INTVAL (operands[3]) & 31;
   int size = INTVAL (operands[2]) & 31;
 
+  if (start >= 16 && start + size == 32)
+    {
+      operands[3] = gen_rtx (CONST_INT, VOIDmode, (1 << (32 - start)) - 1);
+      return \"andil. %0,%1,%3\";
+    }
+  
   if (start + size >= 32)
     operands[3] = const0_rtx;
   else
@@ -1077,15 +1135,15 @@
   [(set_attr "type" "delayed_compare")])
 
 (define_insn "rotlsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		   (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
   ""
   "rl%I2nm %0,%1,%h2,0,31")
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
-	(compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			       (match_operand:SI 2 "reg_or_cint_operand" "ri"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
@@ -1095,18 +1153,18 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
-	(compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	(compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			       (match_operand:SI 2 "reg_or_cint_operand" "ri"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(rotate:SI (match_dup 1) (match_dup 2)))]
   ""
   "rl%I2nm. %0,%1,%h2,0,31"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(and:SI (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			   (match_operand:SI 2 "reg_or_cint_operand" "ri"))
 		(match_operand:SI 3 "mask_operand" "L")))]
   ""
@@ -1115,7 +1173,7 @@
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC (and:SI
-		     (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+		     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 				(match_operand:SI 2 "reg_or_cint_operand" "ri"))
 		     (match_operand:SI 3 "mask_operand" "L"))
 		    (const_int 0)))
@@ -1127,21 +1185,21 @@
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC (and:SI
-		     (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+		     (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 				(match_operand:SI 2 "reg_or_cint_operand" "ri"))
 		     (match_operand:SI 3 "mask_operand" "L"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   ""
   "rl%I2nm. %0,%1,%h2,%m3,%M3"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(zero_extend:SI
 	 (subreg:QI
-	  (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	  (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		     (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
   ""
   "rl%I2nm %0,%1,%h2,24,31")
@@ -1150,7 +1208,7 @@
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC (zero_extend:SI
 		     (subreg:QI
-		      (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+		      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
@@ -1162,20 +1220,20 @@
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
 	(compare:CC (zero_extend:SI
 		     (subreg:QI
-		      (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+		      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
   ""
   "rl%I2nm. %0,%1,%h2,24,31"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(zero_extend:SI
 	 (subreg:HI
-	  (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	  (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		     (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
   ""
   "rl%I2nm %0,%1,%h2,16,31")
@@ -1184,7 +1242,7 @@
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC (zero_extend:SI
 		     (subreg:HI
-		      (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+		      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
@@ -1196,10 +1254,10 @@
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
 	(compare:CC (zero_extend:SI
 		     (subreg:HI
-		      (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
+		      (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
   ""
   "rl%I2nm. %0,%1,%h2,16,31"
@@ -1209,8 +1267,8 @@
 ;; SHIFT_COUNT_TRUNCATED.
 
 (define_insn "ashlsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 		   (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
    (clobber (match_scratch:SI 3 "=q,X"))]
   ""
@@ -1220,7 +1278,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			       (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r"))
@@ -1233,10 +1291,10 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
-	(compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	(compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			       (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(ashift:SI (match_dup 1) (match_dup 2)))
    (clobber (match_scratch:SI 4 "=q,X"))]
   ""
@@ -1246,8 +1304,8 @@
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			   (match_operand:SI 2 "const_int_operand" "i"))
 		(match_operand:SI 3 "mask_operand" "L")))]
   "includes_lshift_p (operands[2], operands[3])"
@@ -1256,7 +1314,7 @@
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC
-	 (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			    (match_operand:SI 2 "const_int_operand" "i"))
 		 (match_operand:SI 3 "mask_operand" "L"))
 	 (const_int 0)))
@@ -1268,11 +1326,11 @@
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
-	 (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			    (match_operand:SI 2 "const_int_operand" "i"))
 		 (match_operand:SI 3 "mask_operand" "L"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "includes_lshift_p (operands[2], operands[3])"
   "rlinm. %0,%h1,%h2,%m3,%M3"
@@ -1281,8 +1339,8 @@
 ;; The RS/6000 assembler mis-handles "sri x,x,0", so write that case as
 ;; "sli x,x,0".
 (define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 		     (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
    (clobber (match_scratch:SI 3 "=q,X"))]
   ""
@@ -1292,7 +1350,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r"))
@@ -1305,10 +1363,10 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(lshiftrt:SI (match_dup 1) (match_dup 2)))
    (clobber (match_scratch:SI 4 "=q,X"))]
   ""
@@ -1318,8 +1376,8 @@
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			     (match_operand:SI 2 "const_int_operand" "i"))
 		(match_operand:SI 3 "mask_operand" "L")))]
   "includes_rshift_p (operands[2], operands[3])"
@@ -1328,7 +1386,7 @@
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC
-	 (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			      (match_operand:SI 2 "const_int_operand" "i"))
 		 (match_operand:SI 3 "mask_operand" "L"))
 	 (const_int 0)))
@@ -1340,21 +1398,21 @@
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
-	 (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			      (match_operand:SI 2 "const_int_operand" "i"))
 		 (match_operand:SI 3 "mask_operand" "L"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
   "includes_rshift_p (operands[2], operands[3])"
   "rlinm. %0,%1,%s2,%m3,%M3"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(zero_extend:SI
 	 (subreg:QI
-	  (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	  (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "const_int_operand" "i")) 0)))]
   "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
   "rlinm %0,%1,%s2,24,31")
@@ -1364,7 +1422,7 @@
 	(compare:CC
 	 (zero_extend:SI
 	  (subreg:QI
-	   (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	   (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "const_int_operand" "i")) 0))
 	 (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
@@ -1377,20 +1435,20 @@
 	(compare:CC
 	 (zero_extend:SI
 	  (subreg:QI
-	   (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	   (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "const_int_operand" "i")) 0))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
   "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
   "rlinm. %0,%1,%s2,24,31"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(zero_extend:SI
 	 (subreg:HI
-	  (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	  (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "const_int_operand" "i")) 0)))]
   "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
   "rlinm %0,%1,%s2,16,31")
@@ -1400,7 +1458,7 @@
 	(compare:CC
 	 (zero_extend:SI
 	  (subreg:HI
-	   (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	   (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "const_int_operand" "i")) 0))
 	 (const_int 0)))
    (clobber (match_scratch:SI 3 "=r"))]
@@ -1413,46 +1471,46 @@
 	(compare:CC
 	 (zero_extend:SI
 	  (subreg:HI
-	   (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	   (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "const_int_operand" "i")) 0))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
   "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
   "rlinm. %0,%1,%s2,16,31"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
 			 (const_int 1)
-			 (match_operand:SI 1 "gen_reg_operand" "r"))
-	(ashiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r")
+			 (match_operand:SI 1 "gpc_reg_operand" "r"))
+	(ashiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
 		     (const_int 31)))]
   ""
   "rrib %0,%1,%2")
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
 			 (const_int 1)
-			 (match_operand:SI 1 "gen_reg_operand" "r"))
-	(lshiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r")
+			 (match_operand:SI 1 "gpc_reg_operand" "r"))
+	(lshiftrt:SI (match_operand:SI 2 "gpc_reg_operand" "r")
 		     (const_int 31)))]
   ""
   "rrib %0,%1,%2")
 
 (define_insn ""
-  [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
+  [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r")
 			 (const_int 1)
-			 (match_operand:SI 1 "gen_reg_operand" "r"))
-	(zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r")
+			 (match_operand:SI 1 "gpc_reg_operand" "r"))
+	(zero_extract:SI (match_operand:SI 2 "gpc_reg_operand" "r")
 			 (const_int 1)
 			 (const_int 0)))]
   ""
   "rrib %0,%1,%2")
 
 (define_insn "ashrsi3"
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 		     (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
    (clobber (match_scratch:SI 3 "=q,X"))]
   ""
@@ -1462,7 +1520,7 @@
 
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
 		    (const_int 0)))
    (clobber (match_scratch:SI 3 "=r,r"))
@@ -1475,10 +1533,10 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
-	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	(compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 				 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(ashiftrt:SI (match_dup 1) (match_dup 2)))
    (clobber (match_scratch:SI 4 "=q,X"))]
   ""
@@ -1489,10 +1547,10 @@
 
 (define_expand "extendqisi2"
   [(parallel [(set (match_dup 2)
-		   (ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
+		   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
 			      (const_int 24)))
 	      (clobber (scratch:SI))])
-   (parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
+   (parallel [(set (match_operand:SI 0 "gpc_reg_operand" "")
 		   (ashiftrt:SI (match_dup 2)
 				(const_int 24)))
 	      (clobber (scratch:SI))])]
@@ -1503,10 +1561,10 @@
 
 (define_expand "extendqihi2"
   [(parallel [(set (match_dup 2)
-		   (ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
+		   (ashift:SI (match_operand:QI 1 "gpc_reg_operand" "")
 			      (const_int 24)))
 	      (clobber (scratch:SI))])
-   (parallel [(set (match_operand:HI 0 "gen_reg_operand" "")
+   (parallel [(set (match_operand:HI 0 "gpc_reg_operand" "")
 		   (ashiftrt:SI (match_dup 2)
 				(const_int 24)))
 	      (clobber (scratch:SI))])]
@@ -1531,8 +1589,8 @@
 ;; is not guaranteed.  Perhaps this should be tightened up at some point.
 
 (define_insn "extendsfdf2"
-  [(set (match_operand:DF 0 "gen_reg_operand" "=f")
-	(float_extend:DF (match_operand:SF 1 "gen_reg_operand" "f")))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "f")))]
   ""
   "*
 {
@@ -1544,8 +1602,8 @@
   [(set_attr "type" "fp")])
 
 (define_insn "truncdfsf2"
-  [(set (match_operand:SF 0 "gen_reg_operand" "=f")
-	(float_truncate:SF (match_operand:DF 1 "gen_reg_operand" "f")))]
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "f")))]
   ""
   "*
 {
@@ -1557,179 +1615,179 @@
   [(set_attr "type" "fp")])
 
 (define_insn "negsf2"
-  [(set (match_operand:SF 0 "gen_reg_operand" "=f")
-	(neg:SF (match_operand:SF 1 "gen_reg_operand" "f")))]
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(neg:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
   ""
   "fneg %0,%1"
   [(set_attr "type" "fp")])
 
 (define_insn "abssf2"
-  [(set (match_operand:SF 0 "gen_reg_operand" "=f")
-	(abs:SF (match_operand:SF 1 "gen_reg_operand" "f")))]
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(abs:SF (match_operand:SF 1 "gpc_reg_operand" "f")))]
   ""
   "fabs %0,%1"
   [(set_attr "type" "fp")])
 
 (define_insn ""
-  [(set (match_operand:SF 0 "gen_reg_operand" "=f")
-	(neg:SF (abs:SF (match_operand:SF 1 "gen_reg_operand" "f"))))]
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(neg:SF (abs:SF (match_operand:SF 1 "gpc_reg_operand" "f"))))]
   ""
   "fnabs %0,%1"
   [(set_attr "type" "fp")])
 
 (define_insn "addsf3"
-  [(set (match_operand:SF 0 "gen_reg_operand" "=f")
-	(plus:SF (match_operand:SF 1 "gen_reg_operand" "%f")
-		 (match_operand:SF 2 "gen_reg_operand" "f")))]
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(plus:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+		 (match_operand:SF 2 "gpc_reg_operand" "f")))]
   ""
   "fa %0,%1,%2"
   [(set_attr "type" "fp")])
 
 (define_insn "subsf3"
-  [(set (match_operand:SF 0 "gen_reg_operand" "=f")
-	(minus:SF (match_operand:SF 1 "gen_reg_operand" "f")
-		  (match_operand:SF 2 "gen_reg_operand" "f")))]
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(minus:SF (match_operand:SF 1 "gpc_reg_operand" "f")
+		  (match_operand:SF 2 "gpc_reg_operand" "f")))]
   ""
   "fs %0,%1,%2"
   [(set_attr "type" "fp")])
 
 (define_insn "mulsf3"
-  [(set (match_operand:SF 0 "gen_reg_operand" "=f")
-	(mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
-		 (match_operand:SF 2 "gen_reg_operand" "f")))]
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+		 (match_operand:SF 2 "gpc_reg_operand" "f")))]
   ""
   "fm %0,%1,%2"
   [(set_attr "type" "fp")])
 
 (define_insn "divsf3"
-  [(set (match_operand:SF 0 "gen_reg_operand" "=f")
-	(div:SF (match_operand:SF 1 "gen_reg_operand" "f")
-		(match_operand:SF 2 "gen_reg_operand" "f")))]
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(div:SF (match_operand:SF 1 "gpc_reg_operand" "f")
+		(match_operand:SF 2 "gpc_reg_operand" "f")))]
   ""
   "fd %0,%1,%2"
   [(set_attr "type" "fp")])
 
 (define_insn ""
-  [(set (match_operand:SF 0 "gen_reg_operand" "=f")
-	(plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
-			  (match_operand:SF 2 "gen_reg_operand" "f"))
-		 (match_operand:SF 3 "gen_reg_operand" "f")))]
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+			  (match_operand:SF 2 "gpc_reg_operand" "f"))
+		 (match_operand:SF 3 "gpc_reg_operand" "f")))]
   ""
   "fma %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
 (define_insn ""
-  [(set (match_operand:SF 0 "gen_reg_operand" "=f")
-	(minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
-			   (match_operand:SF 2 "gen_reg_operand" "f"))
-		  (match_operand:SF 3 "gen_reg_operand" "f")))]
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+			   (match_operand:SF 2 "gpc_reg_operand" "f"))
+		  (match_operand:SF 3 "gpc_reg_operand" "f")))]
   ""
   "fms %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
 (define_insn ""
-  [(set (match_operand:SF 0 "gen_reg_operand" "=f")
-	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
-				  (match_operand:SF 2 "gen_reg_operand" "f"))
-			 (match_operand:SF 3 "gen_reg_operand" "f"))))]
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+				  (match_operand:SF 2 "gpc_reg_operand" "f"))
+			 (match_operand:SF 3 "gpc_reg_operand" "f"))))]
   ""
   "fnma %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
 (define_insn ""
-  [(set (match_operand:SF 0 "gen_reg_operand" "=f")
-	(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
-				   (match_operand:SF 2 "gen_reg_operand" "f"))
-			  (match_operand:SF 3 "gen_reg_operand" "f"))))]
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gpc_reg_operand" "%f")
+				   (match_operand:SF 2 "gpc_reg_operand" "f"))
+			  (match_operand:SF 3 "gpc_reg_operand" "f"))))]
   ""
   "fnms %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
 (define_insn "negdf2"
-  [(set (match_operand:DF 0 "gen_reg_operand" "=f")
-	(neg:DF (match_operand:DF 1 "gen_reg_operand" "f")))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(neg:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
   ""
   "fneg %0,%1"
   [(set_attr "type" "fp")])
 
 (define_insn "absdf2"
-  [(set (match_operand:DF 0 "gen_reg_operand" "=f")
-	(abs:DF (match_operand:DF 1 "gen_reg_operand" "f")))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(abs:DF (match_operand:DF 1 "gpc_reg_operand" "f")))]
   ""
   "fabs %0,%1"
   [(set_attr "type" "fp")])
 
 (define_insn ""
-  [(set (match_operand:DF 0 "gen_reg_operand" "=f")
-	(neg:DF (abs:DF (match_operand:DF 1 "gen_reg_operand" "f"))))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(neg:DF (abs:DF (match_operand:DF 1 "gpc_reg_operand" "f"))))]
   ""
   "fnabs %0,%1"
   [(set_attr "type" "fp")])
 
 (define_insn "adddf3"
-  [(set (match_operand:DF 0 "gen_reg_operand" "=f")
-	(plus:DF (match_operand:DF 1 "gen_reg_operand" "%f")
-		 (match_operand:DF 2 "gen_reg_operand" "f")))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(plus:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+		 (match_operand:DF 2 "gpc_reg_operand" "f")))]
   ""
   "fa %0,%1,%2"
   [(set_attr "type" "fp")])
 
 (define_insn "subdf3"
-  [(set (match_operand:DF 0 "gen_reg_operand" "=f")
-	(minus:DF (match_operand:DF 1 "gen_reg_operand" "f")
-		  (match_operand:DF 2 "gen_reg_operand" "f")))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(minus:DF (match_operand:DF 1 "gpc_reg_operand" "f")
+		  (match_operand:DF 2 "gpc_reg_operand" "f")))]
   ""
   "fs %0,%1,%2"
   [(set_attr "type" "fp")])
 
 (define_insn "muldf3"
-  [(set (match_operand:DF 0 "gen_reg_operand" "=f")
-	(mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
-		 (match_operand:DF 2 "gen_reg_operand" "f")))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+		 (match_operand:DF 2 "gpc_reg_operand" "f")))]
   ""
   "fm %0,%1,%2"
   [(set_attr "type" "fp")])
 
 (define_insn "divdf3"
-  [(set (match_operand:DF 0 "gen_reg_operand" "=f")
-	(div:DF (match_operand:DF 1 "gen_reg_operand" "f")
-		(match_operand:DF 2 "gen_reg_operand" "f")))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(div:DF (match_operand:DF 1 "gpc_reg_operand" "f")
+		(match_operand:DF 2 "gpc_reg_operand" "f")))]
   ""
   "fd %0,%1,%2"
   [(set_attr "type" "fp")])
 
 (define_insn ""
-  [(set (match_operand:DF 0 "gen_reg_operand" "=f")
-	(plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
-			  (match_operand:DF 2 "gen_reg_operand" "f"))
-		 (match_operand:DF 3 "gen_reg_operand" "f")))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+			  (match_operand:DF 2 "gpc_reg_operand" "f"))
+		 (match_operand:DF 3 "gpc_reg_operand" "f")))]
   ""
   "fma %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
 (define_insn ""
-  [(set (match_operand:DF 0 "gen_reg_operand" "=f")
-	(minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
-			   (match_operand:DF 2 "gen_reg_operand" "f"))
-		  (match_operand:DF 3 "gen_reg_operand" "f")))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+			   (match_operand:DF 2 "gpc_reg_operand" "f"))
+		  (match_operand:DF 3 "gpc_reg_operand" "f")))]
   ""
   "fms %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
 (define_insn ""
-  [(set (match_operand:DF 0 "gen_reg_operand" "=f")
-	(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
-				  (match_operand:DF 2 "gen_reg_operand" "f"))
-			 (match_operand:DF 3 "gen_reg_operand" "f"))))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+				  (match_operand:DF 2 "gpc_reg_operand" "f"))
+			 (match_operand:DF 3 "gpc_reg_operand" "f"))))]
   ""
   "fnma %0,%1,%2,%3"
   [(set_attr "type" "fp")])
 
 (define_insn ""
-  [(set (match_operand:DF 0 "gen_reg_operand" "=f")
-	(neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
-				   (match_operand:DF 2 "gen_reg_operand" "f"))
-			  (match_operand:DF 3 "gen_reg_operand" "f"))))]
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=f")
+	(neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gpc_reg_operand" "%f")
+				   (match_operand:DF 2 "gpc_reg_operand" "f"))
+			  (match_operand:DF 3 "gpc_reg_operand" "f"))))]
   ""
   "fnms %0,%1,%2,%3"
   [(set_attr "type" "fp")])
@@ -1738,10 +1796,10 @@
 (define_expand "floatsidf2"
   [(set (match_dup 2)
 	(plus:DI (zero_extend:DI
-		  (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
+		  (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			  (match_dup 3)))
 		 (match_dup 4)))
-   (set (match_operand:DF 0 "gen_reg_operand" "")
+   (set (match_operand:DF 0 "gpc_reg_operand" "")
 	(minus:DF (subreg:DF (match_dup 2) 0)
 		  (match_dup 5)))]
   ""
@@ -1762,9 +1820,9 @@
 
 (define_expand "floatunssidf2"
   [(set (match_dup 2)
-	(plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
+	(plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
 		 (match_dup 3)))
-   (set (match_operand:DF 0 "gen_reg_operand" "")
+   (set (match_operand:DF 0 "gpc_reg_operand" "")
 	(minus:DF (subreg:DF (match_dup 2) 0)
 		  (match_dup 4)))]
   ""
@@ -1783,9 +1841,9 @@
 
 ;; For the above two cases, we always split.
 (define_split
-  [(set (match_operand:DI 0 "gen_reg_operand" "")
+  [(set (match_operand:DI 0 "gpc_reg_operand" "")
 	(plus:DI (zero_extend:DI
-		  (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
+		  (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			  (match_operand:SI 2 "logical_operand" "")))
 		 (match_operand:DI 3 "immediate_operand" "")))]
   "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
@@ -1800,9 +1858,9 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:DI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(plus:DI (zero_extend:DI
-		  (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
+		  (xor:SI (match_operand:SI 1 "gpc_reg_operand" "%r")
 			  (match_operand:SI 2 "logical_operand" "rKJ")))
 		 (match_operand:DI 3 "immediate_operand" "n")))]
   "HOST_BITS_PER_INT == BITS_PER_WORD
@@ -1811,8 +1869,8 @@
   "#")
   
 (define_split
-  [(set (match_operand:DI 0 "gen_reg_operand" "=")
-	(plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=")
+	(plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" ""))
 		 (match_operand:DI 2 "immediate_operand" "")))]
   "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
    && GET_CODE (operands[2]) == CONST_DOUBLE
@@ -1832,8 +1890,8 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:DI 0 "gen_reg_operand" "=r")
-	(plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(plus:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		 (match_operand:DI 2 "immediate_operand" "n")))]
   "HOST_BITS_PER_INT == BITS_PER_WORD
    && GET_CODE (operands[2]) == CONST_DOUBLE
@@ -1841,8 +1899,8 @@
   "#")
 
 (define_expand "fix_truncdfsi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
-	(fix:DF (match_operand:DF 1 "gen_reg_operand" "")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
   ""
   "
 {
@@ -1852,8 +1910,8 @@
 }")
 
 (define_expand "fixuns_truncdfsi2"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
-	(unsigned_fix:DF (match_operand:DF 1 "gen_reg_operand" "")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(unsigned_fix:DF (match_operand:DF 1 "gpc_reg_operand" "")))]
   ""
   "
 {
@@ -1883,12 +1941,12 @@
 }")
 
 (define_expand "trunc_call_rtl"
-  [(set (reg:DF 33) (match_operand:DF 1 "gen_reg_operand" ""))
+  [(set (reg:DF 33) (match_operand:DF 1 "gpc_reg_operand" ""))
    (use (reg:DF 33))
    (parallel [(set (reg:SI 3)
 		   (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
 	      (clobber (scratch:SI))])
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(reg:SI 3))]
   ""
   "
@@ -1899,29 +1957,29 @@
 ;; Define the DImode operations that can be done in a small number
 ;; of instructions.
 (define_insn "adddi3"
-  [(set (match_operand:DI 0 "gen_reg_operand" "=r")
-	(plus:DI (match_operand:DI 1 "gen_reg_operand" "%r")
-		 (match_operand:DI 2 "gen_reg_operand" "r")))]
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r")
+		 (match_operand:DI 2 "gpc_reg_operand" "r")))]
   ""
   "a %L0,%L1,%L2\;ae %0,%1,%2")
 
 (define_insn "subdi3"
-  [(set (match_operand:DI 0 "gen_reg_operand" "=r")
-	(minus:DI (match_operand:DI 1 "gen_reg_operand" "r")
-		  (match_operand:DI 2 "gen_reg_operand" "r")))]
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(minus:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+		  (match_operand:DI 2 "gpc_reg_operand" "r")))]
   ""
   "sf %L0,%L2,%L1\;sfe %0,%2,%1")
 
 (define_insn "negdi3"
-  [(set (match_operand:DI 0 "gen_reg_operand" "=r")
-	(neg:DI (match_operand:DI 1 "gen_reg_operand" "r")))]
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
   ""
   "sfi %L0,%L1,0\;sfze %0,%1")
 
 (define_insn "mulsidi3"
-  [(set (match_operand:DI 0 "gen_reg_operand" "=r")
-	(mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
-		 (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))))
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
+		 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))
    (clobber (match_scratch:SI 3 "=q"))]
   ""
   "mul %0,%1,%2\;mfmq %L0")
@@ -1930,8 +1988,8 @@
 ;; operands 0 and 1 (the usual case) can be in the same register.  That's
 ;; why we have the strange constraints below.
 (define_insn "ashldi3"
-  [(set (match_operand:DI 0 "gen_reg_operand" "=r,r,r,&r")
-	(ashift:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r")
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,&r")
+	(ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
 		   (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
    (clobber (match_scratch:SI 3 "=X,q,q,q"))]
   ""
@@ -1942,23 +2000,23 @@
    sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2")
 
 (define_insn "lshrdi3"
-  [(set (match_operand:DI 0 "gen_reg_operand" "=&r,r,r,&r")
-	(lshiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r")
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r,r,&r")
+	(lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,0,r")
 		     (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
    (clobber (match_scratch:SI 3 "=X,q,q,q"))]
   ""
   "@
    cal %0,0(0)\;s%A2i %L0,%1,%h2
-   s%A2%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2
-   s%A2%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2
-   s%A2%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2")
+   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
+   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2
+   sr%I2q %0,%1,%h2\;srl%I2q %L0,%L1,%h2")
 
 ;; Shift by a variable amount is too complex to be worth open-coding.  We
 ;; just handle shifts by constants.
 
 (define_expand "ashrdi3"
-  [(parallel [(set (match_operand:DI 0 "gen_reg_operand" "=")
-		   (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "")
+  [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=")
+		   (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "")
 				(match_operand:SI 2 "general_operand" "")))
 	      (clobber (match_scratch:SI 3 ""))])]
   ""
@@ -1968,14 +2026,14 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:DI 0 "gen_reg_operand" "=r,r")
-	(ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r")
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+	(ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
 		     (match_operand:SI 2 "const_int_operand" "M,i")))
    (clobber (match_scratch:SI 3 "=X,q"))]
   ""
   "@
    srai %0,%1,31\;srai %L0,%1,%h2
-   sraiq %L0,%L1,%2\;srlq %0,%1,%2")
+   sraiq %0,%1,%h2\;srliq %L0,%L1,%h2")
 
 ;; Now define ways of moving data around.
 ;;
@@ -2012,8 +2070,8 @@
 (define_insn ""
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l")
 	(match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r"))]
-  "gen_reg_operand (operands[0], SImode)
-   || gen_reg_operand (operands[1], SImode)"
+  "gpc_reg_operand (operands[0], SImode)
+   || gpc_reg_operand (operands[1], SImode)"
   "@
    ai %0,%1,0
    l%U1%X1 %0,%1
@@ -2027,9 +2085,9 @@
 
 (define_insn ""
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
-	(compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
+	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r") (match_dup 1))]
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r") (match_dup 1))]
   ""
   "ai. %0,%1,0"
   [(set_attr "type" "compare")])
@@ -2050,8 +2108,8 @@
 (define_insn ""
   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
 	(match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))]
-  "gen_reg_operand (operands[0], HImode)
-   || gen_reg_operand (operands[1], HImode)"
+  "gpc_reg_operand (operands[0], HImode)
+   || gpc_reg_operand (operands[1], HImode)"
   "@
    oril %0,%1,0
    lhz%U1%X1 %0,%1
@@ -2077,8 +2135,8 @@
 (define_insn ""
   [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
 	(match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))]
-  "gen_reg_operand (operands[0], QImode)
-   || gen_reg_operand (operands[1], QImode)"
+  "gpc_reg_operand (operands[0], QImode)
+   || gpc_reg_operand (operands[1], QImode)"
   "@
    oril %0,%1,0
    lbz%U1%X1 %0,%1
@@ -2202,7 +2260,7 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:SF 0 "gen_reg_operand" "=r,r")
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=r,r")
 	(match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))]
   "REGNO (operands[0]) <= 31"
   "@
@@ -2211,7 +2269,7 @@
   [(set_attr "type" "*,load")])
 
 (define_split
-  [(set (match_operand:SF 0 "gen_reg_operand" "")
+  [(set (match_operand:SF 0 "gpc_reg_operand" "")
 	(match_operand:SF 1 "easy_fp_constant" ""))]
   "reload_completed && REGNO (operands[0]) <= 31"
   [(set (match_dup 2) (match_dup 3))]
@@ -2222,8 +2280,8 @@
 (define_insn ""
   [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
 	(match_operand:SF 1 "input_operand" "f,m,f"))]
-  "gen_reg_operand (operands[0], SFmode)
-   || gen_reg_operand (operands[1], SFmode)"
+  "gpc_reg_operand (operands[0], SFmode)
+   || gpc_reg_operand (operands[1], SFmode)"
   "@
    fmr %0,%1
    lfs%U1%X1 %0,%1
@@ -2328,7 +2386,7 @@
 }")
 
 (define_insn ""
-  [(set (match_operand:DF 0 "gen_reg_operand" "=r,r")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "=r,r")
 	(match_operand:DF 1 "mem_or_easy_const_operand" "G,m"))]
   "REGNO (operands[0]) <= 31"
   "@
@@ -2337,7 +2395,7 @@
   [(set_attr "type" "*,load")])
 
 (define_split
-  [(set (match_operand:DF 0 "gen_reg_operand" "")
+  [(set (match_operand:DF 0 "gpc_reg_operand" "")
 	(match_operand:DF 1 "easy_fp_constant" ""))]
   "reload_completed && REGNO (operands[0]) <= 31"
   [(set (match_dup 2) (match_dup 3))
@@ -2351,8 +2409,8 @@
 (define_insn ""
   [(set (match_operand:DF 0 "fp_reg_or_mem_operand" "=f,f,m")
 	(match_operand:DF 1 "fp_reg_or_mem_operand" "f,m,f"))]
-  "gen_reg_operand (operands[0], DFmode)
-   || gen_reg_operand (operands[1], DFmode)"
+  "gpc_reg_operand (operands[0], DFmode)
+   || gpc_reg_operand (operands[1], DFmode)"
   "@
    fmr %0,%1
    lfd%U1%X1 %0,%1
@@ -2384,8 +2442,8 @@
 (define_insn ""
   [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
 	(match_operand:DI 1 "input_operand" "r,m,r"))]
-  "gen_reg_operand (operands[0], DImode)
-   || gen_reg_operand (operands[1], DImode)"
+  "gpc_reg_operand (operands[0], DImode)
+   || gpc_reg_operand (operands[1], DImode)"
   "*
 {
   switch (which_alternative)
@@ -2449,8 +2507,8 @@
   [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r")
 	(match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
    (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
-  "gen_reg_operand (operands[0], TImode)
-   || gen_reg_operand (operands[1], TImode)"
+  "gpc_reg_operand (operands[0], TImode)
+   || gpc_reg_operand (operands[1], TImode)"
   "*
 {
   switch (which_alternative)
@@ -2532,7 +2590,7 @@
 
 (define_insn ""
   [(match_parallel 0 "load_multiple_operation"
-		   [(set (match_operand:SI 1 "gen_reg_operand" "=r")
+		   [(set (match_operand:SI 1 "gpc_reg_operand" "=r")
 			 (match_operand:SI 2 "indirect_operand" "Q"))])]
   ""
   "*
@@ -2605,7 +2663,7 @@
 (define_insn ""
   [(match_parallel 0 "store_multiple_operation"
 		   [(set (match_operand:SI 1 "indirect_operand" "=Q")
-			 (match_operand:SI 2 "gen_reg_operand" "r"))
+			 (match_operand:SI 2 "gpc_reg_operand" "r"))
 		    (clobber (match_scratch:SI 3 "=q"))])]
   ""
   "stsi %2,%P1,%O0")
@@ -2620,10 +2678,10 @@
 ;; that will benefit the most).
 
 (define_insn ""
-  [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
-	(mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
+	(mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
-   (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -2632,10 +2690,10 @@
   [(set_attr "type" "load,load")])
 
 (define_insn ""
-  [(set (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+  [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
-	(match_operand:SI 3 "gen_reg_operand" "r,r"))
-   (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+	(match_operand:SI 3 "gpc_reg_operand" "r,r"))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -2643,10 +2701,10 @@
    stu %3,%2(%1)")
 
 (define_insn ""
-  [(set (match_operand:HI 3 "gen_reg_operand" "=r,r")
-	(mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+  [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
+	(mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
-   (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -2655,11 +2713,11 @@
   [(set_attr "type" "load,load")])
 
 (define_insn ""
-  [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
+  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
 	(zero_extend:SI
-	 (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+	 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			  (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
-   (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -2668,11 +2726,11 @@
   [(set_attr "type" "load,load")])
 
 (define_insn ""
-  [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
+  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
 	(sign_extend:SI
-	 (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+	 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			  (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
-   (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -2681,10 +2739,10 @@
   [(set_attr "type" "load,load")])
 
 (define_insn ""
-  [(set (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+  [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
-	(match_operand:HI 3 "gen_reg_operand" "r,r"))
-   (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+	(match_operand:HI 3 "gpc_reg_operand" "r,r"))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -2693,10 +2751,10 @@
   [(set_attr "type" "load,load")])
 
 (define_insn ""
-  [(set (match_operand:QI 3 "gen_reg_operand" "=r,r")
-	(mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+  [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r")
+	(mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
-   (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -2705,11 +2763,11 @@
   [(set_attr "type" "load,load")])
 
 (define_insn ""
-  [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
+  [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r")
 	(zero_extend:SI
-	 (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+	 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			  (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
-   (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -2718,10 +2776,10 @@
   [(set_attr "type" "load,load")])
 
 (define_insn ""
-  [(set (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+  [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
-	(match_operand:QI 3 "gen_reg_operand" "r,r"))
-   (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+	(match_operand:QI 3 "gpc_reg_operand" "r,r"))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -2729,10 +2787,10 @@
    stbu %3,%2(%1)")
 
 (define_insn ""
-  [(set (match_operand:SF 3 "gen_reg_operand" "=f,f")
-	(mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+  [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
+	(mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
-   (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -2741,10 +2799,10 @@
   [(set_attr "type" "load,load")])
 
 (define_insn ""
-  [(set (mem:SF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+  [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
-	(match_operand:SF 3 "gen_reg_operand" "f,f"))
-   (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+	(match_operand:SF 3 "gpc_reg_operand" "f,f"))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -2752,10 +2810,10 @@
    frsp %3,%3\;stfsu %3,%2(%1)")
 
 (define_insn ""
-  [(set (match_operand:DF 3 "gen_reg_operand" "=f,f")
-	(mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+  [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
+	(mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
-   (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -2764,10 +2822,10 @@
   [(set_attr "type" "load,load")])
 
 (define_insn ""
-  [(set (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
+  [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,I")))
-	(match_operand:DF 3 "gen_reg_operand" "f,f"))
-   (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
+	(match_operand:DF 3 "gpc_reg_operand" "f,f"))
+   (set (match_operand:SI 0 "gpc_reg_operand" "=b,b")
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -2777,9 +2835,7 @@
 ;; Next come insns related to the calling sequence.
 ;;
 ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
-;; We move the back-chain and decrement the stack pointer.  This is slightly
-;; less efficient than it needs to be for long constants, but that case
-;; should be rare.
+;; We move the back-chain and decrement the stack pointer.  
 
 (define_expand "allocate_stack"
   [(set (reg:SI 1)
@@ -2794,6 +2850,63 @@
   emit_move_insn (stack_bot, chain);
   DONE;
 }")
+
+;; These patterns say how to save and restore the stack pointer.  We need not
+;; save the stack pointer at function level since we are careful to
+;; preserve the backchain.  At block level, we have to restore the backchain
+;; when we restore the stack pointer.
+;;
+;; For nonlocal gotos, we must save both the stack pointer and its
+;; backchain and restore both.  Note that in the nonlocal case, the
+;; save area is a memory location.
+
+(define_expand "save_stack_function"
+  [(use (const_int 0))]
+  ""
+  "")
+
+(define_expand "restore_stack_function"
+  [(use (const_int 0))]
+  ""
+  "")
+
+(define_expand "restore_stack_block"
+  [(set (match_dup 2) (mem:SI (match_operand:SI 0 "register_operand" "")))
+   (set (match_dup 0) (match_operand:SI 1 "register_operand" ""))
+   (set (mem:SI (match_dup 0)) (match_dup 2))]
+  ""
+  "
+{ operands[2] = gen_reg_rtx (SImode); }")
+
+(define_expand "save_stack_nonlocal"
+  [(match_operand:DI 0 "memory_operand" "")
+   (match_operand:SI 1 "register_operand" "")]
+  ""
+  "
+{
+  rtx temp = gen_reg_rtx (SImode);
+
+  /* Copy the backchain to the first word, sp to the second.  */
+  emit_move_insn (temp, gen_rtx (MEM, SImode, operands[1]));
+  emit_move_insn (operand_subword (operands[0], 0, 0, DImode), temp);
+  emit_move_insn (operand_subword (operands[0], 1, 0, DImode), operands[1]);
+  DONE;
+}")
+		  
+(define_expand "restore_stack_nonlocal"
+  [(match_operand:SI 0 "register_operand" "")
+   (match_operand:DI 1 "memory_operand" "")]
+  ""
+  "
+{
+  rtx temp = gen_reg_rtx (SImode);
+
+  /* Restore the backchain from the first word, sp from the second.  */
+  emit_move_insn (temp, operand_subword (operands[1], 0, 0, DImode));
+  emit_move_insn (operands[0], operand_subword (operands[1], 1, 0, DImode));
+  emit_move_insn (gen_rtx (MEM, SImode, operands[0]), temp);
+  DONE;
+}")
 
 ;; A function pointer is a pointer to a data area whose first word contains
 ;; the actual address of the function, whose second word contains a pointer
@@ -2806,8 +2919,8 @@
 ;; operands[1] is the address of data area of the function to call
 
 (define_expand "call_via_ptr"
-  [(set (match_operand:SI 0 "gen_reg_operand" "")
-	(mem:SI (match_operand:SI 1 "gen_reg_operand" "")))
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(mem:SI (match_operand:SI 1 "gpc_reg_operand" "")))
    (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
 	(reg:SI 2))
    (set (reg:SI 2)
@@ -2865,7 +2978,7 @@
 (define_insn ""
   [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s"))
 	 (match_operand 1 "" "fg,fg"))
-   (clobber (match_scratch:SI 3 "=l,l"))]
+   (clobber (match_scratch:SI 2 "=l,l"))]
   ""
   "@
    brl\;l 2,20(1)
@@ -2889,7 +3002,7 @@
 ;; how it is used.
 (define_expand "cmpsi"
   [(set (cc0)
-        (compare (match_operand:SI 0 "gen_reg_operand" "")
+        (compare (match_operand:SI 0 "gpc_reg_operand" "")
   		 (match_operand:SI 1 "reg_or_short_operand" "")))]
   ""
   "
@@ -2907,8 +3020,8 @@
 }")
 
 (define_expand "cmpsf"
-  [(set (cc0) (compare (match_operand:SF 0 "gen_reg_operand" "")
-		       (match_operand:SF 1 "gen_reg_operand" "")))]
+  [(set (cc0) (compare (match_operand:SF 0 "gpc_reg_operand" "")
+		       (match_operand:SF 1 "gpc_reg_operand" "")))]
   ""
   "
 {
@@ -2919,8 +3032,8 @@
 }")
 
 (define_expand "cmpdf"
-  [(set (cc0) (compare (match_operand:DF 0 "gen_reg_operand" "")
-		       (match_operand:DF 1 "gen_reg_operand" "")))]
+  [(set (cc0) (compare (match_operand:DF 0 "gpc_reg_operand" "")
+		       (match_operand:DF 1 "gpc_reg_operand" "")))]
   ""
   "
 {
@@ -3083,7 +3196,7 @@
 ;; the cases we don't want to handle.
 (define_expand "seq"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(eq:SI (match_dup 2) (const_int 0)))]
   ""
   "
@@ -3095,7 +3208,7 @@
 
 (define_expand "sne"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(ne:SI (match_dup 2) (const_int 0)))]
   ""
   "
@@ -3110,7 +3223,7 @@
 ;; A > 0 is best done using the portable sequence, so fail in that case.
 (define_expand "sgt"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(gt:SI (match_dup 2) (const_int 0)))]
   ""
   "
@@ -3127,7 +3240,7 @@
 ;; A < 0 is best done in the portable way for A an integer.
 (define_expand "slt"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(lt:SI (match_dup 2) (const_int 0)))]
   ""
   "
@@ -3143,7 +3256,7 @@
 
 (define_expand "sge"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(ge:SI (match_dup 2) (const_int 0)))]
   ""
   "
@@ -3156,7 +3269,7 @@
 ;; A <= 0 is best done the portable way for A an integer.
 (define_expand "sle"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(le:SI (match_dup 2) (const_int 0)))]
   ""
   "
@@ -3172,7 +3285,7 @@
 
 (define_expand "sgtu"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(gtu:SI (match_dup 2) (const_int 0)))]
   ""
   "
@@ -3183,7 +3296,7 @@
 
 (define_expand "sltu"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(ltu:SI (match_dup 2) (const_int 0)))]
   ""
   "
@@ -3194,7 +3307,7 @@
 
 (define_expand "sgeu"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(geu:SI (match_dup 2) (const_int 0)))]
   ""
   "
@@ -3205,7 +3318,7 @@
 
 (define_expand "sleu"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(leu:SI (match_dup 2) (const_int 0)))]
   ""
   "
@@ -3217,15 +3330,43 @@
 ;; Here are the actual compare insns.
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=y")
-	(compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
+	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
 		    (match_operand:SI 2 "reg_or_short_operand" "rI")))]
   ""
   "cmp%I2 %0,%1,%2"
   [(set_attr "type" "compare")])
 
+;; If we are comparing a register for equality with a large constant,
+;; we can do this with an XOR followed by a compare.  But we need a scratch
+;; register for the result of the XOR.
+
+(define_split
+  [(set (match_operand:CC 0 "cc_reg_operand" "")
+	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
+		    (match_operand:SI 2 "non_short_cint_operand" "")))
+   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
+  "find_single_use (operands[0], insn, 0)
+   && (GET_CODE (*find_single_use (operands[0], insn, 0)) == EQ
+       || GET_CODE (*find_single_use (operands[0], insn, 0)) == NE)"
+  [(set (match_dup 3) (xor:SI (match_dup 1) (match_dup 4)))
+   (set (match_dup 0) (compare:CC (match_dup 3) (match_dup 5)))]
+  "
+{
+  /* Get the constant we are comparing against, C,  and see what it looks like
+     sign-extended to 16 bits.  Then see what constant could be XOR'ed
+     with C to get the sign-extended value.  */
+
+  int c = INTVAL (operands[2]);
+  int sextc = (c << 16) >> 16;
+  int xorv = c ^ sextc;
+
+  operands[4] = gen_rtx (CONST_INT, VOIDmode, xorv);
+  operands[5] = gen_rtx (CONST_INT, VOIDmode, sextc);
+}")
+
 (define_insn ""
   [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
-	(compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r")
+	(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
   ""
   "cmpl%I2 %0,%1,%W2"
@@ -3238,27 +3379,27 @@
 
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=y")
-	(compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
+	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
 		    (match_operand:SI 2 "short_cint_operand" "i")))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
   ""
   "#")
    
 (define_insn ""
   [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
-	(compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r")
+	(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "u_short_cint_operand" "i")))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
   ""
   "#")
    
 (define_split
   [(set (match_operand:CC 3 "cc_reg_operand" "")
-	(compare:CC (match_operand:SI 1 "gen_reg_operand" "")
+	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "")
 		    (match_operand:SI 2 "short_cint_operand" "")))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
   ""
   [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
@@ -3266,9 +3407,9 @@
 
 (define_split
   [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
-	(compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "")
+	(compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "")
 		       (match_operand:SI 2 "u_short_cint_operand" "")))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
   ""
   [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
@@ -3276,16 +3417,16 @@
 
 (define_insn ""
   [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
-	(compare:CCFP (match_operand:SF 1 "gen_reg_operand" "f")
-		      (match_operand:SF 2 "gen_reg_operand" "f")))]
+	(compare:CCFP (match_operand:SF 1 "gpc_reg_operand" "f")
+		      (match_operand:SF 2 "gpc_reg_operand" "f")))]
   ""
   "fcmpu %0,%1,%2"
   [(set_attr "type" "fpcompare")])
 
 (define_insn ""
   [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
-	(compare:CCFP (match_operand:DF 1 "gen_reg_operand" "f")
-		      (match_operand:DF 2 "gen_reg_operand" "f")))]
+	(compare:CCFP (match_operand:DF 1 "gpc_reg_operand" "f")
+		      (match_operand:DF 2 "gpc_reg_operand" "f")))]
   ""
   "fcmpu %0,%1,%2"
   [(set_attr "type" "fpcompare")])
@@ -3294,9 +3435,11 @@
 ;; way the machine works.
 ;;
 ;; Note that this is probably faster if we can put an insn between the
-;; mfcr and rlinm, but this is tricky.  Let's leave it for now.
+;; mfcr and rlinm, but this is tricky.  Let's leave it for now.  In most
+;; cases the insns below which don't use an intermediate CR field will
+;; be used instead.
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(match_operator:SI 1 "scc_comparison_operator"
 			   [(match_operand 2 "cc_reg_operand" "y")
 			    (const_int 0)]))]
@@ -3309,14 +3452,14 @@
 				       [(match_operand 2 "cc_reg_operand" "y")
 					(const_int 0)])
 		    (const_int 0)))
-   (set (match_operand:SI 3 "gen_reg_operand" "=r")
+   (set (match_operand:SI 3 "gpc_reg_operand" "=r")
 	(match_op_dup 1 [(match_dup 2) (const_int 0)]))]
   ""
   "%D1mfcr %3\;rlinm. %3,%3,%J1,30,31"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ashift:SI (match_operator:SI 1 "scc_comparison_operator"
 				      [(match_operand 2 "cc_reg_operand" "y")
 				       (const_int 0)])
@@ -3347,7 +3490,7 @@
 					(const_int 0)])
 		    (match_operand:SI 3 "const_int_operand" "n"))
 	 (const_int 0)))
-   (set (match_operand:SI 4 "gen_reg_operand" "=r")
+   (set (match_operand:SI 4 "gpc_reg_operand" "=r")
 	(ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
 		   (match_dup 3)))]
   ""
@@ -3369,6 +3512,52 @@
 }"
   [(set_attr "type" "delayed_compare")])
 
+;; If we are comparing the result of two comparisons, this can be done
+;; using creqv or crxor.
+
+(define_insn ""
+  [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y")
+	(compare:CCEQ (match_operator 1 "scc_comparison_operator"
+			      [(match_operand 2 "cc_reg_operand" "y")
+			       (const_int 0)])
+		      (match_operator 3 "scc_comparison_operator"
+			      [(match_operand 4 "cc_reg_operand" "y")
+			       (const_int 0)])))]
+  "REGNO (operands[2]) != REGNO (operands[4])"
+  "*
+{
+  enum rtx_code code1, code2;
+
+  code1 = GET_CODE (operands[1]);
+  code2 = GET_CODE (operands[3]);
+
+  if ((code1 == EQ || code1 == LT || code1 == GT
+       || code1 == LTU || code1 == GTU
+       || (code1 != NE && GET_MODE (operands[2]) == CCFPmode))
+      !=
+      (code2 == EQ || code2 == LT || code2 == GT
+       || code2 == LTU || code2 == GTU
+       || (code2 != NE && GET_MODE (operands[4]) == CCFPmode)))
+    return \"%C1%C3crxor %E0,%j1,%j3\";
+  else
+    return \"%C1%C3creqv %E0,%j1,%j3\";
+}")
+
+;; There is a 3 cycle delay between consecutive mfcr instructions
+;; so it is useful to combine 2 scc instructions to use only one mfcr.
+
+(define_peephole
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(match_operator:SI 1 "scc_comparison_operator"
+			   [(match_operand 2 "cc_reg_operand" "y")
+			    (const_int 0)]))
+   (set (match_operand:SI 3 "gpc_reg_operand" "=r")
+	(match_operator:SI 4 "scc_comparison_operator"
+			   [(match_operand 5 "cc_reg_operand" "y")
+			    (const_int 0)]))]
+   "REGNO (operands[2]) != REGNO (operands[5])"
+   "%D1%D4mfcr %3\;rlinm %0,%3,%J1,31,31\;rlinm %3,%3,%J4,31,31")
+
 ;; There are some scc insns that can be done directly, without a compare.
 ;; These are faster because they don't involve the communications between
 ;; the FXU and branch units.   In fact, we will be replacing all of the
@@ -3384,8 +3573,8 @@
 ;; the cmp/mfcr sequence we would otherwise generate.
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
-	(eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
+	(eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
 	       (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
    (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
   ""
@@ -3399,10 +3588,10 @@
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
 	(compare:CC 
-	 (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
+	 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
 		(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
 	(eq:SI (match_dup 1) (match_dup 2)))
    (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
   ""
@@ -3415,10 +3604,10 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
-	(plus:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
+	(plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
 			(match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
-		 (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r")))
+		 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))
    (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
   ""
   "@
@@ -3432,9 +3621,9 @@
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
 	(compare:CC 
 	 (plus:SI
-	  (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
+	  (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
 		 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
-	  (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))
+	  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
   ""
@@ -3450,11 +3639,11 @@
   [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
 	(compare:CC 
 	 (plus:SI
-	  (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
+	  (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
 		 (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
-	  (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))
+	  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
 	(plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
   ""
@@ -3467,8 +3656,8 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
-	(neg:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
+	(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r")
 		       (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
   ""
   "@
@@ -3480,11 +3669,11 @@
 
 ;; This is what (plus (ne X (const_int 0)) Y) looks like.
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (lshiftrt:SI
-		  (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
+		  (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
 		  (const_int 31))
-		 (match_operand:SI 2 "gen_reg_operand" "r")))
+		 (match_operand:SI 2 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
   "ai %3,%1,-1\;aze %0,%2")
@@ -3493,9 +3682,9 @@
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC
 	 (plus:SI (lshiftrt:SI
-		   (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
+		   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
 		   (const_int 31))
-		  (match_operand:SI 2 "gen_reg_operand" "r"))
+		  (match_operand:SI 2 "gpc_reg_operand" "r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
@@ -3506,11 +3695,11 @@
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
 	 (plus:SI (lshiftrt:SI
-		   (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
+		   (neg:SI (abs:SI (match_operand:SI 1 "gpc_reg_operand" "r")))
 		   (const_int 31))
-		  (match_operand:SI 2 "gen_reg_operand" "r"))
+		  (match_operand:SI 2 "gpc_reg_operand" "r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
 		 (match_dup 2)))
    (clobber (match_scratch:SI 3 "=&r"))]
@@ -3519,8 +3708,8 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 	       (match_operand:SI 2 "reg_or_short_operand" "r,O")))
    (clobber (match_scratch:SI 3 "=r,X"))]
   ""
@@ -3531,10 +3720,10 @@
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
 	(compare:CC
-	 (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	 (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 		(match_operand:SI 2 "reg_or_short_operand" "r,O"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(le:SI (match_dup 1) (match_dup 2)))
    (clobber (match_scratch:SI 3 "=r,X"))]
   ""
@@ -3544,10 +3733,10 @@
   [(set_attr "type" "delayed_compare,compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			(match_operand:SI 2 "reg_or_short_operand" "r,O"))
-		 (match_operand:SI 3 "gen_reg_operand" "r,r")))
+		 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
   ""
   "@
@@ -3557,9 +3746,9 @@
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
 	(compare:CC
-	 (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
-		  (match_operand:SI 3 "gen_reg_operand" "r,r"))
+		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
   ""
@@ -3571,11 +3760,11 @@
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
 	(compare:CC
-	 (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	 (plus:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_short_operand" "r,O"))
-		  (match_operand:SI 3 "gen_reg_operand" "r,r"))
+		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
   ""
@@ -3585,8 +3774,8 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(neg:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(neg:SI (le:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 		       (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
   ""
   "@
@@ -3594,8 +3783,8 @@
    ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "reg_or_short_operand" "rI")))]
   ""
   "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0")
@@ -3603,20 +3792,20 @@
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
 	(compare:CC
-	 (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		 (match_operand:SI 2 "reg_or_short_operand" "rI"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(leu:SI (match_dup 1) (match_dup 2)))]
    ""
   "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0"
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI"))
-		 (match_operand:SI 3 "gen_reg_operand" "r")))
+		 (match_operand:SI 3 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "sf%I2 %4,%1,%2\;aze %0,%3")
@@ -3624,9 +3813,9 @@
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC
-	 (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			  (match_operand:SI 2 "reg_or_short_operand" "rI"))
-		  (match_operand:SI 3 "gen_reg_operand" "r"))
+		  (match_operand:SI 3 "gpc_reg_operand" "r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
@@ -3636,11 +3825,11 @@
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x")
 	(compare:CC
-	 (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			  (match_operand:SI 2 "reg_or_short_operand" "rI"))
-		  (match_operand:SI 3 "gen_reg_operand" "r"))
+		  (match_operand:SI 3 "gpc_reg_operand" "r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
@@ -3648,18 +3837,18 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(neg:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(neg:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
   ""
   "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (neg:SI
-		 (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+		 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI")))
-		(match_operand:SI 3 "gen_reg_operand" "r")))
+		(match_operand:SI 3 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4")
@@ -3668,9 +3857,9 @@
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC
 	 (and:SI (neg:SI
-		  (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+		  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			  (match_operand:SI 2 "reg_or_short_operand" "rI")))
-		 (match_operand:SI 3 "gen_reg_operand" "r"))
+		 (match_operand:SI 3 "gpc_reg_operand" "r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
@@ -3681,11 +3870,11 @@
   [(set (match_operand:CC 5 "cc_reg_operand" "=x")
 	(compare:CC
 	 (and:SI (neg:SI
-		  (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+		  (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			  (match_operand:SI 2 "reg_or_short_operand" "rI")))
-		 (match_operand:SI 3 "gen_reg_operand" "r"))
+		 (match_operand:SI 3 "gpc_reg_operand" "r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
@@ -3693,8 +3882,8 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 	       (match_operand:SI 2 "reg_or_short_operand" "rI")))]
   ""
   "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31")
@@ -3702,20 +3891,20 @@
 (define_insn ""
   [(set (match_operand:SI 3 "cc_reg_operand" "=x")
 	(compare:CC
-	 (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "reg_or_short_operand" "rI"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(lt:SI (match_dup 1) (match_dup 2)))]
   ""
   "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "reg_or_short_operand" "rI"))
-		 (match_operand:SI 3 "gen_reg_operand" "r")))
+		 (match_operand:SI 3 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3")
@@ -3723,9 +3912,9 @@
 (define_insn ""
   [(set (match_operand:SI 0 "cc_reg_operand" "=x")
 	(compare:CC
-	 (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI"))
-		  (match_operand:SI 3 "gen_reg_operand" "r"))
+		  (match_operand:SI 3 "gpc_reg_operand" "r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
@@ -3735,11 +3924,11 @@
 (define_insn ""
   [(set (match_operand:SI 5 "cc_reg_operand" "=x")
 	(compare:CC
-	 (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (plus:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI"))
-		  (match_operand:SI 3 "gen_reg_operand" "r"))
+		  (match_operand:SI 3 "gpc_reg_operand" "r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
@@ -3747,15 +3936,15 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(neg:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(neg:SI (lt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
   ""
   "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 		(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
   ""
   "@
@@ -3765,10 +3954,10 @@
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
 	(compare:CC
-	 (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	 (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 		 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(ltu:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -3777,8 +3966,8 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
-	(plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
+	(plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
 			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
 		 (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
    (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
@@ -3792,7 +3981,7 @@
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
 	(compare:CC
-	 (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
+	 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
 			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
 		  (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
 	 (const_int 0)))
@@ -3808,11 +3997,11 @@
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x")
 	(compare:CC
-	 (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
+	 (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
 			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
 		  (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
 	(plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
   ""
@@ -3824,8 +4013,8 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(neg:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(neg:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			(match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
   ""
   "@
@@ -3833,8 +4022,8 @@
    ai %0,%1,%n2\;sfe %0,%0,%0")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 	       (match_operand:SI 2 "reg_or_short_operand" "rI")))
    (clobber (match_scratch:SI 3 "=r"))]
   ""
@@ -3843,10 +4032,10 @@
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
-	 (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "reg_or_short_operand" "rI"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ge:SI (match_dup 1) (match_dup 2)))
    (clobber (match_scratch:SI 3 "=r"))]
   ""
@@ -3854,10 +4043,10 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "reg_or_short_operand" "rI"))
-		 (match_operand:SI 3 "gen_reg_operand" "r")))
+		 (match_operand:SI 3 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
@@ -3865,9 +4054,9 @@
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC
-	 (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI"))
-		  (match_operand:SI 3 "gen_reg_operand" "r"))
+		  (match_operand:SI 3 "gpc_reg_operand" "r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
@@ -3877,11 +4066,11 @@
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x")
 	(compare:CC
-	 (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (plus:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI"))
-		  (match_operand:SI 3 "gen_reg_operand" "r"))
+		  (match_operand:SI 3 "gpc_reg_operand" "r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
@@ -3889,20 +4078,20 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(neg:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(neg:SI (ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
   ""
   "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
 
 ;; This is (and (neg (ge X (const_int 0))) Y).
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (neg:SI
 		 (lshiftrt:SI
-		  (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
+		  (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		  (const_int 31)))
-		(match_operand:SI 2 "gen_reg_operand" "r")))
+		(match_operand:SI 2 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
   "srai %3,%1,31\;andc %0,%2,%3")
@@ -3912,9 +4101,9 @@
 	(compare:CC
 	 (and:SI (neg:SI
 		  (lshiftrt:SI
-		   (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
+		   (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		   (const_int 31)))
-		 (match_operand:SI 2 "gen_reg_operand" "r"))
+		 (match_operand:SI 2 "gpc_reg_operand" "r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
@@ -3926,11 +4115,11 @@
 	(compare:CC
 	 (and:SI (neg:SI
 		  (lshiftrt:SI
-		   (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
+		   (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		   (const_int 31)))
-		 (match_operand:SI 2 "gen_reg_operand" "r"))
+		 (match_operand:SI 2 "gpc_reg_operand" "r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
 				     (const_int 31)))
 		(match_dup 2)))
@@ -3940,8 +4129,8 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 		(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
   ""
   "@
@@ -3951,10 +4140,10 @@
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
 	(compare:CC
-	 (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 		 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(geu:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
@@ -3963,10 +4152,10 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
-		 (match_operand:SI 3 "gen_reg_operand" "r,r")))
+		 (match_operand:SI 3 "gpc_reg_operand" "r,r")))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
   ""
   "@
@@ -3976,9 +4165,9 @@
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
 	(compare:CC
-	 (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
-		  (match_operand:SI 3 "gen_reg_operand" "r,r"))
+		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
   ""
@@ -3990,11 +4179,11 @@
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
 	(compare:CC
-	 (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
-		  (match_operand:SI 3 "gen_reg_operand" "r,r"))
+		  (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
   ""
@@ -4004,8 +4193,8 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(neg:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(neg:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			(match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
   ""
   "@
@@ -4013,11 +4202,11 @@
    sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(and:SI (neg:SI
-		 (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+		 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
-		(match_operand:SI 3 "gen_reg_operand" "r,r")))
+		(match_operand:SI 3 "gpc_reg_operand" "r,r")))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
   ""
   "@
@@ -4028,9 +4217,9 @@
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
 	(compare:CC
 	 (and:SI (neg:SI
-		  (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+		  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
-		 (match_operand:SI 3 "gen_reg_operand" "r,r"))
+		 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
   ""
@@ -4043,11 +4232,11 @@
   [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
 	(compare:CC
 	 (and:SI (neg:SI
-		  (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+		  (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			  (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
-		 (match_operand:SI 3 "gen_reg_operand" "r,r"))
+		 (match_operand:SI 3 "gpc_reg_operand" "r,r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
   ""
@@ -4057,8 +4246,8 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 	       (const_int 0)))]
   ""
   "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31")
@@ -4066,18 +4255,18 @@
 (define_insn ""
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
 	(compare:CC
-	 (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(const_int 0))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(gt:SI (match_dup 1) (const_int 0)))]
   ""
   "sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 	       (match_operand:SI 2 "reg_or_short_operand" "r")))]
   ""
   "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31")
@@ -4085,20 +4274,20 @@
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
 	(compare:CC
-	 (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "reg_or_short_operand" "r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(gt:SI (match_dup 1) (match_dup 2)))]
   ""
   "doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31"
   [(set_attr "type" "delayed_compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(const_int 0))
-		 (match_operand:SI 2 "gen_reg_operand" "r")))
+		 (match_operand:SI 2 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
   "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2")
@@ -4106,9 +4295,9 @@
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC
-	 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (const_int 0))
-		  (match_operand:SI 2 "gen_reg_operand" "r"))
+		  (match_operand:SI 2 "gpc_reg_operand" "r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
@@ -4118,11 +4307,11 @@
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
-	 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (const_int 0))
-		  (match_operand:SI 2 "gen_reg_operand" "r"))
+		  (match_operand:SI 2 "gpc_reg_operand" "r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
    (clobber (match_scratch:SI 3 "=&r"))]
   ""
@@ -4130,10 +4319,10 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "reg_or_short_operand" "r"))
-		 (match_operand:SI 3 "gen_reg_operand" "r")))
+		 (match_operand:SI 3 "gpc_reg_operand" "r")))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
   "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3")
@@ -4141,9 +4330,9 @@
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x")
 	(compare:CC
-	 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "reg_or_short_operand" "r"))
-		  (match_operand:SI 3 "gen_reg_operand" "r"))
+		  (match_operand:SI 3 "gpc_reg_operand" "r"))
 	 (const_int 0)))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
@@ -4153,11 +4342,11 @@
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x")
 	(compare:CC
-	 (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			 (match_operand:SI 2 "reg_or_short_operand" "r"))
-		  (match_operand:SI 3 "gen_reg_operand" "r"))
+		  (match_operand:SI 3 "gpc_reg_operand" "r"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r"))]
   ""
@@ -4165,22 +4354,22 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (const_int 0))))]
   ""
   "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(neg:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		       (match_operand:SI 2 "reg_or_short_operand" "r"))))]
   ""
   "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31")
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		(match_operand:SI 2 "reg_or_short_operand" "rI")))]
   ""
   "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0")
@@ -4188,18 +4377,18 @@
 (define_insn ""
   [(set (match_operand:CC 3 "cc_reg_operand" "=x")
 	(compare:CC
-	 (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+	 (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 		 (match_operand:SI 2 "reg_or_short_operand" "rI"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(gtu:SI (match_dup 1) (match_dup 2)))]
   ""
   "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0"
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
-	(plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
 		 (match_operand:SI 3 "reg_or_short_operand" "r,I")))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
@@ -4209,7 +4398,7 @@
 (define_insn ""
   [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
 	(compare:CC
-	 (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			  (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
 		  (match_operand:SI 3 "reg_or_short_operand" "r,I"))
 	 (const_int 0)))
@@ -4221,11 +4410,11 @@
 (define_insn ""
   [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
 	(compare:CC
-	 (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
+	 (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
 			  (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
 		  (match_operand:SI 3 "reg_or_short_operand" "r,I"))
 	 (const_int 0)))
-   (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
 	(plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
    (clobber (match_scratch:SI 4 "=&r,&r"))]
   ""
@@ -4233,8 +4422,8 @@
   [(set_attr "type" "compare")])
 
 (define_insn ""
-  [(set (match_operand:SI 0 "gen_reg_operand" "=r")
-	(neg:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
+	(neg:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
 			(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
   ""
   "sf%I2 %0,%1,%2\;sfe %0,%0,%0")
@@ -4391,11 +4580,11 @@
 (define_split
   [(set (pc)
 	(if_then_else (match_operator 2 "comparison_operator"
-				      [(match_operand:SI 1 "gen_reg_operand" "")
+				      [(match_operand:SI 1 "gpc_reg_operand" "")
 				       (const_int 1)])
 		      (match_operand 5 "" "")
 		      (match_operand 6 "" "")))
-   (set (match_operand:SI 0 "gen_reg_operand" "")
+   (set (match_operand:SI 0 "gpc_reg_operand" "")
 	(plus:SI (match_dup 1) (const_int -1)))
    (clobber (match_scratch:CC 3 ""))
    (clobber (match_scratch:SI 4 ""))]
@@ -4412,7 +4601,7 @@
 (define_split
   [(set (pc)
 	(if_then_else (match_operator 2 "comparison_operator"
-				      [(match_operand:SI 1 "gen_reg_operand" "")
+				      [(match_operand:SI 1 "gpc_reg_operand" "")
 				       (const_int 1)])
 		      (match_operand 5 "" "")
 		      (match_operand 6 "" "")))
@@ -4420,7 +4609,7 @@
 	(plus:SI (match_dup 1) (const_int -1)))
    (clobber (match_scratch:CC 3 ""))
    (clobber (match_scratch:SI 4 ""))]
-  "reload_completed && ! gen_reg_operand (operands[0], SImode)"
+  "reload_completed && ! gpc_reg_operand (operands[0], SImode)"
   [(parallel [(set (match_dup 3)
 		   (compare:CC (plus:SI (match_dup 1) (const_int -1))
 			       (const_int 0)))