--- gcc/config/rs6000.md	2018/04/24 18:00:04	1.1.1.3
+++ gcc/config/rs6000.md	2018/04/24 18:05:59	1.1.1.4
@@ -97,7 +97,7 @@
   [(set_attr "type" "load,*")])
 
 (define_expand "zero_extendhisi2"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "r")
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
 	(zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))]
   ""
   "")
@@ -271,7 +271,8 @@
 
 ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
 ;; instruction and some auxiliary computations.  Then we just have a single
-;; DEFINE_INSN for doz[i].
+;; DEFINE_INSN for doz[i] and the define_splits to make them if made by
+;; combine.
 
 (define_expand "sminsi3"
   [(set (match_dup 3)
@@ -285,6 +286,19 @@
   "
 { operands[3] = gen_reg_rtx (SImode); }")
 
+(define_split
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(smin:SI (match_operand:SI 1 "gpc_reg_operand" "")
+		 (match_operand:SI 2 "reg_or_short_operand" "")))
+   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
+  ""
+  [(set (match_dup 3)
+	(if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
+			 (const_int 0)
+			 (minus:SI (match_dup 2) (match_dup 1))))
+   (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 3)))]
+  "")
+
 (define_expand "smaxsi3"
   [(set (match_dup 3)
 	(if_then_else:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "")
@@ -297,6 +311,19 @@
   "
 { operands[3] = gen_reg_rtx (SImode); }")
 
+(define_split
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(smax:SI (match_operand:SI 1 "gpc_reg_operand" "")
+		 (match_operand:SI 2 "reg_or_short_operand" "")))
+   (clobber (match_operand:SI 3 "gpc_reg_operand" ""))]
+  ""
+  [(set (match_dup 3)
+	(if_then_else:SI (gt:SI (match_dup 1) (match_dup 2))
+			 (const_int 0)
+			 (minus:SI (match_dup 2) (match_dup 1))))
+   (set (match_dup 0) (plus:SI (match_dup 3) (match_dup 1)))]
+  "")
+
 (define_expand "uminsi3"
   [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gpc_reg_operand" "")
 			      (const_int -2147483648)))
@@ -535,13 +562,13 @@
 	 (plus:DI (lshift:DI
 		   (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r"))
 		   (const_int 32))
-		  (zero_extend:DI (match_operand:SI 2 "register_operand" "*q")))
+		  (zero_extend:DI (match_operand:SI 4 "register_operand" "2")))
 	 (match_operand:SI 3 "gpc_reg_operand" "r")))
-   (set (match_operand:SI 4 "register_operand" "=*q")
+   (set (match_operand:SI 2 "register_operand" "=*q")
 	(umod:SI
 	 (plus:DI (lshift:DI
 		   (zero_extend:DI (match_dup 1)) (const_int 32))
-		  (zero_extend:DI (match_dup 2)))
+		  (zero_extend:DI (match_dup 4)))
 	 (match_dup 3)))]
   
   ""
@@ -938,98 +965,98 @@
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-			(match_operand:SI 2 "gpc_reg_operand" "0"))
-		(and:SI (match_dup 1)
+	(ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
+			(match_operand:SI 1 "gpc_reg_operand" "0"))
+		(and:SI (match_dup 2)
 			(match_operand:SI 3 "gpc_reg_operand" "r"))))]
   ""
-  "maskir %0,%3,%1")
+  "maskir %0,%3,%2")
 
 (define_insn ""
   [(set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-			(match_operand:SI 2 "gpc_reg_operand" "0"))
+	(ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
+			(match_operand:SI 1 "gpc_reg_operand" "0"))
 		(and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
-			(match_dup 1))))]
+			(match_dup 2))))]
   ""
-  "maskir %0,%3,%1")
+  "maskir %0,%3,%2")
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (match_dup 1)
+	(ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
 			(match_operand:SI 3 "gpc_reg_operand" "r"))
-		(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-			(match_operand:SI 2 "gpc_reg_operand" "0"))))]
+		(and:SI (not:SI (match_dup 2))
+			(match_operand:SI 1 "gpc_reg_operand" "0"))))]
   ""
-  "maskir %0,%3,%1")
+  "maskir %0,%3,%2")
 
 (define_insn ""
   [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
 	(ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
-			(match_dup 1))
-		(and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-			(match_operand:SI 2 "gpc_reg_operand" "0"))))]
+			(match_operand:SI 2 "gpc_reg_operand" "r"))
+		(and:SI (not:SI (match_dup 2))
+			(match_operand:SI 1 "gpc_reg_operand" "0"))))]
   ""
-  "maskir %0,%3,%1")
+  "maskir %0,%3,%2")
 
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
-	 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-			 (match_operand:SI 2 "gpc_reg_operand" "0"))
-		 (and:SI (match_dup 1)
+	 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
+			 (match_operand:SI 1 "gpc_reg_operand" "0"))
+		 (and:SI (match_dup 2)
 			 (match_operand:SI 3 "gpc_reg_operand" "r")))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
-		(and:SI (match_dup 1) (match_dup 3))))]
+	(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
+		(and:SI (match_dup 2) (match_dup 3))))]
   ""
-  "maskir. %0,%3,%1"
+  "maskir. %0,%3,%2"
   [(set_attr "type" "compare")])
 
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
-	 (ior:SI (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-			 (match_operand:SI 2 "gpc_reg_operand" "0"))
+	 (ior:SI (and:SI (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))
+			 (match_operand:SI 1 "gpc_reg_operand" "0"))
 		 (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
-			 (match_dup 1)))
+			 (match_dup 2)))
 	 (const_int 0)))
    (set (match_operand:SI 0 "register_operand" "=r")
-	(ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
-		(and:SI (match_dup 3) (match_dup 1))))]
+	(ior:SI (and:SI (not:SI (match_dup 2)) (match_dup 1))
+		(and:SI (match_dup 3) (match_dup 2))))]
   ""
-  "maskir. %0,%3,%1"
+  "maskir. %0,%3,%2"
   [(set_attr "type" "compare")])
 
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
-	 (ior:SI (and:SI (match_dup 1)
+	 (ior:SI (and:SI (match_operand:SI 2 "gpc_reg_operand" "r")
 			 (match_operand:SI 3 "gpc_reg_operand" "r"))
-		 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-			 (match_operand:SI 2 "gpc_reg_operand" "0")))
+		 (and:SI (not:SI (match_dup 2))
+			 (match_operand:SI 1 "gpc_reg_operand" "0")))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (match_dup 1) (match_dup 3))
-		(and:SI (not:SI (match_dup 1)) (match_dup 2))))]
+	(ior:SI (and:SI (match_dup 2) (match_dup 3))
+		(and:SI (not:SI (match_dup 2)) (match_dup 1))))]
   ""
-  "maskir. %0,%3,%1"
+  "maskir. %0,%3,%2"
   [(set_attr "type" "compare")])
 
 (define_insn ""
   [(set (match_operand:CC 4 "cc_reg_operand" "=x")
 	(compare:CC
 	 (ior:SI (and:SI (match_operand:SI 3 "gpc_reg_operand" "r")
-			 (match_dup 1))
-		 (and:SI (not:SI (match_operand:SI 1 "gpc_reg_operand" "r"))
-			 (match_operand:SI 2 "gpc_reg_operand" "0")))
+			 (match_operand:SI 2 "gpc_reg_operand" "r"))
+		 (and:SI (not:SI (match_dup 2))
+			 (match_operand:SI 1 "gpc_reg_operand" "0")))
 	 (const_int 0)))
    (set (match_operand:SI 0 "gpc_reg_operand" "=r")
-	(ior:SI (and:SI (match_dup 3) (match_dup 1))
-		(and:SI (not:SI (match_dup 1)) (match_dup 2))))]
+	(ior:SI (and:SI (match_dup 3) (match_dup 2))
+		(and:SI (not:SI (match_dup 2)) (match_dup 1))))]
   ""
-  "maskir. %0,%3,%1"
+  "maskir. %0,%3,%2"
   [(set_attr "type" "compare")])
 
 ;; Rotate and shift insns, in all their variants.  These support shifts,
@@ -1887,6 +1914,14 @@
       emit_move_insn (operands[3], operands[4]);
       DONE;
     }
+
+  if (rtx_equal_p (operands[1], operands[3]))
+    {
+      rtx temp;
+
+      temp = operands[3]; operands[3] = operands[5]; operands[5] = temp;
+      temp = operands[4]; operands[4] = operands[1]; operands[1] = temp;
+    }
 }")
 
 (define_insn ""
@@ -1970,7 +2005,7 @@
   ""
   "sf %L0,%L2,%L1\;sfe %0,%2,%1")
 
-(define_insn "negdi3"
+(define_insn "negdi2"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
 	(neg:DI (match_operand:DI 1 "gpc_reg_operand" "r")))]
   ""
@@ -2083,6 +2118,26 @@
    mt%0 %1"
   [(set_attr "type" "*,load,*,*,*,*,*,mtlr")])
 
+;; Split a load of a large constant into the appropriate two-insn
+;; sequence.
+
+(define_split
+  [(set (match_operand:SI 0 "gpc_reg_operand" "")
+	(match_operand:SI 1 "const_int_operand" ""))]
+  "(unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
+   && (INTVAL (operands[1]) & 0xffff) != 0"
+  [(set (match_dup 0)
+	(match_dup 2))
+   (set (match_dup 0)
+	(ior:SI (match_dup 0)
+		(match_dup 3)))]
+  "
+{
+  operands[2] = gen_rtx (CONST_INT, VOIDmode,
+			 INTVAL (operands[1]) & 0xffff0000);
+  operands[3] = gen_rtx (CONST_INT, VOIDmode, INTVAL (operands[1]) & 0xffff);
+}")
+
 (define_insn ""
   [(set (match_operand:CC 2 "cc_reg_operand" "=x")
 	(compare:CC (match_operand:SI 1 "gpc_reg_operand" "r")
@@ -2425,11 +2480,8 @@
   ""
   "
 {
-  if (GET_CODE (operands[0]) == MEM)
-    operands[1] = force_reg (DImode, operands[1]);
-
-  else if (GET_CODE (operands[1]) == CONST_DOUBLE
-	   || GET_CODE (operands[1]) == CONST_INT)
+  if (GET_CODE (operands[1]) == CONST_DOUBLE
+      || GET_CODE (operands[1]) == CONST_INT)
     {
       emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
 		      operand_subword (operands[1], 0, 0, DImode));
@@ -2437,6 +2489,9 @@
 		      operand_subword (operands[1], 1, 0, DImode));
       DONE;
     }
+
+  if (GET_CODE (operands[0]) == MEM)
+    operands[1] = force_reg (DImode, operands[1]);
 }")
 
 (define_insn ""
@@ -2554,9 +2609,9 @@
   [(set_attr "type" "*,load,load,*,*")])
 
 (define_expand "load_multiple"
-  [(match_parallel 3 "" [(set (match_operand:SI 0 "" "")
-			      (match_operand:SI 1 "" ""))
-			 (use (match_operand:SI 2 "" ""))])]
+  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
+			  (match_operand:SI 1 "" ""))
+		     (use (match_operand:SI 2 "" ""))])]
   ""
   "
 {
@@ -2619,10 +2674,10 @@
   [(set_attr "type" "load")])
 
 (define_expand "store_multiple"
-  [(match_parallel 3 "" [(set (match_operand:SI 0 "" "")
-			      (match_operand:SI 1 "" ""))
-			 (clobber (scratch:SI))
-			 (use (match_operand:SI 2 "" ""))])]
+  [(match_par_dup 3 [(set (match_operand:SI 0 "" "")
+			  (match_operand:SI 1 "" ""))
+		     (clobber (scratch:SI))
+		     (use (match_operand:SI 2 "" ""))])]
   ""
   "
 {
@@ -2685,8 +2740,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   lux %3,%1,%2
-   lu %3,%2(%1)"
+   lux %3,%0,%2
+   lu %3,%2(%0)"
   [(set_attr "type" "load,load")])
 
 (define_insn ""
@@ -2697,8 +2752,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   stux %3,%1,%2
-   stu %3,%2(%1)")
+   stux %3,%0,%2
+   stu %3,%2(%0)")
 
 (define_insn ""
   [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r")
@@ -2708,8 +2763,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   lhzux %3,%1,%2
-   lhzu %3,%2(%1)"
+   lhzux %3,%0,%2
+   lhzu %3,%2(%0)"
   [(set_attr "type" "load,load")])
 
 (define_insn ""
@@ -2721,8 +2776,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   lhzux %3,%1,%2
-   lhzu %3,%2(%1)"
+   lhzux %3,%0,%2
+   lhzu %3,%2(%0)"
   [(set_attr "type" "load,load")])
 
 (define_insn ""
@@ -2734,8 +2789,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   lhaux %3,%1,%2
-   lhau %3,%2(%1)"
+   lhaux %3,%0,%2
+   lhau %3,%2(%0)"
   [(set_attr "type" "load,load")])
 
 (define_insn ""
@@ -2746,8 +2801,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   sthux %3,%1,%2
-   sthu %3,%2(%1)"
+   sthux %3,%0,%2
+   sthu %3,%2(%0)"
   [(set_attr "type" "load,load")])
 
 (define_insn ""
@@ -2758,8 +2813,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   lbzux %3,%1,%2
-   lbzu %3,%2(%1)"
+   lbzux %3,%0,%2
+   lbzu %3,%2(%0)"
   [(set_attr "type" "load,load")])
 
 (define_insn ""
@@ -2771,8 +2826,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   lbzux %3,%1,%2
-   lbzu %3,%2(%1)"
+   lbzux %3,%0,%2
+   lbzu %3,%2(%0)"
   [(set_attr "type" "load,load")])
 
 (define_insn ""
@@ -2783,8 +2838,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   stbux %3,%1,%2
-   stbu %3,%2(%1)")
+   stbux %3,%0,%2
+   stbu %3,%2(%0)")
 
 (define_insn ""
   [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f")
@@ -2794,8 +2849,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   lfsux %3,%1,%2
-   lfsu %3,%2(%1)"
+   lfsux %3,%0,%2
+   lfsu %3,%2(%0)"
   [(set_attr "type" "load,load")])
 
 (define_insn ""
@@ -2806,8 +2861,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   frsp %3,%3\;stfsux %3,%1,%2
-   frsp %3,%3\;stfsu %3,%2(%1)")
+   frsp %3,%3\;stfsux %3,%0,%2
+   frsp %3,%3\;stfsu %3,%2(%0)")
 
 (define_insn ""
   [(set (match_operand:DF 3 "gpc_reg_operand" "=f,f")
@@ -2817,8 +2872,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   lfdux %3,%1,%2
-   lfdu %3,%2(%1)"
+   lfdux %3,%0,%2
+   lfdu %3,%2(%0)"
   [(set_attr "type" "load,load")])
 
 (define_insn ""
@@ -2829,8 +2884,8 @@
 	(plus:SI (match_dup 1) (match_dup 2)))]
   ""
   "@
-   stfdux %3,%1,%2
-   stfdu %3,%2(%1)")
+   stfdux %3,%0,%2
+   stfdu %3,%2(%0)")
 
 ;; Next come insns related to the calling sequence.
 ;;
@@ -2839,7 +2894,7 @@
 
 (define_expand "allocate_stack"
   [(set (reg:SI 1)
-	(minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_cint_operand" "")))]
+	(minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_short_operand" "")))]
   ""
   "
 { rtx chain = gen_reg_rtx (SImode);
@@ -2985,7 +3040,7 @@
    bl %z0\;cror 15,15,15")
 
 (define_insn ""
-  [(set (match_operand 0 "" "fg,fg")
+  [(set (match_operand 0 "" "=fg,fg")
 	(call (mem:SI (match_operand:SI 1 "call_operand" "l,s"))
 	      (match_operand 2 "" "fg,fg")))
    (clobber (match_scratch:SI 3 "=l,l"))]
@@ -4512,7 +4567,7 @@
 
 (define_insn ""
   [(set (pc)
-	(match_operand:SI 0 "register_operand" "c,r"))
+	(match_operand:SI 0 "register_operand" "c,l"))
    (use (label_ref (match_operand 1 "" "")))]
   ""
   "@