![[BACK]](/cvsweb/icons/back.gif){kind=icon}
Return to rs6000.md CVS log ![[TXT]](/cvsweb/icons/text.gif){kind=icon}
![[DIR]](/cvsweb/icons/dir.gif){kind=icon}
Up to [GCC 2.x] / gcc / config|
Return to rs6000.md CVS log | Up to [GCC 2.x] / gcc / config |
1.1 root 1: ;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2: ;; Copyright (C) 1990, 1991 Free Software Foundation, Inc.
3: ;; Contributed by Richard Kenner ([email protected])
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 2, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22:
23: ;; Define an insn type attribute. This is used in function unit delay
24: ;; computations.
25: (define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare"
26: (const_string "integer"))
27:
28: ;; Memory delivers its result in two cycles.
29: (define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0)
30:
31: ;; We consider floating-point insns to deliver their result in two cycles
32: ;; to try to intersperse integer and FP operations.
33: (define_function_unit "fp" 1 0 (eq_attr "type" "fp,fpcompare") 2 0)
34:
35: ;; Most integer comparisons are ready in four cycles (a stall of three).
36: (define_function_unit "compare" 1 0 (eq_attr "type" "compare") 4 0)
37:
38: ;; Some integer comparisons aren't ready for five cycles (a stall of four).
39: (define_function_unit "compare" 1 0 (eq_attr "type" "delayed_compare") 5 0)
40:
41: ;; Floating-point comparisons take eight cycles.
42: (define_function_unit "compare" 1 0 (eq_attr "type" "fpcompare") 8 0)
43:
44: ;; Start with fixed-point load and store insns. Here we put only the more
45: ;; complex forms. Basic data transfer is done later.
46:
47: (define_expand "zero_extendqisi2"
48: [(set (match_operand:SI 0 "gen_reg_operand" "")
49: (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "")))]
50: ""
51: "")
52:
53: (define_insn ""
54: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
55: (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
56: ""
57: "@
58: lbz%U1%X1 %0,%1
59: rlinm %0,%1,0,24,31"
60: [(set_attr "type" "load,*")])
61:
62: (define_insn ""
63: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
64: (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r"))
65: (const_int 0)))
66: (clobber (match_scratch:SI 2 "=r"))]
67: ""
68: "andil. %2,%1,255"
69: [(set_attr "type" "compare")])
70:
71: (define_insn ""
72: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
73: (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r"))
74: (const_int 0)))
75: (set (match_operand:SI 0 "gen_reg_operand" "=r")
76: (zero_extend:SI (match_dup 1)))]
77: ""
78: "andil. %0,%1,255"
79: [(set_attr "type" "compare")])
80:
81: (define_expand "zero_extendqihi2"
82: [(set (match_operand:HI 0 "gen_reg_operand" "")
83: (zero_extend:HI (match_operand:QI 1 "gen_reg_operand" "")))]
84: ""
85: "")
86:
87: (define_insn ""
88: [(set (match_operand:HI 0 "gen_reg_operand" "=r,r")
89: (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
90: ""
91: "@
92: lbz%U1%X1 %0,%1
93: rlinm %0,%1,0,24,31"
94: [(set_attr "type" "load,*")])
95:
96: (define_expand "zero_extendhisi2"
97: [(set (match_operand:SI 0 "gen_reg_operand" "r")
98: (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
99: ""
100: "")
101:
102: (define_insn ""
103: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
104: (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
105: ""
106: "@
107: lhz%U1%X1 %0,%1
108: rlinm %0,%1,0,16,31"
109: [(set_attr "type" "load,*")])
110:
111: (define_insn ""
112: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
113: (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
114: (const_int 0)))
115: (clobber (match_scratch:SI 2 "=r"))]
116: ""
117: "andil. %2,%1,65535"
118: [(set_attr "type" "compare")])
119:
120: (define_insn ""
121: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
122: (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
123: (const_int 0)))
124: (set (match_operand:SI 0 "gen_reg_operand" "=r")
125: (zero_extend:SI (match_dup 1)))]
126: ""
127: "andil. %0,%1,65535"
128: [(set_attr "type" "compare")])
129:
130: (define_expand "extendhisi2"
131: [(set (match_operand:SI 0 "gen_reg_operand" "")
132: (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
133: ""
134: "")
135:
136: (define_insn ""
137: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
138: (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
139: ""
140: "@
141: lha%U1%X1 %0,%1
142: exts %0,%1"
143: [(set_attr "type" "load,*")])
144:
145: (define_insn ""
146: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
147: (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
148: (const_int 0)))
149: (clobber (match_scratch:SI 2 "=r"))]
150: ""
151: "exts. %2,%1"
152: [(set_attr "type" "compare")])
153:
154: (define_insn ""
155: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
156: (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
157: (const_int 0)))
158: (set (match_operand:SI 0 "gen_reg_operand" "=r")
159: (sign_extend:SI (match_dup 1)))]
160: ""
161: "exts. %0,%1"
162: [(set_attr "type" "compare")])
163:
164: ;; Fixed-point arithmetic insns.
165: (define_insn ""
166: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
167: (plus:SI (match_operand:SI 1 "gen_reg_operand" "%r,b")
168: (match_operand:SI 2 "add_operand" "rI,J")))]
169: ""
170: "@
171: a%I2 %0,%1,%2
172: cau %0,%1,%u2")
173:
174: (define_insn ""
175: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
176: (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r")
177: (match_operand:SI 2 "reg_or_short_operand" "rI"))
178: (const_int 0)))
179: (clobber (match_scratch:SI 3 "=r"))]
180: ""
181: "a%I2. %3,%1,%2"
182: [(set_attr "type" "compare")])
183:
184: (define_insn ""
185: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
186: (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r")
187: (match_operand:SI 2 "reg_or_short_operand" "rI"))
188: (const_int 0)))
189: (set (match_operand:SI 0 "gen_reg_operand" "=r")
190: (plus:SI (match_dup 1) (match_dup 2)))]
191: ""
192: "a%I2. %0,%1,%2"
193: [(set_attr "type" "compare")])
194:
195: (define_expand "addsi3"
196: [(set (match_operand:SI 0 "gen_reg_operand" "")
197: (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
198: (match_operand:SI 2 "reg_or_cint_operand" "")))]
199: ""
200: "
201: {
202: if (GET_CODE (operands[2]) == CONST_INT
203: && (unsigned) (INTVAL (operands[2]) + 0x8000) >= 0x10000
204: && (INTVAL (operands[2]) & 0xffff) != 0)
205: {
206: int low = INTVAL (operands[2]) & 0xffff;
207: int high = (unsigned) INTVAL (operands[2]) >> 16;
208:
209: if (low & 0x8000)
210: high++, low |= 0xffff0000;
211:
212: emit_insn (gen_addsi3 (operands[0], operands[1],
213: gen_rtx (CONST_INT, VOIDmode, high << 16)));
214: operands[1] = operands[0];
215: operands[2] = gen_rtx (CONST_INT, VOIDmode, low);
216: }
217: }")
218:
219: (define_insn "one_cmplsi2"
220: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
221: (not:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
222: ""
223: "sfi %0,%1,-1")
224:
225: (define_insn ""
226: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
227: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
228: (match_operand:SI 2 "gen_reg_operand" "r,r")))]
229: ""
230: "@
231: sf %0,%2,%1
232: sfi %0,%2,%1")
233:
234: (define_insn ""
235: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
236: (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r")
237: (match_operand:SI 2 "gen_reg_operand" "r"))
238: (const_int 0)))
239: (clobber (match_scratch:SI 3 "=r"))]
240: ""
241: "sf. %3,%2,%1"
242: [(set_attr "type" "compare")])
243:
244: (define_insn ""
245: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
246: (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r")
247: (match_operand:SI 2 "gen_reg_operand" "r"))
248: (const_int 0)))
249: (set (match_operand:SI 0 "gen_reg_operand" "=r")
250: (minus:SI (match_dup 1) (match_dup 2)))]
251: ""
252: "sf. %0,%2,%1"
253: [(set_attr "type" "compare")])
254:
255: (define_expand "subsi3"
256: [(set (match_operand:SI 0 "gen_reg_operand" "")
257: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
258: (match_operand:SI 2 "reg_or_cint_operand" "")))]
259: ""
260: "
261: {
262: if (GET_CODE (operands[2]) == CONST_INT)
263: {
264: emit_insn (gen_addsi3 (operands[0], operands[1],
265: negate_rtx (SImode, operands[2])));
266: DONE;
267: }
268: else
269: operands[2] = force_reg (SImode, operands[2]);
270: }")
271:
272: ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
273: ;; instruction and some auxiliary computations. Then we just have a single
274: ;; DEFINE_INSN for doz[i].
275:
276: (define_expand "sminsi3"
277: [(set (match_dup 3)
278: (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "")
279: (match_operand:SI 2 "reg_or_short_operand" ""))
280: (const_int 0)
281: (minus:SI (match_dup 2) (match_dup 1))))
282: (set (match_operand:SI 0 "gen_reg_operand" "")
283: (minus:SI (match_dup 2) (match_dup 3)))]
284: ""
285: "
286: { operands[3] = gen_reg_rtx (SImode); }")
287:
288: (define_expand "smaxsi3"
289: [(set (match_dup 3)
290: (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "")
291: (match_operand:SI 2 "reg_or_short_operand" ""))
292: (const_int 0)
293: (minus:SI (match_dup 2) (match_dup 1))))
294: (set (match_operand:SI 0 "gen_reg_operand" "")
295: (plus:SI (match_dup 3) (match_dup 1)))]
296: ""
297: "
298: { operands[3] = gen_reg_rtx (SImode); }")
299:
300: (define_expand "uminsi3"
301: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
302: (const_int -2147483648)))
303: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "")
304: (const_int -2147483648)))
305: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
306: (const_int 0)
307: (minus:SI (match_dup 4) (match_dup 3))))
308: (set (match_operand:SI 0 "gen_reg_operand" "")
309: (minus:SI (match_dup 2) (match_dup 3)))]
310: ""
311: "
312: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
313:
314: (define_expand "umaxsi3"
315: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
316: (const_int -2147483648)))
317: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "")
318: (const_int -2147483648)))
319: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
320: (const_int 0)
321: (minus:SI (match_dup 4) (match_dup 3))))
322: (set (match_operand:SI 0 "gen_reg_operand" "")
323: (plus:SI (match_dup 3) (match_dup 1)))]
324: ""
325: "
326: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
327:
328: (define_insn ""
329: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
330: (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
331: (match_operand:SI 2 "reg_or_short_operand" "r"))
332: (const_int 0)
333: (minus:SI (match_dup 2) (match_dup 1))))]
334: ""
335: "doz%I2 %0,%1,%2")
336:
337: (define_insn ""
338: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
339: (compare:CC
340: (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
341: (match_operand:SI 2 "reg_or_short_operand" "r"))
342: (const_int 0)
343: (minus:SI (match_dup 2) (match_dup 1)))
344: (const_int 0)))
345: (clobber (match_scratch:SI 3 "=r"))]
346: ""
347: "doz%I2. %3,%1,%2"
348: [(set_attr "type" "delayed_compare")])
349:
350: (define_insn ""
351: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
352: (compare:CC
353: (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
354: (match_operand:SI 2 "reg_or_short_operand" "r"))
355: (const_int 0)
356: (minus:SI (match_dup 2) (match_dup 1)))
357: (const_int 0)))
358: (set (match_operand:SI 0 "gen_reg_operand" "=r")
359: (if_then_else:SI (gt (match_dup 1) (match_dup 2))
360: (const_int 0)
361: (minus:SI (match_dup 2) (match_dup 1))))]
362: ""
363: "doz%I2. %0,%1,%2"
364: [(set_attr "type" "delayed_compare")])
365:
366: ;; We don't need abs with condition code because such comparisons should
367: ;; never be done.
368: (define_insn "abssi2"
369: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
370: (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
371: ""
372: "abs %0,%1")
373:
374: (define_insn ""
375: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
376: (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))))]
377: ""
378: "nabs %0,%1")
379:
380: (define_insn "negsi2"
381: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
382: (neg:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
383: ""
384: "neg %0,%1")
385:
386: (define_insn ""
387: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
388: (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r"))
389: (const_int 0)))
390: (clobber (match_scratch:SI 2 "=r"))]
391: ""
392: "neg. %2,%1"
393: [(set_attr "type" "compare")])
394:
395: (define_insn ""
396: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
397: (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r"))
398: (const_int 0)))
399: (set (match_operand:SI 0 "gen_reg_operand" "=r")
400: (neg:SI (match_dup 1)))]
401: ""
402: "neg. %0,%1"
403: [(set_attr "type" "compare")])
404:
405: (define_insn "ffssi2"
406: [(set (match_operand:SI 0 "register_operand" "=&r")
407: (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
408: ""
409: "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi %0,%0,32")
410:
411: ;; There is no need for (set (condition) (compare (ffs) 0)) because that
412: ;; can be simplified to an ordinary comparison. A parallel set and compare
413: ;; might be used, so include it.
414:
415: (define_insn ""
416: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
417: (compare:CC (ffs:SI (match_operand:SI 1 "register_operand" "r"))
418: (const_int 0)))
419: (set (match_operand:SI 0 "register_operand" "=&r")
420: (ffs:SI (match_dup 1)))]
421: ""
422: "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi. %0,%0,32"
423: [(set_attr "type" "compare")])
424:
425: (define_insn "mulsi3"
426: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
427: (mult:SI (match_operand:SI 1 "gen_reg_operand" "%r,r")
428: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
429: (clobber (match_scratch:SI 3 "=q,q"))]
430: ""
431: "@
432: muls %0,%1,%2
433: muli %0,%1,%2")
434:
435: (define_insn ""
436: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
437: (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r")
438: (match_operand:SI 2 "gen_reg_operand" "r"))
439: (const_int 0)))
440: (clobber (match_scratch:SI 3 "=r"))
441: (clobber (match_scratch:SI 4 "=q"))]
442: ""
443: "muls. %3,%1,%2"
444: [(set_attr "type" "delayed_compare")])
445:
446: (define_insn ""
447: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
448: (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r")
449: (match_operand:SI 2 "gen_reg_operand" "r"))
450: (const_int 0)))
451: (set (match_operand:SI 0 "gen_reg_operand" "=r")
452: (mult:SI (match_dup 1) (match_dup 2)))
453: (clobber (match_scratch:SI 4 "=q"))]
454: ""
455: "muls. %0,%1,%2"
456: [(set_attr "type" "delayed_compare")])
457:
458: ;; Operand 1 is divided by operand 2; quotient goes to operand
459: ;; 0 and remainder to operand 3.
460: ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
461:
462: (define_insn "divmodsi4"
463: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
464: (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
465: (match_operand:SI 2 "gen_reg_operand" "r")))
466: (set (match_operand:SI 3 "gen_reg_operand" "=q")
467: (mod:SI (match_dup 1) (match_dup 2)))]
468: ""
469: "divs %0,%1,%2")
470:
471: ;; For powers of two we can do srai/aze for divide and then adjust for
472: ;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used.
473: (define_expand "divsi3"
474: [(set (match_operand:SI 0 "gen_reg_operand" "")
475: (div:SI (match_operand:SI 1 "gen_reg_operand" "")
476: (match_operand:SI 2 "reg_or_cint_operand" "")))]
477: ""
478: "
479: {
480: if (GET_CODE (operands[2]) != CONST_INT
481: || exact_log2 (INTVAL (operands[2])) < 0)
482: FAIL;
483: }")
484:
485: (define_expand "modsi3"
486: [(set (match_dup 3)
487: (div:SI (match_operand:SI 1 "gen_reg_operand" "")
488: (match_operand:SI 2 "reg_or_cint_operand" "")))
489: (parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5)))
490: (clobber (scratch:SI))])
491: (set (match_operand:SI 0 "gen_reg_operand" "")
492: (minus:SI (match_dup 1) (match_dup 4)))]
493: ""
494: "
495: {
496: int i = exact_log2 (INTVAL (operands[2]));
497:
498: if (GET_CODE (operands[2]) != CONST_INT || i < 0)
499: FAIL;
500:
501: operands[3] = gen_reg_rtx (SImode);
502: operands[4] = gen_reg_rtx (SImode);
503: operands[5] = gen_rtx (CONST_INT, VOIDmode, i);
504: }")
505:
506: (define_insn ""
507: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
508: (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
509: (match_operand:SI 2 "const_int_operand" "N")))]
510: "exact_log2 (INTVAL (operands[2])) >= 0"
511: "srai %0,%1,%p2\;aze %0,%0")
512:
513: (define_insn ""
514: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
515: (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
516: (match_operand:SI 2 "const_int_operand" "N")))
517: (clobber (match_scratch:SI 3 "=r"))]
518: "exact_log2 (INTVAL (operands[2])) >= 0"
519: "srai %3,%1,%p2\;aze. %3,%3"
520: [(set_attr "type" "compare")])
521:
522: (define_insn ""
523: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
524: (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
525: (match_operand:SI 2 "const_int_operand" "N")))
526: (set (match_operand:SI 0 "gen_reg_operand" "=r")
527: (div:SI (match_dup 1) (match_dup 2)))]
528: "exact_log2 (INTVAL (operands[2])) >= 0"
529: "srai %0,%1,%p2\;aze. %0,%0"
530: [(set_attr "type" "compare")])
531:
532: (define_insn ""
533: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
534: (udiv:SI
535: (plus:DI (lshift:DI
536: (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
537: (const_int 32))
538: (zero_extend:DI (match_operand:SI 2 "register_operand" "*q")))
539: (match_operand:SI 3 "gen_reg_operand" "r")))
540: (set (match_operand:SI 4 "register_operand" "=*q")
541: (umod:SI
542: (plus:DI (lshift:DI
543: (zero_extend:DI (match_dup 1)) (const_int 32))
544: (zero_extend:DI (match_dup 2)))
545: (match_dup 3)))]
546:
547: ""
548: "div %0,%1,%3")
549:
550: ;; To do unsigned divide we handle the cases of the divisor looking like a
551: ;; negative number. If it is a constant that is less than 2**31, we don't
552: ;; have to worry about the branches. So make a few subroutines here.
553: ;;
554: ;; First comes the normal case.
555: (define_expand "udivmodsi4_normal"
556: [(set (match_dup 4) (const_int 0))
557: (parallel [(set (match_operand:SI 0 "" "")
558: (udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
559: (const_int 32))
560: (zero_extend:DI (match_operand:SI 1 "" "")))
561: (match_operand:SI 2 "" "")))
562: (set (match_operand:SI 3 "" "")
563: (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
564: (const_int 32))
565: (zero_extend:DI (match_dup 1)))
566: (match_dup 2)))])]
567: ""
568: "
569: { operands[4] = gen_reg_rtx (SImode); }")
570:
571: ;; This handles the branches.
572: (define_expand "udivmodsi4_tests"
573: [(set (match_operand:SI 0 "" "") (const_int 0))
574: (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
575: (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
576: (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
577: (label_ref (match_operand:SI 4 "" "")) (pc)))
578: (set (match_dup 0) (const_int 1))
579: (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
580: (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
581: (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
582: (label_ref (match_dup 4)) (pc)))]
583: ""
584: "
585: { operands[5] = gen_reg_rtx (CCUNSmode);
586: operands[6] = gen_reg_rtx (CCmode);
587: }")
588:
589: (define_expand "udivmodsi4"
590: [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
591: (udiv:SI (match_operand:SI 1 "gen_reg_operand" "")
592: (match_operand:SI 2 "reg_or_cint_operand" "")))
593: (set (match_operand:SI 3 "gen_reg_operand" "")
594: (umod:SI (match_dup 1) (match_dup 2)))])]
595: ""
596: "
597: {
598: rtx label = 0;
599:
600: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
601: {
602: operands[2] = force_reg (SImode, operands[2]);
603: label = gen_label_rtx ();
604: emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
605: operands[3], label));
606: }
607: else
608: operands[2] = force_reg (SImode, operands[2]);
609:
610: emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
611: operands[3]));
612: if (label)
613: emit_label (label);
614:
615: DONE;
616: }")
617:
618: (define_insn "andsi3"
619: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
620: (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
621: (match_operand:SI 2 "and_operand" "?r,L,K,J")))
622: (clobber (match_scratch:CC 3 "=X,X,x,x"))]
623: ""
624: "@
625: and %0,%1,%2
626: rlinm %0,%1,0,%m2,%M2
627: andil. %0,%1,%b2
628: andiu. %0,%1,%u2")
629:
630: (define_insn ""
631: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
632: (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
633: (match_operand:SI 2 "and_operand" "r,K,J,L"))
634: (const_int 0)))
635: (clobber (match_scratch:SI 3 "=r,r,r,r"))]
636: ""
637: "@
638: and. %3,%1,%2
639: andil. %3,%1,%b2
640: andiu. %3,%1,%u2
641: rlinm. %3,%1,0,%m2,%M2"
642: [(set_attr "type" "compare,compare,compare,delayed_compare")])
643:
644: (define_insn ""
645: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
646: (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
647: (match_operand:SI 2 "and_operand" "r,K,J,L"))
648: (const_int 0)))
649: (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
650: (and:SI (match_dup 1) (match_dup 2)))]
651: ""
652: "@
653: and. %0,%1,%2
654: andil. %0,%1,%b2
655: andiu. %0,%1,%u2
656: rlinm. %0,%1,0,%m2,%M2"
657: [(set_attr "type" "compare,compare,compare,delayed_compare")])
658:
659: (define_insn ""
660: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r")
661: (ior:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r")
662: (match_operand:SI 2 "logical_operand" "r,K,J")))]
663: ""
664: "@
665: or %0,%1,%2
666: oril %0,%1,%b2
667: oriu %0,%1,%u2")
668:
669: (define_insn ""
670: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
671: (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r")
672: (match_operand:SI 2 "gen_reg_operand" "r"))
673: (const_int 0)))
674: (clobber (match_scratch:SI 3 "=r"))]
675: ""
676: "or. %3,%1,%2"
677: [(set_attr "type" "compare")])
678:
679: (define_insn ""
680: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
681: (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r")
682: (match_operand:SI 2 "gen_reg_operand" "r"))
683: (const_int 0)))
684: (set (match_operand:SI 0 "gen_reg_operand" "=r")
685: (ior:SI (match_dup 1) (match_dup 2)))]
686: ""
687: "or. %0,%1,%2"
688: [(set_attr "type" "compare")])
689:
690: (define_expand "iorsi3"
691: [(set (match_operand:SI 0 "gen_reg_operand" "")
692: (ior:SI (match_operand:SI 1 "gen_reg_operand" "")
693: (match_operand:SI 2 "reg_or_cint_operand" "")))]
694: ""
695: "
696: {
697: if (GET_CODE (operands[2]) == CONST_INT
698: && ! logical_operand (operands[2], SImode))
699: {
700: emit_insn (gen_iorsi3 (operands[0], operands[1],
701: gen_rtx (CONST_INT, VOIDmode,
702: INTVAL (operands[2]) & 0xffff0000)));
703: operands[1] = operands[0];
704: operands[2] = gen_rtx (CONST_INT, VOIDmode,
705: INTVAL (operands[2]) & 0xffff);
706: }
707: }")
708:
709: (define_insn ""
710: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r")
711: (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r")
712: (match_operand:SI 2 "logical_operand" "r,K,J")))]
713: ""
714: "@
715: xor %0,%1,%2
716: xoril %0,%1,%b2
717: xoriu %0,%1,%u2")
718:
719: (define_insn ""
720: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
721: (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r")
722: (match_operand:SI 2 "gen_reg_operand" "r"))
723: (const_int 0)))
724: (clobber (match_scratch:SI 3 "=r"))]
725: ""
726: "xor. %3,%1,%2"
727: [(set_attr "type" "compare")])
728:
729: (define_insn ""
730: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
731: (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r")
732: (match_operand:SI 2 "gen_reg_operand" "r"))
733: (const_int 0)))
734: (set (match_operand:SI 0 "gen_reg_operand" "=r")
735: (xor:SI (match_dup 1) (match_dup 2)))]
736: ""
737: "xor. %0,%1,%2"
738: [(set_attr "type" "compare")])
739:
740: (define_expand "xorsi3"
741: [(set (match_operand:SI 0 "gen_reg_operand" "")
742: (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
743: (match_operand:SI 2 "reg_or_cint_operand" "")))]
744: ""
745: "
746: {
747: if (GET_CODE (operands[2]) == CONST_INT
748: && ! logical_operand (operands[2], SImode))
749: {
750: emit_insn (gen_xorsi3 (operands[0], operands[1],
751: gen_rtx (CONST_INT, VOIDmode,
752: INTVAL (operands[2]) & 0xffff0000)));
753: operands[1] = operands[0];
754: operands[2] = gen_rtx (CONST_INT, VOIDmode,
755: INTVAL (operands[2]) & 0xffff);
756: }
757: }")
758:
759: (define_insn ""
760: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
761: (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
762: (match_operand:SI 2 "gen_reg_operand" "r"))))]
763: ""
764: "eqv %0,%1,%2")
765:
766: (define_insn ""
767: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
768: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
769: (match_operand:SI 2 "gen_reg_operand" "r")))
770: (const_int 0)))
771: (clobber (match_scratch:SI 3 "=r"))]
772: ""
773: "eqv. %3,%1,%2"
774: [(set_attr "type" "compare")])
775:
776: (define_insn ""
777: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
778: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
779: (match_operand:SI 2 "gen_reg_operand" "r")))
780: (const_int 0)))
781: (set (match_operand:SI 0 "gen_reg_operand" "=r")
782: (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
783: ""
784: "eqv. %0,%1,%2"
785: [(set_attr "type" "compare")])
786:
787: (define_insn ""
788: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
789: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
790: (match_operand:SI 2 "gen_reg_operand" "r")))]
791: ""
792: "andc %0,%2,%1")
793:
794: (define_insn ""
795: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
796: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
797: (match_operand:SI 2 "gen_reg_operand" "r"))
798: (const_int 0)))
799: (clobber (match_scratch:SI 3 "=r"))]
800: ""
801: "andc. %3,%2,%1"
802: [(set_attr "type" "compare")])
803:
804: (define_insn ""
805: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
806: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
807: (match_operand:SI 2 "gen_reg_operand" "r"))
808: (const_int 0)))
809: (set (match_operand:SI 0 "gen_reg_operand" "=r")
810: (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
811: ""
812: "andc. %0,%2,%1"
813: [(set_attr "type" "compare")])
814:
815: (define_insn ""
816: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
817: (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
818: (match_operand:SI 2 "gen_reg_operand" "r")))]
819: ""
820: "orc %0,%2,%1")
821:
822: (define_insn ""
823: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
824: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
825: (match_operand:SI 2 "gen_reg_operand" "r"))
826: (const_int 0)))
827: (clobber (match_scratch:SI 3 "=r"))]
828: ""
829: "orc. %3,%2,%1"
830: [(set_attr "type" "compare")])
831:
832: (define_insn ""
833: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
834: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
835: (match_operand:SI 2 "gen_reg_operand" "r"))
836: (const_int 0)))
837: (set (match_operand:SI 0 "gen_reg_operand" "=r")
838: (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
839: ""
840: "orc. %0,%2,%1"
841: [(set_attr "type" "compare")])
842:
843: (define_insn ""
844: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
845: (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
846: (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))]
847: ""
848: "nand %0,%1,%2")
849:
850: (define_insn ""
851: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
852: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
853: (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
854: (const_int 0)))
855: (clobber (match_scratch:SI 3 "=r"))]
856: ""
857: "nand. %3,%1,%2"
858: [(set_attr "type" "compare")])
859:
860: (define_insn ""
861: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
862: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
863: (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
864: (const_int 0)))
865: (set (match_operand:SI 0 "gen_reg_operand" "=r")
866: (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
867: ""
868: "nand. %0,%1,%2"
869: [(set_attr "type" "compare")])
870:
871: (define_insn ""
872: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
873: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
874: (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))]
875: ""
876: "nor %0,%1,%2")
877:
878: (define_insn ""
879: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
880: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
881: (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
882: (const_int 0)))
883: (clobber (match_scratch:SI 3 "=r"))]
884: ""
885: "nor. %3,%1,%2"
886: [(set_attr "type" "compare")])
887:
888: (define_insn ""
889: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
890: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
891: (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
892: (const_int 0)))
893: (set (match_operand:SI 0 "gen_reg_operand" "=r")
894: (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
895: ""
896: "nor. %0,%1,%2"
897: [(set_attr "type" "compare")])
898:
899: ;; maskir insn. We need four forms because things might be in arbitrary
900: ;; orders. Don't define forms that only set CR fields because these
901: ;; would modify an input register.
902:
903: (define_insn ""
904: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
905: (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
906: (match_operand:SI 2 "gen_reg_operand" "0"))
907: (and:SI (match_dup 1)
908: (match_operand:SI 3 "gen_reg_operand" "r"))))]
909: ""
910: "maskir %0,%3,%1")
911:
912: (define_insn ""
913: [(set (match_operand:SI 0 "register_operand" "=r")
914: (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
915: (match_operand:SI 2 "gen_reg_operand" "0"))
916: (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
917: (match_dup 1))))]
918: ""
919: "maskir %0,%3,%1")
920:
921: (define_insn ""
922: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
923: (ior:SI (and:SI (match_dup 1)
924: (match_operand:SI 3 "gen_reg_operand" "r"))
925: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
926: (match_operand:SI 2 "gen_reg_operand" "0"))))]
927: ""
928: "maskir %0,%3,%1")
929:
930: (define_insn ""
931: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
932: (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
933: (match_dup 1))
934: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
935: (match_operand:SI 2 "gen_reg_operand" "0"))))]
936: ""
937: "maskir %0,%3,%1")
938:
939: (define_insn ""
940: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
941: (compare:CC
942: (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
943: (match_operand:SI 2 "gen_reg_operand" "0"))
944: (and:SI (match_dup 1)
945: (match_operand:SI 3 "gen_reg_operand" "r")))
946: (const_int 0)))
947: (set (match_operand:SI 0 "gen_reg_operand" "=r")
948: (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
949: (and:SI (match_dup 1) (match_dup 3))))]
950: ""
951: "maskir. %0,%3,%1"
952: [(set_attr "type" "compare")])
953:
954: (define_insn ""
955: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
956: (compare:CC
957: (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
958: (match_operand:SI 2 "gen_reg_operand" "0"))
959: (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
960: (match_dup 1)))
961: (const_int 0)))
962: (set (match_operand:SI 0 "register_operand" "=r")
963: (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
964: (and:SI (match_dup 3) (match_dup 1))))]
965: ""
966: "maskir. %0,%3,%1"
967: [(set_attr "type" "compare")])
968:
969: (define_insn ""
970: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
971: (compare:CC
972: (ior:SI (and:SI (match_dup 1)
973: (match_operand:SI 3 "gen_reg_operand" "r"))
974: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
975: (match_operand:SI 2 "gen_reg_operand" "0")))
976: (const_int 0)))
977: (set (match_operand:SI 0 "gen_reg_operand" "=r")
978: (ior:SI (and:SI (match_dup 1) (match_dup 3))
979: (and:SI (not:SI (match_dup 1)) (match_dup 2))))]
980: ""
981: "maskir. %0,%3,%1"
982: [(set_attr "type" "compare")])
983:
984: (define_insn ""
985: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
986: (compare:CC
987: (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
988: (match_dup 1))
989: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
990: (match_operand:SI 2 "gen_reg_operand" "0")))
991: (const_int 0)))
992: (set (match_operand:SI 0 "gen_reg_operand" "=r")
993: (ior:SI (and:SI (match_dup 3) (match_dup 1))
994: (and:SI (not:SI (match_dup 1)) (match_dup 2))))]
995: ""
996: "maskir. %0,%3,%1"
997: [(set_attr "type" "compare")])
998:
999: ;; Rotate and shift insns, in all their variants. These support shifts,
1000: ;; field inserts and extracts, and various combinations thereof.
1001: (define_insn "insv"
1002: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1003: (match_operand:SI 1 "const_int_operand" "i")
1004: (match_operand:SI 2 "const_int_operand" "i"))
1005: (match_operand:SI 3 "gen_reg_operand" "r"))]
1006: ""
1007: "*
1008: {
1009: int start = INTVAL (operands[2]) & 31;
1010: int size = INTVAL (operands[1]) & 31;
1011:
1012: operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
1013: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1014: return \"rlimi %0,%3,%4,%h2,%h1\";
1015: }")
1016:
1017: (define_insn "extzv"
1018: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1019: (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
1020: (match_operand:SI 2 "const_int_operand" "i")
1021: (match_operand:SI 3 "const_int_operand" "i")))]
1022: ""
1023: "*
1024: {
1025: int start = INTVAL (operands[3]) & 31;
1026: int size = INTVAL (operands[2]) & 31;
1027:
1028: if (start + size >= 32)
1029: operands[3] = const0_rtx;
1030: else
1031: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1032: return \"rlinm %0,%1,%3,%s2,31\";
1033: }")
1034:
1035: (define_insn ""
1036: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1037: (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
1038: (match_operand:SI 2 "const_int_operand" "i")
1039: (match_operand:SI 3 "const_int_operand" "i"))
1040: (const_int 0)))
1041: (clobber (match_scratch:SI 4 "=r"))]
1042: ""
1043: "*
1044: {
1045: int start = INTVAL (operands[3]) & 31;
1046: int size = INTVAL (operands[2]) & 31;
1047:
1048: if (start + size >= 32)
1049: operands[3] = const0_rtx;
1050: else
1051: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1052: return \"rlinm. %4,%1,%3,%s2,31\";
1053: }"
1054: [(set_attr "type" "compare")])
1055:
1056: (define_insn ""
1057: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1058: (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
1059: (match_operand:SI 2 "const_int_operand" "i")
1060: (match_operand:SI 3 "const_int_operand" "i"))
1061: (const_int 0)))
1062: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1063: (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
1064: ""
1065: "*
1066: {
1067: int start = INTVAL (operands[3]) & 31;
1068: int size = INTVAL (operands[2]) & 31;
1069:
1070: if (start + size >= 32)
1071: operands[3] = const0_rtx;
1072: else
1073: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1074: return \"rlinm. %0,%1,%3,%s2,31\";
1075: }"
1076: [(set_attr "type" "delayed_compare")])
1077:
1078: (define_insn "rotlsi3"
1079: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1080: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1081: (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
1082: ""
1083: "rl%I2nm %0,%1,%h2,0,31")
1084:
1085: (define_insn ""
1086: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1087: (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1088: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1089: (const_int 0)))
1090: (clobber (match_scratch:SI 3 "=r"))]
1091: ""
1092: "rl%I2nm. %3,%1,%h2,0,31"
1093: [(set_attr "type" "delayed_compare")])
1094:
1095: (define_insn ""
1096: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1097: (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1098: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1099: (const_int 0)))
1100: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1101: (rotate:SI (match_dup 1) (match_dup 2)))]
1102: ""
1103: "rl%I2nm. %0,%1,%h2,0,31"
1104: [(set_attr "type" "delayed_compare")])
1105:
1106: (define_insn ""
1107: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1108: (and:SI (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1109: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1110: (match_operand:SI 3 "mask_operand" "L")))]
1111: ""
1112: "rl%I2nm %0,%1,%h2,%m3,%M3")
1113:
1114: (define_insn ""
1115: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1116: (compare:CC (and:SI
1117: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1118: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1119: (match_operand:SI 3 "mask_operand" "L"))
1120: (const_int 0)))
1121: (clobber (match_scratch:SI 4 "=r"))]
1122: ""
1123: "rl%I2nm. %4,%1,%h2,%m3,%M3"
1124: [(set_attr "type" "delayed_compare")])
1125:
1126: (define_insn ""
1127: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1128: (compare:CC (and:SI
1129: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1130: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1131: (match_operand:SI 3 "mask_operand" "L"))
1132: (const_int 0)))
1133: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1134: (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1135: ""
1136: "rl%I2nm. %0,%1,%h2,%m3,%M3"
1137: [(set_attr "type" "delayed_compare")])
1138:
1139: (define_insn ""
1140: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1141: (zero_extend:SI
1142: (subreg:QI
1143: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1144: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1145: ""
1146: "rl%I2nm %0,%1,%h2,24,31")
1147:
1148: (define_insn ""
1149: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1150: (compare:CC (zero_extend:SI
1151: (subreg:QI
1152: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1153: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1154: (const_int 0)))
1155: (clobber (match_scratch:SI 3 "=r"))]
1156: ""
1157: "rl%I2nm. %3,%1,%h2,24,31"
1158: [(set_attr "type" "delayed_compare")])
1159:
1160: (define_insn ""
1161: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1162: (compare:CC (zero_extend:SI
1163: (subreg:QI
1164: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1165: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1166: (const_int 0)))
1167: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1168: (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1169: ""
1170: "rl%I2nm. %0,%1,%h2,24,31"
1171: [(set_attr "type" "delayed_compare")])
1172:
1173: (define_insn ""
1174: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1175: (zero_extend:SI
1176: (subreg:HI
1177: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1178: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1179: ""
1180: "rl%I2nm %0,%1,%h2,16,31")
1181:
1182: (define_insn ""
1183: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1184: (compare:CC (zero_extend:SI
1185: (subreg:HI
1186: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1187: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1188: (const_int 0)))
1189: (clobber (match_scratch:SI 3 "=r"))]
1190: ""
1191: "rl%I2nm. %3,%1,%h2,16,31"
1192: [(set_attr "type" "delayed_compare")])
1193:
1194: (define_insn ""
1195: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1196: (compare:CC (zero_extend:SI
1197: (subreg:HI
1198: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1199: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1200: (const_int 0)))
1201: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1202: (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1203: ""
1204: "rl%I2nm. %0,%1,%h2,16,31"
1205: [(set_attr "type" "delayed_compare")])
1206:
1207: ;; Note that we use "sle." instead of "sl." so that we can set
1208: ;; SHIFT_COUNT_TRUNCATED.
1209:
1210: (define_insn "ashlsi3"
1211: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1212: (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1213: (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1214: (clobber (match_scratch:SI 3 "=q,X"))]
1215: ""
1216: "@
1217: sle %0,%1,%2
1218: sli %0,%1,%h2")
1219:
1220: (define_insn ""
1221: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1222: (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1223: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1224: (const_int 0)))
1225: (clobber (match_scratch:SI 3 "=r,r"))
1226: (clobber (match_scratch:SI 4 "=q,X"))]
1227: ""
1228: "@
1229: sle. %3,%1,%2
1230: sli. %3,%1,%h2"
1231: [(set_attr "type" "delayed_compare")])
1232:
1233: (define_insn ""
1234: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1235: (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1236: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1237: (const_int 0)))
1238: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1239: (ashift:SI (match_dup 1) (match_dup 2)))
1240: (clobber (match_scratch:SI 4 "=q,X"))]
1241: ""
1242: "@
1243: sle. %0,%1,%2
1244: sli. %0,%1,%h2"
1245: [(set_attr "type" "delayed_compare")])
1246:
1247: (define_insn ""
1248: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1249: (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
1250: (match_operand:SI 2 "const_int_operand" "i"))
1251: (match_operand:SI 3 "mask_operand" "L")))]
1252: "includes_lshift_p (operands[2], operands[3])"
1253: "rlinm %0,%h1,%h2,%m3,%M3")
1254:
1255: (define_insn ""
1256: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1257: (compare:CC
1258: (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
1259: (match_operand:SI 2 "const_int_operand" "i"))
1260: (match_operand:SI 3 "mask_operand" "L"))
1261: (const_int 0)))
1262: (clobber (match_scratch:SI 4 "=r"))]
1263: "includes_lshift_p (operands[2], operands[3])"
1264: "rlinm. %4,%h1,%h2,%m3,%M3"
1265: [(set_attr "type" "delayed_compare")])
1266:
1267: (define_insn ""
1268: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1269: (compare:CC
1270: (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
1271: (match_operand:SI 2 "const_int_operand" "i"))
1272: (match_operand:SI 3 "mask_operand" "L"))
1273: (const_int 0)))
1274: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1275: (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1276: "includes_lshift_p (operands[2], operands[3])"
1277: "rlinm. %0,%h1,%h2,%m3,%M3"
1278: [(set_attr "type" "delayed_compare")])
1279:
1280: (define_insn "lshrsi3"
1281: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1282: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1283: (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1284: (clobber (match_scratch:SI 3 "=q,X"))]
1285: ""
1286: "@
1287: sre %0,%1,%2
1288: sri %0,%1,%h2")
1289:
1290: (define_insn ""
1291: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1292: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1293: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1294: (const_int 0)))
1295: (clobber (match_scratch:SI 3 "=r,r"))
1296: (clobber (match_scratch:SI 4 "=q,X"))]
1297: ""
1298: "@
1299: sre. %3,%1,%2
1300: sri. %3,%1,%h2"
1301: [(set_attr "type" "delayed_compare")])
1302:
1303: (define_insn ""
1304: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1305: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1306: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1307: (const_int 0)))
1308: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1309: (lshiftrt:SI (match_dup 1) (match_dup 2)))
1310: (clobber (match_scratch:SI 4 "=q,X"))]
1311: ""
1312: "@
1313: sre. %0,%1,%2
1314: sri. %0,%1,%h2"
1315: [(set_attr "type" "delayed_compare")])
1316:
1317: (define_insn ""
1318: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1319: (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1320: (match_operand:SI 2 "const_int_operand" "i"))
1321: (match_operand:SI 3 "mask_operand" "L")))]
1322: "includes_rshift_p (operands[2], operands[3])"
1323: "rlinm %0,%1,%s2,%m3,%M3")
1324:
1325: (define_insn ""
1326: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1327: (compare:CC
1328: (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1329: (match_operand:SI 2 "const_int_operand" "i"))
1330: (match_operand:SI 3 "mask_operand" "L"))
1331: (const_int 0)))
1332: (clobber (match_scratch:SI 4 "=r"))]
1333: "includes_rshift_p (operands[2], operands[3])"
1334: "rlinm. %4,%1,%s2,%m3,%M3"
1335: [(set_attr "type" "delayed_compare")])
1336:
1337: (define_insn ""
1338: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1339: (compare:CC
1340: (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1341: (match_operand:SI 2 "const_int_operand" "i"))
1342: (match_operand:SI 3 "mask_operand" "L"))
1343: (const_int 0)))
1344: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1345: (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1346: "includes_rshift_p (operands[2], operands[3])"
1347: "rlinm. %0,%1,%s2,%m3,%M3"
1348: [(set_attr "type" "delayed_compare")])
1349:
1350: (define_insn ""
1351: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1352: (zero_extend:SI
1353: (subreg:QI
1354: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1355: (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1356: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1357: "rlinm %0,%1,%s2,24,31")
1358:
1359: (define_insn ""
1360: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1361: (compare:CC
1362: (zero_extend:SI
1363: (subreg:QI
1364: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1365: (match_operand:SI 2 "const_int_operand" "i")) 0))
1366: (const_int 0)))
1367: (clobber (match_scratch:SI 3 "=r"))]
1368: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1369: "rlinm. %3,%1,%s2,24,31"
1370: [(set_attr "type" "delayed_compare")])
1371:
1372: (define_insn ""
1373: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1374: (compare:CC
1375: (zero_extend:SI
1376: (subreg:QI
1377: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1378: (match_operand:SI 2 "const_int_operand" "i")) 0))
1379: (const_int 0)))
1380: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1381: (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1382: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1383: "rlinm. %0,%1,%s2,24,31"
1384: [(set_attr "type" "delayed_compare")])
1385:
1386: (define_insn ""
1387: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1388: (zero_extend:SI
1389: (subreg:HI
1390: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1391: (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1392: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1393: "rlinm %0,%1,%s2,16,31")
1394:
1395: (define_insn ""
1396: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1397: (compare:CC
1398: (zero_extend:SI
1399: (subreg:HI
1400: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1401: (match_operand:SI 2 "const_int_operand" "i")) 0))
1402: (const_int 0)))
1403: (clobber (match_scratch:SI 3 "=r"))]
1404: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1405: "rlinm. %3,%1,%s2,16,31"
1406: [(set_attr "type" "delayed_compare")])
1407:
1408: (define_insn ""
1409: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1410: (compare:CC
1411: (zero_extend:SI
1412: (subreg:HI
1413: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1414: (match_operand:SI 2 "const_int_operand" "i")) 0))
1415: (const_int 0)))
1416: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1417: (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1418: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1419: "rlinm. %0,%1,%s2,16,31"
1420: [(set_attr "type" "delayed_compare")])
1421:
1422: (define_insn ""
1423: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1424: (const_int 1)
1425: (match_operand:SI 1 "gen_reg_operand" "r"))
1426: (ashiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r")
1427: (const_int 31)))]
1428: ""
1429: "rrib %0,%1,%2")
1430:
1431: (define_insn ""
1432: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1433: (const_int 1)
1434: (match_operand:SI 1 "gen_reg_operand" "r"))
1435: (lshiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r")
1436: (const_int 31)))]
1437: ""
1438: "rrib %0,%1,%2")
1439:
1440: (define_insn ""
1441: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1442: (const_int 1)
1443: (match_operand:SI 1 "gen_reg_operand" "r"))
1444: (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r")
1445: (const_int 1)
1446: (const_int 0)))]
1447: ""
1448: "rrib %0,%1,%2")
1449:
1450: (define_insn "ashrsi3"
1451: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1452: (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1453: (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1454: (clobber (match_scratch:SI 3 "=q,X"))]
1455: ""
1456: "@
1457: srea %0,%1,%2
1458: srai %0,%1,%h2")
1459:
1460: (define_insn ""
1461: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1462: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1463: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1464: (const_int 0)))
1465: (clobber (match_scratch:SI 3 "=r,r"))
1466: (clobber (match_scratch:SI 4 "=q,X"))]
1467: ""
1468: "@
1469: srea. %3,%1,%2
1470: srai. %3,%1,%h2"
1471: [(set_attr "type" "delayed_compare")])
1472:
1473: (define_insn ""
1474: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1475: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1476: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1477: (const_int 0)))
1478: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1479: (ashiftrt:SI (match_dup 1) (match_dup 2)))
1480: (clobber (match_scratch:SI 4 "=q,X"))]
1481: ""
1482: "@
1483: srea. %0,%1,%2
1484: srai. %0,%1,%h2"
1485: [(set_attr "type" "delayed_compare")])
1486:
1487: (define_expand "extendqisi2"
1488: [(parallel [(set (match_dup 2)
1489: (ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
1490: (const_int 24)))
1491: (clobber (scratch:SI))])
1492: (parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
1493: (ashiftrt:SI (match_dup 2)
1494: (const_int 24)))
1495: (clobber (scratch:SI))])]
1496: ""
1497: "
1498: { operands[1] = gen_lowpart (SImode, operands[1]);
1499: operands[2] = gen_reg_rtx (SImode); }")
1500:
1501: (define_expand "extendqihi2"
1502: [(parallel [(set (match_dup 2)
1503: (ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
1504: (const_int 24)))
1505: (clobber (scratch:SI))])
1506: (parallel [(set (match_operand:HI 0 "gen_reg_operand" "")
1507: (ashiftrt:SI (match_dup 2)
1508: (const_int 24)))
1509: (clobber (scratch:SI))])]
1510: ""
1511: "
1512: { operands[0] = gen_lowpart (SImode, operands[0]);
1513: operands[1] = gen_lowpart (SImode, operands[1]);
1514: operands[2] = gen_reg_rtx (SImode); }")
1515:
1516: ;; Floating-point insns, excluding normal data motion.
1517: ;;
1518: ;; We pretend that we have both SFmode and DFmode insns, while, in fact,
1519: ;; all fp insns are actually done in double. The only conversions we will
1520: ;; do will be when storing to memory. In that case, we will use the "frsp"
1521: ;; instruction before storing.
1522: ;;
1523: ;; Note that when we store into a single-precision memory location, we need to
1524: ;; use the frsp insn first. If the register being stored isn't dead, we
1525: ;; need a scratch register for the frsp. But this is difficult when the store
1526: ;; is done by reload. It is not incorrect to do the frsp on the register in
1527: ;; this case, we just lose precision that we would have otherwise gotten but
1528: ;; is not guaranteed. Perhaps this should be tightened up at some point.
1529:
1530: (define_insn "extendsfdf2"
1531: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1532: (float_extend:DF (match_operand:SF 1 "gen_reg_operand" "f")))]
1533: ""
1534: "*
1535: {
1536: if (REGNO (operands[0]) == REGNO (operands[1]))
1537: return \"\";
1538: else
1539: return \"fmr %0,%1\";
1540: }"
1541: [(set_attr "type" "fp")])
1542:
1543: (define_insn "truncdfsf2"
1544: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1545: (float_truncate:SF (match_operand:DF 1 "gen_reg_operand" "f")))]
1546: ""
1547: "*
1548: {
1549: if (REGNO (operands[0]) == REGNO (operands[1]))
1550: return \"\";
1551: else
1552: return \"fmr %0,%1\";
1553: }"
1554: [(set_attr "type" "fp")])
1555:
1556: (define_insn "negsf2"
1557: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1558: (neg:SF (match_operand:SF 1 "gen_reg_operand" "f")))]
1559: ""
1560: "fneg %0,%1"
1561: [(set_attr "type" "fp")])
1562:
1563: (define_insn "abssf2"
1564: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1565: (abs:SF (match_operand:SF 1 "gen_reg_operand" "f")))]
1566: ""
1567: "fabs %0,%1"
1568: [(set_attr "type" "fp")])
1569:
1570: (define_insn ""
1571: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1572: (neg:SF (abs:SF (match_operand:SF 1 "gen_reg_operand" "f"))))]
1573: ""
1574: "fnabs %0,%1"
1575: [(set_attr "type" "fp")])
1576:
1577: (define_insn "addsf3"
1578: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1579: (plus:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1580: (match_operand:SF 2 "gen_reg_operand" "f")))]
1581: ""
1582: "fa %0,%1,%2"
1583: [(set_attr "type" "fp")])
1584:
1585: (define_insn "subsf3"
1586: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1587: (minus:SF (match_operand:SF 1 "gen_reg_operand" "f")
1588: (match_operand:SF 2 "gen_reg_operand" "f")))]
1589: ""
1590: "fs %0,%1,%2"
1591: [(set_attr "type" "fp")])
1592:
1593: (define_insn "mulsf3"
1594: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1595: (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1596: (match_operand:SF 2 "gen_reg_operand" "f")))]
1597: ""
1598: "fm %0,%1,%2"
1599: [(set_attr "type" "fp")])
1600:
1601: (define_insn "divsf3"
1602: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1603: (div:SF (match_operand:SF 1 "gen_reg_operand" "f")
1604: (match_operand:SF 2 "gen_reg_operand" "f")))]
1605: ""
1606: "fd %0,%1,%2"
1607: [(set_attr "type" "fp")])
1608:
1609: (define_insn ""
1610: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1611: (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1612: (match_operand:SF 2 "gen_reg_operand" "f"))
1613: (match_operand:SF 3 "gen_reg_operand" "f")))]
1614: ""
1615: "fma %0,%1,%2,%3"
1616: [(set_attr "type" "fp")])
1617:
1618: (define_insn ""
1619: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1620: (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1621: (match_operand:SF 2 "gen_reg_operand" "f"))
1622: (match_operand:SF 3 "gen_reg_operand" "f")))]
1623: ""
1624: "fms %0,%1,%2,%3"
1625: [(set_attr "type" "fp")])
1626:
1627: (define_insn ""
1628: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1629: (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1630: (match_operand:SF 2 "gen_reg_operand" "f"))
1631: (match_operand:SF 3 "gen_reg_operand" "f"))))]
1632: ""
1633: "fnma %0,%1,%2,%3"
1634: [(set_attr "type" "fp")])
1635:
1636: (define_insn ""
1637: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1638: (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1639: (match_operand:SF 2 "gen_reg_operand" "f"))
1640: (match_operand:SF 3 "gen_reg_operand" "f"))))]
1641: ""
1642: "fnms %0,%1,%2,%3"
1643: [(set_attr "type" "fp")])
1644:
1645: (define_insn "negdf2"
1646: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1647: (neg:DF (match_operand:DF 1 "gen_reg_operand" "f")))]
1648: ""
1649: "fneg %0,%1"
1650: [(set_attr "type" "fp")])
1651:
1652: (define_insn "absdf2"
1653: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1654: (abs:DF (match_operand:DF 1 "gen_reg_operand" "f")))]
1655: ""
1656: "fabs %0,%1"
1657: [(set_attr "type" "fp")])
1658:
1659: (define_insn ""
1660: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1661: (neg:DF (abs:DF (match_operand:DF 1 "gen_reg_operand" "f"))))]
1662: ""
1663: "fnabs %0,%1"
1664: [(set_attr "type" "fp")])
1665:
1666: (define_insn "adddf3"
1667: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1668: (plus:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1669: (match_operand:DF 2 "gen_reg_operand" "f")))]
1670: ""
1671: "fa %0,%1,%2"
1672: [(set_attr "type" "fp")])
1673:
1674: (define_insn "subdf3"
1675: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1676: (minus:DF (match_operand:DF 1 "gen_reg_operand" "f")
1677: (match_operand:DF 2 "gen_reg_operand" "f")))]
1678: ""
1679: "fs %0,%1,%2"
1680: [(set_attr "type" "fp")])
1681:
1682: (define_insn "muldf3"
1683: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1684: (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1685: (match_operand:DF 2 "gen_reg_operand" "f")))]
1686: ""
1687: "fm %0,%1,%2"
1688: [(set_attr "type" "fp")])
1689:
1690: (define_insn "divdf3"
1691: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1692: (div:DF (match_operand:DF 1 "gen_reg_operand" "f")
1693: (match_operand:DF 2 "gen_reg_operand" "f")))]
1694: ""
1695: "fd %0,%1,%2"
1696: [(set_attr "type" "fp")])
1697:
1698: (define_insn ""
1699: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1700: (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1701: (match_operand:DF 2 "gen_reg_operand" "f"))
1702: (match_operand:DF 3 "gen_reg_operand" "f")))]
1703: ""
1704: "fma %0,%1,%2,%3"
1705: [(set_attr "type" "fp")])
1706:
1707: (define_insn ""
1708: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1709: (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1710: (match_operand:DF 2 "gen_reg_operand" "f"))
1711: (match_operand:DF 3 "gen_reg_operand" "f")))]
1712: ""
1713: "fms %0,%1,%2,%3"
1714: [(set_attr "type" "fp")])
1715:
1716: (define_insn ""
1717: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1718: (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1719: (match_operand:DF 2 "gen_reg_operand" "f"))
1720: (match_operand:DF 3 "gen_reg_operand" "f"))))]
1721: ""
1722: "fnma %0,%1,%2,%3"
1723: [(set_attr "type" "fp")])
1724:
1725: (define_insn ""
1726: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1727: (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1728: (match_operand:DF 2 "gen_reg_operand" "f"))
1729: (match_operand:DF 3 "gen_reg_operand" "f"))))]
1730: ""
1731: "fnms %0,%1,%2,%3"
1732: [(set_attr "type" "fp")])
1733:
1734: ;; Conversions to and from floating-point.
1735: (define_expand "floatsidf2"
1736: [(set (match_dup 2)
1737: (plus:DI (zero_extend:DI
1738: (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
1739: (match_dup 3)))
1740: (match_dup 4)))
1741: (set (match_operand:DF 0 "gen_reg_operand" "")
1742: (minus:DF (subreg:DF (match_dup 2) 0)
1743: (match_dup 5)))]
1744: ""
1745: "
1746: {
1747: #if HOST_BITS_PER_INT != BITS_PER_WORD
1748: /* Maybe someone can figure out how to do this in that case. I don't
1749: want to right now. */
1750: abort ();
1751: #endif
1752:
1753: operands[2] = gen_reg_rtx (DImode);
1754: operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000);
1755: operands[4] = immed_double_const (0, 0x43300000, DImode);
1756: operands[5] = force_reg (DFmode, immed_double_const (0x43300000,
1757: 0x80000000, DFmode));
1758: }")
1759:
1760: (define_expand "floatunssidf2"
1761: [(set (match_dup 2)
1762: (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
1763: (match_dup 3)))
1764: (set (match_operand:DF 0 "gen_reg_operand" "")
1765: (minus:DF (subreg:DF (match_dup 2) 0)
1766: (match_dup 4)))]
1767: ""
1768: "
1769: {
1770: #if HOST_BITS_PER_INT != BITS_PER_WORD
1771: /* Maybe someone can figure out how to do this in that case. I don't
1772: want to right now. */
1773: abort ();
1774: #endif
1775:
1776: operands[2] = gen_reg_rtx (DImode);
1777: operands[3] = immed_double_const (0, 0x43300000, DImode);
1778: operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode));
1779: }")
1780:
1781: ;; For the above two cases, we always split.
1782: (define_split
1783: [(set (match_operand:DI 0 "gen_reg_operand" "")
1784: (plus:DI (zero_extend:DI
1785: (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
1786: (match_operand:SI 2 "logical_operand" "")))
1787: (match_operand:DI 3 "immediate_operand" "")))]
1788: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1789: && GET_CODE (operands[3]) == CONST_DOUBLE
1790: && CONST_DOUBLE_LOW (operands[3]) == 0"
1791: [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2)))
1792: (set (match_dup 4) (match_dup 5))]
1793: "
1794: { operands[4] = operand_subword (operands[0], 0, 0, DImode);
1795: operands[5] = operand_subword (operands[3], 0, 0, DImode);
1796: operands[6] = operand_subword (operands[0], 1, 0, DImode);
1797: }")
1798:
1799: (define_insn ""
1800: [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1801: (plus:DI (zero_extend:DI
1802: (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
1803: (match_operand:SI 2 "logical_operand" "rKJ")))
1804: (match_operand:DI 3 "immediate_operand" "n")))]
1805: "HOST_BITS_PER_INT == BITS_PER_WORD
1806: && GET_CODE (operands[3]) == CONST_DOUBLE
1807: && CONST_DOUBLE_LOW (operands[3]) == 0"
1808: "#")
1809:
1810: (define_split
1811: [(set (match_operand:DI 0 "gen_reg_operand" "=")
1812: (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
1813: (match_operand:DI 2 "immediate_operand" "")))]
1814: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1815: && GET_CODE (operands[2]) == CONST_DOUBLE
1816: && CONST_DOUBLE_LOW (operands[2]) == 0"
1817: [(set (match_dup 3) (match_dup 4))
1818: (set (match_dup 5) (match_dup 1))]
1819: "
1820: { operands[3] = operand_subword (operands[0], 0, 0, DImode);
1821: operands[4] = operand_subword (operands[2], 0, 0, DImode);
1822: operands[5] = operand_subword (operands[0], 1, 0, DImode);
1823:
1824: if (rtx_equal_p (operands[1], operands[5]))
1825: {
1826: emit_move_insn (operands[3], operands[4]);
1827: DONE;
1828: }
1829: }")
1830:
1831: (define_insn ""
1832: [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1833: (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
1834: (match_operand:DI 2 "immediate_operand" "n")))]
1835: "HOST_BITS_PER_INT == BITS_PER_WORD
1836: && GET_CODE (operands[2]) == CONST_DOUBLE
1837: && CONST_DOUBLE_LOW (operands[2]) == 0"
1838: "#")
1839:
1840: (define_expand "fix_truncdfsi2"
1841: [(set (match_operand:SI 0 "gen_reg_operand" "")
1842: (fix:DF (match_operand:DF 1 "gen_reg_operand" "")))]
1843: ""
1844: "
1845: {
1846: emit_insn (gen_trunc_call (operands[0], operands[1],
1847: gen_rtx (SYMBOL_REF, Pmode, \"itrunc\")));
1848: DONE;
1849: }")
1850:
1851: (define_expand "fixuns_truncdfsi2"
1852: [(set (match_operand:SI 0 "gen_reg_operand" "")
1853: (unsigned_fix:DF (match_operand:DF 1 "gen_reg_operand" "")))]
1854: ""
1855: "
1856: {
1857: emit_insn (gen_trunc_call (operands[0], operands[1],
1858: gen_rtx (SYMBOL_REF, Pmode, \"uitrunc\")));
1859: DONE;
1860: }")
1861:
1862:
1863: (define_expand "trunc_call"
1864: [(parallel [(set (match_operand:SI 0 "" "")
1865: (fix:DF (match_operand:DF 1 "" "")))
1866: (use (match_operand:SI 2 "" ""))])]
1867: ""
1868: "
1869: {
1870: rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
1871: rtx first = XVECEXP (insns, 0, 0);
1872: rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1873:
1874: REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1875: REG_NOTES (first));
1876: REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
1877:
1878: emit_insn (insns);
1879: DONE;
1880: }")
1881:
1882: (define_expand "trunc_call_rtl"
1883: [(set (reg:DF 33) (match_operand:DF 1 "gen_reg_operand" ""))
1884: (use (reg:DF 33))
1885: (parallel [(set (reg:SI 3)
1886: (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
1887: (clobber (scratch:SI))])
1888: (set (match_operand:SI 0 "gen_reg_operand" "")
1889: (reg:SI 3))]
1890: ""
1891: "
1892: {
1893: rs6000_trunc_used = 1;
1894: }")
1895:
1896: ;; Define the DImode operations that can be done in a small number
1897: ;; of instructions.
1898: (define_insn "adddi3"
1899: [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1900: (plus:DI (match_operand:DI 1 "gen_reg_operand" "%r")
1901: (match_operand:DI 2 "gen_reg_operand" "r")))]
1902: ""
1903: "a %L0,%L1,%L2\;ae %0,%1,%2")
1904:
1905: (define_insn "subdi3"
1906: [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1907: (minus:DI (match_operand:DI 1 "gen_reg_operand" "r")
1908: (match_operand:DI 2 "gen_reg_operand" "r")))]
1909: ""
1910: "sf %L0,%L2,%L1\;sfe %0,%2,%1")
1911:
1912: (define_insn "negdi3"
1913: [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1914: (neg:DI (match_operand:DI 1 "gen_reg_operand" "r")))]
1915: ""
1916: "sfi %L0,%L1,0\;sfze %0,%1")
1917:
1918: (define_insn "mulsidi3"
1919: [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1920: (mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
1921: (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))))
1922: (clobber (match_scratch:SI 3 "=q"))]
1923: ""
1924: "mul %0,%1,%2\;mfmq %L0")
1925:
1926: ;; If operands 0 and 2 are in the same register, we have a problem. But
1927: ;; operands 0 and 1 (the usual case) can be in the same register. That's
1928: ;; why we have the strange constraints below.
1929: (define_insn "ashldi3"
1930: [(set (match_operand:DI 0 "gen_reg_operand" "=r,r,r,&r")
1931: (ashift:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r")
1932: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
1933: (clobber (match_scratch:SI 3 "=X,q,q,q"))]
1934: ""
1935: "@
1936: sli %0,%L1,%h2\;cal %L0,0(0)
1937: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
1938: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
1939: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2 ")
1940:
1941: (define_insn "lshrdi3"
1942: [(set (match_operand:DI 0 "gen_reg_operand" "=r,r,r,&r")
1943: (lshiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r")
1944: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
1945: (clobber (match_scratch:SI 3 "=X,q,q,q"))]
1946: ""
1947: "@
1948: cal %0,0(0)\;sri %L0,%1,%h2
1949: sr%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2
1950: sr%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2
1951: sr%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2 ")
1952:
1953: ;; Shift by a variable amount is too complex to be worth open-coding. We
1954: ;; just handle shifts by constants.
1955:
1956: (define_expand "ashrdi3"
1957: [(parallel [(set (match_operand:DI 0 "gen_reg_operand" "=")
1958: (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "")
1959: (match_operand:SI 2 "general_operand" "")))
1960: (clobber (match_scratch:SI 3 ""))])]
1961: ""
1962: "
1963: { if (GET_CODE (operands[2]) != CONST_INT)
1964: FAIL;
1965: }")
1966:
1967: (define_insn ""
1968: [(set (match_operand:DI 0 "gen_reg_operand" "=r,r")
1969: (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r")
1970: (match_operand:SI 2 "const_int_operand" "M,i")))
1971: (clobber (match_scratch:SI 3 "=X,q"))]
1972: ""
1973: "@
1974: srai %0,%1,31\;srai %L0,%1,%h2
1975: sraiq %L0,%L1,%2\;srlq %0,%1,%2")
1976:
1977: ;; Now define ways of moving data around.
1978: ;;
1979: ;; For SI, we special-case integers that can't be loaded in one insn. We
1980: ;; do the load 16-bits at a time. We could do this by loading from memory,
1981: ;; and this is even supposed to be faster, but it is simpler not to get
1982: ;; integers in the TOC.
1983: (define_expand "movsi"
1984: [(set (match_operand:SI 0 "general_operand" "")
1985: (match_operand:SI 1 "any_operand" ""))]
1986: ""
1987: "
1988: {
1989: if (GET_CODE (operands[0]) != REG)
1990: operands[1] = force_reg (SImode, operands[1]);
1991:
1992: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
1993: operands[1] = force_const_mem (SImode, operands[1]);
1994:
1995: if (GET_CODE (operands[1]) == CONST_INT
1996: && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
1997: && (INTVAL (operands[1]) & 0xffff) != 0)
1998: {
1999: emit_move_insn (operands[0],
2000: gen_rtx (CONST_INT, VOIDmode,
2001: INTVAL (operands[1]) & 0xffff0000));
2002: emit_insn (gen_iorsi3 (operands[0], operands[0],
2003: gen_rtx (CONST_INT, VOIDmode,
2004: INTVAL (operands[1]) & 0xffff)));
2005: DONE;
2006: }
2007: }")
2008:
2009: (define_insn ""
2010: [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*h")
2011: (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r"))]
2012: "gen_reg_operand (operands[0], SImode)
2013: || gen_reg_operand (operands[1], SImode)"
2014: "@
2015: ai %0,%1,0
2016: l%U1%X1 %0,%1
2017: st%U0%X0 %1,%0
2018: cal %0,%1(0)
2019: cau %0,0,%u1
2020: mf%1 %0
2021: mt%0 %1"
2022: [(set_attr "type" "*,load,*,*,*,*,*")])
2023:
2024: (define_insn ""
2025: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
2026: (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
2027: (const_int 0)))
2028: (set (match_operand:SI 0 "gen_reg_operand" "=r") (match_dup 1))]
2029: ""
2030: "ai. %0,%1,0"
2031: [(set_attr "type" "compare")])
2032:
2033: (define_expand "movhi"
2034: [(set (match_operand:HI 0 "general_operand" "")
2035: (match_operand:HI 1 "any_operand" ""))]
2036: ""
2037: "
2038: {
2039: if (GET_CODE (operands[0]) != REG)
2040: operands[1] = force_reg (HImode, operands[1]);
2041:
2042: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2043: operands[1] = force_const_mem (HImode, operands[1]);
2044: }")
2045:
2046: (define_insn ""
2047: [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2048: (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))]
2049: "gen_reg_operand (operands[0], HImode)
2050: || gen_reg_operand (operands[1], HImode)"
2051: "@
2052: oril %0,%1,0
2053: lhz%U1%X1 %0,%1
2054: sth%U0%X0 %1,%0
2055: cal %0,%w1(0)
2056: mf%1 %0
2057: mt%0 %1"
2058: [(set_attr "type" "*,load,*,*,*,*")])
2059:
2060: (define_expand "movqi"
2061: [(set (match_operand:QI 0 "general_operand" "")
2062: (match_operand:QI 1 "any_operand" ""))]
2063: ""
2064: "
2065: {
2066: if (GET_CODE (operands[0]) != REG)
2067: operands[1] = force_reg (QImode, operands[1]);
2068:
2069: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2070: operands[1] = force_const_mem (QImode, operands[1]);
2071: }")
2072:
2073: (define_insn ""
2074: [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2075: (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))]
2076: "gen_reg_operand (operands[0], QImode)
2077: || gen_reg_operand (operands[1], QImode)"
2078: "@
2079: oril %0,%1,0
2080: lbz%U1%X1 %0,%1
2081: stb%U0%X0 %1,%0
2082: cal %0,%1(0)
2083: mf%1 %0
2084: mt%0 %1"
2085: [(set_attr "type" "*,load,*,*,*,*")])
2086:
2087: ;; Here is how to move condition codes around. When we store CC data in
2088: ;; an integer register or memory, we store just the high-order 4 bits.
2089: ;; This lets us not shift in the most common case of CR0.
2090: (define_expand "movcc"
2091: [(set (match_operand:CC 0 "nonimmediate_operand" "")
2092: (match_operand:CC 1 "nonimmediate_operand" ""))]
2093: ""
2094: "")
2095:
2096: (define_insn ""
2097: [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
2098: (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
2099: "register_operand (operands[0], CCmode)
2100: || register_operand (operands[1], CCmode)"
2101: "@
2102: mcrf %0,%1
2103: mtcrf 128,%1
2104: rlinm %1,%1,%F0,0,31\;mtcrf %R0,%1\;rlinm %1,%1,%f0,0,31
2105: mfcr %0
2106: mfcr %0\;rlinm %0,%0,%f1,0,3
2107: ai %0,%1,0
2108: l%U1%X1 %0,%1
2109: st%U0%U1 %1,%0"
2110: [(set_attr "type" "*,*,*,compare,*,*,load,*")])
2111:
2112: ;; For floating-point, we normally deal with the floating-point registers.
2113: ;; The sole exception is that parameter passing can produce floating-point
2114: ;; values in fixed-point registers. Unless the value is a simple constant
2115: ;; or already in memory, we deal with this by allocating memory and copying
2116: ;; the value explicitly via that memory location.
2117: (define_expand "movsf"
2118: [(set (match_operand:SF 0 "nonimmediate_operand" "")
2119: (match_operand:SF 1 "any_operand" ""))]
2120: ""
2121: "
2122: {
2123: /* If we are called from reload, we might be getting a SUBREG of a hard
2124: reg. So expand it. */
2125: if (GET_CODE (operands[0]) == SUBREG
2126: && GET_CODE (SUBREG_REG (operands[0])) == REG
2127: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2128: operands[0] = alter_subreg (operands[0]);
2129: if (GET_CODE (operands[1]) == SUBREG
2130: && GET_CODE (SUBREG_REG (operands[1])) == REG
2131: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2132: operands[1] = alter_subreg (operands[1]);
2133:
2134: /* If we are being called from reload, it is possible that operands[1]
2135: is a hard non-fp register. So handle those cases. */
2136: if (reload_in_progress && GET_CODE (operands[1]) == REG
2137: && REGNO (operands[1]) < 32)
2138: {
2139: rtx stack_slot;
2140:
2141: /* Remember that we only see a pseudo here if it didn't get a hard
2142: register, so it is memory. */
2143: if (GET_CODE (operands[0]) == MEM
2144: || (GET_CODE (operands[0]) == REG
2145: && (REGNO (operands[0]) < 32
2146: || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2147: || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32))
2148: {
2149: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2150: operand_subword (operands[1], 0, 0, SFmode));
2151: DONE;
2152: }
2153:
2154: stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx, 4));
2155: emit_move_insn (stack_slot, operands[1]);
2156: emit_move_insn (operands[0], stack_slot);
2157: DONE;
2158: }
2159:
2160: if (GET_CODE (operands[0]) == MEM)
2161: operands[1] = force_reg (SFmode, operands[1]);
2162:
2163: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2164: {
2165: rtx stack_slot;
2166:
2167: if (GET_CODE (operands[1]) == MEM
2168: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2169: || GET_CODE (operands[1]) == CONST_DOUBLE
2170: #endif
2171: || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2172: || (reload_in_progress && GET_CODE (operands[1]) == REG
2173: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2174: {
2175: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2176: operand_subword (operands[1], 0, 0, SFmode));
2177: DONE;
2178: }
2179:
2180: if (reload_in_progress)
2181: stack_slot = gen_rtx (MEM, SFmode,
2182: plus_constant (stack_pointer_rtx, 4));
2183: else
2184: stack_slot = assign_stack_temp (SFmode, 4, 0);
2185: emit_move_insn (stack_slot, operands[1]);
2186: emit_move_insn (operands[0], stack_slot);
2187: DONE;
2188: }
2189:
2190: if (CONSTANT_P (operands[1]))
2191: {
2192: operands[1] = force_const_mem (SFmode, operands[1]);
2193: if (! memory_address_p (SFmode, XEXP (operands[1], 0))
2194: && ! reload_in_progress)
2195: operands[1] = change_address (operands[1], SFmode,
2196: XEXP (operands[1], 0));
2197: }
2198: }")
2199:
2200: (define_insn ""
2201: [(set (match_operand:SF 0 "gen_reg_operand" "=r,r")
2202: (match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))]
2203: "REGNO (operands[0]) <= 31"
2204: "@
2205: #
2206: l%U1%X1 %0,%1"
2207: [(set_attr "type" "*,load")])
2208:
2209: (define_split
2210: [(set (match_operand:SF 0 "gen_reg_operand" "")
2211: (match_operand:SF 1 "easy_fp_constant" ""))]
2212: "reload_completed && REGNO (operands[0]) <= 31"
2213: [(set (match_dup 2) (match_dup 3))]
2214: "
2215: { operands[2] = operand_subword (operands[0], 0, 0, SFmode);
2216: operands[3] = operand_subword (operands[1], 0, 0, SFmode); }")
2217:
2218: (define_insn ""
2219: [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
2220: (match_operand:SF 1 "input_operand" "f,m,f"))]
2221: "gen_reg_operand (operands[0], SFmode)
2222: || gen_reg_operand (operands[1], SFmode)"
2223: "@
2224: fmr %0,%1
2225: lfs%U1%X1 %0,%1
2226: frsp %1,%1\;stfs%U0%X0 %1,%0"
2227: [(set_attr "type" "fp,load,*")])
2228:
2229: (define_expand "movdf"
2230: [(set (match_operand:DF 0 "nonimmediate_operand" "")
2231: (match_operand:DF 1 "any_operand" ""))]
2232: ""
2233: "
2234: {
2235: /* If we are called from reload, we might be getting a SUBREG of a hard
2236: reg. So expand it. */
2237: if (GET_CODE (operands[0]) == SUBREG
2238: && GET_CODE (SUBREG_REG (operands[0])) == REG
2239: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2240: operands[0] = alter_subreg (operands[0]);
2241: if (GET_CODE (operands[1]) == SUBREG
2242: && GET_CODE (SUBREG_REG (operands[1])) == REG
2243: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2244: operands[1] = alter_subreg (operands[1]);
2245:
2246: /* If we are being called from reload, it is possible that operands[1]
2247: is a hard non-fp register. So handle those cases. */
2248: if (reload_in_progress && GET_CODE (operands[1]) == REG
2249: && REGNO (operands[1]) < 32)
2250: {
2251: rtx stack_slot;
2252:
2253: /* Remember that we only see a pseudo here if it didn't get a hard
2254: register, so it is memory. */
2255: if (GET_CODE (operands[0]) == MEM
2256: || (GET_CODE (operands[0]) == REG
2257: && (REGNO (operands[0]) < 32
2258: || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)))
2259: {
2260: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2261: operand_subword (operands[1], 0, 0, DFmode));
2262: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2263: operand_subword (operands[1], 1, 0, DFmode));
2264: DONE;
2265: }
2266:
2267: stack_slot = gen_rtx (MEM, DFmode, plus_constant (stack_pointer_rtx, 8));
2268: emit_move_insn (stack_slot, operands[1]);
2269: emit_move_insn (operands[0], stack_slot);
2270: DONE;
2271: }
2272:
2273: if (GET_CODE (operands[0]) == MEM)
2274: {
2275: if (GET_CODE (operands[1]) == MEM)
2276: {
2277: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2278: operand_subword (operands[1], 0, 0, DFmode));
2279: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2280: operand_subword (operands[1], 1, 0, DFmode));
2281: DONE;
2282: }
2283:
2284: operands[1] = force_reg (DFmode, operands[1]);
2285: }
2286:
2287: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2288: {
2289: rtx stack_slot;
2290:
2291: if (GET_CODE (operands[1]) == MEM
2292: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2293: || GET_CODE (operands[1]) == CONST_DOUBLE
2294: #endif
2295: || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2296: || (reload_in_progress && GET_CODE (operands[1]) == REG
2297: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2298: {
2299: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2300: operand_subword (operands[1], 0, 0, DFmode));
2301: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2302: operand_subword (operands[1], 1, 0, DFmode));
2303: DONE;
2304: }
2305:
2306: if (reload_in_progress)
2307: stack_slot = gen_rtx (MEM, DFmode,
2308: plus_constant (stack_pointer_rtx, 8));
2309: else
2310: stack_slot = assign_stack_temp (DFmode, 8, 0);
2311: emit_move_insn (stack_slot, operands[1]);
2312: emit_move_insn (operands[0], stack_slot);
2313: DONE;
2314: }
2315:
2316: if (CONSTANT_P (operands[1]))
2317: {
2318: operands[1] = force_const_mem (DFmode, operands[1]);
2319: if (! memory_address_p (DFmode, XEXP (operands[1], 0))
2320: && ! reload_in_progress)
2321: operands[1] = change_address (operands[1], DFmode,
2322: XEXP (operands[1], 0));
2323: }
2324: }")
2325:
2326: (define_insn ""
2327: [(set (match_operand:DF 0 "gen_reg_operand" "=r,r")
2328: (match_operand:DF 1 "mem_or_easy_const_operand" "G,m"))]
2329: "REGNO (operands[0]) <= 31"
2330: "@
2331: #
2332: l %0,%1\;l %L0,%L1"
2333: [(set_attr "type" "*,load")])
2334:
2335: (define_split
2336: [(set (match_operand:DF 0 "gen_reg_operand" "")
2337: (match_operand:DF 1 "easy_fp_constant" ""))]
2338: "reload_completed && REGNO (operands[0]) <= 31"
2339: [(set (match_dup 2) (match_dup 3))
2340: (set (match_dup 4) (match_dup 5))]
2341: "
2342: { operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2343: operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2344: operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2345: operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
2346:
2347: (define_insn ""
2348: [(set (match_operand:DF 0 "fp_reg_or_mem_operand" "=f,f,m")
2349: (match_operand:DF 1 "fp_reg_or_mem_operand" "f,m,f"))]
2350: "gen_reg_operand (operands[0], DFmode)
2351: || gen_reg_operand (operands[1], DFmode)"
2352: "@
2353: fmr %0,%1
2354: lfd%U1%X1 %0,%1
2355: stfd%U0%X0 %1,%0"
2356: [(set_attr "type" "fp,load,*")])
2357:
2358: ;; Next come the multi-word integer load and store and the load and store
2359: ;; multiple insns.
2360: (define_expand "movdi"
2361: [(set (match_operand:DI 0 "general_operand" "")
2362: (match_operand:DI 1 "general_operand" ""))]
2363: ""
2364: "
2365: {
2366: if (GET_CODE (operands[0]) == MEM)
2367: operands[1] = force_reg (DImode, operands[1]);
2368:
2369: else if (GET_CODE (operands[1]) == CONST_DOUBLE
2370: || GET_CODE (operands[1]) == CONST_INT)
2371: {
2372: emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
2373: operand_subword (operands[1], 0, 0, DImode));
2374: emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
2375: operand_subword (operands[1], 1, 0, DImode));
2376: DONE;
2377: }
2378: }")
2379:
2380: (define_insn ""
2381: [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
2382: (match_operand:DI 1 "input_operand" "r,m,r"))]
2383: "gen_reg_operand (operands[0], DImode)
2384: || gen_reg_operand (operands[1], DImode)"
2385: "*
2386: {
2387: switch (which_alternative)
2388: {
2389: case 0:
2390: /* We normally copy the low-numbered register first. However, if
2391: the first register operand 0 is the same as the second register of
2392: operand 1, we must copy in the opposite order. */
2393: if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
2394: return \"oril %L0,%L1,0\;oril %0,%1,0\";
2395: else
2396: return \"oril %0,%1,0\;oril %L0,%L1,0\";
2397: case 1:
2398: /* If the low-address word is used in the address, we must load it
2399: last. Otherwise, load it first. Note that we cannot have
2400: auto-increment in that case since the address register is known to be
2401: dead. */
2402: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2403: operands [1], 0))
2404: return \"l %L0,%L1\;l %0,%1\";
2405: else
2406: return \"l%U1 %0,%1\;l %L0,%L1\";
2407: case 2:
2408: return \"st%U0 %1,%0\;st %L1,%L0\";
2409: }
2410: }"
2411: [(set_attr "type" "*,load,*")])
2412:
2413: ;; TImode is similar, except that we usually want to compute the address into
2414: ;; a register and use lsi/stsi (the exception is during reload). MQ is also
2415: ;; clobbered in stsi, so we need a SCRATCH for it.
2416: (define_expand "movti"
2417: [(parallel [(set (match_operand:TI 0 "general_operand" "")
2418: (match_operand:TI 1 "general_operand" ""))
2419: (clobber (scratch:SI))])]
2420: ""
2421: "
2422: {
2423: if (GET_CODE (operands[0]) == MEM)
2424: operands[1] = force_reg (TImode, operands[1]);
2425:
2426: if (GET_CODE (operands[0]) == MEM
2427: && GET_CODE (XEXP (operands[0], 0)) != REG
2428: && ! reload_in_progress)
2429: operands[0] = change_address (operands[0], TImode,
2430: copy_addr_to_reg (XEXP (operands[0], 0)));
2431:
2432: if (GET_CODE (operands[1]) == MEM
2433: && GET_CODE (XEXP (operands[1], 0)) != REG
2434: && ! reload_in_progress)
2435: operands[1] = change_address (operands[1], TImode,
2436: copy_addr_to_reg (XEXP (operands[1], 0)));
2437: }")
2438:
2439: ;; We say that MQ is clobbered in the last alternative because the first
2440: ;; alternative would never get used otherwise since it would need a reload
2441: ;; while the 2nd alternative would not. We put memory cases first so they
2442: ;; are preferred. Otherwise, we'd try to reload the output instead of
2443: ;; giving the SCRATCH mq.
2444: (define_insn ""
2445: [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r")
2446: (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
2447: (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
2448: "gen_reg_operand (operands[0], TImode)
2449: || gen_reg_operand (operands[1], TImode)"
2450: "*
2451: {
2452: switch (which_alternative)
2453: {
2454: case 0:
2455: return \"stsi %1,%P0,16\";
2456:
2457: case 1:
2458: return \"st%U0 %1,%0\;st %L1,%L0\;st %Y1,%Y0\;st %Z1,%Z0\";
2459:
2460: case 2:
2461: /* Normally copy registers with lowest numbered register copied first.
2462: But copy in the other order if the first register of the output
2463: is the second, third, or fourth register in the input. */
2464: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
2465: && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
2466: return \"oril %Z0,%Z1,0\;oril %Y0,%Y1,0\;oril %L0,%L1,0\;oril %0,%1,0\";
2467: else
2468: return \"oril %0,%1,0\;oril %L0,%L1,0\;oril %Y0,%Y1,0\;oril %Z0,%Z1,0\";
2469: case 3:
2470: /* If the address is not used in the output, we can use lsi. Otherwise,
2471: fall through to generating four loads. */
2472: if (! reg_overlap_mentioned_p (operands[0], operands[1]))
2473: return \"lsi %0,%P1,16\";
2474: /* ... fall through ... */
2475: case 4:
2476: /* If the address register is the same as the register for the lowest-
2477: addressed word, load it last. Similarly for the next two words.
2478: Otherwise load lowest address to highest. */
2479: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2480: operands[1], 0))
2481: return \"l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\;l %0,%1\";
2482: else if (refers_to_regno_p (REGNO (operands[0]) + 1,
2483: REGNO (operands[0]) + 2, operands[1], 0))
2484: return \"l %0,%1\;l %Y0,%Y1\;l %Z0,%Z1\;l %L0,%L1\";
2485: else if (refers_to_regno_p (REGNO (operands[0]) + 2,
2486: REGNO (operands[0]) + 3, operands[1], 0))
2487: return \"l %0,%1\;l %L0,%L1\;l %Z0,%Z1\;l %Y0,%Y1\";
2488: else
2489: return \"l%U1 %0,%1\;l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\";
2490: }
2491: }"
2492: [(set_attr "type" "*,load,load,*,*")])
2493:
2494: (define_expand "load_multiple"
2495: [(match_parallel 3 "" [(set (match_operand:SI 0 "" "")
2496: (match_operand:SI 1 "" ""))
2497: (use (match_operand:SI 2 "" ""))])]
2498: ""
2499: "
2500: {
2501: int regno;
2502: int count;
2503: rtx from;
2504: int i;
2505:
2506: /* Support only loading a constant number of fixed-point registers from
2507: memory and only bother with this if more than two; the machine
2508: doesn't support more than eight. */
2509: if (GET_CODE (operands[2]) != CONST_INT
2510: || INTVAL (operands[2]) <= 2
2511: || INTVAL (operands[2]) > 8
2512: || GET_CODE (operands[1]) != MEM
2513: || GET_CODE (operands[0]) != REG
2514: || REGNO (operands[0]) >= 32)
2515: FAIL;
2516:
2517: count = INTVAL (operands[2]);
2518: regno = REGNO (operands[0]);
2519:
2520: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
2521: from = force_reg (SImode, XEXP (operands[1], 0));
2522:
2523: for (i = 0; i < count; i++)
2524: XVECEXP (operands[3], 0, i)
2525: = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
2526: gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
2527: }")
2528:
2529: (define_insn ""
2530: [(match_parallel 0 "load_multiple_operation"
2531: [(set (match_operand:SI 1 "gen_reg_operand" "=r")
2532: (match_operand:SI 2 "indirect_operand" "Q"))])]
2533: ""
2534: "*
2535: {
2536: /* We have to handle the case where the pseudo used to contain the address
2537: is assigned to one of the output registers. In that case, do the
2538: lsi, but then load the correct value. This is a bit of a mess, but is
2539: the best we can do. */
2540: static char result[100];
2541: char newload[40];
2542: int i;
2543:
2544: strcpy (result, \"lsi %1,%P2,%N0\");
2545: for (i = 0; i < XVECLEN (operands[0], 0); i++)
2546: if (refers_to_regno_p (REGNO (operands[1]) + i,
2547: REGNO (operands[1]) + i + 1, operands[2], 0))
2548: {
2549: sprintf (newload, \"\;l %d,%d(%d)\",
2550: REGNO (operands[1]) + i,
2551: i * 4, REGNO (XEXP (operands[2], 0)));
2552: strcat (result, newload);
2553: }
2554:
2555: return result;
2556: }"
2557: [(set_attr "type" "load")])
2558:
2559: (define_expand "store_multiple"
2560: [(match_parallel 3 "" [(set (match_operand:SI 0 "" "")
2561: (match_operand:SI 1 "" ""))
2562: (clobber (scratch:SI))
2563: (use (match_operand:SI 2 "" ""))])]
2564: ""
2565: "
2566: {
2567: int regno;
2568: int count;
2569: rtx to;
2570: int i;
2571:
2572: /* Support only storing a constant number of fixed-point registers to
2573: memory and only bother with this if more than two; the machine
2574: doesn't support more than eight. */
2575: if (GET_CODE (operands[2]) != CONST_INT
2576: || INTVAL (operands[2]) <= 2
2577: || INTVAL (operands[2]) > 8
2578: || GET_CODE (operands[0]) != MEM
2579: || GET_CODE (operands[1]) != REG
2580: || REGNO (operands[1]) >= 32)
2581: FAIL;
2582:
2583: count = INTVAL (operands[2]);
2584: regno = REGNO (operands[1]);
2585:
2586: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
2587: to = force_reg (SImode, XEXP (operands[0], 0));
2588:
2589: XVECEXP (operands[3], 0, 0)
2590: = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]);
2591: XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode,
2592: gen_rtx (SCRATCH, SImode));
2593:
2594: for (i = 1; i < count; i++)
2595: XVECEXP (operands[3], 0, i + 1)
2596: = gen_rtx (SET, VOIDmode,
2597: gen_rtx (MEM, SImode, plus_constant (to, i * 4)),
2598: gen_rtx (REG, SImode, regno + i));
2599: }")
2600:
2601: (define_insn ""
2602: [(match_parallel 0 "store_multiple_operation"
2603: [(set (match_operand:SI 1 "indirect_operand" "=Q")
2604: (match_operand:SI 2 "gen_reg_operand" "r"))
2605: (clobber (match_scratch:SI 3 "=q"))])]
2606: ""
2607: "stsi %2,%P1,%O0")
2608:
2609: ;; Define insns that do load or store with update. Some of these we can
2610: ;; get by using pre-decrement or pre-increment, but the hardware can also
2611: ;; do cases where the increment is not the size of the object.
2612: ;;
2613: ;; In all these cases, we use operands 0 and 1 for the register being
2614: ;; incremented because those are the operands that local-alloc will
2615: ;; tie and these are the pair most likely to be tieable (and the ones
2616: ;; that will benefit the most).
2617:
2618: (define_insn ""
2619: [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2620: (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2621: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2622: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2623: (plus:SI (match_dup 1) (match_dup 2)))]
2624: ""
2625: "@
2626: lux %3,%1,%2
2627: lu %3,%2(%1)"
2628: [(set_attr "type" "load,load")])
2629:
2630: (define_insn ""
2631: [(set (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2632: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2633: (match_operand:SI 3 "gen_reg_operand" "r,r"))
2634: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2635: (plus:SI (match_dup 1) (match_dup 2)))]
2636: ""
2637: "@
2638: stux %3,%1,%2
2639: stu %3,%2(%1)")
2640:
2641: (define_insn ""
2642: [(set (match_operand:HI 3 "gen_reg_operand" "=r,r")
2643: (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2644: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2645: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2646: (plus:SI (match_dup 1) (match_dup 2)))]
2647: ""
2648: "@
2649: lhzux %3,%1,%2
2650: lhzu %3,%2(%1)"
2651: [(set_attr "type" "load,load")])
2652:
2653: (define_insn ""
2654: [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2655: (zero_extend:SI
2656: (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2657: (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2658: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2659: (plus:SI (match_dup 1) (match_dup 2)))]
2660: ""
2661: "@
2662: lhzux %3,%1,%2
2663: lhzu %3,%2(%1)"
2664: [(set_attr "type" "load,load")])
2665:
2666: (define_insn ""
2667: [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2668: (sign_extend:SI
2669: (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2670: (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2671: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2672: (plus:SI (match_dup 1) (match_dup 2)))]
2673: ""
2674: "@
2675: lhaux %3,%1,%2
2676: lhau %3,%2(%1)"
2677: [(set_attr "type" "load,load")])
2678:
2679: (define_insn ""
2680: [(set (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2681: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2682: (match_operand:HI 3 "gen_reg_operand" "r,r"))
2683: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2684: (plus:SI (match_dup 1) (match_dup 2)))]
2685: ""
2686: "@
2687: sthux %3,%1,%2
2688: sthu %3,%2(%1)"
2689: [(set_attr "type" "load,load")])
2690:
2691: (define_insn ""
2692: [(set (match_operand:QI 3 "gen_reg_operand" "=r,r")
2693: (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2694: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2695: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2696: (plus:SI (match_dup 1) (match_dup 2)))]
2697: ""
2698: "@
2699: lbzux %3,%1,%2
2700: lbzu %3,%2(%1)"
2701: [(set_attr "type" "load,load")])
2702:
2703: (define_insn ""
2704: [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2705: (zero_extend:SI
2706: (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2707: (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2708: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2709: (plus:SI (match_dup 1) (match_dup 2)))]
2710: ""
2711: "@
2712: lbzux %3,%1,%2
2713: lbzu %3,%2(%1)"
2714: [(set_attr "type" "load,load")])
2715:
2716: (define_insn ""
2717: [(set (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2718: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2719: (match_operand:QI 3 "gen_reg_operand" "r,r"))
2720: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2721: (plus:SI (match_dup 1) (match_dup 2)))]
2722: ""
2723: "@
2724: stbux %3,%1,%2
2725: stbu %3,%2(%1)")
2726:
2727: (define_insn ""
2728: [(set (match_operand:SF 3 "gen_reg_operand" "=f,f")
2729: (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2730: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2731: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2732: (plus:SI (match_dup 1) (match_dup 2)))]
2733: ""
2734: "@
2735: lfsux %3,%1,%2
2736: lfsu %3,%2(%1)"
2737: [(set_attr "type" "load,load")])
2738:
2739: (define_insn ""
2740: [(set (mem:SF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2741: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2742: (match_operand:SF 3 "gen_reg_operand" "f,f"))
2743: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2744: (plus:SI (match_dup 1) (match_dup 2)))]
2745: ""
2746: "@
2747: frsp %3,%3\;stfsux %3,%1,%2
2748: frsp %3,%3\;stfsu %3,%2(%1)")
2749:
2750: (define_insn ""
2751: [(set (match_operand:DF 3 "gen_reg_operand" "=f,f")
2752: (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2753: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2754: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2755: (plus:SI (match_dup 1) (match_dup 2)))]
2756: ""
2757: "@
2758: lfdux %3,%1,%2
2759: lfdu %3,%2(%1)"
2760: [(set_attr "type" "load,load")])
2761:
2762: (define_insn ""
2763: [(set (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2764: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2765: (match_operand:DF 3 "gen_reg_operand" "f,f"))
2766: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2767: (plus:SI (match_dup 1) (match_dup 2)))]
2768: ""
2769: "@
2770: stfdux %3,%1,%2
2771: stfdu %3,%2(%1)")
2772:
2773: ;; Next come insns related to the calling sequence.
2774: ;;
2775: ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
2776: ;; We move the back-chain and decremement the stack pointer. This is slightly
2777: ;; less efficient than it needs to be for long constants, but that case
2778: ;; should be rare.
2779:
2780: (define_expand "allocate_stack"
2781: [(set (reg:SI 1)
2782: (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_cint_operand" "")))]
2783: ""
2784: "
2785: { rtx chain = gen_reg_rtx (SImode);
2786: rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
2787:
2788: emit_move_insn (chain, stack_bot);
2789: emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0]));
2790: emit_move_insn (stack_bot, chain);
2791: DONE;
2792: }")
2793:
2794: ;; A function pointer is a pointer to a data area whose first word contains
2795: ;; the actual address of the function, whose second word contains a pointer
2796: ;; to its TOC, and whose third word contains a value to place in the static
2797: ;; chain register (r11). Note that if we load the static chain, our
2798: ;; "trampoline" need not have any executable code.
2799: ;;
2800: ;; operands[0] is an SImode pseudo in which we place the address of the
2801: ;; function.
2802: ;; operands[1] is the address of data area of the function to call
2803:
2804: (define_expand "call_via_ptr"
2805: [(set (match_operand:SI 0 "gen_reg_operand" "")
2806: (mem:SI (match_operand:SI 1 "gen_reg_operand" "")))
2807: (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
2808: (reg:SI 2))
2809: (set (reg:SI 2)
2810: (mem:SI (plus:SI (match_dup 1)
2811: (const_int 4))))
2812: (set (reg:SI 11)
2813: (mem:SI (plus:SI (match_dup 1)
2814: (const_int 8))))
2815: (use (reg:SI 2))
2816: (use (reg:SI 11))]
2817: ""
2818: "")
2819:
2820: (define_expand "call"
2821: [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
2822: (match_operand 1 "" ""))
2823: (clobber (scratch:SI))])]
2824: ""
2825: "
2826: {
2827: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
2828: abort ();
2829:
2830: operands[0] = XEXP (operands[0], 0);
2831: if (GET_CODE (operands[0]) != SYMBOL_REF)
2832: {
2833: rtx temp = gen_reg_rtx (SImode);
2834:
2835: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0])));
2836: operands[0] = temp;
2837: }
2838: }")
2839:
2840: (define_expand "call_value"
2841: [(parallel [(set (match_operand 0 "" "")
2842: (call (mem:SI (match_operand:SI 1 "address_operand" ""))
2843: (match_operand 2 "" "")))
2844: (clobber (scratch:SI))])]
2845: ""
2846: "
2847: {
2848: if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
2849: abort ();
2850:
2851: operands[1] = XEXP (operands[1], 0);
2852: if (GET_CODE (operands[1]) != SYMBOL_REF)
2853: {
2854: rtx temp = gen_reg_rtx (SImode);
2855:
2856: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1])));
2857: operands[1] = temp;
2858: }
2859: }")
2860:
2861: (define_insn ""
2862: [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s"))
2863: (match_operand 1 "" "fg,fg"))
2864: (clobber (match_scratch:SI 3 "=l,l"))]
2865: ""
2866: "@
2867: brl\;l 2,20(1)
2868: bl %z0\;cror 15,15,15")
2869:
2870: (define_insn ""
2871: [(set (match_operand 0 "" "fg,fg")
2872: (call (mem:SI (match_operand:SI 1 "call_operand" "l,s"))
2873: (match_operand 2 "" "fg,fg")))
2874: (clobber (match_scratch:SI 3 "=l,l"))]
2875: ""
2876: "@
2877: brl\;l 2,20(1)
2878: bl %z1\;cror 15,15,15")
2879:
2880: ;; Compare insns are next. Note that the RS/6000 has two types of compares,
2881: ;; signed & unsigned, and one type of branch.
2882: ;;
2883: ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
2884: ;; insns, and branches. We store the operands of compares until we see
2885: ;; how it is used.
2886: (define_expand "cmpsi"
2887: [(set (cc0)
2888: (compare (match_operand:SI 0 "gen_reg_operand" "")
2889: (match_operand:SI 1 "reg_or_short_operand" "")))]
2890: ""
2891: "
2892: {
2893: /* Take care of the possibility that operands[1] might be negative but
2894: this might be a logical operation. That insn doesn't exist. */
2895: if (GET_CODE (operands[1]) == CONST_INT
2896: && INTVAL (operands[1]) < 0)
2897: operands[1] = force_reg (SImode, operands[1]);
2898:
2899: rs6000_compare_op0 = operands[0];
2900: rs6000_compare_op1 = operands[1];
2901: rs6000_compare_fp_p = 0;
2902: DONE;
2903: }")
2904:
2905: (define_expand "cmpsf"
2906: [(set (cc0) (compare (match_operand:SF 0 "gen_reg_operand" "")
2907: (match_operand:SF 1 "gen_reg_operand" "")))]
2908: ""
2909: "
2910: {
2911: rs6000_compare_op0 = operands[0];
2912: rs6000_compare_op1 = operands[1];
2913: rs6000_compare_fp_p = 1;
2914: DONE;
2915: }")
2916:
2917: (define_expand "cmpdf"
2918: [(set (cc0) (compare (match_operand:DF 0 "gen_reg_operand" "")
2919: (match_operand:DF 1 "gen_reg_operand" "")))]
2920: ""
2921: "
2922: {
2923: rs6000_compare_op0 = operands[0];
2924: rs6000_compare_op1 = operands[1];
2925: rs6000_compare_fp_p = 1;
2926: DONE;
2927: }")
2928:
2929: (define_expand "beq"
2930: [(set (match_dup 2) (match_dup 1))
2931: (set (pc)
2932: (if_then_else (eq (match_dup 2)
2933: (const_int 0))
2934: (label_ref (match_operand 0 "" ""))
2935: (pc)))]
2936: ""
2937: "
2938: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
2939: operands[1] = gen_rtx (COMPARE, mode,
2940: rs6000_compare_op0, rs6000_compare_op1);
2941: operands[2] = gen_reg_rtx (mode);
2942: }")
2943:
2944: (define_expand "bne"
2945: [(set (match_dup 2) (match_dup 1))
2946: (set (pc)
2947: (if_then_else (ne (match_dup 2)
2948: (const_int 0))
2949: (label_ref (match_operand 0 "" ""))
2950: (pc)))]
2951: ""
2952: "
2953: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
2954: operands[1] = gen_rtx (COMPARE, mode,
2955: rs6000_compare_op0, rs6000_compare_op1);
2956: operands[2] = gen_reg_rtx (mode);
2957: }")
2958:
2959: (define_expand "blt"
2960: [(set (match_dup 2) (match_dup 1))
2961: (set (pc)
2962: (if_then_else (lt (match_dup 2)
2963: (const_int 0))
2964: (label_ref (match_operand 0 "" ""))
2965: (pc)))]
2966: ""
2967: "
2968: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
2969: operands[1] = gen_rtx (COMPARE, mode,
2970: rs6000_compare_op0, rs6000_compare_op1);
2971: operands[2] = gen_reg_rtx (mode);
2972: }")
2973:
2974: (define_expand "bgt"
2975: [(set (match_dup 2) (match_dup 1))
2976: (set (pc)
2977: (if_then_else (gt (match_dup 2)
2978: (const_int 0))
2979: (label_ref (match_operand 0 "" ""))
2980: (pc)))]
2981: ""
2982: "
2983: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
2984: operands[1] = gen_rtx (COMPARE, mode,
2985: rs6000_compare_op0, rs6000_compare_op1);
2986: operands[2] = gen_reg_rtx (mode);
2987: }")
2988:
2989: (define_expand "ble"
2990: [(set (match_dup 2) (match_dup 1))
2991: (set (pc)
2992: (if_then_else (le (match_dup 2)
2993: (const_int 0))
2994: (label_ref (match_operand 0 "" ""))
2995: (pc)))]
2996: ""
2997: "
2998: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
2999: operands[1] = gen_rtx (COMPARE, mode,
3000: rs6000_compare_op0, rs6000_compare_op1);
3001: operands[2] = gen_reg_rtx (mode);
3002: }")
3003:
3004: (define_expand "bge"
3005: [(set (match_dup 2) (match_dup 1))
3006: (set (pc)
3007: (if_then_else (ge (match_dup 2)
3008: (const_int 0))
3009: (label_ref (match_operand 0 "" ""))
3010: (pc)))]
3011: ""
3012: "
3013: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3014: operands[1] = gen_rtx (COMPARE, mode,
3015: rs6000_compare_op0, rs6000_compare_op1);
3016: operands[2] = gen_reg_rtx (mode);
3017: }")
3018:
3019: (define_expand "bgtu"
3020: [(set (match_dup 2) (match_dup 1))
3021: (set (pc)
3022: (if_then_else (gtu (match_dup 2)
3023: (const_int 0))
3024: (label_ref (match_operand 0 "" ""))
3025: (pc)))]
3026: ""
3027: "
3028: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3029: rs6000_compare_op0, rs6000_compare_op1);
3030: operands[2] = gen_reg_rtx (CCUNSmode);
3031: }")
3032:
3033: (define_expand "bltu"
3034: [(set (match_dup 2) (match_dup 1))
3035: (set (pc)
3036: (if_then_else (ltu (match_dup 2)
3037: (const_int 0))
3038: (label_ref (match_operand 0 "" ""))
3039: (pc)))]
3040: ""
3041: "
3042: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3043: rs6000_compare_op0, rs6000_compare_op1);
3044: operands[2] = gen_reg_rtx (CCUNSmode);
3045: }")
3046:
3047: (define_expand "bgeu"
3048: [(set (match_dup 2) (match_dup 1))
3049: (set (pc)
3050: (if_then_else (geu (match_dup 2)
3051: (const_int 0))
3052: (label_ref (match_operand 0 "" ""))
3053: (pc)))]
3054: ""
3055: "
3056: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3057: rs6000_compare_op0, rs6000_compare_op1);
3058: operands[2] = gen_reg_rtx (CCUNSmode);
3059: }")
3060:
3061: (define_expand "bleu"
3062: [(set (match_dup 2) (match_dup 1))
3063: (set (pc)
3064: (if_then_else (leu (match_dup 2)
3065: (const_int 0))
3066: (label_ref (match_operand 0 "" ""))
3067: (pc)))]
3068: ""
3069: "
3070: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3071: rs6000_compare_op0, rs6000_compare_op1);
3072: operands[2] = gen_reg_rtx (CCUNSmode);
3073: }")
3074:
3075: ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
3076: ;; For SEQ, likewise, except that comparisons with zero should be done
3077: ;; with an scc insns. However, due to the order that combine see the
3078: ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
3079: ;; the cases we don't want to handle.
3080: (define_expand "seq"
3081: [(set (match_dup 2) (match_dup 1))
3082: (set (match_operand:SI 0 "gen_reg_operand" "")
3083: (eq:SI (match_dup 2) (const_int 0)))]
3084: ""
3085: "
3086: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3087: operands[1] = gen_rtx (COMPARE, mode,
3088: rs6000_compare_op0, rs6000_compare_op1);
3089: operands[2] = gen_reg_rtx (mode);
3090: }")
3091:
3092: (define_expand "sne"
3093: [(set (match_dup 2) (match_dup 1))
3094: (set (match_operand:SI 0 "gen_reg_operand" "")
3095: (ne:SI (match_dup 2) (const_int 0)))]
3096: ""
3097: "
3098: { if (! rs6000_compare_fp_p)
3099: FAIL;
3100:
3101: operands[1] = gen_rtx (COMPARE, CCFPmode,
3102: rs6000_compare_op0, rs6000_compare_op1);
3103: operands[2] = gen_reg_rtx (CCFPmode);
3104: }")
3105:
3106: ;; A > 0 is best done using the portable sequence, so fail in that case.
3107: (define_expand "sgt"
3108: [(set (match_dup 2) (match_dup 1))
3109: (set (match_operand:SI 0 "gen_reg_operand" "")
3110: (gt:SI (match_dup 2) (const_int 0)))]
3111: ""
3112: "
3113: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3114:
3115: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3116: FAIL;
3117:
3118: operands[1] = gen_rtx (COMPARE, mode,
3119: rs6000_compare_op0, rs6000_compare_op1);
3120: operands[2] = gen_reg_rtx (mode);
3121: }")
3122:
3123: ;; A < 0 is best done in the portable way for A an integer.
3124: (define_expand "slt"
3125: [(set (match_dup 2) (match_dup 1))
3126: (set (match_operand:SI 0 "gen_reg_operand" "")
3127: (lt:SI (match_dup 2) (const_int 0)))]
3128: ""
3129: "
3130: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3131:
3132: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3133: FAIL;
3134:
3135: operands[1] = gen_rtx (COMPARE, mode,
3136: rs6000_compare_op0, rs6000_compare_op1);
3137: operands[2] = gen_reg_rtx (mode);
3138: }")
3139:
3140: (define_expand "sge"
3141: [(set (match_dup 2) (match_dup 1))
3142: (set (match_operand:SI 0 "gen_reg_operand" "")
3143: (ge:SI (match_dup 2) (const_int 0)))]
3144: ""
3145: "
3146: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3147: operands[1] = gen_rtx (COMPARE, mode,
3148: rs6000_compare_op0, rs6000_compare_op1);
3149: operands[2] = gen_reg_rtx (mode);
3150: }")
3151:
3152: ;; A <= 0 is best done the portable way for A an integer.
3153: (define_expand "sle"
3154: [(set (match_dup 2) (match_dup 1))
3155: (set (match_operand:SI 0 "gen_reg_operand" "")
3156: (le:SI (match_dup 2) (const_int 0)))]
3157: ""
3158: "
3159: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3160:
3161: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3162: FAIL;
3163:
3164: operands[1] = gen_rtx (COMPARE, mode,
3165: rs6000_compare_op0, rs6000_compare_op1);
3166: operands[2] = gen_reg_rtx (mode);
3167: }")
3168:
3169: (define_expand "sgtu"
3170: [(set (match_dup 2) (match_dup 1))
3171: (set (match_operand:SI 0 "gen_reg_operand" "")
3172: (gtu:SI (match_dup 2) (const_int 0)))]
3173: ""
3174: "
3175: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3176: rs6000_compare_op0, rs6000_compare_op1);
3177: operands[2] = gen_reg_rtx (CCUNSmode);
3178: }")
3179:
3180: (define_expand "sltu"
3181: [(set (match_dup 2) (match_dup 1))
3182: (set (match_operand:SI 0 "gen_reg_operand" "")
3183: (ltu:SI (match_dup 2) (const_int 0)))]
3184: ""
3185: "
3186: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3187: rs6000_compare_op0, rs6000_compare_op1);
3188: operands[2] = gen_reg_rtx (CCUNSmode);
3189: }")
3190:
3191: (define_expand "sgeu"
3192: [(set (match_dup 2) (match_dup 1))
3193: (set (match_operand:SI 0 "gen_reg_operand" "")
3194: (geu:SI (match_dup 2) (const_int 0)))]
3195: ""
3196: "
3197: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3198: rs6000_compare_op0, rs6000_compare_op1);
3199: operands[2] = gen_reg_rtx (CCUNSmode);
3200: }")
3201:
3202: (define_expand "sleu"
3203: [(set (match_dup 2) (match_dup 1))
3204: (set (match_operand:SI 0 "gen_reg_operand" "")
3205: (leu:SI (match_dup 2) (const_int 0)))]
3206: ""
3207: "
3208: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3209: rs6000_compare_op0, rs6000_compare_op1);
3210: operands[2] = gen_reg_rtx (CCUNSmode);
3211: }")
3212:
3213: ;; Here are the actual compare insns.
3214: (define_insn ""
3215: [(set (match_operand:CC 0 "cc_reg_operand" "=y")
3216: (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
3217: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3218: ""
3219: "cmp%I2 %0,%1,%2"
3220: [(set_attr "type" "compare")])
3221:
3222: (define_insn ""
3223: [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
3224: (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r")
3225: (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
3226: ""
3227: "cmpl%I2 %0,%1,%W2"
3228: [(set_attr "type" "compare")])
3229:
3230: ;; The following two insns don't exist as single insns, but if we provide
3231: ;; them, we can swap an add and compare, which will enable us to overlap more
3232: ;; of the required delay between a compare and branch. We generate code for
3233: ;; them by splitting.
3234:
3235: (define_insn ""
3236: [(set (match_operand:CC 3 "cc_reg_operand" "=y")
3237: (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
3238: (match_operand:SI 2 "short_cint_operand" "i")))
3239: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3240: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3241: ""
3242: "#")
3243:
3244: (define_insn ""
3245: [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
3246: (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r")
3247: (match_operand:SI 2 "u_short_cint_operand" "i")))
3248: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3249: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3250: ""
3251: "#")
3252:
3253: (define_split
3254: [(set (match_operand:CC 3 "cc_reg_operand" "")
3255: (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
3256: (match_operand:SI 2 "short_cint_operand" "")))
3257: (set (match_operand:SI 0 "gen_reg_operand" "")
3258: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3259: ""
3260: [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
3261: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3262:
3263: (define_split
3264: [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
3265: (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "")
3266: (match_operand:SI 2 "u_short_cint_operand" "")))
3267: (set (match_operand:SI 0 "gen_reg_operand" "")
3268: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3269: ""
3270: [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
3271: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3272:
3273: (define_insn ""
3274: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3275: (compare:CCFP (match_operand:SF 1 "gen_reg_operand" "f")
3276: (match_operand:SF 2 "gen_reg_operand" "f")))]
3277: ""
3278: "fcmpu %0,%1,%2"
3279: [(set_attr "type" "fpcompare")])
3280:
3281: (define_insn ""
3282: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3283: (compare:CCFP (match_operand:DF 1 "gen_reg_operand" "f")
3284: (match_operand:DF 2 "gen_reg_operand" "f")))]
3285: ""
3286: "fcmpu %0,%1,%2"
3287: [(set_attr "type" "fpcompare")])
3288:
3289: ;; Now we have the scc insns. We can do some combinations because of the
3290: ;; way the machine works.
3291: ;;
3292: ;; Note that this is probably faster if we can put an insn between the
3293: ;; mfcr and rlinm, but this is tricky. Let's leave it for now.
3294: (define_insn ""
3295: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3296: (match_operator:SI 1 "scc_comparison_operator"
3297: [(match_operand 2 "cc_reg_operand" "y")
3298: (const_int 0)]))]
3299: ""
3300: "%D1mfcr %0\;rlinm %0,%0,%J1,31,31")
3301:
3302: (define_insn ""
3303: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3304: (compare:CC (match_operator:SI 1 "scc_comparison_operator"
3305: [(match_operand 2 "cc_reg_operand" "y")
3306: (const_int 0)])
3307: (const_int 0)))
3308: (set (match_operand:SI 3 "gen_reg_operand" "=r")
3309: (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
3310: ""
3311: "%D1mfcr %3\;rlinm. %3,%3,%J1,30,31"
3312: [(set_attr "type" "delayed_compare")])
3313:
3314: (define_insn ""
3315: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3316: (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3317: [(match_operand 2 "cc_reg_operand" "y")
3318: (const_int 0)])
3319: (match_operand:SI 3 "const_int_operand" "n")))]
3320: ""
3321: "*
3322: {
3323: int is_bit = ccr_bit (operands[1], 1);
3324: int put_bit = 31 - (INTVAL (operands[3]) & 31);
3325: int count;
3326:
3327: if (is_bit >= put_bit)
3328: count = is_bit - put_bit;
3329: else
3330: count = 32 - (put_bit - is_bit);
3331:
3332: operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
3333: operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3334:
3335: return \"%D1mfcr %0\;rlinm %0,%0,%4,%5,%5\";
3336: }")
3337:
3338: (define_insn ""
3339: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3340: (compare:CC
3341: (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3342: [(match_operand 2 "cc_reg_operand" "y")
3343: (const_int 0)])
3344: (match_operand:SI 3 "const_int_operand" "n"))
3345: (const_int 0)))
3346: (set (match_operand:SI 4 "gen_reg_operand" "=r")
3347: (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
3348: (match_dup 3)))]
3349: ""
3350: "*
3351: {
3352: int is_bit = ccr_bit (operands[1], 1);
3353: int put_bit = 31 - (INTVAL (operands[3]) & 31);
3354: int count;
3355:
3356: if (is_bit >= put_bit)
3357: count = is_bit - put_bit;
3358: else
3359: count = 32 - (put_bit - is_bit);
3360:
3361: operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
3362: operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3363:
3364: return \"%D1mfcr %4\;rlinm. %4,%4,%5,%6,%6\";
3365: }"
3366: [(set_attr "type" "delayed_compare")])
3367:
3368: ;; There are some scc insns that can be done directly, without a compare.
3369: ;; These are faster because they don't involve the communications between
3370: ;; the FXU and branch units. In fact, we will be replacing all of the
3371: ;; integer scc insns here or in the portable methods in emit_store_flag.
3372: ;;
3373: ;; Also support (neg (scc ..)) since that construct is used to replace
3374: ;; branches, (plus (scc ..) ..) since that construct is common and
3375: ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
3376: ;; cases where it is no more expensive than (neg (scc ..)).
3377:
3378: ;; Have reload force a constant into a register for the simple insns that
3379: ;; otherwise won't accept constants. We do this because it is faster than
3380: ;; the cmp/mfcr sequence we would otherwise generate.
3381:
3382: (define_insn ""
3383: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3384: (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3385: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
3386: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3387: ""
3388: "@
3389: xor %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0
3390: sfi %3,%1,0\;ae %0,%3,%1
3391: xoril %0,%1,%b2\;sfi %3,%0,0\;ae %0,%3,%0
3392: xoriu %0,%1,%u2\;sfi %3,%0,0\;ae %0,%3,%0
3393: sfi %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0")
3394:
3395: (define_insn ""
3396: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
3397: (compare:CC
3398: (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3399: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3400: (const_int 0)))
3401: (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3402: (eq:SI (match_dup 1) (match_dup 2)))
3403: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3404: ""
3405: "@
3406: xor %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0
3407: sfi %3,%1,0\;ae. %0,%3,%1
3408: xoril %0,%1,%b2\;sfi %3,%0,0\;ae. %0,%3,%0
3409: xoriu %0,%1,%u2\;sfi %3,%0,0\;ae. %0,%3,%0
3410: sfi %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0"
3411: [(set_attr "type" "compare")])
3412:
3413: (define_insn ""
3414: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3415: (plus:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3416: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3417: (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r")))
3418: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3419: ""
3420: "@
3421: xor %4,%1,%2\;sfi %4,%4,0\;aze %0,%3
3422: sfi %4,%1,0\;aze %0,%3
3423: xoril %4,%1,%b2\;sfi %4,%4,0\;aze %0,%3
3424: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze %0,%3
3425: sfi %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
3426:
3427: (define_insn ""
3428: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
3429: (compare:CC
3430: (plus:SI
3431: (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3432: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3433: (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))
3434: (const_int 0)))
3435: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3436: ""
3437: "@
3438: xor %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3
3439: sfi %4,%1,0\;aze. %0,%3
3440: xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %4,%3
3441: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %4,%3
3442: sfi %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
3443: [(set_attr "type" "compare")])
3444:
3445: (define_insn ""
3446: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
3447: (compare:CC
3448: (plus:SI
3449: (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3450: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3451: (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))
3452: (const_int 0)))
3453: (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3454: (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3455: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3456: ""
3457: "@
3458: xor %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3
3459: sfi %4,%1,0\;aze. %4,%3
3460: xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %0,%3
3461: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %0,%3
3462: sfi %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
3463: [(set_attr "type" "compare")])
3464:
3465: (define_insn ""
3466: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3467: (neg:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r,r")
3468: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
3469: ""
3470: "@
3471: xor %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0
3472: ai %0,%1,-1\;sfe %0,%0,%0
3473: xoril %0,%1,%b2\;ai %0,%0,-1\;sfe %0,%0,%0
3474: xoriu %0,%1,%u2\;ai %0,%0,-1\;sfe %0,%0,%0
3475: sfi %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
3476:
3477: ;; This is what (plus (ne X (const_int 0)) Y) looks like.
3478: (define_insn ""
3479: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3480: (plus:SI (lshiftrt:SI
3481: (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
3482: (const_int 31))
3483: (match_operand:SI 2 "gen_reg_operand" "r")))
3484: (clobber (match_scratch:SI 3 "=&r"))]
3485: ""
3486: "ai %3,%1,-1\;aze %0,%2")
3487:
3488: (define_insn ""
3489: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3490: (compare:CC
3491: (plus:SI (lshiftrt:SI
3492: (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
3493: (const_int 31))
3494: (match_operand:SI 2 "gen_reg_operand" "r"))
3495: (const_int 0)))
3496: (clobber (match_scratch:SI 3 "=&r"))]
3497: ""
3498: "ai %3,%1,-1\;aze. %3,%2"
3499: [(set_attr "type" "compare")])
3500:
3501: (define_insn ""
3502: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3503: (compare:CC
3504: (plus:SI (lshiftrt:SI
3505: (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
3506: (const_int 31))
3507: (match_operand:SI 2 "gen_reg_operand" "r"))
3508: (const_int 0)))
3509: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3510: (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
3511: (match_dup 2)))
3512: (clobber (match_scratch:SI 3 "=&r"))]
3513: ""
3514: "ai %3,%1,-1\;aze. %0,%2"
3515: [(set_attr "type" "compare")])
3516:
3517: (define_insn ""
3518: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3519: (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3520: (match_operand:SI 2 "reg_or_short_operand" "r,O")))
3521: (clobber (match_scratch:SI 3 "=r,X"))]
3522: ""
3523: "@
3524: doz %3,%2,%1\;sfi %0,%3,0\;ae %0,%0,%3
3525: ai %0,%1,-1\;aze %0,%0\;sri %0,%0,31")
3526:
3527: (define_insn ""
3528: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
3529: (compare:CC
3530: (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3531: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3532: (const_int 0)))
3533: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3534: (le:SI (match_dup 1) (match_dup 2)))
3535: (clobber (match_scratch:SI 3 "=r,X"))]
3536: ""
3537: "@
3538: doz %3,%2,%1\;sfi %0,%3,0\;ae. %0,%0,%3
3539: ai %0,%1,-1\;aze %0,%0\;sri. %0,%0,31"
3540: [(set_attr "type" "delayed_compare,compare")])
3541:
3542: (define_insn ""
3543: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3544: (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3545: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3546: (match_operand:SI 3 "gen_reg_operand" "r,r")))
3547: (clobber (match_scratch:SI 4 "=&r,&r"))]
3548: ""
3549: "@
3550: doz %4,%2,%1\;sfi %4,%4,0\;aze %0,%3
3551: srai %4,%1,31\;sf %4,%1,%4\;aze %0,%3")
3552:
3553: (define_insn ""
3554: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
3555: (compare:CC
3556: (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3557: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3558: (match_operand:SI 3 "gen_reg_operand" "r,r"))
3559: (const_int 0)))
3560: (clobber (match_scratch:SI 4 "=&r,&r"))]
3561: ""
3562: "@
3563: doz %4,%2,%1\;sfi %4,%4,0\;aze. %4,%3
3564: srai %4,%1,31\;sf %4,%1,%4\;aze. %4,%3"
3565: [(set_attr "type" "compare")])
3566:
3567: (define_insn ""
3568: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
3569: (compare:CC
3570: (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3571: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3572: (match_operand:SI 3 "gen_reg_operand" "r,r"))
3573: (const_int 0)))
3574: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3575: (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3576: (clobber (match_scratch:SI 4 "=&r,&r"))]
3577: ""
3578: "@
3579: doz %4,%2,%1\;sfi %4,%4,0\;aze. %0,%3
3580: srai %4,%1,31\;sf %4,%1,%4\;aze. %0,%3"
3581: [(set_attr "type" "compare")])
3582:
3583: (define_insn ""
3584: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3585: (neg:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3586: (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
3587: ""
3588: "@
3589: doz %0,%2,%1\;ai %0,%0,-1\;sfe %0,%0,%0
3590: ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31")
3591:
3592: (define_insn ""
3593: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3594: (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3595: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3596: ""
3597: "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0")
3598:
3599: (define_insn ""
3600: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3601: (compare:CC
3602: (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3603: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3604: (const_int 0)))
3605: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3606: (leu:SI (match_dup 1) (match_dup 2)))]
3607: ""
3608: "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0"
3609: [(set_attr "type" "compare")])
3610:
3611: (define_insn ""
3612: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3613: (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3614: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3615: (match_operand:SI 3 "gen_reg_operand" "r")))
3616: (clobber (match_scratch:SI 4 "=&r"))]
3617: ""
3618: "sf%I2 %4,%1,%2\;aze %0,%3")
3619:
3620: (define_insn ""
3621: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3622: (compare:CC
3623: (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3624: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3625: (match_operand:SI 3 "gen_reg_operand" "r"))
3626: (const_int 0)))
3627: (clobber (match_scratch:SI 4 "=&r"))]
3628: ""
3629: "sf%I2 %4,%1,%2\;aze. %4,%3"
3630: [(set_attr "type" "compare")])
3631:
3632: (define_insn ""
3633: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3634: (compare:CC
3635: (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3636: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3637: (match_operand:SI 3 "gen_reg_operand" "r"))
3638: (const_int 0)))
3639: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3640: (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3641: (clobber (match_scratch:SI 4 "=&r"))]
3642: ""
3643: "sf%I2 %4,%1,%2\;aze. %0,%3"
3644: [(set_attr "type" "compare")])
3645:
3646: (define_insn ""
3647: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3648: (neg:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3649: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3650: ""
3651: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0")
3652:
3653: (define_insn ""
3654: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3655: (and:SI (neg:SI
3656: (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3657: (match_operand:SI 2 "reg_or_short_operand" "rI")))
3658: (match_operand:SI 3 "gen_reg_operand" "r")))
3659: (clobber (match_scratch:SI 4 "=&r"))]
3660: ""
3661: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4")
3662:
3663: (define_insn ""
3664: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3665: (compare:CC
3666: (and:SI (neg:SI
3667: (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3668: (match_operand:SI 2 "reg_or_short_operand" "rI")))
3669: (match_operand:SI 3 "gen_reg_operand" "r"))
3670: (const_int 0)))
3671: (clobber (match_scratch:SI 4 "=&r"))]
3672: ""
3673: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %4,%3,%4"
3674: [(set_attr "type" "compare")])
3675:
3676: (define_insn ""
3677: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3678: (compare:CC
3679: (and:SI (neg:SI
3680: (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3681: (match_operand:SI 2 "reg_or_short_operand" "rI")))
3682: (match_operand:SI 3 "gen_reg_operand" "r"))
3683: (const_int 0)))
3684: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3685: (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
3686: (clobber (match_scratch:SI 4 "=&r"))]
3687: ""
3688: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %0,%3,%4"
3689: [(set_attr "type" "compare")])
3690:
3691: (define_insn ""
3692: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3693: (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3694: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3695: ""
3696: "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31")
3697:
3698: (define_insn ""
3699: [(set (match_operand:SI 3 "cc_reg_operand" "=x")
3700: (compare:CC
3701: (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3702: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3703: (const_int 0)))
3704: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3705: (lt:SI (match_dup 1) (match_dup 2)))]
3706: ""
3707: "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31"
3708: [(set_attr "type" "delayed_compare")])
3709:
3710: (define_insn ""
3711: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3712: (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3713: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3714: (match_operand:SI 3 "gen_reg_operand" "r")))
3715: (clobber (match_scratch:SI 4 "=&r"))]
3716: ""
3717: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3")
3718:
3719: (define_insn ""
3720: [(set (match_operand:SI 0 "cc_reg_operand" "=x")
3721: (compare:CC
3722: (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3723: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3724: (match_operand:SI 3 "gen_reg_operand" "r"))
3725: (const_int 0)))
3726: (clobber (match_scratch:SI 4 "=&r"))]
3727: ""
3728: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %4,%3"
3729: [(set_attr "type" "compare")])
3730:
3731: (define_insn ""
3732: [(set (match_operand:SI 5 "cc_reg_operand" "=x")
3733: (compare:CC
3734: (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3735: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3736: (match_operand:SI 3 "gen_reg_operand" "r"))
3737: (const_int 0)))
3738: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3739: (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3740: (clobber (match_scratch:SI 4 "=&r"))]
3741: ""
3742: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %0,%3"
3743: [(set_attr "type" "compare")])
3744:
3745: (define_insn ""
3746: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3747: (neg:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3748: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3749: ""
3750: "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31")
3751:
3752: (define_insn ""
3753: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3754: (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3755: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
3756: ""
3757: "@
3758: sf %0,%2,%1\;sfe %0,%0,%0\;neg %0,%0
3759: ai %0,%1,%n2\;sfe %0,%0,%0\;neg %0,%0")
3760:
3761: (define_insn ""
3762: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
3763: (compare:CC
3764: (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3765: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
3766: (const_int 0)))
3767: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3768: (ltu:SI (match_dup 1) (match_dup 2)))]
3769: ""
3770: "@
3771: sf %0,%2,%1\;sfe %0,%0,%0\;neg. %0,%0
3772: ai %0,%1,%n2\;sfe %0,%0,%0\;neg. %0,%0"
3773: [(set_attr "type" "compare")])
3774:
3775: (define_insn ""
3776: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
3777: (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
3778: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3779: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
3780: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3781: ""
3782: "@
3783: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3784: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3785: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3786: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
3787:
3788: (define_insn ""
3789: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
3790: (compare:CC
3791: (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
3792: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3793: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
3794: (const_int 0)))
3795: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3796: ""
3797: "@
3798: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3799: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3800: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3801: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3"
3802: [(set_attr "type" "compare")])
3803:
3804: (define_insn ""
3805: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x")
3806: (compare:CC
3807: (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
3808: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3809: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
3810: (const_int 0)))
3811: (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
3812: (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3813: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3814: ""
3815: "@
3816: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
3817: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
3818: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
3819: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
3820: [(set_attr "type" "compare")])
3821:
3822: (define_insn ""
3823: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3824: (neg:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3825: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
3826: ""
3827: "@
3828: sf %0,%2,%1\;sfe %0,%0,%0
3829: ai %0,%1,%n2\;sfe %0,%0,%0")
3830:
3831: (define_insn ""
3832: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3833: (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3834: (match_operand:SI 2 "reg_or_short_operand" "rI")))
3835: (clobber (match_scratch:SI 3 "=r"))]
3836: ""
3837: "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae %0,%0,%3")
3838:
3839: (define_insn ""
3840: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3841: (compare:CC
3842: (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3843: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3844: (const_int 0)))
3845: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3846: (ge:SI (match_dup 1) (match_dup 2)))
3847: (clobber (match_scratch:SI 3 "=r"))]
3848: ""
3849: "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae. %0,%0,%3"
3850: [(set_attr "type" "compare")])
3851:
3852: (define_insn ""
3853: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3854: (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3855: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3856: (match_operand:SI 3 "gen_reg_operand" "r")))
3857: (clobber (match_scratch:SI 4 "=&r"))]
3858: ""
3859: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
3860:
3861: (define_insn ""
3862: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3863: (compare:CC
3864: (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3865: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3866: (match_operand:SI 3 "gen_reg_operand" "r"))
3867: (const_int 0)))
3868: (clobber (match_scratch:SI 4 "=&r"))]
3869: ""
3870: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
3871: [(set_attr "type" "compare")])
3872:
3873: (define_insn ""
3874: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3875: (compare:CC
3876: (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3877: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3878: (match_operand:SI 3 "gen_reg_operand" "r"))
3879: (const_int 0)))
3880: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3881: (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3882: (clobber (match_scratch:SI 4 "=&r"))]
3883: ""
3884: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
3885: [(set_attr "type" "compare")])
3886:
3887: (define_insn ""
3888: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3889: (neg:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3890: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3891: ""
3892: "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
3893:
3894: ;; This is (and (neg (ge X (const_int 0))) Y).
3895: (define_insn ""
3896: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3897: (and:SI (neg:SI
3898: (lshiftrt:SI
3899: (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
3900: (const_int 31)))
3901: (match_operand:SI 2 "gen_reg_operand" "r")))
3902: (clobber (match_scratch:SI 3 "=&r"))]
3903: ""
3904: "srai %3,%1,31\;andc %0,%2,%3")
3905:
3906: (define_insn ""
3907: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3908: (compare:CC
3909: (and:SI (neg:SI
3910: (lshiftrt:SI
3911: (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
3912: (const_int 31)))
3913: (match_operand:SI 2 "gen_reg_operand" "r"))
3914: (const_int 0)))
3915: (clobber (match_scratch:SI 3 "=&r"))]
3916: ""
3917: "srai %3,%1,31\;andc. %3,%2,%3"
3918: [(set_attr "type" "compare")])
3919:
3920: (define_insn ""
3921: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3922: (compare:CC
3923: (and:SI (neg:SI
3924: (lshiftrt:SI
3925: (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
3926: (const_int 31)))
3927: (match_operand:SI 2 "gen_reg_operand" "r"))
3928: (const_int 0)))
3929: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3930: (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
3931: (const_int 31)))
3932: (match_dup 2)))
3933: (clobber (match_scratch:SI 3 "=&r"))]
3934: ""
3935: "srai %3,%1,31\;andc. %0,%2,%3"
3936: [(set_attr "type" "compare")])
3937:
3938: (define_insn ""
3939: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3940: (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3941: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
3942: ""
3943: "@
3944: sf %0,%2,%1\;cal %0,0(0)\;ae %0,%0,%0
3945: ai %0,%1,%n2\;cal %0,0(0)\;ae %0,%0,%0")
3946:
3947: (define_insn ""
3948: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
3949: (compare:CC
3950: (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3951: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
3952: (const_int 0)))
3953: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3954: (geu:SI (match_dup 1) (match_dup 2)))]
3955: ""
3956: "@
3957: sf %0,%2,%1\;cal %0,0(0)\;ae. %0,%0,%0
3958: ai %0,%1,%n2\;cal %0,0(0)\;ae. %0,%0,%0"
3959: [(set_attr "type" "compare")])
3960:
3961: (define_insn ""
3962: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3963: (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3964: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
3965: (match_operand:SI 3 "gen_reg_operand" "r,r")))
3966: (clobber (match_scratch:SI 4 "=&r,&r"))]
3967: ""
3968: "@
3969: sf %4,%2,%1\;aze %0,%3
3970: ai %4,%1,%n2\;aze %0,%3")
3971:
3972: (define_insn ""
3973: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
3974: (compare:CC
3975: (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3976: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
3977: (match_operand:SI 3 "gen_reg_operand" "r,r"))
3978: (const_int 0)))
3979: (clobber (match_scratch:SI 4 "=&r,&r"))]
3980: ""
3981: "@
3982: sf %4,%2,%1\;aze. %4,%3
3983: ai %4,%1,%n2\;aze. %4,%3"
3984: [(set_attr "type" "compare")])
3985:
3986: (define_insn ""
3987: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
3988: (compare:CC
3989: (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3990: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
3991: (match_operand:SI 3 "gen_reg_operand" "r,r"))
3992: (const_int 0)))
3993: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3994: (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3995: (clobber (match_scratch:SI 4 "=&r,&r"))]
3996: ""
3997: "@
3998: sf %4,%2,%1\;aze. %0,%3
3999: ai %4,%1,%n2\;aze. %4,%3"
4000: [(set_attr "type" "compare")])
4001:
4002: (define_insn ""
4003: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4004: (neg:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4005: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
4006: ""
4007: "@
4008: sf %0,%2,%1\;sfe %0,%0,%0\;nand %0,%0,%0
4009: sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0")
4010:
4011: (define_insn ""
4012: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4013: (and:SI (neg:SI
4014: (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4015: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4016: (match_operand:SI 3 "gen_reg_operand" "r,r")))
4017: (clobber (match_scratch:SI 4 "=&r,&r"))]
4018: ""
4019: "@
4020: sf %4,%2,%1\;sfe %4,%4,%4\;andc %0,%3,%4
4021: ai %4,%1,%n2\;sfe %4,%4,%4\;andc %0,%3,%4")
4022:
4023: (define_insn ""
4024: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4025: (compare:CC
4026: (and:SI (neg:SI
4027: (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4028: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4029: (match_operand:SI 3 "gen_reg_operand" "r,r"))
4030: (const_int 0)))
4031: (clobber (match_scratch:SI 4 "=&r,&r"))]
4032: ""
4033: "@
4034: sf %4,%2,%1\;sfe %4,%4,%4\;andc. %4,%3,%4
4035: ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %4,%3,%4"
4036: [(set_attr "type" "compare")])
4037:
4038: (define_insn ""
4039: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4040: (compare:CC
4041: (and:SI (neg:SI
4042: (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4043: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4044: (match_operand:SI 3 "gen_reg_operand" "r,r"))
4045: (const_int 0)))
4046: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4047: (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
4048: (clobber (match_scratch:SI 4 "=&r,&r"))]
4049: ""
4050: "@
4051: sf %4,%2,%1\;sfe %4,%4,%4\;andc. %0,%3,%4
4052: ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %0,%3,%4"
4053: [(set_attr "type" "compare")])
4054:
4055: (define_insn ""
4056: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4057: (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4058: (const_int 0)))]
4059: ""
4060: "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31")
4061:
4062: (define_insn ""
4063: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4064: (compare:CC
4065: (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4066: (const_int 0))
4067: (const_int 0)))
4068: (set (match_operand:SI 0 "gen_reg_operand" "=r")
4069: (gt:SI (match_dup 1) (const_int 0)))]
4070: ""
4071: "sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31"
4072: [(set_attr "type" "delayed_compare")])
4073:
4074: (define_insn ""
4075: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4076: (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4077: (match_operand:SI 2 "reg_or_short_operand" "r")))]
4078: ""
4079: "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31")
4080:
4081: (define_insn ""
4082: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4083: (compare:CC
4084: (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4085: (match_operand:SI 2 "reg_or_short_operand" "r"))
4086: (const_int 0)))
4087: (set (match_operand:SI 0 "gen_reg_operand" "=r")
4088: (gt:SI (match_dup 1) (match_dup 2)))]
4089: ""
4090: "doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31"
4091: [(set_attr "type" "delayed_compare")])
4092:
4093: (define_insn ""
4094: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4095: (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4096: (const_int 0))
4097: (match_operand:SI 2 "gen_reg_operand" "r")))
4098: (clobber (match_scratch:SI 3 "=&r"))]
4099: ""
4100: "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2")
4101:
4102: (define_insn ""
4103: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4104: (compare:CC
4105: (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4106: (const_int 0))
4107: (match_operand:SI 2 "gen_reg_operand" "r"))
4108: (const_int 0)))
4109: (clobber (match_scratch:SI 3 "=&r"))]
4110: ""
4111: "a %3,%1,%1\;sfe %3,%1,%3\;aze. %0,%2"
4112: [(set_attr "type" "compare")])
4113:
4114: (define_insn ""
4115: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4116: (compare:CC
4117: (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4118: (const_int 0))
4119: (match_operand:SI 2 "gen_reg_operand" "r"))
4120: (const_int 0)))
4121: (set (match_operand:SI 0 "gen_reg_operand" "=r")
4122: (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
4123: (clobber (match_scratch:SI 3 "=&r"))]
4124: ""
4125: "a %3,%1,%1\;sfe %3,%1,%3\;aze. %3,%2"
4126: [(set_attr "type" "compare")])
4127:
4128: (define_insn ""
4129: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4130: (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4131: (match_operand:SI 2 "reg_or_short_operand" "r"))
4132: (match_operand:SI 3 "gen_reg_operand" "r")))
4133: (clobber (match_scratch:SI 4 "=&r"))]
4134: ""
4135: "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3")
4136:
4137: (define_insn ""
4138: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4139: (compare:CC
4140: (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4141: (match_operand:SI 2 "reg_or_short_operand" "r"))
4142: (match_operand:SI 3 "gen_reg_operand" "r"))
4143: (const_int 0)))
4144: (clobber (match_scratch:SI 4 "=&r"))]
4145: ""
4146: "doz %4,%2,%1\;ai %4,%4,-1\;aze. %4,%3"
4147: [(set_attr "type" "compare")])
4148:
4149: (define_insn ""
4150: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4151: (compare:CC
4152: (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4153: (match_operand:SI 2 "reg_or_short_operand" "r"))
4154: (match_operand:SI 3 "gen_reg_operand" "r"))
4155: (const_int 0)))
4156: (set (match_operand:SI 0 "gen_reg_operand" "=r")
4157: (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4158: (clobber (match_scratch:SI 4 "=&r"))]
4159: ""
4160: "doz %4,%2,%1\;ai %4,%4,-1\;aze. %0,%3"
4161: [(set_attr "type" "compare")])
4162:
4163: (define_insn ""
4164: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4165: (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4166: (const_int 0))))]
4167: ""
4168: "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31")
4169:
4170: (define_insn ""
4171: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4172: (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4173: (match_operand:SI 2 "reg_or_short_operand" "r"))))]
4174: ""
4175: "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31")
4176:
4177: (define_insn ""
4178: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4179: (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
4180: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
4181: ""
4182: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0")
4183:
4184: (define_insn ""
4185: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4186: (compare:CC
4187: (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
4188: (match_operand:SI 2 "reg_or_short_operand" "rI"))
4189: (const_int 0)))
4190: (set (match_operand:SI 0 "gen_reg_operand" "=r")
4191: (gtu:SI (match_dup 1) (match_dup 2)))]
4192: ""
4193: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0"
4194: [(set_attr "type" "compare")])
4195:
4196: (define_insn ""
4197: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4198: (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4199: (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4200: (match_operand:SI 3 "reg_or_short_operand" "r,I")))
4201: (clobber (match_scratch:SI 4 "=&r,&r"))]
4202: ""
4203: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
4204:
4205: (define_insn ""
4206: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4207: (compare:CC
4208: (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4209: (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4210: (match_operand:SI 3 "reg_or_short_operand" "r,I"))
4211: (const_int 0)))
4212: (clobber (match_scratch:SI 4 "=&r,&r"))]
4213: ""
4214: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3"
4215: [(set_attr "type" "compare")])
4216:
4217: (define_insn ""
4218: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4219: (compare:CC
4220: (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4221: (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4222: (match_operand:SI 3 "reg_or_short_operand" "r,I"))
4223: (const_int 0)))
4224: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4225: (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4226: (clobber (match_scratch:SI 4 "=&r,&r"))]
4227: ""
4228: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
4229: [(set_attr "type" "compare")])
4230:
4231: (define_insn ""
4232: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4233: (neg:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
4234: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4235: ""
4236: "sf%I2 %0,%1,%2\;sfe %0,%0,%0")
4237:
4238: ;; Define both directions of branch and return. If we need a reload
4239: ;; register, we'd rather use CR0 since it is much easier to copy a
4240: ;; register CC value to there.
4241:
4242: (define_insn ""
4243: [(set (pc)
4244: (if_then_else (match_operator 1 "branch_comparison_operator"
4245: [(match_operand 2
4246: "cc_reg_operand" "x,?y")
4247: (const_int 0)])
4248: (label_ref (match_operand 0 "" ""))
4249: (pc)))]
4250: ""
4251: "%C1bc %t1,%j1,%0")
4252:
4253: (define_insn ""
4254: [(set (pc)
4255: (if_then_else (match_operator 0 "branch_comparison_operator"
4256: [(match_operand 1
4257: "cc_reg_operand" "x,?y")
4258: (const_int 0)])
4259: (return)
4260: (pc)))]
4261: "direct_return ()"
4262: "%C0bcr %t0,%j0")
4263:
4264: (define_insn ""
4265: [(set (pc)
4266: (if_then_else (match_operator 1 "branch_comparison_operator"
4267: [(match_operand 2
4268: "cc_reg_operand" "x,?y")
4269: (const_int 0)])
4270: (pc)
4271: (label_ref (match_operand 0 "" ""))))]
4272: ""
4273: "%C1bc %T1,%j1,%0")
4274:
4275: (define_insn ""
4276: [(set (pc)
4277: (if_then_else (match_operator 0 "branch_comparison_operator"
4278: [(match_operand 1
4279: "cc_reg_operand" "x,?y")
4280: (const_int 0)])
4281: (pc)
4282: (return)))]
4283: "direct_return ()"
4284: "%C0bcr %T0,%j0")
4285:
4286: ;; Unconditional branch and return.
4287:
4288: (define_insn "jump"
4289: [(set (pc)
4290: (label_ref (match_operand 0 "" "")))]
4291: ""
4292: "b %l0")
4293:
4294: (define_insn "return"
4295: [(return)]
4296: "direct_return ()"
4297: "br")
4298:
4299: (define_insn "indirect_jump"
4300: [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
4301: ""
4302: "@
4303: bctr
4304: br")
4305:
4306: ;; Table jump for switch statements:
4307: (define_expand "tablejump"
4308: [(set (match_dup 3)
4309: (plus:SI (match_operand:SI 0 "" "")
4310: (match_dup 2)))
4311: (parallel [(set (pc) (match_dup 3))
4312: (use (label_ref (match_operand 1 "" "")))])]
4313: ""
4314: "
4315: { operands[0] = force_reg (SImode, operands[0]);
4316: operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
4317: operands[3] = gen_reg_rtx (SImode);
4318: }")
4319:
4320: (define_insn ""
4321: [(set (pc)
4322: (match_operand:SI 0 "register_operand" "c,r"))
4323: (use (label_ref (match_operand 1 "" "")))]
4324: ""
4325: "@
4326: bctr
4327: br")
4328:
4329: (define_insn "nop"
4330: [(const_int 0)]
4331: ""
4332: "cror 0,0,0")
4333:
4334: ;; Define the subtract-one-and-jump insns.
4335: ;; We need to be able to do this for any operand, including MEM, or we
4336: ;; will cause reload to blow up since we don't allow output reloads on
4337: ;; JUMP_INSNs.
4338: (define_insn ""
4339: [(set (pc)
4340: (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r")
4341: (const_int 1))
4342: (label_ref (match_operand 2 "" ""))
4343: (pc)))
4344: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4345: (plus:SI (match_dup 1) (const_int -1)))
4346: (clobber (match_scratch:CC 3 "=X,&x,&x"))
4347: (clobber (match_scratch:SI 4 "=X,X,r"))]
4348: ""
4349: "@
4350: bdn %l2
4351: #
4352: #")
4353:
4354: ;; Similar, but we can use GE since we have a REG_NOTES.
4355: (define_insn ""
4356: [(set (pc)
4357: (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r")
4358: (const_int 0))
4359: (label_ref (match_operand 2 "" ""))
4360: (pc)))
4361: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4362: (plus:SI (match_dup 1) (const_int -1)))
4363: (clobber (match_scratch:CC 3 "=X,&x,&X"))
4364: (clobber (match_scratch:SI 4 "=X,X,r"))]
4365: "find_reg_note (insn, REG_NONNEG, 0)"
4366: "@
4367: bdn %l2
4368: #
4369: #")
4370:
4371: (define_insn ""
4372: [(set (pc)
4373: (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r")
4374: (const_int 1))
4375: (label_ref (match_operand 2 "" ""))
4376: (pc)))
4377: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4378: (plus:SI (match_dup 1) (const_int -1)))
4379: (clobber (match_scratch:CC 3 "=X,&x,&x"))
4380: (clobber (match_scratch:SI 4 "=X,X,r"))]
4381: ""
4382: "@
4383: bdz %l2
4384: #
4385: #")
4386:
4387: (define_split
4388: [(set (pc)
4389: (if_then_else (match_operator 2 "comparison_operator"
4390: [(match_operand:SI 1 "gen_reg_operand" "")
4391: (const_int 1)])
4392: (match_operand 5 "" "")
4393: (match_operand 6 "" "")))
4394: (set (match_operand:SI 0 "gen_reg_operand" "")
4395: (plus:SI (match_dup 1) (const_int -1)))
4396: (clobber (match_scratch:CC 3 ""))
4397: (clobber (match_scratch:SI 4 ""))]
4398: "reload_completed"
4399: [(parallel [(set (match_dup 3)
4400: (compare:CC (plus:SI (match_dup 1) (const_int -1))
4401: (const_int 0)))
4402: (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
4403: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4404: "
4405: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
4406: const0_rtx); }")
4407:
4408: (define_split
4409: [(set (pc)
4410: (if_then_else (match_operator 2 "comparison_operator"
4411: [(match_operand:SI 1 "gen_reg_operand" "")
4412: (const_int 1)])
4413: (match_operand 5 "" "")
4414: (match_operand 6 "" "")))
4415: (set (match_operand:SI 0 "general_operand" "")
4416: (plus:SI (match_dup 1) (const_int -1)))
4417: (clobber (match_scratch:CC 3 ""))
4418: (clobber (match_scratch:SI 4 ""))]
4419: "reload_completed && ! gen_reg_operand (operands[0], SImode)"
4420: [(parallel [(set (match_dup 3)
4421: (compare:CC (plus:SI (match_dup 1) (const_int -1))
4422: (const_int 0)))
4423: (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))])
4424: (set (match_dup 0) (match_dup 4))
4425: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4426: "
4427: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
4428: const0_rtx); }")
4429:
4430: ;;- Local variables:
4431: ;;- mode:emacs-lisp
4432: ;;- comment-start: ";;- "
4433: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
4434: ;;- eval: (modify-syntax-entry ?[ "(]")
4435: ;;- eval: (modify-syntax-entry ?] ")[")
4436: ;;- eval: (modify-syntax-entry ?{ "(}")
4437: ;;- eval: (modify-syntax-entry ?} "){")
4438: ;;- End:
This archive runs on limited infrastructure. Preserving old code on modern bandwidth. Automated agents are requested to crawl responsibly.