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1.1 root 1: ;;- Machine description for IBM RISC System 6000 (POWER) for GNU C compiler
2: ;; Copyright (C) 1990, 1991 Free Software Foundation, Inc.
3: ;; Contributed by Richard Kenner ([email protected])
4:
5: ;; This file is part of GNU CC.
6:
7: ;; GNU CC is free software; you can redistribute it and/or modify
8: ;; it under the terms of the GNU General Public License as published by
9: ;; the Free Software Foundation; either version 2, or (at your option)
10: ;; any later version.
11:
12: ;; GNU CC is distributed in the hope that it will be useful,
13: ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14: ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15: ;; GNU General Public License for more details.
16:
17: ;; You should have received a copy of the GNU General Public License
18: ;; along with GNU CC; see the file COPYING. If not, write to
19: ;; the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
20:
21: ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
22:
23: ;; Define an insn type attribute. This is used in function unit delay
24: ;; computations.
1.1.1.2 ! root 25: (define_attr "type" "load,integer,fp,compare,delayed_compare,fpcompare,mtlr"
1.1 root 26: (const_string "integer"))
27:
28: ;; Memory delivers its result in two cycles.
29: (define_function_unit "memory" 1 0 (eq_attr "type" "load") 2 0)
30:
31: ;; We consider floating-point insns to deliver their result in two cycles
32: ;; to try to intersperse integer and FP operations.
33: (define_function_unit "fp" 1 0 (eq_attr "type" "fp,fpcompare") 2 0)
34:
35: ;; Most integer comparisons are ready in four cycles (a stall of three).
36: (define_function_unit "compare" 1 0 (eq_attr "type" "compare") 4 0)
37:
38: ;; Some integer comparisons aren't ready for five cycles (a stall of four).
39: (define_function_unit "compare" 1 0 (eq_attr "type" "delayed_compare") 5 0)
40:
41: ;; Floating-point comparisons take eight cycles.
42: (define_function_unit "compare" 1 0 (eq_attr "type" "fpcompare") 8 0)
1.1.1.2 ! root 43:
! 44: ;; Branches on LR cannot be done until five cycles after LR is set.
! 45: (define_function_unit "branch" 1 0 (eq_attr "type" "mtlr") 5 0)
1.1 root 46:
47: ;; Start with fixed-point load and store insns. Here we put only the more
48: ;; complex forms. Basic data transfer is done later.
49:
50: (define_expand "zero_extendqisi2"
51: [(set (match_operand:SI 0 "gen_reg_operand" "")
52: (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "")))]
53: ""
54: "")
55:
56: (define_insn ""
57: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
58: (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
59: ""
60: "@
61: lbz%U1%X1 %0,%1
62: rlinm %0,%1,0,24,31"
63: [(set_attr "type" "load,*")])
64:
65: (define_insn ""
66: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
67: (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r"))
68: (const_int 0)))
69: (clobber (match_scratch:SI 2 "=r"))]
70: ""
71: "andil. %2,%1,255"
72: [(set_attr "type" "compare")])
73:
74: (define_insn ""
75: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
76: (compare:CC (zero_extend:SI (match_operand:QI 1 "gen_reg_operand" "r"))
77: (const_int 0)))
78: (set (match_operand:SI 0 "gen_reg_operand" "=r")
79: (zero_extend:SI (match_dup 1)))]
80: ""
81: "andil. %0,%1,255"
82: [(set_attr "type" "compare")])
83:
84: (define_expand "zero_extendqihi2"
85: [(set (match_operand:HI 0 "gen_reg_operand" "")
86: (zero_extend:HI (match_operand:QI 1 "gen_reg_operand" "")))]
87: ""
88: "")
89:
90: (define_insn ""
91: [(set (match_operand:HI 0 "gen_reg_operand" "=r,r")
92: (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))]
93: ""
94: "@
95: lbz%U1%X1 %0,%1
96: rlinm %0,%1,0,24,31"
97: [(set_attr "type" "load,*")])
98:
99: (define_expand "zero_extendhisi2"
100: [(set (match_operand:SI 0 "gen_reg_operand" "r")
101: (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
102: ""
103: "")
104:
105: (define_insn ""
106: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
107: (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
108: ""
109: "@
110: lhz%U1%X1 %0,%1
111: rlinm %0,%1,0,16,31"
112: [(set_attr "type" "load,*")])
113:
114: (define_insn ""
115: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
116: (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
117: (const_int 0)))
118: (clobber (match_scratch:SI 2 "=r"))]
119: ""
120: "andil. %2,%1,65535"
121: [(set_attr "type" "compare")])
122:
123: (define_insn ""
124: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
125: (compare:CC (zero_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
126: (const_int 0)))
127: (set (match_operand:SI 0 "gen_reg_operand" "=r")
128: (zero_extend:SI (match_dup 1)))]
129: ""
130: "andil. %0,%1,65535"
131: [(set_attr "type" "compare")])
132:
133: (define_expand "extendhisi2"
134: [(set (match_operand:SI 0 "gen_reg_operand" "")
135: (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "")))]
136: ""
137: "")
138:
139: (define_insn ""
140: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
141: (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))]
142: ""
143: "@
144: lha%U1%X1 %0,%1
145: exts %0,%1"
146: [(set_attr "type" "load,*")])
147:
148: (define_insn ""
149: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
150: (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
151: (const_int 0)))
152: (clobber (match_scratch:SI 2 "=r"))]
153: ""
154: "exts. %2,%1"
155: [(set_attr "type" "compare")])
156:
157: (define_insn ""
158: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
159: (compare:CC (sign_extend:SI (match_operand:HI 1 "gen_reg_operand" "r"))
160: (const_int 0)))
161: (set (match_operand:SI 0 "gen_reg_operand" "=r")
162: (sign_extend:SI (match_dup 1)))]
163: ""
164: "exts. %0,%1"
165: [(set_attr "type" "compare")])
166:
167: ;; Fixed-point arithmetic insns.
168: (define_insn ""
169: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
170: (plus:SI (match_operand:SI 1 "gen_reg_operand" "%r,b")
171: (match_operand:SI 2 "add_operand" "rI,J")))]
172: ""
173: "@
174: a%I2 %0,%1,%2
175: cau %0,%1,%u2")
176:
177: (define_insn ""
178: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
179: (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r")
180: (match_operand:SI 2 "reg_or_short_operand" "rI"))
181: (const_int 0)))
182: (clobber (match_scratch:SI 3 "=r"))]
183: ""
184: "a%I2. %3,%1,%2"
185: [(set_attr "type" "compare")])
186:
187: (define_insn ""
188: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
189: (compare:CC (plus:SI (match_operand:SI 1 "gen_reg_operand" "r")
190: (match_operand:SI 2 "reg_or_short_operand" "rI"))
191: (const_int 0)))
192: (set (match_operand:SI 0 "gen_reg_operand" "=r")
193: (plus:SI (match_dup 1) (match_dup 2)))]
194: ""
195: "a%I2. %0,%1,%2"
196: [(set_attr "type" "compare")])
197:
198: (define_expand "addsi3"
199: [(set (match_operand:SI 0 "gen_reg_operand" "")
200: (plus:SI (match_operand:SI 1 "gen_reg_operand" "")
201: (match_operand:SI 2 "reg_or_cint_operand" "")))]
202: ""
203: "
204: {
205: if (GET_CODE (operands[2]) == CONST_INT
206: && (unsigned) (INTVAL (operands[2]) + 0x8000) >= 0x10000
207: && (INTVAL (operands[2]) & 0xffff) != 0)
208: {
209: int low = INTVAL (operands[2]) & 0xffff;
210: int high = (unsigned) INTVAL (operands[2]) >> 16;
211:
212: if (low & 0x8000)
213: high++, low |= 0xffff0000;
214:
215: emit_insn (gen_addsi3 (operands[0], operands[1],
216: gen_rtx (CONST_INT, VOIDmode, high << 16)));
217: operands[1] = operands[0];
218: operands[2] = gen_rtx (CONST_INT, VOIDmode, low);
219: }
220: }")
221:
222: (define_insn "one_cmplsi2"
223: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
224: (not:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
225: ""
226: "sfi %0,%1,-1")
227:
228: (define_insn ""
229: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
230: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "r,I")
231: (match_operand:SI 2 "gen_reg_operand" "r,r")))]
232: ""
233: "@
234: sf %0,%2,%1
235: sfi %0,%2,%1")
236:
237: (define_insn ""
238: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
239: (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r")
240: (match_operand:SI 2 "gen_reg_operand" "r"))
241: (const_int 0)))
242: (clobber (match_scratch:SI 3 "=r"))]
243: ""
244: "sf. %3,%2,%1"
245: [(set_attr "type" "compare")])
246:
247: (define_insn ""
248: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
249: (compare:CC (minus:SI (match_operand:SI 1 "gen_reg_operand" "r")
250: (match_operand:SI 2 "gen_reg_operand" "r"))
251: (const_int 0)))
252: (set (match_operand:SI 0 "gen_reg_operand" "=r")
253: (minus:SI (match_dup 1) (match_dup 2)))]
254: ""
255: "sf. %0,%2,%1"
256: [(set_attr "type" "compare")])
257:
258: (define_expand "subsi3"
259: [(set (match_operand:SI 0 "gen_reg_operand" "")
260: (minus:SI (match_operand:SI 1 "reg_or_short_operand" "")
261: (match_operand:SI 2 "reg_or_cint_operand" "")))]
262: ""
263: "
264: {
265: if (GET_CODE (operands[2]) == CONST_INT)
266: {
267: emit_insn (gen_addsi3 (operands[0], operands[1],
268: negate_rtx (SImode, operands[2])));
269: DONE;
270: }
271: }")
272:
273: ;; For SMIN, SMAX, UMIN, and UMAX, we use DEFINE_EXPAND's that involve a doz[i]
274: ;; instruction and some auxiliary computations. Then we just have a single
275: ;; DEFINE_INSN for doz[i].
276:
277: (define_expand "sminsi3"
278: [(set (match_dup 3)
279: (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "")
280: (match_operand:SI 2 "reg_or_short_operand" ""))
281: (const_int 0)
282: (minus:SI (match_dup 2) (match_dup 1))))
283: (set (match_operand:SI 0 "gen_reg_operand" "")
284: (minus:SI (match_dup 2) (match_dup 3)))]
285: ""
286: "
287: { operands[3] = gen_reg_rtx (SImode); }")
288:
289: (define_expand "smaxsi3"
290: [(set (match_dup 3)
291: (if_then_else:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "")
292: (match_operand:SI 2 "reg_or_short_operand" ""))
293: (const_int 0)
294: (minus:SI (match_dup 2) (match_dup 1))))
295: (set (match_operand:SI 0 "gen_reg_operand" "")
296: (plus:SI (match_dup 3) (match_dup 1)))]
297: ""
298: "
299: { operands[3] = gen_reg_rtx (SImode); }")
300:
301: (define_expand "uminsi3"
302: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
303: (const_int -2147483648)))
304: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "")
305: (const_int -2147483648)))
306: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
307: (const_int 0)
308: (minus:SI (match_dup 4) (match_dup 3))))
309: (set (match_operand:SI 0 "gen_reg_operand" "")
310: (minus:SI (match_dup 2) (match_dup 3)))]
311: ""
312: "
313: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
314:
315: (define_expand "umaxsi3"
316: [(set (match_dup 3) (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
317: (const_int -2147483648)))
318: (set (match_dup 4) (xor:SI (match_operand:SI 2 "gen_reg_operand" "")
319: (const_int -2147483648)))
320: (set (match_dup 3) (if_then_else:SI (gt (match_dup 3) (match_dup 4))
321: (const_int 0)
322: (minus:SI (match_dup 4) (match_dup 3))))
323: (set (match_operand:SI 0 "gen_reg_operand" "")
324: (plus:SI (match_dup 3) (match_dup 1)))]
325: ""
326: "
327: { operands[3] = gen_reg_rtx (SImode); operands[4] = gen_reg_rtx (SImode); }")
328:
329: (define_insn ""
330: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
331: (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
1.1.1.2 ! root 332: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1 root 333: (const_int 0)
334: (minus:SI (match_dup 2) (match_dup 1))))]
335: ""
336: "doz%I2 %0,%1,%2")
337:
338: (define_insn ""
339: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
340: (compare:CC
341: (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
1.1.1.2 ! root 342: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1 root 343: (const_int 0)
344: (minus:SI (match_dup 2) (match_dup 1)))
345: (const_int 0)))
346: (clobber (match_scratch:SI 3 "=r"))]
347: ""
348: "doz%I2. %3,%1,%2"
349: [(set_attr "type" "delayed_compare")])
350:
351: (define_insn ""
352: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
353: (compare:CC
354: (if_then_else:SI (gt (match_operand:SI 1 "gen_reg_operand" "r")
1.1.1.2 ! root 355: (match_operand:SI 2 "reg_or_short_operand" "rI"))
1.1 root 356: (const_int 0)
357: (minus:SI (match_dup 2) (match_dup 1)))
358: (const_int 0)))
359: (set (match_operand:SI 0 "gen_reg_operand" "=r")
360: (if_then_else:SI (gt (match_dup 1) (match_dup 2))
361: (const_int 0)
362: (minus:SI (match_dup 2) (match_dup 1))))]
363: ""
364: "doz%I2. %0,%1,%2"
365: [(set_attr "type" "delayed_compare")])
366:
367: ;; We don't need abs with condition code because such comparisons should
368: ;; never be done.
369: (define_insn "abssi2"
370: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
371: (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
372: ""
373: "abs %0,%1")
374:
375: (define_insn ""
376: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
377: (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r"))))]
378: ""
379: "nabs %0,%1")
380:
381: (define_insn "negsi2"
382: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
383: (neg:SI (match_operand:SI 1 "gen_reg_operand" "r")))]
384: ""
385: "neg %0,%1")
386:
387: (define_insn ""
388: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
389: (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r"))
390: (const_int 0)))
391: (clobber (match_scratch:SI 2 "=r"))]
392: ""
393: "neg. %2,%1"
394: [(set_attr "type" "compare")])
395:
396: (define_insn ""
397: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
398: (compare:CC (neg:SI (match_operand:SI 1 "gen_reg_operand" "r"))
399: (const_int 0)))
400: (set (match_operand:SI 0 "gen_reg_operand" "=r")
401: (neg:SI (match_dup 1)))]
402: ""
403: "neg. %0,%1"
404: [(set_attr "type" "compare")])
405:
406: (define_insn "ffssi2"
407: [(set (match_operand:SI 0 "register_operand" "=&r")
408: (ffs:SI (match_operand:SI 1 "register_operand" "r")))]
409: ""
410: "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi %0,%0,32")
411:
412: ;; There is no need for (set (condition) (compare (ffs) 0)) because that
413: ;; can be simplified to an ordinary comparison. A parallel set and compare
414: ;; might be used, so include it.
415:
416: (define_insn ""
417: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
418: (compare:CC (ffs:SI (match_operand:SI 1 "register_operand" "r"))
419: (const_int 0)))
420: (set (match_operand:SI 0 "register_operand" "=&r")
421: (ffs:SI (match_dup 1)))]
422: ""
423: "neg %0,%1\;and %0,%0,%1\;cntlz %0,%0\;sfi. %0,%0,32"
424: [(set_attr "type" "compare")])
425:
426: (define_insn "mulsi3"
427: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
428: (mult:SI (match_operand:SI 1 "gen_reg_operand" "%r,r")
429: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
430: (clobber (match_scratch:SI 3 "=q,q"))]
431: ""
432: "@
433: muls %0,%1,%2
434: muli %0,%1,%2")
435:
436: (define_insn ""
437: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
438: (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r")
439: (match_operand:SI 2 "gen_reg_operand" "r"))
440: (const_int 0)))
441: (clobber (match_scratch:SI 3 "=r"))
442: (clobber (match_scratch:SI 4 "=q"))]
443: ""
444: "muls. %3,%1,%2"
445: [(set_attr "type" "delayed_compare")])
446:
447: (define_insn ""
448: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
449: (compare:CC (mult:SI (match_operand:SI 1 "gen_reg_operand" "r")
450: (match_operand:SI 2 "gen_reg_operand" "r"))
451: (const_int 0)))
452: (set (match_operand:SI 0 "gen_reg_operand" "=r")
453: (mult:SI (match_dup 1) (match_dup 2)))
454: (clobber (match_scratch:SI 4 "=q"))]
455: ""
456: "muls. %0,%1,%2"
457: [(set_attr "type" "delayed_compare")])
458:
459: ;; Operand 1 is divided by operand 2; quotient goes to operand
460: ;; 0 and remainder to operand 3.
461: ;; ??? At some point, see what, if anything, we can do about if (x % y == 0).
462:
463: (define_insn "divmodsi4"
464: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
465: (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
466: (match_operand:SI 2 "gen_reg_operand" "r")))
467: (set (match_operand:SI 3 "gen_reg_operand" "=q")
468: (mod:SI (match_dup 1) (match_dup 2)))]
469: ""
470: "divs %0,%1,%2")
471:
472: ;; For powers of two we can do srai/aze for divide and then adjust for
473: ;; modulus. If it isn't a power of two, FAIL so divmodsi4 will be used.
474: (define_expand "divsi3"
475: [(set (match_operand:SI 0 "gen_reg_operand" "")
476: (div:SI (match_operand:SI 1 "gen_reg_operand" "")
477: (match_operand:SI 2 "reg_or_cint_operand" "")))]
478: ""
479: "
480: {
481: if (GET_CODE (operands[2]) != CONST_INT
482: || exact_log2 (INTVAL (operands[2])) < 0)
483: FAIL;
484: }")
485:
486: (define_expand "modsi3"
487: [(set (match_dup 3)
488: (div:SI (match_operand:SI 1 "gen_reg_operand" "")
489: (match_operand:SI 2 "reg_or_cint_operand" "")))
490: (parallel [(set (match_dup 4) (ashift:SI (match_dup 3) (match_dup 5)))
491: (clobber (scratch:SI))])
492: (set (match_operand:SI 0 "gen_reg_operand" "")
493: (minus:SI (match_dup 1) (match_dup 4)))]
494: ""
495: "
496: {
497: int i = exact_log2 (INTVAL (operands[2]));
498:
499: if (GET_CODE (operands[2]) != CONST_INT || i < 0)
500: FAIL;
501:
502: operands[3] = gen_reg_rtx (SImode);
503: operands[4] = gen_reg_rtx (SImode);
504: operands[5] = gen_rtx (CONST_INT, VOIDmode, i);
505: }")
506:
507: (define_insn ""
508: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
509: (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
510: (match_operand:SI 2 "const_int_operand" "N")))]
511: "exact_log2 (INTVAL (operands[2])) >= 0"
512: "srai %0,%1,%p2\;aze %0,%0")
513:
514: (define_insn ""
515: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
516: (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
517: (match_operand:SI 2 "const_int_operand" "N")))
518: (clobber (match_scratch:SI 3 "=r"))]
519: "exact_log2 (INTVAL (operands[2])) >= 0"
520: "srai %3,%1,%p2\;aze. %3,%3"
521: [(set_attr "type" "compare")])
522:
523: (define_insn ""
524: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
525: (div:SI (match_operand:SI 1 "gen_reg_operand" "r")
526: (match_operand:SI 2 "const_int_operand" "N")))
527: (set (match_operand:SI 0 "gen_reg_operand" "=r")
528: (div:SI (match_dup 1) (match_dup 2)))]
529: "exact_log2 (INTVAL (operands[2])) >= 0"
530: "srai %0,%1,%p2\;aze. %0,%0"
531: [(set_attr "type" "compare")])
532:
533: (define_insn ""
534: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
535: (udiv:SI
536: (plus:DI (lshift:DI
537: (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
538: (const_int 32))
539: (zero_extend:DI (match_operand:SI 2 "register_operand" "*q")))
540: (match_operand:SI 3 "gen_reg_operand" "r")))
541: (set (match_operand:SI 4 "register_operand" "=*q")
542: (umod:SI
543: (plus:DI (lshift:DI
544: (zero_extend:DI (match_dup 1)) (const_int 32))
545: (zero_extend:DI (match_dup 2)))
546: (match_dup 3)))]
547:
548: ""
549: "div %0,%1,%3")
550:
551: ;; To do unsigned divide we handle the cases of the divisor looking like a
552: ;; negative number. If it is a constant that is less than 2**31, we don't
553: ;; have to worry about the branches. So make a few subroutines here.
554: ;;
555: ;; First comes the normal case.
556: (define_expand "udivmodsi4_normal"
557: [(set (match_dup 4) (const_int 0))
558: (parallel [(set (match_operand:SI 0 "" "")
559: (udiv:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
560: (const_int 32))
561: (zero_extend:DI (match_operand:SI 1 "" "")))
562: (match_operand:SI 2 "" "")))
563: (set (match_operand:SI 3 "" "")
564: (umod:SI (plus:DI (lshift:DI (zero_extend:DI (match_dup 4))
565: (const_int 32))
566: (zero_extend:DI (match_dup 1)))
567: (match_dup 2)))])]
568: ""
569: "
570: { operands[4] = gen_reg_rtx (SImode); }")
571:
572: ;; This handles the branches.
573: (define_expand "udivmodsi4_tests"
574: [(set (match_operand:SI 0 "" "") (const_int 0))
575: (set (match_operand:SI 3 "" "") (match_operand:SI 1 "" ""))
576: (set (match_dup 5) (compare:CCUNS (match_dup 1) (match_operand:SI 2 "" "")))
577: (set (pc) (if_then_else (ltu (match_dup 5) (const_int 0))
578: (label_ref (match_operand:SI 4 "" "")) (pc)))
579: (set (match_dup 0) (const_int 1))
580: (set (match_dup 3) (minus:SI (match_dup 1) (match_dup 2)))
581: (set (match_dup 6) (compare:CC (match_dup 2) (const_int 0)))
582: (set (pc) (if_then_else (lt (match_dup 6) (const_int 0))
583: (label_ref (match_dup 4)) (pc)))]
584: ""
585: "
586: { operands[5] = gen_reg_rtx (CCUNSmode);
587: operands[6] = gen_reg_rtx (CCmode);
588: }")
589:
590: (define_expand "udivmodsi4"
591: [(parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
592: (udiv:SI (match_operand:SI 1 "gen_reg_operand" "")
593: (match_operand:SI 2 "reg_or_cint_operand" "")))
594: (set (match_operand:SI 3 "gen_reg_operand" "")
595: (umod:SI (match_dup 1) (match_dup 2)))])]
596: ""
597: "
598: {
599: rtx label = 0;
600:
601: if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) < 0)
602: {
603: operands[2] = force_reg (SImode, operands[2]);
604: label = gen_label_rtx ();
605: emit (gen_udivmodsi4_tests (operands[0], operands[1], operands[2],
606: operands[3], label));
607: }
608: else
609: operands[2] = force_reg (SImode, operands[2]);
610:
611: emit (gen_udivmodsi4_normal (operands[0], operands[1], operands[2],
612: operands[3]));
613: if (label)
614: emit_label (label);
615:
616: DONE;
617: }")
618:
619: (define_insn "andsi3"
620: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
621: (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
622: (match_operand:SI 2 "and_operand" "?r,L,K,J")))
623: (clobber (match_scratch:CC 3 "=X,X,x,x"))]
624: ""
625: "@
626: and %0,%1,%2
627: rlinm %0,%1,0,%m2,%M2
628: andil. %0,%1,%b2
629: andiu. %0,%1,%u2")
630:
631: (define_insn ""
632: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
633: (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
634: (match_operand:SI 2 "and_operand" "r,K,J,L"))
635: (const_int 0)))
636: (clobber (match_scratch:SI 3 "=r,r,r,r"))]
637: ""
638: "@
639: and. %3,%1,%2
640: andil. %3,%1,%b2
641: andiu. %3,%1,%u2
642: rlinm. %3,%1,0,%m2,%M2"
643: [(set_attr "type" "compare,compare,compare,delayed_compare")])
644:
645: (define_insn ""
646: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x")
647: (compare:CC (and:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r")
648: (match_operand:SI 2 "and_operand" "r,K,J,L"))
649: (const_int 0)))
650: (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
651: (and:SI (match_dup 1) (match_dup 2)))]
652: ""
653: "@
654: and. %0,%1,%2
655: andil. %0,%1,%b2
656: andiu. %0,%1,%u2
657: rlinm. %0,%1,0,%m2,%M2"
658: [(set_attr "type" "compare,compare,compare,delayed_compare")])
659:
660: (define_insn ""
661: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r")
662: (ior:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r")
663: (match_operand:SI 2 "logical_operand" "r,K,J")))]
664: ""
665: "@
666: or %0,%1,%2
667: oril %0,%1,%b2
668: oriu %0,%1,%u2")
669:
670: (define_insn ""
671: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
672: (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r")
673: (match_operand:SI 2 "gen_reg_operand" "r"))
674: (const_int 0)))
675: (clobber (match_scratch:SI 3 "=r"))]
676: ""
677: "or. %3,%1,%2"
678: [(set_attr "type" "compare")])
679:
680: (define_insn ""
681: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
682: (compare:CC (ior:SI (match_operand:SI 1 "gen_reg_operand" "r")
683: (match_operand:SI 2 "gen_reg_operand" "r"))
684: (const_int 0)))
685: (set (match_operand:SI 0 "gen_reg_operand" "=r")
686: (ior:SI (match_dup 1) (match_dup 2)))]
687: ""
688: "or. %0,%1,%2"
689: [(set_attr "type" "compare")])
690:
691: (define_expand "iorsi3"
692: [(set (match_operand:SI 0 "gen_reg_operand" "")
693: (ior:SI (match_operand:SI 1 "gen_reg_operand" "")
694: (match_operand:SI 2 "reg_or_cint_operand" "")))]
695: ""
696: "
697: {
698: if (GET_CODE (operands[2]) == CONST_INT
699: && ! logical_operand (operands[2], SImode))
700: {
701: emit_insn (gen_iorsi3 (operands[0], operands[1],
702: gen_rtx (CONST_INT, VOIDmode,
703: INTVAL (operands[2]) & 0xffff0000)));
704: operands[1] = operands[0];
705: operands[2] = gen_rtx (CONST_INT, VOIDmode,
706: INTVAL (operands[2]) & 0xffff);
707: }
708: }")
709:
710: (define_insn ""
711: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r")
712: (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r")
713: (match_operand:SI 2 "logical_operand" "r,K,J")))]
714: ""
715: "@
716: xor %0,%1,%2
717: xoril %0,%1,%b2
718: xoriu %0,%1,%u2")
719:
720: (define_insn ""
721: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
722: (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r")
723: (match_operand:SI 2 "gen_reg_operand" "r"))
724: (const_int 0)))
725: (clobber (match_scratch:SI 3 "=r"))]
726: ""
727: "xor. %3,%1,%2"
728: [(set_attr "type" "compare")])
729:
730: (define_insn ""
731: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
732: (compare:CC (xor:SI (match_operand:SI 1 "gen_reg_operand" "r")
733: (match_operand:SI 2 "gen_reg_operand" "r"))
734: (const_int 0)))
735: (set (match_operand:SI 0 "gen_reg_operand" "=r")
736: (xor:SI (match_dup 1) (match_dup 2)))]
737: ""
738: "xor. %0,%1,%2"
739: [(set_attr "type" "compare")])
740:
741: (define_expand "xorsi3"
742: [(set (match_operand:SI 0 "gen_reg_operand" "")
743: (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
744: (match_operand:SI 2 "reg_or_cint_operand" "")))]
745: ""
746: "
747: {
748: if (GET_CODE (operands[2]) == CONST_INT
749: && ! logical_operand (operands[2], SImode))
750: {
751: emit_insn (gen_xorsi3 (operands[0], operands[1],
752: gen_rtx (CONST_INT, VOIDmode,
753: INTVAL (operands[2]) & 0xffff0000)));
754: operands[1] = operands[0];
755: operands[2] = gen_rtx (CONST_INT, VOIDmode,
756: INTVAL (operands[2]) & 0xffff);
757: }
758: }")
759:
760: (define_insn ""
761: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
762: (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
763: (match_operand:SI 2 "gen_reg_operand" "r"))))]
764: ""
765: "eqv %0,%1,%2")
766:
767: (define_insn ""
768: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
769: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
770: (match_operand:SI 2 "gen_reg_operand" "r")))
771: (const_int 0)))
772: (clobber (match_scratch:SI 3 "=r"))]
773: ""
774: "eqv. %3,%1,%2"
775: [(set_attr "type" "compare")])
776:
777: (define_insn ""
778: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
779: (compare:CC (not:SI (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
780: (match_operand:SI 2 "gen_reg_operand" "r")))
781: (const_int 0)))
782: (set (match_operand:SI 0 "gen_reg_operand" "=r")
783: (not:SI (xor:SI (match_dup 1) (match_dup 2))))]
784: ""
785: "eqv. %0,%1,%2"
786: [(set_attr "type" "compare")])
787:
788: (define_insn ""
789: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
790: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
791: (match_operand:SI 2 "gen_reg_operand" "r")))]
792: ""
793: "andc %0,%2,%1")
794:
795: (define_insn ""
796: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
797: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
798: (match_operand:SI 2 "gen_reg_operand" "r"))
799: (const_int 0)))
800: (clobber (match_scratch:SI 3 "=r"))]
801: ""
802: "andc. %3,%2,%1"
803: [(set_attr "type" "compare")])
804:
805: (define_insn ""
806: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
807: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
808: (match_operand:SI 2 "gen_reg_operand" "r"))
809: (const_int 0)))
810: (set (match_operand:SI 0 "gen_reg_operand" "=r")
811: (and:SI (not:SI (match_dup 1)) (match_dup 2)))]
812: ""
813: "andc. %0,%2,%1"
814: [(set_attr "type" "compare")])
815:
816: (define_insn ""
817: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
818: (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
819: (match_operand:SI 2 "gen_reg_operand" "r")))]
820: ""
821: "orc %0,%2,%1")
822:
823: (define_insn ""
824: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
825: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
826: (match_operand:SI 2 "gen_reg_operand" "r"))
827: (const_int 0)))
828: (clobber (match_scratch:SI 3 "=r"))]
829: ""
830: "orc. %3,%2,%1"
831: [(set_attr "type" "compare")])
832:
833: (define_insn ""
834: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
835: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
836: (match_operand:SI 2 "gen_reg_operand" "r"))
837: (const_int 0)))
838: (set (match_operand:SI 0 "gen_reg_operand" "=r")
839: (ior:SI (not:SI (match_dup 1)) (match_dup 2)))]
840: ""
841: "orc. %0,%2,%1"
842: [(set_attr "type" "compare")])
843:
844: (define_insn ""
845: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
846: (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
847: (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))]
848: ""
849: "nand %0,%1,%2")
850:
851: (define_insn ""
852: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
853: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
854: (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
855: (const_int 0)))
856: (clobber (match_scratch:SI 3 "=r"))]
857: ""
858: "nand. %3,%1,%2"
859: [(set_attr "type" "compare")])
860:
861: (define_insn ""
862: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
863: (compare:CC (ior:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
864: (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
865: (const_int 0)))
866: (set (match_operand:SI 0 "gen_reg_operand" "=r")
867: (ior:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
868: ""
869: "nand. %0,%1,%2"
870: [(set_attr "type" "compare")])
871:
872: (define_insn ""
873: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
874: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
875: (not:SI (match_operand:SI 2 "gen_reg_operand" "r"))))]
876: ""
877: "nor %0,%1,%2")
878:
879: (define_insn ""
880: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
881: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
882: (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
883: (const_int 0)))
884: (clobber (match_scratch:SI 3 "=r"))]
885: ""
886: "nor. %3,%1,%2"
887: [(set_attr "type" "compare")])
888:
889: (define_insn ""
890: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
891: (compare:CC (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
892: (not:SI (match_operand:SI 2 "gen_reg_operand" "r")))
893: (const_int 0)))
894: (set (match_operand:SI 0 "gen_reg_operand" "=r")
895: (and:SI (not:SI (match_dup 1)) (not:SI (match_dup 2))))]
896: ""
897: "nor. %0,%1,%2"
898: [(set_attr "type" "compare")])
899:
900: ;; maskir insn. We need four forms because things might be in arbitrary
901: ;; orders. Don't define forms that only set CR fields because these
902: ;; would modify an input register.
903:
904: (define_insn ""
905: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
906: (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
907: (match_operand:SI 2 "gen_reg_operand" "0"))
908: (and:SI (match_dup 1)
909: (match_operand:SI 3 "gen_reg_operand" "r"))))]
910: ""
911: "maskir %0,%3,%1")
912:
913: (define_insn ""
914: [(set (match_operand:SI 0 "register_operand" "=r")
915: (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
916: (match_operand:SI 2 "gen_reg_operand" "0"))
917: (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
918: (match_dup 1))))]
919: ""
920: "maskir %0,%3,%1")
921:
922: (define_insn ""
923: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
924: (ior:SI (and:SI (match_dup 1)
925: (match_operand:SI 3 "gen_reg_operand" "r"))
926: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
927: (match_operand:SI 2 "gen_reg_operand" "0"))))]
928: ""
929: "maskir %0,%3,%1")
930:
931: (define_insn ""
932: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
933: (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
934: (match_dup 1))
935: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
936: (match_operand:SI 2 "gen_reg_operand" "0"))))]
937: ""
938: "maskir %0,%3,%1")
939:
940: (define_insn ""
941: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
942: (compare:CC
943: (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
944: (match_operand:SI 2 "gen_reg_operand" "0"))
945: (and:SI (match_dup 1)
946: (match_operand:SI 3 "gen_reg_operand" "r")))
947: (const_int 0)))
948: (set (match_operand:SI 0 "gen_reg_operand" "=r")
949: (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
950: (and:SI (match_dup 1) (match_dup 3))))]
951: ""
952: "maskir. %0,%3,%1"
953: [(set_attr "type" "compare")])
954:
955: (define_insn ""
956: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
957: (compare:CC
958: (ior:SI (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
959: (match_operand:SI 2 "gen_reg_operand" "0"))
960: (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
961: (match_dup 1)))
962: (const_int 0)))
963: (set (match_operand:SI 0 "register_operand" "=r")
964: (ior:SI (and:SI (not:SI (match_dup 1)) (match_dup 2))
965: (and:SI (match_dup 3) (match_dup 1))))]
966: ""
967: "maskir. %0,%3,%1"
968: [(set_attr "type" "compare")])
969:
970: (define_insn ""
971: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
972: (compare:CC
973: (ior:SI (and:SI (match_dup 1)
974: (match_operand:SI 3 "gen_reg_operand" "r"))
975: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
976: (match_operand:SI 2 "gen_reg_operand" "0")))
977: (const_int 0)))
978: (set (match_operand:SI 0 "gen_reg_operand" "=r")
979: (ior:SI (and:SI (match_dup 1) (match_dup 3))
980: (and:SI (not:SI (match_dup 1)) (match_dup 2))))]
981: ""
982: "maskir. %0,%3,%1"
983: [(set_attr "type" "compare")])
984:
985: (define_insn ""
986: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
987: (compare:CC
988: (ior:SI (and:SI (match_operand:SI 3 "gen_reg_operand" "r")
989: (match_dup 1))
990: (and:SI (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
991: (match_operand:SI 2 "gen_reg_operand" "0")))
992: (const_int 0)))
993: (set (match_operand:SI 0 "gen_reg_operand" "=r")
994: (ior:SI (and:SI (match_dup 3) (match_dup 1))
995: (and:SI (not:SI (match_dup 1)) (match_dup 2))))]
996: ""
997: "maskir. %0,%3,%1"
998: [(set_attr "type" "compare")])
999:
1000: ;; Rotate and shift insns, in all their variants. These support shifts,
1001: ;; field inserts and extracts, and various combinations thereof.
1002: (define_insn "insv"
1003: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1004: (match_operand:SI 1 "const_int_operand" "i")
1005: (match_operand:SI 2 "const_int_operand" "i"))
1006: (match_operand:SI 3 "gen_reg_operand" "r"))]
1007: ""
1008: "*
1009: {
1010: int start = INTVAL (operands[2]) & 31;
1011: int size = INTVAL (operands[1]) & 31;
1012:
1013: operands[4] = gen_rtx (CONST_INT, VOIDmode, 32 - start - size);
1014: operands[1] = gen_rtx (CONST_INT, VOIDmode, start + size - 1);
1015: return \"rlimi %0,%3,%4,%h2,%h1\";
1016: }")
1017:
1018: (define_insn "extzv"
1019: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1020: (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
1021: (match_operand:SI 2 "const_int_operand" "i")
1022: (match_operand:SI 3 "const_int_operand" "i")))]
1023: ""
1024: "*
1025: {
1026: int start = INTVAL (operands[3]) & 31;
1027: int size = INTVAL (operands[2]) & 31;
1028:
1029: if (start + size >= 32)
1030: operands[3] = const0_rtx;
1031: else
1032: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1033: return \"rlinm %0,%1,%3,%s2,31\";
1034: }")
1035:
1036: (define_insn ""
1037: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1038: (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
1039: (match_operand:SI 2 "const_int_operand" "i")
1040: (match_operand:SI 3 "const_int_operand" "i"))
1041: (const_int 0)))
1042: (clobber (match_scratch:SI 4 "=r"))]
1043: ""
1044: "*
1045: {
1046: int start = INTVAL (operands[3]) & 31;
1047: int size = INTVAL (operands[2]) & 31;
1048:
1049: if (start + size >= 32)
1050: operands[3] = const0_rtx;
1051: else
1052: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1053: return \"rlinm. %4,%1,%3,%s2,31\";
1054: }"
1055: [(set_attr "type" "compare")])
1056:
1057: (define_insn ""
1058: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1059: (compare:CC (zero_extract:SI (match_operand:SI 1 "gen_reg_operand" "r")
1060: (match_operand:SI 2 "const_int_operand" "i")
1061: (match_operand:SI 3 "const_int_operand" "i"))
1062: (const_int 0)))
1063: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1064: (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))]
1065: ""
1066: "*
1067: {
1068: int start = INTVAL (operands[3]) & 31;
1069: int size = INTVAL (operands[2]) & 31;
1070:
1071: if (start + size >= 32)
1072: operands[3] = const0_rtx;
1073: else
1074: operands[3] = gen_rtx (CONST_INT, VOIDmode, start + size);
1075: return \"rlinm. %0,%1,%3,%s2,31\";
1076: }"
1077: [(set_attr "type" "delayed_compare")])
1078:
1079: (define_insn "rotlsi3"
1080: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1081: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1082: (match_operand:SI 2 "reg_or_cint_operand" "ri")))]
1083: ""
1084: "rl%I2nm %0,%1,%h2,0,31")
1085:
1086: (define_insn ""
1087: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1088: (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1089: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1090: (const_int 0)))
1091: (clobber (match_scratch:SI 3 "=r"))]
1092: ""
1093: "rl%I2nm. %3,%1,%h2,0,31"
1094: [(set_attr "type" "delayed_compare")])
1095:
1096: (define_insn ""
1097: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1098: (compare:CC (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1099: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1100: (const_int 0)))
1101: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1102: (rotate:SI (match_dup 1) (match_dup 2)))]
1103: ""
1104: "rl%I2nm. %0,%1,%h2,0,31"
1105: [(set_attr "type" "delayed_compare")])
1106:
1107: (define_insn ""
1108: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1109: (and:SI (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1110: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1111: (match_operand:SI 3 "mask_operand" "L")))]
1112: ""
1113: "rl%I2nm %0,%1,%h2,%m3,%M3")
1114:
1115: (define_insn ""
1116: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1117: (compare:CC (and:SI
1118: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1119: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1120: (match_operand:SI 3 "mask_operand" "L"))
1121: (const_int 0)))
1122: (clobber (match_scratch:SI 4 "=r"))]
1123: ""
1124: "rl%I2nm. %4,%1,%h2,%m3,%M3"
1125: [(set_attr "type" "delayed_compare")])
1126:
1127: (define_insn ""
1128: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1129: (compare:CC (and:SI
1130: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1131: (match_operand:SI 2 "reg_or_cint_operand" "ri"))
1132: (match_operand:SI 3 "mask_operand" "L"))
1133: (const_int 0)))
1134: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1135: (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1136: ""
1137: "rl%I2nm. %0,%1,%h2,%m3,%M3"
1138: [(set_attr "type" "delayed_compare")])
1139:
1140: (define_insn ""
1141: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1142: (zero_extend:SI
1143: (subreg:QI
1144: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1145: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1146: ""
1147: "rl%I2nm %0,%1,%h2,24,31")
1148:
1149: (define_insn ""
1150: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1151: (compare:CC (zero_extend:SI
1152: (subreg:QI
1153: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1154: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1155: (const_int 0)))
1156: (clobber (match_scratch:SI 3 "=r"))]
1157: ""
1158: "rl%I2nm. %3,%1,%h2,24,31"
1159: [(set_attr "type" "delayed_compare")])
1160:
1161: (define_insn ""
1162: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1163: (compare:CC (zero_extend:SI
1164: (subreg:QI
1165: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1166: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1167: (const_int 0)))
1168: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1169: (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1170: ""
1171: "rl%I2nm. %0,%1,%h2,24,31"
1172: [(set_attr "type" "delayed_compare")])
1173:
1174: (define_insn ""
1175: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1176: (zero_extend:SI
1177: (subreg:HI
1178: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1179: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))]
1180: ""
1181: "rl%I2nm %0,%1,%h2,16,31")
1182:
1183: (define_insn ""
1184: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1185: (compare:CC (zero_extend:SI
1186: (subreg:HI
1187: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1188: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1189: (const_int 0)))
1190: (clobber (match_scratch:SI 3 "=r"))]
1191: ""
1192: "rl%I2nm. %3,%1,%h2,16,31"
1193: [(set_attr "type" "delayed_compare")])
1194:
1195: (define_insn ""
1196: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1197: (compare:CC (zero_extend:SI
1198: (subreg:HI
1199: (rotate:SI (match_operand:SI 1 "gen_reg_operand" "r")
1200: (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0))
1201: (const_int 0)))
1202: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1203: (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))]
1204: ""
1205: "rl%I2nm. %0,%1,%h2,16,31"
1206: [(set_attr "type" "delayed_compare")])
1207:
1208: ;; Note that we use "sle." instead of "sl." so that we can set
1209: ;; SHIFT_COUNT_TRUNCATED.
1210:
1211: (define_insn "ashlsi3"
1212: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1213: (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1214: (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1215: (clobber (match_scratch:SI 3 "=q,X"))]
1216: ""
1217: "@
1218: sle %0,%1,%2
1219: sli %0,%1,%h2")
1220:
1221: (define_insn ""
1222: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1223: (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1224: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1225: (const_int 0)))
1226: (clobber (match_scratch:SI 3 "=r,r"))
1227: (clobber (match_scratch:SI 4 "=q,X"))]
1228: ""
1229: "@
1230: sle. %3,%1,%2
1231: sli. %3,%1,%h2"
1232: [(set_attr "type" "delayed_compare")])
1233:
1234: (define_insn ""
1235: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1236: (compare:CC (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1237: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1238: (const_int 0)))
1239: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1240: (ashift:SI (match_dup 1) (match_dup 2)))
1241: (clobber (match_scratch:SI 4 "=q,X"))]
1242: ""
1243: "@
1244: sle. %0,%1,%2
1245: sli. %0,%1,%h2"
1246: [(set_attr "type" "delayed_compare")])
1247:
1248: (define_insn ""
1249: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1250: (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
1251: (match_operand:SI 2 "const_int_operand" "i"))
1252: (match_operand:SI 3 "mask_operand" "L")))]
1253: "includes_lshift_p (operands[2], operands[3])"
1254: "rlinm %0,%h1,%h2,%m3,%M3")
1255:
1256: (define_insn ""
1257: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1258: (compare:CC
1259: (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
1260: (match_operand:SI 2 "const_int_operand" "i"))
1261: (match_operand:SI 3 "mask_operand" "L"))
1262: (const_int 0)))
1263: (clobber (match_scratch:SI 4 "=r"))]
1264: "includes_lshift_p (operands[2], operands[3])"
1265: "rlinm. %4,%h1,%h2,%m3,%M3"
1266: [(set_attr "type" "delayed_compare")])
1267:
1268: (define_insn ""
1269: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1270: (compare:CC
1271: (and:SI (ashift:SI (match_operand:SI 1 "gen_reg_operand" "r")
1272: (match_operand:SI 2 "const_int_operand" "i"))
1273: (match_operand:SI 3 "mask_operand" "L"))
1274: (const_int 0)))
1275: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1276: (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1277: "includes_lshift_p (operands[2], operands[3])"
1278: "rlinm. %0,%h1,%h2,%m3,%M3"
1279: [(set_attr "type" "delayed_compare")])
1280:
1.1.1.2 ! root 1281: ;; The RS/6000 assembler mis-handles "sri x,x,0", so write that case as
! 1282: ;; "sli x,x,0".
1.1 root 1283: (define_insn "lshrsi3"
1284: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1285: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1286: (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1287: (clobber (match_scratch:SI 3 "=q,X"))]
1288: ""
1289: "@
1290: sre %0,%1,%2
1.1.1.2 ! root 1291: s%A2i %0,%1,%h2")
1.1 root 1292:
1293: (define_insn ""
1294: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1295: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1296: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1297: (const_int 0)))
1298: (clobber (match_scratch:SI 3 "=r,r"))
1299: (clobber (match_scratch:SI 4 "=q,X"))]
1300: ""
1301: "@
1302: sre. %3,%1,%2
1.1.1.2 ! root 1303: s%A2i. %3,%1,%h2"
1.1 root 1304: [(set_attr "type" "delayed_compare")])
1305:
1306: (define_insn ""
1307: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1308: (compare:CC (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1309: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1310: (const_int 0)))
1311: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1312: (lshiftrt:SI (match_dup 1) (match_dup 2)))
1313: (clobber (match_scratch:SI 4 "=q,X"))]
1314: ""
1315: "@
1316: sre. %0,%1,%2
1.1.1.2 ! root 1317: s%A2i. %0,%1,%h2"
1.1 root 1318: [(set_attr "type" "delayed_compare")])
1319:
1320: (define_insn ""
1321: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1322: (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1323: (match_operand:SI 2 "const_int_operand" "i"))
1324: (match_operand:SI 3 "mask_operand" "L")))]
1325: "includes_rshift_p (operands[2], operands[3])"
1326: "rlinm %0,%1,%s2,%m3,%M3")
1327:
1328: (define_insn ""
1329: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1330: (compare:CC
1331: (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1332: (match_operand:SI 2 "const_int_operand" "i"))
1333: (match_operand:SI 3 "mask_operand" "L"))
1334: (const_int 0)))
1335: (clobber (match_scratch:SI 4 "=r"))]
1336: "includes_rshift_p (operands[2], operands[3])"
1337: "rlinm. %4,%1,%s2,%m3,%M3"
1338: [(set_attr "type" "delayed_compare")])
1339:
1340: (define_insn ""
1341: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
1342: (compare:CC
1343: (and:SI (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1344: (match_operand:SI 2 "const_int_operand" "i"))
1345: (match_operand:SI 3 "mask_operand" "L"))
1346: (const_int 0)))
1347: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1348: (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))]
1349: "includes_rshift_p (operands[2], operands[3])"
1350: "rlinm. %0,%1,%s2,%m3,%M3"
1351: [(set_attr "type" "delayed_compare")])
1352:
1353: (define_insn ""
1354: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1355: (zero_extend:SI
1356: (subreg:QI
1357: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1358: (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1359: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1360: "rlinm %0,%1,%s2,24,31")
1361:
1362: (define_insn ""
1363: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1364: (compare:CC
1365: (zero_extend:SI
1366: (subreg:QI
1367: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1368: (match_operand:SI 2 "const_int_operand" "i")) 0))
1369: (const_int 0)))
1370: (clobber (match_scratch:SI 3 "=r"))]
1371: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1372: "rlinm. %3,%1,%s2,24,31"
1373: [(set_attr "type" "delayed_compare")])
1374:
1375: (define_insn ""
1376: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1377: (compare:CC
1378: (zero_extend:SI
1379: (subreg:QI
1380: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1381: (match_operand:SI 2 "const_int_operand" "i")) 0))
1382: (const_int 0)))
1383: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1384: (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1385: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 255))"
1386: "rlinm. %0,%1,%s2,24,31"
1387: [(set_attr "type" "delayed_compare")])
1388:
1389: (define_insn ""
1390: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
1391: (zero_extend:SI
1392: (subreg:HI
1393: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1394: (match_operand:SI 2 "const_int_operand" "i")) 0)))]
1395: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1396: "rlinm %0,%1,%s2,16,31")
1397:
1398: (define_insn ""
1399: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
1400: (compare:CC
1401: (zero_extend:SI
1402: (subreg:HI
1403: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1404: (match_operand:SI 2 "const_int_operand" "i")) 0))
1405: (const_int 0)))
1406: (clobber (match_scratch:SI 3 "=r"))]
1407: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1408: "rlinm. %3,%1,%s2,16,31"
1409: [(set_attr "type" "delayed_compare")])
1410:
1411: (define_insn ""
1412: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
1413: (compare:CC
1414: (zero_extend:SI
1415: (subreg:HI
1416: (lshiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r")
1417: (match_operand:SI 2 "const_int_operand" "i")) 0))
1418: (const_int 0)))
1419: (set (match_operand:SI 0 "gen_reg_operand" "=r")
1420: (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))]
1421: "includes_rshift_p (operands[2], gen_rtx (CONST_INT, VOIDmode, 65535))"
1422: "rlinm. %0,%1,%s2,16,31"
1423: [(set_attr "type" "delayed_compare")])
1424:
1425: (define_insn ""
1426: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1427: (const_int 1)
1428: (match_operand:SI 1 "gen_reg_operand" "r"))
1429: (ashiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r")
1430: (const_int 31)))]
1431: ""
1432: "rrib %0,%1,%2")
1433:
1434: (define_insn ""
1435: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1436: (const_int 1)
1437: (match_operand:SI 1 "gen_reg_operand" "r"))
1438: (lshiftrt:SI (match_operand:SI 2 "gen_reg_operand" "r")
1439: (const_int 31)))]
1440: ""
1441: "rrib %0,%1,%2")
1442:
1443: (define_insn ""
1444: [(set (zero_extract:SI (match_operand:SI 0 "gen_reg_operand" "+r")
1445: (const_int 1)
1446: (match_operand:SI 1 "gen_reg_operand" "r"))
1447: (zero_extract:SI (match_operand:SI 2 "gen_reg_operand" "r")
1448: (const_int 1)
1449: (const_int 0)))]
1450: ""
1451: "rrib %0,%1,%2")
1452:
1453: (define_insn "ashrsi3"
1454: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1455: (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1456: (match_operand:SI 2 "reg_or_cint_operand" "r,i")))
1457: (clobber (match_scratch:SI 3 "=q,X"))]
1458: ""
1459: "@
1460: srea %0,%1,%2
1461: srai %0,%1,%h2")
1462:
1463: (define_insn ""
1464: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
1465: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1466: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1467: (const_int 0)))
1468: (clobber (match_scratch:SI 3 "=r,r"))
1469: (clobber (match_scratch:SI 4 "=q,X"))]
1470: ""
1471: "@
1472: srea. %3,%1,%2
1473: srai. %3,%1,%h2"
1474: [(set_attr "type" "delayed_compare")])
1475:
1476: (define_insn ""
1477: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
1478: (compare:CC (ashiftrt:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
1479: (match_operand:SI 2 "reg_or_cint_operand" "r,i"))
1480: (const_int 0)))
1481: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
1482: (ashiftrt:SI (match_dup 1) (match_dup 2)))
1483: (clobber (match_scratch:SI 4 "=q,X"))]
1484: ""
1485: "@
1486: srea. %0,%1,%2
1487: srai. %0,%1,%h2"
1488: [(set_attr "type" "delayed_compare")])
1489:
1490: (define_expand "extendqisi2"
1491: [(parallel [(set (match_dup 2)
1492: (ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
1493: (const_int 24)))
1494: (clobber (scratch:SI))])
1495: (parallel [(set (match_operand:SI 0 "gen_reg_operand" "")
1496: (ashiftrt:SI (match_dup 2)
1497: (const_int 24)))
1498: (clobber (scratch:SI))])]
1499: ""
1500: "
1501: { operands[1] = gen_lowpart (SImode, operands[1]);
1502: operands[2] = gen_reg_rtx (SImode); }")
1503:
1504: (define_expand "extendqihi2"
1505: [(parallel [(set (match_dup 2)
1506: (ashift:SI (match_operand:QI 1 "gen_reg_operand" "")
1507: (const_int 24)))
1508: (clobber (scratch:SI))])
1509: (parallel [(set (match_operand:HI 0 "gen_reg_operand" "")
1510: (ashiftrt:SI (match_dup 2)
1511: (const_int 24)))
1512: (clobber (scratch:SI))])]
1513: ""
1514: "
1515: { operands[0] = gen_lowpart (SImode, operands[0]);
1516: operands[1] = gen_lowpart (SImode, operands[1]);
1517: operands[2] = gen_reg_rtx (SImode); }")
1518:
1519: ;; Floating-point insns, excluding normal data motion.
1520: ;;
1521: ;; We pretend that we have both SFmode and DFmode insns, while, in fact,
1522: ;; all fp insns are actually done in double. The only conversions we will
1523: ;; do will be when storing to memory. In that case, we will use the "frsp"
1524: ;; instruction before storing.
1525: ;;
1526: ;; Note that when we store into a single-precision memory location, we need to
1527: ;; use the frsp insn first. If the register being stored isn't dead, we
1528: ;; need a scratch register for the frsp. But this is difficult when the store
1529: ;; is done by reload. It is not incorrect to do the frsp on the register in
1530: ;; this case, we just lose precision that we would have otherwise gotten but
1531: ;; is not guaranteed. Perhaps this should be tightened up at some point.
1532:
1533: (define_insn "extendsfdf2"
1534: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1535: (float_extend:DF (match_operand:SF 1 "gen_reg_operand" "f")))]
1536: ""
1537: "*
1538: {
1539: if (REGNO (operands[0]) == REGNO (operands[1]))
1540: return \"\";
1541: else
1542: return \"fmr %0,%1\";
1543: }"
1544: [(set_attr "type" "fp")])
1545:
1546: (define_insn "truncdfsf2"
1547: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1548: (float_truncate:SF (match_operand:DF 1 "gen_reg_operand" "f")))]
1549: ""
1550: "*
1551: {
1552: if (REGNO (operands[0]) == REGNO (operands[1]))
1553: return \"\";
1554: else
1555: return \"fmr %0,%1\";
1556: }"
1557: [(set_attr "type" "fp")])
1558:
1559: (define_insn "negsf2"
1560: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1561: (neg:SF (match_operand:SF 1 "gen_reg_operand" "f")))]
1562: ""
1563: "fneg %0,%1"
1564: [(set_attr "type" "fp")])
1565:
1566: (define_insn "abssf2"
1567: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1568: (abs:SF (match_operand:SF 1 "gen_reg_operand" "f")))]
1569: ""
1570: "fabs %0,%1"
1571: [(set_attr "type" "fp")])
1572:
1573: (define_insn ""
1574: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1575: (neg:SF (abs:SF (match_operand:SF 1 "gen_reg_operand" "f"))))]
1576: ""
1577: "fnabs %0,%1"
1578: [(set_attr "type" "fp")])
1579:
1580: (define_insn "addsf3"
1581: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1582: (plus:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1583: (match_operand:SF 2 "gen_reg_operand" "f")))]
1584: ""
1585: "fa %0,%1,%2"
1586: [(set_attr "type" "fp")])
1587:
1588: (define_insn "subsf3"
1589: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1590: (minus:SF (match_operand:SF 1 "gen_reg_operand" "f")
1591: (match_operand:SF 2 "gen_reg_operand" "f")))]
1592: ""
1593: "fs %0,%1,%2"
1594: [(set_attr "type" "fp")])
1595:
1596: (define_insn "mulsf3"
1597: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1598: (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1599: (match_operand:SF 2 "gen_reg_operand" "f")))]
1600: ""
1601: "fm %0,%1,%2"
1602: [(set_attr "type" "fp")])
1603:
1604: (define_insn "divsf3"
1605: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1606: (div:SF (match_operand:SF 1 "gen_reg_operand" "f")
1607: (match_operand:SF 2 "gen_reg_operand" "f")))]
1608: ""
1609: "fd %0,%1,%2"
1610: [(set_attr "type" "fp")])
1611:
1612: (define_insn ""
1613: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1614: (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1615: (match_operand:SF 2 "gen_reg_operand" "f"))
1616: (match_operand:SF 3 "gen_reg_operand" "f")))]
1617: ""
1618: "fma %0,%1,%2,%3"
1619: [(set_attr "type" "fp")])
1620:
1621: (define_insn ""
1622: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1623: (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1624: (match_operand:SF 2 "gen_reg_operand" "f"))
1625: (match_operand:SF 3 "gen_reg_operand" "f")))]
1626: ""
1627: "fms %0,%1,%2,%3"
1628: [(set_attr "type" "fp")])
1629:
1630: (define_insn ""
1631: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1632: (neg:SF (plus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1633: (match_operand:SF 2 "gen_reg_operand" "f"))
1634: (match_operand:SF 3 "gen_reg_operand" "f"))))]
1635: ""
1636: "fnma %0,%1,%2,%3"
1637: [(set_attr "type" "fp")])
1638:
1639: (define_insn ""
1640: [(set (match_operand:SF 0 "gen_reg_operand" "=f")
1641: (neg:SF (minus:SF (mult:SF (match_operand:SF 1 "gen_reg_operand" "%f")
1642: (match_operand:SF 2 "gen_reg_operand" "f"))
1643: (match_operand:SF 3 "gen_reg_operand" "f"))))]
1644: ""
1645: "fnms %0,%1,%2,%3"
1646: [(set_attr "type" "fp")])
1647:
1648: (define_insn "negdf2"
1649: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1650: (neg:DF (match_operand:DF 1 "gen_reg_operand" "f")))]
1651: ""
1652: "fneg %0,%1"
1653: [(set_attr "type" "fp")])
1654:
1655: (define_insn "absdf2"
1656: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1657: (abs:DF (match_operand:DF 1 "gen_reg_operand" "f")))]
1658: ""
1659: "fabs %0,%1"
1660: [(set_attr "type" "fp")])
1661:
1662: (define_insn ""
1663: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1664: (neg:DF (abs:DF (match_operand:DF 1 "gen_reg_operand" "f"))))]
1665: ""
1666: "fnabs %0,%1"
1667: [(set_attr "type" "fp")])
1668:
1669: (define_insn "adddf3"
1670: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1671: (plus:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1672: (match_operand:DF 2 "gen_reg_operand" "f")))]
1673: ""
1674: "fa %0,%1,%2"
1675: [(set_attr "type" "fp")])
1676:
1677: (define_insn "subdf3"
1678: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1679: (minus:DF (match_operand:DF 1 "gen_reg_operand" "f")
1680: (match_operand:DF 2 "gen_reg_operand" "f")))]
1681: ""
1682: "fs %0,%1,%2"
1683: [(set_attr "type" "fp")])
1684:
1685: (define_insn "muldf3"
1686: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1687: (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1688: (match_operand:DF 2 "gen_reg_operand" "f")))]
1689: ""
1690: "fm %0,%1,%2"
1691: [(set_attr "type" "fp")])
1692:
1693: (define_insn "divdf3"
1694: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1695: (div:DF (match_operand:DF 1 "gen_reg_operand" "f")
1696: (match_operand:DF 2 "gen_reg_operand" "f")))]
1697: ""
1698: "fd %0,%1,%2"
1699: [(set_attr "type" "fp")])
1700:
1701: (define_insn ""
1702: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1703: (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1704: (match_operand:DF 2 "gen_reg_operand" "f"))
1705: (match_operand:DF 3 "gen_reg_operand" "f")))]
1706: ""
1707: "fma %0,%1,%2,%3"
1708: [(set_attr "type" "fp")])
1709:
1710: (define_insn ""
1711: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1712: (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1713: (match_operand:DF 2 "gen_reg_operand" "f"))
1714: (match_operand:DF 3 "gen_reg_operand" "f")))]
1715: ""
1716: "fms %0,%1,%2,%3"
1717: [(set_attr "type" "fp")])
1718:
1719: (define_insn ""
1720: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1721: (neg:DF (plus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1722: (match_operand:DF 2 "gen_reg_operand" "f"))
1723: (match_operand:DF 3 "gen_reg_operand" "f"))))]
1724: ""
1725: "fnma %0,%1,%2,%3"
1726: [(set_attr "type" "fp")])
1727:
1728: (define_insn ""
1729: [(set (match_operand:DF 0 "gen_reg_operand" "=f")
1730: (neg:DF (minus:DF (mult:DF (match_operand:DF 1 "gen_reg_operand" "%f")
1731: (match_operand:DF 2 "gen_reg_operand" "f"))
1732: (match_operand:DF 3 "gen_reg_operand" "f"))))]
1733: ""
1734: "fnms %0,%1,%2,%3"
1735: [(set_attr "type" "fp")])
1736:
1737: ;; Conversions to and from floating-point.
1738: (define_expand "floatsidf2"
1739: [(set (match_dup 2)
1740: (plus:DI (zero_extend:DI
1741: (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
1742: (match_dup 3)))
1743: (match_dup 4)))
1744: (set (match_operand:DF 0 "gen_reg_operand" "")
1745: (minus:DF (subreg:DF (match_dup 2) 0)
1746: (match_dup 5)))]
1747: ""
1748: "
1749: {
1750: #if HOST_BITS_PER_INT != BITS_PER_WORD
1751: /* Maybe someone can figure out how to do this in that case. I don't
1752: want to right now. */
1753: abort ();
1754: #endif
1755:
1756: operands[2] = gen_reg_rtx (DImode);
1757: operands[3] = gen_rtx (CONST_INT, VOIDmode, 0x80000000);
1758: operands[4] = immed_double_const (0, 0x43300000, DImode);
1759: operands[5] = force_reg (DFmode, immed_double_const (0x43300000,
1760: 0x80000000, DFmode));
1761: }")
1762:
1763: (define_expand "floatunssidf2"
1764: [(set (match_dup 2)
1765: (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
1766: (match_dup 3)))
1767: (set (match_operand:DF 0 "gen_reg_operand" "")
1768: (minus:DF (subreg:DF (match_dup 2) 0)
1769: (match_dup 4)))]
1770: ""
1771: "
1772: {
1773: #if HOST_BITS_PER_INT != BITS_PER_WORD
1774: /* Maybe someone can figure out how to do this in that case. I don't
1775: want to right now. */
1776: abort ();
1777: #endif
1778:
1779: operands[2] = gen_reg_rtx (DImode);
1780: operands[3] = immed_double_const (0, 0x43300000, DImode);
1781: operands[4] = force_reg (DFmode, immed_double_const (0x43300000, 0, DFmode));
1782: }")
1783:
1784: ;; For the above two cases, we always split.
1785: (define_split
1786: [(set (match_operand:DI 0 "gen_reg_operand" "")
1787: (plus:DI (zero_extend:DI
1788: (xor:SI (match_operand:SI 1 "gen_reg_operand" "")
1789: (match_operand:SI 2 "logical_operand" "")))
1790: (match_operand:DI 3 "immediate_operand" "")))]
1791: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1792: && GET_CODE (operands[3]) == CONST_DOUBLE
1793: && CONST_DOUBLE_LOW (operands[3]) == 0"
1794: [(set (match_dup 6) (xor:SI (match_dup 1) (match_dup 2)))
1795: (set (match_dup 4) (match_dup 5))]
1796: "
1797: { operands[4] = operand_subword (operands[0], 0, 0, DImode);
1798: operands[5] = operand_subword (operands[3], 0, 0, DImode);
1799: operands[6] = operand_subword (operands[0], 1, 0, DImode);
1800: }")
1801:
1802: (define_insn ""
1803: [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1804: (plus:DI (zero_extend:DI
1805: (xor:SI (match_operand:SI 1 "gen_reg_operand" "%r")
1806: (match_operand:SI 2 "logical_operand" "rKJ")))
1807: (match_operand:DI 3 "immediate_operand" "n")))]
1808: "HOST_BITS_PER_INT == BITS_PER_WORD
1809: && GET_CODE (operands[3]) == CONST_DOUBLE
1810: && CONST_DOUBLE_LOW (operands[3]) == 0"
1811: "#")
1812:
1813: (define_split
1814: [(set (match_operand:DI 0 "gen_reg_operand" "=")
1815: (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" ""))
1816: (match_operand:DI 2 "immediate_operand" "")))]
1817: "reload_completed && HOST_BITS_PER_INT == BITS_PER_WORD
1818: && GET_CODE (operands[2]) == CONST_DOUBLE
1819: && CONST_DOUBLE_LOW (operands[2]) == 0"
1820: [(set (match_dup 3) (match_dup 4))
1821: (set (match_dup 5) (match_dup 1))]
1822: "
1823: { operands[3] = operand_subword (operands[0], 0, 0, DImode);
1824: operands[4] = operand_subword (operands[2], 0, 0, DImode);
1825: operands[5] = operand_subword (operands[0], 1, 0, DImode);
1826:
1827: if (rtx_equal_p (operands[1], operands[5]))
1828: {
1829: emit_move_insn (operands[3], operands[4]);
1830: DONE;
1831: }
1832: }")
1833:
1834: (define_insn ""
1835: [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1836: (plus:DI (zero_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
1837: (match_operand:DI 2 "immediate_operand" "n")))]
1838: "HOST_BITS_PER_INT == BITS_PER_WORD
1839: && GET_CODE (operands[2]) == CONST_DOUBLE
1840: && CONST_DOUBLE_LOW (operands[2]) == 0"
1841: "#")
1842:
1843: (define_expand "fix_truncdfsi2"
1844: [(set (match_operand:SI 0 "gen_reg_operand" "")
1845: (fix:DF (match_operand:DF 1 "gen_reg_operand" "")))]
1846: ""
1847: "
1848: {
1849: emit_insn (gen_trunc_call (operands[0], operands[1],
1850: gen_rtx (SYMBOL_REF, Pmode, \"itrunc\")));
1851: DONE;
1852: }")
1853:
1854: (define_expand "fixuns_truncdfsi2"
1855: [(set (match_operand:SI 0 "gen_reg_operand" "")
1856: (unsigned_fix:DF (match_operand:DF 1 "gen_reg_operand" "")))]
1857: ""
1858: "
1859: {
1860: emit_insn (gen_trunc_call (operands[0], operands[1],
1861: gen_rtx (SYMBOL_REF, Pmode, \"uitrunc\")));
1862: DONE;
1863: }")
1864:
1865:
1866: (define_expand "trunc_call"
1867: [(parallel [(set (match_operand:SI 0 "" "")
1868: (fix:DF (match_operand:DF 1 "" "")))
1869: (use (match_operand:SI 2 "" ""))])]
1870: ""
1871: "
1872: {
1873: rtx insns = gen_trunc_call_rtl (operands[0], operands[1], operands[2]);
1874: rtx first = XVECEXP (insns, 0, 0);
1875: rtx last = XVECEXP (insns, 0, XVECLEN (insns, 0) - 1);
1876:
1877: REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
1878: REG_NOTES (first));
1879: REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first, REG_NOTES (last));
1880:
1881: emit_insn (insns);
1882: DONE;
1883: }")
1884:
1885: (define_expand "trunc_call_rtl"
1886: [(set (reg:DF 33) (match_operand:DF 1 "gen_reg_operand" ""))
1887: (use (reg:DF 33))
1888: (parallel [(set (reg:SI 3)
1889: (call (mem:SI (match_operand 2 "" "")) (const_int 0)))
1890: (clobber (scratch:SI))])
1891: (set (match_operand:SI 0 "gen_reg_operand" "")
1892: (reg:SI 3))]
1893: ""
1894: "
1895: {
1896: rs6000_trunc_used = 1;
1897: }")
1898:
1899: ;; Define the DImode operations that can be done in a small number
1900: ;; of instructions.
1901: (define_insn "adddi3"
1902: [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1903: (plus:DI (match_operand:DI 1 "gen_reg_operand" "%r")
1904: (match_operand:DI 2 "gen_reg_operand" "r")))]
1905: ""
1906: "a %L0,%L1,%L2\;ae %0,%1,%2")
1907:
1908: (define_insn "subdi3"
1909: [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1910: (minus:DI (match_operand:DI 1 "gen_reg_operand" "r")
1911: (match_operand:DI 2 "gen_reg_operand" "r")))]
1912: ""
1913: "sf %L0,%L2,%L1\;sfe %0,%2,%1")
1914:
1915: (define_insn "negdi3"
1916: [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1917: (neg:DI (match_operand:DI 1 "gen_reg_operand" "r")))]
1918: ""
1919: "sfi %L0,%L1,0\;sfze %0,%1")
1920:
1921: (define_insn "mulsidi3"
1922: [(set (match_operand:DI 0 "gen_reg_operand" "=r")
1923: (mult:DI (sign_extend:DI (match_operand:SI 1 "gen_reg_operand" "r"))
1924: (sign_extend:DI (match_operand:SI 2 "gen_reg_operand" "r"))))
1925: (clobber (match_scratch:SI 3 "=q"))]
1926: ""
1927: "mul %0,%1,%2\;mfmq %L0")
1928:
1929: ;; If operands 0 and 2 are in the same register, we have a problem. But
1930: ;; operands 0 and 1 (the usual case) can be in the same register. That's
1931: ;; why we have the strange constraints below.
1932: (define_insn "ashldi3"
1933: [(set (match_operand:DI 0 "gen_reg_operand" "=r,r,r,&r")
1934: (ashift:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r")
1935: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
1936: (clobber (match_scratch:SI 3 "=X,q,q,q"))]
1937: ""
1938: "@
1939: sli %0,%L1,%h2\;cal %L0,0(0)
1940: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
1941: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2
1.1.1.2 ! root 1942: sl%I2q %L0,%L1,%h2\;sll%I2q %0,%1,%h2")
1.1 root 1943:
1944: (define_insn "lshrdi3"
1.1.1.2 ! root 1945: [(set (match_operand:DI 0 "gen_reg_operand" "=&r,r,r,&r")
1.1 root 1946: (lshiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r,0,r")
1947: (match_operand:SI 2 "reg_or_cint_operand" "M,i,r,r")))
1948: (clobber (match_scratch:SI 3 "=X,q,q,q"))]
1949: ""
1950: "@
1.1.1.2 ! root 1951: cal %0,0(0)\;s%A2i %L0,%1,%h2
! 1952: s%A2%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2
! 1953: s%A2%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2
! 1954: s%A2%I2q %L0,%L1,%2\;srl%I2q %0,%1,%2")
1.1 root 1955:
1956: ;; Shift by a variable amount is too complex to be worth open-coding. We
1957: ;; just handle shifts by constants.
1958:
1959: (define_expand "ashrdi3"
1960: [(parallel [(set (match_operand:DI 0 "gen_reg_operand" "=")
1961: (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "")
1962: (match_operand:SI 2 "general_operand" "")))
1963: (clobber (match_scratch:SI 3 ""))])]
1964: ""
1965: "
1966: { if (GET_CODE (operands[2]) != CONST_INT)
1967: FAIL;
1968: }")
1969:
1970: (define_insn ""
1971: [(set (match_operand:DI 0 "gen_reg_operand" "=r,r")
1972: (ashiftrt:DI (match_operand:DI 1 "gen_reg_operand" "r,r")
1973: (match_operand:SI 2 "const_int_operand" "M,i")))
1974: (clobber (match_scratch:SI 3 "=X,q"))]
1975: ""
1976: "@
1977: srai %0,%1,31\;srai %L0,%1,%h2
1978: sraiq %L0,%L1,%2\;srlq %0,%1,%2")
1979:
1980: ;; Now define ways of moving data around.
1981: ;;
1982: ;; For SI, we special-case integers that can't be loaded in one insn. We
1983: ;; do the load 16-bits at a time. We could do this by loading from memory,
1984: ;; and this is even supposed to be faster, but it is simpler not to get
1985: ;; integers in the TOC.
1986: (define_expand "movsi"
1987: [(set (match_operand:SI 0 "general_operand" "")
1988: (match_operand:SI 1 "any_operand" ""))]
1989: ""
1990: "
1991: {
1992: if (GET_CODE (operands[0]) != REG)
1993: operands[1] = force_reg (SImode, operands[1]);
1994:
1995: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
1996: operands[1] = force_const_mem (SImode, operands[1]);
1997:
1998: if (GET_CODE (operands[1]) == CONST_INT
1999: && (unsigned) (INTVAL (operands[1]) + 0x8000) >= 0x10000
2000: && (INTVAL (operands[1]) & 0xffff) != 0)
2001: {
2002: emit_move_insn (operands[0],
2003: gen_rtx (CONST_INT, VOIDmode,
2004: INTVAL (operands[1]) & 0xffff0000));
2005: emit_insn (gen_iorsi3 (operands[0], operands[0],
2006: gen_rtx (CONST_INT, VOIDmode,
2007: INTVAL (operands[1]) & 0xffff)));
2008: DONE;
2009: }
2010: }")
2011:
2012: (define_insn ""
1.1.1.2 ! root 2013: [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,*c*q,*l")
! 2014: (match_operand:SI 1 "input_operand" "r,m,r,I,J,*h,r,r"))]
1.1 root 2015: "gen_reg_operand (operands[0], SImode)
2016: || gen_reg_operand (operands[1], SImode)"
2017: "@
2018: ai %0,%1,0
2019: l%U1%X1 %0,%1
2020: st%U0%X0 %1,%0
2021: cal %0,%1(0)
2022: cau %0,0,%u1
2023: mf%1 %0
1.1.1.2 ! root 2024: mt%0 %1
1.1 root 2025: mt%0 %1"
1.1.1.2 ! root 2026: [(set_attr "type" "*,load,*,*,*,*,*,mtlr")])
1.1 root 2027:
2028: (define_insn ""
2029: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
2030: (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
2031: (const_int 0)))
2032: (set (match_operand:SI 0 "gen_reg_operand" "=r") (match_dup 1))]
2033: ""
2034: "ai. %0,%1,0"
2035: [(set_attr "type" "compare")])
2036:
2037: (define_expand "movhi"
2038: [(set (match_operand:HI 0 "general_operand" "")
2039: (match_operand:HI 1 "any_operand" ""))]
2040: ""
2041: "
2042: {
2043: if (GET_CODE (operands[0]) != REG)
2044: operands[1] = force_reg (HImode, operands[1]);
2045:
2046: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2047: operands[1] = force_const_mem (HImode, operands[1]);
2048: }")
2049:
2050: (define_insn ""
2051: [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2052: (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r"))]
2053: "gen_reg_operand (operands[0], HImode)
2054: || gen_reg_operand (operands[1], HImode)"
2055: "@
2056: oril %0,%1,0
2057: lhz%U1%X1 %0,%1
2058: sth%U0%X0 %1,%0
2059: cal %0,%w1(0)
2060: mf%1 %0
2061: mt%0 %1"
2062: [(set_attr "type" "*,load,*,*,*,*")])
2063:
2064: (define_expand "movqi"
2065: [(set (match_operand:QI 0 "general_operand" "")
2066: (match_operand:QI 1 "any_operand" ""))]
2067: ""
2068: "
2069: {
2070: if (GET_CODE (operands[0]) != REG)
2071: operands[1] = force_reg (QImode, operands[1]);
2072:
2073: if (CONSTANT_P (operands[1]) && GET_CODE (operands[1]) != CONST_INT)
2074: operands[1] = force_const_mem (QImode, operands[1]);
2075: }")
2076:
2077: (define_insn ""
2078: [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*h")
2079: (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r"))]
2080: "gen_reg_operand (operands[0], QImode)
2081: || gen_reg_operand (operands[1], QImode)"
2082: "@
2083: oril %0,%1,0
2084: lbz%U1%X1 %0,%1
2085: stb%U0%X0 %1,%0
2086: cal %0,%1(0)
2087: mf%1 %0
2088: mt%0 %1"
2089: [(set_attr "type" "*,load,*,*,*,*")])
2090:
2091: ;; Here is how to move condition codes around. When we store CC data in
2092: ;; an integer register or memory, we store just the high-order 4 bits.
2093: ;; This lets us not shift in the most common case of CR0.
2094: (define_expand "movcc"
2095: [(set (match_operand:CC 0 "nonimmediate_operand" "")
2096: (match_operand:CC 1 "nonimmediate_operand" ""))]
2097: ""
2098: "")
2099:
2100: (define_insn ""
2101: [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,y,r,r,r,r,m")
2102: (match_operand:CC 1 "nonimmediate_operand" "y,r,r,x,y,r,m,r"))]
2103: "register_operand (operands[0], CCmode)
2104: || register_operand (operands[1], CCmode)"
2105: "@
2106: mcrf %0,%1
2107: mtcrf 128,%1
2108: rlinm %1,%1,%F0,0,31\;mtcrf %R0,%1\;rlinm %1,%1,%f0,0,31
2109: mfcr %0
2110: mfcr %0\;rlinm %0,%0,%f1,0,3
2111: ai %0,%1,0
2112: l%U1%X1 %0,%1
2113: st%U0%U1 %1,%0"
2114: [(set_attr "type" "*,*,*,compare,*,*,load,*")])
2115:
2116: ;; For floating-point, we normally deal with the floating-point registers.
2117: ;; The sole exception is that parameter passing can produce floating-point
2118: ;; values in fixed-point registers. Unless the value is a simple constant
2119: ;; or already in memory, we deal with this by allocating memory and copying
2120: ;; the value explicitly via that memory location.
2121: (define_expand "movsf"
2122: [(set (match_operand:SF 0 "nonimmediate_operand" "")
2123: (match_operand:SF 1 "any_operand" ""))]
2124: ""
2125: "
2126: {
2127: /* If we are called from reload, we might be getting a SUBREG of a hard
2128: reg. So expand it. */
2129: if (GET_CODE (operands[0]) == SUBREG
2130: && GET_CODE (SUBREG_REG (operands[0])) == REG
2131: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2132: operands[0] = alter_subreg (operands[0]);
2133: if (GET_CODE (operands[1]) == SUBREG
2134: && GET_CODE (SUBREG_REG (operands[1])) == REG
2135: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2136: operands[1] = alter_subreg (operands[1]);
2137:
2138: /* If we are being called from reload, it is possible that operands[1]
2139: is a hard non-fp register. So handle those cases. */
2140: if (reload_in_progress && GET_CODE (operands[1]) == REG
2141: && REGNO (operands[1]) < 32)
2142: {
2143: rtx stack_slot;
2144:
2145: /* Remember that we only see a pseudo here if it didn't get a hard
2146: register, so it is memory. */
2147: if (GET_CODE (operands[0]) == MEM
2148: || (GET_CODE (operands[0]) == REG
2149: && (REGNO (operands[0]) < 32
2150: || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER))
2151: || (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32))
2152: {
2153: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2154: operand_subword (operands[1], 0, 0, SFmode));
2155: DONE;
2156: }
2157:
2158: stack_slot = gen_rtx (MEM, SFmode, plus_constant (stack_pointer_rtx, 4));
2159: emit_move_insn (stack_slot, operands[1]);
2160: emit_move_insn (operands[0], stack_slot);
2161: DONE;
2162: }
2163:
2164: if (GET_CODE (operands[0]) == MEM)
2165: operands[1] = force_reg (SFmode, operands[1]);
2166:
2167: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2168: {
2169: rtx stack_slot;
2170:
2171: if (GET_CODE (operands[1]) == MEM
2172: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2173: || GET_CODE (operands[1]) == CONST_DOUBLE
2174: #endif
2175: || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2176: || (reload_in_progress && GET_CODE (operands[1]) == REG
2177: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2178: {
2179: emit_move_insn (operand_subword (operands[0], 0, 0, SFmode),
2180: operand_subword (operands[1], 0, 0, SFmode));
2181: DONE;
2182: }
2183:
2184: if (reload_in_progress)
2185: stack_slot = gen_rtx (MEM, SFmode,
2186: plus_constant (stack_pointer_rtx, 4));
2187: else
2188: stack_slot = assign_stack_temp (SFmode, 4, 0);
2189: emit_move_insn (stack_slot, operands[1]);
2190: emit_move_insn (operands[0], stack_slot);
2191: DONE;
2192: }
2193:
2194: if (CONSTANT_P (operands[1]))
2195: {
2196: operands[1] = force_const_mem (SFmode, operands[1]);
2197: if (! memory_address_p (SFmode, XEXP (operands[1], 0))
2198: && ! reload_in_progress)
2199: operands[1] = change_address (operands[1], SFmode,
2200: XEXP (operands[1], 0));
2201: }
2202: }")
2203:
2204: (define_insn ""
2205: [(set (match_operand:SF 0 "gen_reg_operand" "=r,r")
2206: (match_operand:SF 1 "mem_or_easy_const_operand" "G,m"))]
2207: "REGNO (operands[0]) <= 31"
2208: "@
2209: #
2210: l%U1%X1 %0,%1"
2211: [(set_attr "type" "*,load")])
2212:
2213: (define_split
2214: [(set (match_operand:SF 0 "gen_reg_operand" "")
2215: (match_operand:SF 1 "easy_fp_constant" ""))]
2216: "reload_completed && REGNO (operands[0]) <= 31"
2217: [(set (match_dup 2) (match_dup 3))]
2218: "
2219: { operands[2] = operand_subword (operands[0], 0, 0, SFmode);
2220: operands[3] = operand_subword (operands[1], 0, 0, SFmode); }")
2221:
2222: (define_insn ""
2223: [(set (match_operand:SF 0 "fp_reg_or_mem_operand" "=f,f,m")
2224: (match_operand:SF 1 "input_operand" "f,m,f"))]
2225: "gen_reg_operand (operands[0], SFmode)
2226: || gen_reg_operand (operands[1], SFmode)"
2227: "@
2228: fmr %0,%1
2229: lfs%U1%X1 %0,%1
2230: frsp %1,%1\;stfs%U0%X0 %1,%0"
2231: [(set_attr "type" "fp,load,*")])
2232:
2233: (define_expand "movdf"
2234: [(set (match_operand:DF 0 "nonimmediate_operand" "")
2235: (match_operand:DF 1 "any_operand" ""))]
2236: ""
2237: "
2238: {
2239: /* If we are called from reload, we might be getting a SUBREG of a hard
2240: reg. So expand it. */
2241: if (GET_CODE (operands[0]) == SUBREG
2242: && GET_CODE (SUBREG_REG (operands[0])) == REG
2243: && REGNO (SUBREG_REG (operands[0])) < FIRST_PSEUDO_REGISTER)
2244: operands[0] = alter_subreg (operands[0]);
2245: if (GET_CODE (operands[1]) == SUBREG
2246: && GET_CODE (SUBREG_REG (operands[1])) == REG
2247: && REGNO (SUBREG_REG (operands[1])) < FIRST_PSEUDO_REGISTER)
2248: operands[1] = alter_subreg (operands[1]);
2249:
2250: /* If we are being called from reload, it is possible that operands[1]
2251: is a hard non-fp register. So handle those cases. */
2252: if (reload_in_progress && GET_CODE (operands[1]) == REG
2253: && REGNO (operands[1]) < 32)
2254: {
2255: rtx stack_slot;
2256:
2257: /* Remember that we only see a pseudo here if it didn't get a hard
2258: register, so it is memory. */
2259: if (GET_CODE (operands[0]) == MEM
2260: || (GET_CODE (operands[0]) == REG
2261: && (REGNO (operands[0]) < 32
2262: || REGNO (operands[0]) >= FIRST_PSEUDO_REGISTER)))
2263: {
2264: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2265: operand_subword (operands[1], 0, 0, DFmode));
2266: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2267: operand_subword (operands[1], 1, 0, DFmode));
2268: DONE;
2269: }
2270:
2271: stack_slot = gen_rtx (MEM, DFmode, plus_constant (stack_pointer_rtx, 8));
2272: emit_move_insn (stack_slot, operands[1]);
2273: emit_move_insn (operands[0], stack_slot);
2274: DONE;
2275: }
2276:
2277: if (GET_CODE (operands[0]) == MEM)
2278: {
2279: if (GET_CODE (operands[1]) == MEM)
2280: {
2281: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2282: operand_subword (operands[1], 0, 0, DFmode));
2283: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2284: operand_subword (operands[1], 1, 0, DFmode));
2285: DONE;
2286: }
2287:
2288: operands[1] = force_reg (DFmode, operands[1]);
2289: }
2290:
2291: if (GET_CODE (operands[0]) == REG && REGNO (operands[0]) < 32)
2292: {
2293: rtx stack_slot;
2294:
2295: if (GET_CODE (operands[1]) == MEM
2296: #if HOST_FLOAT_FORMAT == TARGET_FLOAT_FORMAT && ! defined(REAL_IS_NOT_DOUBLE)
2297: || GET_CODE (operands[1]) == CONST_DOUBLE
2298: #endif
2299: || (GET_CODE (operands[1]) == REG && REGNO (operands[1]) < 32)
2300: || (reload_in_progress && GET_CODE (operands[1]) == REG
2301: && REGNO (operands[1]) >= FIRST_PSEUDO_REGISTER))
2302: {
2303: emit_move_insn (operand_subword (operands[0], 0, 0, DFmode),
2304: operand_subword (operands[1], 0, 0, DFmode));
2305: emit_move_insn (operand_subword (operands[0], 1, 0, DFmode),
2306: operand_subword (operands[1], 1, 0, DFmode));
2307: DONE;
2308: }
2309:
2310: if (reload_in_progress)
2311: stack_slot = gen_rtx (MEM, DFmode,
2312: plus_constant (stack_pointer_rtx, 8));
2313: else
2314: stack_slot = assign_stack_temp (DFmode, 8, 0);
2315: emit_move_insn (stack_slot, operands[1]);
2316: emit_move_insn (operands[0], stack_slot);
2317: DONE;
2318: }
2319:
2320: if (CONSTANT_P (operands[1]))
2321: {
2322: operands[1] = force_const_mem (DFmode, operands[1]);
2323: if (! memory_address_p (DFmode, XEXP (operands[1], 0))
2324: && ! reload_in_progress)
2325: operands[1] = change_address (operands[1], DFmode,
2326: XEXP (operands[1], 0));
2327: }
2328: }")
2329:
2330: (define_insn ""
2331: [(set (match_operand:DF 0 "gen_reg_operand" "=r,r")
2332: (match_operand:DF 1 "mem_or_easy_const_operand" "G,m"))]
2333: "REGNO (operands[0]) <= 31"
2334: "@
2335: #
2336: l %0,%1\;l %L0,%L1"
2337: [(set_attr "type" "*,load")])
2338:
2339: (define_split
2340: [(set (match_operand:DF 0 "gen_reg_operand" "")
2341: (match_operand:DF 1 "easy_fp_constant" ""))]
2342: "reload_completed && REGNO (operands[0]) <= 31"
2343: [(set (match_dup 2) (match_dup 3))
2344: (set (match_dup 4) (match_dup 5))]
2345: "
2346: { operands[2] = operand_subword (operands[0], 0, 0, DFmode);
2347: operands[3] = operand_subword (operands[1], 0, 0, DFmode);
2348: operands[4] = operand_subword (operands[0], 1, 0, DFmode);
2349: operands[5] = operand_subword (operands[1], 1, 0, DFmode); }")
2350:
2351: (define_insn ""
2352: [(set (match_operand:DF 0 "fp_reg_or_mem_operand" "=f,f,m")
2353: (match_operand:DF 1 "fp_reg_or_mem_operand" "f,m,f"))]
2354: "gen_reg_operand (operands[0], DFmode)
2355: || gen_reg_operand (operands[1], DFmode)"
2356: "@
2357: fmr %0,%1
2358: lfd%U1%X1 %0,%1
2359: stfd%U0%X0 %1,%0"
2360: [(set_attr "type" "fp,load,*")])
2361:
2362: ;; Next come the multi-word integer load and store and the load and store
2363: ;; multiple insns.
2364: (define_expand "movdi"
2365: [(set (match_operand:DI 0 "general_operand" "")
2366: (match_operand:DI 1 "general_operand" ""))]
2367: ""
2368: "
2369: {
2370: if (GET_CODE (operands[0]) == MEM)
2371: operands[1] = force_reg (DImode, operands[1]);
2372:
2373: else if (GET_CODE (operands[1]) == CONST_DOUBLE
2374: || GET_CODE (operands[1]) == CONST_INT)
2375: {
2376: emit_move_insn (operand_subword (operands[0], 0, 0, DImode),
2377: operand_subword (operands[1], 0, 0, DImode));
2378: emit_move_insn (operand_subword (operands[0], 1, 0, DImode),
2379: operand_subword (operands[1], 1, 0, DImode));
2380: DONE;
2381: }
2382: }")
2383:
2384: (define_insn ""
2385: [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
2386: (match_operand:DI 1 "input_operand" "r,m,r"))]
2387: "gen_reg_operand (operands[0], DImode)
2388: || gen_reg_operand (operands[1], DImode)"
2389: "*
2390: {
2391: switch (which_alternative)
2392: {
2393: case 0:
2394: /* We normally copy the low-numbered register first. However, if
2395: the first register operand 0 is the same as the second register of
2396: operand 1, we must copy in the opposite order. */
2397: if (REGNO (operands[0]) == REGNO (operands[1]) + 1)
2398: return \"oril %L0,%L1,0\;oril %0,%1,0\";
2399: else
2400: return \"oril %0,%1,0\;oril %L0,%L1,0\";
2401: case 1:
2402: /* If the low-address word is used in the address, we must load it
2403: last. Otherwise, load it first. Note that we cannot have
2404: auto-increment in that case since the address register is known to be
2405: dead. */
2406: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2407: operands [1], 0))
2408: return \"l %L0,%L1\;l %0,%1\";
2409: else
2410: return \"l%U1 %0,%1\;l %L0,%L1\";
2411: case 2:
2412: return \"st%U0 %1,%0\;st %L1,%L0\";
2413: }
2414: }"
2415: [(set_attr "type" "*,load,*")])
2416:
2417: ;; TImode is similar, except that we usually want to compute the address into
2418: ;; a register and use lsi/stsi (the exception is during reload). MQ is also
2419: ;; clobbered in stsi, so we need a SCRATCH for it.
2420: (define_expand "movti"
2421: [(parallel [(set (match_operand:TI 0 "general_operand" "")
2422: (match_operand:TI 1 "general_operand" ""))
2423: (clobber (scratch:SI))])]
2424: ""
2425: "
2426: {
2427: if (GET_CODE (operands[0]) == MEM)
2428: operands[1] = force_reg (TImode, operands[1]);
2429:
2430: if (GET_CODE (operands[0]) == MEM
2431: && GET_CODE (XEXP (operands[0], 0)) != REG
2432: && ! reload_in_progress)
2433: operands[0] = change_address (operands[0], TImode,
2434: copy_addr_to_reg (XEXP (operands[0], 0)));
2435:
2436: if (GET_CODE (operands[1]) == MEM
2437: && GET_CODE (XEXP (operands[1], 0)) != REG
2438: && ! reload_in_progress)
2439: operands[1] = change_address (operands[1], TImode,
2440: copy_addr_to_reg (XEXP (operands[1], 0)));
2441: }")
2442:
2443: ;; We say that MQ is clobbered in the last alternative because the first
2444: ;; alternative would never get used otherwise since it would need a reload
2445: ;; while the 2nd alternative would not. We put memory cases first so they
2446: ;; are preferred. Otherwise, we'd try to reload the output instead of
2447: ;; giving the SCRATCH mq.
2448: (define_insn ""
2449: [(set (match_operand:TI 0 "reg_or_mem_operand" "=Q,m,r,r,r")
2450: (match_operand:TI 1 "reg_or_mem_operand" "r,r,r,Q,m"))
2451: (clobber (match_scratch:SI 2 "=q,q#X,X,X,X"))]
2452: "gen_reg_operand (operands[0], TImode)
2453: || gen_reg_operand (operands[1], TImode)"
2454: "*
2455: {
2456: switch (which_alternative)
2457: {
2458: case 0:
2459: return \"stsi %1,%P0,16\";
2460:
2461: case 1:
2462: return \"st%U0 %1,%0\;st %L1,%L0\;st %Y1,%Y0\;st %Z1,%Z0\";
2463:
2464: case 2:
2465: /* Normally copy registers with lowest numbered register copied first.
2466: But copy in the other order if the first register of the output
2467: is the second, third, or fourth register in the input. */
2468: if (REGNO (operands[0]) >= REGNO (operands[1]) + 1
2469: && REGNO (operands[0]) <= REGNO (operands[1]) + 3)
2470: return \"oril %Z0,%Z1,0\;oril %Y0,%Y1,0\;oril %L0,%L1,0\;oril %0,%1,0\";
2471: else
2472: return \"oril %0,%1,0\;oril %L0,%L1,0\;oril %Y0,%Y1,0\;oril %Z0,%Z1,0\";
2473: case 3:
2474: /* If the address is not used in the output, we can use lsi. Otherwise,
2475: fall through to generating four loads. */
2476: if (! reg_overlap_mentioned_p (operands[0], operands[1]))
2477: return \"lsi %0,%P1,16\";
2478: /* ... fall through ... */
2479: case 4:
2480: /* If the address register is the same as the register for the lowest-
2481: addressed word, load it last. Similarly for the next two words.
2482: Otherwise load lowest address to highest. */
2483: if (refers_to_regno_p (REGNO (operands[0]), REGNO (operands[0]) + 1,
2484: operands[1], 0))
2485: return \"l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\;l %0,%1\";
2486: else if (refers_to_regno_p (REGNO (operands[0]) + 1,
2487: REGNO (operands[0]) + 2, operands[1], 0))
2488: return \"l %0,%1\;l %Y0,%Y1\;l %Z0,%Z1\;l %L0,%L1\";
2489: else if (refers_to_regno_p (REGNO (operands[0]) + 2,
2490: REGNO (operands[0]) + 3, operands[1], 0))
2491: return \"l %0,%1\;l %L0,%L1\;l %Z0,%Z1\;l %Y0,%Y1\";
2492: else
2493: return \"l%U1 %0,%1\;l %L0,%L1\;l %Y0,%Y1\;l %Z0,%Z1\";
2494: }
2495: }"
2496: [(set_attr "type" "*,load,load,*,*")])
2497:
2498: (define_expand "load_multiple"
2499: [(match_parallel 3 "" [(set (match_operand:SI 0 "" "")
2500: (match_operand:SI 1 "" ""))
2501: (use (match_operand:SI 2 "" ""))])]
2502: ""
2503: "
2504: {
2505: int regno;
2506: int count;
2507: rtx from;
2508: int i;
2509:
2510: /* Support only loading a constant number of fixed-point registers from
2511: memory and only bother with this if more than two; the machine
2512: doesn't support more than eight. */
2513: if (GET_CODE (operands[2]) != CONST_INT
2514: || INTVAL (operands[2]) <= 2
2515: || INTVAL (operands[2]) > 8
2516: || GET_CODE (operands[1]) != MEM
2517: || GET_CODE (operands[0]) != REG
2518: || REGNO (operands[0]) >= 32)
2519: FAIL;
2520:
2521: count = INTVAL (operands[2]);
2522: regno = REGNO (operands[0]);
2523:
2524: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count));
2525: from = force_reg (SImode, XEXP (operands[1], 0));
2526:
2527: for (i = 0; i < count; i++)
2528: XVECEXP (operands[3], 0, i)
2529: = gen_rtx (SET, VOIDmode, gen_rtx (REG, SImode, regno + i),
2530: gen_rtx (MEM, SImode, plus_constant (from, i * 4)));
2531: }")
2532:
2533: (define_insn ""
2534: [(match_parallel 0 "load_multiple_operation"
2535: [(set (match_operand:SI 1 "gen_reg_operand" "=r")
2536: (match_operand:SI 2 "indirect_operand" "Q"))])]
2537: ""
2538: "*
2539: {
2540: /* We have to handle the case where the pseudo used to contain the address
2541: is assigned to one of the output registers. In that case, do the
2542: lsi, but then load the correct value. This is a bit of a mess, but is
2543: the best we can do. */
2544: static char result[100];
2545: char newload[40];
2546: int i;
2547:
2548: strcpy (result, \"lsi %1,%P2,%N0\");
2549: for (i = 0; i < XVECLEN (operands[0], 0); i++)
2550: if (refers_to_regno_p (REGNO (operands[1]) + i,
2551: REGNO (operands[1]) + i + 1, operands[2], 0))
2552: {
2553: sprintf (newload, \"\;l %d,%d(%d)\",
2554: REGNO (operands[1]) + i,
2555: i * 4, REGNO (XEXP (operands[2], 0)));
2556: strcat (result, newload);
2557: }
2558:
2559: return result;
2560: }"
2561: [(set_attr "type" "load")])
2562:
2563: (define_expand "store_multiple"
2564: [(match_parallel 3 "" [(set (match_operand:SI 0 "" "")
2565: (match_operand:SI 1 "" ""))
2566: (clobber (scratch:SI))
2567: (use (match_operand:SI 2 "" ""))])]
2568: ""
2569: "
2570: {
2571: int regno;
2572: int count;
2573: rtx to;
2574: int i;
2575:
2576: /* Support only storing a constant number of fixed-point registers to
2577: memory and only bother with this if more than two; the machine
2578: doesn't support more than eight. */
2579: if (GET_CODE (operands[2]) != CONST_INT
2580: || INTVAL (operands[2]) <= 2
2581: || INTVAL (operands[2]) > 8
2582: || GET_CODE (operands[0]) != MEM
2583: || GET_CODE (operands[1]) != REG
2584: || REGNO (operands[1]) >= 32)
2585: FAIL;
2586:
2587: count = INTVAL (operands[2]);
2588: regno = REGNO (operands[1]);
2589:
2590: operands[3] = gen_rtx (PARALLEL, VOIDmode, rtvec_alloc (count + 1));
2591: to = force_reg (SImode, XEXP (operands[0], 0));
2592:
2593: XVECEXP (operands[3], 0, 0)
2594: = gen_rtx (SET, VOIDmode, gen_rtx (MEM, SImode, to), operands[1]);
2595: XVECEXP (operands[3], 0, 1) = gen_rtx (CLOBBER, VOIDmode,
2596: gen_rtx (SCRATCH, SImode));
2597:
2598: for (i = 1; i < count; i++)
2599: XVECEXP (operands[3], 0, i + 1)
2600: = gen_rtx (SET, VOIDmode,
2601: gen_rtx (MEM, SImode, plus_constant (to, i * 4)),
2602: gen_rtx (REG, SImode, regno + i));
2603: }")
2604:
2605: (define_insn ""
2606: [(match_parallel 0 "store_multiple_operation"
2607: [(set (match_operand:SI 1 "indirect_operand" "=Q")
2608: (match_operand:SI 2 "gen_reg_operand" "r"))
2609: (clobber (match_scratch:SI 3 "=q"))])]
2610: ""
2611: "stsi %2,%P1,%O0")
2612:
2613: ;; Define insns that do load or store with update. Some of these we can
2614: ;; get by using pre-decrement or pre-increment, but the hardware can also
2615: ;; do cases where the increment is not the size of the object.
2616: ;;
2617: ;; In all these cases, we use operands 0 and 1 for the register being
2618: ;; incremented because those are the operands that local-alloc will
2619: ;; tie and these are the pair most likely to be tieable (and the ones
2620: ;; that will benefit the most).
2621:
2622: (define_insn ""
2623: [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2624: (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2625: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2626: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2627: (plus:SI (match_dup 1) (match_dup 2)))]
2628: ""
2629: "@
2630: lux %3,%1,%2
2631: lu %3,%2(%1)"
2632: [(set_attr "type" "load,load")])
2633:
2634: (define_insn ""
2635: [(set (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2636: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2637: (match_operand:SI 3 "gen_reg_operand" "r,r"))
2638: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2639: (plus:SI (match_dup 1) (match_dup 2)))]
2640: ""
2641: "@
2642: stux %3,%1,%2
2643: stu %3,%2(%1)")
2644:
2645: (define_insn ""
2646: [(set (match_operand:HI 3 "gen_reg_operand" "=r,r")
2647: (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2648: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2649: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2650: (plus:SI (match_dup 1) (match_dup 2)))]
2651: ""
2652: "@
2653: lhzux %3,%1,%2
2654: lhzu %3,%2(%1)"
2655: [(set_attr "type" "load,load")])
2656:
2657: (define_insn ""
2658: [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2659: (zero_extend:SI
2660: (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2661: (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2662: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2663: (plus:SI (match_dup 1) (match_dup 2)))]
2664: ""
2665: "@
2666: lhzux %3,%1,%2
2667: lhzu %3,%2(%1)"
2668: [(set_attr "type" "load,load")])
2669:
2670: (define_insn ""
2671: [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2672: (sign_extend:SI
2673: (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2674: (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2675: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2676: (plus:SI (match_dup 1) (match_dup 2)))]
2677: ""
2678: "@
2679: lhaux %3,%1,%2
2680: lhau %3,%2(%1)"
2681: [(set_attr "type" "load,load")])
2682:
2683: (define_insn ""
2684: [(set (mem:HI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2685: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2686: (match_operand:HI 3 "gen_reg_operand" "r,r"))
2687: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2688: (plus:SI (match_dup 1) (match_dup 2)))]
2689: ""
2690: "@
2691: sthux %3,%1,%2
2692: sthu %3,%2(%1)"
2693: [(set_attr "type" "load,load")])
2694:
2695: (define_insn ""
2696: [(set (match_operand:QI 3 "gen_reg_operand" "=r,r")
2697: (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2698: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2699: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2700: (plus:SI (match_dup 1) (match_dup 2)))]
2701: ""
2702: "@
2703: lbzux %3,%1,%2
2704: lbzu %3,%2(%1)"
2705: [(set_attr "type" "load,load")])
2706:
2707: (define_insn ""
2708: [(set (match_operand:SI 3 "gen_reg_operand" "=r,r")
2709: (zero_extend:SI
2710: (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2711: (match_operand:SI 2 "reg_or_short_operand" "r,I")))))
2712: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2713: (plus:SI (match_dup 1) (match_dup 2)))]
2714: ""
2715: "@
2716: lbzux %3,%1,%2
2717: lbzu %3,%2(%1)"
2718: [(set_attr "type" "load,load")])
2719:
2720: (define_insn ""
2721: [(set (mem:QI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2722: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2723: (match_operand:QI 3 "gen_reg_operand" "r,r"))
2724: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2725: (plus:SI (match_dup 1) (match_dup 2)))]
2726: ""
2727: "@
2728: stbux %3,%1,%2
2729: stbu %3,%2(%1)")
2730:
2731: (define_insn ""
2732: [(set (match_operand:SF 3 "gen_reg_operand" "=f,f")
2733: (mem:SI (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2734: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2735: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2736: (plus:SI (match_dup 1) (match_dup 2)))]
2737: ""
2738: "@
2739: lfsux %3,%1,%2
2740: lfsu %3,%2(%1)"
2741: [(set_attr "type" "load,load")])
2742:
2743: (define_insn ""
2744: [(set (mem:SF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2745: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2746: (match_operand:SF 3 "gen_reg_operand" "f,f"))
2747: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2748: (plus:SI (match_dup 1) (match_dup 2)))]
2749: ""
2750: "@
2751: frsp %3,%3\;stfsux %3,%1,%2
2752: frsp %3,%3\;stfsu %3,%2(%1)")
2753:
2754: (define_insn ""
2755: [(set (match_operand:DF 3 "gen_reg_operand" "=f,f")
2756: (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2757: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))
2758: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2759: (plus:SI (match_dup 1) (match_dup 2)))]
2760: ""
2761: "@
2762: lfdux %3,%1,%2
2763: lfdu %3,%2(%1)"
2764: [(set_attr "type" "load,load")])
2765:
2766: (define_insn ""
2767: [(set (mem:DF (plus:SI (match_operand:SI 1 "gen_reg_operand" "0,0")
2768: (match_operand:SI 2 "reg_or_short_operand" "r,I")))
2769: (match_operand:DF 3 "gen_reg_operand" "f,f"))
2770: (set (match_operand:SI 0 "gen_reg_operand" "=b,b")
2771: (plus:SI (match_dup 1) (match_dup 2)))]
2772: ""
2773: "@
2774: stfdux %3,%1,%2
2775: stfdu %3,%2(%1)")
2776:
2777: ;; Next come insns related to the calling sequence.
2778: ;;
2779: ;; First, an insn to allocate new stack space for dynamic use (e.g., alloca).
1.1.1.2 ! root 2780: ;; We move the back-chain and decrement the stack pointer. This is slightly
1.1 root 2781: ;; less efficient than it needs to be for long constants, but that case
2782: ;; should be rare.
2783:
2784: (define_expand "allocate_stack"
2785: [(set (reg:SI 1)
2786: (minus:SI (reg:SI 1) (match_operand:SI 0 "reg_or_cint_operand" "")))]
2787: ""
2788: "
2789: { rtx chain = gen_reg_rtx (SImode);
2790: rtx stack_bot = gen_rtx (MEM, Pmode, stack_pointer_rtx);
2791:
2792: emit_move_insn (chain, stack_bot);
2793: emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, operands[0]));
2794: emit_move_insn (stack_bot, chain);
2795: DONE;
2796: }")
2797:
2798: ;; A function pointer is a pointer to a data area whose first word contains
2799: ;; the actual address of the function, whose second word contains a pointer
2800: ;; to its TOC, and whose third word contains a value to place in the static
2801: ;; chain register (r11). Note that if we load the static chain, our
2802: ;; "trampoline" need not have any executable code.
2803: ;;
2804: ;; operands[0] is an SImode pseudo in which we place the address of the
2805: ;; function.
2806: ;; operands[1] is the address of data area of the function to call
2807:
2808: (define_expand "call_via_ptr"
2809: [(set (match_operand:SI 0 "gen_reg_operand" "")
2810: (mem:SI (match_operand:SI 1 "gen_reg_operand" "")))
2811: (set (mem:SI (plus:SI (reg:SI 1) (const_int 20)))
2812: (reg:SI 2))
2813: (set (reg:SI 2)
2814: (mem:SI (plus:SI (match_dup 1)
2815: (const_int 4))))
2816: (set (reg:SI 11)
2817: (mem:SI (plus:SI (match_dup 1)
2818: (const_int 8))))
2819: (use (reg:SI 2))
2820: (use (reg:SI 11))]
2821: ""
2822: "")
2823:
2824: (define_expand "call"
2825: [(parallel [(call (mem:SI (match_operand:SI 0 "address_operand" ""))
2826: (match_operand 1 "" ""))
2827: (clobber (scratch:SI))])]
2828: ""
2829: "
2830: {
2831: if (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != CONST_INT)
2832: abort ();
2833:
2834: operands[0] = XEXP (operands[0], 0);
2835: if (GET_CODE (operands[0]) != SYMBOL_REF)
2836: {
2837: rtx temp = gen_reg_rtx (SImode);
2838:
2839: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[0])));
2840: operands[0] = temp;
2841: }
2842: }")
2843:
2844: (define_expand "call_value"
2845: [(parallel [(set (match_operand 0 "" "")
2846: (call (mem:SI (match_operand:SI 1 "address_operand" ""))
2847: (match_operand 2 "" "")))
2848: (clobber (scratch:SI))])]
2849: ""
2850: "
2851: {
2852: if (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != CONST_INT)
2853: abort ();
2854:
2855: operands[1] = XEXP (operands[1], 0);
2856: if (GET_CODE (operands[1]) != SYMBOL_REF)
2857: {
2858: rtx temp = gen_reg_rtx (SImode);
2859:
2860: emit_insn (gen_call_via_ptr (temp, force_reg (SImode, operands[1])));
2861: operands[1] = temp;
2862: }
2863: }")
2864:
2865: (define_insn ""
2866: [(call (mem:SI (match_operand:SI 0 "call_operand" "l,s"))
2867: (match_operand 1 "" "fg,fg"))
2868: (clobber (match_scratch:SI 3 "=l,l"))]
2869: ""
2870: "@
2871: brl\;l 2,20(1)
2872: bl %z0\;cror 15,15,15")
2873:
2874: (define_insn ""
2875: [(set (match_operand 0 "" "fg,fg")
2876: (call (mem:SI (match_operand:SI 1 "call_operand" "l,s"))
2877: (match_operand 2 "" "fg,fg")))
2878: (clobber (match_scratch:SI 3 "=l,l"))]
2879: ""
2880: "@
2881: brl\;l 2,20(1)
2882: bl %z1\;cror 15,15,15")
2883:
2884: ;; Compare insns are next. Note that the RS/6000 has two types of compares,
2885: ;; signed & unsigned, and one type of branch.
2886: ;;
2887: ;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc
2888: ;; insns, and branches. We store the operands of compares until we see
2889: ;; how it is used.
2890: (define_expand "cmpsi"
2891: [(set (cc0)
2892: (compare (match_operand:SI 0 "gen_reg_operand" "")
2893: (match_operand:SI 1 "reg_or_short_operand" "")))]
2894: ""
2895: "
2896: {
2897: /* Take care of the possibility that operands[1] might be negative but
2898: this might be a logical operation. That insn doesn't exist. */
2899: if (GET_CODE (operands[1]) == CONST_INT
2900: && INTVAL (operands[1]) < 0)
2901: operands[1] = force_reg (SImode, operands[1]);
2902:
2903: rs6000_compare_op0 = operands[0];
2904: rs6000_compare_op1 = operands[1];
2905: rs6000_compare_fp_p = 0;
2906: DONE;
2907: }")
2908:
2909: (define_expand "cmpsf"
2910: [(set (cc0) (compare (match_operand:SF 0 "gen_reg_operand" "")
2911: (match_operand:SF 1 "gen_reg_operand" "")))]
2912: ""
2913: "
2914: {
2915: rs6000_compare_op0 = operands[0];
2916: rs6000_compare_op1 = operands[1];
2917: rs6000_compare_fp_p = 1;
2918: DONE;
2919: }")
2920:
2921: (define_expand "cmpdf"
2922: [(set (cc0) (compare (match_operand:DF 0 "gen_reg_operand" "")
2923: (match_operand:DF 1 "gen_reg_operand" "")))]
2924: ""
2925: "
2926: {
2927: rs6000_compare_op0 = operands[0];
2928: rs6000_compare_op1 = operands[1];
2929: rs6000_compare_fp_p = 1;
2930: DONE;
2931: }")
2932:
2933: (define_expand "beq"
2934: [(set (match_dup 2) (match_dup 1))
2935: (set (pc)
2936: (if_then_else (eq (match_dup 2)
2937: (const_int 0))
2938: (label_ref (match_operand 0 "" ""))
2939: (pc)))]
2940: ""
2941: "
2942: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
2943: operands[1] = gen_rtx (COMPARE, mode,
2944: rs6000_compare_op0, rs6000_compare_op1);
2945: operands[2] = gen_reg_rtx (mode);
2946: }")
2947:
2948: (define_expand "bne"
2949: [(set (match_dup 2) (match_dup 1))
2950: (set (pc)
2951: (if_then_else (ne (match_dup 2)
2952: (const_int 0))
2953: (label_ref (match_operand 0 "" ""))
2954: (pc)))]
2955: ""
2956: "
2957: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
2958: operands[1] = gen_rtx (COMPARE, mode,
2959: rs6000_compare_op0, rs6000_compare_op1);
2960: operands[2] = gen_reg_rtx (mode);
2961: }")
2962:
2963: (define_expand "blt"
2964: [(set (match_dup 2) (match_dup 1))
2965: (set (pc)
2966: (if_then_else (lt (match_dup 2)
2967: (const_int 0))
2968: (label_ref (match_operand 0 "" ""))
2969: (pc)))]
2970: ""
2971: "
2972: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
2973: operands[1] = gen_rtx (COMPARE, mode,
2974: rs6000_compare_op0, rs6000_compare_op1);
2975: operands[2] = gen_reg_rtx (mode);
2976: }")
2977:
2978: (define_expand "bgt"
2979: [(set (match_dup 2) (match_dup 1))
2980: (set (pc)
2981: (if_then_else (gt (match_dup 2)
2982: (const_int 0))
2983: (label_ref (match_operand 0 "" ""))
2984: (pc)))]
2985: ""
2986: "
2987: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
2988: operands[1] = gen_rtx (COMPARE, mode,
2989: rs6000_compare_op0, rs6000_compare_op1);
2990: operands[2] = gen_reg_rtx (mode);
2991: }")
2992:
2993: (define_expand "ble"
2994: [(set (match_dup 2) (match_dup 1))
2995: (set (pc)
2996: (if_then_else (le (match_dup 2)
2997: (const_int 0))
2998: (label_ref (match_operand 0 "" ""))
2999: (pc)))]
3000: ""
3001: "
3002: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3003: operands[1] = gen_rtx (COMPARE, mode,
3004: rs6000_compare_op0, rs6000_compare_op1);
3005: operands[2] = gen_reg_rtx (mode);
3006: }")
3007:
3008: (define_expand "bge"
3009: [(set (match_dup 2) (match_dup 1))
3010: (set (pc)
3011: (if_then_else (ge (match_dup 2)
3012: (const_int 0))
3013: (label_ref (match_operand 0 "" ""))
3014: (pc)))]
3015: ""
3016: "
3017: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3018: operands[1] = gen_rtx (COMPARE, mode,
3019: rs6000_compare_op0, rs6000_compare_op1);
3020: operands[2] = gen_reg_rtx (mode);
3021: }")
3022:
3023: (define_expand "bgtu"
3024: [(set (match_dup 2) (match_dup 1))
3025: (set (pc)
3026: (if_then_else (gtu (match_dup 2)
3027: (const_int 0))
3028: (label_ref (match_operand 0 "" ""))
3029: (pc)))]
3030: ""
3031: "
3032: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3033: rs6000_compare_op0, rs6000_compare_op1);
3034: operands[2] = gen_reg_rtx (CCUNSmode);
3035: }")
3036:
3037: (define_expand "bltu"
3038: [(set (match_dup 2) (match_dup 1))
3039: (set (pc)
3040: (if_then_else (ltu (match_dup 2)
3041: (const_int 0))
3042: (label_ref (match_operand 0 "" ""))
3043: (pc)))]
3044: ""
3045: "
3046: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3047: rs6000_compare_op0, rs6000_compare_op1);
3048: operands[2] = gen_reg_rtx (CCUNSmode);
3049: }")
3050:
3051: (define_expand "bgeu"
3052: [(set (match_dup 2) (match_dup 1))
3053: (set (pc)
3054: (if_then_else (geu (match_dup 2)
3055: (const_int 0))
3056: (label_ref (match_operand 0 "" ""))
3057: (pc)))]
3058: ""
3059: "
3060: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3061: rs6000_compare_op0, rs6000_compare_op1);
3062: operands[2] = gen_reg_rtx (CCUNSmode);
3063: }")
3064:
3065: (define_expand "bleu"
3066: [(set (match_dup 2) (match_dup 1))
3067: (set (pc)
3068: (if_then_else (leu (match_dup 2)
3069: (const_int 0))
3070: (label_ref (match_operand 0 "" ""))
3071: (pc)))]
3072: ""
3073: "
3074: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3075: rs6000_compare_op0, rs6000_compare_op1);
3076: operands[2] = gen_reg_rtx (CCUNSmode);
3077: }")
3078:
3079: ;; For SNE, we would prefer that the xor/abs sequence be used for integers.
3080: ;; For SEQ, likewise, except that comparisons with zero should be done
3081: ;; with an scc insns. However, due to the order that combine see the
3082: ;; resulting insns, we must, in fact, allow SEQ for integers. Fail in
3083: ;; the cases we don't want to handle.
3084: (define_expand "seq"
3085: [(set (match_dup 2) (match_dup 1))
3086: (set (match_operand:SI 0 "gen_reg_operand" "")
3087: (eq:SI (match_dup 2) (const_int 0)))]
3088: ""
3089: "
3090: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3091: operands[1] = gen_rtx (COMPARE, mode,
3092: rs6000_compare_op0, rs6000_compare_op1);
3093: operands[2] = gen_reg_rtx (mode);
3094: }")
3095:
3096: (define_expand "sne"
3097: [(set (match_dup 2) (match_dup 1))
3098: (set (match_operand:SI 0 "gen_reg_operand" "")
3099: (ne:SI (match_dup 2) (const_int 0)))]
3100: ""
3101: "
3102: { if (! rs6000_compare_fp_p)
3103: FAIL;
3104:
3105: operands[1] = gen_rtx (COMPARE, CCFPmode,
3106: rs6000_compare_op0, rs6000_compare_op1);
3107: operands[2] = gen_reg_rtx (CCFPmode);
3108: }")
3109:
3110: ;; A > 0 is best done using the portable sequence, so fail in that case.
3111: (define_expand "sgt"
3112: [(set (match_dup 2) (match_dup 1))
3113: (set (match_operand:SI 0 "gen_reg_operand" "")
3114: (gt:SI (match_dup 2) (const_int 0)))]
3115: ""
3116: "
3117: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3118:
3119: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3120: FAIL;
3121:
3122: operands[1] = gen_rtx (COMPARE, mode,
3123: rs6000_compare_op0, rs6000_compare_op1);
3124: operands[2] = gen_reg_rtx (mode);
3125: }")
3126:
3127: ;; A < 0 is best done in the portable way for A an integer.
3128: (define_expand "slt"
3129: [(set (match_dup 2) (match_dup 1))
3130: (set (match_operand:SI 0 "gen_reg_operand" "")
3131: (lt:SI (match_dup 2) (const_int 0)))]
3132: ""
3133: "
3134: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3135:
3136: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3137: FAIL;
3138:
3139: operands[1] = gen_rtx (COMPARE, mode,
3140: rs6000_compare_op0, rs6000_compare_op1);
3141: operands[2] = gen_reg_rtx (mode);
3142: }")
3143:
3144: (define_expand "sge"
3145: [(set (match_dup 2) (match_dup 1))
3146: (set (match_operand:SI 0 "gen_reg_operand" "")
3147: (ge:SI (match_dup 2) (const_int 0)))]
3148: ""
3149: "
3150: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3151: operands[1] = gen_rtx (COMPARE, mode,
3152: rs6000_compare_op0, rs6000_compare_op1);
3153: operands[2] = gen_reg_rtx (mode);
3154: }")
3155:
3156: ;; A <= 0 is best done the portable way for A an integer.
3157: (define_expand "sle"
3158: [(set (match_dup 2) (match_dup 1))
3159: (set (match_operand:SI 0 "gen_reg_operand" "")
3160: (le:SI (match_dup 2) (const_int 0)))]
3161: ""
3162: "
3163: { enum machine_mode mode = rs6000_compare_fp_p ? CCFPmode : CCmode;
3164:
3165: if (! rs6000_compare_fp_p && rs6000_compare_op1 == const0_rtx)
3166: FAIL;
3167:
3168: operands[1] = gen_rtx (COMPARE, mode,
3169: rs6000_compare_op0, rs6000_compare_op1);
3170: operands[2] = gen_reg_rtx (mode);
3171: }")
3172:
3173: (define_expand "sgtu"
3174: [(set (match_dup 2) (match_dup 1))
3175: (set (match_operand:SI 0 "gen_reg_operand" "")
3176: (gtu:SI (match_dup 2) (const_int 0)))]
3177: ""
3178: "
3179: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3180: rs6000_compare_op0, rs6000_compare_op1);
3181: operands[2] = gen_reg_rtx (CCUNSmode);
3182: }")
3183:
3184: (define_expand "sltu"
3185: [(set (match_dup 2) (match_dup 1))
3186: (set (match_operand:SI 0 "gen_reg_operand" "")
3187: (ltu:SI (match_dup 2) (const_int 0)))]
3188: ""
3189: "
3190: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3191: rs6000_compare_op0, rs6000_compare_op1);
3192: operands[2] = gen_reg_rtx (CCUNSmode);
3193: }")
3194:
3195: (define_expand "sgeu"
3196: [(set (match_dup 2) (match_dup 1))
3197: (set (match_operand:SI 0 "gen_reg_operand" "")
3198: (geu:SI (match_dup 2) (const_int 0)))]
3199: ""
3200: "
3201: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3202: rs6000_compare_op0, rs6000_compare_op1);
3203: operands[2] = gen_reg_rtx (CCUNSmode);
3204: }")
3205:
3206: (define_expand "sleu"
3207: [(set (match_dup 2) (match_dup 1))
3208: (set (match_operand:SI 0 "gen_reg_operand" "")
3209: (leu:SI (match_dup 2) (const_int 0)))]
3210: ""
3211: "
3212: { operands[1] = gen_rtx (COMPARE, CCUNSmode,
3213: rs6000_compare_op0, rs6000_compare_op1);
3214: operands[2] = gen_reg_rtx (CCUNSmode);
3215: }")
3216:
3217: ;; Here are the actual compare insns.
3218: (define_insn ""
3219: [(set (match_operand:CC 0 "cc_reg_operand" "=y")
3220: (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
3221: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3222: ""
3223: "cmp%I2 %0,%1,%2"
3224: [(set_attr "type" "compare")])
3225:
3226: (define_insn ""
3227: [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y")
3228: (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r")
3229: (match_operand:SI 2 "reg_or_u_short_operand" "rI")))]
3230: ""
3231: "cmpl%I2 %0,%1,%W2"
3232: [(set_attr "type" "compare")])
3233:
3234: ;; The following two insns don't exist as single insns, but if we provide
3235: ;; them, we can swap an add and compare, which will enable us to overlap more
3236: ;; of the required delay between a compare and branch. We generate code for
3237: ;; them by splitting.
3238:
3239: (define_insn ""
3240: [(set (match_operand:CC 3 "cc_reg_operand" "=y")
3241: (compare:CC (match_operand:SI 1 "gen_reg_operand" "r")
3242: (match_operand:SI 2 "short_cint_operand" "i")))
3243: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3244: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3245: ""
3246: "#")
3247:
3248: (define_insn ""
3249: [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y")
3250: (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "r")
3251: (match_operand:SI 2 "u_short_cint_operand" "i")))
3252: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3253: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))]
3254: ""
3255: "#")
3256:
3257: (define_split
3258: [(set (match_operand:CC 3 "cc_reg_operand" "")
3259: (compare:CC (match_operand:SI 1 "gen_reg_operand" "")
3260: (match_operand:SI 2 "short_cint_operand" "")))
3261: (set (match_operand:SI 0 "gen_reg_operand" "")
3262: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3263: ""
3264: [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2)))
3265: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3266:
3267: (define_split
3268: [(set (match_operand:CCUNS 3 "cc_reg_operand" "")
3269: (compare:CCUNS (match_operand:SI 1 "gen_reg_operand" "")
3270: (match_operand:SI 2 "u_short_cint_operand" "")))
3271: (set (match_operand:SI 0 "gen_reg_operand" "")
3272: (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))]
3273: ""
3274: [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2)))
3275: (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))])
3276:
3277: (define_insn ""
3278: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3279: (compare:CCFP (match_operand:SF 1 "gen_reg_operand" "f")
3280: (match_operand:SF 2 "gen_reg_operand" "f")))]
3281: ""
3282: "fcmpu %0,%1,%2"
3283: [(set_attr "type" "fpcompare")])
3284:
3285: (define_insn ""
3286: [(set (match_operand:CCFP 0 "cc_reg_operand" "=y")
3287: (compare:CCFP (match_operand:DF 1 "gen_reg_operand" "f")
3288: (match_operand:DF 2 "gen_reg_operand" "f")))]
3289: ""
3290: "fcmpu %0,%1,%2"
3291: [(set_attr "type" "fpcompare")])
3292:
3293: ;; Now we have the scc insns. We can do some combinations because of the
3294: ;; way the machine works.
3295: ;;
3296: ;; Note that this is probably faster if we can put an insn between the
3297: ;; mfcr and rlinm, but this is tricky. Let's leave it for now.
3298: (define_insn ""
3299: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3300: (match_operator:SI 1 "scc_comparison_operator"
3301: [(match_operand 2 "cc_reg_operand" "y")
3302: (const_int 0)]))]
3303: ""
3304: "%D1mfcr %0\;rlinm %0,%0,%J1,31,31")
3305:
3306: (define_insn ""
3307: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3308: (compare:CC (match_operator:SI 1 "scc_comparison_operator"
3309: [(match_operand 2 "cc_reg_operand" "y")
3310: (const_int 0)])
3311: (const_int 0)))
3312: (set (match_operand:SI 3 "gen_reg_operand" "=r")
3313: (match_op_dup 1 [(match_dup 2) (const_int 0)]))]
3314: ""
3315: "%D1mfcr %3\;rlinm. %3,%3,%J1,30,31"
3316: [(set_attr "type" "delayed_compare")])
3317:
3318: (define_insn ""
3319: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3320: (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3321: [(match_operand 2 "cc_reg_operand" "y")
3322: (const_int 0)])
3323: (match_operand:SI 3 "const_int_operand" "n")))]
3324: ""
3325: "*
3326: {
3327: int is_bit = ccr_bit (operands[1], 1);
3328: int put_bit = 31 - (INTVAL (operands[3]) & 31);
3329: int count;
3330:
3331: if (is_bit >= put_bit)
3332: count = is_bit - put_bit;
3333: else
3334: count = 32 - (put_bit - is_bit);
3335:
3336: operands[4] = gen_rtx (CONST_INT, VOIDmode, count);
3337: operands[5] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3338:
3339: return \"%D1mfcr %0\;rlinm %0,%0,%4,%5,%5\";
3340: }")
3341:
3342: (define_insn ""
3343: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3344: (compare:CC
3345: (ashift:SI (match_operator:SI 1 "scc_comparison_operator"
3346: [(match_operand 2 "cc_reg_operand" "y")
3347: (const_int 0)])
3348: (match_operand:SI 3 "const_int_operand" "n"))
3349: (const_int 0)))
3350: (set (match_operand:SI 4 "gen_reg_operand" "=r")
3351: (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)])
3352: (match_dup 3)))]
3353: ""
3354: "*
3355: {
3356: int is_bit = ccr_bit (operands[1], 1);
3357: int put_bit = 31 - (INTVAL (operands[3]) & 31);
3358: int count;
3359:
3360: if (is_bit >= put_bit)
3361: count = is_bit - put_bit;
3362: else
3363: count = 32 - (put_bit - is_bit);
3364:
3365: operands[5] = gen_rtx (CONST_INT, VOIDmode, count);
3366: operands[6] = gen_rtx (CONST_INT, VOIDmode, put_bit);
3367:
3368: return \"%D1mfcr %4\;rlinm. %4,%4,%5,%6,%6\";
3369: }"
3370: [(set_attr "type" "delayed_compare")])
3371:
3372: ;; There are some scc insns that can be done directly, without a compare.
3373: ;; These are faster because they don't involve the communications between
3374: ;; the FXU and branch units. In fact, we will be replacing all of the
3375: ;; integer scc insns here or in the portable methods in emit_store_flag.
3376: ;;
3377: ;; Also support (neg (scc ..)) since that construct is used to replace
3378: ;; branches, (plus (scc ..) ..) since that construct is common and
3379: ;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the
3380: ;; cases where it is no more expensive than (neg (scc ..)).
3381:
3382: ;; Have reload force a constant into a register for the simple insns that
3383: ;; otherwise won't accept constants. We do this because it is faster than
3384: ;; the cmp/mfcr sequence we would otherwise generate.
3385:
3386: (define_insn ""
3387: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3388: (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3389: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I")))
3390: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3391: ""
3392: "@
3393: xor %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0
3394: sfi %3,%1,0\;ae %0,%3,%1
3395: xoril %0,%1,%b2\;sfi %3,%0,0\;ae %0,%3,%0
3396: xoriu %0,%1,%u2\;sfi %3,%0,0\;ae %0,%3,%0
3397: sfi %0,%1,%2\;sfi %3,%0,0\;ae %0,%3,%0")
3398:
3399: (define_insn ""
3400: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x")
3401: (compare:CC
3402: (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3403: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3404: (const_int 0)))
3405: (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3406: (eq:SI (match_dup 1) (match_dup 2)))
3407: (clobber (match_scratch:SI 3 "=r,&r,r,r,r"))]
3408: ""
3409: "@
3410: xor %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0
3411: sfi %3,%1,0\;ae. %0,%3,%1
3412: xoril %0,%1,%b2\;sfi %3,%0,0\;ae. %0,%3,%0
3413: xoriu %0,%1,%u2\;sfi %3,%0,0\;ae. %0,%3,%0
3414: sfi %0,%1,%2\;sfi %3,%0,0\;ae. %0,%3,%0"
3415: [(set_attr "type" "compare")])
3416:
3417: (define_insn ""
3418: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3419: (plus:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3420: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3421: (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r")))
3422: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3423: ""
3424: "@
3425: xor %4,%1,%2\;sfi %4,%4,0\;aze %0,%3
3426: sfi %4,%1,0\;aze %0,%3
3427: xoril %4,%1,%b2\;sfi %4,%4,0\;aze %0,%3
3428: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze %0,%3
3429: sfi %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
3430:
3431: (define_insn ""
3432: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x")
3433: (compare:CC
3434: (plus:SI
3435: (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3436: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3437: (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))
3438: (const_int 0)))
3439: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3440: ""
3441: "@
3442: xor %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3
3443: sfi %4,%1,0\;aze. %0,%3
3444: xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %4,%3
3445: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %4,%3
3446: sfi %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
3447: [(set_attr "type" "compare")])
3448:
3449: (define_insn ""
3450: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x,x")
3451: (compare:CC
3452: (plus:SI
3453: (eq:SI (match_operand:SI 1 "gen_reg_operand" "%r,r,r,r,r")
3454: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))
3455: (match_operand:SI 3 "gen_reg_operand" "r,r,r,r,r"))
3456: (const_int 0)))
3457: (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3458: (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3459: (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r"))]
3460: ""
3461: "@
3462: xor %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3
3463: sfi %4,%1,0\;aze. %4,%3
3464: xoril %4,%1,%b2\;sfi %4,%4,0\;aze. %0,%3
3465: xoriu %4,%1,%u2\;sfi %4,%4,0\;aze. %0,%3
3466: sfi %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
3467: [(set_attr "type" "compare")])
3468:
3469: (define_insn ""
3470: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r,r")
3471: (neg:SI (eq:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r,r")
3472: (match_operand:SI 2 "reg_or_cint_operand" "r,O,K,J,I"))))]
3473: ""
3474: "@
3475: xor %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0
3476: ai %0,%1,-1\;sfe %0,%0,%0
3477: xoril %0,%1,%b2\;ai %0,%0,-1\;sfe %0,%0,%0
3478: xoriu %0,%1,%u2\;ai %0,%0,-1\;sfe %0,%0,%0
3479: sfi %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
3480:
3481: ;; This is what (plus (ne X (const_int 0)) Y) looks like.
3482: (define_insn ""
3483: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3484: (plus:SI (lshiftrt:SI
3485: (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
3486: (const_int 31))
3487: (match_operand:SI 2 "gen_reg_operand" "r")))
3488: (clobber (match_scratch:SI 3 "=&r"))]
3489: ""
3490: "ai %3,%1,-1\;aze %0,%2")
3491:
3492: (define_insn ""
3493: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3494: (compare:CC
3495: (plus:SI (lshiftrt:SI
3496: (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
3497: (const_int 31))
3498: (match_operand:SI 2 "gen_reg_operand" "r"))
3499: (const_int 0)))
3500: (clobber (match_scratch:SI 3 "=&r"))]
3501: ""
3502: "ai %3,%1,-1\;aze. %3,%2"
3503: [(set_attr "type" "compare")])
3504:
3505: (define_insn ""
3506: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3507: (compare:CC
3508: (plus:SI (lshiftrt:SI
3509: (neg:SI (abs:SI (match_operand:SI 1 "gen_reg_operand" "r")))
3510: (const_int 31))
3511: (match_operand:SI 2 "gen_reg_operand" "r"))
3512: (const_int 0)))
3513: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3514: (plus:SI (lshiftrt:SI (neg:SI (abs:SI (match_dup 1))) (const_int 31))
3515: (match_dup 2)))
3516: (clobber (match_scratch:SI 3 "=&r"))]
3517: ""
3518: "ai %3,%1,-1\;aze. %0,%2"
3519: [(set_attr "type" "compare")])
3520:
3521: (define_insn ""
3522: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3523: (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3524: (match_operand:SI 2 "reg_or_short_operand" "r,O")))
3525: (clobber (match_scratch:SI 3 "=r,X"))]
3526: ""
3527: "@
3528: doz %3,%2,%1\;sfi %0,%3,0\;ae %0,%0,%3
3529: ai %0,%1,-1\;aze %0,%0\;sri %0,%0,31")
3530:
3531: (define_insn ""
3532: [(set (match_operand:CC 4 "cc_reg_operand" "=x,x")
3533: (compare:CC
3534: (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3535: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3536: (const_int 0)))
3537: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3538: (le:SI (match_dup 1) (match_dup 2)))
3539: (clobber (match_scratch:SI 3 "=r,X"))]
3540: ""
3541: "@
3542: doz %3,%2,%1\;sfi %0,%3,0\;ae. %0,%0,%3
3543: ai %0,%1,-1\;aze %0,%0\;sri. %0,%0,31"
3544: [(set_attr "type" "delayed_compare,compare")])
3545:
3546: (define_insn ""
3547: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3548: (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3549: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3550: (match_operand:SI 3 "gen_reg_operand" "r,r")))
3551: (clobber (match_scratch:SI 4 "=&r,&r"))]
3552: ""
3553: "@
3554: doz %4,%2,%1\;sfi %4,%4,0\;aze %0,%3
3555: srai %4,%1,31\;sf %4,%1,%4\;aze %0,%3")
3556:
3557: (define_insn ""
3558: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
3559: (compare:CC
3560: (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3561: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3562: (match_operand:SI 3 "gen_reg_operand" "r,r"))
3563: (const_int 0)))
3564: (clobber (match_scratch:SI 4 "=&r,&r"))]
3565: ""
3566: "@
3567: doz %4,%2,%1\;sfi %4,%4,0\;aze. %4,%3
3568: srai %4,%1,31\;sf %4,%1,%4\;aze. %4,%3"
3569: [(set_attr "type" "compare")])
3570:
3571: (define_insn ""
3572: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
3573: (compare:CC
3574: (plus:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3575: (match_operand:SI 2 "reg_or_short_operand" "r,O"))
3576: (match_operand:SI 3 "gen_reg_operand" "r,r"))
3577: (const_int 0)))
3578: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3579: (plus:SI (le:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3580: (clobber (match_scratch:SI 4 "=&r,&r"))]
3581: ""
3582: "@
3583: doz %4,%2,%1\;sfi %4,%4,0\;aze. %0,%3
3584: srai %4,%1,31\;sf %4,%1,%4\;aze. %0,%3"
3585: [(set_attr "type" "compare")])
3586:
3587: (define_insn ""
3588: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3589: (neg:SI (le:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3590: (match_operand:SI 2 "reg_or_short_operand" "r,O"))))]
3591: ""
3592: "@
3593: doz %0,%2,%1\;ai %0,%0,-1\;sfe %0,%0,%0
3594: ai %0,%1,-1\;aze %0,%0\;srai %0,%0,31")
3595:
3596: (define_insn ""
3597: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3598: (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3599: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3600: ""
3601: "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae %0,%0,%0")
3602:
3603: (define_insn ""
3604: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
3605: (compare:CC
3606: (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3607: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3608: (const_int 0)))
3609: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3610: (leu:SI (match_dup 1) (match_dup 2)))]
3611: ""
3612: "sf%I2 %0,%1,%2\;cal %0,0(0)\;ae. %0,%0,%0"
3613: [(set_attr "type" "compare")])
3614:
3615: (define_insn ""
3616: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3617: (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3618: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3619: (match_operand:SI 3 "gen_reg_operand" "r")))
3620: (clobber (match_scratch:SI 4 "=&r"))]
3621: ""
3622: "sf%I2 %4,%1,%2\;aze %0,%3")
3623:
3624: (define_insn ""
3625: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3626: (compare:CC
3627: (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3628: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3629: (match_operand:SI 3 "gen_reg_operand" "r"))
3630: (const_int 0)))
3631: (clobber (match_scratch:SI 4 "=&r"))]
3632: ""
3633: "sf%I2 %4,%1,%2\;aze. %4,%3"
3634: [(set_attr "type" "compare")])
3635:
3636: (define_insn ""
3637: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3638: (compare:CC
3639: (plus:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3640: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3641: (match_operand:SI 3 "gen_reg_operand" "r"))
3642: (const_int 0)))
3643: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3644: (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3645: (clobber (match_scratch:SI 4 "=&r"))]
3646: ""
3647: "sf%I2 %4,%1,%2\;aze. %0,%3"
3648: [(set_attr "type" "compare")])
3649:
3650: (define_insn ""
3651: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3652: (neg:SI (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3653: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3654: ""
3655: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;nand %0,%0,%0")
3656:
3657: (define_insn ""
3658: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3659: (and:SI (neg:SI
3660: (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3661: (match_operand:SI 2 "reg_or_short_operand" "rI")))
3662: (match_operand:SI 3 "gen_reg_operand" "r")))
3663: (clobber (match_scratch:SI 4 "=&r"))]
3664: ""
3665: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc %0,%3,%4")
3666:
3667: (define_insn ""
3668: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3669: (compare:CC
3670: (and:SI (neg:SI
3671: (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3672: (match_operand:SI 2 "reg_or_short_operand" "rI")))
3673: (match_operand:SI 3 "gen_reg_operand" "r"))
3674: (const_int 0)))
3675: (clobber (match_scratch:SI 4 "=&r"))]
3676: ""
3677: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %4,%3,%4"
3678: [(set_attr "type" "compare")])
3679:
3680: (define_insn ""
3681: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3682: (compare:CC
3683: (and:SI (neg:SI
3684: (leu:SI (match_operand:SI 1 "gen_reg_operand" "r")
3685: (match_operand:SI 2 "reg_or_short_operand" "rI")))
3686: (match_operand:SI 3 "gen_reg_operand" "r"))
3687: (const_int 0)))
3688: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3689: (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
3690: (clobber (match_scratch:SI 4 "=&r"))]
3691: ""
3692: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;andc. %0,%3,%4"
3693: [(set_attr "type" "compare")])
3694:
3695: (define_insn ""
3696: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3697: (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3698: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
3699: ""
3700: "doz%I2 %0,%1,%2\;nabs %0,%0\;sri %0,%0,31")
3701:
3702: (define_insn ""
3703: [(set (match_operand:SI 3 "cc_reg_operand" "=x")
3704: (compare:CC
3705: (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3706: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3707: (const_int 0)))
3708: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3709: (lt:SI (match_dup 1) (match_dup 2)))]
3710: ""
3711: "doz%I2 %0,%1,%2\;nabs %0,%0\;sri. %0,%0,31"
3712: [(set_attr "type" "delayed_compare")])
3713:
3714: (define_insn ""
3715: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3716: (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3717: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3718: (match_operand:SI 3 "gen_reg_operand" "r")))
3719: (clobber (match_scratch:SI 4 "=&r"))]
3720: ""
3721: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze %0,%3")
3722:
3723: (define_insn ""
3724: [(set (match_operand:SI 0 "cc_reg_operand" "=x")
3725: (compare:CC
3726: (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3727: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3728: (match_operand:SI 3 "gen_reg_operand" "r"))
3729: (const_int 0)))
3730: (clobber (match_scratch:SI 4 "=&r"))]
3731: ""
3732: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %4,%3"
3733: [(set_attr "type" "compare")])
3734:
3735: (define_insn ""
3736: [(set (match_operand:SI 5 "cc_reg_operand" "=x")
3737: (compare:CC
3738: (plus:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3739: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3740: (match_operand:SI 3 "gen_reg_operand" "r"))
3741: (const_int 0)))
3742: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3743: (plus:SI (lt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3744: (clobber (match_scratch:SI 4 "=&r"))]
3745: ""
3746: "doz%I2 %4,%1,%2\;ai %4,%4,-1\;aze. %0,%3"
3747: [(set_attr "type" "compare")])
3748:
3749: (define_insn ""
3750: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3751: (neg:SI (lt:SI (match_operand:SI 1 "gen_reg_operand" "r")
3752: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3753: ""
3754: "doz%I2 %0,%1,%2\;nabs %0,%0\;srai %0,%0,31")
3755:
3756: (define_insn ""
3757: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3758: (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3759: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
3760: ""
3761: "@
3762: sf %0,%2,%1\;sfe %0,%0,%0\;neg %0,%0
3763: ai %0,%1,%n2\;sfe %0,%0,%0\;neg %0,%0")
3764:
3765: (define_insn ""
3766: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
3767: (compare:CC
3768: (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3769: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
3770: (const_int 0)))
3771: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3772: (ltu:SI (match_dup 1) (match_dup 2)))]
3773: ""
3774: "@
3775: sf %0,%2,%1\;sfe %0,%0,%0\;neg. %0,%0
3776: ai %0,%1,%n2\;sfe %0,%0,%0\;neg. %0,%0"
3777: [(set_attr "type" "compare")])
3778:
3779: (define_insn ""
3780: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
3781: (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
3782: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3783: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))
3784: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3785: ""
3786: "@
3787: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3788: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3789: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3
3790: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
3791:
3792: (define_insn ""
3793: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x")
3794: (compare:CC
3795: (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
3796: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3797: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
3798: (const_int 0)))
3799: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3800: ""
3801: "@
3802: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3803: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3804: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3
3805: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3"
3806: [(set_attr "type" "compare")])
3807:
3808: (define_insn ""
3809: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x,x,x")
3810: (compare:CC
3811: (plus:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r,r,r")
3812: (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
3813: (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I"))
3814: (const_int 0)))
3815: (set (match_operand:SI 0 "gen_reg_operand" "=r,r,r,r")
3816: (plus:SI (ltu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3817: (clobber (match_scratch:SI 4 "=&r,r,&r,r"))]
3818: ""
3819: "@
3820: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
3821: sf %4,%2,%1\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
3822: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3
3823: ai %4,%1,%n2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
3824: [(set_attr "type" "compare")])
3825:
3826: (define_insn ""
3827: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3828: (neg:SI (ltu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3829: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))))]
3830: ""
3831: "@
3832: sf %0,%2,%1\;sfe %0,%0,%0
3833: ai %0,%1,%n2\;sfe %0,%0,%0")
3834:
3835: (define_insn ""
3836: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3837: (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3838: (match_operand:SI 2 "reg_or_short_operand" "rI")))
3839: (clobber (match_scratch:SI 3 "=r"))]
3840: ""
3841: "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae %0,%0,%3")
3842:
3843: (define_insn ""
3844: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3845: (compare:CC
3846: (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3847: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3848: (const_int 0)))
3849: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3850: (ge:SI (match_dup 1) (match_dup 2)))
3851: (clobber (match_scratch:SI 3 "=r"))]
3852: ""
3853: "doz%I2 %3,%1,%2\;sfi %0,%3,0\;ae. %0,%0,%3"
3854: [(set_attr "type" "compare")])
3855:
3856: (define_insn ""
3857: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3858: (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3859: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3860: (match_operand:SI 3 "gen_reg_operand" "r")))
3861: (clobber (match_scratch:SI 4 "=&r"))]
3862: ""
3863: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze %0,%3")
3864:
3865: (define_insn ""
3866: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3867: (compare:CC
3868: (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3869: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3870: (match_operand:SI 3 "gen_reg_operand" "r"))
3871: (const_int 0)))
3872: (clobber (match_scratch:SI 4 "=&r"))]
3873: ""
3874: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %4,%3"
3875: [(set_attr "type" "compare")])
3876:
3877: (define_insn ""
3878: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
3879: (compare:CC
3880: (plus:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3881: (match_operand:SI 2 "reg_or_short_operand" "rI"))
3882: (match_operand:SI 3 "gen_reg_operand" "r"))
3883: (const_int 0)))
3884: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3885: (plus:SI (ge:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3886: (clobber (match_scratch:SI 4 "=&r"))]
3887: ""
3888: "doz%I2 %4,%1,%2\;sfi %4,%4,0\;aze. %0,%3"
3889: [(set_attr "type" "compare")])
3890:
3891: (define_insn ""
3892: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3893: (neg:SI (ge:SI (match_operand:SI 1 "gen_reg_operand" "r")
3894: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
3895: ""
3896: "doz%I2 %0,%1,%2\;ai %0,%0,-1\;sfe %0,%0,%0")
3897:
3898: ;; This is (and (neg (ge X (const_int 0))) Y).
3899: (define_insn ""
3900: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
3901: (and:SI (neg:SI
3902: (lshiftrt:SI
3903: (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
3904: (const_int 31)))
3905: (match_operand:SI 2 "gen_reg_operand" "r")))
3906: (clobber (match_scratch:SI 3 "=&r"))]
3907: ""
3908: "srai %3,%1,31\;andc %0,%2,%3")
3909:
3910: (define_insn ""
3911: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
3912: (compare:CC
3913: (and:SI (neg:SI
3914: (lshiftrt:SI
3915: (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
3916: (const_int 31)))
3917: (match_operand:SI 2 "gen_reg_operand" "r"))
3918: (const_int 0)))
3919: (clobber (match_scratch:SI 3 "=&r"))]
3920: ""
3921: "srai %3,%1,31\;andc. %3,%2,%3"
3922: [(set_attr "type" "compare")])
3923:
3924: (define_insn ""
3925: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
3926: (compare:CC
3927: (and:SI (neg:SI
3928: (lshiftrt:SI
3929: (not:SI (match_operand:SI 1 "gen_reg_operand" "r"))
3930: (const_int 31)))
3931: (match_operand:SI 2 "gen_reg_operand" "r"))
3932: (const_int 0)))
3933: (set (match_operand:SI 0 "gen_reg_operand" "=r")
3934: (and:SI (neg:SI (lshiftrt:SI (not:SI (match_dup 1))
3935: (const_int 31)))
3936: (match_dup 2)))
3937: (clobber (match_scratch:SI 3 "=&r"))]
3938: ""
3939: "srai %3,%1,31\;andc. %0,%2,%3"
3940: [(set_attr "type" "compare")])
3941:
3942: (define_insn ""
3943: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3944: (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3945: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
3946: ""
3947: "@
3948: sf %0,%2,%1\;cal %0,0(0)\;ae %0,%0,%0
3949: ai %0,%1,%n2\;cal %0,0(0)\;ae %0,%0,%0")
3950:
3951: (define_insn ""
3952: [(set (match_operand:CC 3 "cc_reg_operand" "=x,x")
3953: (compare:CC
3954: (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3955: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
3956: (const_int 0)))
3957: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3958: (geu:SI (match_dup 1) (match_dup 2)))]
3959: ""
3960: "@
3961: sf %0,%2,%1\;cal %0,0(0)\;ae. %0,%0,%0
3962: ai %0,%1,%n2\;cal %0,0(0)\;ae. %0,%0,%0"
3963: [(set_attr "type" "compare")])
3964:
3965: (define_insn ""
3966: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3967: (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3968: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
3969: (match_operand:SI 3 "gen_reg_operand" "r,r")))
3970: (clobber (match_scratch:SI 4 "=&r,&r"))]
3971: ""
3972: "@
3973: sf %4,%2,%1\;aze %0,%3
3974: ai %4,%1,%n2\;aze %0,%3")
3975:
3976: (define_insn ""
3977: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
3978: (compare:CC
3979: (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3980: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
3981: (match_operand:SI 3 "gen_reg_operand" "r,r"))
3982: (const_int 0)))
3983: (clobber (match_scratch:SI 4 "=&r,&r"))]
3984: ""
3985: "@
3986: sf %4,%2,%1\;aze. %4,%3
3987: ai %4,%1,%n2\;aze. %4,%3"
3988: [(set_attr "type" "compare")])
3989:
3990: (define_insn ""
3991: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
3992: (compare:CC
3993: (plus:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
3994: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
3995: (match_operand:SI 3 "gen_reg_operand" "r,r"))
3996: (const_int 0)))
3997: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
3998: (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
3999: (clobber (match_scratch:SI 4 "=&r,&r"))]
4000: ""
4001: "@
4002: sf %4,%2,%1\;aze. %0,%3
4003: ai %4,%1,%n2\;aze. %4,%3"
4004: [(set_attr "type" "compare")])
4005:
4006: (define_insn ""
4007: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4008: (neg:SI (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4009: (match_operand:SI 2 "reg_or_short_operand" "r,I"))))]
4010: ""
4011: "@
4012: sf %0,%2,%1\;sfe %0,%0,%0\;nand %0,%0,%0
4013: sfi %0,%1,-1\;a%I2 %0,%0,%2\;sfe %0,%0,%0")
4014:
4015: (define_insn ""
4016: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4017: (and:SI (neg:SI
4018: (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4019: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4020: (match_operand:SI 3 "gen_reg_operand" "r,r")))
4021: (clobber (match_scratch:SI 4 "=&r,&r"))]
4022: ""
4023: "@
4024: sf %4,%2,%1\;sfe %4,%4,%4\;andc %0,%3,%4
4025: ai %4,%1,%n2\;sfe %4,%4,%4\;andc %0,%3,%4")
4026:
4027: (define_insn ""
4028: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4029: (compare:CC
4030: (and:SI (neg:SI
4031: (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4032: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4033: (match_operand:SI 3 "gen_reg_operand" "r,r"))
4034: (const_int 0)))
4035: (clobber (match_scratch:SI 4 "=&r,&r"))]
4036: ""
4037: "@
4038: sf %4,%2,%1\;sfe %4,%4,%4\;andc. %4,%3,%4
4039: ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %4,%3,%4"
4040: [(set_attr "type" "compare")])
4041:
4042: (define_insn ""
4043: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4044: (compare:CC
4045: (and:SI (neg:SI
4046: (geu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4047: (match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))
4048: (match_operand:SI 3 "gen_reg_operand" "r,r"))
4049: (const_int 0)))
4050: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4051: (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))
4052: (clobber (match_scratch:SI 4 "=&r,&r"))]
4053: ""
4054: "@
4055: sf %4,%2,%1\;sfe %4,%4,%4\;andc. %0,%3,%4
4056: ai %4,%1,%n2\;sfe %4,%4,%4\;andc. %0,%3,%4"
4057: [(set_attr "type" "compare")])
4058:
4059: (define_insn ""
4060: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4061: (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4062: (const_int 0)))]
4063: ""
4064: "sfi %0,%1,0\;ame %0,%0\;sri %0,%0,31")
4065:
4066: (define_insn ""
4067: [(set (match_operand:CC 2 "cc_reg_operand" "=x")
4068: (compare:CC
4069: (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4070: (const_int 0))
4071: (const_int 0)))
4072: (set (match_operand:SI 0 "gen_reg_operand" "=r")
4073: (gt:SI (match_dup 1) (const_int 0)))]
4074: ""
4075: "sfi %0,%1,0\;ame %0,%0\;sri. %0,%0,31"
4076: [(set_attr "type" "delayed_compare")])
4077:
4078: (define_insn ""
4079: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4080: (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4081: (match_operand:SI 2 "reg_or_short_operand" "r")))]
4082: ""
4083: "doz %0,%2,%1\;nabs %0,%0\;sri %0,%0,31")
4084:
4085: (define_insn ""
4086: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4087: (compare:CC
4088: (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4089: (match_operand:SI 2 "reg_or_short_operand" "r"))
4090: (const_int 0)))
4091: (set (match_operand:SI 0 "gen_reg_operand" "=r")
4092: (gt:SI (match_dup 1) (match_dup 2)))]
4093: ""
4094: "doz %0,%2,%1\;nabs %0,%0\;sri. %0,%0,31"
4095: [(set_attr "type" "delayed_compare")])
4096:
4097: (define_insn ""
4098: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4099: (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4100: (const_int 0))
4101: (match_operand:SI 2 "gen_reg_operand" "r")))
4102: (clobber (match_scratch:SI 3 "=&r"))]
4103: ""
4104: "a %3,%1,%1\;sfe %3,%1,%3\;aze %0,%2")
4105:
4106: (define_insn ""
4107: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4108: (compare:CC
4109: (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4110: (const_int 0))
4111: (match_operand:SI 2 "gen_reg_operand" "r"))
4112: (const_int 0)))
4113: (clobber (match_scratch:SI 3 "=&r"))]
4114: ""
4115: "a %3,%1,%1\;sfe %3,%1,%3\;aze. %0,%2"
4116: [(set_attr "type" "compare")])
4117:
4118: (define_insn ""
4119: [(set (match_operand:CC 4 "cc_reg_operand" "=x")
4120: (compare:CC
4121: (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4122: (const_int 0))
4123: (match_operand:SI 2 "gen_reg_operand" "r"))
4124: (const_int 0)))
4125: (set (match_operand:SI 0 "gen_reg_operand" "=r")
4126: (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))
4127: (clobber (match_scratch:SI 3 "=&r"))]
4128: ""
4129: "a %3,%1,%1\;sfe %3,%1,%3\;aze. %3,%2"
4130: [(set_attr "type" "compare")])
4131:
4132: (define_insn ""
4133: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4134: (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4135: (match_operand:SI 2 "reg_or_short_operand" "r"))
4136: (match_operand:SI 3 "gen_reg_operand" "r")))
4137: (clobber (match_scratch:SI 4 "=&r"))]
4138: ""
4139: "doz %4,%2,%1\;ai %4,%4,-1\;aze %0,%3")
4140:
4141: (define_insn ""
4142: [(set (match_operand:CC 0 "cc_reg_operand" "=x")
4143: (compare:CC
4144: (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4145: (match_operand:SI 2 "reg_or_short_operand" "r"))
4146: (match_operand:SI 3 "gen_reg_operand" "r"))
4147: (const_int 0)))
4148: (clobber (match_scratch:SI 4 "=&r"))]
4149: ""
4150: "doz %4,%2,%1\;ai %4,%4,-1\;aze. %4,%3"
4151: [(set_attr "type" "compare")])
4152:
4153: (define_insn ""
4154: [(set (match_operand:CC 5 "cc_reg_operand" "=x")
4155: (compare:CC
4156: (plus:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4157: (match_operand:SI 2 "reg_or_short_operand" "r"))
4158: (match_operand:SI 3 "gen_reg_operand" "r"))
4159: (const_int 0)))
4160: (set (match_operand:SI 0 "gen_reg_operand" "=r")
4161: (plus:SI (gt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4162: (clobber (match_scratch:SI 4 "=&r"))]
4163: ""
4164: "doz %4,%2,%1\;ai %4,%4,-1\;aze. %0,%3"
4165: [(set_attr "type" "compare")])
4166:
4167: (define_insn ""
4168: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4169: (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4170: (const_int 0))))]
4171: ""
4172: "sfi %0,%1,0\;ame %0,%0\;srai %0,%0,31")
4173:
4174: (define_insn ""
4175: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4176: (neg:SI (gt:SI (match_operand:SI 1 "gen_reg_operand" "r")
4177: (match_operand:SI 2 "reg_or_short_operand" "r"))))]
4178: ""
4179: "doz %0,%2,%1\;nabs %0,%0\;srai %0,%0,31")
4180:
4181: (define_insn ""
4182: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4183: (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
4184: (match_operand:SI 2 "reg_or_short_operand" "rI")))]
4185: ""
4186: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg %0,%0")
4187:
4188: (define_insn ""
4189: [(set (match_operand:CC 3 "cc_reg_operand" "=x")
4190: (compare:CC
4191: (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
4192: (match_operand:SI 2 "reg_or_short_operand" "rI"))
4193: (const_int 0)))
4194: (set (match_operand:SI 0 "gen_reg_operand" "=r")
4195: (gtu:SI (match_dup 1) (match_dup 2)))]
4196: ""
4197: "sf%I2 %0,%1,%2\;sfe %0,%0,%0\;neg. %0,%0"
4198: [(set_attr "type" "compare")])
4199:
4200: (define_insn ""
4201: [(set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4202: (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4203: (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4204: (match_operand:SI 3 "reg_or_short_operand" "r,I")))
4205: (clobber (match_scratch:SI 4 "=&r,&r"))]
4206: ""
4207: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3 %0,%4,%3")
4208:
4209: (define_insn ""
4210: [(set (match_operand:CC 0 "cc_reg_operand" "=x,x")
4211: (compare:CC
4212: (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4213: (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4214: (match_operand:SI 3 "reg_or_short_operand" "r,I"))
4215: (const_int 0)))
4216: (clobber (match_scratch:SI 4 "=&r,&r"))]
4217: ""
4218: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %4,%4,%3"
4219: [(set_attr "type" "compare")])
4220:
4221: (define_insn ""
4222: [(set (match_operand:CC 5 "cc_reg_operand" "=x,x")
4223: (compare:CC
4224: (plus:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r,r")
4225: (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))
4226: (match_operand:SI 3 "reg_or_short_operand" "r,I"))
4227: (const_int 0)))
4228: (set (match_operand:SI 0 "gen_reg_operand" "=r,r")
4229: (plus:SI (gtu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))
4230: (clobber (match_scratch:SI 4 "=&r,&r"))]
4231: ""
4232: "sf%I2 %4,%1,%2\;sfe %4,%4,%4\;sf%I3. %0,%4,%3"
4233: [(set_attr "type" "compare")])
4234:
4235: (define_insn ""
4236: [(set (match_operand:SI 0 "gen_reg_operand" "=r")
4237: (neg:SI (gtu:SI (match_operand:SI 1 "gen_reg_operand" "r")
4238: (match_operand:SI 2 "reg_or_short_operand" "rI"))))]
4239: ""
4240: "sf%I2 %0,%1,%2\;sfe %0,%0,%0")
4241:
4242: ;; Define both directions of branch and return. If we need a reload
4243: ;; register, we'd rather use CR0 since it is much easier to copy a
4244: ;; register CC value to there.
4245:
4246: (define_insn ""
4247: [(set (pc)
4248: (if_then_else (match_operator 1 "branch_comparison_operator"
4249: [(match_operand 2
4250: "cc_reg_operand" "x,?y")
4251: (const_int 0)])
4252: (label_ref (match_operand 0 "" ""))
4253: (pc)))]
4254: ""
4255: "%C1bc %t1,%j1,%0")
4256:
4257: (define_insn ""
4258: [(set (pc)
4259: (if_then_else (match_operator 0 "branch_comparison_operator"
4260: [(match_operand 1
4261: "cc_reg_operand" "x,?y")
4262: (const_int 0)])
4263: (return)
4264: (pc)))]
4265: "direct_return ()"
4266: "%C0bcr %t0,%j0")
4267:
4268: (define_insn ""
4269: [(set (pc)
4270: (if_then_else (match_operator 1 "branch_comparison_operator"
4271: [(match_operand 2
4272: "cc_reg_operand" "x,?y")
4273: (const_int 0)])
4274: (pc)
4275: (label_ref (match_operand 0 "" ""))))]
4276: ""
4277: "%C1bc %T1,%j1,%0")
4278:
4279: (define_insn ""
4280: [(set (pc)
4281: (if_then_else (match_operator 0 "branch_comparison_operator"
4282: [(match_operand 1
4283: "cc_reg_operand" "x,?y")
4284: (const_int 0)])
4285: (pc)
4286: (return)))]
4287: "direct_return ()"
4288: "%C0bcr %T0,%j0")
4289:
4290: ;; Unconditional branch and return.
4291:
4292: (define_insn "jump"
4293: [(set (pc)
4294: (label_ref (match_operand 0 "" "")))]
4295: ""
4296: "b %l0")
4297:
4298: (define_insn "return"
4299: [(return)]
4300: "direct_return ()"
4301: "br")
4302:
4303: (define_insn "indirect_jump"
4304: [(set (pc) (match_operand:SI 0 "register_operand" "c,l"))]
4305: ""
4306: "@
4307: bctr
4308: br")
4309:
4310: ;; Table jump for switch statements:
4311: (define_expand "tablejump"
4312: [(set (match_dup 3)
4313: (plus:SI (match_operand:SI 0 "" "")
4314: (match_dup 2)))
4315: (parallel [(set (pc) (match_dup 3))
4316: (use (label_ref (match_operand 1 "" "")))])]
4317: ""
4318: "
4319: { operands[0] = force_reg (SImode, operands[0]);
4320: operands[2] = force_reg (SImode, gen_rtx (LABEL_REF, VOIDmode, operands[1]));
4321: operands[3] = gen_reg_rtx (SImode);
4322: }")
4323:
4324: (define_insn ""
4325: [(set (pc)
4326: (match_operand:SI 0 "register_operand" "c,r"))
4327: (use (label_ref (match_operand 1 "" "")))]
4328: ""
4329: "@
4330: bctr
4331: br")
4332:
4333: (define_insn "nop"
4334: [(const_int 0)]
4335: ""
4336: "cror 0,0,0")
4337:
4338: ;; Define the subtract-one-and-jump insns.
4339: ;; We need to be able to do this for any operand, including MEM, or we
4340: ;; will cause reload to blow up since we don't allow output reloads on
4341: ;; JUMP_INSNs.
4342: (define_insn ""
4343: [(set (pc)
4344: (if_then_else (ne (match_operand:SI 1 "register_operand" "0,*r,*r")
4345: (const_int 1))
4346: (label_ref (match_operand 2 "" ""))
4347: (pc)))
4348: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4349: (plus:SI (match_dup 1) (const_int -1)))
4350: (clobber (match_scratch:CC 3 "=X,&x,&x"))
4351: (clobber (match_scratch:SI 4 "=X,X,r"))]
4352: ""
4353: "@
4354: bdn %l2
4355: #
4356: #")
4357:
4358: ;; Similar, but we can use GE since we have a REG_NOTES.
4359: (define_insn ""
4360: [(set (pc)
4361: (if_then_else (ge (match_operand:SI 1 "register_operand" "0,*r,*r")
4362: (const_int 0))
4363: (label_ref (match_operand 2 "" ""))
4364: (pc)))
4365: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4366: (plus:SI (match_dup 1) (const_int -1)))
4367: (clobber (match_scratch:CC 3 "=X,&x,&X"))
4368: (clobber (match_scratch:SI 4 "=X,X,r"))]
4369: "find_reg_note (insn, REG_NONNEG, 0)"
4370: "@
4371: bdn %l2
4372: #
4373: #")
4374:
4375: (define_insn ""
4376: [(set (pc)
4377: (if_then_else (eq (match_operand:SI 1 "register_operand" "0,*r,*r")
4378: (const_int 1))
4379: (label_ref (match_operand 2 "" ""))
4380: (pc)))
4381: (set (match_operand:SI 0 "register_operand" "=c,*r,m*q*c*l")
4382: (plus:SI (match_dup 1) (const_int -1)))
4383: (clobber (match_scratch:CC 3 "=X,&x,&x"))
4384: (clobber (match_scratch:SI 4 "=X,X,r"))]
4385: ""
4386: "@
4387: bdz %l2
4388: #
4389: #")
4390:
4391: (define_split
4392: [(set (pc)
4393: (if_then_else (match_operator 2 "comparison_operator"
4394: [(match_operand:SI 1 "gen_reg_operand" "")
4395: (const_int 1)])
4396: (match_operand 5 "" "")
4397: (match_operand 6 "" "")))
4398: (set (match_operand:SI 0 "gen_reg_operand" "")
4399: (plus:SI (match_dup 1) (const_int -1)))
4400: (clobber (match_scratch:CC 3 ""))
4401: (clobber (match_scratch:SI 4 ""))]
4402: "reload_completed"
4403: [(parallel [(set (match_dup 3)
4404: (compare:CC (plus:SI (match_dup 1) (const_int -1))
4405: (const_int 0)))
4406: (set (match_dup 0) (plus:SI (match_dup 1) (const_int -1)))])
4407: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4408: "
4409: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
4410: const0_rtx); }")
4411:
4412: (define_split
4413: [(set (pc)
4414: (if_then_else (match_operator 2 "comparison_operator"
4415: [(match_operand:SI 1 "gen_reg_operand" "")
4416: (const_int 1)])
4417: (match_operand 5 "" "")
4418: (match_operand 6 "" "")))
4419: (set (match_operand:SI 0 "general_operand" "")
4420: (plus:SI (match_dup 1) (const_int -1)))
4421: (clobber (match_scratch:CC 3 ""))
4422: (clobber (match_scratch:SI 4 ""))]
4423: "reload_completed && ! gen_reg_operand (operands[0], SImode)"
4424: [(parallel [(set (match_dup 3)
4425: (compare:CC (plus:SI (match_dup 1) (const_int -1))
4426: (const_int 0)))
4427: (set (match_dup 4) (plus:SI (match_dup 1) (const_int -1)))])
4428: (set (match_dup 0) (match_dup 4))
4429: (set (pc) (if_then_else (match_dup 7) (match_dup 5) (match_dup 6)))]
4430: "
4431: { operands[7] = gen_rtx (GET_CODE (operands[2]), VOIDmode, operands[3],
4432: const0_rtx); }")
4433:
4434: ;;- Local variables:
4435: ;;- mode:emacs-lisp
4436: ;;- comment-start: ";;- "
4437: ;;- eval: (set-syntax-table (copy-sequence (syntax-table)))
4438: ;;- eval: (modify-syntax-entry ?[ "(]")
4439: ;;- eval: (modify-syntax-entry ?] ")[")
4440: ;;- eval: (modify-syntax-entry ?{ "(}")
4441: ;;- eval: (modify-syntax-entry ?} "){")
4442: ;;- End:
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